diff --git a/Documentation/ABI/obsolete/sysfs-bus-iio b/Documentation/ABI/obsolete/sysfs-bus-iio new file mode 100644 index 000000000000..c9531bb64816 --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-bus-iio @@ -0,0 +1,182 @@ +What: /sys/bus/iio/devices/iio:deviceX/buffer/length +KernelVersion: 2.6.35 +Contact: linux-iio@vger.kernel.org +Description: + Number of scans contained by the buffer. + + Since Kernel 5.11, multiple buffers are supported. + so, it is better to use, instead: + /sys/bus/iio/devices/iio:deviceX/bufferY/length + +What: /sys/bus/iio/devices/iio:deviceX/buffer/enable +KernelVersion: 2.6.35 +Contact: linux-iio@vger.kernel.org +Description: + Actually start the buffer capture up. Will start trigger + if first device and appropriate. + + Since Kernel 5.11, multiple buffers are supported. + so, it is better to use, instead: + /sys/bus/iio/devices/iio:deviceX/bufferY/enable + +What: /sys/bus/iio/devices/iio:deviceX/scan_elements +KernelVersion: 2.6.37 +Contact: linux-iio@vger.kernel.org +Description: + Directory containing interfaces for elements that will be + captured for a single triggered sample set in the buffer. + + Since kernel 5.11 the scan_elements attributes are merged into + the bufferY directory, to be configurable per buffer. + +What: /sys/.../iio:deviceX/scan_elements/in_accel_x_en +What: /sys/.../iio:deviceX/scan_elements/in_accel_y_en +What: /sys/.../iio:deviceX/scan_elements/in_accel_z_en +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_x_en +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_y_en +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_z_en +What: /sys/.../iio:deviceX/scan_elements/in_magn_x_en +What: /sys/.../iio:deviceX/scan_elements/in_magn_y_en +What: /sys/.../iio:deviceX/scan_elements/in_magn_z_en +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_en +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_en +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_tilt_comp_en +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_tilt_comp_en +What: /sys/.../iio:deviceX/scan_elements/in_timestamp_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY-voltageZ_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_en +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_en +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_en +What: /sys/.../iio:deviceX/scan_elements/in_incli_x_en +What: /sys/.../iio:deviceX/scan_elements/in_incli_y_en +What: /sys/.../iio:deviceX/scan_elements/in_pressureY_en +What: /sys/.../iio:deviceX/scan_elements/in_pressure_en +What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_en +What: /sys/.../iio:deviceX/scan_elements/in_proximity_en +KernelVersion: 2.6.37 +Contact: linux-iio@vger.kernel.org +Description: + Scan element control for triggered data capture. + + Since kernel 5.11 the scan_elements attributes are merged into + the bufferY directory, to be configurable per buffer. + +What: /sys/.../iio:deviceX/scan_elements/in_accel_type +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_type +What: /sys/.../iio:deviceX/scan_elements/in_magn_type +What: /sys/.../iio:deviceX/scan_elements/in_incli_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_type +What: /sys/.../iio:deviceX/scan_elements/in_voltage_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_type +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_type +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_type +What: /sys/.../iio:deviceX/scan_elements/in_timestamp_type +What: /sys/.../iio:deviceX/scan_elements/in_pressureY_type +What: /sys/.../iio:deviceX/scan_elements/in_pressure_type +What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_type +What: /sys/.../iio:deviceX/scan_elements/in_proximity_type +KernelVersion: 2.6.37 +Contact: linux-iio@vger.kernel.org +Description: + Description of the scan element data storage within the buffer + and hence the form in which it is read from user-space. + Form is [be|le]:[s|u]bits/storagebits[>>shift]. + be or le specifies big or little endian. s or u specifies if + signed (2's complement) or unsigned. bits is the number of bits + of data and storagebits is the space (after padding) that it + occupies in the buffer. shift if specified, is the shift that + needs to be applied prior to masking out unused bits. Some + devices put their data in the middle of the transferred elements + with additional information on both sides. Note that some + devices will have additional information in the unused bits + so to get a clean value, the bits value must be used to mask + the buffer output value appropriately. The storagebits value + also specifies the data alignment. So s48/64>>2 will be a + signed 48 bit integer stored in a 64 bit location aligned to + a 64 bit boundary. To obtain the clean value, shift right 2 + and apply a mask to zero the top 16 bits of the result. + For other storage combinations this attribute will be extended + appropriately. + + Since kernel 5.11 the scan_elements attributes are merged into + the bufferY directory, to be configurable per buffer. + +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_index +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_index +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_index +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_index +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_index +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_index +What: /sys/.../iio:deviceX/scan_elements/in_accel_x_index +What: /sys/.../iio:deviceX/scan_elements/in_accel_y_index +What: /sys/.../iio:deviceX/scan_elements/in_accel_z_index +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_x_index +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_y_index +What: /sys/.../iio:deviceX/scan_elements/in_anglvel_z_index +What: /sys/.../iio:deviceX/scan_elements/in_magn_x_index +What: /sys/.../iio:deviceX/scan_elements/in_magn_y_index +What: /sys/.../iio:deviceX/scan_elements/in_magn_z_index +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_index +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_index +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_tilt_comp_index +What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_tilt_comp_index +What: /sys/.../iio:deviceX/scan_elements/in_incli_x_index +What: /sys/.../iio:deviceX/scan_elements/in_incli_y_index +What: /sys/.../iio:deviceX/scan_elements/in_timestamp_index +What: /sys/.../iio:deviceX/scan_elements/in_pressureY_index +What: /sys/.../iio:deviceX/scan_elements/in_pressure_index +What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_index +What: /sys/.../iio:deviceX/scan_elements/in_proximity_index +KernelVersion: 2.6.37 +Description: + A single positive integer specifying the position of this + scan element in the buffer. Note these are not dependent on + what is enabled and may not be contiguous. Thus for user-space + to establish the full layout these must be used in conjunction + with all _en attributes to establish which channels are present, + and the relevant _type attributes to establish the data storage + format. + + Since kernel 5.11 the scan_elements attributes are merged into + the bufferY directory, to be configurable per buffer. + +What: /sys/bus/iio/devices/iio:deviceX/buffer/watermark +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + A single positive integer specifying the maximum number of scan + elements to wait for. + + Poll will block until the watermark is reached. + + Blocking read will wait until the minimum between the requested + read amount or the low water mark is available. + + Non-blocking read will retrieve the available samples from the + buffer even if there are less samples then watermark level. This + allows the application to block on poll with a timeout and read + the available samples after the timeout expires and thus have a + maximum delay guarantee. + + Since Kernel 5.11, multiple buffers are supported. + so, it is better to use, instead: + /sys/bus/iio/devices/iio:deviceX/bufferY/watermark + +What: /sys/bus/iio/devices/iio:deviceX/buffer/data_available +KernelVersion: 4.16 +Contact: linux-iio@vger.kernel.org +Description: + A read-only value indicating the bytes of data available in the + buffer. In the case of an output buffer, this indicates the + amount of empty space available to write data to. In the case of + an input buffer, this indicates the amount of data available for + reading. + + Since Kernel 5.11, multiple buffers are supported. + so, it is better to use, instead: + /sys/bus/iio/devices/iio:deviceX/bufferY/data_available diff --git a/Documentation/ABI/stable/sysfs-class-infiniband b/Documentation/ABI/stable/sysfs-class-infiniband index 348c4ac803ad..9b1bdfa43354 100644 --- a/Documentation/ABI/stable/sysfs-class-infiniband +++ b/Documentation/ABI/stable/sysfs-class-infiniband @@ -731,26 +731,6 @@ Description: is the irq number of "sdma3", and M is irq number of "sdma4" in the /proc/interrupts file. - -sysfs interface for Intel(R) X722 iWARP i40iw driver ----------------------------------------------------- - -What: /sys/class/infiniband/i40iwX/hw_rev -What: /sys/class/infiniband/i40iwX/hca_type -What: /sys/class/infiniband/i40iwX/board_id -Date: Jan, 2016 -KernelVersion: v4.10 -Contact: linux-rdma@vger.kernel.org -Description: - =============== ==== ======================== - hw_rev: (RO) Hardware revision number - - hca_type: (RO) Show HCA type (I40IW) - - board_id: (RO) I40IW board ID - =============== ==== ======================== - - sysfs interface for QLogic qedr NIC Driver ------------------------------------------ diff --git a/Documentation/ABI/stable/sysfs-driver-w1_ds2438 b/Documentation/ABI/stable/sysfs-driver-w1_ds2438 new file mode 100644 index 000000000000..d2e7681cc287 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-driver-w1_ds2438 @@ -0,0 +1,13 @@ +What: /sys/bus/w1/devices/.../page1 +Date: April 2021 +Contact: Luiz Sampaio +Description: read the contents of the page1 of the DS2438 + see Documentation/w1/slaves/w1_ds2438.rst for detailed information +Users: any user space application which wants to communicate with DS2438 + +What: /sys/bus/w1/devices/.../offset +Date: April 2021 +Contact: Luiz Sampaio +Description: write the contents to the offset register of the DS2438 + see Documentation/w1/slaves/w1_ds2438.rst for detailed information +Users: any user space application which wants to communicate with DS2438 diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uac2 b/Documentation/ABI/testing/configfs-usb-gadget-uac2 index d4356c8b8cd6..26fb8e9b4e61 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uac2 +++ b/Documentation/ABI/testing/configfs-usb-gadget-uac2 @@ -8,6 +8,8 @@ Description: c_chmask capture channel mask c_srate capture sampling rate c_ssize capture sample size (bytes) + c_sync capture synchronization type (async/adaptive) + fb_max maximum extra bandwidth in async mode p_chmask playback channel mask p_srate playback sampling rate p_ssize playback sample size (bytes) diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index e89c6351503c..a5c28f606865 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -207,6 +207,14 @@ Contact: ogabbay@kernel.org Description: Sets the PCI power state. Valid values are "1" for D0 and "2" for D3Hot +What: /sys/kernel/debug/habanalabs/hl/skip_reset_on_timeout +Date: Jun 2021 +KernelVersion: 5.13 +Contact: ynudelman@habana.ai +Description: Sets the skip reset on timeout option for the device. Value of + "0" means device will be reset in case some CS has timed out, + otherwise it will not be reset. + What: /sys/kernel/debug/habanalabs/hl/stop_on_err Date: Mar 2020 KernelVersion: 5.6 diff --git a/Documentation/ABI/testing/sysfs-bus-counter b/Documentation/ABI/testing/sysfs-bus-counter index 566bd99fe0a5..20fe5afd4f9e 100644 --- a/Documentation/ABI/testing/sysfs-bus-counter +++ b/Documentation/ABI/testing/sysfs-bus-counter @@ -57,6 +57,7 @@ Description: What: /sys/bus/counter/devices/counterX/countY/count_mode_available What: /sys/bus/counter/devices/counterX/countY/error_noise_available What: /sys/bus/counter/devices/counterX/countY/function_available +What: /sys/bus/counter/devices/counterX/countY/prescaler_available What: /sys/bus/counter/devices/counterX/countY/signalZ_action_available KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -154,6 +155,15 @@ Description: Count Y. If possible, this should match the name of the respective channel as it appears in the device datasheet. +What: /sys/bus/counter/devices/counterX/countY/prescaler +KernelVersion: 5.2 +Contact: linux-iio@vger.kernel.org +Description: + Configure the prescaler value associated with Count Y. + On the FlexTimer, the counter clock source passes through a + prescaler (i.e. a counter). This acts like a clock + divider. + What: /sys/bus/counter/devices/counterX/countY/preset KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -193,6 +203,15 @@ Description: both edges: Any state transition. +What: /sys/bus/counter/devices/counterX/countY/spike_filter_ns +KernelVersion: 5.14 +Contact: linux-iio@vger.kernel.org +Description: + If the counter device supports programmable spike filter this + attribute indicates the value in nanoseconds where noise pulses + shorter or equal to configured value are ignored. Value 0 means + filter is disabled. + What: /sys/bus/counter/devices/counterX/name KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org @@ -215,11 +234,45 @@ Description: Read-only attribute that indicates the total number of Signals belonging to the Counter. -What: /sys/bus/counter/devices/counterX/signalY/signal +What: /sys/bus/counter/devices/counterX/signalY/cable_fault +KernelVersion: 5.7 +Contact: linux-iio@vger.kernel.org +Description: + Read-only attribute that indicates whether a differential + encoder cable fault (not connected or loose wires) is detected + for the respective channel of Signal Y. Valid attribute values + are boolean. Detection must first be enabled via the + corresponding cable_fault_enable attribute. + +What: /sys/bus/counter/devices/counterX/signalY/cable_fault_enable +KernelVersion: 5.7 +Contact: linux-iio@vger.kernel.org +Description: + Whether detection of differential encoder cable faults for the + respective channel of Signal Y is enabled. Valid attribute + values are boolean. + +What: /sys/bus/counter/devices/counterX/signalY/filter_clock_prescaler +KernelVersion: 5.7 +Contact: linux-iio@vger.kernel.org +Description: + Filter clock factor for input Signal Y. This prescaler value + affects the inputs of both quadrature pair signals. + +What: /sys/bus/counter/devices/counterX/signalY/index_polarity KernelVersion: 5.2 Contact: linux-iio@vger.kernel.org Description: - Signal data of Signal Y represented as a string. + Active level of index input Signal Y; irrelevant in + non-synchronous load mode. + +What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available +What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available +KernelVersion: 5.2 +Contact: linux-iio@vger.kernel.org +Description: + Discrete set of available values for the respective Signal Y + configuration are listed in this file. What: /sys/bus/counter/devices/counterX/signalY/name KernelVersion: 5.2 @@ -228,3 +281,31 @@ Description: Read-only attribute that indicates the device-specific name of Signal Y. If possible, this should match the name of the respective signal as it appears in the device datasheet. + +What: /sys/bus/counter/devices/counterX/signalY/signal +KernelVersion: 5.2 +Contact: linux-iio@vger.kernel.org +Description: + Signal data of Signal Y represented as a string. + +What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode +KernelVersion: 5.2 +Contact: linux-iio@vger.kernel.org +Description: + Configure the counter associated with Signal Y for + non-synchronous or synchronous load mode. Synchronous load mode + cannot be selected in non-quadrature (Pulse-Direction) clock + mode. + + non-synchronous: + A logic low level is the active level at this index + input. The index function (as enabled via preset_enable) + is performed directly on the active level of the index + input. + + synchronous: + Intended for interfacing with encoder Index output in + quadrature clock mode. The active level is configured + via index_polarity. The index function (as enabled via + preset_enable) is performed synchronously with the + quadrature clock on the active level of the index input. diff --git a/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 b/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 deleted file mode 100644 index eac32180c40d..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 +++ /dev/null @@ -1,61 +0,0 @@ -What: /sys/bus/counter/devices/counterX/signalY/cable_fault -KernelVersion: 5.7 -Contact: linux-iio@vger.kernel.org -Description: - Read-only attribute that indicates whether a differential - encoder cable fault (not connected or loose wires) is detected - for the respective channel of Signal Y. Valid attribute values - are boolean. Detection must first be enabled via the - corresponding cable_fault_enable attribute. - -What: /sys/bus/counter/devices/counterX/signalY/cable_fault_enable -KernelVersion: 5.7 -Contact: linux-iio@vger.kernel.org -Description: - Whether detection of differential encoder cable faults for the - respective channel of Signal Y is enabled. Valid attribute - values are boolean. - -What: /sys/bus/counter/devices/counterX/signalY/filter_clock_prescaler -KernelVersion: 5.7 -Contact: linux-iio@vger.kernel.org -Description: - Filter clock factor for input Signal Y. This prescaler value - affects the inputs of both quadrature pair signals. - -What: /sys/bus/counter/devices/counterX/signalY/index_polarity -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Active level of index input Signal Y; irrelevant in - non-synchronous load mode. - -What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available -What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Discrete set of available values for the respective Signal Y - configuration are listed in this file. - -What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Configure the counter associated with Signal Y for - non-synchronous or synchronous load mode. Synchronous load mode - cannot be selected in non-quadrature (Pulse-Direction) clock - mode. - - non-synchronous: - A logic low level is the active level at this index - input. The index function (as enabled via preset_enable) - is performed directly on the active level of the index - input. - - synchronous: - Intended for interfacing with encoder Index output in - quadrature clock mode. The active level is configured - via index_polarity. The index function (as enabled via - preset_enable) is performed synchronously with the - quadrature clock on the active level of the index input. diff --git a/Documentation/ABI/testing/sysfs-bus-counter-ftm-quaddec b/Documentation/ABI/testing/sysfs-bus-counter-ftm-quaddec deleted file mode 100644 index 7d2e7b363467..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-counter-ftm-quaddec +++ /dev/null @@ -1,16 +0,0 @@ -What: /sys/bus/counter/devices/counterX/countY/prescaler_available -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Discrete set of available values for the respective Count Y - configuration are listed in this file. Values are delimited by - newline characters. - -What: /sys/bus/counter/devices/counterX/countY/prescaler -KernelVersion: 5.2 -Contact: linux-iio@vger.kernel.org -Description: - Configure the prescaler value associated with Count Y. - On the FlexTimer, the counter clock source passes through a - prescaler (i.e. a counter). This acts like a clock - divider. diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 2fe7490ad6a8..0b6a2e6e8fbb 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -24,3 +24,106 @@ Description: (RO) "Persistent Only Capacity" as bytes. Represents the identically named field in the Identify Memory Device Output Payload in the CXL-2.0 specification. + +What: /sys/bus/cxl/devices/*/devtype +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + CXL device objects export the devtype attribute which mirrors + the same value communicated in the DEVTYPE environment variable + for uevents for devices on the "cxl" bus. + +What: /sys/bus/cxl/devices/portX/uport +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + CXL port objects are enumerated from either a platform firmware + device (ACPI0017 and ACPI0016) or PCIe switch upstream port with + CXL component registers. The 'uport' symlink connects the CXL + portX object to the device that published the CXL port + capability. + +What: /sys/bus/cxl/devices/portX/dportY +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + CXL port objects are enumerated from either a platform firmware + device (ACPI0017 and ACPI0016) or PCIe switch upstream port with + CXL component registers. The 'dportY' symlink identifies one or + more downstream ports that the upstream port may target in its + decode of CXL memory resources. The 'Y' integer reflects the + hardware port unique-id used in the hardware decoder target + list. + +What: /sys/bus/cxl/devices/decoderX.Y +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + CXL decoder objects are enumerated from either a platform + firmware description, or a CXL HDM decoder register set in a + PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder + Capability Structure). The 'X' in decoderX.Y represents the + cxl_port container of this decoder, and 'Y' represents the + instance id of a given decoder resource. + +What: /sys/bus/cxl/devices/decoderX.Y/{start,size} +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + The 'start' and 'size' attributes together convey the physical + address base and number of bytes mapped in the decoder's decode + window. For decoders of devtype "cxl_decoder_root" the address + range is fixed. For decoders of devtype "cxl_decoder_switch" the + address is bounded by the decode range of the cxl_port ancestor + of the decoder's cxl_port, and dynamically updates based on the + active memory regions in that address space. + +What: /sys/bus/cxl/devices/decoderX.Y/locked +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + CXL HDM decoders have the capability to lock the configuration + until the next device reset. For decoders of devtype + "cxl_decoder_root" there is no standard facility to unlock them. + For decoders of devtype "cxl_decoder_switch" a secondary bus + reset, of the PCIe bridge that provides the bus for this + decoders uport, unlocks / resets the decoder. + +What: /sys/bus/cxl/devices/decoderX.Y/target_list +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + Display a comma separated list of the current decoder target + configuration. The list is ordered by the current configured + interleave order of the decoder's dport instances. Each entry in + the list is a dport id. + +What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + When a CXL decoder is of devtype "cxl_decoder_root", it + represents a fixed memory window identified by platform + firmware. A fixed window may only support a subset of memory + types. The 'cap_*' attributes indicate whether persistent + memory, volatile memory, accelerator memory, and / or expander + memory may be mapped behind this decoder's memory window. + +What: /sys/bus/cxl/devices/decoderX.Y/target_type +Date: June, 2021 +KernelVersion: v5.14 +Contact: linux-cxl@vger.kernel.org +Description: + When a CXL decoder is of devtype "cxl_decoder_switch", it can + optionally decode either accelerator memory (type-2) or expander + memory (type-3). The 'target_type' attribute indicates the + current setting which may dynamically change based on what + memory regions are activated in this decode hierarchy. diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 6f98b6a9b785..6ad47a67521c 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -455,6 +455,19 @@ Contact: linux-iio@vger.kernel.org Description: Hardware applied calibration offset (assumed to fix production inaccuracies). + icm42600: For this device values are real physical offsets + expressed in SI units (m/s^2 for accelerometers and rad/s + for gyroscope)/ + +What: /sys/bus/iio/devices/iio:deviceX/in_accel_calibbias_available +What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_calibbias_available +KernelVersion: 5.8 +Contact: linux-iio@vger.kernel.org +Description: + Available values of calibbias. Maybe expressed as either of: + + - a small discrete set of values like "0 2 4 6 8" + - a range specified as "[min step max]" What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_calibscale @@ -652,6 +665,25 @@ Description: Output frequency for channel Y in Hz. The number must always be specified and unique if the output corresponds to a single channel. + Some drivers have additional constraints: + ADF4371 has an integrated VCO with fundamendal output + frequency ranging from 4000000000 Hz 8000000000 Hz. + + out_altvoltage0_frequency: + A divide by 1, 2, 4, 8, 16, 32 or circuit generates + frequencies from 62500000 Hz to 8000000000 Hz. + out_altvoltage1_frequency: + This channel duplicates the channel 0 frequency + out_altvoltage2_frequency: + A frequency doubler generates frequencies from + 8000000000 Hz to 16000000000 Hz. + out_altvoltage3_frequency: + A frequency quadrupler generates frequencies from + 16000000000 Hz to 32000000000 Hz. + + Note: writes to one of the channels will affect the frequency of + all the other channels, since it involves changing the VCO + fundamental output frequency. What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_phase KernelVersion: 3.4.0 @@ -663,6 +695,17 @@ Description: specified and unique if the output corresponds to a single channel. +What: /sys/bus/iio/devices/iio:deviceX/out_currentY_raw +Date: May 2012 +KernelVersion: 3.5 +Contact: Johan Hovold +Description: + Set/get output current for channel Y. Units after application + of scale and offset are milliamps. + For some devices current channels are used to specify + current supplied to elements used in taking a measurement + of a different type. E.g. LED currents. + What: /sys/bus/iio/devices/iio:deviceX/events KernelVersion: 2.6.35 Contact: linux-iio@vger.kernel.org @@ -1195,16 +1238,12 @@ Description: The name of the trigger source being used, as per string given in /sys/class/iio/triggerY/name. -What: /sys/bus/iio/devices/iio:deviceX/buffer/length -KernelVersion: 2.6.35 What: /sys/bus/iio/devices/iio:deviceX/bufferY/length KernelVersion: 5.11 Contact: linux-iio@vger.kernel.org Description: Number of scans contained by the buffer. -What: /sys/bus/iio/devices/iio:deviceX/buffer/enable -KernelVersion: 2.6.35 What: /sys/bus/iio/devices/iio:deviceX/bufferY/enable KernelVersion: 5.11 Contact: linux-iio@vger.kernel.org @@ -1212,8 +1251,6 @@ Description: Actually start the buffer capture up. Will start trigger if first device and appropriate. -What: /sys/bus/iio/devices/iio:deviceX/scan_elements -KernelVersion: 2.6.37 What: /sys/bus/iio/devices/iio:deviceX/bufferY KernelVersion: 5.11 Contact: linux-iio@vger.kernel.org @@ -1224,34 +1261,6 @@ Description: Since kernel 5.11 the scan_elements attributes are merged into the bufferY directory, to be configurable per buffer. -What: /sys/.../iio:deviceX/scan_elements/in_accel_x_en -What: /sys/.../iio:deviceX/scan_elements/in_accel_y_en -What: /sys/.../iio:deviceX/scan_elements/in_accel_z_en -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_x_en -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_y_en -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_z_en -What: /sys/.../iio:deviceX/scan_elements/in_magn_x_en -What: /sys/.../iio:deviceX/scan_elements/in_magn_y_en -What: /sys/.../iio:deviceX/scan_elements/in_magn_z_en -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_en -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_en -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_tilt_comp_en -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_tilt_comp_en -What: /sys/.../iio:deviceX/scan_elements/in_timestamp_en -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_en -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_en -What: /sys/.../iio:deviceX/scan_elements/in_voltageY-voltageZ_en -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_en -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_en -What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_en -What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_en -What: /sys/.../iio:deviceX/scan_elements/in_incli_x_en -What: /sys/.../iio:deviceX/scan_elements/in_incli_y_en -What: /sys/.../iio:deviceX/scan_elements/in_pressureY_en -What: /sys/.../iio:deviceX/scan_elements/in_pressure_en -What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_en -What: /sys/.../iio:deviceX/scan_elements/in_proximity_en -KernelVersion: 2.6.37 What: /sys/.../iio:deviceX/bufferY/in_accel_x_en What: /sys/.../iio:deviceX/bufferY/in_accel_y_en What: /sys/.../iio:deviceX/bufferY/in_accel_z_en @@ -1284,23 +1293,6 @@ Contact: linux-iio@vger.kernel.org Description: Scan element control for triggered data capture. -What: /sys/.../iio:deviceX/scan_elements/in_accel_type -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_type -What: /sys/.../iio:deviceX/scan_elements/in_magn_type -What: /sys/.../iio:deviceX/scan_elements/in_incli_type -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_type -What: /sys/.../iio:deviceX/scan_elements/in_voltage_type -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_type -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_type -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_type -What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_type -What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_type -What: /sys/.../iio:deviceX/scan_elements/in_timestamp_type -What: /sys/.../iio:deviceX/scan_elements/in_pressureY_type -What: /sys/.../iio:deviceX/scan_elements/in_pressure_type -What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_type -What: /sys/.../iio:deviceX/scan_elements/in_proximity_type -KernelVersion: 2.6.37 What: /sys/.../iio:deviceX/bufferY/in_accel_type What: /sys/.../iio:deviceX/bufferY/in_anglvel_type What: /sys/.../iio:deviceX/bufferY/in_magn_type @@ -1347,33 +1339,6 @@ Description: If the type parameter can take one of a small set of values, this attribute lists them. -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_index -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_index -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_index -What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_index -What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_index -What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_index -What: /sys/.../iio:deviceX/scan_elements/in_accel_x_index -What: /sys/.../iio:deviceX/scan_elements/in_accel_y_index -What: /sys/.../iio:deviceX/scan_elements/in_accel_z_index -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_x_index -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_y_index -What: /sys/.../iio:deviceX/scan_elements/in_anglvel_z_index -What: /sys/.../iio:deviceX/scan_elements/in_magn_x_index -What: /sys/.../iio:deviceX/scan_elements/in_magn_y_index -What: /sys/.../iio:deviceX/scan_elements/in_magn_z_index -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_index -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_index -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_magnetic_tilt_comp_index -What: /sys/.../iio:deviceX/scan_elements/in_rot_from_north_true_tilt_comp_index -What: /sys/.../iio:deviceX/scan_elements/in_incli_x_index -What: /sys/.../iio:deviceX/scan_elements/in_incli_y_index -What: /sys/.../iio:deviceX/scan_elements/in_timestamp_index -What: /sys/.../iio:deviceX/scan_elements/in_pressureY_index -What: /sys/.../iio:deviceX/scan_elements/in_pressure_index -What: /sys/.../iio:deviceX/scan_elements/in_rot_quaternion_index -What: /sys/.../iio:deviceX/scan_elements/in_proximity_index -KernelVersion: 2.6.37 What: /sys/.../iio:deviceX/bufferY/in_voltageY_index What: /sys/.../iio:deviceX/bufferY/in_voltageY_supply_index What: /sys/.../iio:deviceX/bufferY/in_voltageY_i_index @@ -1613,8 +1578,6 @@ Description: Specifies number of seconds in which we compute the steps that occur in order to decide if the consumer is making steps. -What: /sys/bus/iio/devices/iio:deviceX/buffer/watermark -KernelVersion: 4.2 What: /sys/bus/iio/devices/iio:deviceX/bufferY/watermark KernelVersion: 5.11 Contact: linux-iio@vger.kernel.org @@ -1633,8 +1596,6 @@ Description: the available samples after the timeout expires and thus have a maximum delay guarantee. -What: /sys/bus/iio/devices/iio:deviceX/buffer/data_available -KernelVersion: 4.16 What: /sys/bus/iio/devices/iio:deviceX/bufferY/data_available KernelVersion: 5.11 Contact: linux-iio@vger.kernel.org diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4371 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4371 index 544548ee794c..7fe6935d1448 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4371 +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4371 @@ -1,28 +1,3 @@ -What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency -KernelVersion: -Contact: linux-iio@vger.kernel.org -Description: - Stores the PLL frequency in Hz for channel Y. - Reading returns the actual frequency in Hz. - The ADF4371 has an integrated VCO with fundamendal output - frequency ranging from 4000000000 Hz 8000000000 Hz. - - out_altvoltage0_frequency: - A divide by 1, 2, 4, 8, 16, 32 or circuit generates - frequencies from 62500000 Hz to 8000000000 Hz. - out_altvoltage1_frequency: - This channel duplicates the channel 0 frequency - out_altvoltage2_frequency: - A frequency doubler generates frequencies from - 8000000000 Hz to 16000000000 Hz. - out_altvoltage3_frequency: - A frequency quadrupler generates frequencies from - 16000000000 Hz to 32000000000 Hz. - - Note: writes to one of the channels will affect the frequency of - all the other channels, since it involves changing the VCO - fundamental output frequency. - What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_name KernelVersion: Contact: linux-iio@vger.kernel.org @@ -34,11 +9,3 @@ Description: out_altvoltage2_name: RF16x out_altvoltage3_name: RF32x -What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_powerdown -KernelVersion: -Contact: linux-iio@vger.kernel.org -Description: - This attribute allows the user to power down the PLL and it's - RFOut buffers. - Writing 1 causes the specified channel to power down. - Clearing returns to normal operation. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x b/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x index 66b621f10223..a8e04b41d9ff 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x +++ b/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x @@ -18,6 +18,8 @@ Description: respectively which simply helper channels containing the calculated difference in the value of stage 1 - 2 and 3 - 4. The values are expressed in 24-bit twos complement. + The LED current for the stage is controlled via + out_currentY_raw. What: /sys/bus/iio/devices/iio:deviceX/in_intensityY_offset Date: May 2016 @@ -35,11 +37,3 @@ Contact: Andrew F. Davis Description: Get and set the resistance and the capacitance settings for the Transimpedance Amplifier during the associated stage. - -What: /sys/bus/iio/devices/iio:deviceX/out_currentY_raw -Date: May 2016 -KernelVersion: -Contact: Andrew F. Davis -Description: - Get and set the LED current for the specified LED active during - this stage. Y is the specific stage number. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-icm42600 b/Documentation/ABI/testing/sysfs-bus-iio-icm42600 deleted file mode 100644 index 0bf1fd4f5bf1..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-iio-icm42600 +++ /dev/null @@ -1,20 +0,0 @@ -What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibbias -What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibbias -What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibbias -What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_x_calibbias -What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_y_calibbias -What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_z_calibbias -KernelVersion: 5.8 -Contact: linux-iio@vger.kernel.org -Description: - Hardware applied calibration offset (assumed to fix production - inaccuracies). Values represent a real physical offset expressed - in SI units (m/s^2 for accelerometer and rad/s for gyroscope). - -What: /sys/bus/iio/devices/iio:deviceX/in_accel_calibbias_available -What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_calibbias_available -KernelVersion: 5.8 -Contact: linux-iio@vger.kernel.org -Description: - Range of available values for hardware offset. Values in SI - units (m/s^2 for accelerometer and rad/s for gyroscope). diff --git a/Documentation/ABI/testing/sysfs-bus-iio-light-lm3533-als b/Documentation/ABI/testing/sysfs-bus-iio-light-lm3533-als index 22c5ea670971..c476d48d0f82 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-light-lm3533-als +++ b/Documentation/ABI/testing/sysfs-bus-iio-light-lm3533-als @@ -41,14 +41,6 @@ Description: Get the current light zone (0..4) as defined by the in_illuminance0_threshY_{falling,rising} thresholds. -What: /sys/bus/iio/devices/iio:deviceX/out_currentY_raw -Date: May 2012 -KernelVersion: 3.5 -Contact: Johan Hovold -Description: - Get output current for channel Y (0..255), that is, - out_currentY_currentZ_raw, where Z is the current zone. - What: /sys/bus/iio/devices/iio:deviceX/out_currentY_currentZ_raw Date: May 2012 KernelVersion: 3.5 @@ -59,3 +51,6 @@ Description: These values correspond to the ALS-mapper target registers for ALS-mapper Y + 1. + + Note that out_currentY_raw provides the current for the + current zone. diff --git a/Documentation/ABI/testing/sysfs-bus-papr-pmem b/Documentation/ABI/testing/sysfs-bus-papr-pmem index 92e2db0e2d3d..95254cec92bf 100644 --- a/Documentation/ABI/testing/sysfs-bus-papr-pmem +++ b/Documentation/ABI/testing/sysfs-bus-papr-pmem @@ -39,9 +39,11 @@ KernelVersion: v5.9 Contact: linuxppc-dev , nvdimm@lists.linux.dev, Description: (RO) Report various performance stats related to papr-scm NVDIMM - device. Each stat is reported on a new line with each line - composed of a stat-identifier followed by it value. Below are - currently known dimm performance stats which are reported: + device. This attribute is only available for NVDIMM devices + that support reporting NVDIMM performance stats. Each stat is + reported on a new line with each line composed of a + stat-identifier followed by it value. Below are currently known + dimm performance stats which are reported: * "CtlResCt" : Controller Reset Count * "CtlResTm" : Controller Reset Elapsed Time diff --git a/Documentation/ABI/testing/sysfs-bus-spi-devices-spi-nor b/Documentation/ABI/testing/sysfs-bus-spi-devices-spi-nor new file mode 100644 index 000000000000..d76cd3946434 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-spi-devices-spi-nor @@ -0,0 +1,31 @@ +What: /sys/bus/spi/devices/.../spi-nor/jedec_id +Date: April 2021 +KernelVersion: 5.14 +Contact: linux-mtd@lists.infradead.org +Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the + flash device. + + +What: /sys/bus/spi/devices/.../spi-nor/manufacturer +Date: April 2021 +KernelVersion: 5.14 +Contact: linux-mtd@lists.infradead.org +Description: (RO) Manufacturer of the SPI NOR flash. + + +What: /sys/bus/spi/devices/.../spi-nor/partname +Date: April 2021 +KernelVersion: 5.14 +Contact: linux-mtd@lists.infradead.org +Description: (RO) Part name of the SPI NOR flash. + + +What: /sys/bus/spi/devices/.../spi-nor/sfdp +Date: April 2021 +KernelVersion: 5.14 +Contact: linux-mtd@lists.infradead.org +Description: (RO) This attribute is only present if the SPI NOR flash + device supports the "Read SFDP" command (5Ah). + + If present, it contains the complete SFDP (serial flash + discoverable parameters) binary data of the flash. diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt b/Documentation/ABI/testing/sysfs-bus-thunderbolt index c41c68f64693..95c21d6c9a84 100644 --- a/Documentation/ABI/testing/sysfs-bus-thunderbolt +++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt @@ -1,4 +1,4 @@ -What: /sys/bus/thunderbolt/devices/.../domainX/boot_acl +What: /sys/bus/thunderbolt/devices/.../domainX/boot_acl Date: Jun 2018 KernelVersion: 4.17 Contact: thunderbolt-software@lists.01.org @@ -21,7 +21,7 @@ Description: Holds a comma separated list of device unique_ids that If a device is authorized automatically during boot its boot attribute is set to 1. -What: /sys/bus/thunderbolt/devices/.../domainX/deauthorization +What: /sys/bus/thunderbolt/devices/.../domainX/deauthorization Date: May 2021 KernelVersion: 5.12 Contact: Mika Westerberg @@ -30,7 +30,7 @@ Description: This attribute tells whether the system supports de-authorize PCIe tunnel by writing 0 to authorized attribute under each device. -What: /sys/bus/thunderbolt/devices/.../domainX/iommu_dma_protection +What: /sys/bus/thunderbolt/devices/.../domainX/iommu_dma_protection Date: Mar 2019 KernelVersion: 4.21 Contact: thunderbolt-software@lists.01.org @@ -39,7 +39,7 @@ Description: This attribute tells whether the system uses IOMMU it is not (DMA protection is solely based on Thunderbolt security levels). -What: /sys/bus/thunderbolt/devices/.../domainX/security +What: /sys/bus/thunderbolt/devices/.../domainX/security Date: Sep 2017 KernelVersion: 4.13 Contact: thunderbolt-software@lists.01.org @@ -61,7 +61,7 @@ Description: This attribute holds current Thunderbolt security level the BIOS. ======= ================================================== -What: /sys/bus/thunderbolt/devices/.../authorized +What: /sys/bus/thunderbolt/devices/.../authorized Date: Sep 2017 KernelVersion: 4.13 Contact: thunderbolt-software@lists.01.org @@ -95,14 +95,14 @@ Description: This attribute is used to authorize Thunderbolt devices EKEYREJECTED if the challenge response did not match. == ======================================================== -What: /sys/bus/thunderbolt/devices/.../boot +What: /sys/bus/thunderbolt/devices/.../boot Date: Jun 2018 KernelVersion: 4.17 Contact: thunderbolt-software@lists.01.org Description: This attribute contains 1 if Thunderbolt device was already authorized on boot and 0 otherwise. -What: /sys/bus/thunderbolt/devices/.../generation +What: /sys/bus/thunderbolt/devices/.../generation Date: Jan 2020 KernelVersion: 5.5 Contact: Christian Kellner @@ -110,7 +110,7 @@ Description: This attribute contains the generation of the Thunderbolt controller associated with the device. It will contain 4 for USB4. -What: /sys/bus/thunderbolt/devices/.../key +What: /sys/bus/thunderbolt/devices/.../key Date: Sep 2017 KernelVersion: 4.13 Contact: thunderbolt-software@lists.01.org @@ -213,12 +213,15 @@ Description: When new NVM image is written to the non-active NVM restarted with the new NVM firmware. If the image verification fails an error code is returned instead. - This file will accept writing values "1" or "2" + This file will accept writing values "1", "2" or "3". - Writing "1" will flush the image to the storage area and authenticate the image in one action. - Writing "2" will run some basic validation on the image and flush it to the storage area. + - Writing "3" will authenticate the image that is + currently written in the storage area. This is only + supported with USB4 devices and retimers. When read holds status of the last authentication operation if an error occurred during the process. This @@ -226,6 +229,20 @@ Description: When new NVM image is written to the non-active NVM based mailbox before the device is power cycled. Writing 0 here clears the status. +What: /sys/bus/thunderbolt/devices/.../nvm_authenticate_on_disconnect +Date: Oct 2020 +KernelVersion: v5.9 +Contact: Mario Limonciello +Description: For supported devices, automatically authenticate the new Thunderbolt + image when the device is disconnected from the host system. + + This file will accept writing values "1" or "2" + + - Writing "1" will flush the image to the storage + area and prepare the device for authentication on disconnect. + - Writing "2" will run some basic validation on the image + and flush it to the storage area. + What: /sys/bus/thunderbolt/devices/./key Date: Jan 2018 KernelVersion: 4.15 @@ -276,6 +293,39 @@ Contact: thunderbolt-software@lists.01.org Description: This contains XDomain service specific settings as bitmask. Format: %x +What: /sys/bus/thunderbolt/devices/usb4_portX/link +Date: Sep 2021 +KernelVersion: v5.14 +Contact: Mika Westerberg +Description: Returns the current link mode. Possible values are + "usb4", "tbt" and "none". + +What: /sys/bus/thunderbolt/devices/usb4_portX/offline +Date: Sep 2021 +KernelVersion: v5.14 +Contact: Rajmohan Mani +Description: Writing 1 to this attribute puts the USB4 port into + offline mode. Only allowed when there is nothing + connected to the port (link attribute returns "none"). + Once the port is in offline mode it does not receive any + hotplug events. This is used to update NVM firmware of + on-board retimers. Writing 0 puts the port back to + online mode. + + This attribute is only visible if the platform supports + powering on retimers when there is no cable connected. + +What: /sys/bus/thunderbolt/devices/usb4_portX/rescan +Date: Sep 2021 +KernelVersion: v5.14 +Contact: Rajmohan Mani +Description: When the USB4 port is in offline mode writing 1 to this + attribute forces rescan of the sideband for on-board + retimers. Each retimer appear under the USB4 port as if + the USB4 link was up. These retimers act in the same way + as if the cable was connected so upgrading their NVM + firmware can be done the usual way. + What: /sys/bus/thunderbolt/devices/:./device Date: Oct 2020 KernelVersion: v5.9 @@ -308,17 +358,3 @@ Date: Oct 2020 KernelVersion: v5.9 Contact: Mika Westerberg Description: Retimer vendor identifier read from the hardware. - -What: /sys/bus/thunderbolt/devices/.../nvm_authenticate_on_disconnect -Date: Oct 2020 -KernelVersion: v5.9 -Contact: Mario Limonciello -Description: For supported devices, automatically authenticate the new Thunderbolt - image when the device is disconnected from the host system. - - This file will accept writing values "1" or "2" - - - Writing "1" will flush the image to the storage - area and prepare the device for authentication on disconnect. - - Writing "2" will run some basic validation on the image - and flush it to the storage area. diff --git a/Documentation/ABI/testing/sysfs-bus-usb b/Documentation/ABI/testing/sysfs-bus-usb index bf2c1968525f..73eb23bc1f34 100644 --- a/Documentation/ABI/testing/sysfs-bus-usb +++ b/Documentation/ABI/testing/sysfs-bus-usb @@ -154,17 +154,6 @@ Description: files hold a string value (enable or disable) indicating whether or not USB3 hardware LPM U1 or U2 is enabled for the device. -What: /sys/bus/usb/devices/.../removable -Date: February 2012 -Contact: Matthew Garrett -Description: - Some information about whether a given USB device is - physically fixed to the platform can be inferred from a - combination of hub descriptor bits and platform-specific data - such as ACPI. This file will read either "removable" or - "fixed" if the information is available, and "unknown" - otherwise. - What: /sys/bus/usb/devices/.../ltm_capable Date: July 2012 Contact: Sarah Sharp diff --git a/Documentation/ABI/testing/sysfs-class-spi-eeprom b/Documentation/ABI/testing/sysfs-class-spi-eeprom new file mode 100644 index 000000000000..1ff757982079 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-spi-eeprom @@ -0,0 +1,19 @@ +What: /sys/class/spi_master/spi/spi./fram +Date: June 2021 +KernelVersion: 5.14 +Contact: Jiri Prchal +Description: + Contains the FRAM binary data. Same as EEPROM, just another file + name to indicate that it employs ferroelectric process. + It performs write operations at bus speed - no write delays. + +What: /sys/class/spi_master/spi/spi./sernum +Date: May 2021 +KernelVersion: 5.14 +Contact: Jiri Prchal +Description: + Contains the serial number of the Cypress FRAM (FM25VN) if it is + present. It will be displayed as a 8 byte hex string, as read + from the device. + + This is a read-only attribute. diff --git a/Documentation/ABI/testing/sysfs-devices-removable b/Documentation/ABI/testing/sysfs-devices-removable new file mode 100644 index 000000000000..bda6c320c8d3 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-removable @@ -0,0 +1,18 @@ +What: /sys/devices/.../removable +Date: May 2021 +Contact: Rajat Jain +Description: + Information about whether a given device can be removed from the + platform by the user. This is determined by its subsystem in a + bus / platform-specific way. This attribute is only present for + devices that can support determining such information: + + "removable": device can be removed from the platform by the user + "fixed": device is fixed to the platform / cannot be removed + by the user. + "unknown": The information is unavailable / cannot be deduced. + + Currently this is only supported by USB (which infers the + information from a combination of hub descriptor bits and + platform-specific data such as ACPI) and PCI (which gets this + from ACPI / device tree). diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs index eaac6898f0c0..b4a5d55fa19f 100644 --- a/Documentation/ABI/testing/sysfs-driver-ufs +++ b/Documentation/ABI/testing/sysfs-driver-ufs @@ -995,6 +995,132 @@ Description: This entry shows the target state of an UFS UIC link The file is read only. +What: /sys/bus/platform/drivers/ufshcd/*/monitor/monitor_enable +Date: January 2021 +Contact: Can Guo +Description: This file shows the status of performance monitor enablement + and it can be used to start/stop the monitor. When the monitor + is stopped, the performance data collected is also cleared. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/monitor_chunk_size +Date: January 2021 +Contact: Can Guo +Description: This file tells the monitor to focus on requests transferring + data of specific chunk size (in Bytes). 0 means any chunk size. + It can only be changed when monitor is disabled. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_total_sectors +Date: January 2021 +Contact: Can Guo +Description: This file shows how many sectors (in 512 Bytes) have been + sent from device to host after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_total_busy +Date: January 2021 +Contact: Can Guo +Description: This file shows how long (in micro seconds) has been spent + sending data from device to host after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_nr_requests +Date: January 2021 +Contact: Can Guo +Description: This file shows how many read requests have been sent after + monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_req_latency_max +Date: January 2021 +Contact: Can Guo +Description: This file shows the maximum latency (in micro seconds) of + read requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_req_latency_min +Date: January 2021 +Contact: Can Guo +Description: This file shows the minimum latency (in micro seconds) of + read requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_req_latency_avg +Date: January 2021 +Contact: Can Guo +Description: This file shows the average latency (in micro seconds) of + read requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/read_req_latency_sum +Date: January 2021 +Contact: Can Guo +Description: This file shows the total latency (in micro seconds) of + read requests sent after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_total_sectors +Date: January 2021 +Contact: Can Guo +Description: This file shows how many sectors (in 512 Bytes) have been sent + from host to device after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_total_busy +Date: January 2021 +Contact: Can Guo +Description: This file shows how long (in micro seconds) has been spent + sending data from host to device after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_nr_requests +Date: January 2021 +Contact: Can Guo +Description: This file shows how many write requests have been sent after + monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_req_latency_max +Date: January 2021 +Contact: Can Guo +Description: This file shows the maximum latency (in micro seconds) of write + requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_req_latency_min +Date: January 2021 +Contact: Can Guo +Description: This file shows the minimum latency (in micro seconds) of write + requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_req_latency_avg +Date: January 2021 +Contact: Can Guo +Description: This file shows the average latency (in micro seconds) of write + requests after monitor gets started. + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/monitor/write_req_latency_sum +Date: January 2021 +Contact: Can Guo +Description: This file shows the total latency (in micro seconds) of write + requests after monitor gets started. + + The file is read only. + What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/wb_presv_us_en Date: June 2020 Contact: Asutosh Das diff --git a/Documentation/ABI/testing/sysfs-firmware-memmap b/Documentation/ABI/testing/sysfs-firmware-memmap index 1f6f4d3a32c0..9205122fa4b1 100644 --- a/Documentation/ABI/testing/sysfs-firmware-memmap +++ b/Documentation/ABI/testing/sysfs-firmware-memmap @@ -56,6 +56,10 @@ Description: - System RAM - ACPI Tables - ACPI Non-volatile Storage + - Unusable memory + - Persistent Memory (legacy) + - Persistent Memory + - Soft Reserved - reserved Following shell snippet can be used to display that memory diff --git a/Documentation/RCU/Design/Memory-Ordering/Tree-RCU-Memory-Ordering.rst b/Documentation/RCU/Design/Memory-Ordering/Tree-RCU-Memory-Ordering.rst index a648b423ba0e..11cdab037bff 100644 --- a/Documentation/RCU/Design/Memory-Ordering/Tree-RCU-Memory-Ordering.rst +++ b/Documentation/RCU/Design/Memory-Ordering/Tree-RCU-Memory-Ordering.rst @@ -21,7 +21,7 @@ Any code that happens after the end of a given RCU grace period is guaranteed to see the effects of all accesses prior to the beginning of that grace period that are within RCU read-side critical sections. Similarly, any code that happens before the beginning of a given RCU grace -period is guaranteed to see the effects of all accesses following the end +period is guaranteed to not see the effects of all accesses following the end of that grace period that are within RCU read-side critical sections. Note well that RCU-sched read-side critical sections include any region @@ -339,14 +339,14 @@ The diagram below shows the path of ordering if the leftmost leftmost ``rcu_node`` structure offlines its last CPU and if the next ``rcu_node`` structure has no online CPUs). -.. kernel-figure:: TreeRCU-gp-init-1.svg +.. kernel-figure:: TreeRCU-gp-init-2.svg The final ``rcu_gp_init()`` pass through the ``rcu_node`` tree traverses breadth-first, setting each ``rcu_node`` structure's ``->gp_seq`` field to the newly advanced value from the ``rcu_state`` structure, as shown in the following diagram. -.. kernel-figure:: TreeRCU-gp-init-1.svg +.. kernel-figure:: TreeRCU-gp-init-3.svg This change will also cause each CPU's next call to ``__note_gp_changes()`` to notice that a new grace period has started, diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 4e59925e6583..5c7377b5bd3e 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -953,6 +953,21 @@ All cgroup core files are prefixed with "cgroup." it's possible to delete a frozen (and empty) cgroup, as well as create new sub-cgroups. + cgroup.kill + A write-only single value file which exists in non-root cgroups. + The only allowed value is "1". + + Writing "1" to the file causes the cgroup and all descendant cgroups to + be killed. This means that all processes located in the affected cgroup + tree will be killed via SIGKILL. + + Killing a cgroup tree will deal with concurrent forks appropriately and + is protected against migrations. + + In a threaded cgroup, writing this file fails with EOPNOTSUPP as + killing cgroups is a process directed operation, i.e. it affects + the whole thread-group. + Controllers =========== diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst index 3996b54158bf..01ba293a2d70 100644 --- a/Documentation/admin-guide/kernel-parameters.rst +++ b/Documentation/admin-guide/kernel-parameters.rst @@ -76,6 +76,11 @@ to change, such as less cores in the CPU list, then N and any ranges using N will also change. Use the same on a small 4 core system, and "16-N" becomes "16-3" and now the same boot input will be flagged as invalid (start > end). +The special case-tolerant group name "all" has a meaning of selecting all CPUs, +so that "nohz_full=all" is the equivalent of "nohz_full=0-N". + +The semantics of "N" and "all" is supported on a level of bitmaps and holds for +all users of bitmap_parse(). This document may not be entirely up to date and comprehensive. The command "modinfo -p ${modulename}" shows a current list of all parameters of a loadable diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 02af13bfe588..6f10a677632e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -301,6 +301,9 @@ allowed anymore to lift isolation requirements as needed. This option does not override iommu=pt + force_enable - Force enable the IOMMU on platforms known + to be buggy with IOMMU enabled. Use this + option with care. amd_iommu_dump= [HW,X86-64] Enable AMD IOMMU driver option to dump the ACPI table @@ -1119,6 +1122,11 @@ the driver will use only 32-bit accessors to read/write the device registers. + liteuart, + Start an early console on a litex serial port at the + specified address. The serial port must already be + setup and configured. Options are not yet supported. + meson, Start an early, polled-mode console on a meson serial port at the specified address. The serial port must @@ -1594,6 +1602,23 @@ Documentation/admin-guide/mm/hugetlbpage.rst. Format: size[KMG] + hugetlb_free_vmemmap= + [KNL] Reguires CONFIG_HUGETLB_PAGE_FREE_VMEMMAP + enabled. + Allows heavy hugetlb users to free up some more + memory (6 * PAGE_SIZE for each 2MB hugetlb page). + Format: { on | off (default) } + + on: enable the feature + off: disable the feature + + Built with CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y, + the default is on. + + This is not compatible with memory_hotplug.memmap_on_memory. + If both parameters are enabled, hugetlb_free_vmemmap takes + precedence over memory_hotplug.memmap_on_memory. + hung_task_panic= [KNL] Should the hung task detector generate panics. Format: 0 | 1 @@ -2018,7 +2043,7 @@ forcing Dual Address Cycle for PCI cards supporting greater than 32-bit addressing. - iommu.strict= [ARM64] Configure TLB invalidation behaviour + iommu.strict= [ARM64, X86] Configure TLB invalidation behaviour Format: { "0" | "1" } 0 - Lazy mode. Request that DMA unmap operations use deferred @@ -2029,6 +2054,10 @@ 1 - Strict mode (default). DMA unmap operations invalidate IOMMU hardware TLBs synchronously. + Note: on x86, the default behaviour depends on the + equivalent driver-specific parameters, but a strict + mode explicitly specified by either method takes + precedence. iommu.passthrough= [ARM64, X86] Configure DMA to bypass the IOMMU by default. @@ -2864,6 +2893,10 @@ Note that even when enabled, there are a few cases where the feature is not effective. + This is not compatible with hugetlb_free_vmemmap. If + both parameters are enabled, hugetlb_free_vmemmap takes + precedence over memory_hotplug.memmap_on_memory. + memtest= [KNL,X86,ARM,PPC,RISCV] Enable memtest Format: default : 0 @@ -4330,6 +4363,11 @@ whole algorithm to behave better in low memory condition. + rcutree.rcu_delay_page_cache_fill_msec= [KNL] + Set the page-cache refill delay (in milliseconds) + in response to low-memory conditions. The range + of permitted values is in the range 0:100000. + rcutree.jiffies_till_first_fqs= [KNL] Set delay from grace-period initialization to first attempt to force quiescent states. @@ -5648,12 +5686,25 @@ Note, echoing 1 into this file without the tracepoint_printk kernel cmdline option has no effect. + The tp_printk_stop_on_boot (see below) can also be used + to stop the printing of events to console at + late_initcall_sync. + ** CAUTION ** Having tracepoints sent to printk() and activating high frequency tracepoints such as irq or sched, can cause the system to live lock. + tp_printk_stop_on_boot[FTRACE] + When tp_printk (above) is set, it can cause a lot of noise + on the console. It may be useful to only include the + printing of events during boot up, as user space may + make the system inoperable. + + This command line option will stop the printing of events + to console at the late_initcall_sync() time frame. + traceoff_on_warning [FTRACE] enable this option to disable tracing when a warning is hit. This turns off "tracing_on". Tracing can diff --git a/Documentation/admin-guide/mm/hugetlbpage.rst b/Documentation/admin-guide/mm/hugetlbpage.rst index f7b1c7462991..8abaeb144e44 100644 --- a/Documentation/admin-guide/mm/hugetlbpage.rst +++ b/Documentation/admin-guide/mm/hugetlbpage.rst @@ -60,6 +60,10 @@ HugePages_Surp the pool above the value in ``/proc/sys/vm/nr_hugepages``. The maximum number of surplus huge pages is controlled by ``/proc/sys/vm/nr_overcommit_hugepages``. + Note: When the feature of freeing unused vmemmap pages associated + with each hugetlb page is enabled, the number of surplus huge pages + may be temporarily larger than the maximum number of surplus huge + pages when the system is under memory pressure. Hugepagesize is the default hugepage size (in Kb). Hugetlb @@ -80,6 +84,10 @@ returned to the huge page pool when freed by a task. A user with root privileges can dynamically allocate more or free some persistent huge pages by increasing or decreasing the value of ``nr_hugepages``. +Note: When the feature of freeing unused vmemmap pages associated with each +hugetlb page is enabled, we can fail to free the huge pages triggered by +the user when ths system is under memory pressure. Please try again later. + Pages that are used as huge pages are reserved inside the kernel and cannot be used for other purposes. Huge pages cannot be swapped out under memory pressure. @@ -145,6 +153,9 @@ default_hugepagesz will all result in 256 2M huge pages being allocated. Valid default huge page size is architecture dependent. +hugetlb_free_vmemmap + When CONFIG_HUGETLB_PAGE_FREE_VMEMMAP is set, this enables freeing + unused vmemmap pages associated with each HugeTLB page. When multiple huge page sizes are supported, ``/proc/sys/vm/nr_hugepages`` indicates the current number of pre-allocated huge pages of the default size. diff --git a/Documentation/admin-guide/mm/memory-hotplug.rst b/Documentation/admin-guide/mm/memory-hotplug.rst index 05d51d2d8beb..c6bae2d77160 100644 --- a/Documentation/admin-guide/mm/memory-hotplug.rst +++ b/Documentation/admin-guide/mm/memory-hotplug.rst @@ -357,6 +357,19 @@ creates ZONE_MOVABLE as following. Unfortunately, there is no information to show which memory block belongs to ZONE_MOVABLE. This is TBD. + Memory offlining can fail when dissolving a free huge page on ZONE_MOVABLE + and the feature of freeing unused vmemmap pages associated with each hugetlb + page is enabled. + + This can happen when we have plenty of ZONE_MOVABLE memory, but not enough + kernel memory to allocate vmemmmap pages. We may even be able to migrate + huge page contents, but will not be able to dissolve the source huge page. + This will prevent an offline operation and is unfortunate as memory offlining + is expected to succeed on movable zones. Users that depend on memory hotplug + to succeed for movable zones should carefully consider whether the memory + savings gained from this feature are worth the risk of possibly not being + able to offline memory in certain situations. + .. note:: Techniques that rely on long-term pinnings of memory (especially, RDMA and vfio) are fundamentally problematic with ZONE_MOVABLE and, therefore, memory diff --git a/Documentation/admin-guide/mm/pagemap.rst b/Documentation/admin-guide/mm/pagemap.rst index 340a5aee9b80..fb578fbbb76c 100644 --- a/Documentation/admin-guide/mm/pagemap.rst +++ b/Documentation/admin-guide/mm/pagemap.rst @@ -21,6 +21,8 @@ There are four components to pagemap: * Bit 55 pte is soft-dirty (see :ref:`Documentation/admin-guide/mm/soft-dirty.rst `) * Bit 56 page exclusively mapped (since 4.2) + * Bit 57 pte is uffd-wp write-protected (since 5.13) (see + :ref:`Documentation/admin-guide/mm/userfaultfd.rst `) * Bits 57-60 zero * Bit 61 page is file-page or shared-anon (since 3.5) * Bit 62 page swapped diff --git a/Documentation/admin-guide/mm/userfaultfd.rst b/Documentation/admin-guide/mm/userfaultfd.rst index 3aa38e8b8361..6528036093e1 100644 --- a/Documentation/admin-guide/mm/userfaultfd.rst +++ b/Documentation/admin-guide/mm/userfaultfd.rst @@ -77,7 +77,8 @@ events, except page fault notifications, may be generated: - ``UFFD_FEATURE_MINOR_HUGETLBFS`` indicates that the kernel supports ``UFFDIO_REGISTER_MODE_MINOR`` registration for hugetlbfs virtual memory - areas. + areas. ``UFFD_FEATURE_MINOR_SHMEM`` is the analogous feature indicating + support for shmem virtual memory areas. The userland application should set the feature flags it intends to use when invoking the ``UFFDIO_API`` ioctl, to request that those features be diff --git a/Documentation/admin-guide/thunderbolt.rst b/Documentation/admin-guide/thunderbolt.rst index f18e881373c4..2ed79f41a411 100644 --- a/Documentation/admin-guide/thunderbolt.rst +++ b/Documentation/admin-guide/thunderbolt.rst @@ -256,6 +256,35 @@ Note names of the NVMem devices ``nvm_activeN`` and ``nvm_non_activeN`` depend on the order they are registered in the NVMem subsystem. N in the name is the identifier added by the NVMem subsystem. +Upgrading on-board retimer NVM when there is no cable connected +--------------------------------------------------------------- +If the platform supports, it may be possible to upgrade the retimer NVM +firmware even when there is nothing connected to the USB4 +ports. When this is the case the ``usb4_portX`` devices have two special +attributes: ``offline`` and ``rescan``. The way to upgrade the firmware +is to first put the USB4 port into offline mode:: + + # echo 1 > /sys/bus/thunderbolt/devices/0-0/usb4_port1/offline + +This step makes sure the port does not respond to any hotplug events, +and also ensures the retimers are powered on. The next step is to scan +for the retimers:: + + # echo 1 > /sys/bus/thunderbolt/devices/0-0/usb4_port1/rescan + +This enumerates and adds the on-board retimers. Now retimer NVM can be +upgraded in the same way than with cable connected (see previous +section). However, the retimer is not disconnected as we are offline +mode) so after writing ``1`` to ``nvm_authenticate`` one should wait for +5 or more seconds before running rescan again:: + + # echo 1 > /sys/bus/thunderbolt/devices/0-0/usb4_port1/rescan + +This point if everything went fine, the port can be put back to +functional state again:: + + # echo 0 > /sys/bus/thunderbolt/devices/0-0/usb4_port1/offline + Upgrading NVM when host controller is in safe mode -------------------------------------------------- If the existing NVM is not properly authenticated (or is missing) the diff --git a/Documentation/core-api/kernel-api.rst b/Documentation/core-api/kernel-api.rst index 741aa37dc181..2a7444e3a4c2 100644 --- a/Documentation/core-api/kernel-api.rst +++ b/Documentation/core-api/kernel-api.rst @@ -24,11 +24,8 @@ String Conversions .. kernel-doc:: lib/vsprintf.c :export: -.. kernel-doc:: include/linux/kernel.h - :functions: kstrtol - -.. kernel-doc:: include/linux/kernel.h - :functions: kstrtoul +.. kernel-doc:: include/linux/kstrtox.h + :functions: kstrtol kstrtoul .. kernel-doc:: lib/kstrtox.c :export: diff --git a/Documentation/dev-tools/kcsan.rst b/Documentation/dev-tools/kcsan.rst index d85ce238ace7..6a600cf8430b 100644 --- a/Documentation/dev-tools/kcsan.rst +++ b/Documentation/dev-tools/kcsan.rst @@ -27,75 +27,57 @@ Error reports A typical data race report looks like this:: ================================================================== - BUG: KCSAN: data-race in generic_permission / kernfs_refresh_inode + BUG: KCSAN: data-race in test_kernel_read / test_kernel_write - write to 0xffff8fee4c40700c of 4 bytes by task 175 on cpu 4: - kernfs_refresh_inode+0x70/0x170 - kernfs_iop_permission+0x4f/0x90 - inode_permission+0x190/0x200 - link_path_walk.part.0+0x503/0x8e0 - path_lookupat.isra.0+0x69/0x4d0 - filename_lookup+0x136/0x280 - user_path_at_empty+0x47/0x60 - vfs_statx+0x9b/0x130 - __do_sys_newlstat+0x50/0xb0 - __x64_sys_newlstat+0x37/0x50 - do_syscall_64+0x85/0x260 - entry_SYSCALL_64_after_hwframe+0x44/0xa9 + write to 0xffffffffc009a628 of 8 bytes by task 487 on cpu 0: + test_kernel_write+0x1d/0x30 + access_thread+0x89/0xd0 + kthread+0x23e/0x260 + ret_from_fork+0x22/0x30 - read to 0xffff8fee4c40700c of 4 bytes by task 166 on cpu 6: - generic_permission+0x5b/0x2a0 - kernfs_iop_permission+0x66/0x90 - inode_permission+0x190/0x200 - link_path_walk.part.0+0x503/0x8e0 - path_lookupat.isra.0+0x69/0x4d0 - filename_lookup+0x136/0x280 - user_path_at_empty+0x47/0x60 - do_faccessat+0x11a/0x390 - __x64_sys_access+0x3c/0x50 - do_syscall_64+0x85/0x260 - entry_SYSCALL_64_after_hwframe+0x44/0xa9 + read to 0xffffffffc009a628 of 8 bytes by task 488 on cpu 6: + test_kernel_read+0x10/0x20 + access_thread+0x89/0xd0 + kthread+0x23e/0x260 + ret_from_fork+0x22/0x30 + + value changed: 0x00000000000009a6 -> 0x00000000000009b2 Reported by Kernel Concurrency Sanitizer on: - CPU: 6 PID: 166 Comm: systemd-journal Not tainted 5.3.0-rc7+ #1 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 + CPU: 6 PID: 488 Comm: access_thread Not tainted 5.12.0-rc2+ #1 + Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014 ================================================================== The header of the report provides a short summary of the functions involved in the race. It is followed by the access types and stack traces of the 2 threads -involved in the data race. +involved in the data race. If KCSAN also observed a value change, the observed +old value and new value are shown on the "value changed" line respectively. The other less common type of data race report looks like this:: ================================================================== - BUG: KCSAN: data-race in e1000_clean_rx_irq+0x551/0xb10 + BUG: KCSAN: data-race in test_kernel_rmw_array+0x71/0xd0 - race at unknown origin, with read to 0xffff933db8a2ae6c of 1 bytes by interrupt on cpu 0: - e1000_clean_rx_irq+0x551/0xb10 - e1000_clean+0x533/0xda0 - net_rx_action+0x329/0x900 - __do_softirq+0xdb/0x2db - irq_exit+0x9b/0xa0 - do_IRQ+0x9c/0xf0 - ret_from_intr+0x0/0x18 - default_idle+0x3f/0x220 - arch_cpu_idle+0x21/0x30 - do_idle+0x1df/0x230 - cpu_startup_entry+0x14/0x20 - rest_init+0xc5/0xcb - arch_call_rest_init+0x13/0x2b - start_kernel+0x6db/0x700 + race at unknown origin, with read to 0xffffffffc009bdb0 of 8 bytes by task 515 on cpu 2: + test_kernel_rmw_array+0x71/0xd0 + access_thread+0x89/0xd0 + kthread+0x23e/0x260 + ret_from_fork+0x22/0x30 + + value changed: 0x0000000000002328 -> 0x0000000000002329 Reported by Kernel Concurrency Sanitizer on: - CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.3.0-rc7+ #2 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 + CPU: 2 PID: 515 Comm: access_thread Not tainted 5.12.0-rc2+ #1 + Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014 ================================================================== This report is generated where it was not possible to determine the other racing thread, but a race was inferred due to the data value of the watched -memory location having changed. These can occur either due to missing -instrumentation or e.g. DMA accesses. These reports will only be generated if -``CONFIG_KCSAN_REPORT_RACE_UNKNOWN_ORIGIN=y`` (selected by default). +memory location having changed. These reports always show a "value changed" +line. A common reason for reports of this type are missing instrumentation in +the racing thread, but could also occur due to e.g. DMA accesses. Such reports +are shown only if ``CONFIG_KCSAN_REPORT_RACE_UNKNOWN_ORIGIN=y``, which is +enabled by default. Selective analysis ~~~~~~~~~~~~~~~~~~ @@ -106,7 +88,8 @@ the below options are available: * KCSAN understands the ``data_race(expr)`` annotation, which tells KCSAN that any data races due to accesses in ``expr`` should be ignored and resulting - behaviour when encountering a data race is deemed safe. + behaviour when encountering a data race is deemed safe. Please see + `"Marking Shared-Memory Accesses" in the LKMM`_ for more information. * Disabling data race detection for entire functions can be accomplished by using the function attribute ``__no_kcsan``:: @@ -128,6 +111,8 @@ the below options are available: KCSAN_SANITIZE := n +.. _"Marking Shared-Memory Accesses" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/memory-model/Documentation/access-marking.txt + Furthermore, it is possible to tell KCSAN to show or hide entire classes of data races, depending on preferences. These can be changed via the following Kconfig options: diff --git a/Documentation/dev-tools/kunit/index.rst b/Documentation/dev-tools/kunit/index.rst index 25d92a9a05ea..cacb35ec658d 100644 --- a/Documentation/dev-tools/kunit/index.rst +++ b/Documentation/dev-tools/kunit/index.rst @@ -14,6 +14,7 @@ KUnit - Unit Testing for the Linux Kernel style faq tips + running_tips What is KUnit? ============== diff --git a/Documentation/dev-tools/kunit/kunit-tool.rst b/Documentation/dev-tools/kunit/kunit-tool.rst index 29ae2fee8123..c7ff9afe407a 100644 --- a/Documentation/dev-tools/kunit/kunit-tool.rst +++ b/Documentation/dev-tools/kunit/kunit-tool.rst @@ -22,14 +22,19 @@ not require any virtualization support: it is just a regular program. What is a .kunitconfig? ======================= -It's just a defconfig that kunit_tool looks for in the base directory. -kunit_tool uses it to generate a .config as you might expect. In addition, it -verifies that the generated .config contains the CONFIG options in the -.kunitconfig; the reason it does this is so that it is easy to be sure that a -CONFIG that enables a test actually ends up in the .config. +It's just a defconfig that kunit_tool looks for in the build directory +(``.kunit`` by default). kunit_tool uses it to generate a .config as you might +expect. In addition, it verifies that the generated .config contains the CONFIG +options in the .kunitconfig; the reason it does this is so that it is easy to +be sure that a CONFIG that enables a test actually ends up in the .config. -How do I use kunit_tool? -======================== +It's also possible to pass a separate .kunitconfig fragment to kunit_tool, +which is useful if you have several different groups of tests you wish +to run independently, or if you want to use pre-defined test configs for +certain subsystems. + +Getting Started with kunit_tool +=============================== If a kunitconfig is present at the root directory, all you have to do is: @@ -48,10 +53,177 @@ However, you most likely want to use it with the following options: .. note:: This command will work even without a .kunitconfig file: if no - .kunitconfig is present, a default one will be used instead. + .kunitconfig is present, a default one will be used instead. + +If you wish to use a different .kunitconfig file (such as one provided for +testing a particular subsystem), you can pass it as an option. + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py run --kunitconfig=fs/ext4/.kunitconfig For a list of all the flags supported by kunit_tool, you can run: .. code-block:: bash ./tools/testing/kunit/kunit.py run --help + +Configuring, Building, and Running Tests +======================================== + +It's also possible to run just parts of the KUnit build process independently, +which is useful if you want to make manual changes to part of the process. + +A .config can be generated from a .kunitconfig by using the ``config`` argument +when running kunit_tool: + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py config + +Similarly, if you just want to build a KUnit kernel from the current .config, +you can use the ``build`` argument: + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py build + +And, if you already have a built UML kernel with built-in KUnit tests, you can +run the kernel and display the test results with the ``exec`` argument: + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py exec + +The ``run`` command which is discussed above is equivalent to running all three +of these in sequence. + +All of these commands accept a number of optional command-line arguments. The +``--help`` flag will give a complete list of these, or keep reading this page +for a guide to some of the more useful ones. + +Parsing Test Results +==================== + +KUnit tests output their results in TAP (Test Anything Protocol) format. +kunit_tool will, when running tests, parse this output and print a summary +which is much more pleasant to read. If you wish to look at the raw test +results in TAP format, you can pass the ``--raw_output`` argument. + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py run --raw_output + +.. note:: + The raw output from test runs may contain other, non-KUnit kernel log + lines. + +If you have KUnit results in their raw TAP format, you can parse them and print +the human-readable summary with the ``parse`` command for kunit_tool. This +accepts a filename for an argument, or will read from standard input. + +.. code-block:: bash + + # Reading from a file + ./tools/testing/kunit/kunit.py parse /var/log/dmesg + # Reading from stdin + dmesg | ./tools/testing/kunit/kunit.py parse + +This is very useful if you wish to run tests in a configuration not supported +by kunit_tool (such as on real hardware, or an unsupported architecture). + +Filtering Tests +=============== + +It's possible to run only a subset of the tests built into a kernel by passing +a filter to the ``exec`` or ``run`` commands. For example, if you only wanted +to run KUnit resource tests, you could use: + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py run 'kunit-resource*' + +This uses the standard glob format for wildcards. + +Running Tests on QEMU +===================== + +kunit_tool supports running tests on QEMU as well as via UML (as mentioned +elsewhere). The default way of running tests on QEMU requires two flags: + +``--arch`` + Selects a collection of configs (Kconfig as well as QEMU configs + options, etc) that allow KUnit tests to be run on the specified + architecture in a minimal way; this is usually not much slower than + using UML. The architecture argument is the same as the name of the + option passed to the ``ARCH`` variable used by Kbuild. Not all + architectures are currently supported by this flag, but can be handled + by the ``--qemu_config`` discussed later. If ``um`` is passed (or this + this flag is ignored) the tests will run via UML. Non-UML architectures, + e.g. i386, x86_64, arm, um, etc. Non-UML run on QEMU. + +``--cross_compile`` + Specifies the use of a toolchain by Kbuild. The argument passed here is + the same passed to the ``CROSS_COMPILE`` variable used by Kbuild. As a + reminder this will be the prefix for the toolchain binaries such as gcc + for example ``sparc64-linux-gnu-`` if you have the sparc toolchain + installed on your system, or + ``$HOME/toolchains/microblaze/gcc-9.2.0-nolibc/microblaze-linux/bin/microblaze-linux-`` + if you have downloaded the microblaze toolchain from the 0-day website + to a directory in your home directory called ``toolchains``. + +In many cases it is likely that you may want to run an architecture which is +not supported by the ``--arch`` flag, or you may want to just run KUnit tests +on QEMU using a non-default configuration. For this use case, you can write +your own QemuConfig. These QemuConfigs are written in Python. They must have an +import line ``from ..qemu_config import QemuArchParams`` at the top of the file +and the file must contain a variable called ``QEMU_ARCH`` that has an instance +of ``QemuArchParams`` assigned to it. An example can be seen in +``tools/testing/kunit/qemu_configs/x86_64.py``. + +Once you have a QemuConfig you can pass it into kunit_tool using the +``--qemu_config`` flag; when used this flag replaces the ``--arch`` flag. If we +were to do this with the ``x86_64.py`` example from above, the invocation would +look something like this: + +.. code-block:: bash + + ./tools/testing/kunit/kunit.py run \ + --timeout=60 \ + --jobs=12 \ + --qemu_config=./tools/testing/kunit/qemu_configs/x86_64.py + +Other Useful Options +==================== + +kunit_tool has a number of other command-line arguments which can be useful +when adapting it to fit your environment or needs. + +Some of the more useful ones are: + +``--help`` + Lists all of the available options. Note that different commands + (``config``, ``build``, ``run``, etc) will have different supported + options. Place ``--help`` before the command to list common options, + and after the command for options specific to that command. + +``--build_dir`` + Specifies the build directory that kunit_tool will use. This is where + the .kunitconfig file is located, as well as where the .config and + compiled kernel will be placed. Defaults to ``.kunit``. + +``--make_options`` + Specifies additional options to pass to ``make`` when compiling a + kernel (with the ``build`` or ``run`` commands). For example, to enable + compiler warnings, you can pass ``--make_options W=1``. + +``--alltests`` + Builds a UML kernel with all config options enabled using ``make + allyesconfig``. This allows you to run as many tests as is possible, + but is very slow and prone to breakage as new options are added or + modified. In most cases, enabling all tests which have satisfied + dependencies by adding ``CONFIG_KUNIT_ALL_TESTS=1`` to your + .kunitconfig is preferable. + +There are several other options (and new ones are often added), so do check +``--help`` if you're looking for something not mentioned here. diff --git a/Documentation/dev-tools/kunit/running_tips.rst b/Documentation/dev-tools/kunit/running_tips.rst new file mode 100644 index 000000000000..7d99386cf94a --- /dev/null +++ b/Documentation/dev-tools/kunit/running_tips.rst @@ -0,0 +1,259 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================ +Tips For Running KUnit Tests +============================ + +Using ``kunit.py run`` ("kunit tool") +===================================== + +Running from any directory +-------------------------- + +It can be handy to create a bash function like: + +.. code-block:: bash + + function run_kunit() { + ( cd "$(git rev-parse --show-toplevel)" && ./tools/testing/kunit/kunit.py run $@ ) + } + +.. note:: + Early versions of ``kunit.py`` (before 5.6) didn't work unless run from + the kernel root, hence the use of a subshell and ``cd``. + +Running a subset of tests +------------------------- + +``kunit.py run`` accepts an optional glob argument to filter tests. Currently +this only matches against suite names, but this may change in the future. + +Say that we wanted to run the sysctl tests, we could do so via: + +.. code-block:: bash + + $ echo -e 'CONFIG_KUNIT=y\nCONFIG_KUNIT_ALL_TESTS=y' > .kunit/.kunitconfig + $ ./tools/testing/kunit/kunit.py run 'sysctl*' + +We're paying the cost of building more tests than we need this way, but it's +easier than fiddling with ``.kunitconfig`` files or commenting out +``kunit_suite``'s. + +However, if we wanted to define a set of tests in a less ad hoc way, the next +tip is useful. + +Defining a set of tests +----------------------- + +``kunit.py run`` (along with ``build``, and ``config``) supports a +``--kunitconfig`` flag. So if you have a set of tests that you want to run on a +regular basis (especially if they have other dependencies), you can create a +specific ``.kunitconfig`` for them. + +E.g. kunit has one for its tests: + +.. code-block:: bash + + $ ./tools/testing/kunit/kunit.py run --kunitconfig=lib/kunit/.kunitconfig + +Alternatively, if you're following the convention of naming your +file ``.kunitconfig``, you can just pass in the dir, e.g. + +.. code-block:: bash + + $ ./tools/testing/kunit/kunit.py run --kunitconfig=lib/kunit + +.. note:: + This is a relatively new feature (5.12+) so we don't have any + conventions yet about on what files should be checked in versus just + kept around locally. It's up to you and your maintainer to decide if a + config is useful enough to submit (and therefore have to maintain). + +.. note:: + Having ``.kunitconfig`` fragments in a parent and child directory is + iffy. There's discussion about adding an "import" statement in these + files to make it possible to have a top-level config run tests from all + child directories. But that would mean ``.kunitconfig`` files are no + longer just simple .config fragments. + + One alternative would be to have kunit tool recursively combine configs + automagically, but tests could theoretically depend on incompatible + options, so handling that would be tricky. + +Generating code coverage reports under UML +------------------------------------------ + +.. note:: + TODO(brendanhiggins@google.com): There are various issues with UML and + versions of gcc 7 and up. You're likely to run into missing ``.gcda`` + files or compile errors. We know one `faulty GCC commit + `_ + but not how we'd go about getting this fixed. The compile errors still + need some investigation. + +.. note:: + TODO(brendanhiggins@google.com): for recent versions of Linux + (5.10-5.12, maybe earlier), there's a bug with gcov counters not being + flushed in UML. This translates to very low (<1%) reported coverage. This is + related to the above issue and can be worked around by replacing the + one call to ``uml_abort()`` (it's in ``os_dump_core()``) with a plain + ``exit()``. + + +This is different from the "normal" way of getting coverage information that is +documented in Documentation/dev-tools/gcov.rst. + +Instead of enabling ``CONFIG_GCOV_KERNEL=y``, we can set these options: + +.. code-block:: none + + CONFIG_DEBUG_KERNEL=y + CONFIG_DEBUG_INFO=y + CONFIG_GCOV=y + + +Putting it together into a copy-pastable sequence of commands: + +.. code-block:: bash + + # Append coverage options to the current config + $ echo -e "CONFIG_DEBUG_KERNEL=y\nCONFIG_DEBUG_INFO=y\nCONFIG_GCOV=y" >> .kunit/.kunitconfig + $ ./tools/testing/kunit/kunit.py run + # Extract the coverage information from the build dir (.kunit/) + $ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/ + + # From here on, it's the same process as with CONFIG_GCOV_KERNEL=y + # E.g. can generate an HTML report in a tmp dir like so: + $ genhtml -o /tmp/coverage_html coverage.info + + +If your installed version of gcc doesn't work, you can tweak the steps: + +.. code-block:: bash + + $ ./tools/testing/kunit/kunit.py run --make_options=CC=/usr/bin/gcc-6 + $ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/ --gcov-tool=/usr/bin/gcov-6 + + +Running tests manually +====================== + +Running tests without using ``kunit.py run`` is also an important use case. +Currently it's your only option if you want to test on architectures other than +UML. + +As running the tests under UML is fairly straightforward (configure and compile +the kernel, run the ``./linux`` binary), this section will focus on testing +non-UML architectures. + + +Running built-in tests +---------------------- + +When setting tests to ``=y``, the tests will run as part of boot and print +results to dmesg in TAP format. So you just need to add your tests to your +``.config``, build and boot your kernel as normal. + +So if we compiled our kernel with: + +.. code-block:: none + + CONFIG_KUNIT=y + CONFIG_KUNIT_EXAMPLE_TEST=y + +Then we'd see output like this in dmesg signaling the test ran and passed: + +.. code-block:: none + + TAP version 14 + 1..1 + # Subtest: example + 1..1 + # example_simple_test: initializing + ok 1 - example_simple_test + ok 1 - example + +Running tests as modules +------------------------ + +Depending on the tests, you can build them as loadable modules. + +For example, we'd change the config options from before to + +.. code-block:: none + + CONFIG_KUNIT=y + CONFIG_KUNIT_EXAMPLE_TEST=m + +Then after booting into our kernel, we can run the test via + +.. code-block:: none + + $ modprobe kunit-example-test + +This will then cause it to print TAP output to stdout. + +.. note:: + The ``modprobe`` will *not* have a non-zero exit code if any test + failed (as of 5.13). But ``kunit.py parse`` would, see below. + +.. note:: + You can set ``CONFIG_KUNIT=m`` as well, however, some features will not + work and thus some tests might break. Ideally tests would specify they + depend on ``KUNIT=y`` in their ``Kconfig``'s, but this is an edge case + most test authors won't think about. + As of 5.13, the only difference is that ``current->kunit_test`` will + not exist. + +Pretty-printing results +----------------------- + +You can use ``kunit.py parse`` to parse dmesg for test output and print out +results in the same familiar format that ``kunit.py run`` does. + +.. code-block:: bash + + $ ./tools/testing/kunit/kunit.py parse /var/log/dmesg + + +Retrieving per suite results +---------------------------- + +Regardless of how you're running your tests, you can enable +``CONFIG_KUNIT_DEBUGFS`` to expose per-suite TAP-formatted results: + +.. code-block:: none + + CONFIG_KUNIT=y + CONFIG_KUNIT_EXAMPLE_TEST=m + CONFIG_KUNIT_DEBUGFS=y + +The results for each suite will be exposed under +``/sys/kernel/debug/kunit//results``. +So using our example config: + +.. code-block:: bash + + $ modprobe kunit-example-test > /dev/null + $ cat /sys/kernel/debug/kunit/example/results + ... ... + + # After removing the module, the corresponding files will go away + $ modprobe -r kunit-example-test + $ cat /sys/kernel/debug/kunit/example/results + /sys/kernel/debug/kunit/example/results: No such file or directory + +Generating code coverage reports +-------------------------------- + +See Documentation/dev-tools/gcov.rst for details on how to do this. + +The only vaguely KUnit-specific advice here is that you probably want to build +your tests as modules. That way you can isolate the coverage from tests from +other code executed during boot, e.g. + +.. code-block:: bash + + # Reset coverage counters before running the test. + $ echo 0 > /sys/kernel/debug/gcov/reset + $ modprobe kunit-example-test diff --git a/Documentation/dev-tools/kunit/start.rst b/Documentation/dev-tools/kunit/start.rst index 63ef7b625c13..1e00f9226f74 100644 --- a/Documentation/dev-tools/kunit/start.rst +++ b/Documentation/dev-tools/kunit/start.rst @@ -36,7 +36,7 @@ A good starting point for a ``.kunitconfig`` is the KUnit defconfig: .. code-block:: bash cd $PATH_TO_LINUX_REPO - cp arch/um/configs/kunit_defconfig .kunitconfig + cp tools/testing/kunit/configs/default.config .kunitconfig You can then add any other Kconfig options you wish, e.g.: @@ -236,5 +236,7 @@ Next Steps ========== * Check out the Documentation/dev-tools/kunit/tips.rst page for tips on writing idiomatic KUnit tests. +* Check out the :doc:`running_tips` page for tips on + how to make running KUnit tests easier. * Optional: see the :doc:`usage` page for a more in-depth explanation of KUnit. diff --git a/Documentation/dev-tools/kunit/usage.rst b/Documentation/dev-tools/kunit/usage.rst index 3ee7ab91f712..63f1bb89ebf5 100644 --- a/Documentation/dev-tools/kunit/usage.rst +++ b/Documentation/dev-tools/kunit/usage.rst @@ -467,10 +467,9 @@ fictitious example for ``sha1sum(1)`` .. code-block:: c - /* Note: the cast is to satisfy overly strict type-checking. */ #define TEST_SHA1(in, want) \ sha1sum(in, out); \ - KUNIT_EXPECT_STREQ_MSG(test, (char *)out, want, "sha1sum(%s)", in); + KUNIT_EXPECT_STREQ_MSG(test, out, want, "sha1sum(%s)", in); char out[40]; TEST_SHA1("hello world", "2aae6c35c94fcfb415dbe95f408b9ce91ee846ed"); @@ -509,7 +508,7 @@ In some cases, it can be helpful to write a *table-driven test* instead, e.g. }; for (i = 0; i < ARRAY_SIZE(cases); ++i) { sha1sum(cases[i].str, out); - KUNIT_EXPECT_STREQ_MSG(test, (char *)out, cases[i].sha1, + KUNIT_EXPECT_STREQ_MSG(test, out, cases[i].sha1, "sha1sum(%s)", cases[i].str); } @@ -570,7 +569,7 @@ Reusing the same ``cases`` array from above, we can write the test as a struct sha1_test_case *test_param = (struct sha1_test_case *)(test->param_value); sha1sum(test_param->str, out); - KUNIT_EXPECT_STREQ_MSG(test, (char *)out, test_param->sha1, + KUNIT_EXPECT_STREQ_MSG(test, out, test_param->sha1, "sha1sum(%s)", test_param->str); } @@ -611,17 +610,45 @@ non-UML architectures: None of these are reasons not to run your KUnit tests on real hardware; they are only things to be aware of when doing so. -The biggest impediment will likely be that certain KUnit features and -infrastructure may not support your target environment. For example, at this -time the KUnit Wrapper (``tools/testing/kunit/kunit.py``) does not work outside -of UML. Unfortunately, there is no way around this. Using UML (or even just a -particular architecture) allows us to make a lot of assumptions that make it -possible to do things which might otherwise be impossible. +Currently, the KUnit Wrapper (``tools/testing/kunit/kunit.py``) (aka +kunit_tool) only fully supports running tests inside of UML and QEMU; however, +this is only due to our own time limitations as humans working on KUnit. It is +entirely possible to support other emulators and even actual hardware, but for +now QEMU and UML is what is fully supported within the KUnit Wrapper. Again, to +be clear, this is just the Wrapper. The actualy KUnit tests and the KUnit +library they are written in is fully architecture agnostic and can be used in +virtually any setup, you just won't have the benefit of typing a single command +out of the box and having everything magically work perfectly. -Nevertheless, all core KUnit framework features are fully supported on all -architectures, and using them is straightforward: all you need to do is to take -your kunitconfig, your Kconfig options for the tests you would like to run, and -merge them into whatever config your are using for your platform. That's it! +Again, all core KUnit framework features are fully supported on all +architectures, and using them is straightforward: Most popular architectures +are supported directly in the KUnit Wrapper via QEMU. Currently, supported +architectures on QEMU include: + +* i386 +* x86_64 +* arm +* arm64 +* alpha +* powerpc +* riscv +* s390 +* sparc + +In order to run KUnit tests on one of these architectures via QEMU with the +KUnit wrapper, all you need to do is specify the flags ``--arch`` and +``--cross_compile`` when invoking the KUnit Wrapper. For example, we could run +the default KUnit tests on ARM in the following manner (assuming we have an ARM +toolchain installed): + +.. code-block:: bash + + tools/testing/kunit/kunit.py run --timeout=60 --jobs=12 --arch=arm --cross_compile=arm-linux-gnueabihf- + +Alternatively, if you want to run your tests on real hardware or in some other +emulation environment, all you need to do is to take your kunitconfig, your +Kconfig options for the tests you would like to run, and merge them into +whatever config your are using for your platform. That's it! For example, let's say you have the following kunitconfig: diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt deleted file mode 100644 index 5ab59da052df..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ /dev/null @@ -1,27 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) ----------------------------------------------------------- -Required properties - -- compatible : should be "amlogic,meson-gxbb-scpi" - -AMLOGIC SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "amlogic,meson-gxbb-sram" - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared - memory on Amlogic GXBB SoC. - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -SCPI provides an API to access the various sensors on the SoC. - -Required properties: -- compatible : should be "amlogic,meson-gxbb-scpi-sensors". - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt deleted file mode 100644 index 667d58e0a659..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ /dev/null @@ -1,239 +0,0 @@ -System Control and Management Interface (SCMI) Message Protocol ----------------------------------------------------------- - -The SCMI is intended to allow agents such as OSPM to manage various functions -that are provided by the hardware platform it is running on, including power -and performance functions. - -This binding is intended to define the interface the firmware implementing -the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control -and Management Interface Platform Design Document")[0] provide for OSPM in -the device tree. - -Required properties: - -The scmi node with the following properties shall be under the /firmware/ node. - -- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports -- mboxes: List of phandle and mailbox channel specifiers. It should contain - exactly one or two mailboxes, one for transmitting messages("tx") - and another optional for receiving the notifications("rx") if - supported. -- shmem : List of phandle pointing to the shared memory(SHM) area as per - generic mailbox client binding. -- #address-cells : should be '1' if the device has sub-nodes, maps to - protocol identifier for a given sub-node. -- #size-cells : should be '0' as 'reg' property doesn't have any size - associated with it. -- arm,smc-id : SMC id required when using smc or hvc transports - -Optional properties: - -- mbox-names: shall be "tx" or "rx" depending on mboxes entries. - -- interrupts : when using smc or hvc transports, this optional - property indicates that msg completion by the platform is indicated - by an interrupt rather than by the return of the smc call. This - should not be used except when the platform requires such behavior. - -- interrupt-names : if "interrupts" is present, interrupt-names must also - be present and have the value "a2p". - -See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details -about the generic mailbox controller and client driver bindings. - -The mailbox is the only permitted method of calling the SCMI firmware. -Mailbox doorbell is used as a mechanism to alert the presence of a -messages and/or notification. - -Each protocol supported shall have a sub-node with corresponding compatible -as described in the following sections. If the platform supports dedicated -communication channel for a particular protocol, the 3 properties namely: -mboxes, mbox-names and shmem shall be present in the sub-node corresponding -to that protocol. - -Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Required properties: -- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. - -Power domain bindings for the power domains based on SCMI Message Protocol ------------------------------------------------------------- - -This binding for the SCMI power domain providers uses the generic power -domain binding[2]. - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCMI commands. - -Regulator bindings for the SCMI Regulator based on SCMI Message Protocol ------------------------------------------------------------- -An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain, -and should be always positioned as a root regulator. -It does not support any current operation. - -SCMI Regulators are grouped under a 'regulators' node which in turn is a child -of the SCMI Voltage protocol node inside the desired SCMI instance node. - -This binding uses the common regulator binding[6]. - -Required properties: - - reg : shall identify an existent SCMI Voltage Domain. - -Sensor bindings for the sensors based on SCMI Message Protocol --------------------------------------------------------------- -SCMI provides an API to access the various sensors on the SoC. - -Required properties: -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[3]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -Reset signal bindings for the reset domains based on SCMI Message Protocol ------------------------------------------------------------- - -This binding for the SCMI reset domain providers uses the generic reset -signal binding[5]. - -Required properties: - - #reset-cells : Should be 1. Contains the reset domain ID value used - by SCMI commands. - -SRAM and Shared Memory for SCMI -------------------------------- - -A small area of SRAM is reserved for SCMI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [4] - -Each sub-node represents the reserved area for SCMI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based - shared memory - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/thermal/thermal*.yaml -[4] Documentation/devicetree/bindings/sram/sram.yaml -[5] Documentation/devicetree/bindings/reset/reset.txt -[6] Documentation/devicetree/bindings/regulator/regulator.yaml - -Example: - -sram@50000000 { - compatible = "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,scmi-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox@40000000 { - .... - #mbox-cells = <1>; - reg = <0x0 0x40000000 0x0 0x10000>; -}; - -firmware { - - ... - - scmi { - compatible = "arm,scmi"; - mboxes = <&mailbox 0 &mailbox 1>; - mbox-names = "tx", "rx"; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_dvfs: protocol@13 { - reg = <0x13>; - #clock-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_sensors0: protocol@15 { - reg = <0x15>; - #thermal-sensor-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - - scmi_voltage: protocol@17 { - reg = <0x17>; - - regulators { - regulator_devX: regulator@0 { - reg = <0x0>; - regulator-max-microvolt = <3300000>; - }; - - regulator_devY: regulator@9 { - reg = <0x9>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <4200000>; - }; - - ... - }; - }; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scmi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scmi_clk 4>; - power-domains = <&scmi_devpd 1>; - resets = <&scmi_reset 10>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - /* sensor ID */ - thermal-sensors = <&scmi_sensors0 3>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt deleted file mode 100644 index bcd6c3ec471e..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ /dev/null @@ -1,219 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol ----------------------------------------------------------- - -Firmware implementing the SCPI described in ARM document number ARM DUI 0922B -("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used -by Linux to initiate various system control and power operations. - -Required properties: - -- compatible : should be - * "arm,scpi" : For implementations complying to SCPI v1.0 or above - * "arm,scpi-pre-1.0" : For implementations complying to all - unversioned releases prior to SCPI v1.0 -- mboxes: List of phandle and mailbox channel specifiers - All the channels reserved by remote SCP firmware for use by - SCPI message protocol should be specified in any order -- shmem : List of phandle pointing to the shared memory(SHM) area between the - processors using these mailboxes for IPC, one for each mailbox - SHM can be any memory reserved for the purpose of this communication - between the processors. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt -for more details about the generic mailbox controller and -client driver bindings. - -Clock bindings for the clocks based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Container Node -============== -Required properties: -- compatible : should be "arm,scpi-clocks" - All the clocks provided by SCP firmware via SCPI message - protocol much be listed as sub-nodes under this node. - -Sub-nodes -========= -Required properties: -- compatible : shall include one of the following - "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based. - These clocks don't provide an entire range of values between the - limits but only discrete points within the range. The firmware - provides the mapping for each such operating frequency and the - index associated with it. The firmware also manages the - voltage scaling appropriately with the clock scaling. - "arm,scpi-variable-clocks" - all the clocks that are variable and provide full - range within the specified range. The firmware provides the - range of values within a specified range. - -Other required properties for all clocks(all from common clock binding): -- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands. -- clock-output-names : shall be the corresponding names of the outputs. -- clock-indices: The identifying number for the clocks(i.e.clock_id) in the - node. It can be non linear and hence provide the mapping of identifiers - into the clock-output-names array. - -SRAM and Shared Memory for SCPI -------------------------------- - -A small area of SRAM is reserved for SCPI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [3] - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scp-shmem" for Non-secure SRAM based - shared memory - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -SCPI provides an API to access the various sensors on the SoC. - -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[2]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -Power domain bindings for the power domains based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the generic power domain binding[4]. - -PM domain providers -=================== - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCPI commands. - - num-domains: Total number of power domains provided by SCPI. This is - needed as the SCPI message protocol lacks a mechanism to - query this information at runtime. - -PM domain consumers -=================== - -Required properties: - - power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/thermal/thermal*.yaml -[3] Documentation/devicetree/bindings/sram/sram.yaml -[4] Documentation/devicetree/bindings/power/power-domain.yaml - -Example: - -sram: sram@50000000 { - compatible = "arm,juno-sram-ns", "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,juno-scp-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,juno-scp-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox: mailbox0@40000000 { - .... - #mbox-cells = <1>; -}; - -scpi_protocol: scpi@2e000000 { - compatible = "arm,scpi"; - mboxes = <&mailbox 0 &mailbox 1>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "atlclk", "aplclk","gpuclk"; - }; - scpi_clk: scpi_clocks@3 { - compatible = "arm,scpi-variable-clocks"; - #clock-cells = <1>; - clock-indices = <3>, <4>; - clock-output-names = "pxlclk0", "pxlclk1"; - }; - }; - - scpi_sensors0: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - - scpi_devpd: scpi-power-domains { - compatible = "arm,scpi-power-domains"; - num-domains = <2>; - #power-domain-cells = <1>; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scpi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scpi_clk 4>; - power-domains = <&scpi_devpd 1>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - /* sensor ID */ - thermal-sensors = <&scpi_sensors0 3>; - ... - }; -}; - -In the above example, the #clock-cells is set to 1 as required. -scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0, -1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 -and pxlclk1 with 3 and 4 as clock-indices. - -The first consumer in the example is cpu@0 and it has '0' as the clock -specifier which points to the first entry in the output clocks of -scpi_dvfs i.e. "atlclk". - -Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input -clock. '4' in the clock specifier here points to the second entry -in the output clocks of scpi_clocks i.e. "pxlclk1" - -The thermal-sensors property in the soc_thermal node uses the -temperature sensor provided by SCP firmware to setup a thermal -zone. The ID "3" is the sensor identifier for the temperature sensor -as used by the firmware. - -The num-domains property in scpi-power-domains domain specifies that -SCPI provides 2 power domains. The hdlcd node uses the power domain with -domain ID 1. diff --git a/Documentation/devicetree/bindings/arm/arm,scu.yaml b/Documentation/devicetree/bindings/arm/arm,scu.yaml new file mode 100644 index 000000000000..dae2aa27e641 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,scu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Snoop Control Unit (SCU) + +maintainers: + - Linus Walleij + +description: | + As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided + with a Snoop Control Unit. The register range is usually 256 (0x100) + bytes. + + References: + - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual + Revision r2p0 + - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual + Revision r0p1 + - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference + Manial Revision r2p0 + +properties: + compatible: + enum: + - arm,cortex-a9-scu + - arm,cortex-a5-scu + - arm,arm11mp-scu + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt deleted file mode 100644 index d38834c67dff..000000000000 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt +++ /dev/null @@ -1,31 +0,0 @@ -OP-TEE Device Tree Bindings - -OP-TEE is a piece of software using hardware features to provide a Trusted -Execution Environment. The security can be provided with ARM TrustZone, but -also by virtualization or a separate chip. - -We're using "linaro" as the first part of the compatible property for -the reference implementation maintained by Linaro. - -* OP-TEE based on ARM TrustZone required properties: - -- compatible : should contain "linaro,optee-tz" - -- method : The method of calling the OP-TEE Trusted OS. Permitted - values are: - - "smc" : SMC #0, with the register assignments specified - in drivers/tee/optee/optee_smc.h - - "hvc" : HVC #0, with the register assignments specified - in drivers/tee/optee/optee_smc.h - - - -Example: - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml new file mode 100644 index 000000000000..c24047c1fdd5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OP-TEE Device Tree Bindings + +maintainers: + - Jens Wiklander + +description: | + OP-TEE is a piece of software using hardware features to provide a Trusted + Execution Environment. The security can be provided with ARM TrustZone, but + also by virtualization or a separate chip. + + We're using "linaro" as the first part of the compatible property for + the reference implementation maintained by Linaro. + +properties: + $nodename: + const: optee + + compatible: + const: linaro,optee-tz + + method: + enum: [smc, hvc] + description: | + The method of calling the OP-TEE Trusted OS depending on smc or hvc + instruction usage. + SMC #0, register assignments + or + HVC #0, register assignments + register assignments are specified in drivers/tee/optee/optee_smc.h + +required: + - compatible + - method + +additionalProperties: false + +examples: + - | + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + - | + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "hvc"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 395359dc94fd..fd0061712443 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -86,13 +86,11 @@ This binding uses the common clock binding[1]. Required properties: - compatible: Should be one of: - "fsl,imx8qm-clock" - "fsl,imx8qxp-clock" + "fsl,imx8qm-clk" + "fsl,imx8qxp-clk" followed by "fsl,scu-clk" -- #clock-cells: Should be either - 2: Contains the Resource and Clock ID value. - or - 1: Contains the Clock ID value. (DEPRECATED) +- #clock-cells: Should be 2. + Contains the Resource and Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml index 69cd30872928..107e686ab207 100644 --- a/Documentation/devicetree/bindings/arm/intel,keembay.yaml +++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml @@ -11,6 +11,8 @@ maintainers: - Daniele Alessandrelli properties: + $nodename: + const: '/' compatible: items: - enum: diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt deleted file mode 100644 index 2ace8696bbee..000000000000 --- a/Documentation/devicetree/bindings/arm/juno,scpi.txt +++ /dev/null @@ -1,26 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) - -Juno SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. - For Juno R0 and Juno R1 refer to [1] for the - sensor identifiers - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt -[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt deleted file mode 100644 index 6f0cd31c1520..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt +++ /dev/null @@ -1,86 +0,0 @@ -Texas Instruments System Control Interface (TI-SCI) Message Protocol --------------------------------------------------------------------- - -Texas Instrument's processors including those belonging to Keystone generation -of processors have separate hardware entity which is now responsible for the -management of the System on Chip (SoC) system. These include various system -level functions as well. - -An example of such an SoC is K2G, which contains the system control hardware -block called Power Management Micro Controller (PMMC). This hardware block is -initialized early into boot process and provides services to Operating Systems -on multiple processors including ones running Linux. - -See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. - -TI-SCI controller Device Node: -============================= - -The TI-SCI node describes the Texas Instrument's System Controller entity node. -This parent node may optionally have additional children nodes which describe -specific functionality such as clocks, power domain, reset or additional -functionality as may be required for the SoC. This hierarchy also describes the -relationship between the TI-SCI parent node to the child node. - -Required properties: -------------------- -- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC - should be "ti,am654-sci" for for TI AM654 SoC -- mbox-names: - "rx" - Mailbox corresponding to receive path - "tx" - Mailbox corresponding to transmit path - -- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes - property should contain a phandle to the mailbox controller device - node and an args specifier that will be the phandle to the intended - sub-mailbox child node to be used for communication. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details -about the generic mailbox controller and client driver bindings. Also see -Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical -controller that is used to communicate with this System controllers. - -Optional Properties: -------------------- -- reg-names: - debug_messages - Map the Debug message region -- reg: register space corresponding to the debug_messages -- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot -- ti,host-id: Integer value corresponding to the host ID assigned by Firmware - for identification of host processing entities such as virtual - machines - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - ti,host-id = <2>; - mbox-names = "rx", "tx"; - mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>, - <&msgmgr &msgmgr_proxy_pmmc_tx>; - reg-names = "debug_messages"; - reg = <0x02921800 0x800>; - }; - - -TI-SCI Client Device Node: -========================= - -Client nodes are maintained as children of the relevant TI-SCI device node. - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - ... - - my_clk_node: clk_node { - ... - ... - }; - - my_pd_node: pd_node { - ... - ... - }; - }; diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml new file mode 100644 index 000000000000..34f5f877d444 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI controller device node bindings + +maintainers: + - Nishanth Menon + +description: | + Texas Instrument's processors including those belonging to Keystone generation + of processors have separate hardware entity which is now responsible for the + management of the System on Chip (SoC) system. These include various system + level functions as well. + + An example of such an SoC is K2G, which contains the system control hardware + block called Power Management Micro Controller (PMMC). This hardware block is + initialized early into boot process and provides services to Operating Systems + on multiple processors including ones running Linux. + + See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. + + The TI-SCI node describes the Texas Instrument's System Controller entity node. + This parent node may optionally have additional children nodes which describe + specific functionality such as clocks, power domain, reset or additional + functionality as may be required for the SoC. This hierarchy also describes the + relationship between the TI-SCI parent node to the child node. + +properties: + $nodename: + pattern: "^system-controller@[0-9a-f]+$" + + compatible: + oneOf: + - description: System controller on TI 66AK2G SoC and other K3 SoCs + items: + - const: ti,k2g-sci + - description: System controller on TI AM654 SoC + items: + - const: ti,am654-sci + + reg-names: + description: | + Specifies the debug messages memory mapped region that is optionally + made available from TI-SCI controller. + const: debug_messages + + reg: + minItems: 1 + + mbox-names: + description: | + Specifies the mailboxes used to communicate with TI-SCI Controller + made available from TI-SCI controller. + items: + - const: rx + - const: tx + + mboxes: + minItems: 2 + + ti,system-reboot-controller: + description: Determines If system reboot can be triggered by SoC reboot + type: boolean + + ti,host-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Value corresponding to the host ID assigned by Firmware + for identification of host processing entities such as virtual machines. + + power-controller: + type: object + $ref: /schemas/soc/ti/sci-pm-domain.yaml# + + clock-controller: + type: object + $ref: /schemas/clock/ti,sci-clk.yaml# + + reset-controller: + type: object + $ref: /schemas/reset/ti,sci-reset.yaml# + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + pmmc: system-controller@2921800 { + compatible = "ti,k2g-sci"; + ti,system-reboot-controller; + mbox-names = "rx", "tx"; + mboxes= <&msgmgr 5 2>, + <&msgmgr 0 0>; + reg-names = "debug_messages"; + reg = <0x02921800 0x800>; + }; + + - | + dmsc: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x44083000 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt deleted file mode 100644 index 74d0a780ce51..000000000000 --- a/Documentation/devicetree/bindings/arm/scu.txt +++ /dev/null @@ -1,28 +0,0 @@ -* ARM Snoop Control Unit (SCU) - -As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided -with a Snoop Control Unit. The register range is usually 256 (0x100) -bytes. - -References: - -- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual - Revision r2p0 -- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual - Revision r0p1 -- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference - Manial Revision r2p0 - -- compatible : Should be: - "arm,cortex-a9-scu" - "arm,cortex-a5-scu" - "arm,arm11mp-scu" - -- reg : Specify the base address and the size of the SCU register window. - -Example: - -scu@a0410000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; -}; diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt index 89408de55bfd..18d55532d31e 100644 --- a/Documentation/devicetree/bindings/arm/ux500/boards.txt +++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt @@ -20,13 +20,13 @@ during retention, system won't boot without this): compatible = "ste,dbx500-backupram" scu: - see binding for arm/scu.txt + see binding for arm/arm,scu.yaml interrupt-controller: see binding for interrupt-controller/arm,gic.txt timer: - see binding for timer/arm,twd.txt + see binding for timer/arm,twd-timer.yaml clocks: see binding for clocks/ux500.txt diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml index a75e9a8f539a..3c7a2425f3e6 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml @@ -20,7 +20,6 @@ properties: reg: minItems: 2 - maxItems: 3 items: - description: AHCI registers - description: SATA configuration and IPFS registers diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml index d06096a7ba4b..c060c7914cae 100644 --- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -53,6 +53,17 @@ required: - reg - interrupts - clocks + - power-domains + +if: + not: + properties: + compatible: + contains: + const: renesas,sata-r8a7779 +then: + required: + - resets additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index a27025cd3909..c4b7243ddcf2 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -51,7 +51,6 @@ properties: clocks: minItems: 2 - maxItems: 4 items: - description: High Frequency Oscillator (usually at 24MHz) - description: Low Frequency Oscillator (usually at 32kHz) @@ -60,7 +59,6 @@ properties: clock-names: minItems: 2 - maxItems: 4 items: - const: hosc - const: losc diff --git a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt b/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt deleted file mode 100644 index 2be1e038ca62..000000000000 --- a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt +++ /dev/null @@ -1,19 +0,0 @@ -Binding for simple gpio clock multiplexer. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-mux-clock". -- clocks: list of two references to parent clocks. -- #clock-cells : from common clock binding; shall be set to 0. -- select-gpios : GPIO reference for selecting the parent clock. - -Example: - clock { - compatible = "gpio-mux-clock"; - clocks = <&parentclk1>, <&parentclk2>; - #clock-cells = <0>; - select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml new file mode 100644 index 000000000000..1e21f8b3a4ff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple GPIO clock multiplexer + +maintainers: + - Sergej Sawazki + +properties: + compatible: + const: gpio-mux-clock + + clocks: + items: + - description: First parent clock + - description: Second parent clock + + '#clock-cells': + const: 0 + + select-gpios: + description: GPIO reference for selecting the parent clock. + maxItems: 1 + +required: + - compatible + - clocks + - '#clock-cells' + - select-gpios + +additionalProperties: false + +examples: + - | + #include + + clock { + compatible = "gpio-mux-clock"; + clocks = <&parentclk1>, <&parentclk2>; + #clock-cells = <0>; + select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml b/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml new file mode 100644 index 000000000000..3ceb29cec704 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon SOC Clock for HI3559AV100 + +maintainers: + - Dongjiu Geng + +description: | + Hisilicon SOC clock control module which supports the clocks, resets and + power domains on HI3559AV100. + + See also: + dt-bindings/clock/hi3559av100-clock.h + +properties: + compatible: + enum: + - hisilicon,hi3559av100-clock + - hisilicon,hi3559av100-shub-clock + + reg: + minItems: 1 + maxItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 2 + description: | + First cell is reset request register offset. + Second cell is bit offset in reset request register. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@12010000 { + compatible = "hisilicon,hi3559av100-clock"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x0 0x12010000 0x0 0x10000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 28675b0b80f1..26ed040bc717 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -84,6 +84,7 @@ patternProperties: idt,slew-percent: description: The Slew rate control for CMOS single-ended. enum: [ 80, 85, 90, 100 ] + additionalProperties: false required: - compatible @@ -139,13 +140,13 @@ examples: clock-names = "xin"; OUT1 { - idt,drive-mode = ; - idt,voltage-microvolts = <1800000>; + idt,mode = ; + idt,voltage-microvolt = <1800000>; idt,slew-percent = <80>; }; OUT4 { - idt,drive-mode = ; + idt,mode = ; }; }; }; diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index c65b9458c0b6..6e80dbc8b8b9 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -22,6 +22,8 @@ select: enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4760-cgu + - ingenic,jz4760b-cgu - ingenic,jz4770-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu @@ -49,6 +51,8 @@ properties: - enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4760-cgu + - ingenic,jz4760b-cgu - ingenic,jz4770-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu @@ -93,6 +97,8 @@ required: patternProperties: "^usb-phy@[a-f0-9]+$": allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ] + "^mac-phy-ctrl@[a-f0-9]+$": + allOf: [ $ref: "../net/ingenic,mac.yaml#" ] additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml new file mode 100644 index 000000000000..9f239c3960d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SM8250 + +maintainers: + - Jonathan Marek + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SM8250. + + See also dt-bindings/clock/qcom,camcc-sm8250.h + +properties: + compatible: + const: qcom,sm8250-camcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..6667261dc665 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index eacccc88bbf6..8e2eac6cbfb9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -46,7 +46,6 @@ properties: nvmem-cell-names: minItems: 1 - maxItems: 2 items: - const: calib - const: calib_backup diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml index 1121b3934cb9..b0d1c65aa354 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -27,7 +27,6 @@ properties: - description: Sleep clock source - description: PLL test clock source (Optional clock) minItems: 2 - maxItems: 3 clock-names: items: @@ -35,7 +34,6 @@ properties: - const: sleep_clk - const: core_bi_pll_test_se # Optional clock minItems: 2 - maxItems: 3 '#clock-cells': const: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml new file mode 100644 index 000000000000..ab12b391effc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM6125. + + See also: + - dt-bindings/clock/qcom,gcc-sm6125.h + +properties: + compatible: + const: qcom,gcc-sm6125 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@1400000 { + compatible = "qcom,gcc-sm6125"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml index 78f35832aa41..1122700dcc2b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -36,7 +36,6 @@ properties: - description: USB3 phy wrapper pipe clock source (Optional clock) - description: USB3 phy sec pipe clock source (Optional clock) minItems: 2 - maxItems: 13 clock-names: items: @@ -54,7 +53,6 @@ properties: - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock minItems: 2 - maxItems: 13 '#clock-cells': const: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 490edad25830..8453eeddf30e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -26,9 +26,10 @@ description: | - dt-bindings/reset/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8660.h - dt-bindings/reset/qcom,gcc-msm8660.h - - dt-bindings/clock/qcom,gcc-msm8974.h - - dt-bindings/reset/qcom,gcc-msm8974.h + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/clock/qcom,gcc-msm8994.h + - dt-bindings/clock/qcom,gcc-mdm9607.h - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) @@ -40,6 +41,8 @@ properties: - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-ipq8064 + - qcom,gcc-mdm9607 + - qcom,gcc-msm8226 - qcom,gcc-msm8660 - qcom,gcc-msm8916 - qcom,gcc-msm8939 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index b44a0622fb3a..6cf5a7ec2b4c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -12,6 +12,7 @@ Required properties : "qcom,rpmcc-msm8660", "qcom,rpmcc" "qcom,rpmcc-apq8060", "qcom,rpmcc" + "qcom,rpmcc-msm8226", "qcom,rpmcc" "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8936", "qcom,rpmcc" "qcom,rpmcc-msm8974", "qcom,rpmcc" diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt deleted file mode 100644 index 268ca615459e..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree Clock bindings for Renesas EMMA Mobile EV2 - -This binding uses the common clock binding. - -* SMU -System Management Unit described in user's manual R19UH0037EJ1000_SMU. -This is not a clock provider, but clocks under SMU depend on it. - -Required properties: -- compatible: Should be "renesas,emev2-smu" -- reg: Address and Size of SMU registers - -* SMU_CLKDIV -Function block with an input mux and a divider, which corresponds to -"Serial clock generator" in fig."Clock System Overview" of the manual, -and "xxx frequency division setting register" (XXXCLKDIV) registers. -This makes internal (neither input nor output) clock that is provided -to input of xxxGCLK block. - -Required properties: -- compatible: Should be "renesas,emev2-smu-clkdiv" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Parent clocks. Input clocks as described in clock-bindings.txt -- #clock-cells: Should be <0> - -* SMU_GCLK -Clock gating node shown as "Clock stop processing block" in the -fig."Clock System Overview" of the manual. -Registers are "xxx clock gate control register" (XXXGCLKCTRL). - -Required properties: -- compatible: Should be "renesas,emev2-smu-gclk" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Input clock as described in clock-bindings.txt -- #clock-cells: Should be <0> - -Example of provider: - -usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>; - #clock-cells = <0>; -}; - -usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; -}; - -Example of consumer: - -serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = <0 8 0>; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; -}; - -Example of clock-tree description: - - This describes a clock path in the clock tree - c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk - -smu@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml new file mode 100644 index 000000000000..4d9a64800481 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile EV2 System Management Unit + +maintainers: + - Geert Uytterhoeven + - Magnus Damm + +description: | + The System Management Unit is described in user's manual R19UH0037EJ1000_SMU. + This is not a clock provider, but clocks under SMU depend on it. + +properties: + compatible: + const: renesas,emev2-smu + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +patternProperties: + ".*sclkdiv@.*": + type: object + + description: | + Function block with an input mux and a divider, which corresponds to + "Serial clock generator" in fig. "Clock System Overview" of the manual, + and "xxx frequency division setting register" (XXXCLKDIV) registers. + This makes internal (neither input nor output) clock that is provided + to input of xxxGCLK block. + + properties: + compatible: + const: renesas,emev2-smu-clkdiv + + reg: + maxItems: 1 + description: + Byte offset from SMU base and Bit position in the register. + + clocks: + minItems: 1 + maxItems: 4 + + '#clock-cells': + const: 0 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + + additionalProperties: false + + ".*sclk@.*": + type: object + + description: | + Clock gating node shown as "Clock stop processing block" in the + fig. "Clock System Overview" of the manual. + Registers are "xxx clock gate control register" (XXXGCLKCTRL). + + properties: + compatible: + const: renesas,emev2-smu-gclk + + reg: + maxItems: 1 + description: + Byte offset from SMU base and Bit position in the register. + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + + additionalProperties: false + +additionalProperties: true + +examples: + - | + // Example of clock-tree description: + // + // This describes a clock path in the clock tree + // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk + clocks@e0110000 { + compatible = "renesas,emev2-smu"; + reg = <0xe0110000 0x10000>; + #address-cells = <2>; + #size-cells = <0>; + + c32ki: c32ki { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; + clock-div = <1>; + clock-mult = <7000>; + #clock-cells = <0>; + }; + usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x610 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usia_u0_sclk: usia_u0_sclk@4a0,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4a0 1>; + clocks = <&usia_u0_sclkdiv>; + #clock-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt deleted file mode 100644 index aed713cf0831..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Renesas R9A06G032 SYSCTRL - -Required Properties: - - - compatible: Must be: - - "renesas,r9a06g032-sysctrl" - - reg: Base address and length of the SYSCTRL IO block. - - #clock-cells: Must be 1 - - clocks: References to the parent clocks: - - external 40mhz crystal. - - external (optional) 32.768khz - - external (optional) jtag input - - external (optional) RGMII_REFCLK - - clock-names: Must be: - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - - #power-domain-cells: Must be 0 - -Examples --------- - - - SYSCTRL node: - - sysctrl: system-controller@4000c000 { - compatible = "renesas,r9a06g032-sysctrl"; - reg = <0x4000c000 0x1000>; - #clock-cells = <1>; - - clocks = <&ext_mclk>, <&ext_rtc_clk>, - <&ext_jtag_clk>, <&ext_rgmii_ref>; - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - #power-domain-cells = <0>; - }; - - - Other nodes can use the clocks provided by SYSCTRL as in: - - #include - uart0: serial@40060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40060000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - power-domains = <&sysctrl>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml new file mode 100644 index 000000000000..25dbb0fac065 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1D (R9A06G032) System Controller + +maintainers: + - Gareth Williams + - Geert Uytterhoeven + +properties: + compatible: + const: renesas,r9a06g032-sysctrl + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: External 40 MHz crystal + - description: Optional external 32.768 kHz crystal + - description: Optional external JTAG input + - description: Optional external RGMII_REFCLK + + clock-names: + minItems: 1 + items: + - const: mclk + - const: rtc + - const: jtag + - const: rgmii_ref_ext + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, + <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml new file mode 100644 index 000000000000..30b2e3d0d25d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode + +maintainers: + - Geert Uytterhoeven + +description: | + On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module + Standby Mode share the same register block. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The Module Standby Mode block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + const: renesas,r9a07g044-cpg # RZ/G2{L,LC} + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: + Clock source to CPG can be either from external clock input (EXCLK) or + crystal oscillator (XIN/XOUT). + const: extal + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in the . + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/Module Standby Mode Clock Domain and + can be power-managed through Module Standby should refer to the CPG device + node in their "power-domains" property, as documented by the generic PM + Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + the . + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0x11010000 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.txt b/Documentation/devicetree/bindings/clock/silabs,si5341.txt index 504cce3abe46..ce55aba0ce22 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5341.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.txt @@ -24,9 +24,8 @@ it. The device type, speed grade and revision are determined runtime by probing. -The driver currently only supports XTAL input mode, and does not support any -fancy input configurations. They can still be programmed into the chip and -the driver will leave them "as is". +The driver currently does not support any fancy input configurations. They can +still be programmed into the chip and the driver will leave them "as is". ==I2C device node== @@ -45,9 +44,9 @@ Required properties: corresponding to inputs. Use a fixed clock for the "xtal" input. At least one must be present. - clock-names: One of: "xtal", "in0", "in1", "in2" -- vdd-supply: Regulator node for VDD Optional properties: +- vdd-supply: Regulator node for VDD - vdda-supply: Regulator node for VDDA - vdds-supply: Regulator node for VDDS - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL @@ -60,7 +59,14 @@ Optional properties: be initialized, and always performs the soft-reset routine. Since this will temporarily stop all output clocks, don't do this if the chip is generating the CPU clock for example. +- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used + in EXTCLK (external reference clock) rather than XTAL (crystal) mode. - interrupts: Interrupt for INTRb pin. +- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V + rather than 1.8V thresholds. +- vddoX-supply (where X is an output index): Regulator node for VDDO for the + specified output. The driver selects the output VDD_SEL setting based on this + voltage. - #address-cells: shall be set to 1. - #size-cells: shall be set to 0. @@ -77,8 +83,6 @@ Required child node properties: - reg: number of clock output. Optional child node properties: -- vdd-supply: Regulator node for VDD for this output. The driver selects default - values for common-mode and amplitude based on the voltage. - silabs,format: Output format, one of: 1 = differential (defaults to LVDS levels) 2 = low-power (defaults to HCSL levels) diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml index 4069e09cb62d..47e1ab08c95d 100644 --- a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -40,7 +40,6 @@ properties: clock-names: minItems: 1 - maxItems: 4 items: - const: ext-26m - const: ext-32k diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 4e385508f516..8b1ecb2ecdd5 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -54,7 +54,9 @@ properties: compatible: items: - - const: st,stm32mp1-rcc + - enum: + - st,stm32mp1-rcc-secure + - st,stm32mp1-rcc - const: syscon reg: @@ -71,7 +73,7 @@ additionalProperties: false examples: - | rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; + compatible = "st,stm32mp1-rcc-secure", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml index 6b419a9878f3..9b537bc876b5 100644 --- a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -12,7 +12,9 @@ maintainers: properties: compatible: items: - - const: ti,am654-ehrpwm-tbclk + - enum: + - ti,am654-ehrpwm-tbclk + - ti,am64-epwm-tbclk - const: syscon "#clock-cells": diff --git a/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml b/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml new file mode 100644 index 000000000000..bd8173848253 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml @@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for the Texas Instruments LMK04832 + +maintainers: + - Liam Beguin + +description: | + Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B + support. The LMK04832 is pin compatible with the LMK0482x family. + + Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf + +properties: + compatible: + enum: + - ti,lmk04832 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#clock-cells': + const: 1 + + spi-max-frequency: + maximum: 5000000 + + clocks: + items: + - description: PLL2 reference clock. + + clock-names: + items: + - const: oscin + + reset-gpios: + maxItems: 1 + + ti,spi-4wire-rdbk: + description: | + Select SPI 4wire readback pin configuration. + Available readback pins are, + CLKin_SEL0 0 + CLKin_SEL1 1 + RESET 2 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + ti,vco-hz: + description: Optional to set VCO frequency of the PLL in Hertz. + + ti,sysref-ddly: + description: SYSREF digital delay value. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 8191 + default: 8 + + ti,sysref-mux: + description: | + SYSREF Mux configuration. + Available options are, + Normal SYNC 0 + Re-clocked 1 + SYSREF Pulser 2 + SYSREF Continuous 3 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 3 + + ti,sync-mode: + description: SYNC pin configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + ti,sysref-pulse-count: + description: + Number of SYSREF pulses to send when SYSREF is not in continuous mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + default: 4 + +patternProperties: + "@[0-9a-d]+$": + type: object + description: + Child nodes used to configure output clocks. + + properties: + reg: + description: + clock output identifier. + minimum: 0 + maximum: 13 + + ti,clkout-fmt: + description: + Clock output format. + Available options are, + Powerdown 0x00 + LVDS 0x01 + HSDS 6 mA 0x02 + HSDS 8 mA 0x03 + LVPECL 1600 mV 0x04 + LVPECL 2000 mV 0x05 + LCPECL 0x06 + CML 16 mA 0x07 + CML 24 mA 0x08 + CML 32 mA 0x09 + CMOS (Off/Inverted) 0x0a + CMOS (Normal/Off) 0x0b + CMOS (Inverted/Inverted) 0x0c + CMOS (Inverted/Normal) 0x0d + CMOS (Normal/Inverted) 0x0e + CMOS (Normal/Normal) 0x0f + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + ti,clkout-sysref: + description: + Select SYSREF clock path for output clock. + type: boolean + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clocks { + lmk04832_oscin: oscin { + compatible = "fixed-clock"; + + #clock-cells = <0>; + clock-frequency = <122880000>; + clock-output-names = "lmk04832-oscin"; + }; + }; + + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + lmk04832: clock-controller@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + compatible = "ti,lmk04832"; + spi-max-frequency = <781250>; + + reset-gpios = <&gpio_lmk 0 0 0>; + + #clock-cells = <1>; + clocks = <&lmk04832_oscin>; + clock-names = "oscin"; + + ti,spi-4wire-rdbk = <0>; + ti,vco-hz = <2457600000>; + + assigned-clocks = + <&lmk04832 0>, <&lmk04832 1>, + <&lmk04832 2>, <&lmk04832 3>, + <&lmk04832 4>, + <&lmk04832 6>, <&lmk04832 7>, + <&lmk04832 10>, <&lmk04832 11>; + assigned-clock-rates = + <122880000>, <384000>, + <122880000>, <384000>, + <122880000>, + <153600000>, <384000>, + <614400000>, <384000>; + + clkout0@0 { + reg = <0>; + ti,clkout-fmt = <0x01>; // LVDS + }; + + clkout1@1 { + reg = <1>; + ti,clkout-fmt = <0x01>; // LVDS + ti,clkout-sysref; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt deleted file mode 100644 index 4e59dc6b1778..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt +++ /dev/null @@ -1,36 +0,0 @@ -Texas Instruments TI-SCI Clocks -=============================== - -All clocks on Texas Instruments' SoCs that contain a System Controller, -are only controlled by this entity. Communication between a host processor -running an OS and the System Controller happens through a protocol known -as TI-SCI[1]. This clock implementation plugs into the common clock -framework and makes use of the TI-SCI protocol on clock API requests. - -[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -Required properties: -------------------- -- compatible: Must be "ti,k2g-sci-clk" -- #clock-cells: Shall be 2. - In clock consumers, this cell represents the device ID and clock ID - exposed by the PM firmware. The list of valid values for the device IDs - and clocks IDs for 66AK2G SoC are documented at - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Examples: --------- - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; -}; - -uart0: serial@2530c00 { - compatible = "ns16550a"; - clocks = <&k2g_clks 0x2c 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml new file mode 100644 index 000000000000..0e370289a053 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI clock controller node bindings + +maintainers: + - Nishanth Menon + +description: | + Some TI SoCs contain a system controller (like the Power Management Micro + Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling + the state of the various hardware modules present on the SoC. Communication + between the host processor running an OS and the system controller happens + through a protocol called TI System Control Interface (TI-SCI protocol). + + This clock controller node uses the TI SCI protocol to perform various clock + management of various hardware modules (devices) present on the SoC. This + node must be a child node of the associated TI-SCI system controller node. + +properties: + $nodename: + pattern: "^clock-controller$" + + compatible: + const: ti,k2g-sci-clk + + "#clock-cells": + const: 2 + description: + The two cells represent values that the TI-SCI controller defines. + + The first cell should contain the device ID. + + The second cell should contain the clock ID. + + Please see http://processors.wiki.ti.com/index.php/TISCI for + protocol documentation for the values to be used for different devices. + +additionalProperties: false + +examples: + - | + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index df57009ff8e7..37a7cb6ad07d 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -42,6 +42,11 @@ Required properties: "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) + "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains + the frequency spreading register base address (optional) + "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains + the modulation frequency register base address + (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers @@ -51,6 +56,14 @@ Optional properties: - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate + - ti,min-div : the minimum divisor to start from to round the DPLL + target rate + - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency + spreading in permille (10th of a percent) + - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread + spectrum modulation frequency + - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean + to enable the downspread feature Examples: dpll_core_ck: dpll_core_ck@44e00490 { @@ -83,3 +96,10 @@ Examples: clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml index 6ab07eba7778..00648f9d9278 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml @@ -30,7 +30,6 @@ properties: - description: Module clock - description: MBus clock minItems: 2 - maxItems: 3 clock-names: items: @@ -38,7 +37,6 @@ properties: - const: mod - const: ram minItems: 2 - maxItems: 3 resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml b/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml new file mode 100644 index 000000000000..9c97874a6dbd --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm TrustZone CryptoCell cryptographic engine + +maintainers: + - Gilad Ben-Yossef + +properties: + compatible: + enum: + - arm,cryptocell-713-ree + - arm,cryptocell-703-ree + - arm,cryptocell-712-ree + - arm,cryptocell-710-ree + - arm,cryptocell-630p-ree + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + arm_cc712: crypto@80000000 { + compatible = "arm,cryptocell-712-ree"; + reg = <0x80000000 0x10000>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt deleted file mode 100644 index 6130e6eb4af8..000000000000 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ /dev/null @@ -1,25 +0,0 @@ -Arm TrustZone CryptoCell cryptographic engine - -Required properties: -- compatible: Should be one of - - "arm,cryptocell-713-ree" - "arm,cryptocell-703-ree" - "arm,cryptocell-712-ree" - "arm,cryptocell-710-ree" - "arm,cryptocell-630p-ree" -- reg: Base physical address of the engine and length of memory mapped region. -- interrupts: Interrupt number for the device. - -Optional properties: -- clocks: Reference to the crypto engine clock. -- dma-coherent: Present if dma operations are coherent. - -Examples: - - arm_cc712: crypto@80000000 { - compatible = "arm,cryptocell-712-ree"; - interrupt-parent = <&intc>; - interrupts = < 0 30 4 >; - reg = < 0x80000000 0x10000 >; - - }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml index a30bf38a4a49..99be01539fcd 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml @@ -27,7 +27,6 @@ properties: - description: MXS DCP DCP interrupt - description: MXS DCP secure interrupt minItems: 2 - maxItems: 3 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml index 12a7df0e38b2..3d8ea3c2d8dd 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml @@ -26,14 +26,12 @@ properties: reg: minItems: 1 - maxItems: 2 items: - description: Display Backend registers - description: SAT registers reg-names: minItems: 1 - maxItems: 2 items: - const: be - const: sat @@ -43,7 +41,6 @@ properties: clocks: minItems: 3 - maxItems: 4 items: - description: The backend interface clock - description: The backend module clock @@ -52,7 +49,6 @@ properties: clock-names: minItems: 3 - maxItems: 4 items: - const: ahb - const: mod @@ -61,14 +57,12 @@ properties: resets: minItems: 1 - maxItems: 2 items: - description: The Backend reset line - description: The SAT reset line reset-names: minItems: 1 - maxItems: 2 items: - const: be - const: sat diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index a738d7c12a97..bf0bdf54e5f9 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -24,7 +24,6 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: Bus Clock - description: Module Clock diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index 907fb47cc84a..5d42d36608d9 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -46,7 +46,6 @@ properties: clocks: minItems: 3 - maxItems: 6 items: - description: Bus Clock - description: Register Clock @@ -57,7 +56,6 @@ properties: clock-names: minItems: 3 - maxItems: 6 items: - const: iahb - const: isfr @@ -68,14 +66,12 @@ properties: resets: minItems: 1 - maxItems: 2 items: - description: HDMI Controller Reset - description: HDCP Reset reset-names: minItems: 1 - maxItems: 2 items: - const: ctrl - const: hdcp diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml index 501cec16168c..a97366aaf924 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml @@ -27,7 +27,6 @@ properties: clocks: minItems: 2 - maxItems: 4 items: - description: Bus Clock - description: Module Clock @@ -36,7 +35,6 @@ properties: clock-names: minItems: 2 - maxItems: 4 items: - const: bus - const: mod diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml index ec21e8bf2767..61ef7b337218 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -48,7 +48,6 @@ properties: clocks: minItems: 2 - maxItems: 6 items: - description: The TCON TOP interface clock - description: The TCON TOP TV0 clock @@ -59,7 +58,6 @@ properties: clock-names: minItems: 2 - maxItems: 6 items: - const: bus - const: tcon-tv0 diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml index d900cc57b4ec..9b24081a0dbd 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: brcm,bcm2835-vec + enum: + - brcm,bcm2711-vec + - brcm,bcm2835-vec reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt deleted file mode 100644 index 659523f538bf..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ /dev/null @@ -1,143 +0,0 @@ -Analog Devices ADV7511(W)/13/33/35 HDMI Encoders ------------------------------------------------- - -The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video -transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space -conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input -pixels, while the others support RGB interface. - -Required properties: - -- compatible: Should be one of: - "adi,adv7511" - "adi,adv7511w" - "adi,adv7513" - "adi,adv7533" - "adi,adv7535" - -- reg: I2C slave addresses - The ADV7511 internal registers are split into four pages exposed through - different I2C addresses, creating four register maps. Each map has it own - I2C address and acts as a standard slave device on the I2C bus. The main - address is mandatory, others are optional and revert to defaults if not - specified. - - -The ADV7511 supports a large number of input data formats that differ by their -color depth, color format, clock mode, bit justification and random -arrangement of components on the data bus. The combination of the following -properties describe the input and map directly to the video input tables of the -ADV7511 datasheet that document all the supported combinations. - -- adi,input-depth: Number of bits per color component at the input (8, 10 or - 12). -- adi,input-colorspace: The input color space, one of "rgb", "yuv422" or - "yuv444". -- adi,input-clock: The input clock type, one of "1x" (one clock cycle per - pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel, - data driven on both edges). - -The following input format properties are required except in "rgb 1x" and -"yuv444 1x" modes, in which case they must not be specified. - -- adi,input-style: The input components arrangement variant (1, 2 or 3), as - listed in the input format tables in the datasheet. -- adi,input-justification: The input bit justification ("left", "evenly", - "right"). - -- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip. -- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip. -- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip. -- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V - on the chip. -- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is - needed only for ADV7511. - -The following properties are required for ADV7533 and ADV7535: - -- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should - be one of 1, 2, 3 or 4. -- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip. -- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip. -- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be - either 1.2V or 1.8V for ADV7533 but only 1.8V for ADV7535. - -Optional properties: - -- interrupts: Specifier for the ADV7511 interrupt -- pd-gpios: Specifier for the GPIO connected to the power down signal - -- adi,clock-delay: Video data clock delay relative to the pixel clock, in ps - (-1200 ps .. 1600 ps). Defaults to no delay. -- adi,embedded-sync: The input uses synchronization signals embedded in the - data stream (similar to BT.656). Defaults to separate H/V synchronization - signals. -- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the - internal timing generator. The chip will rely on the sync signals in the - DSI data lanes, rather than generate its own timings for HDMI output. -- clocks: from common clock binding: reference to the CEC clock. -- clock-names: from common clock binding: must be "cec". -- reg-names : Names of maps with programmable addresses. - It can contain any map needing a non-default address. - Possible maps names are : "main", "edid", "cec", "packet" - -Required nodes: - -The ADV7511 has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533/5, the - remote endpoint phandle should be a reference to a valid mipi_dsi_host device - node. -- Video port 1 for the HDMI output -- Audio port 2 for the HDMI audio input - - -Example -------- - - adv7511w: hdmi@39 { - compatible = "adi,adv7511w"; - /* - * The EDID page will be accessible on address 0x66 on the I2C - * bus. All other maps continue to use their default addresses. - */ - reg = <0x39>, <0x66>; - reg-names = "main", "edid"; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511w_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - - port@2 { - reg = <2>; - codec_endpoint: endpoint { - remote-endpoint = <&i2s0_cpu_endpoint>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml new file mode 100644 index 000000000000..d3dd7a79b909 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/adi,adv7511.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7511/11W/13 HDMI Encoders + +maintainers: + - Laurent Pinchart + +description: | + The ADV7511, ADV7511W and ADV7513 are HDMI audio and video + transmitters compatible with HDMI 1.4 and DVI 1.0. They support color + space conversion, S/PDIF, CEC and HDCP. The transmitter input is + parallel RGB or YUV data. + +properties: + compatible: + enum: + - adi,adv7511 + - adi,adv7511w + - adi,adv7513 + + reg: + description: | + I2C slave addresses. + + The ADV7511/11W/13 internal registers are split into four pages + exposed through different I2C addresses, creating four register + maps. Each map has it own I2C address and acts as a standard slave + device on the I2C bus. The main address is mandatory, others are + optional and revert to defaults if not specified. + minItems: 1 + maxItems: 4 + + reg-names: + description: + Names of maps with programmable addresses. It can contain any map + needing a non-default address. + minItems: 1 + items: + - const: main + - const: edid + - const: cec + - const: packet + + clocks: + description: Reference to the CEC clock. + maxItems: 1 + + clock-names: + const: cec + + interrupts: + maxItems: 1 + + pd-gpios: + description: GPIO connected to the power down signal. + maxItems: 1 + + avdd-supply: + description: A 1.8V supply that powers up the AVDD pin. + + dvdd-supply: + description: A 1.8V supply that powers up the DVDD pin. + + pvdd-supply: + description: A 1.8V supply that powers up the PVDD pin. + + dvdd-3v-supply: + description: A 3.3V supply that powers up the DVDD_3V pin. + + bgvdd-supply: + description: A 1.8V supply that powers up the BGVDD pin. + + adi,input-depth: + description: Number of bits per color component at the input. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 8, 10, 12 ] + + adi,input-colorspace: + description: Input color space. + enum: [ rgb, yuv422, yuv444 ] + + adi,input-clock: + description: | + Input clock type. + "1x": one clock cycle per pixel + "2x": two clock cycles per pixel + "dd": one clock cycle per pixel, data driven on both edges + enum: [ 1x, 2x, dd ] + + adi,clock-delay: + description: + Video data clock delay relative to the pixel clock, in ps + (-1200ps .. 1600 ps). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + adi,embedded-sync: + description: + If defined, the input uses synchronization signals embedded in the + data stream (similar to BT.656). + type: boolean + + adi,input-style: + description: + Input components arrangement variant as listed in the input + format tables in the datasheet. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 3 ] + + adi,input-justification: + description: Input bit justification. + enum: [ left, evenly, right ] + + ports: + description: + The ADV7511(W)/13 has two video ports and one audio port. This node + models their connections as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + type: object + properties: + port@0: + description: Video port for the RGB or YUV input. + type: object + + port@1: + description: Video port for the HDMI output. + type: object + + port@2: + description: Audio port for the HDMI output. + type: object + +# adi,input-colorspace and adi,input-clock are required except in +# "rgb 1x" and "yuv444 1x" modes, in which case they must not be +# specified. +if: + not: + properties: + adi,input-colorspace: + contains: + enum: [ rgb, yuv444 ] + adi,input-clock: + contains: + const: 1x + +then: + required: + - adi,input-style + - adi,input-justification + +else: + properties: + adi,input-style: false + adi,input-justification: false + + +required: + - compatible + - reg + - ports + - adi,input-depth + - adi,input-colorspace + - adi,input-clock + - avdd-supply + - dvdd-supply + - pvdd-supply + - dvdd-3v-supply + - bgvdd-supply + +additionalProperties: false + +examples: + - | + #include + + i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe6500000>; + + adv7511w: hdmi@39 { + compatible = "adi,adv7511w"; + /* + * The EDID page will be accessible on address 0x66 on the I2C + * bus. All other maps continue to use their default addresses. + */ + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + clocks = <&cec_clock>; + clock-names = "cec"; + avdd-supply = <&v1v8>; + dvdd-supply = <&v1v8>; + pvdd-supply = <&v1v8>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v1v8>; + + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + + adi,input-style = <3>; + adi,input-justification = "right"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511w_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + port@2 { + reg = <2>; + codec_endpoint: endpoint { + remote-endpoint = <&i2s0_cpu_endpoint>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml new file mode 100644 index 000000000000..f36209137c8a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7533/35 HDMI Encoders + +maintainers: + - Laurent Pinchart + +description: | + The ADV7533 and ADV7535 are HDMI audio and video transmitters + compatible with HDMI 1.4 and DVI 1.0. They support color space + conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI. + +properties: + compatible: + enum: + - adi,adv7533 + - adi,adv7535 + + reg: + description: | + I2C slave addresses. + + The ADV7533/35 internal registers are split into four pages + exposed through different I2C addresses, creating four register + maps. Each map has it own I2C address and acts as a standard slave + device on the I2C bus. The main address is mandatory, others are + optional and revert to defaults if not specified. + minItems: 1 + maxItems: 4 + + reg-names: + description: + Names of maps with programmable addresses. It can contain any map + needing a non-default address. + minItems: 1 + items: + - const: main + - const: edid + - const: cec + - const: packet + + clocks: + description: Reference to the CEC clock. + maxItems: 1 + + clock-names: + const: cec + + interrupts: + maxItems: 1 + + pd-gpios: + description: GPIO connected to the power down signal. + maxItems: 1 + + avdd-supply: + description: A 1.8V supply that powers up the AVDD pin. + + dvdd-supply: + description: A 1.8V supply that powers up the DVDD pin. + + pvdd-supply: + description: A 1.8V supply that powers up the PVDD pin. + + a2vdd-supply: + description: A 1.8V supply that powers up the A2VDD pin. + + v3p3-supply: + description: A 3.3V supply that powers up the V3P3 pin. + + v1p2-supply: + description: + A supply that powers up the V1P2 pin. It can be either 1.2V + or 1.8V for ADV7533 but only 1.8V for ADV7535. + + adi,disable-timing-generator: + description: + Disables the internal timing generator. The chip will rely on the + sync signals in the DSI data lanes, rather than generating its own + timings for HDMI output. + type: boolean + + adi,dsi-lanes: + description: Number of DSI data lanes connected to the DSI host. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 3, 4 ] + + ports: + description: + The ADV7533/35 has two video ports and one audio port. This node + models their connections as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + type: object + properties: + port@0: + description: + Video port for the DSI input. The remote endpoint phandle + should be a reference to a valid mipi_dsi_host_device. + type: object + + port@1: + description: Video port for the HDMI output. + type: object + + port@2: + description: Audio port for the HDMI output. + type: object + +required: + - compatible + - reg + - ports + - adi,dsi-lanes + - avdd-supply + - dvdd-supply + - pvdd-supply + - a2vdd-supply + - v3p3-supply + +additionalProperties: false + +examples: + - | + #include + + i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe6500000>; + + adv7533: hdmi@39 { + compatible = "adi,adv7533"; + /* + * The EDID page will be accessible on address 0x66 on the I2C + * bus. All other maps continue to use their default addresses. + */ + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + clocks = <&cec_clock>; + clock-names = "cec"; + adi,dsi-lanes = <4>; + avdd-supply = <&v1v8>; + dvdd-supply = <&v1v8>; + pvdd-supply = <&v1v8>; + a2vdd-supply = <&v1v8>; + v3p3-supply = <&v3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + port@2 { + reg = <2>; + codec_endpoint: endpoint { + remote-endpoint = <&i2s0_cpu_endpoint>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml index 63427878715e..b2e8bc6da9d0 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -18,7 +18,6 @@ properties: reg: minItems: 1 - maxItems: 2 items: - description: Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). @@ -26,13 +25,15 @@ properties: included in the associated PHY. - description: Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. + - description: + Register block of mhdptx sapb registers. reg-names: minItems: 1 - maxItems: 2 items: - const: mhdptx - const: j721e-intg + - const: mhdptx-sapb clocks: maxItems: 1 @@ -99,14 +100,18 @@ allOf: properties: reg: minItems: 2 + maxItems: 3 reg-names: minItems: 2 + maxItems: 3 else: properties: reg: - maxItems: 1 + minItems: 1 + maxItems: 2 reg-names: - maxItems: 1 + minItems: 1 + maxItems: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml b/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml new file mode 100644 index 000000000000..9f7cc6b757cb --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port + +maintainers: + - Nicolas Boichat + - Enric Balletbo i Serra + +description: | + ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to + DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip + which is connected to and operated by the ChromeOS Embedded Controller + (See google,cros-ec.yaml). It is accessed using I2C tunneling through + the EC and therefore its node should be a child of an EC I2C tunnel node + (See google,cros-ec-i2c-tunnel.yaml). + +properties: + compatible: + const: google,cros-ec-anx7688 + + reg: + maxItems: 1 + description: I2C address of the device. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for HDMI input. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: USB Type-c connector. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +additionalProperties: false + +examples: + - | + i2c_tunnel_b: i2c-tunnel1 { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + anx7688: anx7688@2c { + compatible = "google,cros-ec-anx7688"; + reg = <0x2c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + anx7688_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + port@1 { + reg = <1>; + anx7688_out: endpoint { + remote-endpoint = <&typec_connector>; + }; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml new file mode 100644 index 000000000000..6ec1d5fbb8bc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE it66121 HDMI bridge Device Tree Bindings + +maintainers: + - Phong LE + - Neil Armstrong + +description: | + The IT66121 is a high-performance and low-power single channel HDMI + transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible + to DVI 1.0 specifications. + +properties: + compatible: + const: ite,it66121 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: GPIO connected to active low reset + + vrf12-supply: + description: Regulator for 1.2V analog core power. + + vcn33-supply: + description: Regulator for 3.3V digital core power. + + vcn18-supply: + description: Regulator for 1.8V IO core power. + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DPI input port. + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + bus-width: + description: + Endpoint bus width. + enum: + - 12 # 12 data lines connected and dual-edge mode + - 24 # 24 data lines connected and single-edge mode + default: 24 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI Connector port. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reset-gpios + - vrf12-supply + - vcn33-supply + - vcn18-supply + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + it66121hdmitx: hdmitx@4c { + compatible = "ite,it66121"; + pinctrl-names = "default"; + pinctrl-0 = <&ite_pins_default>; + vcn33-supply = <&mt6358_vcn33_wifi_reg>; + vcn18-supply = <&mt6358_vcn18_reg>; + vrf12-supply = <&mt6358_vrf12_reg>; + reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pio>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + reg = <0x4c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it66121_in: endpoint { + bus-width = <12>; + remote-endpoint = <&display_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi_conn_out: endpoint { + remote-endpoint = <&hdmi_conn_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml index 735d0233a7d6..674891ee2f8e 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml @@ -29,7 +29,8 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Primary MIPI port for MIPI input diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml new file mode 100644 index 000000000000..d101233ae17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip + +maintainers: + - Marek Vasut + +description: | + Texas Instruments SN65DSI83 1x Single-link MIPI DSI + to 1x Single-link LVDS + https://www.ti.com/lit/gpn/sn65dsi83 + Texas Instruments SN65DSI84 1x Single-link MIPI DSI + to 1x Dual-link or 2x Single-link LVDS + https://www.ti.com/lit/gpn/sn65dsi84 + +properties: + compatible: + enum: + - ti,sn65dsi83 + - ti,sn65dsi84 + + reg: + enum: + - 0x2c + - 0x2d + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge_en pin (active high). + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for MIPI DSI Channel-A input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + maxItems: 4 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for MIPI DSI Channel-B input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + maxItems: 4 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for LVDS Channel-A output (panel or bridge). + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for LVDS Channel-B output (panel or bridge). + + required: + - port@0 + - port@2 + +required: + - compatible + - reg + - enable-gpios + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: ti,sn65dsi83 + then: + properties: + ports: + properties: + port@1: false + port@3: false + + - if: + properties: + compatible: + contains: + const: ti,sn65dsi84 + then: + properties: + ports: + properties: + port@1: false + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi83"; + reg = <0x2d>; + + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/faraday,tve200.txt b/Documentation/devicetree/bindings/display/faraday,tve200.txt deleted file mode 100644 index 82e3bc0b7485..000000000000 --- a/Documentation/devicetree/bindings/display/faraday,tve200.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Faraday TV Encoder TVE200 - -Required properties: - -- compatible: must be one of: - "faraday,tve200" - "cortina,gemini-tvc", "faraday,tve200" - -- reg: base address and size of the control registers block - -- interrupts: contains an interrupt specifier for the interrupt - line from the TVE200 - -- clock-names: should contain "PCLK" for the clock line clocking the - silicon and "TVE" for the 27MHz clock to the video driver - -- clocks: contains phandle and clock specifier pairs for the entries - in the clock-names property. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional properties: - -- resets: contains the reset line phandle for the block - -Required sub-nodes: - -- port: describes LCD panel signals, following the common binding - for video transmitter interfaces; see - Documentation/devicetree/bindings/media/video-interfaces.txt - This port should have the properties: - reg = <0>; - It should have one endpoint connected to a remote endpoint where - the display is connected. - -Example: - -display-controller@6a000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "faraday,tve200"; - reg = <0x6a000000 0x1000>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_TVC>; - clocks = <&syscon GEMINI_CLK_GATE_TVC>, - <&syscon GEMINI_CLK_TVC>; - clock-names = "PCLK", "TVE"; - - port@0 { - reg = <0>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/faraday,tve200.yaml b/Documentation/devicetree/bindings/display/faraday,tve200.yaml new file mode 100644 index 000000000000..e2ee77767321 --- /dev/null +++ b/Documentation/devicetree/bindings/display/faraday,tve200.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/faraday,tve200.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday TV Encoder TVE200 + +maintainers: + - Linus Walleij + +properties: + compatible: + oneOf: + - const: faraday,tve200 + - items: + - const: cortina,gemini-tvc + - const: faraday,tve200 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + + clock-names: + items: + - const: PCLK + - const: TVE + + clocks: + minItems: 2 + + resets: + minItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + display-controller@6a000000 { + compatible = "faraday,tve200"; + reg = <0x6a000000 0x1000>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_TVC>; + clocks = <&syscon GEMINI_CLK_GATE_TVC>, + <&syscon GEMINI_CLK_TVC>; + clock-names = "PCLK", "TVE"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml new file mode 100644 index 000000000000..66288b9f0aa6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI CEC Controller Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI CEC controller handles hotplug detection and CEC communication. + +properties: + compatible: + enum: + - mediatek,mt7623-cec + - mediatek,mt8167-cec + - mediatek,mt8173-cec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + cec: cec@10013000 { + compatible = "mediatek,mt8173-cec"; + reg = <0x10013000 0xbc>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml new file mode 100644 index 000000000000..b6fcdfb99ab2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt7623-hdmi-ddc + - mediatek,mt8167-hdmi-ddc + - mediatek,mt8173-hdmi-ddc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi_ddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + reg = <0x11012000 0x1c>; + interrupts = ; + clocks = <&pericfg CLK_PERI_I2C5>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt deleted file mode 100644 index b284ca51b913..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ /dev/null @@ -1,136 +0,0 @@ -Mediatek HDMI Encoder -===================== - -The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from -its parallel input. - -Required properties: -- compatible: Should be "mediatek,-hdmi". -- the supported chips are mt2701, mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "pixel", "pll", "bclk", and "spdif". -- phys: phandle link to the HDMI PHY node. - See Documentation/devicetree/bindings/phy/phy-bindings.txt for details. -- phy-names: must contain "hdmi" -- mediatek,syscon-hdmi: phandle link and register offset to the system - configuration registers. For mt8173 this must be offset 0x900 into the - MMSYS_CONFIG region: <&mmsys 0x900>. -- ports: A node containing input and output port nodes with endpoint - definitions as documented in Documentation/devicetree/bindings/graph.txt. -- port@0: The input port in the ports node should be connected to a DPI output - port. -- port@1: The output port in the ports node should be connected to the input - port of a connector node that contains a ddc-i2c-bus property, or to the - input port of an attached bridge chip, such as a SlimPort transmitter. - -HDMI CEC -======== - -The HDMI CEC controller handles hotplug detection and CEC communication. - -Required properties: -- compatible: Should be "mediatek,-cec" -- the supported chips are mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clock - -HDMI DDC -======== - -The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. -The Mediatek's I2C controller is used to interface with I2C devices. - -Required properties: -- compatible: Should be "mediatek,-hdmi-ddc" -- the supported chips are mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- clocks: device clock -- clock-names: Should be "ddc-i2c". - -HDMI PHY -======== -See phy/mediatek,hdmi-phy.yaml - -Example: - -cec: cec@10013000 { - compatible = "mediatek,mt8173-cec"; - reg = <0 0x10013000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; -}; - -hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt8173-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - #clock-cells = <0>; - #phy-cells = <0>; -}; - -hdmi_ddc0: i2c@11012000 { - compatible = "mediatek,mt8173-hdmi-ddc"; - reg = <0 0x11012000 0 0x1c>; - interrupts = ; - clocks = <&pericfg CLK_PERI_I2C5>; - clock-names = "ddc-i2c"; -}; - -hdmi0: hdmi@14025000 { - compatible = "mediatek,mt8173-hdmi"; - reg = <0 0x14025000 0 0x400>; - interrupts = ; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLLCK>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pin>; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; - assigned-clock-parents = <&hdmi_phy>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml new file mode 100644 index 000000000000..111967efa999 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt2701-hdmi + - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi + - mediatek,mt8173-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Pixel Clock + - description: HDMI PLL + - description: Bit Clock + - description: S/PDIF Clock + + clock-names: + items: + - const: pixel + - const: pll + - const: bclk + - const: spdif + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + + mediatek,syscon-hdmi: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: | + phandle link and register offset to the system configuration registers. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: | + Input port node. This port should be connected to a DPI output port. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + Output port node. This port should be connected to the input port of a connector + node that contains a ddc-i2c-bus property, or to the input port of an attached + bridge chip, such as a SlimPort transmitter. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - mediatek,syscon-hdmi + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0x14025000 0x400>; + interrupts = ; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file mode 100644 index 000000000000..64d8d9e5e47a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM Display Port Controller + +maintainers: + - Kuogee Hsieh + +description: | + Device tree bindings for DisplayPort host controller for MSM targets + that are compatible with VESA DisplayPort interface specification. + +properties: + compatible: + enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AHB clock to enable register access + - description: Display Port AUX clock + - description: Display Port Link clock + - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + + assigned-clocks: + items: + - description: link clock source + - description: pixel clock source + + assigned-clock-parents: + items: + - description: phy 0 parent + - description: phy 1 parent + + phys: + maxItems: 1 + + phy-names: + items: + - const: dp + + operating-points-v2: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the controller + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - "#sound-dai-cells" + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + displayport-controller@ae90000 { + compatible = "qcom,sc7180-dp"; + reg = <0xae90000 0x1400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + + phys = <&dp_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + power-domains = <&rpmhpd SC7180_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&typec>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file mode 100644 index 000000000000..12a86b1ec1bc --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SC7180 target + +maintainers: + - Krishna Manikandan + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + + interconnects: + items: + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + const: mdp0-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF0 (DP) + + required: + - port@0 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7180-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file mode 100644 index 000000000000..b4ea7c92fb3d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SDM845 target + +maintainers: + - Krishna Manikandan + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SDM845 target. + +properties: + compatible: + items: + - const: qcom,sdm845-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + + ranges: true + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sdm845-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) + + required: + - port@0 + - port@1 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt deleted file mode 100644 index 586e6eac5b08..000000000000 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ /dev/null @@ -1,141 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates -sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" -- reg: physical base address and length of controller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- iommus: phandle of iommu device node. -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. -- interconnects : interconnect path specifier for MDSS according to - Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be - 2 paths corresponding to 2 AXI ports. -- interconnect-names : MDSS will have 2 port names to differentiate between the - 2 interconnect paths defined with interconnect specifier. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region is required: - * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. These ports connect - to interfaces that are external to the DPU hardware, such as DSI, DP etc. - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, - <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; - - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <0 0 300000000 19200000>; - - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file mode 100644 index 000000000000..76348b71f736 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI controller + +maintainers: + - Krishna Manikandan + +allOf: + - $ref: "../dsi-controller.yaml#" + +properties: + compatible: + items: + - const: qcom,mdss-dsi-ctrl + + reg: + maxItems: 1 + + reg-names: + const: dsi_ctrl + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Display byte clock + - description: Display byte interface clock + - description: Display pixel clock + - description: Display escape clock + - description: Display AHB clock + - description: Display AXI clock + + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + phys: + maxItems: 1 + + phy-names: + const: dsi + + "#address-cells": true + + "#size-cells": true + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2). + $ref: "/schemas/types.yaml#/definitions/phandle" + + qcom,dual-dsi-mode: + type: boolean + description: | + Indicates if the DSI controller is driving a panel which needs + 2 DSI links. + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: "/schemas/graph.yaml#/properties/ports" + description: | + Contains DSI controller input and output ports as children, each + containing one endpoint subnode. + + properties: + port@0: + $ref: "/schemas/graph.yaml#/properties/port" + description: | + Input endpoints of the controller. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + maxItems: 4 + minItems: 4 + items: + enum: [ 0, 1, 2, 3 ] + + port@1: + $ref: "/schemas/graph.yaml#/properties/port" + description: | + Output endpoints of the controller. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + maxItems: 4 + minItems: 4 + items: + enum: [ 0, 1, 2, 3 ] + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - phys + - phy-names + - power-domains + - operating-points-v2 + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&dsi_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file mode 100644 index 000000000000..4a26bef19360 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 10nm PHY + +maintainers: + - Krishna Manikandan + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-10nm + - const: qcom,dsi-phy-10nm-8998 + + reg: + items: + - description: dsi phy register set + - description: dsi phy lane register set + - description: dsi pll register set + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + vdds-supply: + description: | + Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and + connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target + +required: + - compatible + - reg + - reg-names + - vdds-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vdda_mipi_dsi0_pll>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file mode 100644 index 000000000000..72a00cce0147 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 14nm PHY + +maintainers: + - Krishna Manikandan + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-14nm + - const: qcom,dsi-phy-14nm-660 + + reg: + items: + - description: dsi phy register set + - description: dsi phy lane register set + - description: dsi pll register set + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + vcca-supply: + description: Phandle to vcca regulator device node. + +required: + - compatible + - reg + - reg-names + - vcca-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vcca-supply = <&vcca_reg>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file mode 100644 index 000000000000..743806d61afe --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 20nm PHY + +maintainers: + - Krishna Manikandan + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-20nm + + reg: + items: + - description: dsi pll register set + - description: dsi phy register set + - description: dsi phy regulator register set + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + vcca-supply: + description: Phandle to vcca regulator device node. + + vddio-supply: + description: Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - vddio-supply + - vcca-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-20nm"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vcca-supply = <&vcca_reg>; + vddio-supply = <&vddio_reg>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file mode 100644 index 000000000000..b106007116b4 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 28nm PHY + +maintainers: + - Krishna Manikandan + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-28nm-hpm + - const: qcom,dsi-phy-28nm-lp + - const: qcom,dsi-phy-28nm-8960 + + reg: + items: + - description: dsi pll register set + - description: dsi phy register set + - description: dsi phy regulator register set + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + vddio-supply: + description: Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - vddio-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vddio-supply = <&vddio_reg>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml new file mode 100644 index 000000000000..502bdda90235 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI PHY common dt properties + +maintainers: + - Krishna Manikandan + +description: | + This defines the DSI PHY dt properties which are common for all + dsi phy versions. + +properties: + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: Display AHB clock + - description: Board XO source + + clock-names: + items: + - const: iface + - const: ref + +required: + - clocks + - clock-names + - "#clock-cells" + - "#phy-cells" + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt deleted file mode 100644 index b9a64d3ff184..000000000000 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ /dev/null @@ -1,249 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon DSI output - -DSI Controller: -Required properties: -- compatible: - * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller -- reg-names: The names of register regions. The following regions are required: - * "dsi_ctrl" -- interrupts: The interrupt signal from the DSI block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. -- clock-names: the following clocks are required: - * "mdp_core" - * "iface" - * "bus" - * "core_mmss" - * "byte" - * "pixel" - * "core" - For DSIv2, we need an additional clock: - * "src" - For DSI6G v2.0 onwards, we need also need the clock: - * "byte_intf" -- assigned-clocks: Parents of "byte" and "pixel" for the given platform. -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided - by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node -- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node -- phys: phandle to DSI PHY device node -- phy-names: the name of the corresponding PHY device -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains - an endpoint subnode as defined in [2] and [3]. - -Optional properties: -- panel@0: Node of panel connected to this DSI controller. - See files in [4] for each supported panel. -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is - driving a panel which needs 2 DSI links. -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving - the master link of the 2-DSI panel. -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is - driving a 2-DSI panel whose 2 links need receive command simultaneously. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-n: the "sleep" pinctrl state -- ports: contains DSI controller input and output ports as children, each - containing one endpoint subnode. - - DSI Endpoint properties: - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's - input endpoint. For port@1, set to the MDP interface output. See [2] for - device graph info. - - - data-lanes: this describes how the physical DSI data lanes are mapped - to the logical lanes on the given platform. The value contained in - index n describes what physical lane is mapped to the logical lane n - (DATAn, where n lies between 0 and 3). The clock lane position is fixed - and can't be changed. Hence, they aren't a part of the DT bindings. See - [3] for more info on the data-lanes property. - - For example: - - data-lanes = <3 0 1 2>; - - The above mapping describes that the logical data lane DATA0 is mapped to - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 - to phys DATA1 and logic DATA3 to phys DATA2. - - There are only a limited number of physical to logical mappings possible: - <0 1 2 3> - <1 2 3 0> - <2 3 0 1> - <3 0 1 2> - <0 3 2 1> - <1 0 3 2> - <2 1 0 3> - <3 2 1 0> - -DSI PHY: -Required properties: -- compatible: Could be the following - * "qcom,dsi-phy-28nm-hpm" - * "qcom,dsi-phy-28nm-lp" - * "qcom,dsi-phy-20nm" - * "qcom,dsi-phy-28nm-8960" - * "qcom,dsi-phy-14nm" - * "qcom,dsi-phy-14nm-660" - * "qcom,dsi-phy-10nm" - * "qcom,dsi-phy-10nm-8998" - * "qcom,dsi-phy-7nm" - * "qcom,dsi-phy-7nm-8150" -- reg: Physical base address and length of the registers of PLL, PHY. Some - revisions require the PHY regulator base address, whereas others require the - PHY lane base address. See below for each PHY revision. -- reg-names: The names of register regions. The following regions are required: - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - For DSI 14nm, 10nm and 7nm PHYs: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_lane" -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating - 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. See [1] for details on clock bindings. -- clock-names: the following clocks are required: - * "iface" - * "ref" (only required for new DTS files/entries) - For 28nm HPM/LP, 28nm 8960 PHYs: -- vddio-supply: phandle to vdd-io regulator device node - For 20nm PHY: -- vddio-supply: phandle to vdd-io regulator device node -- vcca-supply: phandle to vcca regulator device node - For 14nm PHY: -- vcca-supply: phandle to vcca regulator device node - For 10nm and 7nm PHY: -- vdds-supply: phandle to vdds regulator device node - -Optional properties: -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY - regulator is wanted. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split is enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/graph.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/display/panel/ - -Example: - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - qcom,dsi-host-index = <0>; - interrupt-parent = <&mdp>; - interrupts = <4 0>; - reg-names = "dsi_ctrl"; - reg = <0xfd922800 0x200>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "bus", - "byte", - "core", - "core_mmss", - "iface", - "mdp_core", - "pixel"; - clocks = - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_PCLK0_CLK>; - - assigned-clocks = - <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = - <&dsi_phy0 0>, - <&dsi_phy0 1>; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - phys = <&dsi_phy0>; - phy-names ="dsi-phy"; - - qcom,dual-dsi-mode; - qcom,master-dsi; - qcom,sync-dual-dsi; - - qcom,mdss-mdp-transfer-time-us = <12000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dsi_active>; - pinctrl-1 = <&dsi_suspend>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - qcom,dsi-phy-index = <0>; - reg-names = - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>; - clock-names = "iface"; - clocks = <&mmcc MDSS_AHB_CLK>; - #clock-cells = <1>; - vddio-supply = <&pma8084_l12>; - - qcom,dsi-phy-regulator-ldo-mode; - }; diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml index 31164608ba1d..49460c9dceea 100644 --- a/Documentation/devicetree/bindings/display/panel/lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml @@ -51,37 +51,37 @@ properties: - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< - DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] specifications. Data are transferred as follows on 4 LVDS lanes. - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< - DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< - DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< + DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< + DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. Data are transferred as follows on 4 LVDS lanes. - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< - DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< - DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< + DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< Control signals are mapped as follows. diff --git a/Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml b/Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml new file mode 100644 index 000000000000..4cb75a5f2e3a --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,lms397kf04.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung LMS397KF04 display panel + +description: The datasheet claims this is based around a display controller + named DB7430 with a separate backlight controller. + +maintainers: + - Linus Walleij + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,lms397kf04 + + reg: true + + reset-gpios: true + + vci-supply: + description: regulator that supplies the VCI analog voltage + usually around 3.0 V + + vccio-supply: + description: regulator that supplies the VCCIO voltage usually + around 1.8 V + + backlight: true + + spi-max-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: inherited as a SPI client node, the datasheet specifies + maximum 300 ns minimum cycle which gives around 3 MHz max frequency + maximum: 3000000 + + port: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "samsung,lms397kf04"; + spi-max-frequency = <3000000>; + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&lcd_1v8_reg>; + reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + backlight = <&ktd259>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index 121596f106da..5f4345d43020 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -55,7 +55,7 @@ properties: maxItems: 1 ports: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/properties/ports description: | The connections to the DU output video ports are modeled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml index 75cd9c686e98..da3b889ad8fc 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -29,7 +29,6 @@ properties: clocks: minItems: 2 - maxItems: 5 items: - {} - {} @@ -41,7 +40,6 @@ properties: clock-names: minItems: 2 - maxItems: 5 items: - {} - {} diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index 679daed4124e..ed310bbe3afe 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -29,7 +29,6 @@ properties: - description: DSI bus clock - description: Pixel clock minItems: 2 - maxItems: 3 clock-names: items: @@ -37,7 +36,6 @@ properties: - const: ref - const: px_clk minItems: 2 - maxItems: 3 resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d54f9ca207af..4ae3d75492d3 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -22,7 +22,6 @@ properties: - description: events interrupt line. - description: errors interrupt line. minItems: 1 - maxItems: 2 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml index 403d57977ee7..d88bd93f4b80 100644 --- a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml @@ -65,7 +65,6 @@ properties: The APB clock and at least one video clock are mandatory, the audio clock is optional. minItems: 2 - maxItems: 4 items: - description: dp_apb_clk is the APB clock - description: dp_aud_clk is the Audio clock @@ -78,13 +77,11 @@ properties: clock-names: oneOf: - minItems: 2 - maxItems: 3 items: - const: dp_apb_clk - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] - minItems: 3 - maxItems: 4 items: - const: dp_apb_clk - const: dp_aud_clk @@ -116,7 +113,6 @@ properties: maxItems: 2 phy-names: minItems: 1 - maxItems: 2 items: - const: dp-phy0 - const: dp-phy1 diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml new file mode 100644 index 000000000000..a4f9fe23dcd9 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera mSGDMA IP core + +maintainers: + - Olivier Dautricourt + +description: | + Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) + intellectual property (IP) + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + const: altr,socfpga-msgdma + + reg: + items: + - description: Control and Status Register Slave Port + - description: Descriptor Slave Port + - description: Response Slave Port + + reg-names: + items: + - const: csr + - const: desc + - const: resp + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + description: + The cell identifies the channel id (must be 0) + +required: + - compatible + - reg + - reg-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + msgdma_controller: dma-controller@ff200b00 { + compatible = "altr,socfpga-msgdma"; + reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>; + reg-names = "csr", "desc", "resp"; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.txt b/Documentation/devicetree/bindings/dma/arm-pl08x.txt deleted file mode 100644 index 0ba81f79266f..000000000000 --- a/Documentation/devicetree/bindings/dma/arm-pl08x.txt +++ /dev/null @@ -1,59 +0,0 @@ -* ARM PrimeCells PL080 and PL081 and derivatives DMA controller - -Required properties: -- compatible: "arm,pl080", "arm,primecell"; - "arm,pl081", "arm,primecell"; - "faraday,ftdmac020", "arm,primecell" -- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded - in the hardware and must be specified here as <0x0003b080>. This number - follows the PrimeCell standard numbering using the JEP106 vendor code 0x38 - for Faraday Technology. -- reg: Address range of the PL08x registers -- interrupt: The PL08x interrupt number -- clocks: The clock running the IP core clock -- clock-names: Must contain "apb_pclk" -- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs -- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs -- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents -- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents -- #dma-cells: must be <2>. First cell should contain the DMA request, - second cell should contain either 1 or 2 depending on - which AHB master that is used. - -Optional properties: -- dma-channels: contains the total number of DMA channels supported by the DMAC -- dma-requests: contains the total number of DMA requests supported by the DMAC -- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 - 64, 128 or 256 bytes are legal values -- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal - values, the Faraday FTDMAC020 can also accept 64 bits - -Clients -Required properties: -- dmas: List of DMA controller phandle, request channel and AHB master id -- dma-names: Names of the aforementioned requested channels - -Example: - -dmac0: dma-controller@10130000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <15>; - clocks = <&hclkdma0>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; -}; - -device@40008000 { - ... - dmas = <&dmac0 0 2 - &dmac0 1 2>; - dma-names = "tx", "rx"; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.yaml b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml new file mode 100644 index 000000000000..3bd9eea543ca --- /dev/null +++ b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller + +maintainers: + - Vinod Koul + +allOf: + - $ref: "dma-controller.yaml#" + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + enum: + - arm,pl080 + - arm,pl081 + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - arm,pl080 + - arm,pl081 + - const: arm,primecell + - items: + - const: faraday,ftdma020 + - const: arm,pl080 + - const: arm,primecell + + reg: + maxItems: 1 + description: Address range of the PL08x registers + + interrupts: + minItems: 1 + description: The PL08x interrupt number + + clocks: + minItems: 1 + description: The clock running the IP core clock + + clock-names: + maxItems: 1 + + lli-bus-interface-ahb1: + type: boolean + description: if AHB master 1 is eligible for fetching LLIs + + lli-bus-interface-ahb2: + type: boolean + description: if AHB master 2 is eligible for fetching LLIs + + mem-bus-interface-ahb1: + type: boolean + description: if AHB master 1 is eligible for fetching memory contents + + mem-bus-interface-ahb2: + type: boolean + description: if AHB master 2 is eligible for fetching memory contents + + memcpy-burst-size: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 1 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + description: the size of the bursts for memcpy + + memcpy-bus-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 8 + - 16 + - 32 + - 64 + description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits + +required: + - reg + - interrupts + - clocks + - clock-names + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + - | + #include + #include + #include + dma-controller@67000000 { + compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; + /* Faraday Technology FTDMAC020 variant */ + arm,primecell-periphid = <0x0003b080>; + reg = <0x67000000 0x1000>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_DMAC>; + clocks = <&syscon GEMINI_CLK_AHB>; + clock-names = "apb_pclk"; + /* Bus interface AHB1 (AHB0) is totally tilted */ + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index e302147e53c6..e614fe3187bb 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -21,6 +21,7 @@ properties: enum: - qcom,sdm845-gpi-dma - qcom,sm8150-gpi-dma + - qcom,sm8250-gpi-dma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml index 7f2a54bc732d..d8142cbd13d3 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml @@ -52,7 +52,6 @@ properties: interrupt-names: minItems: 9 - maxItems: 17 items: - const: error - pattern: "^ch([0-9]|1[0-5])$" diff --git a/Documentation/devicetree/bindings/dma/renesas,shdma.txt b/Documentation/devicetree/bindings/dma/renesas,shdma.txt deleted file mode 100644 index a91920a49433..000000000000 --- a/Documentation/devicetree/bindings/dma/renesas,shdma.txt +++ /dev/null @@ -1,84 +0,0 @@ -* SHDMA Device Tree bindings - -Sh-/r-mobile and R-Car systems often have multiple identical DMA controller -instances, capable of serving any of a common set of DMA slave devices, using -the same configuration. To describe this topology we require all compatible -SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible -DMAC instances have the same number of channels and use the same DMA -descriptors. Therefore respective DMA DT bindings can also all be placed in the -multiplexer node. Even if there is only one such DMAC instance on a system, it -still has to be placed under such a multiplexer node. - -* DMA multiplexer - -Required properties: -- compatible: should be "renesas,shdma-mux" -- #dma-cells: should be <1>, see "dmas" property below - -Optional properties (currently unused): -- dma-channels: number of DMA channels -- dma-requests: number of DMA request signals - -* DMA controller - -Required properties: -- compatible: should be of the form "renesas,shdma-", where should - be replaced with the desired SoC model, e.g. - "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC - -Example: - dmac: dma-multiplexer@0 { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupt-parent = <&gic>; - interrupts = <0 220 4 - 0 200 4 - 0 201 4 - 0 202 4 - 0 203 4 - 0 204 4 - 0 205 4 - 0 206 4 - 0 207 4 - 0 208 4 - 0 209 4 - 0 210 4 - 0 211 4 - 0 212 4 - 0 213 4 - 0 214 4 - 0 215 4 - 0 216 4 - 0 217 4 - 0 218 4 - 0 219 4>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - }; - }; - -* DMA client - -Required properties: -- dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs, - where MID/RID values are fixed handles, specified in the SoC - manual -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: - dmas = <&dmac 0xd1 - &dmac 0xd2>; - dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 29fcd37082e8..f719e1612b0a 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -33,7 +33,7 @@ The following are mandatory properties for 66AK2G SoCs only: - power-domains:Should contain a phandle to a PM domain provider node and an args specifier containing the device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml Optional properties: ------------------- @@ -70,7 +70,7 @@ The following are mandatory properties for 66AK2G SoCs only: - power-domains:Should contain a phandle to a PM domain provider node and an args specifier containing the device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml Optional properties: ------------------- diff --git a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml index 57e5270a0741..4cfc3a187004 100644 --- a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml +++ b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml @@ -30,14 +30,12 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: uncorrectable error interrupt - description: correctable error interrupt interrupt-names: minItems: 1 - maxItems: 2 items: - const: ue - const: ce diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 021d8ae42da3..914a423ec449 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -32,7 +32,6 @@ properties: oneOf: - allOf: - minItems: 1 - maxItems: 2 items: - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$" - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" diff --git a/Documentation/devicetree/bindings/eeprom/at25.yaml b/Documentation/devicetree/bindings/eeprom/at25.yaml index 6a2dc8b3ed14..fbf99e346966 100644 --- a/Documentation/devicetree/bindings/eeprom/at25.yaml +++ b/Documentation/devicetree/bindings/eeprom/at25.yaml @@ -4,14 +4,16 @@ $id: "http://devicetree.org/schemas/eeprom/at25.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: SPI EEPROMs compatible with Atmel's AT25 +title: SPI EEPROMs or FRAMs compatible with Atmel's AT25 maintainers: - Christian Eggers properties: $nodename: - pattern: "^eeprom@[0-9a-f]{1,2}$" + anyOf: + - pattern: "^eeprom@[0-9a-f]{1,2}$" + - pattern: "^fram@[0-9a-f]{1,2}$" # There are multiple known vendors who manufacture EEPROM chips compatible # with Atmel's AT25. The compatible string requires two items where the @@ -31,6 +33,7 @@ properties: - microchip,25lc040 - st,m95m02 - st,m95256 + - cypress,fm25 - const: atmel,at25 @@ -47,7 +50,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072] description: - Size of the eeprom page. + Size of the eeprom page. FRAMs don't have pages. size: $ref: /schemas/types.yaml#/definitions/uint32 @@ -100,9 +103,19 @@ required: - compatible - reg - spi-max-frequency - - pagesize - - size - - address-width + +allOf: + - if: + properties: + compatible: + not: + contains: + const: cypress,fm25 + then: + required: + - pagesize + - size + - address-width additionalProperties: false @@ -125,4 +138,10 @@ examples: size = <32768>; address-width = <16>; }; + + fram@1 { + compatible = "cypress,fm25", "atmel,at25"; + reg = <1>; + spi-max-frequency = <40000000>; + }; }; diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index a97f39109f8d..ff6ec65145cf 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -91,7 +91,6 @@ properties: interrupts: # Either 1 or 2 interrupts can be present minItems: 1 - maxItems: 2 items: - description: tx or combined interrupt - description: rx interrupt @@ -105,7 +104,6 @@ properties: interrupt-names: # minItems must be specified here because the default would be 2 minItems: 1 - maxItems: 2 items: - const: tx irq - const: rx irq diff --git a/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt b/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt deleted file mode 100644 index fc3888e09549..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt +++ /dev/null @@ -1,21 +0,0 @@ - -* SM5502 MUIC (Micro-USB Interface Controller) device - -The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device -which can detect the state of external accessory when external accessory is -attached or detached and button is pressed or released. It is interfaced to -the host controller using an I2C interface. - -Required properties: -- compatible: Should be "siliconmitus,sm5502-muic" -- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25 -- interrupts: Interrupt specifiers for detection interrupt sources. - -Example: - - sm5502@25 { - compatible = "siliconmitus,sm5502-muic"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x25>; - }; diff --git a/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml b/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml new file mode 100644 index 000000000000..fd2e55088888 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/siliconmitus,sm5502-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SM5502/SM5504 MUIC (Micro-USB Interface Controller) device + +maintainers: + - Chanwoo Choi + +description: + The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device + which can detect the state of external accessory when external accessory is + attached or detached and button is pressed or released. It is interfaced to + the host controller using an I2C interface. + +properties: + compatible: + enum: + - siliconmitus,sm5502-muic + - siliconmitus,sm5504-muic + + reg: + maxItems: 1 + description: I2C slave address of the device. Usually 0x25 for SM5502, + 0x14 for SM5504. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + extcon@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml new file mode 100644 index 000000000000..cebf6ffe70d5 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -0,0 +1,341 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2021 ARM Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Control and Management Interface (SCMI) Message Protocol bindings + +maintainers: + - Sudeep Holla + +description: | + The SCMI is intended to allow agents such as OSPM to manage various functions + that are provided by the hardware platform it is running on, including power + and performance functions. + + This binding is intended to define the interface the firmware implementing + the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control + and Management Interface Platform Design Document")[0] provide for OSPM in + the device tree. + + [0] https://developer.arm.com/documentation/den0056/latest + +properties: + $nodename: + const: scmi + + compatible: + oneOf: + - description: SCMI compliant firmware with mailbox transport + items: + - const: arm,scmi + - description: SCMI compliant firmware with ARM SMC/HVC transport + items: + - const: arm,scmi-smc + + interrupts: + description: + The interrupt that indicates message completion by the platform + rather than by the return of the smc call. This should not be used + except when the platform requires such behavior. + maxItems: 1 + + interrupt-names: + const: a2p + + mbox-names: + description: + Specifies the mailboxes used to communicate with SCMI compliant + firmware. + items: + - const: tx + - const: rx + + mboxes: + description: + List of phandle and mailbox channel specifiers. It should contain + exactly one or two mailboxes, one for transmitting messages("tx") + and another optional for receiving the notifications("rx") if supported. + minItems: 1 + maxItems: 2 + + shmem: + description: + List of phandle pointing to the shared memory(SHM) area, for each + transport channel specified. + minItems: 1 + maxItems: 2 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + arm,smc-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + SMC id required when using smc or hvc transports + + protocol@11: + type: object + properties: + reg: + const: 0x11 + + '#power-domain-cells': + const: 1 + + required: + - '#power-domain-cells' + + protocol@13: + type: object + properties: + reg: + const: 0x13 + + '#clock-cells': + const: 1 + + required: + - '#clock-cells' + + protocol@14: + type: object + properties: + reg: + const: 0x14 + + '#clock-cells': + const: 1 + + required: + - '#clock-cells' + + protocol@15: + type: object + properties: + reg: + const: 0x15 + + '#thermal-sensor-cells': + const: 1 + + required: + - '#thermal-sensor-cells' + + protocol@16: + type: object + properties: + reg: + const: 0x16 + + '#reset-cells': + const: 1 + + required: + - '#reset-cells' + + protocol@17: + type: object + properties: + reg: + const: 0x17 + + regulators: + type: object + description: + The list of all regulators provided by this SCMI controller. + + patternProperties: + '^regulators@[0-9a-f]+$': + type: object + $ref: "../regulator/regulator.yaml#" + + properties: + reg: + maxItems: 1 + description: Identifier for the voltage regulator. + + required: + - reg + +additionalProperties: false + +patternProperties: + '^protocol@[0-9a-f]+$': + type: object + description: + Each sub-node represents a protocol supported. If the platform + supports a dedicated communication channel for a particular protocol, + then the corresponding transport properties must be present. + + properties: + reg: + maxItems: 1 + + mbox-names: + items: + - const: tx + - const: rx + + mboxes: + minItems: 1 + maxItems: 2 + + shmem: + minItems: 1 + maxItems: 2 + + required: + - reg + +required: + - compatible + - shmem + +if: + properties: + compatible: + contains: + const: arm,scmi +then: + properties: + interrupts: false + interrupt-names: false + + required: + - mboxes + +else: + if: + properties: + compatible: + contains: + const: arm,scmi-smc + then: + required: + - arm,smc-id + +examples: + - | + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mhuB 0 0>, + <&mhuB 0 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, + <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + + mboxes = <&mhuB 1 0>, + <&mhuB 1 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_hpri0>, + <&cpu_scp_hpri1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltage: protocol@17 { + reg = <0x17>; + regulators { + #address-cells = <1>; + #size-cells = <0>; + + regulator_devX: regulator@0 { + reg = <0x0>; + regulator-max-microvolt = <3300000>; + }; + + regulator_devY: regulator@9 { + reg = <0x9>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <4200000>; + }; + }; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_lpri1: scp-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + + cpu_scp_hpri0: scp-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + + cpu_scp_hpri2: scp-sram-section@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x80>; + }; + }; + }; + + - | + firmware { + scmi { + compatible = "arm,scmi-smc"; + shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; + arm,smc-id = <0xc3000001>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd1: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + }; + }; + +... diff --git a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml new file mode 100644 index 000000000000..d7113b06454b --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2021 ARM Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/arm,scpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Control and Power Interface (SCPI) Message Protocol bindings + +maintainers: + - Sudeep Holla + +description: | + Firmware implementing the SCPI described in ARM document number ARM DUI + 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be + used by Linux to initiate various system control and power operations. + + This binding is intended to define the interface the firmware implementing + the SCPI provide for OSPM in the device tree. + + [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html + +properties: + $nodename: + const: scpi + + compatible: + description: + SCPI compliant firmware complying to SCPI v1.0 and above OR + SCPI compliant firmware complying to all unversioned releases + prior to SCPI v1.0 + oneOf: + - const: arm,scpi # SCPI v1.0 and above + - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0 + - items: + - enum: + - amlogic,meson-gxbb-scpi + - const: arm,scpi-pre-1.0 + + mboxes: + description: + List of phandle and mailbox channel specifiers. All the channels reserved + by remote SCP firmware for use by SCPI message protocol should be + specified in any order. + minItems: 1 + + shmem: + description: + List of phandle pointing to the shared memory(SHM) area between the + processors using these mailboxes for IPC, one for each mailbox SHM can + be any memory reserved for the purpose of this communication between the + processors. + minItems: 1 + + power-controller: + type: object + description: + This sub-node represents SCPI power domain controller. + + properties: + compatible: + const: arm,scpi-power-domains + + '#power-domain-cells': + const: 1 + + num-domains: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total number of power domains provided by SCPI. This is needed as + the SCPI message protocol lacks a mechanism to query this + information at runtime. + + required: + - compatible + - '#power-domain-cells' + - num-domains + + additionalProperties: false + + sensors: + type: object + description: | + This sub-node represents SCPI sensors controller. + + properties: + compatible: + oneOf: + - const: arm,scpi-sensors + - items: + - enum: + - amlogic,meson-gxbb-scpi-sensors + - const: arm,scpi-sensors + + '#thermal-sensor-cells': + const: 1 + + required: + - compatible + - '#thermal-sensor-cells' + + additionalProperties: false + + clocks: + type: object + description: + This is the container node. Each sub-node represents one of the types + of clock controller - indexed or full range. + + properties: + compatible: + const: arm,scpi-clocks + + patternProperties: + "^clocks-[0-9a-f]+$": + type: object + description: | + This sub-node represents one of the types of clock controller + - indexed or full range. + + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index + based. These clocks don't provide an entire range of values between + the limits but only discrete points within the range. The firmware + provides the mapping for each such operating frequency and the index + associated with it. The firmware also manages the voltage scaling + appropriately with the clock scaling. + + "arm,scpi-variable-clocks" - all the clocks that are variable and + provide full range within the specified range. The firmware provides + the range of values within a specified range. + + properties: + compatible: + oneOf: + - const: arm,scpi-dvfs-clocks + - const: arm,scpi-variable-clocks + + '#clock-cells': + const: 1 + + clock-output-names: true + + clock-indices: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The identifying number for the clocks(i.e.clock_id) in the node. + It can be non linear and hence provide the mapping of identifiers + into the clock-output-names array. + + required: + - compatible + - '#clock-cells' + - clock-output-names + - clock-indices + + additionalProperties: false + + required: + - compatible + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + +examples: + - | + firmware { + scpi { + compatible = "arm,scpi"; + mboxes = <&mhuA 1>; + shmem = <&cpu_scp_hpri>; /* HP-NonSecure */ + + scpi_devpd: power-controller { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clocks-0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "atlclk", "aplclk","gpuclk"; + }; + + scpi_clk: clocks-1 { + compatible = "arm,scpi-variable-clocks"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + }; + + scpi_sensors: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-sram-section@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-sram-section@200 { + compatible = "arm,scp-shmem"; + reg = <0x200 0x200>; + }; + }; + }; + + - | + firmware { + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_sensors1: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index d787d57491a1..7d3515264838 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -38,7 +38,7 @@ Partial Reconfiguration (PR) Partial Reconfiguration Region (PRR) * Also called a "reconfigurable partition" - * A PRR is a specific section of a FPGA reserved for reconfiguration. + * A PRR is a specific section of an FPGA reserved for reconfiguration. * A base (or static) FPGA image may create a set of PRR's that later may be independently reprogrammed many times. * The size and specific location of each PRR is fixed. @@ -105,7 +105,7 @@ reprogrammed independently while the rest of the system continues to function. Sequence ======== -When a DT overlay that targets a FPGA Region is applied, the FPGA Region will +When a DT overlay that targets an FPGA Region is applied, the FPGA Region will do the following: 1. Disable appropriate FPGA bridges. @@ -134,8 +134,8 @@ The intended use is that a Device Tree overlay (DTO) can be used to reprogram an FPGA while an operating system is running. An FPGA Region that exists in the live Device Tree reflects the current state. -If the live tree shows a "firmware-name" property or child nodes under a FPGA -Region, the FPGA already has been programmed. A DTO that targets a FPGA Region +If the live tree shows a "firmware-name" property or child nodes under an FPGA +Region, the FPGA already has been programmed. A DTO that targets an FPGA Region and adds the "firmware-name" property is taken as a request to reprogram the FPGA. After reprogramming is successful, the overlay is accepted into the live tree. @@ -152,9 +152,9 @@ These FPGA regions are children of FPGA bridges which are then children of the base FPGA region. The "Full Reconfiguration to add PRR's" example below shows this. -If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA +If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA Manager specified by its ancestor FPGA Region. This supports both the case -where the same FPGA Manager is used for all of a FPGA as well the case where +where the same FPGA Manager is used for all of an FPGA as well the case where a different FPGA Manager is used for each region. FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents @@ -166,7 +166,7 @@ within the static image of the FPGA. Required properties: - compatible : should contain "fpga-region" - fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions - inherit this property from their ancestor regions. A fpga-mgr property + inherit this property from their ancestor regions. An fpga-mgr property in a region will override any inherited FPGA manager. - #address-cells, #size-cells, ranges : must be present to handle address space mapping for child nodes. @@ -175,12 +175,12 @@ Optional properties: - firmware-name : should contain the name of an FPGA image file located on the firmware search path. If this property shows up in a live device tree it indicates that the FPGA has already been programmed with this image. - If this property is in an overlay targeting a FPGA region, it is a + If this property is in an overlay targeting an FPGA region, it is a request to program the FPGA with that image. - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be controlled during FPGA programming along with the parent FPGA bridge. This property is optional if the FPGA Manager handles the bridges. - If the fpga-region is the child of a fpga-bridge, the list should not + If the fpga-region is the child of an fpga-bridge, the list should not contain the parent bridge. - partial-fpga-config : boolean, set if partial reconfiguration is to be done, otherwise full reconfiguration is done. @@ -279,7 +279,7 @@ Supported Use Models In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some -uses are specific to a FPGA device. +uses are specific to an FPGA device. * No FPGA Bridges In this case, the FPGA Manager which programs the FPGA also handles the @@ -300,7 +300,7 @@ uses are specific to a FPGA device. bridges need to exist in the FPGA that can gate the buses going to each FPGA region while the buses are enabled for other sections. Before any partial reconfiguration can be done, a base FPGA image must be loaded which includes - PRR's with FPGA bridges. The device tree should have a FPGA region for each + PRR's with FPGA bridges. The device tree should have an FPGA region for each PRR. Device Tree Examples diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt deleted file mode 100644 index 7018aa896835..000000000000 --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt +++ /dev/null @@ -1,19 +0,0 @@ -Xilinx Zynq FPGA Manager - -Required properties: -- compatible: should contain "xlnx,zynq-devcfg-1.0" -- reg: base address and size for memory mapped io -- interrupts: interrupt for the FPGA manager device -- clocks: phandle for clocks required operation -- clock-names: name for the clock, should be "ref_clk" -- syscon: phandle for access to SLCR registers - -Example: - devcfg: devcfg@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml new file mode 100644 index 000000000000..29daca4be47f --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq FPGA Manager Device Tree Bindings + +maintainers: + - Michal Simek + +properties: + compatible: + const: xlnx,zynq-devcfg-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ref_clk + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to syscon block which provide access to SLCR registers + +required: + - compatible + - reg + - clocks + - clock-names + - syscon + +additionalProperties: false + +examples: + - | + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupts = <0 8 4>; + clocks = <&clkc 12>; + clock-names = "ref_clk"; + syscon = <&slcr>; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt deleted file mode 100644 index 696ea46227d1..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt +++ /dev/null @@ -1,167 +0,0 @@ -Davinci/Keystone GPIO controller bindings - -Required Properties: -- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs - "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L, - 66AK2E SoCs - "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G - "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654 - "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs - "ti,am64-gpio", "ti,keystone-gpio": for AM64 SoCs - -- reg: Physical base address of the controller and the size of memory mapped - registers. - -- gpio-controller : Marks the device node as a gpio controller. - -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify optional parameters (unused) - -- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are - supported at a time. - -- ti,ngpio: The number of GPIO pins supported. - -- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt - line to processor. - -- clocks: Should contain the device's input clock, and should be defined as per - the appropriate clock bindings consumer usage in, - - Documentation/devicetree/bindings/clock/keystone-gate.txt - for 66AK2HK/66AK2L/66AK2E SoCs or, - - Documentation/devicetree/bindings/clock/ti,sci-clk.txt - for 66AK2G SoCs - -- clock-names: Name should be "gpio"; - -Currently clock-names and clocks are needed for all keystone 2 platforms -Davinci platforms do not have DT clocks as of now. - -The GPIO controller also acts as an interrupt controller. It uses the default -two cells specifier as described in Documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -Example: - -gpio: gpio@1e26000 { - compatible = "ti,dm6441-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x226000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH - 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH - 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH - 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH - 50 IRQ_TYPE_EDGE_BOTH>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -leds { - compatible = "gpio-leds"; - - led1 { - label = "davinci:green:usr1"; - gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; - ... - }; - - led2 { - label = "davinci:red:debug1"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - ... - }; -}; - -Example for 66AK2G: - -gpio0: gpio@2603000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x02603000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001b 0x0>; - clock-names = "gpio"; -}; - -Example for 66AK2HK/66AK2L/66AK2E: - -gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; -}; - -Example for K3 AM654: - -wkup_gpio0: wkup_gpio0@42110000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x42110000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_wkup_gpio>; - interrupts = <59 128>, <59 129>, <59 130>, <59 131>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <56>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 59 0>; - clock-names = "gpio"; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml b/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml new file mode 100644 index 000000000000..f32e09ef937c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO controller for Davinci and keystone devices + +maintainers: + - Keerthy + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,k2g-gpio + - ti,am654-gpio + - ti,j721e-gpio + - ti,am64-gpio + - const: ti,keystone-gpio + + - items: + - enum: + - ti,dm6441-gpio + - ti,keystone-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + gpio-ranges: true + + gpio-line-names: + description: strings describing the names of each gpio line. + minItems: 1 + maxItems: 100 + + "#gpio-cells": + const: 2 + description: + first cell is the pin number and second cell is used to specify optional parameters (unused). + + interrupts: + description: + The interrupts are specified as per the interrupt parent. Only banked + or unbanked IRQs are supported at a time. If the interrupts are + banked then provide list of interrupts corresponding to each bank, else + provide the list of interrupts for each gpio. + minItems: 1 + maxItems: 100 + + ti,ngpio: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of GPIO pins supported consecutively. + minimum: 1 + + ti,davinci-gpio-unbanked: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of GPIOs that have an individual interrupt line to processor. + minimum: 0 + + clocks: + maxItems: 1 + + clock-names: + const: gpio + + interrupt-controller: true + + power-domains: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + + required: + - gpio-hog + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupts + - ti,ngpio + - ti,davinci-gpio-unbanked + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + gpio0: gpio@2603000 { + compatible = "ti,k2g-gpio", "ti,keystone-gpio"; + reg = <0x02603000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k2g_clks 0x001b 0x0>; + clock-names = "gpio"; + }; + + - | + #include + + gpio1: gpio@260bf00 { + compatible = "ti,keystone-gpio"; + reg = <0x0260bf00 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + - | + wkup_gpio0: gpio0@42110000 { + compatible = "ti,am654-gpio", "ti,keystone-gpio"; + reg = <0x42110000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&intr_wkup_gpio>; + interrupts = <60>, <61>, <62>, <63>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <56>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k3_clks 59 0>; + clock-names = "gpio"; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt deleted file mode 100644 index e57b2cb28f6c..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ /dev/null @@ -1,45 +0,0 @@ -OMAP GPIO controller bindings - -Required properties: -- compatible: - - "ti,omap2-gpio" for OMAP2 controllers - - "ti,omap3-gpio" for OMAP3 controllers - - "ti,omap4-gpio" for OMAP4 controllers -- reg : Physical base address of the controller and length of memory mapped - region. -- gpio-controller : Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify optional parameters (unused) -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- interrupts : The interrupt the controller is rising as output when an - interrupt occures - -OMAP specific properties: -- ti,hwmods: Name of the hwmod associated to the GPIO: - "gpio", being the 1-based instance number - from the HW spec. -- ti,gpio-always-on: Indicates if a GPIO bank is always powered and - so will never lose its logic state. - - -Example: - -gpio0: gpio@44e07000 { - compatible = "ti,omap4-gpio"; - reg = <0x44e07000 0x1000>; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <96>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt b/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt deleted file mode 100644 index a482455a205b..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt +++ /dev/null @@ -1,69 +0,0 @@ -* PCF857x-compatible I/O expanders - -The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be -driven high by a pull-up current source or driven low to ground. This combines -the direction and output level into a single bit per line, which can't be read -back. We can't actually know at initialization time whether a line is configured -(a) as output and driving the signal low/high, or (b) as input and reporting a -low/high value, without knowing the last value written since the chip came out -of reset (if any). The only reliable solution for setting up line direction is -thus to do it explicitly. - -Required Properties: - - - compatible: should be one of the following. - - "maxim,max7328": For the Maxim MAX7378 - - "maxim,max7329": For the Maxim MAX7329 - - "nxp,pca8574": For the NXP PCA8574 - - "nxp,pca8575": For the NXP PCA8575 - - "nxp,pca9670": For the NXP PCA9670 - - "nxp,pca9671": For the NXP PCA9671 - - "nxp,pca9672": For the NXP PCA9672 - - "nxp,pca9673": For the NXP PCA9673 - - "nxp,pca9674": For the NXP PCA9674 - - "nxp,pca9675": For the NXP PCA9675 - - "nxp,pcf8574": For the NXP PCF8574 - - "nxp,pcf8574a": For the NXP PCF8574A - - "nxp,pcf8575": For the NXP PCF8575 - - - reg: I2C slave address. - - - gpio-controller: Marks the device node as a gpio controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -Optional Properties: - - - lines-initial-states: Bitmask that specifies the initial state of each - line. When a bit is set to zero, the corresponding line will be initialized to - the input (pulled-up) state. When the bit is set to one, the line will be - initialized the low-level output state. If the property is not specified - all lines will be initialized to the input state. - - The I/O expander can detect input state changes, and thus optionally act as - an interrupt controller. When the expander interrupt line is connected all the - following properties must be set. For more information please see the - interrupt controller device tree bindings documentation available at - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. - - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2. - - interrupts: Interrupt specifier for the controllers interrupt. - - -Please refer to gpio.txt in this directory for details of the common GPIO -bindings used by client devices. - -Example: PCF8575 I/O expander node - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt deleted file mode 100644 index 78458adbf4b7..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt +++ /dev/null @@ -1,42 +0,0 @@ -Lantiq SoC Serial To Parallel (STP) GPIO controller - -The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a -peripheral controller used to drive external shift register cascades. At most -3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem -to drive the 2 LSBs of the cascade automatically. - - -Required properties: -- compatible : Should be "lantiq,gpio-stp-xway" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). -- gpio-controller : Marks the device node as a gpio controller. - -Optional properties: -- lantiq,shadow : The default value that we shall assume as already set on the - shift register cascade. -- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled - in the shift register cascade. -- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit - property can enable this feature. -- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. -- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. -- lantiq,rising : use rising instead of falling edge for the shift register - -Example: - -gpio1: stp@e100bb0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x3>; - lantiq,phy1 = <0x7>; - lantiq,phy2 = <0x7>; - /* lantiq,rising; */ -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml new file mode 100644 index 000000000000..d565c4b63dbf --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq SoC Serial To Parallel (STP) GPIO controller + +description: | + The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a + peripheral controller used to drive external shift register cascades. At most + 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem + and Ethernet PHYs to drive some bytes of the cascade automatically. + +maintainers: + - John Crispin + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: lantiq,gpio-stp-xway + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + description: + The first cell is the pin number and the second cell is used to specify + consumer flags. + const: 2 + + lantiq,shadow: + description: + The default value that we shall assume as already set on the + shift register cascade. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x000000 + maximum: 0xffffff + + lantiq,groups: + description: + Set the 3 bit mask to select which of the 3 groups are enabled + in the shift register cascade. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x0 + maximum: 0x7 + + lantiq,dsl: + description: + The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit + property can enable this feature. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x0 + maximum: 0x3 + + lantiq,rising: + description: + Use rising instead of falling edge for the shift register. + type: boolean + +patternProperties: + "^lantiq,phy[1-4]$": + description: + The gphy core can control 3 bits of the gpio cascade. In the xRX200 family + phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4]. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x0 + maximum: 0x7 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@e100bb0 { + compatible = "lantiq,gpio-stp-xway"; + reg = <0xE100BB0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + + lantiq,shadow = <0xffffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x3>; + lantiq,phy1 = <0x7>; + lantiq,phy2 = <0x7>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt deleted file mode 100644 index f693e82b4c0f..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt +++ /dev/null @@ -1,36 +0,0 @@ -Xilinx Zynq GPIO controller Device Tree Bindings -------------------------------------------- - -Required properties: -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify optional - parameters (unused) -- compatible : Should be "xlnx,zynq-gpio-1.0" or - "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0 - or "xlnx,pmc-gpio-1.0 -- clocks : Clock specifier (see clock bindings for details) -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt specifier (see interrupt bindings for - details) -- interrupt-controller : Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- reg : Address and length of the register set for the device - -Example: - gpio@e000a000 { - #gpio-cells = <2>; - compatible = "xlnx,zynq-gpio-1.0"; - clocks = <&clkc 42>; - gpio-controller; - interrupt-parent = <&intc>; - interrupts = <0 20 4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xe000a000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml new file mode 100644 index 000000000000..378da2649e66 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq GPIO controller Device Tree Bindings + +maintainers: + - Michal Simek + +properties: + compatible: + const: xlnx,zynq-gpio-1.0 + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + + gpio-controller: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#gpio-cells" + - interrupts + - gpio-controller + - interrupt-controller + - "#interrupt-cells" + - clocks + +additionalProperties: false + +examples: + - | + gpio@e000a000 { + #gpio-cells = <2>; + compatible = "xlnx,zynq-gpio-1.0"; + clocks = <&clkc 42>; + gpio-controller; + interrupt-parent = <&intc>; + interrupts = <0 20 4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xe000a000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/gpio/idt,32434-gpio.yaml b/Documentation/devicetree/bindings/gpio/idt,32434-gpio.yaml new file mode 100644 index 000000000000..d38de8144656 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/idt,32434-gpio.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/idt,32434-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IDT 79RC32434 GPIO controller + +maintainers: + - Thomas Bogendoerfer + +properties: + compatible: + const: idt,32434-gpio + + reg: + maxItems: 2 + + reg-names: + items: + - const: gpio + - const: pic + + gpio-controller: true + + "#gpio-cells": + const: 2 + + ngpios: + minimum: 1 + maximum: 32 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio0: gpio@50004 { + compatible = "idt,32434-gpio"; + reg = <0x50004 0x10>, <0x38030 0x0c>; + reg-names = "gpio", "pic"; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <14>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml new file mode 100644 index 000000000000..f0ff66c4c74e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCF857x-compatible I/O expanders + +maintainers: + - Laurent Pinchart + +description: + The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be + driven high by a pull-up current source or driven low to ground. This + combines the direction and output level into a single bit per line, which + can't be read back. We can't actually know at initialization time whether a + line is configured (a) as output and driving the signal low/high, or (b) as + input and reporting a low/high value, without knowing the last value written + since the chip came out of reset (if any). The only reliable solution for + setting up line direction is thus to do it explicitly. + +properties: + compatible: + enum: + - maxim,max7328 + - maxim,max7329 + - nxp,pca8574 + - nxp,pca8575 + - nxp,pca9670 + - nxp,pca9671 + - nxp,pca9672 + - nxp,pca9673 + - nxp,pca9674 + - nxp,pca9675 + - nxp,pcf8574 + - nxp,pcf8574a + - nxp,pcf8575 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell is the GPIO number and the second cell specifies GPIO + flags, as defined in . Only the GPIO_ACTIVE_HIGH + and GPIO_ACTIVE_LOW flags are supported. + + lines-initial-states: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask that specifies the initial state of each line. + When a bit is set to zero, the corresponding line will be initialized to + the input (pulled-up) state. + When the bit is set to one, the line will be initialized to the + low-level output state. + If the property is not specified all lines will be initialized to the + input state. + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + wakeup-source: true + +patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + + required: + - gpio-hog + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt deleted file mode 100644 index f9231df17c2b..000000000000 --- a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt +++ /dev/null @@ -1,32 +0,0 @@ -Rockchip RK3328 GRF (General Register Files) GPIO controller. - -In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute -control, can also be used for general purpose. It is manipulated by the -GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can -also be set in the same way. - -Currently this GPIO controller only supports the mute pin. If needed in the -future, the HDMI pins support can also be added. - -Required properties: -- compatible: Should contain "rockchip,rk3328-grf-gpio". -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = Active high, - 1 = Active low. - -Example: - - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - - grf_gpio: grf-gpio { - compatible = "rockchip,rk3328-grf-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - -Note: The grf_gpio node should be declared as the child of the GRF (General -Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>. diff --git a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.yaml b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.yaml new file mode 100644 index 000000000000..d8cce73ea0ae --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/rockchip,rk3328-grf-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3328 General Register Files GPIO controller + +description: + The Rockchip RK3328 General Register File (GRF) outputs only the + GPIO_MUTE pin, originally for codec mute control, but it can also be used + for general purpose. It is manipulated by the GRF_SOC_CON10 register. + If needed in the future support for the HDMI pins can also be added. + The GPIO node should be declared as the child of the GRF node. + + The GPIO_MUTE pin is referred to in the format + + <&grf_gpio 0 GPIO_ACTIVE_LOW> + + The first cell is the pin number and + the second cell is used to specify the GPIO polarity + 0 = Active high + 1 = Active low + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: rockchip,rk3328-grf-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + grf_gpio: gpio { + compatible = "rockchip,rk3328-grf-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml b/Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml new file mode 100644 index 000000000000..7087e4a5013f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP GPIO controller bindings + +maintainers: + - Grygorii Strashko + +description: | + The general-purpose interface combines general-purpose input/output (GPIO) banks. + Each GPIO banks provides up to 32 dedicated general-purpose pins with input + and output capabilities; interrupt generation in active mode and wake-up + request generation in idle mode upon the detection of external events. + +properties: + compatible: + oneOf: + - enum: + - ti,omap2-gpio + - ti,omap3-gpio + - ti,omap4-gpio + - items: + - const: ti,am4372-gpio + - const: ti,omap4-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + gpio-ranges: true + + gpio-line-names: + minItems: 1 + maxItems: 32 + + ti,gpio-always-on: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicates if a GPIO bank is always powered and will never lose its logic state. + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + description: + Name of the hwmod associated with the GPIO. Needed on some legacy OMAP + SoCs which have not been converted to the ti,sysc interconnect hierarachy. + + ti,no-reset-on-init: + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + description: + Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which + have not been converted to the ti,sysc interconnect hierarachy. + +patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + + required: + - gpio-hog + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + + gpio0: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <96>; + ti,gpio-always-on; + + ls-buf-en-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; + }; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 894ba217ab32..0f73f436bea7 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - amlogic,meson-g12a-mali + - mediatek,mt8183-mali - realtek,rtd1619-mali - rockchip,px30-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -41,10 +42,13 @@ properties: mali-supply: true + sram-supply: true + operating-points-v2: true power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 resets: maxItems: 2 @@ -89,6 +93,30 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mali + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + + required: + - sram-supply + - power-domains + - power-domain-names + else: + properties: + power-domains: + maxItems: 1 + sram-supply: false examples: - | diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index 9d72264fa90a..e6485f7b046f 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -34,7 +34,6 @@ properties: - enum: [ bridge, gca ] - enum: [ bridge, gca ] minItems: 2 - maxItems: 4 interrupts: items: diff --git a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml index 3ed172629974..93e7244cdc0e 100644 --- a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml +++ b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml @@ -36,7 +36,6 @@ properties: - description: AHB/slave interface clock (only required if GPU can gate slave interface independently) minItems: 1 - maxItems: 4 clock-names: items: diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml new file mode 100644 index 000000000000..ea643e6c3ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs Device Tree Bindings + +maintainers: + - Rayn Chen + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2400-i2c-bus + - aspeed,ast2500-i2c-bus + - aspeed,ast2600-i2c-bus + + reg: + minItems: 1 + items: + - description: address offset and range of bus + - description: address offset and range of bus buffer + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + root clock of bus, should reference the APB + clock in the second cell + + resets: + maxItems: 1 + + bus-frequency: + minimum: 500 + maximum: 4000000 + default: 100000 + description: frequency of the bus clock in Hz defaults to 100 kHz when not + specified + + multi-master: + type: boolean + description: + states that there is another master active on this bus + +required: + - reg + - compatible + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + #include + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-bus"; + reg = <0x40 0x40>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + }; diff --git a/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml index edbca2476128..7070c04469ed 100644 --- a/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml @@ -21,7 +21,6 @@ properties: reg: minItems: 1 - maxItems: 2 items: - description: BSC register range - description: Auto-I2C register range diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt deleted file mode 100644 index b47f6ccb196a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt +++ /dev/null @@ -1,49 +0,0 @@ -Device tree configuration for the I2C busses on the AST24XX, AST25XX, and AST26XX SoCs. - -Required Properties: -- #address-cells : should be 1 -- #size-cells : should be 0 -- reg : address offset and range of bus -- compatible : should be "aspeed,ast2400-i2c-bus" - or "aspeed,ast2500-i2c-bus" - or "aspeed,ast2600-i2c-bus" -- clocks : root clock of bus, should reference the APB - clock in the second cell -- resets : phandle to reset controller with the reset number in - the second cell -- interrupts : interrupt number - -Optional Properties: -- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not - specified -- multi-master : states that there is another master active on this bus. - -Example: - -i2c { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x40 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt index b745f3706120..6590501c53d4 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt @@ -8,7 +8,7 @@ Required properties: - reg : Offset and length of the register set for the device - clocks: I2C functional clock phandle. For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt + Documentation/devicetree/bindings/clock/ti,sci-clk.yaml SoC-specific Required Properties: @@ -17,7 +17,7 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only: - power-domains: Should contain a phandle to a PM domain provider node and an args specifier containing the I2C device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml Recommended properties : - interrupts : standard interrupt property. diff --git a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt index 81b5d55086fa..86b2e433a969 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt @@ -27,7 +27,7 @@ Required properties: - i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C parents. -Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this +Furthermore, I2C mux properties and child nodes. See i2c-mux.yaml in this directory. Example: diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt index 7f0194fdd0cc..5ea216ae7084 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt @@ -15,6 +15,7 @@ Required properties: "mediatek,mt8173-i2c": for MediaTek MT8173 "mediatek,mt8183-i2c": for MediaTek MT8183 "mediatek,mt8192-i2c": for MediaTek MT8192 + "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195 "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516 - reg: physical base address of the controller and dma base, length of memory mapped region. @@ -32,6 +33,7 @@ Optional properties: - mediatek,have-pmic: platform can control i2c form special pmic side. Only mt6589 and mt8135 support this feature. - mediatek,use-push-pull: IO config use push-pull mode. + - vbus-supply: phandle to the regulator that provides power to SCL/SDA. Example: diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt index 21da3ecbb370..d4cf10582a26 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt @@ -22,8 +22,8 @@ Required properties: - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side port is connected to. - mux-gpios: list of gpios used to control the muxer -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. +* Standard I2C mux properties. See i2c-mux.yaml in this directory. +* I2C child bus nodes. See i2c-mux.yaml in this directory. Optional properties: - idle-state: value to set the muxer to when idle. When no value is @@ -62,7 +62,6 @@ Example: reg = <0x3c>; pwms = <&pwm 4 3000>; reset-gpios = <&gpio2 7 1>; - reset-active-low; }; }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt deleted file mode 100644 index 8b444b94e92f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt +++ /dev/null @@ -1,99 +0,0 @@ -General Purpose I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses a mux controller -from the mux subsystem to route the I2C signals. - - .-----. .-----. - | dev | | dev | - .------------. '-----' '-----' - | SoC | | | - | | .--------+--------' - | .------. | .------+ child bus A, on MUX value set to 0 - | | I2C |-|--| Mux | - | '------' | '--+---+ child bus B, on MUX value set to 1 - | .------. | | '----------+--------+--------. - | | MUX- | | | | | | - | | Ctrl |-|-----+ .-----. .-----. .-----. - | '------' | | dev | | dev | | dev | - '------------' '-----' '-----' '-----' - -Required properties: -- compatible: i2c-mux -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -- mux-controls: The phandle of the mux controller to use for operating the - mux. -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number - is also the mux-controller state described in ../mux/mux-controller.txt - -Optional properties: -- mux-locked: If present, explicitly allow unrelated I2C transactions on the - parent I2C adapter at these times: - + during setup of the multiplexer - + between setup of the multiplexer and the child bus I2C transaction - + between the child bus I2C transaction and releasing of the multiplexer - + during releasing of the multiplexer - However, I2C transactions to devices behind all I2C multiplexers connected - to the same parent adapter that this multiplexer is connected to are blocked - for the full duration of the complete multiplexed I2C transaction (i.e. - including the times covered by the above list). - If mux-locked is not present, the multiplexer is assumed to be parent-locked. - This means that no unrelated I2C transactions are allowed on the parent I2C - adapter for the complete multiplexed I2C transaction. - The properties of mux-locked and parent-locked multiplexers are discussed - in more detail in Documentation/i2c/i2c-topology.rst. - -For each i2c child node, an I2C child bus will be created. They will -be numbered based on their order in the device tree. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be set as the state in the -mux controller. - -Example: - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - i2c-mux { - compatible = "i2c-mux"; - mux-locked; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7 1>; - reset-active-low; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml new file mode 100644 index 000000000000..9b0603a72f40 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: General Purpose I2C Bus Mux + +maintainers: + - Peter Rosin + +description: |+ + This binding describes an I2C bus multiplexer that uses a mux controller + from the mux subsystem to route the I2C signals. + + .-----. .-----. + | dev | | dev | + .------------. '-----' '-----' + | SoC | | | + | | .--------+--------' + | .------. | .------+ child bus A, on MUX value set to 0 + | | I2C |-|--| Mux | + | '------' | '--+---+ child bus B, on MUX value set to 1 + | .------. | | '----------+--------+--------. + | | MUX- | | | | | | + | | Ctrl |-|-----+ .-----. .-----. .-----. + | '------' | | dev | | dev | | dev | + '------------' '-----' '-----' '-----' + + + +allOf: + - $ref: /schemas/i2c/i2c-mux.yaml# + +properties: + compatible: + const: i2c-mux + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the I2C bus that this multiplexer's master-side port is + connected to. + + mux-controls: + maxItems: 1 + description: + The mux-controller states are the I2C sub-bus numbers. + + mux-locked: + type: boolean + description: | + Explicitly allow unrelated I2C transactions on the parent I2C adapter at + these times: + - during setup of the multiplexer + - between setup of the multiplexer and the child bus I2C transaction + - between the child bus I2C transaction and releasing of the multiplexer + - during releasing of the multiplexer + + However, I2C transactions to devices behind all I2C multiplexers connected + to the same parent adapter that this multiplexer is connected to are blocked + for the full duration of the complete multiplexed I2C transaction (i.e. + including the times covered by the above list). + If mux-locked is not present, the multiplexer is assumed to be parent-locked. + This means that no unrelated I2C transactions are allowed on the parent I2C + adapter for the complete multiplexed I2C transaction. + The properties of mux-locked and parent-locked multiplexers are discussed + in more detail in Documentation/i2c/i2c-topology.rst. + +required: + - compatible + - i2c-parent + - mux-controls + +unevaluatedProperties: false + +examples: + - | + #include + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, + <&pioA 1 GPIO_ACTIVE_HIGH>; + }; + + i2c-mux { + compatible = "i2c-mux"; + mux-locked; + i2c-parent = <&i2c1>; + + mux-controls = <&mux>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt index 8b1e49cdce3f..29c4550c9782 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt @@ -8,8 +8,8 @@ Required Properties: The following required properties are defined externally: - - Standard I2C mux properties. See i2c-mux.txt in this directory. - - I2C child bus nodes. See i2c-mux.txt in this directory. + - Standard I2C mux properties. See i2c-mux.yaml in this directory. + - I2C child bus nodes. See i2c-mux.yaml in this directory. Optional Properties: diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt deleted file mode 100644 index 7abda506b828..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ /dev/null @@ -1,74 +0,0 @@ -* NXP PCA954x I2C bus switch - -The driver supports NXP PCA954x and PCA984x I2C mux/switch devices. - -Required Properties: - - - compatible: Must contain one of the following. - "nxp,pca9540", - "nxp,pca9542", - "nxp,pca9543", - "nxp,pca9544", - "nxp,pca9545", - "nxp,pca9546", "nxp,pca9846", - "nxp,pca9547", "nxp,pca9847", - "nxp,pca9548", "nxp,pca9848", - "nxp,pca9849" - - - reg: The I2C address of the device. - - The following required properties are defined externally: - - - Standard I2C mux properties. See i2c-mux.txt in this directory. - - I2C child bus nodes. See i2c-mux.txt in this directory. - -Optional Properties: - - - reset-gpios: Reference to the GPIO connected to the reset input. - - idle-state: if present, overrides i2c-mux-idle-disconnect, - Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt - - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all - children in idle state. This is necessary for example, if there are several - multiplexers on the bus and the devices behind them use same I2C addresses. - - interrupts: Interrupt mapping for IRQ. - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. - See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example: - - i2c-switch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - interrupt-parent = <&ipic>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml new file mode 100644 index 000000000000..9f1726d0356b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PCA954x I2C bus switch + +maintainers: + - Laurent Pinchart + +description: + The binding supports NXP PCA954x and PCA984x I2C mux/switch devices. + +allOf: + - $ref: /schemas/i2c/i2c-mux.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,pca9540 + - nxp,pca9542 + - nxp,pca9543 + - nxp,pca9544 + - nxp,pca9545 + - nxp,pca9546 + - nxp,pca9547 + - nxp,pca9548 + - nxp,pca9846 + - nxp,pca9847 + - nxp,pca9848 + - nxp,pca9849 + - items: + - const: nxp,pca9646 + - const: nxp,pca9546 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + reset-gpios: + maxItems: 1 + + i2c-mux-idle-disconnect: + type: boolean + description: Forces mux to disconnect all children in idle state. This is + necessary for example, if there are several multiplexers on the bus and + the devices behind them use same I2C addresses. + + idle-state: + description: if present, overrides i2c-mux-idle-disconnect + $ref: /schemas/mux/mux-controller.yaml#/properties/idle-state + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + interrupt-parent = <&ipic>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt index 33119a98e144..997a287ed3f6 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt @@ -28,9 +28,9 @@ Also required are: * Standard pinctrl properties that specify the pin mux state for each child bus. See ../pinctrl/pinctrl-bindings.txt. -* Standard I2C mux properties. See i2c-mux.txt in this directory. +* Standard I2C mux properties. See i2c-mux.yaml in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. +* I2C child bus nodes. See i2c-mux.yaml in this directory. For each named state defined in the pinctrl-names property, an I2C child bus will be created. I2C child bus numbers are assigned based on the index into diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt index de00d7fc450b..b9d9755e4172 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt @@ -7,8 +7,8 @@ Required properties: - compatible: i2c-mux-reg - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side port is connected to. -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. +* Standard I2C mux properties. See i2c-mux.yaml in this directory. +* I2C child bus nodes. See i2c-mux.yaml in this directory. Optional properties: - reg: this pair of specifies the register to control the mux. diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt deleted file mode 100644 index b38f58a1c878..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt +++ /dev/null @@ -1,73 +0,0 @@ -Common i2c bus multiplexer/switch properties. - -An i2c bus multiplexer/switch will have several child busses that are -numbered uniquely in a device dependent manner. The nodes for an i2c bus -multiplexer/switch will have one child node for each child bus. - -Optional properties: -- #address-cells = <1>; - This property is required if the i2c-mux child node does not exist. - -- #size-cells = <0>; - This property is required if the i2c-mux child node does not exist. - -- i2c-mux - For i2c multiplexers/switches that have child nodes that are a mixture - of both i2c child busses and other child nodes, the 'i2c-mux' subnode - can be used for populating the i2c child busses. If an 'i2c-mux' - subnode is present, only subnodes of this will be considered as i2c - child busses. - -Required properties for the i2c-mux child node: -- #address-cells = <1>; -- #size-cells = <0>; - -Required properties for i2c child bus nodes: -- #address-cells = <1>; -- #size-cells = <0>; -- reg : The sub-bus number. - -Optional properties for i2c child bus nodes: -- Other properties specific to the multiplexer/switch hardware. -- Child nodes conforming to i2c bus binding - - -Example : - - /* - An NXP pca9548 8 channel I2C multiplexer at address 0x70 - with two NXP pca8574 GPIO expanders attached, one each to - ports 3 and 4. - */ - - mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - gpio1: gpio@38 { - compatible = "nxp,pca8574"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - gpio2: gpio@38 { - compatible = "nxp,pca8574"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux.yaml new file mode 100644 index 000000000000..24cac36037f5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mux.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common i2c bus multiplexer/switch properties. + +maintainers: + - Peter Rosin + +description: |+ + An i2c bus multiplexer/switch will have several child busses that are numbered + uniquely in a device dependent manner. The nodes for an i2c bus + multiplexer/switch will have one child node for each child bus. + + For i2c multiplexers/switches that have child nodes that are a mixture of both + i2c child busses and other child nodes, the 'i2c-mux' subnode can be used for + populating the i2c child busses. If an 'i2c-mux' subnode is present, only + subnodes of this will be considered as i2c child busses. + +properties: + $nodename: + pattern: '^(i2c-?)?mux' + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^i2c@[0-9a-f]+$': + $ref: /schemas/i2c/i2c-controller.yaml + unevaluatedProperties: false + + properties: + reg: + description: The mux selector sub-bus number for the child I2C bus. + maxItems: 1 + +additionalProperties: true + +examples: + - | + /* + * An NXP pca9548 8 channel I2C multiplexer at address 0x70 + * with two NXP pca8574 GPIO expanders attached, one each to + * ports 3 and 4. + */ + i2c { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt deleted file mode 100644 index a425b91af48f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt +++ /dev/null @@ -1,37 +0,0 @@ -I2C for OMAP platforms - -Required properties : -- compatible : Must be - "ti,omap2420-i2c" for OMAP2420 SoCs - "ti,omap2430-i2c" for OMAP2430 SoCs - "ti,omap3-i2c" for OMAP3 SoCs - "ti,omap4-i2c" for OMAP4+ SoCs - "ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs - "ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs - "ti,am64-i2c", "ti,omap4-i2c" for AM64 SoCs -- ti,hwmods : Must be "i2c", n being the instance number (1-based) -- #address-cells = <1>; -- #size-cells = <0>; - -Recommended properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise - the default 100 kHz frequency will be used. - -Optional properties: -- Child nodes conforming to i2c bus binding - -Note: Current implementation will fetch base address, irq and dma -from omap hwmod data base during device registration. -Future plan is to migrate hwmod data base contents into device tree -blob so that, all the required data will be used from device tree dts -file. - -Examples : - -i2c1: i2c@0 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt index 569b16248514..1ff6f8487a2d 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt @@ -71,7 +71,7 @@ This is an example which is used on FalconFalls: /* This I2C controller has one gpio controller */ gpio@26 { #gpio-cells = <2>; - compatible = "ti,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; }; @@ -85,7 +85,7 @@ This is an example which is used on FalconFalls: gpio@26 { #gpio-cells = <2>; - compatible = "ti,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt index c6668b7c66e6..7b9fc0c22eaf 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt @@ -9,6 +9,7 @@ PROPERTIES: "qcom,msm8916-cci" "qcom,msm8996-cci" "qcom,sdm845-cci" + "qcom,sm8250-cci" - reg Usage: required @@ -41,8 +42,8 @@ PROPERTIES: SUBNODES: -The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and -sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996, +sdm845 and sm8250), described as subdevices named "i2c-bus@0" and "i2c-bus@1". PROPERTIES: diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml index 7f254d79558c..5339dd4fc370 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -36,6 +36,7 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3568-i2c - const: rockchip,rk3399-i2c reg: diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index df41f72afc87..b864916e087f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -89,8 +89,11 @@ wants to support one of the below features, it should adapt these bindings. - smbus states that additional SMBus restrictions and features apply to this bus. - Examples of features are SMBusHostNotify and SMBusAlert. Examples of - restrictions are more reserved addresses and timeout definitions. + An example of feature is SMBusHostNotify. Examples of restrictions are + more reserved addresses and timeout definitions. + +- smbus-alert + states that the optional SMBus-Alert feature apply to this bus. Required properties (per child device) -------------------------------------- diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index eb72dd571def..f771c09aabfc 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -43,14 +43,12 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: Reference clock for the I2C bus - description: Bus clock (Only for Armada 7K/8K) clock-names: minItems: 1 - maxItems: 2 items: - const: core - const: reg diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml index d2b401d062b9..93198d5d43a6 100644 --- a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml +++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml @@ -20,7 +20,6 @@ properties: reg: minItems: 3 - maxItems: 4 items: - description: Smbus block registers - description: Cause master registers diff --git a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt deleted file mode 100644 index 5762d2d1ab9c..000000000000 --- a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt +++ /dev/null @@ -1,67 +0,0 @@ -I2C for R-Car platforms - -Required properties: -- compatible: - "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC. - "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. - "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC. - "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. - "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC. - "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. - "renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC. - "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC. - "renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC. - "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. - "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. - "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. - "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC. - "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC. - "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC. - "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. - "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. - "renesas,i2c-r8a7796" if the device is a part of a R8A77960 SoC. - "renesas,i2c-r8a77961" if the device is a part of a R8A77961 SoC. - "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC. - "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. - "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC. - "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC. - "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. - "renesas,i2c-r8a779a0" if the device is a part of a R8A779A0 SoC. - "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. - "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible - device. - "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 or RZ/G2 compatible - device. - "renesas,i2c-rcar" (deprecated) - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first followed - by the generic version. - -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt specifier. - -Optional properties: -- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this - property indicates the default frequency 100 kHz. -- clocks: clock specifier. -- dmas: Must contain a list of two references to DMA specifiers, one for - transmission, and one for reception. -- dma-names: Must contain a list of two DMA names, "tx" and "rx". - -- i2c-scl-falling-time-ns: see i2c.txt -- i2c-scl-internal-delay-ns: see i2c.txt -- i2c-scl-rising-time-ns: see i2c.txt - -Examples : - -i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt b/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt deleted file mode 100644 index 5ed1ea1c7e14..000000000000 --- a/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt +++ /dev/null @@ -1,22 +0,0 @@ -Device tree configuration for Renesas EMEV2 IIC controller - -Required properties: -- compatible : "renesas,iic-emev2" -- reg : address start and address range size of device -- interrupts : specifier for the IIC controller interrupt -- clocks : phandle to the IP core SCLK -- clock-names : must be "sclk" -- #address-cells : should be <1> -- #size-cells : should be <0> - -Example: - - iic0: i2c@e0070000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe0070000 0x28>; - interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; - clocks = <&iic0_sclk>; - clock-names = "sclk"; - }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml b/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml new file mode 100644 index 000000000000..17c1102562be --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,iic-emev2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile EV2 IIC Interface + +maintainers: + - Wolfram Sang + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: renesas,iic-emev2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: sclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + iic0: i2c@e0070000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe0070000 0x28>; + interrupts = ; + clocks = <&iic0_sclk>; + clock-names = "sclk"; + }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,iic.txt b/Documentation/devicetree/bindings/i2c/renesas,iic.txt deleted file mode 100644 index 93d412832e66..000000000000 --- a/Documentation/devicetree/bindings/i2c/renesas,iic.txt +++ /dev/null @@ -1,72 +0,0 @@ -Device tree configuration for Renesas IIC (sh_mobile) driver - -Required properties: -- compatible : - - "renesas,iic-r8a73a4" (R-Mobile APE6) - - "renesas,iic-r8a7740" (R-Mobile A1) - - "renesas,iic-r8a7742" (RZ/G1H) - - "renesas,iic-r8a7743" (RZ/G1M) - - "renesas,iic-r8a7744" (RZ/G1N) - - "renesas,iic-r8a7745" (RZ/G1E) - - "renesas,iic-r8a774a1" (RZ/G2M) - - "renesas,iic-r8a774b1" (RZ/G2N) - - "renesas,iic-r8a774c0" (RZ/G2E) - - "renesas,iic-r8a774e1" (RZ/G2H) - - "renesas,iic-r8a7790" (R-Car H2) - - "renesas,iic-r8a7791" (R-Car M2-W) - - "renesas,iic-r8a7792" (R-Car V2H) - - "renesas,iic-r8a7793" (R-Car M2-N) - - "renesas,iic-r8a7794" (R-Car E2) - - "renesas,iic-r8a7795" (R-Car H3) - - "renesas,iic-r8a7796" (R-Car M3-W) - - "renesas,iic-r8a77961" (R-Car M3-W+) - - "renesas,iic-r8a77965" (R-Car M3-N) - - "renesas,iic-r8a77990" (R-Car E3) - - "renesas,iic-sh73a0" (SH-Mobile AG5) - - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 - compatible device) - - "renesas,rcar-gen3-iic" (generic R-Car Gen3 or RZ/G2 - compatible device) - - "renesas,rmobile-iic" (generic device) - - When compatible with a generic R-Car version, nodes - must list the SoC-specific version corresponding to - the platform first followed by the generic R-Car - version. - - When compatible with "renesas,rmobile-iic" it should - be the last compatibility string listed. - - The r8a77990 (R-Car E3) and r8a774c0 (RZ/G2E) - controllers are not considered compatible with - "renesas,rcar-gen3-iic" or "renesas,rmobile-iic" - due to the absence of automatic transmission registers. - -- reg : address start and address range size of device -- interrupts : interrupt of device -- clocks : clock for device -- #address-cells : should be <1> -- #size-cells : should be <0> - -Optional properties: -- clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset. -- dmas : Must contain a list of two references to DMA - specifiers, one for transmission, and one for - reception. -- dma-names : Must contain a list of two DMA names, "tx" and "rx". - - -Pinctrl properties might be needed, too. See there. - -Example: - - iic0: i2c@e6500000 { - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml new file mode 100644 index 000000000000..052aad44e781 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car I2C Controller + +maintainers: + - Wolfram Sang + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,i2c-r8a7778 # R-Car M1A + - renesas,i2c-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-i2c # R-Car Gen1 + + - items: + - enum: + - renesas,i2c-r8a7742 # RZ/G1H + - renesas,i2c-r8a7743 # RZ/G1M + - renesas,i2c-r8a7744 # RZ/G1N + - renesas,i2c-r8a7745 # RZ/G1E + - renesas,i2c-r8a77470 # RZ/G1C + - renesas,i2c-r8a7790 # R-Car H2 + - renesas,i2c-r8a7791 # R-Car M2-W + - renesas,i2c-r8a7792 # R-Car V2H + - renesas,i2c-r8a7793 # R-Car M2-N + - renesas,i2c-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1 + + - items: + - enum: + - renesas,i2c-r8a774a1 # RZ/G2M + - renesas,i2c-r8a774b1 # RZ/G2N + - renesas,i2c-r8a774c0 # RZ/G2E + - renesas,i2c-r8a774e1 # RZ/G2H + - renesas,i2c-r8a7795 # R-Car H3 + - renesas,i2c-r8a7796 # R-Car M3-W + - renesas,i2c-r8a77961 # R-Car M3-W+ + - renesas,i2c-r8a77965 # R-Car M3-N + - renesas,i2c-r8a77970 # R-Car V3M + - renesas,i2c-r8a77980 # R-Car V3H + - renesas,i2c-r8a77990 # R-Car E3 + - renesas,i2c-r8a77995 # R-Car D3 + - renesas,i2c-r8a779a0 # R-Car V3U + - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: + Desired I2C bus clock frequency in Hz. The absence of this property + indicates the default frequency 100 kHz. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + + i2c-scl-falling-time-ns: + default: 35 + description: + Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C + specification. + + i2c-scl-internal-delay-ns: + default: 50 + description: + Number of nanoseconds the IP core additionally needs to setup SCL. + + i2c-scl-rising-time-ns: + default: 200 + description: + Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C + specification. + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - '#address-cells' + - '#size-cells' + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen1-i2c + - renesas,rcar-gen2-i2c + then: + properties: + dmas: false + dma-names: false + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-i2c + - renesas,rcar-gen3-i2c + then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; + reg = <0xe6508000 0x40>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.txt b/Documentation/devicetree/bindings/i2c/renesas,riic.txt deleted file mode 100644 index e26fe3ad86a9..000000000000 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.txt +++ /dev/null @@ -1,32 +0,0 @@ -Device tree configuration for Renesas RIIC driver - -Required properties: -- compatible : - "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC. - "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC. - "renesas,riic-rz" for a generic RZ/A compatible device. -- reg : address start and address range size of device -- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI) -- clock-frequency : frequency of bus clock in Hz -- #address-cells : should be <1> -- #size-cells : should be <0> - -Pinctrl properties might be needed, too. See there. - -Example: - - i2c0: i2c@fcfee000 { - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, - <0 158 IRQ_TYPE_EDGE_RISING>, - <0 159 IRQ_TYPE_EDGE_RISING>, - <0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 164 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml new file mode 100644 index 000000000000..52d92ec7ec0b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,riic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC) + +maintainers: + - Chris Brandt + - Wolfram Sang + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,riic-r7s72100 # RZ/A1H + - renesas,riic-r7s9210 # RZ/A2M + - renesas,riic-r9a07g044 # RZ/G2{L,LC} + - const: renesas,riic-rz # RZ/A or RZ/G2L + + reg: + maxItems: 1 + + interrupts: + items: + - description: Transmit End Interrupt (TEI) + - description: Receive Data Full Interrupt (RI) + - description: Transmit Data Empty Interrupt (TI) + - description: Stop Condition Detection Interrupt (SPI) + - description: Start Condition Detection Interrupt (STI) + - description: NACK Reception Interrupt (NAKI) + - description: Arbitration-Lost Interrupt (ALI) + - description: Timeout Interrupt (TMOI) + + clock-frequency: + description: + Desired I2C bus clock frequency in Hz. The absence of this property + indicates the default frequency 100 kHz. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-frequency + - power-domains + - '#address-cells' + - '#size-cells' + +if: + properties: + compatible: + contains: + enum: + - renesas,riic-r9a07g044 +then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c0: i2c@fcfee000 { + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml b/Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml new file mode 100644 index 000000000000..04e4ffd80bc0 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,rmobile-iic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Mobile I2C Bus Interface (IIC) + +maintainers: + - Wolfram Sang + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,iic-r8a73a4 # R-Mobile APE6 + - renesas,iic-r8a7740 # R-Mobile A1 + - renesas,iic-sh73a0 # SH-Mobile AG5 + - const: renesas,rmobile-iic # Generic + + - items: + - enum: + - renesas,iic-r8a7742 # RZ/G1H + - renesas,iic-r8a7743 # RZ/G1M + - renesas,iic-r8a7744 # RZ/G1N + - renesas,iic-r8a7745 # RZ/G1E + - renesas,iic-r8a7790 # R-Car H2 + - renesas,iic-r8a7791 # R-Car M2-W + - renesas,iic-r8a7792 # R-Car V2H + - renesas,iic-r8a7793 # R-Car M2-N + - renesas,iic-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-iic # R-Car Gen2 and RZ/G1 + - const: renesas,rmobile-iic # Generic + + - items: + - enum: + - renesas,iic-r8a774a1 # RZ/G2M + - renesas,iic-r8a774b1 # RZ/G2N + - renesas,iic-r8a774c0 # RZ/G2E + - renesas,iic-r8a774e1 # RZ/G2H + - renesas,iic-r8a7795 # R-Car H3 + - renesas,iic-r8a7796 # R-Car M3-W + - renesas,iic-r8a77961 # R-Car M3-W+ + - renesas,iic-r8a77965 # R-Car M3-N + - renesas,iic-r8a77990 # R-Car E3 + - const: renesas,rcar-gen3-iic # R-Car Gen3 and RZ/G2 + - const: renesas,rmobile-iic # Generic + + reg: + maxItems: 1 + + interrupts: true + + clock-frequency: + description: + Desired I2C bus clock frequency in Hz. The absence of this property + indicates the default frequency 100 kHz. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - '#address-cells' + - '#size-cells' + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,iic-r8a7740 + - renesas,iic-sh73a0 + then: + properties: + interrupts: + items: + - description: Arbitration Lost Interrupt (ALI) + - description: Non-acknowledge Detection Interrupt (TACKI) + - description: Wait Interrupt (WAITI) + - description: Data Transmit Enable interrupt (DTEI) + else: + properties: + interrupts: + items: + - description: Single combined interrupt + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-iic + - renesas,rcar-gen3-iic + then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + iic0: i2c@e6500000 { + compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0xe6500000 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + clock-frequency = <400000>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml b/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml new file mode 100644 index 000000000000..ff165ad1bee8 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ti,omap4-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for I2C controllers on TI's OMAP and K3 SoCs + +maintainers: + - Vignesh Raghavendra + +properties: + compatible: + oneOf: + - enum: + - ti,omap2420-i2c + - ti,omap2430-i2c + - ti,omap3-i2c + - ti,omap4-i2c + - items: + - enum: + - ti,am4372-i2c + - ti,am64-i2c + - ti,am654-i2c + - ti,j721e-i2c + - const: ti,omap4-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + clock-frequency: true + + power-domains: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + ti,hwmods: + description: + Must be "i2c", n being the instance number (1-based). + This property is applicable only on legacy platforms mainly omap2/3 + and ti81xx and should not be used on other platforms. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +# subnode's properties +patternProperties: + "@[0-9a-f]+$": + type: object + description: + Flash device uses the below defined properties in the subnode. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +if: + properties: + compatible: + oneOf: + - const: ti,omap2420-i2c + - const: ti,omap2430-i2c + - const: ti,omap3-i2c + - const: ti,omap4-i2c + +then: + properties: + ti,hwmods: + items: + - pattern: "^i2c([1-9])$" + +else: + properties: + ti,hwmods: false + +examples: + - | + #include + #include + + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x2000000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml new file mode 100644 index 000000000000..6f8f8a6258fe --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/adi,adis16201.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADIS16201 Dual Axis Inclinometer and similar + +maintainers: + - Jonathan Cameron + +description: | + Two similar parts from external interface point of view. + SPI interface. + https://www.analog.com/en/products/adis16201.html + https://www.analog.com/en/products/adis16209.html + +properties: + compatible: + enum: + - adi,adis16201 + - adi,adis16209 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: true + + vdd-supply: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@0 { + compatible = "adi,adis16201"; + reg = <0>; + spi-max-frequency = <2500000>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma180.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma180.yaml index 45b3abde298f..a7e84089cc3d 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma180.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma180.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/accel/bosch,bma180.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial accelerometers +title: Bosch BMA023 / BMA150/ BMA180 / BMA250 / SMB380 triaxial accelerometers maintainers: - Jonathan Cameron @@ -21,7 +21,6 @@ properties: - bosch,bma150 - bosch,bma180 - bosch,bma250 - - bosch,bma254 - bosch,smb380 reg: diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml new file mode 100644 index 000000000000..942b23ad0712 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/bosch,bma220.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch BMA220 Trixial Acceleration Sensor + +maintainers: + - Jonathan Cameron + +properties: + compatible: + enum: + - bosch,bma220 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: true + + vdda-supply: true + vddd-supply: true + vddio-supply: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@0 { + compatible = "bosch,bma220"; + reg = <0>; + spi-max-frequency = <2500000>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml index c2efbb813ca2..e830d5295b92 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml @@ -18,6 +18,8 @@ properties: enum: - bosch,bmc150_accel - bosch,bmi055_accel + - bosch,bma253 + - bosch,bma254 - bosch,bma255 - bosch,bma250e - bosch,bma222 @@ -31,7 +33,12 @@ properties: vddio-supply: true interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + The first interrupt listed must be the one connected to the INT1 pin, + the second (optional) interrupt listed must be the one connected to the + INT2 pin (if available). mount-matrix: description: an optional 3x3 mounting rotation matrix. diff --git a/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml b/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml new file mode 100644 index 000000000000..7c8f8bdc2333 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/fsl,mma7455.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MMA7455 and MMA7456 three axis accelerometers + +maintainers: + - Joachim Eastwood + - Jonathan Cameron + +description: + Devices support both SPI and I2C interfaces. + +properties: + compatible: + enum: + - fsl,mma7455 + - fsl,mma7456 + reg: + maxItems: 1 + + avdd-supply: true + vddio-supply: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + description: + Data ready is only available on INT1, but events can use either or + both pins. If not specified, first element assumed to correspond + to INT1 and second (where present) to INT2. + minItems: 1 + maxItems: 2 + items: + enum: + - "INT1" + - "INT2" + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + # include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@18 { + compatible = "fsl,mma7455"; + reg = <0x18>; + vddio-supply = <&iovdd>; + avdd-supply = <&avdd>; + interrupts = <57 IRQ_TYPE_EDGE_FALLING>, <58 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT2", "INT1"; + }; + }; + - | + # include + spi { + #address-cells = <1>; + #size-cells = <0>; + accelerometer@0 { + compatible = "fsl,mma7456"; + reg = <0>; + spi-max-frequency = <10000000>; + vddio-supply = <&iovdd>; + avdd-supply = <&avdd>; + interrupts = <57 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT1"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml index fbb714431e3d..52fa0f7c2d0e 100644 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml +++ b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml @@ -16,6 +16,7 @@ properties: - kionix,kxcj91008 - kionix,kxtj21009 - kionix,kxtf9 + - kionix,kx023-1025 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml new file mode 100644 index 000000000000..55fd3548e3b6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/murata,sca3300.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Murata SCA3300 Accelerometer + +description: | + 3-axis industrial accelerometer with digital SPI interface + https://www.murata.com/en-global/products/sensor/accel/sca3300 + +maintainers: + - Tomas Melin + +properties: + compatible: + enum: + - murata,sca3300 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 8000000 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + accelerometer@0 { + compatible = "murata,sca3300"; + reg = <0x0>; + spi-max-frequency = <4000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml new file mode 100644 index 000000000000..ad529ab2c6e2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/nxp,fxls8962af.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP FXLS8962AF/FXLS8964AF Accelerometer driver + +maintainers: + - Sean Nyekjaer + +description: | + NXP FXLS8962AF/FXLS8964AF Accelerometer driver that supports + SPI and I2C interface. + https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf + https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf + +properties: + compatible: + enum: + - nxp,fxls8962af + - nxp,fxls8964af + + reg: + maxItems: 1 + + vdd-supply: + description: phandle to the regulator that provides power to the accelerometer + + spi-max-frequency: true + + interrupts: + maxItems: 1 + + interrupt-names: + enum: + - INT1 + - INT2 + + drive-open-drain: + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a I2C device node */ + accelerometer@62 { + compatible = "nxp,fxls8962af"; + reg = <0x62>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; + }; + - | + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a SPI device node */ + accelerometer@0 { + compatible = "nxp,fxls8962af"; + reg = <0>; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adc.yaml b/Documentation/devicetree/bindings/iio/adc/adc.yaml index 912a7635edc4..db348fcbb52c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adc.yaml @@ -39,4 +39,16 @@ properties: The first value specifies the positive input pin, the second specifies the negative input pin. + settling-time-us: + description: + Time between enabling the channel and first stable readings. + + oversampling-ratio: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Oversampling is used as replacement of or addition to the low-pass filter. + In some cases, the desired filtering characteristics are a function the + device design and can interact with other characteristics such as + settling time. + additionalProperties: true diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7298.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7298.yaml new file mode 100644 index 000000000000..ca414bb396c5 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7298.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7298.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7298 ADC + +maintainers: + - Michael Hennerich + +description: | + Bindings for the Analog Devices AD7298 ADC device. Datasheet can be + found here: + https://www.analog.com/en/products/ad7298.html + +properties: + compatible: + const: adi,ad7298 + + reg: + maxItems: 1 + + vref-supply: true + vdd-supply: true + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7298"; + reg = <0>; + spi-max-frequency = <5000000>; + vref-supply = <&adc_vref>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml new file mode 100644 index 000000000000..cf711082ad7d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7476.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AD7476 and similar simple SPI ADCs from multiple manufacturers. + +maintainers: + - Michael Hennerich + +description: | + A lot of simple SPI ADCs have very straight forward interfaces. + They typically don't provide a MOSI pin, simply reading out data + on MISO when the clock toggles. + +properties: + compatible: + enum: + - adi,ad7091 + - adi,ad7091r + - adi,ad7273 + - adi,ad7274 + - adi,ad7276 + - adi,ad7277 + - adi,ad7278 + - adi,ad7466 + - adi,ad7467 + - adi,ad7468 + - adi,ad7475 + - adi,ad7476 + - adi,ad7476a + - adi,ad7477 + - adi,ad7477a + - adi,ad7478 + - adi,ad7478a + - adi,ad7495 + - adi,ad7910 + - adi,ad7920 + - adi,ad7940 + - ti,adc081s + - ti,adc101s + - ti,adc121s + - ti,ads7866 + - ti,ads7867 + - ti,ads7868 + - lltc,ltc2314-14 + + reg: + maxItems: 1 + + vcc-supply: + description: + Main powersupply voltage for the chips, sometimes referred to as VDD on + datasheets. If there is no separate vref-supply, then this is needed + to establish channel scaling. + + vdrive-supply: + description: + Some devices have separate supply for their digital control side. + + vref-supply: + description: + Some devices have a specific reference voltage supplied on a different pin + to the other supplies. Needed to be able to establish channel scaling + unless there is also an internal reference available (e.g. ad7091r) + + spi-max-frequency: true + + adi,conversion-start-gpios: + description: A GPIO used to trigger the start of a conversion + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +allOf: + # Devices where reference is vcc + - if: + properties: + compatible: + contains: + enum: + - adi,ad7091 + - adi,ad7276 + - adi,ad7277 + - adi,ad7278 + - adi,ad7466 + - adi,ad7467 + - adi,ad7468 + - adi,ad7940 + - ti,adc081s + - ti,adc101s + - ti,adc121s + - ti,ads7866 + - ti,ads7868 + required: + - vcc-supply + # Devices with a vref + - if: + properties: + compatible: + contains: + enum: + - adi,ad7091r + - adi,ad7273 + - adi,ad7274 + - adi,ad7475 + - lltc,ltc2314-14 + then: + properties: + vref-supply: true + else: + properties: + vref-supply: false + # Devices with a vref where it is not optional + - if: + properties: + compatible: + contains: + enum: + - adi,ad7273 + - adi,ad7274 + - adi,ad7475 + - lltc,ltc2314-14 + then: + required: + - vref-supply + - if: + properties: + compatible: + contains: + enum: + - adi,ad7475 + - adi,ad7495 + then: + properties: + vdrive-supply: true + else: + properties: + vdrive-supply: false + - if: + properties: + compatible: + contains: + enum: + - adi,ad7091 + - adi,ad7091r + then: + properties: + adi,conversion-start-gpios: true + else: + properties: + adi,conversion-start-gpios: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7091r"; + reg = <0>; + spi-max-frequency = <5000000>; + vcc-supply = <&adc_vcc>; + vref-supply = <&adc_vref>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml index 3be8955587e4..7e8328e9ce13 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml @@ -41,7 +41,6 @@ properties: clock-names: minItems: 2 - maxItems: 4 items: - const: clkin - const: core diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1e7894e524f9..733351dee252 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -38,14 +38,12 @@ properties: dfsdm clock can also feed CLKOUT, when CLKOUT is used. - description: audio clock can be used as an alternate to feed CLKOUT. minItems: 1 - maxItems: 2 clock-names: items: - const: dfsdm - const: audio minItems: 1 - maxItems: 2 "#address-cells": const: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml new file mode 100644 index 000000000000..601d69971d84 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,tsc2046.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TSC2046 touch screen controller. + +maintainers: + - Oleksij Rempel + +description: | + TSC2046 is a touch screen controller with 8 channels ADC. + +properties: + compatible: + enum: + - ti,tsc2046e-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: true + + "#io-channel-cells": + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + +patternProperties: + "^channel@[0-7]$": + $ref: "adc.yaml" + type: object + + properties: + reg: + description: | + The channel number. It can have up to 8 channels + items: + minimum: 0 + maximum: 7 + + settling-time-us: true + oversampling-ratio: true + + required: + - reg + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.yaml b/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.yaml index 90439a8dc785..f8a112c9a822 100644 --- a/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.yaml +++ b/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.yaml @@ -24,6 +24,9 @@ properties: description: | Channel node of a voltage io-channel. + "#io-channel-cells": + const: 0 + shunt-resistor-micro-ohms: description: The shunt resistance. @@ -57,6 +60,7 @@ examples: sysi { compatible = "current-sense-shunt"; io-channels = <&tiadc 0>; + #io-channel-cells = <0>; /* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */ shunt-resistor-micro-ohms = <3300000>; diff --git a/Documentation/devicetree/bindings/iio/cdc/adi,ad7746.yaml b/Documentation/devicetree/bindings/iio/cdc/adi,ad7746.yaml new file mode 100644 index 000000000000..a02036ef9e8d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/cdc/adi,ad7746.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/cdc/adi,ad7746.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AD7746 24-Bit Capacitance-to-Digital Converter with Temperature Sensor + +maintainers: + - Michael Hennerich + +description: | + AD7746 24-Bit Capacitance-to-Digital Converter with Temperature Sensor + + Specifications about the part can be found at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad7291.pdf + +properties: + compatible: + enum: + - adi,ad7745 + - adi,ad7746 + - adi,ad7747 + + reg: + maxItems: 1 + + adi,excitation-vdd-permille: + description: | + Set VDD per mille to be used as the excitation voltage. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [125, 250, 375, 500] + + adi,exca-output-en: + description: Enables the EXCA pin as the excitation output. + type: boolean + + adi,exca-output-invert: + description: | + Inverts the excitation output in the EXCA pin. + Normally only one of the EXCX pins would be inverted, check the following + application notes for more details + https://www.analog.com/media/en/technical-documentation/application-notes/AN-1585.pdf + type: boolean + + adi,excb-output-en: + description: Enables the EXCB pin as the excitation output. + type: boolean + + adi,excb-output-invert: + description: Inverts the excitation output in the EXCB pin. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ad7746: cdc@48 { + compatible = "adi,ad7746"; + reg = <0x48>; + adi,excitation-vdd-permille = <125>; + + adi,exca-output-en; + adi,exca-output-invert; + adi,excb-output-en; + adi,excb-output-invert; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml index a93d1972a5c2..967500b7e773 100644 --- a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml @@ -22,7 +22,6 @@ properties: required: - compatible - - reg additionalProperties: false @@ -37,5 +36,11 @@ examples: reg = <0x69>; }; }; + - | + serial { + air-pollution-sensor { + compatible = "sensirion,sps30"; + }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/ad5755.txt b/Documentation/devicetree/bindings/iio/dac/ad5755.txt deleted file mode 100644 index 502e1e55adbd..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ad5755.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver - -Required properties: - - compatible: Has to contain one of the following: - adi,ad5755 - adi,ad5755-1 - adi,ad5757 - adi,ad5735 - adi,ad5737 - - - reg: spi chip select number for the device - - spi-cpha or spi-cpol: is the only modes that is supported - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -See include/dt-bindings/iio/ad5755.h - - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an - external resistor and thereby bypasses - the internal compensation resistor. - - adi,dc-dc-phase: - Valid values for DC DC Phase control is: - 0: All dc-to-dc converters clock on the same edge. - 1: Channel A and Channel B clock on the same edge, - Channel C and Channel D clock on opposite edges. - 2: Channel A and Channel C clock on the same edge, - Channel B and Channel D clock on opposite edges. - 3: Channel A, Channel B, Channel C, and Channel D - clock 90 degrees out of phase from each other. - - adi,dc-dc-freq-hz: - Valid values for DC DC frequency is [Hz]: - 250000 - 410000 - 650000 - - adi,dc-dc-max-microvolt: - Valid values for the maximum allowed Vboost voltage supplied by - the dc-to-dc converter is: - 23000000 - 24500000 - 27000000 - 29500000 - -Optional for every channel: - - adi,mode: - Valid values for DAC modes is: - 0: 0 V to 5 V voltage range. - 1: 0 V to 10 V voltage range. - 2: Plus minus 5 V voltage range. - 3: Plus minus 10 V voltage range. - 4: 4 mA to 20 mA current range. - 5: 0 mA to 20 mA current range. - 6: 0 mA to 24 mA current range. - - adi,ext-current-sense-resistor: boolean set if the hardware a external - current sense resistor. - - adi,enable-voltage-overrange: boolean enable voltage overrange - - adi,slew: Array of slewrate settings should contain 3 fields: - 1: Should be either 0 or 1 in order to enable or disable slewrate. - 2: Slew rate settings: - Valid values for the slew rate update frequency: - 64000 - 32000 - 16000 - 8000 - 4000 - 2000 - 1000 - 500 - 250 - 125 - 64 - 32 - 16 - 8 - 4 - 0 - 3: Slew step size: - Valid values for the step size LSBs: - 1 - 2 - 4 - 16 - 32 - 64 - 128 - 256 - -Example: -dac@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "adi,ad5755"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - adi,dc-dc-phase = <0>; - adi,dc-dc-freq-hz = <410000>; - adi,dc-dc-max-microvolt = <23000000>; - channel@0 { - reg = <0>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@1 { - reg = <1>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@2 { - reg = <2>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@3 { - reg = <3>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml new file mode 100644 index 000000000000..be419ac46caa --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5755.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5755 Multi-Channel DAC + +maintainers: + - Sean Nyekjaer + +properties: + compatible: + enum: + - adi,ad5755 + - adi,ad5755-1 + - adi,ad5757 + - adi,ad5735 + - adi,ad5737 + + reg: + maxItems: 1 + + spi-cpha: + description: Either this or spi-cpol but not both. + spi-cpol: true + + spi-max-frequency: true + + adi,ext-dc-dc-compenstation-resistor: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set if the hardware have an external resistor and thereby bypasses + the internal compensation resistor. + + adi,dc-dc-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Valid values for DC DC Phase control is: + 0: All dc-to-dc converters clock on the same edge. + 1: Channel A and Channel B clock on the same edge, + Channel C and Channel D clock on opposite edges. + 2: Channel A and Channel C clock on the same edge, + Channel B and Channel D clock on opposite edges. + 3: Channel A, Channel B, Channel C, and Channel D + clock 90 degrees out of phase from each other. + + adi,dc-dc-freq-hz: + enum: [250000, 410000, 650000] + + adi,dc-dc-max-microvolt: + description: + Maximum allowed Vboost voltage supplied by the dc-to-dc converter. + enum: [23000000, 24500000, 27000000, 29500000] + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "^channel@[0-7]$": + type: object + description: Child node to describe a channel + properties: + reg: + maxItems: 1 + + adi,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + description: | + Valid values for DAC modes is: + 0: 0 V to 5 V voltage range. + 1: 0 V to 10 V voltage range. + 2: Plus minus 5 V voltage range. + 3: Plus minus 10 V voltage range. + 4: 4 mA to 20 mA current range. + 5: 0 mA to 20 mA current range. + 6: 0 mA to 24 mA current range. + + adi,ext-current-sense-resistor: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set if the hardware has an external current sense resistor + + adi,enable-voltage-overrange: + $ref: /schemas/types.yaml#/definitions/flag + description: Enable voltage overrange + + adi,slew: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Array of slewrate settings should contain 3 fields: + 1: Should be either 0 or 1 in order to enable or disable slewrate. + 2: Slew rate update frequency + 3: Slew step size + items: + - enum: [0, 1] + - enum: [64000, 32000, 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 64, 32, 16, 8, 4, 0] + - enum: [1, 2, 4, 16, 32, 64, 128, 256] + + required: + - reg + + additionalProperties: false + +oneOf: + - required: + - spi-cpha + - required: + - spi-cpol + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad5755"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + adi,dc-dc-phase = <0>; + adi,dc-dc-freq-hz = <410000>; + adi,dc-dc-max-microvolt = <23000000>; + channel@0 { + reg = <0>; + adi,mode = <4>; + adi,ext-current-sense-resistor; + adi,slew = <0 64000 1>; + }; + channel@1 { + reg = <1>; + adi,mode = <4>; + adi,ext-current-sense-resistor; + adi,slew = <0 64000 1>; + }; + channel@2 { + reg = <2>; + adi,mode = <4>; + adi,ext-current-sense-resistor; + adi,slew = <0 64000 1>; + }; + channel@3 { + reg = <3>; + adi,mode = <4>; + adi,ext-current-sense-resistor; + adi,slew = <0 64000 1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac082s085.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac082s085.yaml new file mode 100644 index 000000000000..b0157050f1ee --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac082s085.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/ti,dac082s085.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DAC082s085 and similar DACs + +description: + A family of Texas Instruments 8/10/12-bit 2/4-channel DACs + +maintainers: + - Lukas Wunner + +properties: + compatible: + enum: + - ti,dac082s085 + - ti,dac102s085 + - ti,dac122s085 + - ti,dac084s085 + - ti,dac104s085 + - ti,dac124s085 + + reg: + maxItems: 1 + + spi-cpha: true + spi-cpol: + description: + Must be either spi-cpha, or spi-cpol but not both. + + vref-supply: + description: Needed to provide output scaling. + + spi-max-frequency: true + +required: + - compatible + - reg + - vref-supply + +additionalProperties: false + +oneOf: + - required: + - spi-cpha + - required: + - spi-cpol + +examples: + - | + vref_2v5_reg: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "ti,dac082s085"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-cpol; + vref-supply = <&vref_2v5_reg>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt b/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt deleted file mode 100644 index 9cb0e10df704..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt +++ /dev/null @@ -1,34 +0,0 @@ -Texas Instruments 8/10/12-bit 2/4-channel DAC driver - -Required properties: - - compatible: Must be one of: - "ti,dac082s085" - "ti,dac102s085" - "ti,dac122s085" - "ti,dac084s085" - "ti,dac104s085" - "ti,dac124s085" - - reg: Chip select number. - - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify - either spi-cpha or spi-cpol (but not both). - - vref-supply: Phandle to the external reference voltage supply. - -For other required and optional properties of SPI slave nodes please refer to -../../spi/spi-bus.txt. - -Example: - vref_2v5_reg: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - dac@0 { - compatible = "ti,dac082s085"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-cpol; - vref-supply = <&vref_2v5_reg>; - }; diff --git a/Documentation/devicetree/bindings/iio/light/amstaos,tsl2591.yaml b/Documentation/devicetree/bindings/iio/light/amstaos,tsl2591.yaml new file mode 100644 index 000000000000..83b88c6a243d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/amstaos,tsl2591.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/amstaos,tsl2591.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMS/TAOS TSL2591 Ambient Light Sensor (ALS) + +maintainers: + - Joe Sandom + +description: | + AMS/TAOS TSL2591 is a very-high sensitivity + light-to-digital converter that transforms light intensity into a digital + signal. + +properties: + compatible: + const: amstaos,tsl2591 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + Interrupt (INT:Pin 2) Active low. Should be set to IRQ_TYPE_EDGE_FALLING. + interrupt is used to detect if the light intensity has fallen below + or reached above the configured threshold values. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tsl2591@29 { + compatible = "amstaos,tsl2591"; + reg = <0x29>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt deleted file mode 100644 index 89647d714387..000000000000 --- a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt +++ /dev/null @@ -1,39 +0,0 @@ -I/O channel multiplexer bindings - -If a multiplexer is used to select which hardware signal is fed to -e.g. an ADC channel, these bindings describe that situation. - -Required properties: -- compatible : "io-channel-mux" -- io-channels : Channel node of the parent channel that has multiplexed - input. -- io-channel-names : Should be "parent". -- #address-cells = <1>; -- #size-cells = <0>; -- mux-controls : Mux controller node to use for operating the mux -- channels : List of strings, labeling the mux controller states. - -For each non-empty string in the channels property, an io-channel will -be created. The number of this io-channel is the same as the index into -the list of strings in the channels property, and also matches the mux -controller state. The mux controller state is described in -../mux/mux-controller.txt - -Example: - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync", "in", "system-regulator"; - }; diff --git a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml new file mode 100644 index 000000000000..870b043406d8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I/O channel multiplexer bindings + +maintainers: + - Peter Rosin + +description: | + If a multiplexer is used to select which hardware signal is fed to + e.g. an ADC channel, these bindings describe that situation. + + For each non-empty string in the channels property, an io-channel will be + created. The number of this io-channel is the same as the index into the list + of strings in the channels property, and also matches the mux controller + state. The mux controller state is described in + Documentation/devicetree/bindings/mux/mux-controller.yaml + +properties: + + compatible: + const: io-channel-mux + + io-channels: + maxItems: 1 + description: Channel node of the parent channel that has multiplexed input. + + io-channel-names: + const: parent + + mux-controls: true + mux-control-names: true + + channels: + $ref: /schemas/types.yaml#/definitions/string-array + description: + List of strings, labeling the mux controller states. + +required: + - compatible + - io-channels + - io-channel-names + - mux-controls + - channels + +additionalProperties: false + +examples: + - | + #include + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, + <&pioA 1 GPIO_ACTIVE_HIGH>; + }; + + adc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 0>; + io-channel-names = "parent"; + + mux-controls = <&mux>; + channels = "sync", "in", "system-regulator"; + }; +... diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml index 7e98f47987dc..b2a1e42c56fa 100644 --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml @@ -6,7 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics MEMS sensors -description: | +description: The STMicroelectronics sensor devices are pretty straight-forward + I2C or SPI devices, all sharing the same device tree descriptions no matter + what type of sensor it is. Note that whilst this covers many STMicro MEMs sensors, some more complex IMUs need their own bindings. The STMicroelectronics sensor devices are pretty straight-forward I2C or @@ -15,90 +17,181 @@ description: | maintainers: - Denis Ciocca + - Linus Walleij properties: compatible: - description: | - Some values are deprecated. - st,lis3lv02d (deprecated, use st,lis3lv02dl-accel) - st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel) - enum: - # Accelerometers - - st,lis3lv02d - - st,lis302dl-spi - - st,lis3lv02dl-accel - - st,lsm303dlh-accel - - st,lsm303dlhc-accel - - st,lis3dh-accel - - st,lsm330d-accel - - st,lsm330dl-accel - - st,lsm330dlc-accel - - st,lis331dl-accel - - st,lis331dlh-accel - - st,lsm303dl-accel - - st,lsm303dlm-accel - - st,lsm330-accel - - st,lsm303agr-accel - - st,lis2dh12-accel - - st,h3lis331dl-accel - - st,lng2dm-accel - - st,lis3l02dq - - st,lis2dw12 - - st,lis3dhh - - st,lis3de - - st,lis2de12 - - st,lis2hh12 - # Gyroscopes - - st,l3g4200d-gyro - - st,lsm330d-gyro - - st,lsm330dl-gyro - - st,lsm330dlc-gyro - - st,l3gd20-gyro - - st,l3gd20h-gyro - - st,l3g4is-gyro - - st,lsm330-gyro - - st,lsm9ds0-gyro - # Magnetometers - - st,lsm303agr-magn - - st,lsm303dlh-magn - - st,lsm303dlhc-magn - - st,lsm303dlm-magn - - st,lis3mdl-magn - - st,lis2mdl - - st,lsm9ds1-magn - - st,iis2mdc - # Pressure sensors - - st,lps001wp-press - - st,lps25h-press - - st,lps331ap-press - - st,lps22hb-press - - st,lps33hw - - st,lps35hw - - st,lps22hh + oneOf: + - description: STMicroelectronics Accelerometers + enum: + - st,h3lis331dl-accel + - st,lis2de12 + - st,lis2dw12 + - st,lis2hh12 + - st,lis2dh12-accel + - st,lis331dl-accel + - st,lis331dlh-accel + - st,lis3de + - st,lis3dh-accel + - st,lis3dhh + - st,lis3l02dq + - st,lis3lv02dl-accel + - st,lng2dm-accel + - st,lsm303agr-accel + - st,lsm303dl-accel + - st,lsm303dlh-accel + - st,lsm303dlhc-accel + - st,lsm303dlm-accel + - st,lsm330-accel + - st,lsm330d-accel + - st,lsm330dl-accel + - st,lsm330dlc-accel + - description: STMicroelectronics Gyroscopes + enum: + - st,l3g4200d-gyro + - st,l3g4is-gyro + - st,l3gd20-gyro + - st,l3gd20h-gyro + - st,lsm330-gyro + - st,lsm330d-gyro + - st,lsm330dl-gyro + - st,lsm330dlc-gyro + - st,lsm9ds0-gyro + - description: STMicroelectronics Magnetometers + enum: + - st,lis2mdl + - st,lis3mdl-magn + - st,lsm303agr-magn + - st,lsm303dlh-magn + - st,lsm303dlhc-magn + - st,lsm303dlm-magn + - st,lsm9ds1-magn + - description: STMicroelectronics Pressure Sensors + enum: + - st,lps001wp-press + - st,lps22hb-press + - st,lps22hh + - st,lps25h-press + - st,lps331ap-press + - st,lps33hw + - st,lps35hw + - description: IMUs + enum: + - st,lsm9ds0-imu + - description: Deprecated bindings + enum: + - st,lis302dl-spi + - st,lis3lv02d + deprecated: true reg: maxItems: 1 interrupts: + description: interrupt line(s) connected to the DRDY line(s) and/or the + Intertial interrupt lines INT1 and INT2 if these exist. This means up to + three interrupts, and the DRDY must be the first one if it exists on + the package. The trigger edge of the interrupts is sometimes software + configurable in the hardware so the operating system should parse this + flag and set up the trigger edge as indicated in the device tree. minItems: 1 + maxItems: 2 vdd-supply: true vddio-supply: true st,drdy-int-pin: + description: the pin on the package that will be used to signal + "data ready" (valid values 1 or 2). This property is not configurable + on all sensors. $ref: /schemas/types.yaml#/definitions/uint32 - description: - Some sensors have multiple possible pins via which they can provide - a data ready interrupt. This selects which one. - enum: - - 1 - - 2 + enum: [1, 2] drive-open-drain: $ref: /schemas/types.yaml#/definitions/flag - description: | - The interrupt/data ready line will be configured as open drain, which - is useful if several sensors share the same interrupt line. + description: the interrupt/data ready line will be configured + as open drain, which is useful if several sensors share the same + interrupt line. (This binding is taken from pinctrl.) + + mount-matrix: + description: an optional 3x3 mounting rotation matrix. + +allOf: + - if: + properties: + compatible: + enum: + # These have no interrupts + - st,lps001wp + then: + properties: + interrupts: false + st,drdy-int-pin: false + drive-open-drain: false + + - if: + properties: + compatible: + enum: + # These have only DRDY + - st,lis2mdl + - st,lis3l02dq + - st,lis3lv02dl-accel + - st,lps22hb-press + - st,lps22hh + - st,lps25h-press + - st,lps33hw + - st,lps35hw + - st,lsm303agr-magn + - st,lsm303dlh-magn + - st,lsm303dlhc-magn + - st,lsm303dlm-magn + then: + properties: + interrupts: + maxItems: 1 + st,drdy-int-pin: false + + - if: + properties: + compatible: + enum: + # Two intertial interrupts i.e. accelerometer/gyro interrupts + - st,h3lis331dl-accel + - st,l3g4200d-gyro + - st,l3g4is-gyro + - st,l3gd20-gyro + - st,l3gd20h-gyro + - st,lis2de12 + - st,lis2dw12 + - st,lis2hh12 + - st,lis2dh12-accel + - st,lis331dl-accel + - st,lis331dlh-accel + - st,lis3de + - st,lis3dh-accel + - st,lis3dhh + - st,lis3mdl-magn + - st,lng2dm-accel + - st,lps331ap-press + - st,lsm303agr-accel + - st,lsm303dlh-accel + - st,lsm303dlhc-accel + - st,lsm303dlm-accel + - st,lsm330-accel + - st,lsm330-gyro + - st,lsm330d-accel + - st,lsm330d-gyro + - st,lsm330dl-accel + - st,lsm330dl-gyro + - st,lsm330dlc-accel + - st,lsm330dlc-gyro + - st,lsm9ds0-gyro + - st,lsm9ds1-magn + then: + properties: + interrupts: + maxItems: 2 required: - compatible @@ -110,15 +203,30 @@ examples: - | #include i2c { - #address-cells = <1>; - #size-cells = <0>; - accelerometer@1d { - compatible = "st,lis3lv02dl-accel"; - reg = <0x1d>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; - pinctrl-0 = <&lis3lv02dl_nhk_mode>; - pinctrl-names = "default"; - }; + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@1c { + compatible = "st,lis331dl-accel"; + reg = <0x1c>; + st,drdy-int-pin = <1>; + vdd-supply = <&ldo1>; + vddio-supply = <&ldo2>; + interrupt-parent = <&gpio>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; + }; + }; + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + + l3g4200d: gyroscope@0 { + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0>; + vdd-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml new file mode 100644 index 000000000000..347bc16a4671 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: "TI TMP117 - Digital temperature sensor with integrated NV memory" + +description: | + TI TMP117 - Digital temperature sensor with integrated NV memory that supports + I2C interface. + https://www.ti.com/lit/gpn/tmp1 + +maintainers: + - Puranjay Mohan + +properties: + compatible: + enum: + - ti,tmp117 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tmp117@48 { + compatible = "ti,tmp117"; + reg = <0x48>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/fsl-mma8450.txt b/Documentation/devicetree/bindings/input/fsl-mma8450.txt deleted file mode 100644 index 0b96e5737d3a..000000000000 --- a/Documentation/devicetree/bindings/input/fsl-mma8450.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale MMA8450 3-Axis Accelerometer - -Required properties: -- compatible : "fsl,mma8450". -- reg: the I2C address of MMA8450 - -Example: - -accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; -}; diff --git a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt index 34ab5763f494..6cd08bca2c66 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt +++ b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt @@ -8,6 +8,8 @@ PROPERTIES Definition: must be one of: "qcom,pm8941-pwrkey" "qcom,pm8941-resin" + "qcom,pmk8350-pwrkey" + "qcom,pmk8350-resin" - reg: Usage: required diff --git a/Documentation/devicetree/bindings/input/touchscreen/cypress,cy8ctma340.yaml b/Documentation/devicetree/bindings/input/touchscreen/cypress,cy8ctma340.yaml new file mode 100644 index 000000000000..762e56ee90cd --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/cypress,cy8ctma340.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/cypress,cy8ctma340.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress CY8CTMA340 series touchscreen controller bindings + +description: The Cypress CY8CTMA340 series (also known as "CYTTSP" after + the marketing name Cypress TrueTouch Standard Product) touchscreens can + be connected to either I2C or SPI buses. + +maintainers: + - Javier Martinez Canillas + - Linus Walleij + +allOf: + - $ref: touchscreen.yaml# + +properties: + $nodename: + pattern: "^touchscreen(@.*)?$" + + compatible: + oneOf: + - const: cypress,cy8ctma340 + - const: cypress,cy8ctst341 + - const: cypress,cyttsp-spi + description: Legacy compatible for SPI connected CY8CTMA340 + deprecated: true + - const: cypress,cyttsp-i2c + description: Legacy compatible for I2C connected CY8CTMA340 + deprecated: true + + reg: + description: I2C address when used on the I2C bus, or the SPI chip + select index when used on the SPI bus + + clock-frequency: + description: I2C client clock frequency, defined for host when using + the device on the I2C bus + minimum: 0 + maximum: 400000 + + spi-max-frequency: + description: SPI clock frequency, defined for host, defined when using + the device on the SPI bus. The throughput is maximum 2 Mbps so the + typical value is 2000000, if higher rates are used the total throughput + needs to be restricted to 2 Mbps. + minimum: 0 + maximum: 6000000 + + interrupts: + description: Interrupt to host + maxItems: 1 + + vcpin-supply: + description: Analog power supply regulator on VCPIN pin + + vdd-supply: + description: Digital power supply regulator on VDD pin + + reset-gpios: + description: Reset line for the touchscreen, should be tagged + as GPIO_ACTIVE_LOW + + bootloader-key: + description: the 8-byte bootloader key that is required to switch + the chip from bootloader mode (default mode) to application mode + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 8 + maxItems: 8 + + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-fuzz-x: true + touchscreen-fuzz-y: true + + active-distance: + description: the distance in pixels beyond which a touch must move + before movement is detected and reported by the device + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + active-interval-ms: + description: the minimum period in ms between consecutive + scanning/processing cycles when the chip is in active mode + minimum: 0 + maximum: 255 + + lowpower-interval-ms: + description: the minimum period in ms between consecutive + scanning/processing cycles when the chip is in low-power mode + minimum: 0 + maximum: 2550 + + touch-timeout-ms: + description: minimum time in ms spent in the active power state while no + touches are detected before entering low-power mode + minimum: 0 + maximum: 2550 + + use-handshake: + description: enable register-based handshake (boolean). This should only + be used if the chip is configured to use 'blocking communication with + timeout' (in this case the device generates an interrupt at the end of + every scanning/processing cycle) + $ref: /schemas/types.yaml#/definitions/flag + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - bootloader-key + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + + touchscreen@0 { + compatible = "cypress,cy8ctma340"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>; + vdd-supply = <&ldo_aux1_reg>; + vcpin-supply = <&ldo_aux2_reg>; + bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + active-interval-ms = <0>; + touch-timeout-ms = <255>; + lowpower-interval-ms = <10>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt b/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt deleted file mode 100644 index 6ee274aa8b03..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Cypress cyttsp touchscreen controller - -Required properties: - - compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi" - - reg : Device I2C address or SPI chip select number - - spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi) - - interrupts : (gpio) interrupt to which the chip is connected - (see interrupt binding[0]). - - bootloader-key : the 8-byte bootloader key that is required to switch - the chip from bootloader mode (default mode) to - application mode. - This property has to be specified as an array of 8 - '/bits/ 8' values. - -Optional properties: - - reset-gpios : the reset gpio the chip is connected to - (see GPIO binding[1] for more details). - - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) - - touchscreen-size-y : vertical resolution of touchscreen (in pixels) - - touchscreen-fuzz-x : horizontal noise value of the absolute input device - (in pixels) - - touchscreen-fuzz-y : vertical noise value of the absolute input device - (in pixels) - - active-distance : the distance in pixels beyond which a touch must move - before movement is detected and reported by the device. - Valid values: 0-15. - - active-interval-ms : the minimum period in ms between consecutive - scanning/processing cycles when the chip is in active mode. - Valid values: 0-255. - - lowpower-interval-ms : the minimum period in ms between consecutive - scanning/processing cycles when the chip is in low-power mode. - Valid values: 0-2550 - - touch-timeout-ms : minimum time in ms spent in the active power state while no - touches are detected before entering low-power mode. - Valid values: 0-2550 - - use-handshake : enable register-based handshake (boolean). This should - only be used if the chip is configured to use 'blocking - communication with timeout' (in this case the device - generates an interrupt at the end of every - scanning/processing cycle). - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/gpio/gpio.txt - -Example: - &i2c1 { - /* ... */ - cyttsp@a { - compatible = "cypress,cyttsp-i2c"; - reg = <0xa>; - interrupt-parent = <&gpio0>; - interrupts = <28 0>; - reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - - bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>; - active-distance = <8>; - active-interval-ms = <0>; - lowpower-interval-ms = <200>; - touch-timeout-ms = <100>; - }; - - /* ... */ - }; - - &mcspi1 { - /* ... */ - cyttsp@0 { - compatible = "cypress,cyttsp-spi"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <28 0>; - reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - - bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>; - active-distance = <8>; - active-interval-ms = <0>; - lowpower-interval-ms = <200>; - touch-timeout-ms = <100>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml index bfc3a8b5e118..2e8da7470513 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml @@ -56,6 +56,7 @@ properties: wakeup-source: true vcc-supply: true + iovcc-supply: true gain: description: Allows setting the sensitivity in the range from 0 to 31. diff --git a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt deleted file mode 100644 index af5223bb5bdd..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt +++ /dev/null @@ -1,33 +0,0 @@ -Generic resistive touchscreen ADC - -Required properties: - - - compatible: must be "resistive-adc-touch" -The device must be connected to an ADC device that provides channels for -position measurement and optional pressure. -Refer to -https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml -for details - - - iio-channels: must have at least two channels connected to an ADC device. -These should correspond to the channels exposed by the ADC device and should -have the right index as the ADC device registers them. These channels -represent the relative position on the "x" and "y" axes. - - iio-channel-names: must have all the channels' names. Mandatory channels -are "x" and "y". - -Optional properties: - - iio-channels: The third channel named "pressure" is optional and can be -used if the ADC device also measures pressure besides position. -If this channel is missing, pressure will be ignored and the touchscreen -will only report position. - - iio-channel-names: optional channel named "pressure". - -Example: - - resistive_touch: resistive_touch { - compatible = "resistive-adc-touch"; - touchscreen-min-pressure = <50000>; - io-channels = <&adc 24>, <&adc 25>, <&adc 26>; - io-channel-names = "x", "y", "pressure"; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml new file mode 100644 index 000000000000..7fc22a403d48 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/resistive-adc-touch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic resistive touchscreen ADC + +maintainers: + - Oleksij Rempel + +description: | + Generic ADC based resistive touchscreen controller + The device must be connected to an ADC device that provides channels for + position measurement and optional pressure. + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + const: resistive-adc-touch + + io-channels: + minItems: 2 + items: + - description: x + - description: y + - description: pressure (optional) + - description: z1 (optional) + - description: z2 (optional) + + io-channel-names: + oneOf: + - items: + - enum: [x, y] + - enum: [x, y] + - items: + - enum: [x, y, pressure] + - enum: [x, y, pressure] + - enum: [x, y, pressure] + - items: + - enum: [x, y, z1, z2] + - enum: [x, y, z1, z2] + - enum: [x, y, z1, z2] + - enum: [x, y, z1, z2] + + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-fuzz-x: true + touchscreen-fuzz-y: true + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-swapped-x-y: true + touchscreen-min-pressure: true + touchscreen-x-plate-ohms: true + +additionalProperties: false + +required: + - compatible + - io-channels + - io-channel-names + +examples: + - | + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc 24>, <&adc 25>; + io-channel-names = "y", "x"; + }; + - | + touchscreen { + compatible = "resistive-adc-touch"; + touchscreen-min-pressure = <50000>; + io-channels = <&adc 24>, <&adc 25>, <&adc 26>; + io-channel-names = "y", "pressure", "x"; + }; + - | + touchscreen { + compatible = "resistive-adc-touch"; + touchscreen-min-pressure = <50000>; + io-channels = <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + io-channel-names = "x", "z1", "z2", "y"; + touchscreen-x-plate-ohms = <800>; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sitronix,st1232.yaml b/Documentation/devicetree/bindings/input/touchscreen/sitronix,st1232.yaml new file mode 100644 index 000000000000..1d8ca19fd37a --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/sitronix,st1232.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/sitronix,st1232.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix st1232 or st1633 touchscreen controller + +maintainers: + - Bastian Hecht + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - sitronix,st1232 + - sitronix,st1633 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpios: + description: A phandle to the reset GPIO + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupts = <2 0>; + gpios = <&gpio1 166 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt b/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt deleted file mode 100644 index 019373253b28..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Sitronix st1232 or st1633 touchscreen controller - -Required properties: -- compatible: must contain one of - * "sitronix,st1232" - * "sitronix,st1633" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected - -Optional properties: -- gpios: a phandle to the reset GPIO - -For additional optional properties see: touchscreen.txt - -Example: - - i2c@00000000 { - /* ... */ - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupts = <2 0>; - gpios = <&gpio1 166 0>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml index 046ace461cc9..4b5b212c772c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -74,6 +74,12 @@ properties: touchscreen-y-mm: description: vertical length in mm of the touchscreen + touchscreen-x-plate-ohms: + description: Resistance of the X-plate in Ohms + + touchscreen-y-plate-ohms: + description: Resistance of the Y-plate in Ohms + dependencies: touchscreen-size-x: [ touchscreen-size-y ] touchscreen-size-y: [ touchscreen-size-x ] diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 36c955965d90..5accc0d113be 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -37,6 +37,18 @@ properties: - qcom,sc7180-npu-noc - qcom,sc7180-qup-virt - qcom,sc7180-system-noc + - qcom,sc7280-aggre1-noc + - qcom,sc7280-aggre2-noc + - qcom,sc7280-clk-virt + - qcom,sc7280-cnoc2 + - qcom,sc7280-cnoc3 + - qcom,sc7280-dc-noc + - qcom,sc7280-gem-noc + - qcom,sc7280-lpass-ag-noc + - qcom,sc7280-mc-virt + - qcom,sc7280-mmss-noc + - qcom,sc7280-nsp-noc + - qcom,sc7280-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc - qcom,sdm845-config-noc diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt deleted file mode 100644 index dd527216c5fb..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt +++ /dev/null @@ -1,41 +0,0 @@ -* ARM Vectored Interrupt Controller - -One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM -system for interrupt routing. For multiple controllers they can either be -nested or have the outputs wire-OR'd together. - -Required properties: - -- compatible : should be one of - "arm,pl190-vic" - "arm,pl192-vic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as - the VIC has no configuration options for interrupt sources. The cell is a u32 - and defines the interrupt number. -- reg : The register bank for the VIC. - -Optional properties: - -- interrupts : Interrupt source for parent controllers if the VIC is nested. -- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit - represents single interrupt source, starting from source 0 at LSb and ending - at source 31 at MSb. A bit that is set means that the source is wired and - clear means otherwise. If unspecified, defaults to all valid. -- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be - configured as wake up source for the system. Order of bits is the same as for - valid-mask property. A set bit means that this interrupt source can be - configured as a wake up source for the system. If unspecied, defaults to all - interrupt sources configurable as wake up sources. - -Example: - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x60000 0x1000>; - - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x0000ff7f>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml new file mode 100644 index 000000000000..0075e72fe8c1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Vectored Interrupt Controller + +maintainers: + - Rob Herring + +description: |+ + One or more Vectored Interrupt Controllers (VIC's) can be connected in an + ARM system for interrupt routing. For multiple controllers they can either + be nested or have the outputs wire-OR'd together. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - arm,pl190-vic + - arm,pl192-vic + - arm,versatile-vic + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: + The number of cells to define the interrupts. It must be 1 as the + VIC has no configuration options for interrupt sources. The single + cell defines the interrupt number. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + valid-mask: + description: + A one cell big bit mask of valid interrupt sources. Each bit + represents single interrupt source, starting from source 0 at + LSb and ending at source 31 at MSb. A bit that is set means + that the source is wired and clear means otherwise. If unspecified, + defaults to all valid. + $ref: /schemas/types.yaml#/definitions/uint32 + + valid-wakeup-mask: + description: + A one cell big bit mask of interrupt sources that can be configured + as wake up source for the system. Order of bits is the same as for + valid-mask property. A set bit means that this interrupt source + can be configured as a wake up source for the system. If unspecied, + defaults to all interrupt sources configurable as wake up sources. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + // PL192 VIC + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x60000 0x1000>; + + valid-mask = <0xffffff7f>; + valid-wakeup-mask = <0x0000ff7f>; + }; + +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml index 3b11a1a15398..bcb5e20fa9ca 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml @@ -35,7 +35,6 @@ properties: - description: output interrupt 6 - description: output interrupt 7 minItems: 1 - maxItems: 8 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml index 067165c4b836..edf26452dc72 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml @@ -50,7 +50,6 @@ properties: - const: int2 - const: int3 minItems: 1 - maxItems: 4 '#interrupt-cells': const: 2 diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml index 9731dd4421a1..051beb45d998 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml @@ -134,7 +134,7 @@ examples: /* AM4376 PRU-ICSS */ #include pruss@0 { - compatible = "ti,am4376-pruss"; + compatible = "ti,am4376-pruss1"; reg = <0x0 0x40000>; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 5951c6f98c74..e87bfbcc6913 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -38,7 +38,6 @@ properties: If provided, then the combined interrupt will be used in preference to any others. - minItems: 2 - maxItems: 4 items: - const: eventq # Event Queue not empty - const: gerror # Global Error activated diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt index 3c36334e4f94..26ba9e530f13 100644 --- a/Documentation/devicetree/bindings/iommu/iommu.txt +++ b/Documentation/devicetree/bindings/iommu/iommu.txt @@ -92,6 +92,24 @@ Optional properties: tagging DMA transactions with an address space identifier. By default, this is 0, which means that the device only has one address space. +- dma-can-stall: When present, the master can wait for a transaction to + complete for an indefinite amount of time. Upon translation fault some + IOMMUs, instead of aborting the translation immediately, may first + notify the driver and keep the transaction in flight. This allows the OS + to inspect the fault and, for example, make physical pages resident + before updating the mappings and completing the transaction. Such IOMMU + accepts a limited number of simultaneous stalled transactions before + having to either put back-pressure on the master, or abort new faulting + transactions. + + Firmware has to opt-in stalling, because most buses and masters don't + support it. In particular it isn't compatible with PCI, where + transactions have to complete before a time limit. More generally it + won't work in systems and masters that haven't been designed for + stalling. For example the OS, in order to handle a stalled transaction, + may attempt to retrieve pages from secondary storage in a stalled + domain, leading to a deadlock. + Notes: ====== diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml index dda44976acc1..02c69a95c332 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml @@ -49,7 +49,6 @@ properties: interrupts: minItems: 1 - maxItems: 2 description: Specifiers for the MMU fault interrupts. Not required for cache IPMMUs. items: diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt deleted file mode 100644 index 6ecefea1c6f9..000000000000 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt +++ /dev/null @@ -1,38 +0,0 @@ -Rockchip IOMMU -============== - -A Rockchip DRM iommu translates io virtual addresses to physical addresses for -its master device. Each slave device is bound to a single master device, and -shares its clocks, power domain and irq. - -Required properties: -- compatible : Should be "rockchip,iommu" -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- interrupt-names : Interrupt name for the IOMMU instance -- #iommu-cells : Should be <0>. This indicates the iommu is a - "single-master" device, and needs no additional information - to associate with its master device. See: - Documentation/devicetree/bindings/iommu/iommu.txt -- clocks : A list of clocks required for the IOMMU to be accessible by - the host CPU. -- clock-names : Should contain the following: - "iface" - Main peripheral bus clock (PCLK/HCL) (required) - "aclk" - AXI bus clock (required) - -Optional properties: -- rockchip,disable-mmu-reset : Don't use the mmu reset operation. - Some mmu instances may produce unexpected results - when the reset operation is used. - -Example: - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0xff940300 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml new file mode 100644 index 000000000000..d2e28a9e3545 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip IOMMU + +maintainers: + - Heiko Stuebner + +description: |+ + A Rockchip DRM iommu translates io virtual addresses to physical addresses for + its master device. Each slave device is bound to a single master device and + shares its clocks, power domain and irq. + + For information on assigning IOMMU controller to its peripheral devices, + see generic IOMMU bindings. + +properties: + compatible: + enum: + - rockchip,iommu + - rockchip,rk3568-iommu + + reg: + items: + - description: configuration registers for MMU instance 0 + - description: configuration registers for MMU instance 1 + minItems: 1 + maxItems: 2 + + interrupts: + items: + - description: interruption for MMU instance 0 + - description: interruption for MMU instance 1 + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: aclk + - const: iface + + "#iommu-cells": + const: 0 + + power-domains: + maxItems: 1 + + rockchip,disable-mmu-reset: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Do not use the mmu reset operation. + Some mmu instances may produce unexpected results + when the reset operation is used. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + vopl_mmu: iommu@ff940300 { + compatible = "rockchip,iommu"; + reg = <0xff940300 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/richtek,rt4831-backlight.yaml b/Documentation/devicetree/bindings/leds/backlight/richtek,rt4831-backlight.yaml new file mode 100644 index 000000000000..e0ac68694b63 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/richtek,rt4831-backlight.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT4831 Backlight + +maintainers: + - ChiYuan Huang + +description: | + RT4831 is a mutifunctional device that can provide power to the LCD display + and LCD backlight. + + For the LCD backlight, it can provide four channel WLED driving capability. + Each channel driving current is up to 30mA + + Datasheet is available at + https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: richtek,rt4831-backlight + + default-brightness: + minimum: 0 + maximum: 2048 + + max-brightness: + minimum: 0 + maximum: 2048 + + richtek,pwm-enable: + description: | + Specify the backlight dimming following by PWM duty or by SW control. + type: boolean + + richtek,bled-ovp-sel: + description: | + Backlight OVP level selection, currently support 17V/21V/25V/29V. + $ref: /schemas/types.yaml#/definitions/uint8 + default: 1 + minimum: 0 + maximum: 3 + + richtek,channel-use: + description: | + Backlight LED channel to be used. + BIT 0/1/2/3 is used to indicate led channel 1/2/3/4 enable or disable. + $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 1 + maximum: 15 + +required: + - compatible + - richtek,channel-use + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index d07eb00b97c8..bd49c201477d 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -101,11 +101,19 @@ examples: clocks = <&clock 0 2 1>; clock-names = "apb_pclk"; }; + }; - mhu_client_scb: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0 0x4000>; + firmware { + scpi { + compatible = "arm,scpi"; mboxes = <&mhuA 1>; /* HP-NonSecure */ + shmem = <&cpu_scp_hpri>; /* HP-NonSecure */ + + scpi_devpd: power-controller { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; }; }; @@ -125,10 +133,36 @@ examples: clocks = <&clock 0 2 1>; clock-names = "apb_pclk"; }; + }; - mhu_client_scpi: scpi@2f000000 { - compatible = "arm,scpi"; - reg = <0 0x2f000000 0 0x200>; - mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */ + <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */ + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, + <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + + mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */ + <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */ + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_hpri0>, + <&cpu_scp_hpri1>; + }; }; }; + +... diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml index 6608545ea66f..a4f1fe63659a 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml @@ -192,18 +192,17 @@ examples: arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>; }; - mhu_client: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0 0x4000>; - - mboxes = - //data-transfer protocol with 5 windows, mhu-tx - <&mhu_tx 2 0>, - //data-transfer protocol with 7 windows, mhu-tx - <&mhu_tx 3 0>, - //doorbell protocol channel 4, doorbell 27, mhu-tx - <&mhu_tx 4 27>, - //data-transfer protocol with 1 window, mhu-rx - <&mhu_rx 0 0>; + mhu_client: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0 0x596e8000 0 0x88000>; + clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>; + clock-names = "ipg", "ocram", "core"; + power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx + <&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx + <&mhu_rx 2 27>, //doorbell protocol channel 2, doorbell 27, mhu-rx + <&mhu_rx 0 0>; //data-transfer protocol with 1 window, mhu-rx + memory-region = <&dsp_reserved>; }; }; diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt deleted file mode 100644 index 12371f5c6cd9..000000000000 --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +++ /dev/null @@ -1,184 +0,0 @@ -OMAP2+ and K3 Mailbox -===================== - -The OMAP mailbox hardware facilitates communication between different processors -using a queued mailbox interrupt mechanism. The IP block is external to the -various processor subsystems and is connected on an interconnect bus. The -communication is achieved through a set of registers for message storage and -interrupt configuration registers. - -Each mailbox IP block/cluster has a certain number of h/w fifo queues and output -interrupt lines. An output interrupt line is routed to an interrupt controller -within a processor subsystem, and there can be more than one line going to a -specific processor's interrupt controller. The interrupt line connections are -fixed for an instance and are dictated by the IP integration into the SoC -(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is -programmable through a set of interrupt configuration registers, and have a rx -and tx interrupt source per h/w fifo. Communication between different processors -is achieved through the appropriate programming of the rx and tx interrupt -sources on the appropriate interrupt lines. - -The number of h/w fifo queues and interrupt lines dictate the usable registers. -All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP -instance. DRA7xx has multiple instances with different number of h/w fifo queues -and interrupt lines between different instances. The interrupt lines can also be -routed to different processor sub-systems on DRA7xx as they are routed through -the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E -SoCs has each of these instances form a cluster and combine multiple clusters -into a single IP block present within the Main NavSS. The interrupt lines from -all these clusters are multiplexed and routed to different processor subsystems -over a limited number of common interrupt output lines of an Interrupt Router. -The AM64x SoCS also uses a single IP block comprising of multiple clusters, -but the number of clusters are smaller, and the interrupt output lines are -connected directly to various processors. - -Mailbox Device Node: -==================== -A Mailbox device node is used to represent a Mailbox IP instance/cluster within -a SoC. The sub-mailboxes are represented as child nodes of this parent node. - -Required properties: --------------------- -- compatible: Should be one of the following, - "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs - "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs - "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, - AM43xx and DRA7xx SoCs - "ti,am654-mailbox" for K3 AM65x and J721E SoCs - "ti,am64-mailbox" for K3 AM64x SoCs -- reg: Contains the mailbox register address range (base - address and length) -- interrupts: Contains the interrupt information for the mailbox - device. The format is dependent on which interrupt - controller the Mailbox device uses -- #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be - 1 -- ti,mbox-num-users: Number of targets (processor devices) that the mailbox - device can interrupt -- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block - -SoC-specific Required properties: ---------------------------------- -The following are mandatory properties for the OMAP architecture based SoCs -only: -- ti,hwmods: Name of the hwmod associated with the mailbox. This - should be defined in the mailbox node only if the node - is not defined as a child node of a corresponding sysc - interconnect node. - -The following are mandatory properties for the K3 AM65x and J721E SoCs only: -- interrupt-parent: Should contain a phandle to the TI-SCI interrupt - controller node that is used to dynamically program - the interrupt routes between the IP and the main GIC - controllers. See the following binding for additional - details, - Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml - -Child Nodes: -============ -A child node is used for representing the actual sub-mailbox device that is -used for the communication between the host processor and a remote processor. -Each child node should have a unique node name across all the different -mailbox device nodes. - -Required properties: --------------------- -- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo -- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo - -Sub-mailbox Descriptor Data ---------------------------- -Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of -data that represent the following: - Cell #1 (fifo_id) - mailbox fifo id used either for transmitting - (ti,mbox-tx) or for receiving (ti,mbox-rx) - Cell #2 (irq_id) - irq identifier index number to use from the parent's - interrupts data. Should be 0 for most of the cases, a - positive index value is seen only on mailboxes that have - multiple interrupt lines connected to the MPU processor. - Cell #3 (usr_id) - mailbox user id for identifying the interrupt line - associated with generating a tx/rx fifo interrupt. - -Optional Properties: --------------------- -- ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox - to send messages without triggering a Tx ready interrupt, - and to control the Tx ticker. Should be used only on - sub-mailboxes used to communicate with WkupM3 remote - processor on AM33xx/AM43xx SoCs. - -Mailbox Users: -============== -A device needing to communicate with a target processor device should specify -them using the common mailbox binding properties, "mboxes" and the optional -"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt -for details). Each value of the mboxes property should contain a phandle to the -mailbox controller device node and an args specifier that will be the phandle to -the intended sub-mailbox child node to be used for communication. The equivalent -"mbox-names" property value can be used to give a name to the communication channel -to be used by the client user. - - -Example: --------- - -1. /* OMAP4 */ -mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; -}; - -dsp { - ... - mboxes = <&mailbox &mbox_dsp>; - ... -}; - -2. /* AM33xx */ -mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; -}; - -3. /* AM65x */ -&cbass_main { - cbass_main_navss: interconnect0 { - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - interrupts = <164 0>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml index 3b7ab61a144f..b15da9ba90b2 100644 --- a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -32,7 +32,6 @@ properties: - description: tx channel free - description: wakeup source minItems: 2 - maxItems: 3 interrupt-names: items: @@ -40,7 +39,6 @@ properties: - const: tx - const: wakeup minItems: 2 - maxItems: 3 wakeup-source: true diff --git a/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml new file mode 100644 index 000000000000..e864d798168d --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP2+ and K3 Mailbox devices + +maintainers: + - Suman Anna + +description: | + The OMAP Mailbox hardware facilitates communication between different + processors using a queued mailbox interrupt mechanism. The IP block is + external to the various processor subsystems and is connected on an + interconnect bus. The communication is achieved through a set of registers + for message storage and interrupt configuration registers. + + Each mailbox IP block/cluster has a certain number of h/w fifo queues and + output interrupt lines. An output interrupt line is routed to an interrupt + controller within a processor subsystem, and there can be more than one line + going to a specific processor's interrupt controller. The interrupt line + connections are fixed for an instance and are dictated by the IP integration + into the SoC (excluding the SoCs that have an Interrupt Crossbar or an + Interrupt Router IP). Each interrupt line is programmable through a set of + interrupt configuration registers, and have a rx and tx interrupt source per + h/w fifo. Communication between different processors is achieved through the + appropriate programming of the rx and tx interrupt sources on the appropriate + interrupt lines. + + The number of h/w fifo queues and interrupt lines dictate the usable + registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a + single IP instance. DRA7xx has multiple instances with different number of + h/w fifo queues and interrupt lines between different instances. The interrupt + lines can also be routed to different processor sub-systems on DRA7xx as they + are routed through the Crossbar, a kind of interrupt router/multiplexer. The + K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and + combine multiple clusters into a single IP block present within the Main + NavSS. The interrupt lines from all these clusters are multiplexed and routed + to different processor subsystems over a limited number of common interrupt + output lines of an Interrupt Router. The AM64x SoCS also uses a single IP + block comprising of multiple clusters, but the number of clusters are + smaller, and the interrupt output lines are connected directly to various + processors. + + Mailbox Controller Nodes + ========================= + A Mailbox device node is used to represent a Mailbox IP instance/cluster + within a SoC. The sub-mailboxes (actual communication channels) are + represented as child nodes of this parent node. + + Mailbox Users + ============== + A device needing to communicate with a target processor device should specify + them using the common mailbox binding properties, "mboxes" and the optional + "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt + for details). Each value of the mboxes property should contain a phandle to + the mailbox controller device node and an args specifier that will be the + phandle to the intended sub-mailbox child node to be used for communication. + The equivalent "mbox-names" property value can be used to give a name to the + communication channel to be used by the client user. + +$defs: + omap-mbox-descriptor: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The omap-mbox-descriptor is made of up of 3 cells and represents a single + uni-directional communication channel. A typical sub-mailbox device uses + two such channels - one for transmitting (Tx) and one for receiving (Rx). + items: + - description: + mailbox fifo id used either for transmitting on ti,mbox-tx channel or + for receiving on ti,mbox-rx channel (fifo_id). This is the hardware + fifo number within a mailbox cluster. + - description: + irq identifier index number to use from the parent's interrupts data. + Should be 0 for most of the cases, a positive index value is seen only + on mailboxes that have multiple interrupt lines connected to the MPU + processor (irq_id). This is an index number in the listed interrupts + property in the DT nodes. + - description: + mailbox user id for identifying the interrupt line associated with + generating a tx/rx fifo interrupt (usr_id). This is the hardware + user id number within a mailbox cluster. + + omap-sub-mailbox: + type: object + description: + The omap-sub-mailbox is a child node within a Mailbox controller device + node and represents the actual communication channel used to send and + receive messages between the host processor and a remote processor. Each + child node should have a unique node name across all the different mailbox + device nodes. + + properties: + ti,mbox-tx: + $ref: "#/$defs/omap-mbox-descriptor" + description: sub-mailbox descriptor property defining a Tx fifo. + + ti,mbox-rx: + $ref: "#/$defs/omap-mbox-descriptor" + description: sub-mailbox descriptor property defining a Rx fifo. + + ti,mbox-send-noirq: + type: boolean + description: + Quirk flag to allow the client user of this sub-mailbox to send + messages without triggering a Tx ready interrupt, and to control + the Tx ticker. Should be used only on sub-mailboxes used to + communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs. + + required: + - ti,mbox-tx + - ti,mbox-rx + +properties: + compatible: + enum: + - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs + - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs + - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs + - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs + - ti,am64-mailbox # for K3 AM64x SoCs + + reg: + maxItems: 1 + + interrupts: + description: + Contains the interrupt information for the mailbox device. The format is + dependent on which interrupt controller the Mailbox device uses. The + number of interrupts listed will at most be the value specified in + ti,mbox-num-users property, but is usually limited by the number of + interrupts reaching the main processor. An interrupt-parent property + is required on SoCs where the interrupt lines are connected through a + Interrupt Router before reaching the main processor's GIC. + + "#mbox-cells": + const: 1 + description: + The specifier is a phandle to an omap-sub-mailbox device. + + ti,mbox-num-users: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of targets (processor devices) that the mailbox device can + interrupt. + + ti,mbox-num-fifos: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of h/w fifo queues within the mailbox IP block. + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + description: + Name of the hwmod associated with the mailbox. This should be defined + in the mailbox node only if the node is not defined as a child node of + a corresponding sysc interconnect node. + + This property is only needed on some legacy OMAP SoCs which have not + yet been converted to the ti,sysc interconnect hierarachy, but is + otherwise considered obsolete. + +patternProperties: + "^mbox-[a-z0-9-]+$": + $ref: "#/$defs/omap-sub-mailbox" + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + - ti,mbox-num-users + - ti,mbox-num-fifos + +allOf: + - if: + properties: + compatible: + enum: + - ti,am654-mailbox + then: + required: + - interrupt-parent + + - if: + properties: + compatible: + enum: + - ti,am654-mailbox + - ti,am64-mailbox + then: + properties: + ti,mbox-num-users: + const: 4 + ti,mbox-num-fifos: + const: 16 + interrupts: + minItems: 1 + maxItems: 4 + + - if: + properties: + compatible: + enum: + - ti,omap4-mailbox + then: + properties: + ti,mbox-num-users: + enum: [3, 4] + ti,mbox-num-fifos: + enum: [8, 12] + interrupts: + minItems: 1 + maxItems: 4 + + - if: + properties: + compatible: + enum: + - ti,omap3-mailbox + then: + properties: + ti,mbox-num-users: + const: 2 + ti,mbox-num-fifos: + const: 2 + interrupts: + minItems: 1 + maxItems: 1 + + - if: + properties: + compatible: + enum: + - ti,omap2-mailbox + then: + properties: + ti,mbox-num-users: + const: 4 + ti,mbox-num-fifos: + const: 6 + interrupts: + minItems: 1 + maxItems: 2 + +additionalProperties: false + +examples: + - | + /* OMAP4 */ + #include + mailbox: mailbox@4a0f4000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4a0f4000 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + + mbox_ipu: mbox-ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; + + dsp { + mboxes = <&mailbox &mbox_dsp>; + }; + + - | + /* AM33xx */ + mailbox1: mailbox@480c8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480c8000 0x200>; + interrupts = <77>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + + mbox_wkupm3: mbox-wkup-m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + ti,mbox-send-noirq; + }; + }; + + - | + /* AM65x */ + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x31f80000 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml index b902495d278b..5044c4bb94e0 100644 --- a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml +++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml @@ -67,7 +67,6 @@ properties: clock-names: minItems: 4 - maxItems: 5 items: - const: dos_parser - const: dos diff --git a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adv7180.yaml index bcfd93739b4f..3ce4af143a3a 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adv7180.yaml @@ -36,7 +36,13 @@ properties: maxItems: 1 port: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false ports: true diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adv7604.yaml index df634b0c1f8c..de15cebe2955 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adv7604.yaml @@ -30,7 +30,6 @@ properties: reg-names: minItems: 1 - maxItems: 13 items: - const: main - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] diff --git a/Documentation/devicetree/bindings/media/i2c/imx258.yaml b/Documentation/devicetree/bindings/media/i2c/imx258.yaml index 515317eff41a..cde0f7383b2a 100644 --- a/Documentation/devicetree/bindings/media/i2c/imx258.yaml +++ b/Documentation/devicetree/bindings/media/i2c/imx258.yaml @@ -49,7 +49,7 @@ properties: # See ../video-interfaces.txt for more details port: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base additionalProperties: false properties: diff --git a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml index ee16102fdfe7..02f656e78700 100644 --- a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml @@ -111,17 +111,10 @@ properties: i2c-mux: type: object + $ref: /schemas/i2c/i2c-mux.yaml# + unevaluatedProperties: false description: | - Each GMSL link is modelled as a child bus of an i2c bus - multiplexer/switch, in accordance with bindings described in - Documentation/devicetree/bindings/i2c/i2c-mux.txt. - - properties: - '#address-cells': - const: 1 - - '#size-cells': - const: 0 + Each GMSL link is modelled as a child bus of an i2c bus multiplexer/switch. patternProperties: "^i2c@[0-3]$": @@ -133,12 +126,6 @@ properties: channels. properties: - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - reg: description: The index of the GMSL channel. maxItems: 1 @@ -173,10 +160,6 @@ properties: additionalProperties: false - additionalProperties: false - - additionalProperties: false - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml index 9149f5685688..246dc5fec716 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml @@ -45,7 +45,7 @@ properties: port: description: MIPI CSI-2 transmitter port - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base additionalProperties: false properties: diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml index 0699c7e4fdeb..b962863e4f65 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml @@ -45,7 +45,7 @@ properties: port: description: MIPI CSI-2 transmitter port - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base additionalProperties: false properties: diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml index 27cc5b7ff613..f5055b9db693 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml @@ -37,7 +37,7 @@ properties: port: additionalProperties: false - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base properties: endpoint: diff --git a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml index c14c7d827b00..b39b84c5f012 100644 --- a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml +++ b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml @@ -43,7 +43,6 @@ properties: clocks: minItems: 1 - maxItems: 3 items: - description: AXI bus interface clock - description: Peripheral clock diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index 04013e5dd044..90b4af2c9724 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -30,7 +30,6 @@ properties: power-domain-names: minItems: 2 - maxItems: 3 items: - const: venus - const: vcodec0 diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml index 04b9af4db191..177bf81544b1 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml @@ -30,7 +30,6 @@ properties: power-domain-names: minItems: 3 - maxItems: 4 items: - const: venus - const: vcodec0 diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml index 7b81bd7f2399..ebf8f3d866a5 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml @@ -30,7 +30,6 @@ properties: power-domain-names: minItems: 2 - maxItems: 3 items: - const: venus - const: vcodec0 diff --git a/Documentation/devicetree/bindings/media/renesas,drif.yaml b/Documentation/devicetree/bindings/media/renesas,drif.yaml index 9cd56ff2c316..817a6d566738 100644 --- a/Documentation/devicetree/bindings/media/renesas,drif.yaml +++ b/Documentation/devicetree/bindings/media/renesas,drif.yaml @@ -78,7 +78,6 @@ properties: dma-names: minItems: 1 - maxItems: 2 items: - const: rx - const: rx diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml index 39bb6db2fb32..c0442e79cbb4 100644 --- a/Documentation/devicetree/bindings/media/renesas,vin.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml @@ -120,7 +120,8 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Input port node, single endpoint describing a parallel input source. diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml b/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml new file mode 100644 index 000000000000..7a63c85ef8c5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM PL353 Static Memory Controller (SMC) device-tree bindings + +maintainers: + - Miquel Raynal + - Naga Sureshkumar Relli + +description: + The PL353 Static Memory Controller is a bus where you can connect two kinds + of memory interfaces, which are NAND and memory mapped interfaces (such as + SRAM or NOR). + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,pl353-smc-r2p1 + required: + - compatible + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + items: + - const: arm,pl353-smc-r2p1 + - const: arm,primecell + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + reg: + items: + - description: + Configuration registers for the host and sub-controllers. + The three chip select regions are defined in 'ranges'. + + clocks: + items: + - description: clock for the memory device bus + - description: main clock of the SMC + + clock-names: + items: + - const: memclk + - const: apb_pclk + + ranges: + minItems: 1 + maxItems: 3 + description: | + Memory bus areas for interacting with the devices. Reflects + the memory layout with four integer values following: + 0 + items: + - description: NAND bank 0 + - description: NOR/SRAM bank 0 + - description: NOR/SRAM bank 1 + + interrupts: true + +patternProperties: + "@[0-3],[a-f0-9]+$": + type: object + description: | + The child device node represents the controller connected to the SMC + bus. The controller can be a NAND controller or a pair of any memory + mapped controllers such as NOR and SRAM controllers. + + properties: + compatible: + description: + Compatible of memory controller. + + reg: + items: + - items: + - description: | + Chip-select ID, as in the parent range property. + minimum: 0 + maximum: 2 + - description: | + Offset of the memory region requested by the device. + - description: | + Length of the memory region requested by the device. + + required: + - compatible + - reg + +required: + - compatible + - reg + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + smcc: memory-controller@e000e000 { + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + reg = <0xe000e000 0x0001000>; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ + #address-cells = <2>; + #size-cells = <1>; + + nfc0: nand-controller@0,0 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0 0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index a08a32340987..e87e4382807c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -53,14 +53,12 @@ properties: apb and smi are mandatory. the async is only for generation 1 smi HW. gals(global async local sync) also is optional, see below. minItems: 2 - maxItems: 4 items: - description: apb is Advanced Peripheral Bus clock, It's the clock for setting the register. - description: smi is the clock for transfer data and command. - - description: async is asynchronous clock, it help transform the smi - clock into the emi clock domain. - - description: gals0 is the path0 clock of gals. + - description: Either asynchronous clock to help transform the smi clock + into the emi clock domain on Gen1 h/w, or the path0 clock of gals. - description: gals1 is the path1 clock of gals. clock-names: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 7ed7839ff0a7..2353f6cf3c80 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -37,7 +37,6 @@ properties: description: | apb and smi are mandatory. gals(global async local sync) is optional. minItems: 2 - maxItems: 3 items: - description: apb is Advanced Peripheral Bus clock, It's the clock for setting the register. diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt deleted file mode 100644 index d2250498c36d..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,130 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. -- interrupts : Should contain EMC General interrupt. -- clocks : Should contain EMC clock. -- nvidia,memory-controller : Phandle of the Memory Controller node. -- #interconnect-cells : Should be 0. -- operating-points-v2: See ../bindings/opp/opp.txt for details. - -For each opp entry in 'operating-points-v2' table: -- opp-supported-hw: One bitfield indicating SoC process ID mask - - A bitwise AND is performed against this value and if any bit - matches, the OPP gets enabled. - -Optional properties: -- power-domains: Phandle of the SoC "core" power domain. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - opp_table: opp-table { - compatible = "operating-points-v2"; - - opp@36000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <36000000>; - }; - ... - }; - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - #interconnect-cells = <0>; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x400>; - interrupts = <0 78 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - nvidia,memory-controller = <&mc>; - power-domains = <&domain>; - operating-points-v2 = <&opp_table>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml new file mode 100644 index 000000000000..cac6842dc8f1 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC External Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The External Memory Controller (EMC) interfaces with the off-chip SDRAM to + service the request stream sent from Memory Controller. The EMC also has + various performance-affecting settings beyond the obvious SDRAM configuration + parameters and initialization settings. Tegra20 EMC supports multiple JEDEC + standard protocols: DDR1, LPDDR2 and DDR2. + +properties: + compatible: + const: nvidia,tegra20-emc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#interconnect-cells": + const: 0 + + nvidia,memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the Memory Controller node. + + power-domains: + maxItems: 1 + description: + Phandle of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC process ID mask. + + nvidia,use-ram-code: + type: boolean + description: + If present, the emc-tables@ sub-nodes will be addressed. + +$defs: + emc-table: + type: object + properties: + compatible: + const: nvidia,tegra20-emc-table + + clock-frequency: + description: + Memory clock rate in kHz. + minimum: 1000 + maximum: 900000 + + reg: + maxItems: 1 + description: + Either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). + + nvidia,emc-registers: + description: + EMC timing characterization data. These are the registers + (see section "15.4.1 EMC Registers" in the TRM) whose values + need to be specified, according to the board documentation. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: EMC_RC + - description: EMC_RFC + - description: EMC_RAS + - description: EMC_RP + - description: EMC_R2W + - description: EMC_W2R + - description: EMC_R2P + - description: EMC_W2P + - description: EMC_RD_RCD + - description: EMC_WR_RCD + - description: EMC_RRD + - description: EMC_REXT + - description: EMC_WDV + - description: EMC_QUSE + - description: EMC_QRST + - description: EMC_QSAFE + - description: EMC_RDV + - description: EMC_REFRESH + - description: EMC_BURST_REFRESH_NUM + - description: EMC_PDEX2WR + - description: EMC_PDEX2RD + - description: EMC_PCHG2PDEN + - description: EMC_ACT2PDEN + - description: EMC_AR2PDEN + - description: EMC_RW2PDEN + - description: EMC_TXSR + - description: EMC_TCKE + - description: EMC_TFAW + - description: EMC_TRPAB + - description: EMC_TCLKSTABLE + - description: EMC_TCLKSTOP + - description: EMC_TREFBW + - description: EMC_QUSE_EXTRA + - description: EMC_FBIO_CFG6 + - description: EMC_ODT_WRITE + - description: EMC_ODT_READ + - description: EMC_FBIO_CFG5 + - description: EMC_CFG_DIG_DLL + - description: EMC_DLL_XFORM_DQS + - description: EMC_DLL_XFORM_QUSE + - description: EMC_ZCAL_REF_CNT + - description: EMC_ZCAL_WAIT_CNT + - description: EMC_AUTO_CAL_INTERVAL + - description: EMC_CFG_CLKTRIM_0 + - description: EMC_CFG_CLKTRIM_1 + - description: EMC_CFG_CLKTRIM_2 + + required: + - clock-frequency + - compatible + - reg + - nvidia,emc-registers + + additionalProperties: false + +patternProperties: + "^emc-table@[0-9]+$": + $ref: "#/$defs/emc-table" + + "^emc-tables@[a-z0-9-]+$": + type: object + properties: + reg: + maxItems: 1 + description: + An opaque enumerator to tell different tables apart. + + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^emc-table@[0-9]+$": + $ref: "#/$defs/emc-table" + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - nvidia,memory-controller + - "#interconnect-cells" + - operating-points-v2 + +additionalProperties: false + +examples: + - | + external-memory-controller@7000f400 { + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x400>; + interrupts = <0 78 4>; + clocks = <&clock_controller 57>; + + nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; + + #interconnect-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0>; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt deleted file mode 100644 index d56615fd343a..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ /dev/null @@ -1,47 +0,0 @@ -Device tree bindings for ARM PL353 static memory controller - -PL353 static memory controller supports two kinds of memory -interfaces.i.e NAND and SRAM/NOR interfaces. -The actual devices are instantiated from the child nodes of pl353 smc node. - -Required properties: -- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". -- reg : Controller registers map and length. -- clock-names : List of input clock names - "memclk", "apb_pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). -- address-cells : Must be 2. -- size-cells : Must be 1. - -Child nodes: - For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are -supported as child nodes. - -for NAND partition information please refer the below file -Documentation/devicetree/bindings/mtd/partition.txt - -Example: - smcc: memory-controller@e000e000 - compatible = "arm,pl353-smc-r2p1", "arm,primecell"; - clock-names = "memclk", "apb_pclk"; - clocks = <&clkc 11>, <&clkc 44>; - reg = <0xe000e000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region - 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region - 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region - nand_0: flash@e1000000 { - compatible = "arm,pl353-nand-r2p1" - reg = <0 0 0x1000000>; - (...) - }; - nor0: flash@e2000000 { - compatible = "cfi-flash"; - reg = <1 0 0x2000000>; - }; - nor1: flash@e4000000 { - compatible = "cfi-flash"; - reg = <2 0 0x2000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 4dfa70a013ae..d793dd0316b7 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -117,6 +117,22 @@ properties: - "#address-cells" - "#size-cells" + cbas: + type: object + + description: + This device is used to signal when a detachable base is attached + to a Chrome OS tablet. This device cannot be detected at runtime. + + properties: + compatible: + const: google,cros-cbas + + required: + - compatible + + additionalProperties: false + patternProperties: "^i2c-tunnel[0-9]*$": type: object @@ -187,6 +203,10 @@ examples: proximity { compatible = "google,cros-ec-mkbp-proximity"; }; + + cbas { + compatible = "google,cros-cbas"; + }; }; }; diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt index b52e7a33f0f9..190230216de8 100644 --- a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt +++ b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt @@ -16,8 +16,8 @@ Optional subnodes: The sub-functions of CPCAP get their own node with their own compatible values, which are described in the following files: -- Documentation/devicetree/bindings/power/supply/cpcap-battery.txt -- Documentation/devicetree/bindings/power/supply/cpcap-charger.txt +- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml +- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml - Documentation/devicetree/bindings/regulator/cpcap-regulator.txt - Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt - Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml new file mode 100644 index 000000000000..779936850ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/qcom,pm8008.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PM8008 PMIC bindings + +maintainers: + - Guru Das Srinagesh + +description: | + Qualcomm Technologies, Inc. PM8008 is a dedicated camera PMIC that integrates + all the necessary power management, housekeeping, and interface support + functions into a single IC. + +properties: + compatible: + const: qcom,pm8008 + + reg: + description: + I2C slave address. + + maxItems: 1 + + interrupts: + maxItems: 1 + + description: Parent interrupt. + + "#interrupt-cells": + const: 2 + + description: | + The first cell is the IRQ number, the second cell is the IRQ trigger + flag. All interrupts are listed in include/dt-bindings/mfd/qcom-pm8008.h. + + interrupt-controller: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + + description: | + The GPIO peripheral. This node may be specified twice, one for each GPIO. + + properties: + compatible: + const: qcom,pm8008-gpio + + reg: + description: Peripheral address of one of the two GPIO peripherals. + maxItems: 1 + + gpio-controller: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + "#gpio-cells": + const: 2 + + required: + - compatible + - reg + - gpio-controller + - interrupt-controller + - "#gpio-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + #include + qupv3_se13_i2c { + #address-cells = <1>; + #size-cells = <0>; + pm8008i@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&tlmm>; + interrupts = <32 IRQ_TYPE_EDGE_RISING>; + + gpio@c000 { + compatible = "qcom,pm8008-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt index 79367a43b27d..5ef79bf3d035 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt @@ -34,6 +34,10 @@ Required properties: "qcom,pm8998", "qcom,pmi8998", "qcom,pm8005", + "qcom,pm8350c", + "qcom,pmk8350", + "qcom,pm7325", + "qcom,pmr735a", or generalized "qcom,spmi-pmic". - reg: Specifies the SPMI USID slave address for this device. For more information see: diff --git a/Documentation/devicetree/bindings/mfd/richtek,rt4831.yaml b/Documentation/devicetree/bindings/mfd/richtek,rt4831.yaml new file mode 100644 index 000000000000..4762eb1439ce --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/richtek,rt4831.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/richtek,rt4831.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT4831 DSV and Backlight Integrated IC + +maintainers: + - ChiYuan Huang + +description: | + RT4831 is a multifunctional device that can provide power to the LCD display + and LCD backlight. + + For Display Bias Voltage DSVP and DSVN, the output range is about 4V to 6.5V. + It's sufficient to meet the current LCD power requirement. + + For the LCD backlight, it can provide four channel WLED driving capability. + Each channel driving current is up to 30mA + + Datasheet is available at + https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf + +properties: + compatible: + const: richtek,rt4831 + + reg: + description: I2C device address. + maxItems: 1 + + enable-gpios: + description: | + GPIO to enable/disable the chip. It is optional. + Some usage directly tied this pin to follow VIO 1.8V power on sequence. + maxItems: 1 + + regulators: + $ref: ../regulator/richtek,rt4831-regulator.yaml + + backlight: + $ref: ../leds/backlight/richtek,rt4831-backlight.yaml + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rt4831@11 { + compatible = "richtek,rt4831"; + reg = <0x11>; + + regulators { + DSVLCM { + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <7150000>; + regulator-allow-bypass; + }; + DSVP { + regulator-name = "rt4831-dsvp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6500000>; + regulator-boot-on; + }; + DSVN { + regulator-name = "rt4831-dsvn"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6500000>; + regulator-boot-on; + }; + }; + + backlight { + compatible = "richtek,rt4831-backlight"; + default-brightness = <1024>; + max-brightness = <2048>; + richtek,bled-ovp-sel = /bits/ 8 ; + richtek,channel-use = /bits/ 8 ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 04df07f6f793..23a17a6663ec 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -23,6 +23,7 @@ Optional properties: default output clock name - rockchip,system-power-controller: Telling whether or not this pmic is controlling the system power. +- wakeup-source: Device can be used as a wakeup source. Optional RK805 properties: - vcc1-supply: The input supply for DCDC_REG1 @@ -63,8 +64,18 @@ Optional RK809 properties: - vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2 Optional RK817 properties: +- clocks: The input clock for the audio codec +- clock-names: The clock name for the codec clock. Should be "mclk". +- #sound-dai-cells: Needed for the interpretation of sound dais. Should be 0. + - vcc8-supply: The input supply for BOOST - vcc9-supply: The input supply for OTG_SWITCH +- codec: The child node for the codec to hold additional properties. + If no additional properties are required for the codec, this + node can be omitted. + +- rockchip,mic-in-differential: Telling if the microphone uses differential + mode. Should be under the codec child node. Optional RK818 properties: - vcc1-supply: The input supply for DCDC_REG1 @@ -275,3 +286,180 @@ Example: }; }; }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "xin32k"; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S1_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; + wakeup-source; + #clock-cells = <1>; + #sound-dai-cells = <0>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + + rk817_codec: codec { + rockchip,mic-in-differential; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index 0f16c8864a87..dace35362a7a 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -119,8 +119,6 @@ patternProperties: - compatible required: - - "#address-cells" - - "#size-cells" - compatible - reg - clocks diff --git a/Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml b/Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml new file mode 100644 index 000000000000..a0d4bad5dc81 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit + +maintainers: + - Linus Walleij + +description: + The DB8500 Power Reset and Control Management Unit is an XP70 8-bit + microprocessor that is embedded in the always-on power domain of the + DB8500 SoCs to manage the low power states, powering up and down parts + of the silicon, and controlling reset of different IP blocks. + +properties: + $nodename: + pattern: '^prcmu@[0-9a-f]+$' + + compatible: + description: The device is compatible both to the device-specific + compatible "stericsson,db8500-prcmu" and "syscon". The latter + compatible is needed for the device to be exposed as a system + controller so that arbitrary registers can be access by + different operating system components. + items: + - const: stericsson,db8500-prcmu + - const: syscon + + reg: + items: + - description: Main PRCMU register area + - description: PRCMU TCPM register area + - description: PRCMU TCDM register area + + reg-names: + items: + - const: prcmu + - const: prcmu-tcpm + - const: prcmu-tcdm + + interrupts: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + db8500-prcmu-regulators: + description: Node describing the DB8500 regulators. These are mainly + power rails inside the silicon but some of those are also routed + out to external pins. + type: object + + properties: + compatible: + const: stericsson,db8500-prcmu-regulator + + db8500_vape: + description: The voltage for the application processor, the + main voltage domain for the chip. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_varm: + description: The voltage for the ARM Cortex A-9 CPU. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vmodem: + description: The voltage for the modem subsystem. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vpll: + description: The voltage for the phase locked loop clocks. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vsmps1: + description: Also known as VIO12, is a step-down voltage regulator + for 1.2V I/O. SMPS means System Management Power Source. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vsmps2: + description: Also known as VIO18, is a step-down voltage regulator + for 1.8V I/O. SMPS means System Management Power Source. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vsmps3: + description: This is a step-down voltage regulator + for 0.87 thru 1.875V I/O. SMPS means System Management Power Source. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_vrf1: + description: RF transciever voltage regulator. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sva_mmdsp: + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) + voltage regulator. This is the voltage for the accelerator DSP + for video encoding and decoding. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sva_mmdsp_ret: + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) + voltage regulator for retention mode. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sva_pipe: + description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP) + voltage regulator for the data pipe. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sia_mmdsp: + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) + voltage regulator. This is the voltage for the accelerator DSP + for image encoding and decoding. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sia_mmdsp_ret: + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) + voltage regulator for retention mode. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sia_pipe: + description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP) + voltage regulator for the data pipe. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_sga: + description: Smart Graphics Accelerator (SGA) voltage regulator. + This is in effect controlling the power to the MALI400 3D + accelerator block. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_b2r2_mcde: + description: Blit Blend Rotate and Rescale (B2R2), and Multi-Channel + Display Engine (MCDE) voltage regulator. These are two graphics + blocks. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_esram12: + description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_esram12_ret: + description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator for + retention mode. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_esram34: + description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator. + type: object + $ref: ../regulator/regulator.yaml# + + db8500_esram34_ret: + description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator for + retention mode. + type: object + $ref: ../regulator/regulator.yaml# + + required: + - compatible + - db8500_vape + - db8500_varm + - db8500_vmodem + - db8500_vpll + - db8500_vsmps1 + - db8500_vsmps2 + - db8500_vsmps3 + - db8500_vrf1 + - db8500_sva_mmdsp + - db8500_sva_mmdsp_ret + - db8500_sva_pipe + - db8500_sia_mmdsp + - db8500_sia_mmdsp_ret + - db8500_sia_pipe + - db8500_sga + - db8500_b2r2_mcde + - db8500_esram12 + - db8500_esram12_ret + - db8500_esram34 + - db8500_esram34_ret + + additionalProperties: false + +patternProperties: + "^thermal@[0-9a-f]+$": + description: Node describing the DB8500 thermal control functions. + This binds to an operating system driver that monitors the + temperature of the SoC. + type: object + + properties: + compatible: + const: stericsson,db8500-thermal + + reg: + maxItems: 1 + + interrupts: + items: + - description: Hotmon low interrupt (falling temperature) + - description: Hotmon high interrupt (rising temperature) + + interrupt-names: + items: + - const: IRQ_HOTMON_LOW + - const: IRQ_HOTMON_HIGH + + '#thermal-sensor-cells': + const: 0 + + additionalProperties: false + + "^prcmu-timer-4@[0-9a-f]+$": + description: Node describing the externally visible timer 4 in the + PRCMU block. This timer is interesting to the operating system + since even thought it has a very low resolution (32768 Hz) it is + always on, and thus provides a consistent monotonic timeline for + the system. + type: object + + properties: + compatible: + const: stericsson,db8500-prcmu-timer-4 + + reg: + maxItems: 1 + + additionalProperties: false + + "^ab850[05]$": + description: Node describing the Analog Baseband 8500 mixed-signals + ASIC AB8500 and subcomponents. The AB8500 is accessed through the + PRCMU and hence it appears here. This component has a separate + set of devicetree bindings. The AB8505 is a newer version of the + same ASIC. + type: object + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - ranges + - interrupts + - interrupt-controller + - '#interrupt-cells' + - db8500-prcmu-regulators + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml index 19fcf59fd2fe..272832e9f8f2 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -43,12 +43,10 @@ properties: patternProperties: # Optional children - "^serdes-ln-ctrl@[0-9a-f]+$": + "^mux-controller@[0-9a-f]+$": type: object - description: | - This is the SERDES lane control mux. It should follow the bindings - specified in - Documentation/devicetree/bindings/mux/reg-mux.txt + description: + This is the SERDES lane control mux. required: - compatible @@ -68,9 +66,18 @@ examples: #size-cells = <1>; ranges; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; + + #mux-control-cells = <1>; + mux-reg-masks = + <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; + /* SERDES4 lane0/1/2/3 select */ }; }; ... diff --git a/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt b/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt index 7b636b7a8311..72ea0af368d4 100644 --- a/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt +++ b/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt @@ -2,7 +2,10 @@ EEPROMs (SPI) compatible with Microchip Technology 93xx46 family. Required properties: - compatible : shall be one of: + "atmel,at93c46" "atmel,at93c46d" + "atmel,at93c56" + "atmel,at93c66" "eeprom-93xx46" "microchip,93lc46b" - data-size : number of data bits per word (either 8 or 16) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index e75b3a8ba816..4f62ad6ce50c 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -64,7 +64,6 @@ properties: clocks: minItems: 2 - maxItems: 4 items: - description: Bus Clock - description: Module Clock @@ -73,7 +72,6 @@ properties: clock-names: minItems: 2 - maxItems: 4 items: - const: ahb - const: mmc diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 369471814496..b5baf439fbac 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -116,7 +116,6 @@ properties: pinctrl-names: minItems: 1 - maxItems: 4 items: - const: default - const: state_100mhz diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 8648d48dbbfd..e866e985549e 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -31,6 +31,8 @@ properties: - const: mediatek,mt2701-mmc - items: - const: mediatek,mt8192-mmc + - const: mediatek,mt8183-mmc + - items: - const: mediatek,mt8195-mmc - const: mediatek,mt8183-mmc @@ -38,7 +40,6 @@ properties: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). @@ -51,7 +52,6 @@ properties: clock-names: minItems: 2 - maxItems: 8 items: - const: source - const: hclk diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 1118b6fa93c9..677989bc5924 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -75,7 +75,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: core - const: cd @@ -107,7 +106,6 @@ properties: pinctrl-names: minItems: 1 - maxItems: 2 items: - const: default - const: state_uhs diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml index 29399e88ac53..224303f5b913 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml @@ -44,7 +44,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: clk_ahb - const: clk_xin diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index aa12480648a5..1c87f4218e18 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -57,7 +57,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: io - const: core diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index 4a9145ef15d6..57d077c0b7c1 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -25,10 +25,10 @@ The following are mandatory properties for 66AK2G SoCs only: - power-domains:Should contain a phandle to a PM domain provider node and an args specifier containing the MMC device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - clocks: Must contain an entry for each entry in clock-names. Should be defined as per the he appropriate clock bindings consumer - usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt + usage in Documentation/devicetree/bindings/clock/ti,sci-clk.yaml - clock-names: Shall be "fck" for the functional clock, and "mmchsdb_fck" for the debounce clock. diff --git a/Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml b/Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml new file mode 100644 index 000000000000..5f126bb9b202 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PL353 NAND Controller device tree bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Miquel Raynal + - Naga Sureshkumar Relli + +properties: + compatible: + items: + - const: arm,pl353-nand-r2p1 + + reg: + items: + - items: + - description: CS with regard to the parent ranges property + - description: Offset of the memory region requested by the device + - description: Length of the memory region requested by the device + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + smcc: memory-controller@e000e000 { + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + reg = <0xe000e000 0x0001000>; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ + #address-cells = <2>; + #size-cells = <1>; + + nfc0: nand-controller@0,0 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0 0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt deleted file mode 100644 index 4ec28796a3c0..000000000000 --- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt +++ /dev/null @@ -1,26 +0,0 @@ -Flash device on ARM Versatile board - -These flash chips are found in the ARM reference designs like Integrator, -Versatile, RealView, Versatile Express etc. - -They are regular CFI compatible (Intel or AMD extended) flash chips with -some special write protect/VPP bits that can be controlled by the machine's -system controller. - -Required properties: -- compatible : must be "arm,versatile-flash", "cfi-flash"; -- reg : memory address for the flash chip -- bank-width : width in bytes of flash interface. - -For the rest of the properties, see mtd-physmap.txt. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@34000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x34000000 0x4000000>; - bank-width = <4>; -}; diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt deleted file mode 100644 index 44335a4f8bfb..000000000000 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ /dev/null @@ -1,186 +0,0 @@ -* Broadcom STB NAND Controller - -The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND -flash chips. It has a memory-mapped register interface for both control -registers and for its data input/output buffer. On some SoCs, this controller is -paired with a custom DMA engine (inventively named "Flash DMA") which supports -basic PROGRAM and READ functions, among other features. - -This controller was originally designed for STB SoCs (BCM7xxx) but is now -available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and -iProc/Cygnus. Its history includes several similar (but not fully register -compatible) versions. - -Required properties: -- compatible : May contain an SoC-specific compatibility string (see below) - to account for any SoC-specific hardware bits that may be - added on top of the base core controller. - In addition, must contain compatibility information about - the core NAND controller, of the following form: - "brcm,brcmnand" and an appropriate version compatibility - string, like "brcm,brcmnand-v7.0" - Possible values: - brcm,brcmnand-v2.1 - brcm,brcmnand-v2.2 - brcm,brcmnand-v4.0 - brcm,brcmnand-v5.0 - brcm,brcmnand-v6.0 - brcm,brcmnand-v6.1 - brcm,brcmnand-v6.2 - brcm,brcmnand-v7.0 - brcm,brcmnand-v7.1 - brcm,brcmnand-v7.2 - brcm,brcmnand-v7.3 - brcm,brcmnand -- reg : the register start and length for NAND register region. - (optional) Flash DMA register range (if present) - (optional) NAND flash cache range (if at non-standard offset) -- reg-names : a list of the names corresponding to the previous register - ranges. Should contain "nand" and (optionally) - "flash-dma" or "flash-edu" and/or "nand-cache". -- interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available) - FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE -- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done", - if broken out as individual interrupts. - May be "nand", if the SoC has the individual NAND - interrupts multiplexed behind another custom piece of - hardware -- #address-cells : <1> - subnodes give the chip-select number -- #size-cells : <0> - -Optional properties: -- clock : reference to the clock for the NAND controller -- clock-names : "nand" (required for the above clock) -- brcm,nand-has-wp : Some versions of this IP include a write-protect - (WP) control bit. It is always available on >= - v7.0. Use this property to describe the rare - earlier versions of this core that include WP - - -- Additional SoC-specific NAND controller properties -- - -The NAND controller is integrated differently on the variety of SoCs on which it -is found. Part of this integration involves providing status and enable bits -with which to control the 8 exposed NAND interrupts, as well as hardware for -configuring the endianness of the data bus. On some SoCs, these features are -handled via standard, modular components (e.g., their interrupts look like a -normal IRQ chip), but on others, they are controlled in unique and interesting -ways, sometimes with registers that lump multiple NAND-related functions -together. The former case can be described simply by the standard interrupts -properties in the main controller node. But for the latter exceptional cases, -we define additional 'compatible' properties and associated register resources within the NAND controller node above. - - - compatible: Can be one of several SoC-specific strings. Each SoC may have - different requirements for its additional properties, as described below each - bullet point below. - - * "brcm,nand-bcm63138" - - reg: (required) the 'NAND_INT_BASE' register range, with separate status - and enable registers - - reg-names: (required) "nand-int-base" - - * "brcm,nand-bcm6368" - - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm6368" - - reg: (required) the 'NAND_INTR_BASE' register range, with combined status - and enable registers, and boot address registers - - reg-names: (required) "nand-int-base" - - * "brcm,nand-iproc" - - reg: (required) the "IDM" register range, for interrupt enable and APB - bus access endianness configuration, and the "EXT" register range, - for interrupt status/ack. - - reg-names: (required) a list of the names corresponding to the previous - register ranges. Should contain "iproc-idm" and "iproc-ext". - - -* NAND chip-select - -Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes -to represent enabled chip-selects which (may) contain NAND flash chips. Their -properties are as follows. - -Required properties: -- compatible : should contain "brcm,nandcs" -- reg : a single integer representing the chip-select - number (e.g., 0, 1, 2, etc.) -- #address-cells : see partition.txt -- #size-cells : see partition.txt - -Optional properties: -- nand-ecc-strength : see nand-controller.yaml -- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml -- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this - chip-select. See nand-controller.yaml -- brcm,nand-oob-sector-size : integer, to denote the spare area sector size - expected for the ECC layout in use. This size, in - addition to the strength and step-size, - determines how the hardware BCH engine will lay - out the parity bytes it stores on the flash. - This property can be automatically determined by - the flash geometry (particularly the NAND page - and OOB size) in many cases, but when booting - from NAND, the boot controller has only a limited - number of available options for its default ECC - layout. - -Each nandcs device node may optionally contain sub-nodes describing the flash -partition mapping. See partition.txt for more detail. - - -Example: - -nand@f0442800 { - compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; - reg = <0xF0442800 0x600>, - <0xF0443000 0x100>; - reg-names = "nand", "flash-dma"; - interrupt-parent = <&hif_intr2_intc>; - interrupts = <24>, <4>; - - #address-cells = <1>; - #size-cells = <0>; - - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <1>; // Chip select 1 - nand-on-flash-bbt; - nand-ecc-strength = <12>; - nand-ecc-step-size = <512>; - - // Partitions - #address-cells = <1>; // <2>, for 64-bit offset - #size-cells = <1>; // <2>, for 64-bit length - flash0.rootfs@0 { - reg = <0 0x10000000>; - }; - flash0@0 { - reg = <0 0>; // MTDPART_SIZ_FULL - }; - flash0.kernel@10000000 { - reg = <0x10000000 0x400000>; - }; - }; -}; - -nand@10000200 { - compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", - "brcm,brcmnand-v4.0", "brcm,brcmnand"; - reg = <0x10000200 0x180>, - <0x10000600 0x200>, - <0x100000b0 0x10>; - reg-names = "nand", "nand-cache", "nand-int-base"; - interrupt-parent = <&periph_intc>; - interrupts = <50>; - clocks = <&periph_clk 20>; - clock-names = "nand"; - - #address-cells = <1>; - #size-cells = <0>; - - nand0: nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <1>; - nand-ecc-step-size = <512>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml new file mode 100644 index 000000000000..e5f1a33332a5 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB NAND Controller + +maintainers: + - Brian Norris + - Kamal Dasu + +description: | + The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND + flash chips. It has a memory-mapped register interface for both control + registers and for its data input/output buffer. On some SoCs, this controller + is paired with a custom DMA engine (inventively named "Flash DMA") which + supports basic PROGRAM and READ functions, among other features. + + This controller was originally designed for STB SoCs (BCM7xxx) but is now + available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and + iProc/Cygnus. Its history includes several similar (but not fully register + compatible) versions. + + -- Additional SoC-specific NAND controller properties -- + + The NAND controller is integrated differently on the variety of SoCs on which + it is found. Part of this integration involves providing status and enable + bits with which to control the 8 exposed NAND interrupts, as well as hardware + for configuring the endianness of the data bus. On some SoCs, these features + are handled via standard, modular components (e.g., their interrupts look like + a normal IRQ chip), but on others, they are controlled in unique and + interesting ways, sometimes with registers that lump multiple NAND-related + functions together. The former case can be described simply by the standard + interrupts properties in the main controller node. But for the latter + exceptional cases, we define additional 'compatible' properties and associated + register resources within the NAND controller node above. + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,brcmnand-v2.1 + - brcm,brcmnand-v2.2 + - brcm,brcmnand-v4.0 + - brcm,brcmnand-v5.0 + - brcm,brcmnand-v6.0 + - brcm,brcmnand-v6.1 + - brcm,brcmnand-v6.2 + - brcm,brcmnand-v7.0 + - brcm,brcmnand-v7.1 + - brcm,brcmnand-v7.2 + - brcm,brcmnand-v7.3 + - const: brcm,brcmnand + - description: BCM63138 SoC-specific NAND controller + items: + - const: brcm,nand-bcm63138 + - enum: + - brcm,brcmnand-v7.0 + - brcm,brcmnand-v7.1 + - const: brcm,brcmnand + - description: iProc SoC-specific NAND controller + items: + - const: brcm,nand-iproc + - const: brcm,brcmnand-v6.1 + - const: brcm,brcmnand + - description: BCM63168 SoC-specific NAND controller + items: + - const: brcm,nand-bcm63168 + - const: brcm,nand-bcm6368 + - const: brcm,brcmnand-v4.0 + - const: brcm,brcmnand + + reg: + minItems: 1 + maxItems: 6 + + reg-names: + minItems: 1 + maxItems: 6 + items: + enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ] + + interrupts: + minItems: 1 + maxItems: 3 + items: + - description: NAND CTLRDY interrupt + - description: FLASH_DMA_DONE if flash DMA is available + - description: FLASH_EDU_DONE if EDU is available + + interrupt-names: + minItems: 1 + maxItems: 3 + items: + - const: nand_ctlrdy + - const: flash_dma_done + - const: flash_edu_done + + clocks: + maxItems: 1 + description: reference to the clock for the NAND controller + + clock-names: + const: nand + + brcm,nand-has-wp: + description: > + Some versions of this IP include a write-protect + (WP) control bit. It is always available on >= + v7.0. Use this property to describe the rare + earlier versions of this core that include WP + type: boolean + +patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + compatible: + const: brcm,nandcs + + nand-ecc-step-size: + enum: [ 512, 1024 ] + + brcm,nand-oob-sector-size: + description: | + integer, to denote the spare area sector size + expected for the ECC layout in use. This size, in + addition to the strength and step-size, + determines how the hardware BCH engine will lay + out the parity bytes it stores on the flash. + This property can be automatically determined by + the flash geometry (particularly the NAND page + and OOB size) in many cases, but when booting + from NAND, the boot controller has only a limited + number of available options for its default ECC + layout. + $ref: /schemas/types.yaml#/definitions/uint32 + +allOf: + - $ref: nand-controller.yaml# + - if: + properties: + compatible: + contains: + const: brcm,nand-bcm63138 + then: + properties: + reg-names: + minItems: 2 + maxItems: 2 + items: + - const: nand + - const: nand-int-base + - if: + properties: + compatible: + contains: + const: brcm,nand-bcm6368 + then: + properties: + reg-names: + minItems: 3 + maxItems: 3 + items: + - const: nand + - const: nand-int-base + - const: nand-cache + - if: + properties: + compatible: + contains: + const: brcm,nand-iproc + then: + properties: + reg-names: + minItems: 3 + maxItems: 3 + items: + - const: nand + - const: iproc-idm + - const: iproc-ext + +unevaluatedProperties: false + +required: + - reg + - reg-names + - interrupts + +examples: + - | + nand-controller@f0442800 { + compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; + reg = <0xf0442800 0x600>, + <0xf0443000 0x100>; + reg-names = "nand", "flash-dma"; + interrupt-parent = <&hif_intr2_intc>; + interrupts = <24>, <4>; + + #address-cells = <1>; + #size-cells = <0>; + + nand@1 { + compatible = "brcm,nandcs"; + reg = <1>; // Chip select 1 + nand-on-flash-bbt; + nand-ecc-strength = <12>; + nand-ecc-step-size = <512>; + + #address-cells = <1>; + #size-cells = <1>; + }; + }; + - | + nand-controller@10000200 { + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", + "brcm,brcmnand-v4.0", "brcm,brcmnand"; + reg = <0x10000200 0x180>, + <0x100000b0 0x10>, + <0x10000600 0x200>; + reg-names = "nand", "nand-int-base", "nand-cache"; + interrupt-parent = <&periph_intc>; + interrupts = <50>; + clocks = <&periph_clk 20>; + clock-names = "nand"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; + + #address-cells = <1>; + #size-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/common.txt b/Documentation/devicetree/bindings/mtd/common.txt index fc068b923d7a..ae16f9ea8606 100644 --- a/Documentation/devicetree/bindings/mtd/common.txt +++ b/Documentation/devicetree/bindings/mtd/common.txt @@ -1,15 +1 @@ -* Common properties of all MTD devices - -Optional properties: -- label: user-defined MTD device name. Can be used to assign user - friendly names to MTD devices (instead of the flash model or flash - controller based name) in order to ease flash device identification - and/or describe what they are used for. - -Example: - - flash@0 { - label = "System-firmware"; - - /* flash type specific properties */ - }; +This file has been moved to mtd.yaml. diff --git a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt index 3fa1b34d69ad..efa5b2aba829 100644 --- a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt +++ b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt @@ -9,7 +9,7 @@ Required properties: - syscon : must be a phandle to the system controller - bank-width : width in bytes of flash interface, should be <2> -For the rest of the properties, see mtd-physmap.txt. +For the rest of the properties, see mtd-physmap.yaml. The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt b/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt deleted file mode 100644 index ad42f4db32f1..000000000000 --- a/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt +++ /dev/null @@ -1,13 +0,0 @@ -Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus -specification and supports Cypress CFI specification 1.5 command set. - -Required properties: -- compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips -- reg : Address of flash's memory map - -Example: - - flash@0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x0 0x4000000>; - }; diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt deleted file mode 100644 index 4bdcb92ae381..000000000000 --- a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt +++ /dev/null @@ -1,22 +0,0 @@ -Flash device on Intel IXP4xx SoC - -This flash is regular CFI compatible (Intel or AMD extended) flash chips with -specific big-endian or mixed-endian memory access pattern. - -Required properties: -- compatible : must be "intel,ixp4xx-flash", "cfi-flash"; -- reg : memory address for the flash chip -- bank-width : width in bytes of flash interface, should be <2> - -For the rest of the properties, see mtd-physmap.txt. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - reg = <0x50000000 0x01000000>; - bank-width = <2>; -}; diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 5e7e5349f9a1..ed590d7c6e37 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -9,6 +9,9 @@ title: SPI NOR flash ST M25Pxx (and similar) serial flash chips maintainers: - Rob Herring +allOf: + - $ref: "mtd.yaml#" + properties: compatible: oneOf: @@ -82,6 +85,9 @@ patternProperties: '^partition@': type: object + "^otp(-[0-9]+)?$": + type: object + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml b/Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml new file mode 100644 index 000000000000..2cdf6bf3dc4a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip 48l640 (and similar) serial EERAM bindings + +maintainers: + - Heiko Schocher + +description: | + The Microchip 48l640 is a 8KByte EERAM connected via SPI. + + datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/20006055B.pdf + +properties: + compatible: + items: + - const: microchip,48l640 + + reg: + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + eeram@0 { + compatible = "microchip,48l640"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt deleted file mode 100644 index c69f4f065d23..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ /dev/null @@ -1,114 +0,0 @@ -CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) - -Flash chips (Memory Technology Devices) are often used for solid state -file systems on embedded devices. - - - compatible : should contain the specific model of mtd chip(s) - used, if known, followed by either "cfi-flash", "jedec-flash", - "mtd-ram" or "mtd-rom". - - reg : Address range(s) of the mtd chip(s) - It's possible to (optionally) define multiple "reg" tuples so that - non-identical chips can be described in one node. - - bank-width : Width (in bytes) of the bank. Equal to the - device width times the number of interleaved chips. - - device-width : (optional) Width of a single mtd chip. If - omitted, assumed to be equal to 'bank-width'. - - #address-cells, #size-cells : Must be present if the device has - sub-nodes representing partitions (see below). In this case - both #address-cells and #size-cells must be equal to 1. - - no-unaligned-direct-access: boolean to disable the default direct - mapping of the flash. - On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause - problems with JFFS2 usage, as the local bus (LPB) doesn't support - unaligned accesses as implemented in the JFFS2 code via memcpy(). - By defining "no-unaligned-direct-access", the flash will not be - exposed directly to the MTD users (e.g. JFFS2) any more. - - linux,mtd-name: allow to specify the mtd name for retro capability with - physmap-flash drivers as boot loader pass the mtd partition via the old - device name physmap-flash. - - use-advanced-sector-protection: boolean to enable support for the - advanced sector protection (Spansion: PPB - Persistent Protection - Bits) locking. - - addr-gpios : (optional) List of GPIO descriptors that will be used to - address the MSBs address lines. The order goes from LSB to MSB. - -For JEDEC compatible devices, the following additional properties -are defined: - - - vendor-id : Contains the flash chip's vendor id (1 byte). - - device-id : Contains the flash chip's device id (1 byte). - -For ROM compatible devices (and ROM fallback from cfi-flash), the following -additional (optional) property is defined: - - - erase-size : The chip's physical erase block size in bytes. - - The device tree may optionally contain endianness property. - little-endian or big-endian : It Represents the endianness that should be used - by the controller to properly read/write data - from/to the flash. If this property is missing, - the endianness is chosen by the system - (potentially based on extra configuration options). - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - - flash@ff000000 { - compatible = "amd,am29lv128ml", "cfi-flash"; - reg = ; - bank-width = <4>; - device-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - fs@0 { - label = "fs"; - reg = <0 f80000>; - }; - firmware@f80000 { - label ="firmware"; - reg = ; - read-only; - }; - }; - -Here an example with multiple "reg" tuples: - - flash@f0000000,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "intel,PC48F4400P0VB", "cfi-flash"; - reg = <0 0x00000000 0x02000000 - 0 0x02000000 0x02000000>; - bank-width = <2>; - partition@0 { - label = "test-part1"; - reg = <0 0x04000000>; - }; - }; - -An example using SRAM: - - sram@2,0 { - compatible = "samsung,k6f1616u6a", "mtd-ram"; - reg = <2 0 0x00200000>; - bank-width = <2>; - }; - -An example using gpio-addrs - - flash@20000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash", "jedec-flash"; - reg = <0x20000000 0x02000000>; - ranges = <0 0x00000000 0x02000000 - 1 0x02000000 0x02000000>; - bank-width = <2>; - addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - partition@0 { - label = "test-part1"; - reg = <0 0x04000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml new file mode 100644 index 000000000000..13c29cc91b59 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) + +maintainers: + - Rob Herring + +description: | + Flash chips (Memory Technology Devices) are often used for solid state + file systems on embedded devices. + +properties: + compatible: + oneOf: + - items: + - enum: + - amd,s29gl01gp + - amd,s29gl032a + - amd,s29gl256n + - amd,s29gl512n + - arm,versatile-flash + - cortina,gemini-flash + - cypress,hyperflash + - ge,imp3a-firmware-mirror + - ge,imp3a-paged-flash + - gef,ppc9a-firmware-mirror + - gef,ppc9a-paged-flash + - gef,sbc310-firmware-mirror + - gef,sbc310-paged-flash + - gef,sbc610-firmware-mirror + - gef,sbc610-paged-flash + - intel,28f128j3 + - intel,dt28f160 + - intel,ixp4xx-flash + - intel,JS28F128 + - intel,JS28F640 + - intel,PC28F640P30T85 + - numonyx,js28f00a + - numonyx,js28f128 + - sst,sst39vf320 + - xlnx,xps-mch-emc-2.00.a + - const: cfi-flash + - items: + - enum: + - cypress,cy7c1019dv33-10zsxi + - arm,vexpress-psram + - const: mtd-ram + - enum: + - cfi-flash + - jedec-flash + - mtd-ram + - mtd-rom + + reg: + description: | + It's possible to (optionally) define multiple "reg" tuples so that + non-identical chips can be described in one node. + minItems: 1 + maxItems: 8 + + bank-width: + description: Width (in bytes) of the bank. Equal to the device width times + the number of interleaved chips. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + device-width: + description: + Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2 ] + + no-unaligned-direct-access: + type: boolean + description: | + Disables the default direct mapping of the flash. + + On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems + with JFFS2 usage, as the local bus (LPB) doesn't support unaligned + accesses as implemented in the JFFS2 code via memcpy(). By defining + "no-unaligned-direct-access", the flash will not be exposed directly to + the MTD users (e.g. JFFS2) any more. + + linux,mtd-name: + description: + Allows specifying the mtd name for retro capability with physmap-flash + drivers as boot loader pass the mtd partition via the old device name + physmap-flash. + $ref: /schemas/types.yaml#/definitions/string + + use-advanced-sector-protection: + type: boolean + description: | + Enables support for the advanced sector protection (Spansion: PPB - + Persistent Protection Bits) locking. + + erase-size: + description: The chip's physical erase block size in bytes. + $ref: /schemas/types.yaml#/definitions/uint32 + + addr-gpios: + description: + List of GPIO descriptors that will be used to address the MSBs address + lines. The order goes from LSB to MSB. + minItems: 1 + maxItems: 8 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + big-endian: true + little-endian: true + +patternProperties: + '@[0-9a-f]+$': + $ref: partitions/partition.yaml + +required: + - compatible + - reg + +# FIXME: A parent bus may define timing properties +additionalProperties: true + +examples: + - | + + flash@ff000000 { + compatible = "cfi-flash"; + reg = <0xff000000 0x01000000>; + bank-width = <4>; + device-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff000000 0x01000000>; + + fs@0 { + label = "fs"; + reg = <0 0xf80000>; + }; + firmware@f80000 { + label ="firmware"; + reg = <0xf80000 0x80000>; + read-only; + }; + }; + + - | + /* An example with multiple "reg" tuples */ + + flash@0 { + compatible = "intel,PC28F640P30T85", "cfi-flash"; + reg = <0x00000000 0x02000000>, + <0x02000000 0x02000000>; + bank-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x04000000>; + + partition@0 { + label = "test-part1"; + reg = <0 0x04000000>; + }; + }; + + - | + /* An example using SRAM */ + bus { + #address-cells = <2>; + #size-cells = <1>; + + sram@2,0 { + compatible = "mtd-ram"; + reg = <2 0 0x00200000>; + bank-width = <2>; + }; + }; + + - | + /* An example using addr-gpios */ + #include + + flash@20000000 { + compatible = "cfi-flash"; + reg = <0x20000000 0x02000000>; + bank-width = <2>; + addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0x02000000>, + <1 0x02000000 0x02000000>; + + partition@0 { + label = "test-part1"; + reg = <0 0x04000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/mtd.yaml b/Documentation/devicetree/bindings/mtd/mtd.yaml new file mode 100644 index 000000000000..376b679cfc70 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtd.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mtd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MTD (Memory Technology Device) Device Tree Bindings + +maintainers: + - Miquel Raynal + - Richard Weinberger + +properties: + $nodename: + pattern: "^flash(@.*)?$" + + label: + description: + User-defined MTD device name. Can be used to assign user friendly + names to MTD devices (instead of the flash model or flash controller + based name) in order to ease flash device identification and/or + describe what they are used for. + +patternProperties: + "^otp(-[0-9]+)?$": + type: object + $ref: ../nvmem/nvmem.yaml# + + description: | + An OTP memory region. Some flashes provide a one-time-programmable + memory whose content can either be programmed by a user or is already + pre-programmed by the factory. Some flashes might provide both. + + properties: + compatible: + enum: + - user-otp + - factory-otp + + required: + - compatible + +additionalProperties: true + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + label = "System-firmware"; + }; + }; + + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + + otp-1 { + compatible = "factory-otp"; + #address-cells = <1>; + #size-cells = <1>; + + electronic-serial-number@0 { + reg = <0 8>; + }; + }; + + otp-2 { + compatible = "user-otp"; + #address-cells = <1>; + #size-cells = <1>; + + mac-address@0 { + reg = <0 6>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index 678b39952502..bd217e6f5018 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -38,6 +38,17 @@ properties: ranges: true + cs-gpios: + minItems: 1 + maxItems: 8 + description: + Array of chip-select available to the controller. The first + entries are a 1:1 mapping of the available chip-select on the + NAND controller (even if they are not used). As many additional + chip-select as needed may follow and should be phandles of GPIO + lines. 'reg' entries of the NAND chip subnodes become indexes of + this array when this property is present. + patternProperties: "^nand@[a-f0-9]$": type: object @@ -164,14 +175,19 @@ examples: nand-controller { #address-cells = <1>; #size-cells = <0>; + cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */ /* controller specific properties */ nand@0 { - reg = <0>; + reg = <0>; /* Native CS */ nand-use-soft-ecc-engine; nand-ecc-algo = "bch"; /* controller specific properties */ }; + + nand@1 { + reg = <1>; /* GPIO CS */ + }; }; diff --git a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt b/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt index b677147ca4e1..c2175d3c82ec 100644 --- a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt +++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt @@ -28,6 +28,11 @@ detected by a software parsing TRX header. Required properties: - compatible : (required) must be "brcm,trx" +Optional properties: + +- brcm,trx-magic: TRX magic, if it is different from the default magic + 0x30524448 as a u32. + Example: flash@0 { diff --git a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt deleted file mode 100644 index faa81c2e5da6..000000000000 --- a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt +++ /dev/null @@ -1,51 +0,0 @@ -Bindings for HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs - -Required properties: -- compatible : "ti,am654-hbmc" for AM654 SoC -- reg : Two entries: - First entry pointed to the register space of HBMC controller - Second entry pointing to the memory map region dedicated for - MMIO access to attached flash devices -- ranges : Address translation from offset within CS to allocated MMIO - space in SoC - -Optional properties: -- mux-controls : phandle to the multiplexer that controls selection of - HBMC vs OSPI inside Flash SubSystem (FSS). Default is OSPI, - if property is absent. - See Documentation/devicetree/bindings/mux/reg-mux.txt - for mmio-mux binding details - -Example: - - system-controller@47000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: multiplexer { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */ - }; - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x0 0x47034000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - power-domains = <&k3_pds 55>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */ - <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */ - mux-controls = <&hbmc_mux 0>; - - /* Slave flash node */ - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x0 0x0 0x4000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.yaml b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.yaml new file mode 100644 index 000000000000..30b458c41cac --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs + +maintainers: + - Vignesh Raghavendra + +properties: + compatible: + const: ti,am654-hbmc + + reg: + maxItems: 2 + + power-domains: true + '#address-cells': true + '#size-cells': true + ranges: true + + mux-controls: + description: MMIO mux controller node to select b/w OSPI and HBMC. + + clocks: + maxItems: 1 + +patternProperties: + "^flash@[0-1],[0-9a-f]+$": + type: object + +required: + - compatible + - reg + - ranges + - clocks + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + hbmc: memory-controller@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x0 0x47034000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */ + <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */ + clocks = <&k3_clks 102 0>; + #address-cells = <2>; + #size-cells = <1>; + power-domains = <&k3_pds 55>; + mux-controls = <&hbmc_mux 0>; + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mux/adi,adg792a.txt b/Documentation/devicetree/bindings/mux/adi,adg792a.txt index 96b787a69f50..b0e5bf6903d8 100644 --- a/Documentation/devicetree/bindings/mux/adi,adg792a.txt +++ b/Documentation/devicetree/bindings/mux/adi,adg792a.txt @@ -5,7 +5,7 @@ Required properties: - #mux-control-cells : <0> if parallel (the three muxes are bound together with a single mux controller controlling all three muxes), or <1> if not (one mux controller for each mux). -* Standard mux-controller bindings as described in mux-controller.txt +* Standard mux-controller bindings as described in mux-controller.yaml Optional properties for ADG792G: - gpio-controller : if present, #gpio-cells below is required. diff --git a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt b/Documentation/devicetree/bindings/mux/adi,adgs1408.txt index be6947f4d86b..453a38961c13 100644 --- a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt +++ b/Documentation/devicetree/bindings/mux/adi,adgs1408.txt @@ -4,7 +4,7 @@ Required properties: - compatible : Should be one of * "adi,adgs1408" * "adi,adgs1409" -* Standard mux-controller bindings as described in mux-controller.txt +* Standard mux-controller bindings as described in mux-controller.yaml Optional properties for ADGS1408/1409: - gpio-controller : if present, #gpio-cells is required. diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.txt b/Documentation/devicetree/bindings/mux/gpio-mux.txt deleted file mode 100644 index b8f746344d80..000000000000 --- a/Documentation/devicetree/bindings/mux/gpio-mux.txt +++ /dev/null @@ -1,69 +0,0 @@ -GPIO-based multiplexer controller bindings - -Define what GPIO pins are used to control a multiplexer. Or several -multiplexers, if the same pins control more than one multiplexer. - -Required properties: -- compatible : "gpio-mux" -- mux-gpios : list of gpios used to control the multiplexer, least - significant bit first. -- #mux-control-cells : <0> -* Standard mux-controller bindings as decribed in mux-controller.txt - -Optional properties: -- idle-state : if present, the state the mux will have when idle. The - special state MUX_IDLE_AS_IS is the default. - -The multiplexer state is defined as the number represented by the -multiplexer GPIO pins, where the first pin is the least significant -bit. An active pin is a binary 1, an inactive pin is a binary 0. - -Example: - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync-1", "in", "out", "sync-2"; - }; - - i2c-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - /* ... */ - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - /* ... */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml new file mode 100644 index 000000000000..0a7c8d64981a --- /dev/null +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/gpio-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO-based multiplexer controller bindings + +maintainers: + - Peter Rosin + +description: |+ + Define what GPIO pins are used to control a multiplexer. Or several + multiplexers, if the same pins control more than one multiplexer. + + The multiplexer state is defined as the number represented by the + multiplexer GPIO pins, where the first pin is the least significant + bit. An active pin is a binary 1, an inactive pin is a binary 0. + +properties: + compatible: + const: gpio-mux + + mux-gpios: + description: + List of gpios used to control the multiplexer, least significant bit first. + + '#mux-control-cells': + const: 0 + + idle-state: + default: -1 + +required: + - compatible + - mux-gpios + - "#mux-control-cells" + +additionalProperties: false + +examples: + - | + #include + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, + <&pioA 1 GPIO_ACTIVE_HIGH>; + }; + + adc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 0>; + io-channel-names = "parent"; + + mux-controls = <&mux>; + + channels = "sync-1", "in", "out", "sync-2"; + }; + + i2c-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c1>; + + mux-controls = <&mux>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssd1307: oled@3c { + reg = <0x3c>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: pca9555@20 { + reg = <0x20>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mux/mux-consumer.yaml b/Documentation/devicetree/bindings/mux/mux-consumer.yaml new file mode 100644 index 000000000000..7af93298ab5c --- /dev/null +++ b/Documentation/devicetree/bindings/mux/mux-consumer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/mux-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common multiplexer controller consumer bindings + +maintainers: + - Peter Rosin + +description: | + Mux controller consumers should specify a list of mux controllers that they + want to use with a property containing a 'mux-ctrl-list': + + mux-ctrl-list ::= [mux-ctrl-list] + single-mux-ctrl ::= [mux-ctrl-specifier] + mux-ctrl-phandle : phandle to mux controller node + mux-ctrl-specifier : array of #mux-control-cells specifying the + given mux controller (controller specific) + + Mux controller properties should be named "mux-controls". The exact meaning of + each mux controller property must be documented in the device tree binding for + each consumer. An optional property "mux-control-names" may contain a list of + strings to label each of the mux controllers listed in the "mux-controls" + property. + + mux-ctrl-specifier typically encodes the chip-relative mux controller number. + If the mux controller chip only provides a single mux controller, the + mux-ctrl-specifier can typically be left out. + +select: true + +properties: + mux-controls: + $ref: /schemas/types.yaml#/definitions/phandle-array + + mux-control-names: + description: + Devices that use more than a single mux controller can use the + "mux-control-names" property to map the name of the requested mux + controller to an index into the list given by the "mux-controls" property. + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/mux/mux-controller.txt b/Documentation/devicetree/bindings/mux/mux-controller.txt deleted file mode 100644 index 4f47e4bd2fa0..000000000000 --- a/Documentation/devicetree/bindings/mux/mux-controller.txt +++ /dev/null @@ -1,157 +0,0 @@ -Common multiplexer controller bindings -====================================== - -A multiplexer (or mux) controller will have one, or several, consumer devices -that uses the mux controller. Thus, a mux controller can possibly control -several parallel multiplexers. Presumably there will be at least one -multiplexer needed by each consumer, but a single mux controller can of course -control several multiplexers for a single consumer. - -A mux controller provides a number of states to its consumers, and the state -space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer, -0-7 for an 8-way multiplexer, etc. - - -Consumers ---------- - -Mux controller consumers should specify a list of mux controllers that they -want to use with a property containing a 'mux-ctrl-list': - - mux-ctrl-list ::= [mux-ctrl-list] - single-mux-ctrl ::= [mux-ctrl-specifier] - mux-ctrl-phandle : phandle to mux controller node - mux-ctrl-specifier : array of #mux-control-cells specifying the - given mux controller (controller specific) - -Mux controller properties should be named "mux-controls". The exact meaning of -each mux controller property must be documented in the device tree binding for -each consumer. An optional property "mux-control-names" may contain a list of -strings to label each of the mux controllers listed in the "mux-controls" -property. - -Drivers for devices that use more than a single mux controller can use the -"mux-control-names" property to map the name of the requested mux controller -to an index into the list given by the "mux-controls" property. - -mux-ctrl-specifier typically encodes the chip-relative mux controller number. -If the mux controller chip only provides a single mux controller, the -mux-ctrl-specifier can typically be left out. - -Example: - - /* One consumer of a 2-way mux controller (one GPIO-line) */ - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - mux-control-names = "adc"; - - channels = "sync", "in"; - }; - -Note that in the example above, specifying the "mux-control-names" is redundant -because there is only one mux controller in the list. However, if the driver -for the consumer node in fact asks for a named mux controller, that name is of -course still required. - - /* - * Two consumers (one for an ADC line and one for an i2c bus) of - * parallel 4-way multiplexers controlled by the same two GPIO-lines. - */ - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync-1", "in", "out", "sync-2"; - }; - - i2c-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - /* ... */ - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - /* ... */ - }; - }; - }; - - -Mux controller nodes --------------------- - -Mux controller nodes must specify the number of cells used for the -specifier using the '#mux-control-cells' property. - -Optionally, mux controller nodes can also specify the state the mux should -have when it is idle. The idle-state property is used for this. If the -idle-state is not present, the mux controller is typically left as is when -it is idle. For multiplexer chips that expose several mux controllers, the -idle-state property is an array with one idle state for each mux controller. - -The special value (-1) may be used to indicate that the mux should be left -as is when it is idle. This is the default, but can still be useful for -mux controller chips with more than one mux controller, particularly when -there is a need to "step past" a mux controller and set some other idle -state for a mux controller with a higher index. - -Some mux controllers have the ability to disconnect the input/output of the -multiplexer. Using this disconnected high-impedance state as the idle state -is indicated with idle state (-2). - -These constants are available in - - #include - -as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2). - -An example mux controller node look like this (the adg972a chip is a triple -4-way multiplexer): - - mux: mux-controller@50 { - compatible = "adi,adg792a"; - reg = <0x50>; - #mux-control-cells = <1>; - - idle-state = ; - }; diff --git a/Documentation/devicetree/bindings/mux/mux-controller.yaml b/Documentation/devicetree/bindings/mux/mux-controller.yaml new file mode 100644 index 000000000000..736a84c3b6a5 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/mux-controller.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/mux-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common multiplexer controller provider bindings + +maintainers: + - Peter Rosin + +description: | + A multiplexer (or mux) controller will have one, or several, consumer devices + that uses the mux controller. Thus, a mux controller can possibly control + several parallel multiplexers. Presumably there will be at least one + multiplexer needed by each consumer, but a single mux controller can of course + control several multiplexers for a single consumer. + + A mux controller provides a number of states to its consumers, and the state + space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer, + 0-7 for an 8-way multiplexer, etc. + + + Mux controller nodes + -------------------- + + Mux controller nodes must specify the number of cells used for the + specifier using the '#mux-control-cells' property. + + Optionally, mux controller nodes can also specify the state the mux should + have when it is idle. The idle-state property is used for this. If the + idle-state is not present, the mux controller is typically left as is when + it is idle. For multiplexer chips that expose several mux controllers, the + idle-state property is an array with one idle state for each mux controller. + + The special value (-1) may be used to indicate that the mux should be left + as is when it is idle. This is the default, but can still be useful for + mux controller chips with more than one mux controller, particularly when + there is a need to "step past" a mux controller and set some other idle + state for a mux controller with a higher index. + + Some mux controllers have the ability to disconnect the input/output of the + multiplexer. Using this disconnected high-impedance state as the idle state + is indicated with idle state (-2). + + These constants are available in + + #include + + as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2). + + An example mux controller node look like this (the adg972a chip is a triple + 4-way multiplexer): + + mux: mux-controller@50 { + compatible = "adi,adg792a"; + reg = <0x50>; + #mux-control-cells = <1>; + + idle-state = ; + }; + +select: + anyOf: + - properties: + $nodename: + pattern: '^mux-controller' + - required: + - '#mux-control-cells' + +properties: + $nodename: + pattern: '^mux-controller(@.*|-[0-9a-f]+)?$' + + '#mux-control-cells': + enum: [ 0, 1 ] + + idle-state: + $ref: /schemas/types.yaml#/definitions/int32 + minimum: -2 + + idle-states: + description: | + Mux controller nodes can specify the state the mux should have when it is + idle. If the idle-state is not present, the mux controller is typically + left as is when it is idle. For multiplexer chips that expose several mux + controllers, the idle-state property is an array with one idle state for + each mux controller. + + The special value (-1) may be used to indicate that the mux should be left + as is when it is idle. This is the default, but can still be useful for + mux controller chips with more than one mux controller, particularly when + there is a need to "step past" a mux controller and set some other idle + state for a mux controller with a higher index. + + Some mux controllers have the ability to disconnect the input/output of the + multiplexer. Using this disconnected high-impedance state as the idle state + is indicated with idle state (-2). + $ref: /schemas/types.yaml#/definitions/int32-array + items: + minimum: -2 + +additionalProperties: true + +examples: + - | + #include + + /* One consumer of a 2-way mux controller (one GPIO-line) */ + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>; + }; + + adc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 0>; + io-channel-names = "parent"; + + mux-controls = <&mux>; + mux-control-names = "adc"; + + channels = "sync", "in"; + }; + + - | + #include + + /* + * Two consumers (one for an ADC line and one for an i2c bus) of + * parallel 4-way multiplexers controlled by the same two GPIO-lines. + */ + mux2: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, + <&pioA 1 GPIO_ACTIVE_HIGH>; + }; + + adc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 0>; + io-channel-names = "parent"; + + mux-controls = <&mux2>; + + channels = "sync-1", "in", "out", "sync-2"; + }; + + i2c-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c1>; + + mux-controls = <&mux2>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssd1307: oled@3c { + reg = <0x3c>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: pca9555@20 { + reg = <0x20>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mux/reg-mux.txt b/Documentation/devicetree/bindings/mux/reg-mux.txt deleted file mode 100644 index 4afd7ba73d60..000000000000 --- a/Documentation/devicetree/bindings/mux/reg-mux.txt +++ /dev/null @@ -1,129 +0,0 @@ -Generic register bitfield-based multiplexer controller bindings - -Define register bitfields to be used to control multiplexers. The parent -device tree node must be a device node to provide register r/w access. - -Required properties: -- compatible : should be one of - "reg-mux" : if parent device of mux controller is not syscon device - "mmio-mux" : if parent device of mux controller is syscon device -- #mux-control-cells : <1> -- mux-reg-masks : an array of register offset and pre-shifted bitfield mask - pairs, each describing a single mux control. -* Standard mux-controller bindings as decribed in mux-controller.txt - -Optional properties: -- idle-states : if present, the state the muxes will have when idle. The - special state MUX_IDLE_AS_IS is the default. - -The multiplexer state of each multiplexer is defined as the value of the -bitfield described by the corresponding register offset and bitfield mask -pair in the mux-reg-masks array. - -Example 1: -The parent device of mux controller is not a syscon device. - -&i2c0 { - fpga@66 { // fpga connected to i2c - compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", - "simple-mfd"; - reg = <0x66>; - - mux: mux-controller { - compatible = "reg-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ - <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ - }; - }; -}; - -mdio-mux-1 { - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 0>; - mdio-parent-bus = <&emdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@8 { - reg = <0x8>; - #address-cells = <1>; - #size-cells = <0>; - }; - - .. - .. -}; - -mdio-mux-2 { - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 1>; - mdio-parent-bus = <&emdio2>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - .. - .. -}; - -Example 2: -The parent device of mux controller is syscon device. - -syscon { - compatible = "syscon"; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - - mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ - <0x3 0x40>, /* 1: reg 0x3, bit 6 */ - idle-states = , <0>; - }; -}; - -video-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - - ports { - /* inputs 0..3 */ - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - port@2 { - reg = <2>; - }; - port@3 { - reg = <3>; - }; - - /* output */ - port@4 { - reg = <4>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mux/reg-mux.yaml b/Documentation/devicetree/bindings/mux/reg-mux.yaml new file mode 100644 index 000000000000..60d5746eb39d --- /dev/null +++ b/Documentation/devicetree/bindings/mux/reg-mux.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/reg-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic register bitfield-based multiplexer controller bindings + +maintainers: + - Peter Rosin + +description: |+ + Define register bitfields to be used to control multiplexers. The parent + device tree node must be a device node to provide register r/w access. + +properties: + compatible: + enum: + - reg-mux # parent device of mux controller is not syscon device + - mmio-mux # parent device of mux controller is syscon device + + reg: true + + '#mux-control-cells': + const: 1 + + mux-reg-masks: + description: an array of register offset and pre-shifted bitfield mask + pairs, each describing a single mux control. + + idle-states: true + +required: + - compatible + - mux-reg-masks + - '#mux-control-cells' + +additionalProperties: false + +examples: + - | + /* The parent device of mux controller is not a syscon device. */ + + #include + + mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = + <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ + }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux1 0>; + mdio-parent-bus = <&emdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux1 1>; + mdio-parent-bus = <&emdio2>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + - | + /* The parent device of mux controller is syscon device. */ + + #include + syscon@1000 { + compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; + reg = <0x1000 0x100>; + + mux2: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = + <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ + <0x3 0x40>; /* 1: reg 0x3, bit 6 */ + idle-states = , <0>; + }; + }; + + video-mux { + compatible = "video-mux"; + mux-controls = <&mux2 0>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* inputs 0..3 */ + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + + /* output */ + port@4 { + reg = <4>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 0467441d7037..608e1d62bed5 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -43,7 +43,6 @@ allOf: properties: clocks: minItems: 3 - maxItems: 4 items: - description: GMAC main clock - description: First parent clock of the internal mux @@ -52,7 +51,6 @@ allOf: clock-names: minItems: 3 - maxItems: 4 items: - const: stmmaceth - const: clkin0 diff --git a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml index 2f46e45dcd60..a93d2f165899 100644 --- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml +++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml @@ -23,14 +23,12 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: RX interrupt - description: TX interrupt interrupt-names: minItems: 1 - maxItems: 2 items: - const: rx - const: tx diff --git a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt b/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt index b58843f29591..deb9e852ea27 100644 --- a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt +++ b/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt @@ -17,7 +17,7 @@ Optional properties: - clocks: phandle of the core clock which drives the mdio block. Additional information regarding generic multiplexer properties can be found -at- Documentation/devicetree/bindings/net/mdio-mux.txt +at- Documentation/devicetree/bindings/net/mdio-mux.yaml for example: diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 798fa5fb7bb2..f84e31348d80 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -30,14 +30,12 @@ properties: - description: interrupt line0 - description: interrupt line1 minItems: 1 - maxItems: 2 interrupt-names: items: - const: int0 - const: int1 minItems: 1 - maxItems: 2 clocks: items: diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt index 2d504256b0d8..366479806acb 100644 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ b/Documentation/devicetree/bindings/net/can/c_can.txt @@ -19,10 +19,10 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only: - power-domains : Should contain a phandle to a PM domain provider node and an args specifier containing the DCAN device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - clocks : CAN functional clock phandle. This property is as per the binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt + Documentation/devicetree/bindings/clock/ti,sci-clk.yaml Optional properties: - syscon-raminit : Handle to system control region that contains the diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml index d730fe5a4355..d159ac78cec1 100644 --- a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml +++ b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml @@ -48,14 +48,12 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: switch's main clock - description: dividing of the switch core clock clock-names: minItems: 1 - maxItems: 2 items: - const: sw_switch - const: sw_switch_mdiv diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt deleted file mode 100644 index 4d91a36c5cf5..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-gpio.txt +++ /dev/null @@ -1,27 +0,0 @@ -MDIO on GPIOs - -Currently defined compatibles: -- virtual,gpio-mdio -- microchip,mdio-smi0 - -MDC and MDIO lines connected to GPIO controllers are listed in the -gpios property as described in section VIII.1 in the following order: - -MDC, MDIO. - -Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases" -node. - -Example: - -aliases { - mdio-gpio0 = &mdio0; -}; - -mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qe_pio_a 11 - &qe_pio_c 6>; -}; diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.yaml b/Documentation/devicetree/bindings/net/mdio-gpio.yaml new file mode 100644 index 000000000000..1d83b8dcce2c --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-gpio.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mdio-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MDIO on GPIOs + +maintainers: + - Andrew Lunn + - Heiner Kallweit + - Russell King + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + enum: + - virtual,mdio-gpio + - microchip,mdio-smi0 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + gpios: + minItems: 2 + items: + - description: MDC + - description: MDIO + - description: MDO + +#Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases" +#node. +additionalProperties: + type: object + +examples: + - | + aliases { + mdio-gpio0 = &mdio0; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&qe_pio_a 11>, + <&qe_pio_c 6>; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt deleted file mode 100644 index 694987d3c17a..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt +++ /dev/null @@ -1,119 +0,0 @@ -Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. - -This is a special case of a MDIO bus multiplexer. One or more GPIO -lines are used to control which child bus is connected. - -Required properties in addition to the generic multiplexer properties: - -- compatible : mdio-mux-gpio. -- gpios : GPIO specifiers for each GPIO line. One or more must be specified. - - -Example : - - /* The parent MDIO bus. */ - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - }; - - /* - An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a - pair of GPIO lines. Child busses 2 and 3 populated with 4 - PHYs each. - */ - mdio-mux { - compatible = "mdio-mux-gpio"; - gpios = <&gpio1 3 0>, <&gpio1 4 0>; - mdio-parent-bus = <&smi1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy11: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy12: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy13: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy14: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - }; - - mdio@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - phy21: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy22: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy23: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy24: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml b/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml new file mode 100644 index 000000000000..71c25c4580ea --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. + +maintainers: + - Andrew Lunn + +description: + This is a special case of a MDIO bus multiplexer. One or more GPIO + lines are used to control which child bus is connected. + +allOf: + - $ref: /schemas/net/mdio-mux.yaml# + +properties: + compatible: + const: mdio-mux-gpio + + gpios: + description: + List of GPIOs used to control the multiplexer, least significant bit first. + minItems: 1 + maxItems: 32 + +required: + - compatible + - gpios + +unevaluatedProperties: false + +examples: + - | + /* + An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a + pair of GPIO lines. Child busses 2 and 3 populated with 4 + PHYs each. + */ + mdio-mux { + compatible = "mdio-mux-gpio"; + gpios = <&gpio1 3 0>, <&gpio1 4 0>; + mdio-parent-bus = <&smi1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <1>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + ethernet-phy@2 { + reg = <2>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + ethernet-phy@3 { + reg = <3>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + ethernet-phy@4 { + reg = <4>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <10 8>; /* Pin 10, active low */ + }; + }; + + mdio@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <1>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + ethernet-phy@2 { + reg = <2>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + ethernet-phy@3 { + reg = <3>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + ethernet-phy@4 { + reg = <4>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt deleted file mode 100644 index 065e8bdb957d..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt +++ /dev/null @@ -1,75 +0,0 @@ -Properties for an MDIO bus multiplexer controlled by a memory-mapped device - -This is a special case of a MDIO bus multiplexer. A memory-mapped device, -like an FPGA, is used to control which child bus is connected. The mdio-mux -node must be a child of the memory-mapped device. The driver currently only -supports devices with 8, 16 or 32-bit registers. - -Required properties in addition to the generic multiplexer properties: - -- compatible : string, must contain "mdio-mux-mmioreg" - -- reg : integer, contains the offset of the register that controls the bus - multiplexer. The size field in the 'reg' property is the size of - register, and must therefore be 1, 2, or 4. - -- mux-mask : integer, contains an eight-bit mask that specifies which - bits in the register control the actual bus multiplexer. The - 'reg' property of each child mdio-mux node must be constrained by - this mask. - -Example: - -The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes. -For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus. -A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on -BRDCFG1 that control the actual mux. - - /* The FPGA node */ - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; - reg = <3 0 0x30>; - ranges = <0 3 0 0x30>; - - mdio-mux-emi2 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&xmdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <9 1>; // BRDCFG1 - mux-mask = <0x6>; // EMI2 - - emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2) - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - phy_xgmii_slot1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <4>; - }; - }; - - emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1) - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy_xgmii_slot2: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - }; - }; - }; - - /* The parent MDIO bus. */ - xmdio0: mdio@f1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - interrupts = <100 1 0 0>; - }; diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml new file mode 100644 index 000000000000..cf86bb0b0b62 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device + +maintainers: + - Andrew Lunn + +description: |+ + This is a special case of a MDIO bus multiplexer. A memory-mapped device, + like an FPGA, is used to control which child bus is connected. The mdio-mux + node must be a child of the memory-mapped device. The driver currently only + supports devices with 8, 16 or 32-bit registers. + +allOf: + - $ref: /schemas/net/mdio-mux.yaml# + +properties: + compatible: + items: + - const: mdio-mux-mmioreg + - const: mdio-mux + + reg: + description: Contains the offset of the register that controls the bus + multiplexer. The size field in the 'reg' property is the size of register, + and must therefore be 1, 2, or 4. + maxItems: 1 + + mux-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Contains an eight-bit mask that specifies which bits in the + register control the actual bus multiplexer. The 'reg' property of each + child mdio-mux node must be constrained by this mask. + +required: + - compatible + - reg + - mux-mask + +unevaluatedProperties: false + +examples: + - | + mdio-mux@9 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&xmdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <9 1>; // BRDCFG1 + mux-mask = <0x6>; // EMI2 + + mdio@0 { // Slot 1 XAUI (FM2) + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_xgmii_slot1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + + mdio@2 { // Slot 2 XAUI (FM1) + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt deleted file mode 100644 index 534e38058fe0..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt +++ /dev/null @@ -1,82 +0,0 @@ -Properties for an MDIO bus multiplexer consumer device - -This is a special case of MDIO mux when MDIO mux is defined as a consumer -of a mux producer device. The mux producer can be of any type like mmio mux -producer, gpio mux producer or generic register based mux producer. - -Required properties in addition to the MDIO Bus multiplexer properties: - -- compatible : should be "mmio-mux-multiplexer" -- mux-controls : mux controller node to use for operating the mux -- mdio-parent-bus : phandle to the parent MDIO bus. - -each child node of mdio bus multiplexer consumer device represent a mdio -bus. - -for more information please refer -Documentation/devicetree/bindings/mux/mux-controller.txt -and Documentation/devicetree/bindings/net/mdio-mux.txt - -Example: -In below example the Mux producer and consumer are separate nodes. - -&i2c0 { - fpga@66 { // fpga connected to i2c - compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", - "simple-mfd"; - reg = <0x66>; - - mux: mux-controller { // Mux Producer - compatible = "reg-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ - <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ - }; - }; -}; - -mdio-mux-1 { // Mux consumer - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 0>; - mdio-parent-bus = <&emdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@8 { - reg = <0x8>; - #address-cells = <1>; - #size-cells = <0>; - }; - - .. - .. -}; - -mdio-mux-2 { // Mux consumer - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 1>; - mdio-parent-bus = <&emdio2>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - .. - .. -}; diff --git a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml new file mode 100644 index 000000000000..282987074ee4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Properties for an MDIO bus multiplexer consumer device + +maintainers: + - Andrew Lunn + +description: |+ + This is a special case of MDIO mux when MDIO mux is defined as a consumer + of a mux producer device. The mux producer can be of any type like mmio mux + producer, gpio mux producer or generic register based mux producer. + + +allOf: + - $ref: /schemas/net/mdio-mux.yaml# + +properties: + compatible: + const: mdio-mux-multiplexer + + mux-controls: + maxItems: 1 + +required: + - compatible + - mux-controls + +unevaluatedProperties: false + +examples: + - | + mux: mux-controller { // Mux Producer + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ + }; + + mdio-mux-1 { // Mux consumer + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { // Mux consumer + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt deleted file mode 100644 index f58571f36570..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux.txt +++ /dev/null @@ -1,129 +0,0 @@ -Common MDIO bus multiplexer/switch properties. - -An MDIO bus multiplexer/switch will have several child busses that are -numbered uniquely in a device dependent manner. The nodes for an MDIO -bus multiplexer/switch will have one child node for each child bus. - -Required properties: -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- mdio-parent-bus : phandle to the parent MDIO bus. - -- Other properties specific to the multiplexer/switch hardware. - -Required properties for child nodes: -- #address-cells = <1>; -- #size-cells = <0>; -- reg : The sub-bus number. - - -Example : - - /* The parent MDIO bus. */ - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - }; - - /* - An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a - pair of GPIO lines. Child busses 2 and 3 populated with 4 - PHYs each. - */ - mdio-mux { - compatible = "mdio-mux-gpio"; - gpios = <&gpio1 3 0>, <&gpio1 4 0>; - mdio-parent-bus = <&smi1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy11: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy12: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy13: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy14: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - }; - - mdio@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - phy21: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy22: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy23: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy24: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mdio-mux.yaml b/Documentation/devicetree/bindings/net/mdio-mux.yaml new file mode 100644 index 000000000000..d169adf5d9f4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mdio-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common MDIO bus multiplexer/switch properties. + +maintainers: + - Andrew Lunn + +description: |+ + An MDIO bus multiplexer/switch will have several child busses that are + numbered uniquely in a device dependent manner. The nodes for an MDIO + bus multiplexer/switch will have one child node for each child bus. + +properties: + $nodename: + pattern: '^mdio-mux[\-@]?' + + mdio-parent-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the MDIO bus that this multiplexer's master-side port is + connected to. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^mdio@[0-9a-f]+$': + type: object + + properties: + reg: + maxItems: 1 + description: The sub-bus number. + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 56f2235f5fb5..d7652596a09b 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -91,7 +91,6 @@ properties: interrupts: minItems: 1 - maxItems: 3 items: - description: Combined signal for various interrupt events - description: The interrupt to manage the remote wake-up packet detection @@ -99,7 +98,6 @@ properties: interrupt-names: minItems: 1 - maxItems: 3 items: - const: macirq - const: eth_wake_irq diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 27eb6066793f..19c7bd482a51 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -46,7 +46,6 @@ properties: clocks: minItems: 3 - maxItems: 5 items: - description: GMAC main clock - description: MAC TX clock diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index f90557f6deb8..b9589a0daa5c 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -25,14 +25,12 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: PCIe host controller - description: builtin MSI controller interrupt-names: minItems: 1 - maxItems: 2 items: - const: pcie - const: msi diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml index 81bae060cbde..82bc6c486ca3 100644 --- a/Documentation/devicetree/bindings/pci/loongson.yaml +++ b/Documentation/devicetree/bindings/pci/loongson.yaml @@ -24,7 +24,6 @@ properties: reg: minItems: 1 - maxItems: 2 items: - description: CFG0 standard config space register - description: CFG1 extended config space register diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index e7b1f9892da4..742206dbd965 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,7 +70,6 @@ properties: reset-names: minItems: 1 - maxItems: 2 items: - const: phy - const: mac diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 04251d71f56b..fb95c276a986 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -26,14 +26,12 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: PCIe host controller - description: builtin MSI controller interrupt-names: minItems: 1 - maxItems: 2 items: - const: pcie - const: msi diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt deleted file mode 100644 index 47202a2938f2..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ /dev/null @@ -1,115 +0,0 @@ -TI Keystone PCIe interface - -Keystone PCI host Controller is based on the Synopsys DesignWare PCI -hardware version 3.65. It shares common functions with the PCIe DesignWare -core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt - -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt -for the details of DesignWare DT bindings. Additional properties are -described here as well as properties that are not applicable. - -Required Properties:- - -compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC - Should be "ti,am654-pcie-rc" for RC on AM654x SoC -reg: Three register ranges as listed in the reg-names property -reg-names: "dbics" for the DesignWare PCIe registers, "app" for the - TI specific application registers, "config" for the - configuration space address - -pcie_msi_intc : Interrupt controller device node for MSI IRQ chip - interrupt-cells: should be set to 1 - interrupts: GIC interrupt lines connected to PCI MSI interrupt lines - (required if the compatible is "ti,keystone-pcie") -msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt - (required if the compatible is "ti,am654-pcie-rc". - -ti,syscon-pcie-id : phandle to the device control module required to set device - id and vendor id. -ti,syscon-pcie-mode : phandle to the device control module required to configure - PCI in either RC mode or EP mode. - - Example: - pcie_msi_intc: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - -pcie_intc: Interrupt controller device node for Legacy IRQ chip - interrupt-cells: should be set to 1 - - Example: - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - -Optional properties:- - phys: phandle to generic Keystone SerDes PHY for PCI - phy-names: name of the generic Keystone SerDes PHY for PCI - - If boot loader already does PCI link establishment, then phys and - phy-names shouldn't be present. - interrupts: platform interrupt for error interrupts. - -DesignWare DT Properties not applicable for Keystone PCI - -1. pcie_bus clock-names not used. Instead, a phandle to phys is used. - -AM654 PCIe Endpoint -=================== - -Required Properties:- - -compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC -reg: Four register ranges as listed in the reg-names property -reg-names: "dbics" for the DesignWare PCIe registers, "app" for the - TI specific application registers, "atu" for the - Address Translation Unit configuration registers and - "addr_space" used to map remote RC address space -num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt -num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt -num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt -power-domains: As documented by the generic PM domain bindings in - Documentation/devicetree/bindings/power/power_domain.txt. -ti,syscon-pcie-mode: phandle to the device control module required to configure - PCI in either RC mode or EP mode. - -Optional properties:- - -phys: list of PHY specifiers (used by generic PHY framework) -phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of lanes as specified in *num-lanes* property. -("phys" and "phy-names" DT bindings are specified in -Documentation/devicetree/bindings/phy/phy-bindings.txt) -interrupts: platform interrupt for error interrupts. - -pcie-ep { - compatible = "ti,am654-pcie-ep"; - reg = <0x5500000 0x1000>, <0x5501000 0x1000>, - <0x10000000 0x8000000>, <0x5506000 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120>; - ti,syscon-pcie-mode = <&pcie0_mode>; - num-lanes = <1>; - num-ib-windows = <16>; - num-ob-windows = <16>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 0da458a051b6..25f4def468bf 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-ipq6018" for ipq6018 - reg: Usage: required @@ -123,6 +124,16 @@ - "ahb" AHB clock - "aux" Auxiliary clock +- clock-names: + Usage: required for ipq6018 + Value type: + Definition: Should contain the following entries + - "iface" PCIe to SysNOC BIU clock + - "axi_m" AXI Master clock + - "axi_s" AXI Slave clock + - "axi_bridge" AXI bridge clock + - "rchng" + - clock-names: Usage: required for qcs404 Value type: @@ -209,6 +220,19 @@ - "ahb" AHB Reset - "axi_m_sticky" AXI Master Sticky reset +- reset-names: + Usage: required for ipq6018 + Value type: + Definition: Should contain the following entries + - "pipe" PIPE reset + - "sleep" Sleep reset + - "sticky" Core Sticky reset + - "axi_m" AXI Master reset + - "axi_s" AXI Slave reset + - "ahb" AHB Reset + - "axi_m_sticky" AXI Master Sticky reset + - "axi_s_sticky" AXI Slave Sticky reset + - reset-names: Usage: required for qcs404 Value type: diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml new file mode 100644 index 000000000000..78c217d362a7 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM65 PCI Endpoint + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: pci-ep.yaml# + +properties: + compatible: + enum: + - ti,am654-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: app + - const: dbics + - const: addr_space + - const: atu + + power-domains: + maxItems: 1 + + ti,syscon-pcie-mode: + description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + minItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - reg-names + - max-link-speed + - power-domains + - ti,syscon-pcie-mode + - dma-coherent + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie0_ep: pcie-ep@5500000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x8000000>, + <0x5506000 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,syscon-pcie-mode = <&pcie0_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml new file mode 100644 index 000000000000..834dc1c1743c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM65 PCI Host + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + enum: + - ti,am654-pcie-rc + - ti,keystone-pcie + + reg: + maxItems: 4 + + reg-names: + items: + - const: app + - const: dbics + - const: config + - const: atu + + power-domains: + maxItems: 1 + + ti,syscon-pcie-id: + description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID + $ref: /schemas/types.yaml#/definitions/phandle + + ti,syscon-pcie-mode: + description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. + $ref: /schemas/types.yaml#/definitions/phandle + + msi-map: true + + dma-coherent: true + +required: + - compatible + - reg + - reg-names + - max-link-speed + - ti,syscon-pcie-id + - ti,syscon-pcie-mode + - ranges + +if: + properties: + compatible: + enum: + - ti,am654-pcie-rc +then: + required: + - dma-coherent + - power-domains + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie0_rc: pcie@5500000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x2000>, + <0x5506000 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x10020000 0 0x00010000>, + <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie0_mode>; + bus-range = <0x0 0xff>; + num-viewport = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = ; + msi-map = <0x0 &gic_its 0x0 0x10000>; + device_type = "pci"; + }; diff --git a/Documentation/devicetree/bindings/perf/arm,cmn.yaml b/Documentation/devicetree/bindings/perf/arm,cmn.yaml index e4fcc0de25e2..42424ccbdd0c 100644 --- a/Documentation/devicetree/bindings/perf/arm,cmn.yaml +++ b/Documentation/devicetree/bindings/perf/arm,cmn.yaml @@ -21,7 +21,6 @@ properties: interrupts: minItems: 1 - maxItems: 4 items: - description: Overflow interrupt for DTC0 - description: Overflow interrupt for DTC1 diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index f80431060803..e288450e0844 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -15,7 +15,9 @@ properties: const: 1 compatible: - const: allwinner,sun8i-h3-usb-phy + enum: + - allwinner,sun8i-h3-usb-phy + - allwinner,sun50i-h616-usb-phy reg: items: diff --git a/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml index 9a2e779e6d38..0f0bcde9eb88 100644 --- a/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml +++ b/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml @@ -28,7 +28,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: usbh - const: usb_ref diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml index 5f9e91bfb5ff..43a4b880534c 100644 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml @@ -22,7 +22,6 @@ properties: reg: minItems: 1 - maxItems: 6 items: - description: the base CTRL register - description: XHCI EC register @@ -33,7 +32,6 @@ properties: reg-names: minItems: 1 - maxItems: 6 items: - const: ctrl - const: xhci_ec @@ -51,7 +49,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: sw_usb - const: sw_usb3 diff --git a/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml index 04edda504ab6..cb1aa325336f 100644 --- a/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml +++ b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml @@ -35,7 +35,6 @@ properties: reg-names: minItems: 1 - maxItems: 2 items: - const: phy - const: phy-ctrl diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml similarity index 100% rename from drivers/staging/hikey9xx/phy-hi3670-usb3.yaml rename to Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml index 0ccaded3f245..29d4123323c2 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -16,6 +16,9 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + "#phy-cells": const: 1 description: selects if the phy is dual-ported @@ -23,6 +26,7 @@ properties: required: - compatible - reg + - clocks - "#phy-cells" additionalProperties: false @@ -32,5 +36,6 @@ examples: pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc 0>; #phy-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index b8a7651a3d9a..ef9d9d4e6875 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -131,7 +131,6 @@ patternProperties: clocks: minItems: 1 - maxItems: 2 items: - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) - description: Reference clock of analog phy @@ -141,7 +140,6 @@ patternProperties: clock-names: minItems: 1 - maxItems: 2 items: - const: ref - const: da_ref diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index 84383e2e0b34..e71b32c9c0d1 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -31,14 +31,12 @@ properties: resets: minItems: 1 - maxItems: 2 items: - description: Sierra PHY reset. - description: Sierra APB reset. This is optional. reset-names: minItems: 1 - maxItems: 2 items: - const: sierra_reset - const: sierra_apb diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 320a232c7208..bd9ae11c9994 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -52,28 +52,24 @@ properties: reg: minItems: 1 - maxItems: 2 items: - description: Offset of the Torrent PHY configuration registers. - description: Offset of the DPTX PHY configuration registers. reg-names: minItems: 1 - maxItems: 2 items: - const: torrent_phy - const: dptx_phy resets: minItems: 1 - maxItems: 2 items: - description: Torrent PHY reset. - description: Torrent APB reset. This is optional. reset-names: minItems: 1 - maxItems: 2 items: - const: torrent_reset - const: torrent_apb diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml index fb29ad807b68..a5b027a6e70f 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml @@ -14,6 +14,7 @@ properties: enum: - rockchip,px30-usb2phy - rockchip,rk3228-usb2phy + - rockchip,rk3308-usb2phy - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 018cc1246ee1..3329f1d33a4f 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -74,6 +74,13 @@ patternProperties: "#phy-cells": enum: [ 0x0, 0x1 ] + connector: + type: object + allOf: + - $ref: ../connector/usb-connector.yaml + properties: + vbus-supply: true + allOf: - if: properties: @@ -130,6 +137,10 @@ examples: reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; }; usbphyc_port1: usb-phy@1 { diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml index 17f132ce5516..35296c588e78 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml @@ -30,7 +30,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: ref - const: xo diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml index 17fd7f6b83bb..6cf5c6c06072 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml @@ -30,7 +30,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: ref - const: xo diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 7808ec8bc712..f0497b8623ad 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy @@ -45,11 +46,11 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy reg: minItems: 1 - maxItems: 2 items: - description: Address and length of PHY's common serdes block. - description: Address and length of PHY's DP_COM control block. @@ -296,6 +297,30 @@ allOf: items: - const: phy - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + clock-names: + items: + - const: aux + - const: cfg_ahb + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common - if: properties: compatible: @@ -303,6 +328,7 @@ allOf: enum: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 9f9cf07b7d45..ec9ccaaba098 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -23,6 +23,8 @@ properties: - qcom,msm8998-qusb2-phy - qcom,sdm660-qusb2-phy - qcom,ipq6018-qusb2-phy + - qcom,sm4250-qusb2-phy + - qcom,sm6115-qusb2-phy - items: - enum: - qcom,sc7180-qusb2-phy @@ -36,7 +38,6 @@ properties: clocks: minItems: 2 - maxItems: 3 items: - description: phy config clock - description: 19.2 MHz ref clk @@ -44,7 +45,6 @@ properties: clock-names: minItems: 2 - maxItems: 3 items: - const: cfg_ahb - const: ref diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt deleted file mode 100644 index 63853b35e083..000000000000 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas R-Car generation 3 PCIe PHY - -This file provides information on what the device node for the R-Car -generation 3 PCIe PHY contains. - -Required properties: -- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the - R8A77980 SoC. -- reg: offset and length of the register block. -- clocks: clock phandle and specifier pair. -- power-domains: power domain phandle and specifier pair. -- resets: reset phandle and specifier pair. -- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. - -Example (R-Car V3H): - - pcie-phy@e65d0000 { - compatible = "renesas,r8a77980-pcie-phy"; - reg = <0 0xe65d0000 0 0x8000>; - #phy-cells = <0>; - clocks = <&cpg CPG_MOD 319>; - power-domains = <&sysc 32>; - resets = <&cpg 319>; - }; diff --git a/Documentation/devicetree/bindings/phy/renesas,rcar-gen3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,rcar-gen3-pcie-phy.yaml new file mode 100644 index 000000000000..247ef7c47cf5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/renesas,rcar-gen3-pcie-phy.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Generation 3 PCIe PHY + +maintainers: + - Sergei Shtylyov + +properties: + compatible: + const: renesas,r8a77980-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + pcie-phy@e65d0000 { + compatible = "renesas,r8a77980-pcie-phy"; + reg = <0xe65d0000 0x8000>; + #phy-cells = <0>; + clocks = <&cpg CPG_MOD 319>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 319>; + }; diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 0f358d5b84ef..d5dc5a3cdceb 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -39,7 +39,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: fck - const: usb_x1 @@ -61,7 +60,6 @@ properties: resets: minItems: 1 - maxItems: 2 items: - description: reset of USB 2.0 host side - description: reset of USB 2.0 peripheral side diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml index f3ef738a3ff6..b8483f9edbfc 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml @@ -33,7 +33,6 @@ properties: # If you want to use the ssc, the clock-frequency of usb_extal # must not be 0. minItems: 2 - maxItems: 3 items: - const: usb3-if # The funcional clock - const: usb3s_clk # The usb3's external clock diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml new file mode 100644 index 000000000000..bb4a2e4b8ab0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings + +maintainers: + - Heiko Stuebner + +description: | + The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich + connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. + +properties: + compatible: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + + '#phy-cells': + const: 0 + + power-domains: + description: Video in/out power domain. + maxItems: 1 + + resets: + items: + - description: exclusive PHY reset line + + reset-names: + items: + - const: apb + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are access through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#phy-cells' + - power-domains + - resets + - reset-names + - rockchip,grf + +additionalProperties: false + +examples: + - | + + csi_dphy: phy@ff2f0000 { + compatible = "rockchip,px30-csi-dphy"; + reg = <0xff2f0000 0x4000>; + clocks = <&cru 1>; + clock-names = "pclk"; + #phy-cells = <0>; + power-domains = <&power 1>; + resets = <&cru 1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + }; diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt deleted file mode 100644 index 4ed569046daf..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt +++ /dev/null @@ -1,52 +0,0 @@ -ROCKCHIP USB2 PHY - -Required properties: - - compatible: matching the soc type, one of - "rockchip,rk3066a-usb-phy" - "rockchip,rk3188-usb-phy" - "rockchip,rk3288-usb-phy" - - #address-cells: should be 1 - - #size-cells: should be 0 - -Deprecated properties: - - rockchip,grf : phandle to the syscon managing the "general - register files" - phy should be a child of the GRF instead - -Sub-nodes: -Each PHY should be represented as a sub-node. - -Sub-nodes -required properties: -- #phy-cells: should be 0 -- reg: PHY configure reg address offset in GRF - "0x320" - for PHY attach to OTG controller - "0x334" - for PHY attach to HOST0 controller - "0x348" - for PHY attach to HOST1 controller - -Optional Properties: -- clocks : phandle + clock specifier for the phy clocks -- clock-names: string, clock name, must be "phyclk" -- #clock-cells: for users of the phy-pll, should be 0 -- reset-names: Only allow the following entries: - - phy-reset -- resets: Must contain an entry for each entry in reset-names. -- vbus-supply: power-supply phandle for vbus power source - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - -... - - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - reg = <0x320>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.yaml new file mode 100644 index 000000000000..f0fc8275dcd0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB2.0 phy + +maintainers: + - Heiko Stuebner + +properties: + compatible: + oneOf: + - const: rockchip,rk3288-usb-phy + - items: + - enum: + - rockchip,rk3066a-usb-phy + - rockchip,rk3188-usb-phy + - const: rockchip,rk3288-usb-phy + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +patternProperties: + "usb-phy@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-names: + const: phyclk + + "#clock-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy-reset + + vbus-supply: + description: phandle for vbus power source + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +examples: + - | + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@320 { + reg = <0x320>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml new file mode 100644 index 000000000000..6107880e5246 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TCAN104x CAN TRANSCEIVER PHY + +maintainers: + - Aswath Govindraju + +properties: + $nodename: + pattern: "^can-phy" + + compatible: + enum: + - ti,tcan1042 + - ti,tcan1043 + + '#phy-cells': + const: 0 + + standby-gpios: + description: + gpio node to toggle standby signal on transceiver + maxItems: 1 + + enable-gpios: + description: + gpio node to toggle enable signal on transceiver + maxItems: 1 + + max-bitrate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max bit rate supported in bps + minimum: 1 + +required: + - compatible + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + + transceiver1: can-phy { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&wakeup_gpio1 16 GPIO_ACTIVE_LOW>; + enable-gpios = <&main_gpio1 67 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml index ccdd9e3820d7..3f94f6944740 100644 --- a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml @@ -26,7 +26,6 @@ properties: - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control - description: PAD Drive Capacity Select minItems: 1 - maxItems: 4 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml new file mode 100644 index 000000000000..d50571affd1f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple GPIO controller + +maintainers: + - Mark Kettenis + +description: | + The Apple GPIO controller is a simple combined pin and GPIO + controller present on Apple ARM SoC platforms, including various + iPhone and iPad devices and the "Apple Silicon" Macs. + +properties: + compatible: + items: + - const: apple,t8103-pinctrl + - const: apple,pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupts: + description: One interrupt for each of the (up to 7) interrupt + groups supported by the controller sorted by interrupt group + number in ascending order. + minItems: 1 + maxItems: 7 + + interrupt-controller: true + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and alternate function + configuration number using the APPLE_PINMUX() helper macro + defined in include/dt-bindings/pinctrl/apple.h. + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@23c100000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 212>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + pcie_pins: pcie-pins { + pinmux = , + , + ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index ad91c0bc54da..ad2866c99738 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -46,8 +46,8 @@ patternProperties: PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, - SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, - SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, + SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, @@ -74,9 +74,9 @@ patternProperties: RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, - SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL, - SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, - SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, + SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2, + SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, + SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt deleted file mode 100644 index 8ab2d468dbdb..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom Northstar pins mux controller - -Some of Northstar SoCs's pins can be used for various purposes thanks to the mux -controller. This binding allows describing mux controller and listing available -functions. They can be referenced later by other bindings to let system -configure controller correctly. - -A list of pins varies across chipsets so few bindings are available. - -Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" -noce. - -Required properties: -- compatible: must be one of: - "brcm,bcm4708-pinmux" - "brcm,bcm4709-pinmux" - "brcm,bcm53012-pinmux" -- offset: offset of pin registers in the CRU block - -Functions and their groups available for all chipsets: -- "spi": "spi_grp" -- "i2c": "i2c_grp" -- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" -- "uart1": "uart1_grp" - -Additionally available on BCM4709 and BCM53012: -- "mdio": "mdio_grp" -- "uart2": "uart2_grp" -- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp" - -For documentation of subnodes see: -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - dmu@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - cru@100 { - compatible = "syscon", "simple-mfd"; - reg = <0x100 0x1a4>; - - pinctrl { - compatible = "brcm,bcm4708-pinmux"; - offset = <0xc0>; - - spi-pins { - function = "spi"; - groups = "spi_grp"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml new file mode 100644 index 000000000000..470aff599c27 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar pins mux controller + +maintainers: + - Rafał Miłecki + +description: + Some of Northstar SoCs's pins can be used for various purposes thanks to the + mux controller. This binding allows describing mux controller and listing + available functions. They can be referenced later by other bindings to let + system configure controller correctly. + + A list of pins varies across chipsets so few bindings are available. + + Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" + node. + +properties: + compatible: + enum: + - brcm,bcm4708-pinmux + - brcm,bcm4709-pinmux + - brcm,bcm53012-pinmux + + offset: + description: offset of pin registers in the CRU block + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + +patternProperties: + '-pins$': + type: object + description: pin node + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ] + groups: + minItems: 1 + maxItems: 4 + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ] + + required: + - function + - groups + + additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm4708-pinmux + then: + patternProperties: + '-pins$': + properties: + function: + enum: [ spi, i2c, pwm, uart1 ] + groups: + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp ] + +required: + - offset + +additionalProperties: false + +examples: + - | + cru@1800c100 { + compatible = "syscon", "simple-mfd"; + reg = <0x1800c100 0x1a4>; + + pinctrl { + compatible = "brcm,bcm4708-pinmux"; + offset = <0xc0>; + + spi-pins { + function = "spi"; + groups = "spi_grp"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index 6ec3c8d79f49..2fa5edac7a35 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -49,6 +49,7 @@ Optional properties: - interrupt-controller: Marks the device node as a interrupt controller. - drive-open-drain: Sets the ODR flag in the IOCON register. This configures the IRQ output as open drain active low. +- reset-gpios: Corresponds to the active-low RESET# pin for the chip Optional device specific properties: - microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices @@ -135,6 +136,7 @@ gpio21: gpio@21 { microchip,irq-mirror; pinctrl-names = "default"; pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; gpio21pullups: pinmux { pins = "gpio0", "gpio1", "gpio2", "gpio3", diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 360e59c9301a..5fe2c26c28bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. + "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl. "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index f6a9760558a6..161216daf463 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -31,6 +31,7 @@ PMIC's from Qualcomm. "qcom,pm8350b-gpio" "qcom,pm8350c-gpio" "qcom,pmk8350-gpio" + "qcom,pm7325-gpio" "qcom,pmr735a-gpio" "qcom,pmr735b-gpio" "qcom,pm6150-gpio" @@ -120,6 +121,7 @@ to specify in a pin configuration subnode: gpio1-gpio8 for pm8350b gpio1-gpio9 for pm8350c gpio1-gpio4 for pmk8350 + gpio1-gpio10 for pm7325 gpio1-gpio4 for pmr735a gpio1-gpio4 for pmr735b gpio1-gpio10 for pm6150 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index 0ba07bc96c55..5363d44cbb74 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -21,6 +21,7 @@ of PMIC's from Qualcomm. "qcom,pmi8950-mpp", "qcom,pm8994-mpp", "qcom,pma8084-mpp", + "qcom,pmi8994-mpp", And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" if the device is on an spmi bus or an ssbi bus respectively. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml new file mode 100644 index 000000000000..5f7adaa81f83 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Qualcomm Technologies, Inc. SM6125 TLMM block + +maintainers: + - Martin Botka + +description: | + This binding describes the Top Level Mode Multiplexer (TLMM) block found + in the SM6125 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6125-tlmm + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "south" + - const: "east" + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sm6125-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sm6125-tlmm-state" + +$defs: + qcom-sm6125-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, + atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, + atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, + audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, + dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, + nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, + qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, + qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, + swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, + wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@500000 { + compatible = "qcom,sm6125-tlmm"; + reg = <0x00500000 0x400000>, + <0x00900000 0x400000>, + <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml index d30f85cc395e..f005abac7079 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml @@ -37,7 +37,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: vpu - const: vapb diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt deleted file mode 100644 index 49aba15dff8b..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt +++ /dev/null @@ -1,100 +0,0 @@ -DT bindings for the Renesas R-Mobile System Controller - -== System Controller Node == - -The R-Mobile System Controller provides the following functions: - - Boot mode management, - - Reset generation, - - Power management. - -Required properties: -- compatible: Should be "renesas,sysc-", "renesas,sysc-rmobile" as - fallback. - Examples with soctypes are: - - "renesas,sysc-r8a73a4" (R-Mobile APE6) - - "renesas,sysc-r8a7740" (R-Mobile A1) - - "renesas,sysc-sh73a0" (SH-Mobile AG5) -- reg: Two address start and address range blocks for the device: - - The first block refers to the normally accessible registers, - - the second block refers to the registers protected by the HPB - semaphore. - -Optional nodes: -- pm-domains: This node contains a hierarchy of PM domain nodes, which should - match the Power Area Hierarchy in the Power Domain Specifications section of - the device's datasheet. - - -== PM Domain Nodes == - -Each of the PM domain nodes represents a PM domain, as documented by the -generic PM domain bindings in -Documentation/devicetree/bindings/power/power-domain.yaml. - -The nodes should be named by the real power area names, and thus their names -should be unique. - -Required properties: - - #power-domain-cells: Must be 0. - -Optional properties: -- reg: If the PM domain is not always-on, this property must contain the bit - index number for the corresponding power area in the various Power - Control and Status Registers. The parent's node must contain the - following two properties: - - #address-cells: Must be 1, - - #size-cells: Must be 0. - If the PM domain is always-on, this property must be omitted. - - -Example: - -This shows a subset of the r8a7740 PM domain hierarchy, containing the -C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain, -which is a subdomain of A4S. - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a4s: a4s@10 { - reg = <10>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - }; - - pd_a4su: a4su@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; - - -== PM Domain Consumers == - -Hardware blocks belonging to a PM domain should contain a "power-domains" -property that is a phandle pointing to the corresponding PM domain node. - -Example: - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; - clocks = <&mstp3_clks R8A7740_CLK_TPU0>; - power-domains = <&pd_a3sp>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml new file mode 100644 index 000000000000..559718997de7 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/renesas,sysc-rmobile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Mobile System Controller + +maintainers: + - Geert Uytterhoeven + - Magnus Damm + +description: | + The R-Mobile System Controller provides the following functions: + - Boot mode management, + - Reset generation, + - Power management. + +properties: + compatible: + items: + - enum: + - renesas,sysc-r8a73a4 # R-Mobile APE6 + - renesas,sysc-r8a7740 # R-Mobile A1 + - renesas,sysc-sh73a0 # SH-Mobile AG5 + - const: renesas,sysc-rmobile # Generic SH/R-Mobile + + reg: + items: + - description: Normally accessible register block + - description: Register block protected by the HPB semaphore + + pm-domains: + type: object + description: | + This node contains a hierarchy of PM domain nodes, which should match the + Power Area Hierarchy in the Power Domain Specifications section of the + device's datasheet. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + additionalProperties: + $ref: "#/$defs/pd-node" + +required: + - compatible + - reg + - pm-domains + +additionalProperties: false + +$defs: + pd-node: + type: object + description: + PM domain node representing a PM domain. This node hould be named by + the real power area name, and thus its name should be unique. + + properties: + reg: + maxItems: 1 + description: + If the PM domain is not always-on, this property must contain the + bit index number for the corresponding power area in the various + Power Control and Status Registers. + If the PM domain is always-on, this property must be omitted. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#power-domain-cells': + const: 0 + + required: + - '#power-domain-cells' + + additionalProperties: + $ref: "#/$defs/pd-node" + +examples: + - | + // This shows a subset of the r8a7740 PM domain hierarchy, containing the + // C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP + // domain, which is a subdomain of A4S. + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a4s: a4s@10 { + reg = <10>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + }; + + pd_a4su: a4su@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/property-units.txt b/Documentation/devicetree/bindings/property-units.txt deleted file mode 100644 index 218f99fa311f..000000000000 --- a/Documentation/devicetree/bindings/property-units.txt +++ /dev/null @@ -1,48 +0,0 @@ -Standard Unit Suffixes for Property names - -Properties which have a unit of measure are recommended to have a unit -suffix appended to the property name. The list below contains the -recommended suffixes. Other variations exist in bindings, but should not -be used in new bindings or added here. The inconsistency in the unit -prefixes is due to selecting the most commonly used variants. - -It is also recommended to use the units listed here and not add additional -unit prefixes. - -Time/Frequency ----------------------------------------- --mhz : megahertz --hz : hertz (preferred) --sec : second --ms : millisecond --us : microsecond --ns : nanosecond --ps : picosecond - -Distance ----------------------------------------- --mm : millimeter - -Electricity ----------------------------------------- --microamp : microampere --microamp-hours : microampere hour --ohms : ohm --micro-ohms : microohm --microwatt-hours: microwatt hour --microvolt : microvolt --picofarads : picofarad --femtofarads : femtofarad - -Temperature ----------------------------------------- --celsius : degree Celsius --millicelsius : millidegree Celsius - -Pressure ----------------------------------------- --kpascal : kilopascal - -Throughput ----------------------------------------- --kBps : kilobytes per second diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 7dcab2bf8128..54a7700df08f 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -37,7 +37,6 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: Module Clock - description: Bus Clock diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt deleted file mode 100644 index 655f6cd4ef46..000000000000 --- a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt +++ /dev/null @@ -1,21 +0,0 @@ -Broadcom iProc PWM controller device tree bindings - -This controller has 4 channels. - -Required Properties : -- compatible: must be "brcm,iproc-pwm" -- reg: physical base address and length of the controller's registers -- clocks: phandle + clock specifier pair for the external clock -- #pwm-cells: Should be 3. See pwm.yaml in this directory for a - description of the cells format. - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - -pwm: pwm@18031000 { - compatible = "brcm,iproc-pwm"; - reg = <0x18031000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; -}; diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml new file mode 100644 index 000000000000..218ab06c34d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PWM controller + +maintainers: + - Rafał Miłecki + +description: + This controller has 4 channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: brcm,iproc-pwm + + reg: + maxItems: 1 + + clocks: + description: external clock + maxItems: 1 + + "#pwm-cells": + const: 3 + +unevaluatedProperties: false + +required: + - reg + - clocks + +examples: + - | + pwm@18031000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18031000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml index 7d1f687cee9c..2effe6c0de6b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm.yaml @@ -24,8 +24,9 @@ additionalProperties: true examples: - | - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; + pwm: pwm@1c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml index 3c2fa2e93d1b..7ea1070b4b3a 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml @@ -61,6 +61,19 @@ required: - reg - '#pwm-cells' - clocks + - power-domains + +if: + not: + properties: + compatible: + contains: + enum: + - renesas,pwm-r8a7778 + - renesas,pwm-r8a7779 +then: + required: + - resets additionalProperties: false diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml index aa9a4570c906..81ccb2110162 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml @@ -9,6 +9,15 @@ title: Renesas R-Car Timer Pulse Unit PWM Controller maintainers: - Laurent Pinchart +select: + properties: + compatible: + contains: + const: renesas,tpu + required: + - compatible + - '#pwm-cells' + properties: compatible: items: @@ -58,6 +67,23 @@ required: - compatible - reg - '#pwm-cells' + - clocks + - power-domains + +allOf: + - $ref: pwm.yaml# + + - if: + not: + properties: + compatible: + contains: + enum: + - renesas,tpu-r8a73a4 + - renesas,tpu-r8a7740 + then: + required: + - resets additionalProperties: false diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 64afdcfb613d..1e6225677e00 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -72,7 +72,6 @@ properties: - from local to remote, where ACK from the remote means that communnication as been stopped on the remote side. minItems: 1 - maxItems: 4 mbox-names: items: @@ -81,7 +80,6 @@ properties: - const: shutdown - const: detach minItems: 1 - maxItems: 4 memory-region: description: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt index 461dc1d8d570..463a97c11eff 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt +++ b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt @@ -48,7 +48,7 @@ The following are the mandatory properties: bindings for the reset argument specifier as per SoC, Documentation/devicetree/bindings/reset/ti-syscon-reset.txt for 66AK2HK/66AK2L/66AK2E SoCs or, - Documentation/devicetree/bindings/reset/ti,sci-reset.txt + Documentation/devicetree/bindings/reset/ti,sci-reset.yaml for 66AK2G SoCs - interrupts: Should contain an entry for each value in 'interrupt-names'. @@ -82,7 +82,7 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only: - power-domains: Should contain a phandle to a PM domain provider node and an args specifier containing the DSP device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml Optional properties: -------------------- diff --git a/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml index 73400bc6e91d..c6c12129d6b7 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml @@ -65,7 +65,7 @@ properties: OMAP Mailbox specifier denoting the sub-mailbox, to be used for communication with the remote processor. The specifier format is as per the bindings, - Documentation/devicetree/bindings/mailbox/omap-mailbox.txt + Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml This property should match with the sub-mailbox node used in the firmware image. @@ -116,7 +116,6 @@ properties: list, in the specified order, each representing the corresponding internal RAM memory region. minItems: 1 - maxItems: 3 items: - const: l2ram - const: l1pram diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml index 27c5e34a3ac6..b11ac533f914 100644 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml @@ -59,7 +59,6 @@ properties: - description: SRC interrupt - description: CPU WDOG interrupts out of SRC minItems: 1 - maxItems: 2 '#reset-cells': const: 1 diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt deleted file mode 100644 index 8b1cf022f18a..000000000000 --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt +++ /dev/null @@ -1,62 +0,0 @@ -Texas Instruments System Control Interface (TI-SCI) Reset Controller -===================================================================== - -Some TI SoCs contain a system controller (like the Power Management Micro -Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling -the state of the various hardware modules present on the SoC. Communication -between the host processor running an OS and the system controller happens -through a protocol called TI System Control Interface (TI-SCI protocol). -For TI SCI details, please refer to the document, -Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -TI-SCI Reset Controller Node -============================ -This reset controller node uses the TI SCI protocol to perform the reset -management of various hardware modules present on the SoC. Must be a child -node of the associated TI-SCI system controller node. - -Required properties: --------------------- - - compatible : Should be "ti,sci-reset" - - #reset-cells : Should be 2. Please see the reset consumer node below for - usage details. - -TI-SCI Reset Consumer Nodes -=========================== -Each of the reset consumer nodes should have the following properties, -in addition to their own properties. - -Required properties: --------------------- - - resets : A phandle and reset specifier pair, one pair for each reset - signal that affects the device, or that the device manages. - The phandle should point to the TI-SCI reset controller node, - and the reset specifier should have 2 cell-values. The first - cell should contain the device ID. The second cell should - contain the reset mask value used by system controller. - Please refer to the protocol documentation for these values - to be used for different devices, - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Please also refer to Documentation/devicetree/bindings/reset/reset.txt for -common reset controller usage by consumers. - -Example: --------- -The following example demonstrates both a TI-SCI reset controller node and a -consumer (a DSP device) on the 66AK2G SoC. - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; -}; - -dsp0: dsp@10800000 { - ... - resets = <&k2g_reset 0x0046 0x1>; - ... -}; diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml new file mode 100644 index 000000000000..4639d2cec557 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI reset controller node bindings + +maintainers: + - Nishanth Menon + +description: | + Some TI SoCs contain a system controller (like the Power Management Micro + Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling + the state of the various hardware modules present on the SoC. Communication + between the host processor running an OS and the system controller happens + through a protocol called TI System Control Interface (TI-SCI protocol). + + This reset controller node uses the TI SCI protocol to perform the reset + management of various hardware modules present on the SoC. Must be a child + node of the associated TI-SCI system controller node. + +properties: + $nodename: + pattern: "^reset-controller$" + + compatible: + const: ti,sci-reset + + "#reset-cells": + const: 2 + description: + The two cells represent values that the TI-SCI controller defines. + + The first cell should contain the device ID. + + The second cell should contain the reset mask corresponding to the device + used by system controller. + + Please see http://processors.wiki.ti.com/index.php/TISCI for + protocol documentation for the values to be used for different devices. + + +additionalProperties: false + +examples: + - | + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index 23b227614366..1d38ff76d18f 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -56,7 +56,6 @@ properties: interrupts: minItems: 3 - maxItems: 4 items: - description: DirError interrupt - description: DataError interrupt diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.txt b/Documentation/devicetree/bindings/rng/mtk-rng.txt deleted file mode 100644 index dfdcb5cd2ea8..000000000000 --- a/Documentation/devicetree/bindings/rng/mtk-rng.txt +++ /dev/null @@ -1,22 +0,0 @@ -Device-Tree bindings for Mediatek random number generator -found in MediaTek SoC family - -Required properties: -- compatible : Should be - "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622 - "mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629 - "mediatek,mt7623-rng" : for MT7623 - "mediatek,mt8516-rng", "mediatek,mt7623-rng" : for MT8516 -- clocks : list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : Should contain "rng" entries; -- reg : Specifies base physical address and size of the registers - -Example: - -rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; -}; diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml new file mode 100644 index 000000000000..61888e07bda0 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Random number generator + +maintainers: + - Sean Wang + +properties: + $nodename: + pattern: "^rng@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - mediatek,mt7623-rng + - items: + - enum: + - mediatek,mt7622-rng + - mediatek,mt7629-rng + - mediatek,mt8365-rng + - mediatek,mt8516-rng + - const: mediatek,mt7623-rng + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rng + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + rng: rng@1020f000 { + compatible = "mediatek,mt7623-rng"; + reg = <0x1020f000 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index b1b0ee769b71..beeb90e55727 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -32,7 +32,6 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: RTC Alarm 0 - description: RTC Alarm 1 diff --git a/Documentation/devicetree/bindings/rtc/arm,pl031.yaml b/Documentation/devicetree/bindings/rtc/arm,pl031.yaml new file mode 100644 index 000000000000..fa5f2eda372e --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/arm,pl031.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/arm,pl031.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Primecell PL031 Real Time Clock + +select: + properties: + compatible: + contains: + const: arm,pl031 + required: + - compatible + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Rob Herring + +properties: + compatible: + items: + - const: arm,pl031 + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + start-year: true + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml index 06bd737821c1..4807c95a663c 100644 --- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml @@ -21,7 +21,6 @@ properties: - description: rtc alarm interrupt - description: dryice security violation interrupt minItems: 1 - maxItems: 2 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml new file mode 100644 index 000000000000..a98b72752349 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf8563.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Philips PCF8563/Epson RTC8564 Real Time Clock + +maintainers: + - Alexandre Belloni + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - epson,rtc8564 + - microcrystal,rv8564 + - nxp,pca8565 + - nxp,pcf8563 + - nxp,pcf85263 + - nxp,pcf85363 + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + interrupts: + maxItems: 1 + + start-year: true + wakeup-source: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt deleted file mode 100644 index 94adc1cf93d9..000000000000 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ /dev/null @@ -1,17 +0,0 @@ -NXP PCF85263/PCF85363 Real Time Clock -============================ - -Required properties: -- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". -- reg: I2C address for chip. - -Optional properties: -- interrupts: IRQ line for the RTC (not implemented). - -Example: - -pcf85363: pcf85363@51 { - compatible = "nxp,pcf85363"; - reg = <0x51>; -}; - diff --git a/Documentation/devicetree/bindings/rtc/pcf8563.txt b/Documentation/devicetree/bindings/rtc/pcf8563.txt deleted file mode 100644 index 0a900f7c8977..000000000000 --- a/Documentation/devicetree/bindings/rtc/pcf8563.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Philips PCF8563/Epson RTC8564 Real Time Clock - -Philips PCF8563/Epson RTC8564 Real Time Clock - -Required properties: -- compatible: Should contain "nxp,pcf8563", - "epson,rtc8564" or - "microcrystal,rv8564" or - "nxp,pca8565" -- reg: I2C address for chip. - -Optional property: -- #clock-cells: Should be 0. -- clock-output-names: - overwrite the default clock name "pcf8563-clkout" - -Example: - -pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - #clock-cells = <0>; -}; - -device { -... - clocks = <&pcf8563>; -... -}; diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml new file mode 100644 index 000000000000..bdb72d3ddf2a --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock + +description: + RTC controller for the Xilinx Zynq MPSoC Real Time Clock. + The RTC controller has separate IRQ lines for seconds and alarm. + +maintainers: + - Michal Simek + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: xlnx,zynqmp-rtc + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + + interrupt-names: + items: + - const: alarm + - const: sec + + calibration: + description: | + calibration value for 1 sec period which will + be programmed directly to calibration register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0x1FFFFF + default: 0x198233 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + rtc: rtc@ffa60000 { + compatible = "xlnx,zynqmp-rtc"; + reg = <0x0 0xffa60000 0x0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 26 4>, <0 27 4>; + interrupt-names = "alarm", "sec"; + calibration = <0x198233>; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt deleted file mode 100644 index 0df6f016b1b7..000000000000 --- a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock - -RTC controller for the Xilinx Zynq MPSoC Real Time Clock -Separate IRQ lines for seconds and alarm - -Required properties: -- compatible: Should be "xlnx,zynqmp-rtc" -- reg: Physical base address of the controller and length - of memory mapped region. -- interrupts: IRQ lines for the RTC. -- interrupt-names: interrupt line names eg. "sec" "alarm" - -Optional: -- calibration: calibration value for 1 sec period which will - be programmed directly to calibration register - -Example: -rtc: rtc@ffa60000 { - compatible = "xlnx,zynqmp-rtc"; - reg = <0x0 0xffa60000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; - interrupt-names = "alarm", "sec"; - calibration = <0x198233>; -}; diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 41f57c448621..a0bf061b80fe 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -10,7 +10,7 @@ maintainers: - devicetree@vger.kernel.org allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# - if: anyOf: - required: diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml new file mode 100644 index 000000000000..1c826fcf5828 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/8250_omap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs + +maintainers: + - Vignesh Raghavendra + +allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +properties: + compatible: + oneOf: + - enum: + - ti,am3352-uart + - ti,am4372-uart + - ti,am654-uart + - ti,dra742-uart + - ti,omap2-uart + - ti,omap3-uart + - ti,omap4-uart + - items: + - enum: + - ti,am64-uart + - ti,j721e-uart + - const: ti,am654-uart + + ti,hwmods: + description: + Must be "uart", n being the instance number (1-based) + This property is applicable only on legacy platforms mainly omap2/3 + and ti81xx and should not be used on other platforms. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + description: + First entry is module IRQ required for normal IO operation. + Second entry is optional and corresponds to system wakeup IRQ + where supported. + + clocks: + maxItems: 1 + + clock-names: + const: fclk + + rts-gpios: true + cts-gpios: true + dtr-gpios: true + dsr-gpios: true + rng-gpios: true + dcd-gpios: true + rs485-rts-delay: true + rs485-rts-active-low: true + rs485-rx-during-tx: true + rs485-rts-active-high: true + linux,rs485-enabled-at-boot-time: true + rts-gpio: true + power-domains: true + clock-frequency: true + current-speed: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +if: + properties: + compatible: + oneOf: + - const: ti,omap2-uart + - const: ti,omap3-uart + - const: ti,omap4-uart + +then: + properties: + ti,hwmods: + items: + - pattern: "^uart([1-9])$" + +else: + properties: + ti,hwmods: false + +examples: + - | + serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 75ebc9952a99..7487aa6ef849 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -55,6 +55,11 @@ properties: - const: pclk - const: baud + fifo-size: + description: The fifo size supported by the UART channel. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [64, 128] + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml index 46c62745f901..6d176588df47 100644 --- a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml +++ b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml @@ -10,7 +10,7 @@ maintainers: - Al Cooper allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# description: |+ The Broadcom UART is based on the basic 8250 UART but with diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml index 2b06c6ce4a75..9d949296a142 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -71,6 +71,18 @@ properties: received, and that the peripheral should invert its input using the INVR registers. + fsl,dma-info: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: | + First cell contains the size of DMA buffer chunks, second cell contains + the amount of chunks used for the device. Multiplying both numbers is + the total size of memory used for receiving data. + When not being configured the system will use default settings, which + are sensible for most use cases. If you need low latency processing on + slow connections this needs to be configured appropriately. + uart-has-rtscts: true rs485-rts-delay: true diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index bd21060d26e0..a90c971b4f1f 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -36,14 +36,12 @@ properties: - description: ipg clock - description: baud clock minItems: 1 - maxItems: 2 clock-names: items: - const: ipg - const: baud minItems: 1 - maxItems: 2 dmas: items: diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml index 7748d8c3bab8..b432d4dff730 100644 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml @@ -10,7 +10,7 @@ maintainers: - Paul Cercueil allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# properties: $nodename: diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index b7e0e32b9ac6..2d0dbdf32d1d 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -5,10 +5,10 @@ Required properties: - compatible: - "marvell,armada-3700-uart" for the standard variant of the UART (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the - FIFO, baudrate limited to 230400). + FIFO), called also UART1. - "marvell,armada-3700-uart-ext" for the extended variant of the UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit - accesses to the FIFO, baudrate unlimited by the dividers). + accesses to the FIFO), called also UART2. - reg: offset and length of the register set for the device. - clocks: UART reference clock used to derive the baudrate. If no clock is provided (possible only with the "marvell,armada-3700-uart" @@ -33,7 +33,7 @@ Required properties: Example: uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; + reg = <0x12000 0x18>; clocks = <&xtalclk>; interrupts = , diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt deleted file mode 100644 index c2db8cabf2ab..000000000000 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ /dev/null @@ -1,40 +0,0 @@ -OMAP UART controller - -Required properties: -- compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers -- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers -- compatible : should be "ti,am654-uart" for AM654 controllers -- compatible : should be "ti,omap2-uart" for OMAP2 controllers -- compatible : should be "ti,omap3-uart" for OMAP3 controllers -- compatible : should be "ti,omap4-uart" for OMAP4 controllers -- compatible : should be "ti,am4372-uart" for AM437x controllers -- compatible : should be "ti,am3352-uart" for AM335x controllers -- compatible : should be "ti,dra742-uart" for DRA7x controllers -- reg : address and length of the register space -- interrupts or interrupts-extended : Should contain the uart interrupt - specifier or both the interrupt - controller phandle and interrupt - specifier. -- ti,hwmods : Must be "uart", n being the instance number (1-based) - -Optional properties: -- clock-frequency : frequency of the clock input to the UART -- dmas : DMA specifier, consisting of a phandle to the DMA controller - node and a DMA channel number. -- dma-names : "rx" for receive channel, "tx" for transmit channel. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt -- rs485-rts-active-high: drive RTS high when sending (default is low). -- clocks: phandle to the functional clock as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Example: - - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 1f8e9f2644b6..5ea00f8a283d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -10,7 +10,7 @@ maintainers: - Rob Herring allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# # Need a custom select here or 'arm,primecell' will match on lots of nodes select: @@ -24,12 +24,9 @@ select: properties: compatible: - oneOf: - - items: - - const: arm,pl011 - - const: arm,primecell - - items: - - const: arm,primecell + items: + - const: arm,pl011 + - const: arm,primecell reg: maxItems: 1 @@ -103,7 +100,7 @@ dependencies: poll-rate-ms: [ auto-poll ] poll-timeout-ms: [ auto-poll ] -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml b/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml index a344369285b6..a644e5af12b2 100644 --- a/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml +++ b/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml @@ -10,7 +10,7 @@ maintainers: - Oleksij Rempel allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# properties: compatible: @@ -35,7 +35,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index 82aefdb0d45e..e98ec48fee46 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -35,7 +35,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 22d76829f7ae..6b8731f7f2fb 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -64,6 +64,10 @@ properties: - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 - const: renesas,scif # generic SCIF compatible UART + - items: + - enum: + - renesas,scif-r9a07g044 # RZ/G2{L,LC} + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 97ec8a093bf3..f064e5b76cf1 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -44,7 +44,6 @@ properties: clock-names: description: N = 0 is allowed for SoCs without internal baud clock mux. minItems: 2 - maxItems: 5 items: - const: uart - pattern: '^clk_uart_baud[0-3]$' @@ -82,7 +81,7 @@ required: unevaluatedProperties: false allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# - if: properties: diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml index 2fdf4ed198da..c75ba3fb6465 100644 --- a/Documentation/devicetree/bindings/serial/serial.yaml +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -23,6 +23,8 @@ properties: $nodename: pattern: "^serial(@.*)?$" + label: true + cts-gpios: maxItems: 1 description: diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 5fa94dacbba9..09aae43f65a7 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -12,7 +12,7 @@ maintainers: - Palmer Dabbelt allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# properties: compatible: @@ -49,7 +49,7 @@ required: - interrupts - clocks -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 87ef1e218152..b49fda5e608f 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -10,7 +10,7 @@ maintainers: - Rob Herring allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# properties: compatible: @@ -23,6 +23,7 @@ properties: - items: - enum: - rockchip,px30-uart + - rockchip,rk1808-uart - rockchip,rk3036-uart - rockchip,rk3066-uart - rockchip,rk3188-uart @@ -31,6 +32,7 @@ properties: - rockchip,rk3328-uart - rockchip,rk3368-uart - rockchip,rk3399-uart + - rockchip,rk3568-uart - rockchip,rv1108-uart - const: snps,dw-apb-uart - items: diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 71a6426bc558..f50f4ca893a0 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -112,8 +112,7 @@ required: - interrupts - clocks -additionalProperties: - type: object +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 84671950ca0d..4663c2bcad50 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -164,7 +164,6 @@ patternProperties: interrupts: minItems: 1 - maxItems: 2 items: - description: UART core irq - description: Wakeup irq (RX GPIO) diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt deleted file mode 100644 index 6217e64309de..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +++ /dev/null @@ -1,65 +0,0 @@ -Texas Instruments TI-SCI Generic Power Domain ---------------------------------------------- - -Some TI SoCs contain a system controller (like the PMMC, etc...) that is -responsible for controlling the state of the IPs that are present. -Communication between the host processor running an OS and the system -controller happens through a protocol known as TI-SCI [1]. - -[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -PM Domain Node -============== -The PM domain node represents the global PM domain managed by the PMMC, which -in this case is the implementation as documented by the generic PM domain -bindings in Documentation/devicetree/bindings/power/power-domain.yaml. Because -this relies on the TI SCI protocol to communicate with the PMMC it must be a -child of the pmmc node. - -Required Properties: --------------------- -- compatible: should be "ti,sci-pm-domain" -- #power-domain-cells: Can be one of the following: - 1: Containing the device id of each node - 2: First entry should be device id - Second entry should be one of the floowing: - TI_SCI_PD_EXCLUSIVE: To allow device to be - exclusively controlled by - the requesting hosts. - TI_SCI_PD_SHARED: To allow device to be shared - by multiple hosts. - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - ... - - k2g_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <1>; - }; - }; - -PM Domain Consumers -=================== -Hardware blocks belonging to a PM domain should contain a "power-domains" -property that is a phandle pointing to the corresponding PM domain node -along with an index representing the device id to be passed to the PMMC -for device control. - -Required Properties: --------------------- -- power-domains: phandle pointing to the corresponding PM domain node - and an ID representing the device. - -See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list -of valid identifiers for k2g. - -Example (K2G): --------------------- - uart0: serial@2530c00 { - compatible = "ns16550a"; - ... - power-domains = <&k2g_pds 0x002c>; - }; diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml new file mode 100644 index 000000000000..9e6cb4ee9755 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI generic power domain node bindings + +maintainers: + - Nishanth Menon + +allOf: + - $ref: /schemas/power/power-domain.yaml# + +description: | + Some TI SoCs contain a system controller (like the Power Management Micro + Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling + the state of the various hardware modules present on the SoC. Communication + between the host processor running an OS and the system controller happens + through a protocol called TI System Control Interface (TI-SCI protocol). + + This PM domain node represents the global PM domain managed by the TI-SCI + controller. Since this relies on the TI SCI protocol to communicate with + the TI-SCI controller, it must be a child of the TI-SCI controller node. + +properties: + compatible: + const: ti,sci-pm-domain + + "#power-domain-cells": + enum: [1, 2] + description: + The two cells represent values that the TI-SCI controller defines. + + The first cell should contain the device ID. + + The second cell, if cell-value is 2, should be one of the following + TI_SCI_PD_EXCLUSIVE - Allows the device to be exclusively controlled + or + TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts. + Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions. + + Please see http://processors.wiki.ti.com/index.php/TISCI for + protocol documentation for the values to be used for different devices. + +additionalProperties: false + +examples: + - | + k2g_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + - | + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index dbc62821c60b..9790617af1bc 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -100,7 +100,6 @@ patternProperties: properties: reg: minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. - maxItems: 3 items: - description: Address and size of the Data RAM0. - description: Address and size of the Data RAM1. @@ -111,7 +110,6 @@ patternProperties: reg-names: minItems: 2 - maxItems: 3 items: - const: dram0 - const: dram1 diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 67405e6d8168..19f111f40225 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -12,7 +12,11 @@ maintainers: properties: "#sound-dai-cells": - const: 0 + minimum: 0 + maximum: 1 + description: + A value of 0 is deprecated. When used, it only allows access to + the ADC/DAC and AIF1 (the CPU DAI), not the other two AIFs/DAIs. compatible: oneOf: @@ -50,7 +54,7 @@ additionalProperties: false examples: - | audio-codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = <0 29 4>; diff --git a/Documentation/devicetree/bindings/sound/cs42l42.txt b/Documentation/devicetree/bindings/sound/cs42l42.txt index 7dfaa2ab906f..5d416fdaf023 100644 --- a/Documentation/devicetree/bindings/sound/cs42l42.txt +++ b/Documentation/devicetree/bindings/sound/cs42l42.txt @@ -81,6 +81,13 @@ Optional properties: < x1 x2 x3 x4 > Default = < 15 8 4 1> + - cirrus,hs-bias-sense-disable: This is boolean property. If present the + HSBIAS sense is disabled. Configures HSBIAS output current sense through + the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce + the potential pop noise during the headset plug out slowly. But on some + platforms ESD voltage will affect it causing test to fail, especially + with CTIA headset type. For different hardware setups, a designer might + want to tweak default behavior. Example: diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml index 4454aca34d56..f226ec13167a 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -25,6 +25,7 @@ properties: - fsl,imx8mq-spdif - fsl,imx8mm-spdif - fsl,imx8mn-spdif + - fsl,imx8ulp-spdif reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 0dc83cc4a236..c71c5861d787 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -9,8 +9,10 @@ Required properties: - compatible : Compatible list, contains "fsl,vf610-sai", "fsl,imx6sx-sai", "fsl,imx6ul-sai", - "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or - "fsl,imx8qm-sai". + "fsl,imx7ulp-sai", "fsl,imx8mq-sai", + "fsl,imx8qm-sai", "fsl,imx8mm-sai", + "fsl,imx8mn-sai", "fsl,imx8mp-sai", or + "fsl,imx8ulp-sai". - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml new file mode 100644 index 000000000000..d1816dd061cf --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/imx-audio-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX audio sound card. + +maintainers: + - Shengjiu Wang + +properties: + compatible: + enum: + - fsl,imx-audio-card + + model: + $ref: /schemas/types.yaml#/definitions/string + description: User specified audio sound card name + + audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + A list of the connections between audio components. Each entry is a + pair of strings, the first being the connection's sink, the second + being the connection's source. Valid names could be power supplies, + MicBias of codec and the jacks on the board. + +patternProperties: + ".*-dai-link$": + description: + Each subnode represents a dai link. Subnodes of each dai links would be + cpu/codec dais. + + type: object + + properties: + link-name: + description: Indicates dai-link name and PCM stream name. + $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 + + format: + description: audio format. + items: + enum: + - i2s + - dsp_b + + dai-tdm-slot-num: + description: see tdm-slot.txt. + $ref: /schemas/types.yaml#/definitions/uint32 + + dai-tdm-slot-width: + description: see tdm-slot.txt. + $ref: /schemas/types.yaml#/definitions/uint32 + + cpu: + description: Holds subnode which indicates cpu dai. + type: object + properties: + sound-dai: true + + codec: + description: Holds subnode which indicates codec dai. + type: object + properties: + sound-dai: true + + fsl,mclk-equal-bclk: + description: Indicates mclk can be equal to bclk, especially for sai interface + $ref: /schemas/types.yaml#/definitions/flag + + required: + - link-name + - cpu + + additionalProperties: false + +required: + - compatible + - model + +additionalProperties: false + +examples: + - | + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + }; + fe-dai-link { + link-name = "HiFi-ASRC-FE"; + format = "i2s"; + cpu { + sound-dai = <&easrc>; + }; + }; + be-dai-link { + link-name = "HiFi-ASRC-BE"; + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt deleted file mode 100644 index 2db4dcbee1b9..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audmux.txt +++ /dev/null @@ -1,28 +0,0 @@ -Freescale Digital Audio Mux (AUDMUX) device - -Required properties: - - - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used - on i.MX21, or "fsl,imx31-audmux" for the version - firstly used on i.MX31. - - - reg : Should contain AUDMUX registers location and length. - -An initial configuration can be setup using child nodes. - -Required properties of optional child nodes: - - - fsl,audmux-port : Integer of the audmux port that is configured by this - child node. - - - fsl,port-config : List of configuration options for the specific port. - For imx31-audmux and above, it is a list of tuples - . For imx21-audmux it is a list of pcr - values. - -Example: - -audmux@21d8000 { - compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; -}; diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.yaml b/Documentation/devicetree/bindings/sound/imx-audmux.yaml new file mode 100644 index 000000000000..dab45c310670 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audmux.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/imx-audmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Digital Audio Mux device + +maintainers: + - Oleksij Rempel + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx27-audmux + - const: fsl,imx21-audmux + - items: + - enum: + - fsl,imx25-audmux + - fsl,imx35-audmux + - fsl,imx50-audmux + - fsl,imx51-audmux + - fsl,imx53-audmux + - fsl,imx6q-audmux + - fsl,imx6sl-audmux + - fsl,imx6sll-audmux + - fsl,imx6sx-audmux + - const: fsl,imx31-audmux + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: audmux + +patternProperties: + "^mux-[0-9a-z]*$": + type: object + properties: + fsl,audmux-port: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Integer of the audmux port that is configured by this child node + + fsl,port-config: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + List of configuration options for the specific port. + For imx31-audmux and above, it is a list of tuples ptcr pdcr. + For imx21-audmux it is a list of pcr values. + + required: + - fsl,audmux-port + - fsl,port-config + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + audmux@21d8000 { + compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + }; + - | + audmux@10016000 { + compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; + reg = <0x10016000 0x1000>; + clocks = <&clks 1>; + clock-names = "audmux"; + + mux-ssi0 { + fsl,audmux-port = <0>; + fsl,port-config = <0xcb205000>; + }; + + mux-pins4 { + fsl,audmux-port = <2>; + fsl,port-config = <0x00001000>; + }; + }; + - | + #include + audmux@21d8000 { + compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml index 249970952202..5bdd30a8a404 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml @@ -28,7 +28,6 @@ properties: minItems: 2 clock-names: - minItems: 2 items: - const: pll_a - const: plla_out0 diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml index 38e52e7dbb40..63370709c768 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml @@ -34,7 +34,6 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: I2S bit clock - description: @@ -48,7 +47,6 @@ properties: clock-names: minItems: 1 - maxItems: 2 items: - const: i2s - const: sync_input diff --git a/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml b/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml new file mode 100644 index 000000000000..ffb8fcfeb629 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nxp,tfa989x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP/Goodix TFA989X (TFA1) Audio Amplifiers + +maintainers: + - Stephan Gerhold + +properties: + compatible: + enum: + - nxp,tfa9895 + - nxp,tfa9897 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + sound-name-prefix: + $ref: /schemas/types.yaml#/definitions/string + description: + Used as prefix for sink/source names of the component. Must be a + unique string among multiple instances of the same component. + + vddd-supply: + description: regulator phandle for the VDDD power supply. + +required: + - compatible + - reg + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@34 { + compatible = "nxp,tfa9895"; + reg = <0x34>; + sound-name-prefix = "Speaker Left"; + #sound-dai-cells = <0>; + }; + audio-codec@36 { + compatible = "nxp,tfa9895"; + reg = <0x36>; + sound-name-prefix = "Speaker Right"; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml index e8f716b5f875..9b225dbf8b79 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml @@ -77,6 +77,31 @@ properties: minimum: 1800000 maximum: 2850000 + qcom,hphl-jack-type-normally-closed: + description: Indicates that HPHL jack switch type is normally closed + type: boolean + + qcom,ground-jack-type-normally-closed: + description: Indicates that Headset Ground switch type is normally closed + type: boolean + + qcom,mbhc-headset-vthreshold-microvolt: + description: Voltage threshold value for headset detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-headphone-vthreshold-microvolt: + description: Voltage threshold value for headphone detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + clock-output-names: const: mclk @@ -159,6 +184,11 @@ examples: qcom,micbias2-microvolt = <1800000>; qcom,micbias3-microvolt = <1800000>; qcom,micbias4-microvolt = <1800000>; + qcom,hphl-jack-type-normally-closed; + qcom,ground-jack-type-normally-closed; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; clock-names = "extclk"; clocks = <&rpmhcc 2>; diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd938x-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd938x-sdw.yaml new file mode 100644 index 000000000000..49a267b306f6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wcd938x-sdw.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Qualcomm SoundWire Slave devices on WCD9380/WCD9385 + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire slave devices. This bindings is for the + slave devices. + +properties: + compatible: + const: sdw20217010d00 + + reg: + maxItems: 1 + + qcom,tx-port-mapping: + description: | + Specifies static port mapping between slave and master tx ports. + In the order of slave port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + + qcom,rx-port-mapping: + description: | + Specifies static port mapping between slave and master rx ports. + In the order of slave port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd938x_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml new file mode 100644 index 000000000000..cb74ce40c2e6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd938x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Qualcomm WCD9380/WCD9385 Audio Codec + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire slave devices. + +properties: + compatible: + enum: + - qcom,wcd9380-codec + - qcom,wcd9385-codec + + reset-gpios: + description: GPIO spec for reset line to use + maxItems: 1 + + vdd-buck-supply: + description: A reference to the 1.8V buck supply + + vdd-rxtx-supply: + description: A reference to the 1.8V rx supply + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + qcom,tx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire tx device phandle + + qcom,rx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire rx device phandle + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias4-microvolt: + description: micbias4 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,hphl-jack-type-normally-closed: + description: Indicates that HPHL jack switch type is normally closed + type: boolean + + qcom,ground-jack-type-normally-closed: + description: Indicates that Headset Ground switch type is normally closed + type: boolean + + qcom,mbhc-headset-vthreshold-microvolt: + description: Voltage threshold value for headset detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-headphone-vthreshold-microvolt: + description: Voltage threshold value for headphone detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reset-gpios + - qcom,tx-device + - qcom,rx-device + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - qcom,micbias4-microvolt + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + codec { + compatible = "qcom,wcd9380-codec"; + reset-gpios = <&tlmm 32 0>; + #sound-dai-cells = <1>; + qcom,tx-device = <&wcd938x_tx>; + qcom,rx-device = <&wcd938x_rx>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,hphl-jack-type-normally-closed; + qcom,ground-jack-type-normally-closed; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + }; + + /* ... */ + + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd938x_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 605de3a5847f..ee936d1aa724 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -86,9 +86,11 @@ properties: power-domains: true resets: + minItems: 1 maxItems: 11 reset-names: + minItems: 1 maxItems: 11 clocks: @@ -110,6 +112,13 @@ properties: - pattern: '^dvc\.[0-1]$' - pattern: '^clk_(a|b|c|i)$' + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port(@[0-9a-f]+)?: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + port: $ref: audio-graph-port.yaml# unevaluatedProperties: false @@ -257,7 +266,6 @@ required: - "#sound-dai-cells" allOf: - - $ref: audio-graph.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.yaml b/Documentation/devicetree/bindings/sound/sgtl5000.yaml index 70b4a8831073..e762c320b574 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.yaml +++ b/Documentation/devicetree/bindings/sound/sgtl5000.yaml @@ -75,6 +75,10 @@ properties: $ref: "/schemas/types.yaml#/definitions/uint32" enum: [ 0, 1, 2, 3 ] + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index f2443b651282..06e83461705c 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -26,7 +26,6 @@ properties: - description: Base address and size of SAI common register set. - description: Base address and size of SAI identification register set. minItems: 1 - maxItems: 2 ranges: maxItems: 1 @@ -81,14 +80,12 @@ patternProperties: - description: sai_ck clock feeding the internal clock generator. - description: MCLK clock from a SAI set as master clock provider. minItems: 1 - maxItems: 2 clock-names: items: - const: sai_ck - const: MCLK minItems: 1 - maxItems: 2 dmas: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt b/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt index ca75890f0d07..f59125bc79d1 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt @@ -6,6 +6,7 @@ Required properties: - compatible - "string" - One of: "ti,tlv320aic32x4" TLV320AIC3204 "ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256 + "ti,tas2505" TAS2505, TAS2521 - reg: I2C slave address - supply-*: Required supply regulators are: "iov" - digital IO power supply diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt deleted file mode 100644 index 682f221f6f38..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8750.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8750 and WM8987 audio CODECs - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8750" or "wlf,wm8987" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8750: codec@1a { - compatible = "wlf,wm8750"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8750.yaml b/Documentation/devicetree/bindings/sound/wm8750.yaml new file mode 100644 index 000000000000..24246ac7bbdf --- /dev/null +++ b/Documentation/devicetree/bindings/sound/wm8750.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/wm8750.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WM8750 and WM8987 audio CODECs + +description: | + These devices support both I2C and SPI (configured with pin strapping + on the board). + +maintainers: + - Mark Brown + +properties: + compatible: + enum: + - wlf,wm8750 + - wlf,wm8987 + + reg: + description: + The I2C address of the device for I2C, the chip select number for SPI + maxItems: 1 + +additionalProperties: false + +required: + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "wlf,wm8750"; + reg = <0x1a>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index e3fb553d9180..4d46c49ec32b 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -35,7 +35,6 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: controller register bus clock - description: baud rate generator and delay control clock diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml index 6ee19d49fd3c..ec5873919170 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml @@ -56,7 +56,6 @@ properties: reg-names: minItems: 1 - maxItems: 5 items: - const: mspi - const: bspi @@ -71,7 +70,6 @@ properties: interrupt-names: oneOf: - minItems: 1 - maxItems: 7 items: - const: mspi_done - const: mspi_halted diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt index e2198a389484..200c7fc7b089 100644 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -25,7 +25,7 @@ Required properties: - interrupts: interrupt number mapped to CPU. - clocks: spi clk phandle For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt + Documentation/devicetree/bindings/clock/ti,sci-clk.yaml SoC-specific Required Properties: diff --git a/drivers/staging/hikey9xx/hisilicon,hisi-spmi-controller.yaml b/Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml similarity index 89% rename from drivers/staging/hikey9xx/hisilicon,hisi-spmi-controller.yaml rename to Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml index 6b755039a74c..f882903769f9 100644 --- a/drivers/staging/hikey9xx/hisilicon,hisi-spmi-controller.yaml +++ b/Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml @@ -14,7 +14,7 @@ description: | It is a MIPI System Power Management (SPMI) controller. The PMIC part is provided by - drivers/staging/hikey9xx/hisilicon,hi6421-spmi-pmic.yaml. + ./Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml. allOf: - $ref: spmi.yaml# @@ -30,7 +30,7 @@ properties: reg: maxItems: 1 - spmi-channel: + hisilicon,spmi-channel: $ref: /schemas/types.yaml#/definitions/uint32 description: | number of the Kirin 970 SPMI channel where the SPMI devices are connected. @@ -38,10 +38,12 @@ properties: required: - compatible - reg - - spmi-channel + - hisilicon,spmi-channel patternProperties: "@[0-9a-f]$": + type: object + description: | PMIC properties, which are specific to the used SPMI PMIC device(s). When used in combination with HiSilicon 6421v600, the properties @@ -61,7 +63,7 @@ examples: #address-cells = <2>; #size-cells = <0>; reg = <0x0 0xfff24000 0x0 0x1000>; - spmi-channel = <2>; + hisilicon,spmi-channel = <2>; pmic@0 { reg = <0 0>; diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml index 173940930719..1d243faef2f8 100644 --- a/Documentation/devicetree/bindings/spmi/spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/spmi.yaml @@ -40,14 +40,15 @@ patternProperties: properties: reg: - minItems: 1 - maxItems: 2 items: - - minimum: 0 - maximum: 0xf - - enum: [ 0 ] - description: | - 0 means user ID address. 1 is reserved for group ID address. + - minItems: 1 + items: + - minimum: 0 + maximum: 0xf + - enum: [ 0 ] + description: + 0 means user ID address. 1 is reserved for group ID + address. required: - reg diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index c1a5afa73cfe..3eda5049d183 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -28,6 +28,8 @@ properties: contains: enum: - mmio-sram + - amlogic,meson-gxbb-sram + - arm,juno-sram-ns - atmel,sama5d2-securam - rockchip,rk3288-pmu-sram @@ -80,6 +82,9 @@ patternProperties: - amlogic,meson8b-smp-sram - amlogic,meson-gxbb-scp-shmem - amlogic,meson-axg-scp-shmem + - arm,juno-scp-shmem + - arm,scmi-shmem + - arm,scp-shmem - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index bf97d1fb33e7..6e0b110153b0 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -23,14 +23,12 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: Bus Clock - description: Module Clock clock-names: minItems: 1 - maxItems: 2 items: - const: bus - const: mod diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0242fd91b622..0b3b6af7bd5b 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -77,7 +77,6 @@ properties: nvmem-cell-names: minItems: 1 - maxItems: 2 items: - const: calib - enum: diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index b6a6d03a08b2..2ecac754e1cd 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -24,7 +24,6 @@ properties: interrupts: minItems: 2 - maxItems: 4 items: - description: Timer 0 Interrupt - description: Timer 1 Interrupt diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index 7f5e3af58255..df8ce87fd54b 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -35,7 +35,6 @@ properties: interrupts: minItems: 1 - maxItems: 5 items: - description: secure timer irq - description: non-secure timer irq diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml index d83a1f97f911..cd2176cad53a 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -71,14 +71,12 @@ patternProperties: interrupts: minItems: 1 - maxItems: 2 items: - description: physical timer irq - description: virtual timer irq reg: minItems: 1 - maxItems: 2 items: - description: 1st view base address - description: 2nd optional view base address diff --git a/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml new file mode 100644 index 000000000000..5684df6448ef --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Timer-Watchdog Timer + +maintainers: + - Rob Herring + +description: + ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core + Timer-Watchdog (aka TWD), which provides both a per-cpu local timer + and watchdog. + + The TWD is usually attached to a GIC to deliver its two per-processor + interrupts. + +properties: + compatible: + enum: + - arm,cortex-a9-twd-timer + - arm,cortex-a5-twd-timer + - arm,arm11mp-twd-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + always-on: + description: + If present, the timer is powered through an always-on power domain, + therefore it never loses context. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + timer@2c000600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x2c000600 0x20>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/timer/arm,twd.txt b/Documentation/devicetree/bindings/timer/arm,twd.txt deleted file mode 100644 index 383ea19c2bf0..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,twd.txt +++ /dev/null @@ -1,53 +0,0 @@ -* ARM Timer Watchdog - -ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core -Timer-Watchdog (aka TWD), which provides both a per-cpu local timer -and watchdog. - -The TWD is usually attached to a GIC to deliver its two per-processor -interrupts. - -** Timer node required properties: - -- compatible : Should be one of: - "arm,cortex-a9-twd-timer" - "arm,cortex-a5-twd-timer" - "arm,arm11mp-twd-timer" - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the TWD timer - register window. - -Optional - -- always-on : a boolean property. If present, the timer is powered through - an always-on power domain, therefore it never loses context. - -Example: - - twd-timer@2c000600 { - compatible = "arm,arm11mp-twd-timer""; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0xf01>; - }; - -** Watchdog node properties: - -- compatible : Should be one of: - "arm,cortex-a9-twd-wdt" - "arm,cortex-a5-twd-wdt" - "arm,arm11mp-twd-wdt" - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the TWD watchdog - register window. - -Example: - - twd-watchdog@2c000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0xf01>; - }; diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml index a8de99b0c0f9..f32575d4b5aa 100644 --- a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml @@ -22,7 +22,6 @@ properties: interrupts: minItems: 1 - maxItems: 2 items: - description: Timer 1 interrupt - description: Timer 2 interrupt diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index f0f0f121c355..c57169118b68 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -36,6 +36,7 @@ properties: - renesas,tmu-r8a77980 # R-Car V3H - renesas,tmu-r8a77990 # R-Car E3 - renesas,tmu-r8a77995 # R-Car D3 + - renesas,tmu-r8a779a0 # R-Car V3U - const: renesas,tmu reg: diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.txt b/Documentation/devicetree/bindings/timer/renesas,tpu.txt deleted file mode 100644 index 1d46f9de4feb..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,tpu.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Renesas H8/300 Timer Pulse Unit - -The TPU is a 16bit timer/counter with configurable clock inputs and -programmable compare match. -This implementation support only cascade mode. - -Required Properties: - - - compatible: must contain "renesas,tpu" - - reg: base address and length of the registers block in 2 channel. - - clocks: a list of phandle, one for each entry in clock-names. - - clock-names: must contain "peripheral_clk" for the functional clock. - - -Example: - tpu: tpu@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&pclk>; - clock-names = "peripheral_clk"; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml new file mode 100644 index 000000000000..01554dff23d8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas H8/300 Timer Pulse Unit + +maintainers: + - Yoshinori Sato + +description: + The TPU is a 16bit timer/counter with configurable clock inputs and + programmable compare match. + This implementation supports only cascade mode. + +select: + properties: + compatible: + contains: + const: renesas,tpu + '#pwm-cells': false + required: + - compatible + +properties: + compatible: + const: renesas,tpu + + reg: + items: + - description: First channel + - description: Second channel + + clocks: + maxItems: 1 + + clock-names: + const: fck + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tpu: tpu@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&pclk>; + clock-names = "fck"; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 37ac0a3ae3b4..919a4bf03a5a 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -177,8 +177,14 @@ properties: - meas,tsys01 # MEMSIC magnetometer - memsic,mmc35240 + # MEMSIC 3-axis accelerometer + - memsic,mx4005 # MEMSIC 2-axis 8-bit digital accelerometer - memsic,mxc6225 + # MEMSIC 2-axis 8-bit digital accelerometer + - memsic,mxc6255 + # MEMSIC 3-axis accelerometer + - memsic,mxc6655 # Microchip differential I2C ADC, 1 Channel, 18 bit - microchip,mcp3421 # Microchip differential I2C ADC, 2 Channel, 18 bit @@ -263,6 +269,10 @@ properties: - sensirion,sgpc3 # Sensirion multi-pixel gas sensor with I2C interface - sensirion,sgp30 + # Sensortek 3 axis accelerometer + - sensortek,stk8312 + # Sensortek 3 axis accelerometer + - sensortek,stk8ba50 # SGX Sensortech VZ89X Sensors - sgx,vz89x # Relative Humidity and Temperature Sensors @@ -272,6 +282,8 @@ properties: # Socionext SynQuacer TPM MMIO module - socionext,synquacer-tpm-mmio # i2c serial eeprom (24cxx) + - sparkfun,qwiic-joystick + # SparkFun Qwiic Joystick (COM-15168) with i2c interface - st,24c256 # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index 0f520f17735e..933fa356d2ce 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -22,6 +22,9 @@ properties: - allwinner,sun8i-a83t-musb - allwinner,sun50i-h6-musb - const: allwinner,sun8i-a33-musb + - items: + - const: allwinner,sun50i-h616-musb + - const: allwinner,sun8i-h3-musb reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml index a407e1143cf4..dc9d6ed0781d 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -28,9 +28,9 @@ properties: interrupts: minItems: 3 items: - - description: OTG/DRD controller interrupt - description: XHCI host controller interrupt - description: Device controller interrupt + - description: OTG/DRD controller interrupt - description: interrupt used to wake up core, e.g when usbcmd.rs is cleared by xhci core, this interrupt is optional @@ -75,6 +75,7 @@ required: - reg - reg-names - interrupts + - interrupt-names additionalProperties: false diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index e5ee51b7b470..10c7d9b6cc53 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -24,6 +24,7 @@ properties: - rockchip,rk3188-usb - rockchip,rk3228-usb - rockchip,rk3288-usb + - rockchip,rk3308-usb - rockchip,rk3328-usb - rockchip,rk3368-usb - rockchip,rv1108-usb diff --git a/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml b/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml index 4241d38d5864..1d893d3d3432 100644 --- a/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml +++ b/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml @@ -30,14 +30,12 @@ properties: - description: usb irq from max3420 - description: vbus detection irq minItems: 1 - maxItems: 2 interrupt-names: items: - const: udc - const: vbus minItems: 1 - maxItems: 2 spi-max-frequency: maximum: 26000000 diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index e60e590dbe12..8428415896ce 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -25,7 +25,6 @@ properties: reg: minItems: 2 - maxItems: 3 items: - description: XUSB device controller registers - description: XUSB device PCI Config registers @@ -33,7 +32,6 @@ properties: reg-names: minItems: 2 - maxItems: 3 items: - const: base - const: fpci @@ -45,7 +43,6 @@ properties: clocks: minItems: 4 - maxItems: 5 items: - description: Clock to enable core XUSB dev clock. - description: Clock to enable XUSB super speed clock. @@ -55,7 +52,6 @@ properties: clock-names: minItems: 4 - maxItems: 5 items: - const: dev - const: ss diff --git a/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml b/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml new file mode 100644 index 000000000000..a88f99adfe8e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/nxp,isp1760.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP ISP1760 family controller bindings + +maintainers: + - Sebastian Siewior + - Laurent Pinchart + +description: | + NXP ISP1760 family, which includes ISP1760/1761/1763 devicetree controller + bindings + +properties: + compatible: + enum: + - nxp,usb-isp1760 + - nxp,usb-isp1761 + - nxp,usb-isp1763 + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: Host controller interrupt + - description: Device controller interrupt in isp1761 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + - const: host + - const: peripheral + + bus-width: + description: + Number of data lines. + enum: [8, 16, 32] + default: 32 + + dr_mode: + enum: + - host + - peripheral + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = ; + bus-width = <16>; + dr_mode = "host"; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 413299b5fe2b..4e6451789806 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -19,6 +19,8 @@ properties: - qcom,sc7280-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8350-dwc3 diff --git a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml new file mode 100644 index 000000000000..04ee255eb4f0 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for the Realtek RTS5411 USB 3.0 hub controller + +maintainers: + - Matthias Kaehlcke + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + items: + - enum: + - usbbda,5411 + - usbbda,411 + + reg: true + + vdd-supply: + description: + phandle to the regulator that provides power to the hub. + + companion-hub: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + phandle to the companion hub on the controller. + +required: + - companion-hub + - compatible + - reg + +additionalProperties: false + +examples: + - | + usb { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + vdd-supply = <&pp3300_hub>; + companion-hub = <&hub_3_0>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + vdd-supply = <&pp3300_hub>; + companion-hub = <&hub_2_0>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index e67223d90bb7..ad73339ffe1d 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -53,7 +53,6 @@ properties: clocks: minItems: 1 - maxItems: 3 items: - description: USB 2.0 host - description: USB 2.0 peripheral @@ -86,7 +85,6 @@ properties: dma-names: minItems: 2 - maxItems: 4 items: - const: ch0 - const: ch1 @@ -100,7 +98,6 @@ properties: resets: minItems: 1 - maxItems: 2 items: - description: USB 2.0 host - description: USB 2.0 peripheral diff --git a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml index 7ec87a783c5c..a634774c537c 100644 --- a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml +++ b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml @@ -27,7 +27,7 @@ properties: description: PM domain provider node and an args specifier containing the USB device id value. See, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml maxItems: 1 clocks: diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml index 9a068d3bc73b..f6e91a5fd8fe 100644 --- a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml @@ -47,7 +47,7 @@ properties: description: Should contain a phandle to a PM domain provider node and an args specifier containing the USB device id value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml phys: maxItems: 1 diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b868cefc7c55..2bbc27aae977 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -472,7 +472,7 @@ patternProperties: "^hirschmann,.*": description: Hirschmann Automation and Control GmbH "^hisilicon,.*": - description: Hisilicon Limited. + description: HiSilicon Limited. "^hit,.*": description: Hitachi Ltd. "^hitex,.*": @@ -533,6 +533,8 @@ patternProperties: description: Innolux Corporation "^inside-secure,.*": description: INSIDE Secure + "^insignal,.*": + description: Insignal Ltd. "^inspur,.*": description: Inspur Corporation "^intel,.*": @@ -830,6 +832,8 @@ patternProperties: description: Opal Kelly Incorporated "^opencores,.*": description: OpenCores.org + "^openembed,.*": + description: OpenEmbed "^openrisc,.*": description: OpenRISC.io "^option,.*": @@ -1076,6 +1080,8 @@ patternProperties: description: Sony Corporation "^spansion,.*": description: Spansion Inc. + "^sparkfun,.*": + description: SparkFun Electronics "^sprd,.*": description: Spreadtrum Communications Inc. "^sst,.*": @@ -1085,6 +1091,8 @@ patternProperties: (formerly part of MStar Semiconductor, Inc.) "^st,.*": description: STMicroelectronics + "^starfive,.*": + description: StarFive Technology Co. Ltd. "^starry,.*": description: Starry Electronic Technology (ShenZhen) Co., LTD "^startek,.*": diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt deleted file mode 100644 index 0a575f329f6e..000000000000 --- a/Documentation/devicetree/bindings/virtio/mmio.txt +++ /dev/null @@ -1,47 +0,0 @@ -* virtio memory mapped device - -See https://ozlabs.org/~rusty/virtio-spec/ for more details. - -Required properties: - -- compatible: "virtio,mmio" compatibility string -- reg: control registers base address and size including configuration space -- interrupts: interrupt generated by the device - -Required properties for virtio-iommu: - -- #iommu-cells: When the node corresponds to a virtio-iommu device, it is - linked to DMA masters using the "iommus" or "iommu-map" - properties [1][2]. #iommu-cells specifies the size of the - "iommus" property. For virtio-iommu #iommu-cells must be - 1, each cell describing a single endpoint ID. - -Optional properties: - -- iommus: If the device accesses memory through an IOMMU, it should - have an "iommus" property [1]. Since virtio-iommu itself - does not access memory through an IOMMU, the "virtio,mmio" - node cannot have both an "#iommu-cells" and an "iommus" - property. - -Example: - - virtio_block@3000 { - compatible = "virtio,mmio"; - reg = <0x3000 0x100>; - interrupts = <41>; - - /* Device has endpoint ID 23 */ - iommus = <&viommu 23> - } - - viommu: iommu@3100 { - compatible = "virtio,mmio"; - reg = <0x3100 0x100>; - interrupts = <42>; - - #iommu-cells = <1> - } - -[1] Documentation/devicetree/bindings/iommu/iommu.txt -[2] Documentation/devicetree/bindings/pci/pci-iommu.txt diff --git a/Documentation/devicetree/bindings/virtio/mmio.yaml b/Documentation/devicetree/bindings/virtio/mmio.yaml new file mode 100644 index 000000000000..d46597028cf1 --- /dev/null +++ b/Documentation/devicetree/bindings/virtio/mmio.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/virtio/mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: virtio memory mapped devices + +maintainers: + - Jean-Philippe Brucker + +description: + See https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio for + more details. + +properties: + compatible: + const: virtio,mmio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#iommu-cells': + description: Required when the node corresponds to a virtio-iommu device. + const: 1 + + iommus: + description: Required for devices making accesses thru an IOMMU. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + virtio@3000 { + compatible = "virtio,mmio"; + reg = <0x3000 0x100>; + interrupts = <41>; + + /* Device has endpoint ID 23 */ + iommus = <&viommu 23>; + }; + + viommu: iommu@3100 { + compatible = "virtio,mmio"; + reg = <0x3100 0x100>; + interrupts = <42>; + + #iommu-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml b/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml new file mode 100644 index 000000000000..6bfa46353c4e --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SBSA (Server Base System Architecture) Generic Watchdog + +maintainers: + - Fu Wei + +description: | + The SBSA Generic Watchdog Timer is used to force a reset of the system after + two stages of timeout have elapsed. A detailed definition of the watchdog + timer can be found in the ARM document: ARM-DEN-0029 - Server Base System + Architecture (SBSA) + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: arm,sbsa-gwdt + + reg: + items: + - description: Watchdog control frame + - description: Refresh frame + + interrupts: + description: The Watchdog Signal 0 (WS0) SPI (Shared Peripheral Interrupt) + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + + watchdog@2a440000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x2a440000 0x1000>, + <0x2a450000 0x1000>; + interrupts = <0 27 4>; + timeout-sec = <30>; + }; +... diff --git a/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml b/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml new file mode 100644 index 000000000000..bb8901854222 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Timer-Watchdog Watchdog + +maintainers: + - Rob Herring + +description: + ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core + Timer-Watchdog (aka TWD), which provides both a per-cpu local timer + and watchdog. + + The TWD is usually attached to a GIC to deliver its two per-processor + interrupts. + +properties: + compatible: + enum: + - arm,cortex-a9-twd-wdt + - arm,cortex-a5-twd-wdt + - arm,arm11mp-twd-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + watchdog@2c000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0x2c000620 0x20>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt b/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt deleted file mode 100644 index 6f2d5f91964d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt +++ /dev/null @@ -1,31 +0,0 @@ -* SBSA (Server Base System Architecture) Generic Watchdog - -The SBSA Generic Watchdog Timer is used to force a reset of the system -after two stages of timeout have elapsed. A detailed definition of the -watchdog timer can be found in the ARM document: ARM-DEN-0029 - Server -Base System Architecture (SBSA) - -Required properties: -- compatible: Should at least contain "arm,sbsa-gwdt". - -- reg: Each entry specifies the base physical address of a register frame - and the length of that frame; currently, two frames must be defined, - in this order: - 1: Watchdog control frame; - 2: Refresh frame. - -- interrupts: Should contain the Watchdog Signal 0 (WS0) SPI (Shared - Peripheral Interrupt) number of SBSA Generic Watchdog. - -Optional properties -- timeout-sec: Watchdog timeout values (in seconds). - -Example for FVP Foundation Model v8: - -watchdog@2a440000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x2a440000 0 0x1000>, - <0x0 0x2a450000 0 0x1000>; - interrupts = <0 27 4>; - timeout-sec = <30>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml index 3f1ba1d6c6b5..481bf91f988a 100644 --- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml +++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml @@ -27,7 +27,6 @@ properties: - description: Low speed clock - description: Optional peripheral clock minItems: 1 - maxItems: 2 clock-names: items: diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 45ff426d0019..f7dfb98c156e 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -52,7 +52,8 @@ Properties constraints specific to the device. - DO use common property unit suffixes for properties with scientific units. - See property-units.txt. + Recommended suffixes are listed at + https://github.com/devicetree-org/dt-schema/blob/master/schemas/property-units.yaml - DO define properties in terms of constraints. How many entries? What are possible values? What is the order? diff --git a/Documentation/driver-api/auxiliary_bus.rst b/Documentation/driver-api/auxiliary_bus.rst index fff96c7ba7a8..ef902daf0d68 100644 --- a/Documentation/driver-api/auxiliary_bus.rst +++ b/Documentation/driver-api/auxiliary_bus.rst @@ -11,7 +11,7 @@ too complex for a single device to be managed by a monolithic driver (e.g. Sound Open Firmware), multiple devices might implement a common intersection of functionality (e.g. NICs + RDMA), or a driver may want to export an interface for another subsystem to drive (e.g. SIOV Physical Function -export Virtual Function management). A split of the functinoality into child- +export Virtual Function management). A split of the functionality into child- devices representing sub-domains of functionality makes it possible to compartmentalize, layer, and distribute domain-specific concerns via a Linux device-driver model. diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst index 1bad466f9167..487ce4f41d77 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -22,16 +22,22 @@ This section covers the driver infrastructure for a CXL memory device. CXL Memory Device ----------------- -.. kernel-doc:: drivers/cxl/mem.c - :doc: cxl mem +.. kernel-doc:: drivers/cxl/pci.c + :doc: cxl pci -.. kernel-doc:: drivers/cxl/mem.c +.. kernel-doc:: drivers/cxl/pci.c :internal: -CXL Bus -------- -.. kernel-doc:: drivers/cxl/bus.c - :doc: cxl bus +CXL Core +-------- +.. kernel-doc:: drivers/cxl/cxl.h + :doc: cxl objects + +.. kernel-doc:: drivers/cxl/cxl.h + :internal: + +.. kernel-doc:: drivers/cxl/core.c + :doc: cxl core External Interfaces =================== diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 7f37ec30d9fd..7f21425d9435 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -178,6 +178,15 @@ DMA Fence Array .. kernel-doc:: include/linux/dma-fence-array.h :internal: +DMA Fence Chain +~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence-chain.c + :export: + +.. kernel-doc:: include/linux/dma-fence-chain.h + :internal: + DMA Fence uABI/Sync File ~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/driver-api/driver-model/devres.rst b/Documentation/driver-api/driver-model/devres.rst index e0814d214048..0fe1fffa295e 100644 --- a/Documentation/driver-api/driver-model/devres.rst +++ b/Documentation/driver-api/driver-model/devres.rst @@ -314,7 +314,6 @@ IOMAP devm_ioremap_resource() : checks resource, requests memory region, ioremaps devm_ioremap_resource_wc() devm_platform_ioremap_resource() : calls devm_ioremap_resource() for platform device - devm_platform_ioremap_resource_wc() devm_platform_ioremap_resource_byname() devm_platform_get_and_ioremap_resource() devm_iounmap() diff --git a/Documentation/driver-api/generic-counter.rst b/Documentation/driver-api/generic-counter.rst index b02c52cd69d6..64fe7db080e5 100644 --- a/Documentation/driver-api/generic-counter.rst +++ b/Documentation/driver-api/generic-counter.rst @@ -307,7 +307,7 @@ Determining the type of extension to create is a matter of scope. * Device extensions are attributes that expose information/control non-specific to a particular Count or Signal. This is where you would - put your global features or other miscellanous functionality. + put your global features or other miscellaneous functionality. For example, if your device has an overtemp sensor, you can report the chip overheated via a device extension called "error_overtemp": diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index e2474425fb0c..71eefe5a023f 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -95,7 +95,7 @@ this in our driver:: To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and selected drivers, you need to select them from your machine's Kconfig entry, since these are so tightly integrated with the machines they are used on. -See for example arch/arm/mach-u300/Kconfig for an example. +See for example arch/arm/mach-ux500/Kconfig for an example. Pins usually have fancier names than this. You can find these in the datasheet for your chip. Notice that the core pinctrl.h file provides a fancy macro diff --git a/Documentation/driver-api/serial/moxa-smartio.rst b/Documentation/driver-api/serial/moxa-smartio.rst index 156100f17c3f..af25bc5cc3e6 100644 --- a/Documentation/driver-api/serial/moxa-smartio.rst +++ b/Documentation/driver-api/serial/moxa-smartio.rst @@ -2,14 +2,8 @@ MOXA Smartio/Industio Family Device Driver Installation Guide ============================================================= -.. note:: - - This file is outdated. It needs some care in order to make it - updated to Kernel 5.0 and upper - Copyright (C) 2008, Moxa Inc. - -Date: 01/21/2008 +Copyright (C) 2021, Jiri Slaby .. Content @@ -17,12 +11,7 @@ Date: 01/21/2008 2. System Requirement 3. Installation 3.1 Hardware installation - 3.2 Driver files - 3.3 Device naming convention - 3.4 Module driver configuration - 3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x. - 3.6 Custom configuration - 3.7 Verify driver installation + 3.2 Device naming convention 4. Utilities 5. Setserial 6. Troubleshooting @@ -31,14 +20,13 @@ Date: 01/21/2008 ^^^^^^^^^^^^^^^ The Smartio/Industio/UPCI family Linux driver supports following multiport - boards. + boards: - 2 ports multiport board CP-102U, CP-102UL, CP-102UF CP-132U-I, CP-132UL, CP-132, CP-132I, CP132S, CP-132IS, - CI-132, CI-132I, CI-132IS, - (C102H, C102HI, C102HIS, C102P, CP-102, CP-102S) + (CP-102, CP-102S) - 4 ports multiport board CP-104EL, @@ -46,10 +34,7 @@ Date: 01/21/2008 CP-134U, CP-134U-I, C104H/PCI, C104HS/PCI, CP-114, CP-114I, CP-114S, CP-114IS, CP-114UL, - C104H, C104HS, - CI-104J, CI-104JS, - CI-134, CI-134I, CI-134IS, - (C114HI, CT-114I, C104P), + (C114HI, CT-114I), POS-104UL, CB-114, CB-134I @@ -58,15 +43,10 @@ Date: 01/21/2008 CP-118EL, CP-168EL, CP-118U, CP-168U, C168H/PCI, - C168H, C168HS, - (C168P), CB-108 - This driver and installation procedure have been developed upon Linux Kernel - 2.4.x and 2.6.x. This driver supports Intel x86 hardware platform. In order - to maintain compatibility, this version has also been properly tested with - RedHat, Mandrake, Fedora and S.u.S.E Linux. However, if compatibility problem - occurs, please contact Moxa at support@moxa.com.tw. + If a compatibility problem occurs, please contact Moxa at + support@moxa.com.tw. In addition to device driver, useful utilities are also provided in this version. They are: @@ -78,22 +58,19 @@ Date: 01/21/2008 Monitor program to observe data count and line status signals. - msterm A simple terminal program which is useful in testing serial ports. - - io-irq.exe - Configuration program to setup ISA boards. Please note that - this program can only be executed under DOS. All the drivers and utilities are published in form of source code under GNU General Public License in this version. Please refer to GNU General Public License announcement in each source code file for more detail. - In Moxa's Web sites, you may always find latest driver at http://www.moxa.com/. + In Moxa's Web sites, you may always find the latest driver at + https://www.moxa.com/. - This version of driver can be installed as Loadable Module (Module driver) - or built-in into kernel (Static driver). You may refer to following - installation procedure for suitable one. Before you install the driver, + This version of driver can be installed as a Loadable Module (Module driver) + or built-in into kernel (Static driver). Before you install the driver, please refer to hardware installation procedure in the User's Manual. - We assume the user should be familiar with following documents. + We assume the user should be familiar with following documents: - Serial-HOWTO - Kernel-HOWTO @@ -101,9 +78,6 @@ Date: 01/21/2008 2. System Requirement ^^^^^^^^^^^^^^^^^^^^^ - - Hardware platform: Intel x86 machine - - Kernel version: 2.4.x or 2.6.x - - gcc version 2.72 or later - Maximum 4 boards can be installed in combination 3. Installation @@ -112,23 +86,12 @@ Date: 01/21/2008 3.1 Hardware installation ========================= - There are two types of buses, ISA and PCI, for Smartio/Industio - family multiport board. - -ISA board ---------- - - You'll have to configure CAP address, I/O address, Interrupt Vector - as well as IRQ before installing this driver. Please refer to hardware - installation procedure in User's Manual before proceed any further. - Please make sure the JP1 is open after the ISA board is set properly. - PCI/UPCI board -------------- - You may need to adjust IRQ usage in BIOS to avoid from IRQ conflict - with other ISA devices. Please refer to hardware installation - procedure in User's Manual in advance. + You may need to adjust IRQ usage in BIOS to avoid IRQ conflict with other + ISA devices. Please refer to hardware installation procedure in User's + Manual in advance. PCI IRQ Sharing --------------- @@ -138,42 +101,11 @@ PCI IRQ Sharing together on one system and they can share the same IRQ. -3.2 Driver files -================ - The driver file may be obtained from ftp, CD-ROM or floppy disk. The - first step, anyway, is to copy driver file "mxser.tgz" into specified - directory. e.g. /moxa. The execute commands as below:: - - # cd / - # mkdir moxa - # cd /moxa - # tar xvf /dev/fd0 - -or:: - - # cd / - # mkdir moxa - # cd /moxa - # cp /mnt/cdrom//mxser.tgz . - # tar xvfz mxser.tgz - - -3.3 Device naming convention +3.2 Device naming convention ============================ - You may find all the driver and utilities files in /moxa/mxser. - Following installation procedure depends on the model you'd like to - run the driver. If you prefer module driver, please refer to 3.4. - If static driver is required, please refer to 3.5. - -Dialin and callout port ------------------------ - - This driver remains traditional serial device properties. There are - two special file name for each serial port. One is dial-in port - which is named "ttyMxx". For callout port, the naming convention - is "cumxx". + The device node is named "ttyMxx". Device naming when more than 2 boards installed ----------------------------------------------- @@ -181,322 +113,13 @@ Device naming when more than 2 boards installed Naming convention for each Smartio/Industio multiport board is pre-defined as below. - ============ =============== ============== - Board Num. Dial-in Port Callout port - 1st board ttyM0 - ttyM7 cum0 - cum7 - 2nd board ttyM8 - ttyM15 cum8 - cum15 - 3rd board ttyM16 - ttyM23 cum16 - cum23 - 4th board ttyM24 - ttym31 cum24 - cum31 - ============ =============== ============== - -.. note:: - - Under Kernel 2.6 and upper, the cum Device is Obsolete. So use ttyM* - device instead. - -Board sequence --------------- - - This driver will activate ISA boards according to the parameter set - in the driver. After all specified ISA board activated, PCI board - will be installed in the system automatically driven. - Therefore the board number is sorted by the CAP address of ISA boards. - For PCI boards, their sequence will be after ISA boards and C168H/PCI - has higher priority than C104H/PCI boards. - -3.4 Module driver configuration -=============================== - - Module driver is easiest way to install. If you prefer static driver - installation, please skip this paragraph. - - - ------------- Prepare to use the MOXA driver -------------------- - -3.4.1 Create tty device with correct major number -------------------------------------------------- - - Before using MOXA driver, your system must have the tty devices - which are created with driver's major number. We offer one shell - script "msmknod" to simplify the procedure. - This step is only needed to be executed once. But you still - need to do this procedure when: - - a. You change the driver's major number. Please refer the "3.7" - section. - b. Your total installed MOXA boards number is changed. Maybe you - add/delete one MOXA board. - c. You want to change the tty name. This needs to modify the - shell script "msmknod" - - The procedure is:: - - # cd /moxa/mxser/driver - # ./msmknod - - This shell script will require the major number for dial-in - device and callout device to create tty device. You also need - to specify the total installed MOXA board number. Default major - numbers for dial-in device and callout device are 30, 35. If - you need to change to other number, please refer section "3.7" - for more detailed procedure. - Msmknod will delete any special files occupying the same device - naming. - -3.4.2 Build the MOXA driver and utilities ------------------------------------------ - - Before using the MOXA driver and utilities, you need compile the - all the source code. This step is only need to be executed once. - But you still re-compile the source code if you modify the source - code. For example, if you change the driver's major number (see - "3.7" section), then you need to do this step again. - - Find "Makefile" in /moxa/mxser, then run - - # make clean; make install - - ..note:: - - For Red Hat 9, Red Hat Enterprise Linux AS3/ES3/WS3 & Fedora Core1: - # make clean; make installsp1 - - For Red Hat Enterprise Linux AS4/ES4/WS4: - # make clean; make installsp2 - - The driver files "mxser.o" and utilities will be properly compiled - and copied to system directories respectively. - -------------- Load MOXA driver-------------------- - -3.4.3 Load the MOXA driver --------------------------- - - :: - - # modprobe mxser - - will activate the module driver. You may run "lsmod" to check - if "mxser" is activated. If the MOXA board is ISA board, the - is needed. Please refer to section "3.4.5" for more - information. - -------------- Load MOXA driver on boot -------------------- - -3.4.4 Load the mxser driver ---------------------------- - - - For the above description, you may manually execute - "modprobe mxser" to activate this driver and run - "rmmod mxser" to remove it. - - However, it's better to have a boot time configuration to - eliminate manual operation. Boot time configuration can be - achieved by rc file. We offer one "rc.mxser" file to simplify - the procedure under "moxa/mxser/driver". - - But if you use ISA board, please modify the "modprobe ..." command - to add the argument (see "3.4.5" section). After modifying the - rc.mxser, please try to execute "/moxa/mxser/driver/rc.mxser" - manually to make sure the modification is ok. If any error - encountered, please try to modify again. If the modification is - completed, follow the below step. - - Run following command for setting rc files:: - - # cd /moxa/mxser/driver - # cp ./rc.mxser /etc/rc.d - # cd /etc/rc.d - - Check "rc.serial" is existed or not. If "rc.serial" doesn't exist, - create it by vi, run "chmod 755 rc.serial" to change the permission. - - Add "/etc/rc.d/rc.mxser" in last line. - - Reboot and check if moxa.o activated by "lsmod" command. - -3.4.5. specify CAP address --------------------------- - - If you'd like to drive Smartio/Industio ISA boards in the system, - you'll have to add parameter to specify CAP address of given - board while activating "mxser.o". The format for parameters are - as follows.:: - - modprobe mxser ioaddr=0x???,0x???,0x???,0x??? - | | | | - | | | +- 4th ISA board - | | +------ 3rd ISA board - | +------------ 2nd ISA board - +-------------------1st ISA board - -3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x -================================================================ - - Note: - To use static driver, you must install the linux kernel - source package. - -3.5.1 Backup the built-in driver in the kernel ----------------------------------------------- - - :: - - # cd /usr/src/linux/drivers/char - # mv mxser.c mxser.c.old - - For Red Hat 7.x user, you need to create link: - # cd /usr/src - # ln -s linux-2.4 linux - -3.5.2 Create link ------------------ - :: - - # cd /usr/src/linux/drivers/char - # ln -s /moxa/mxser/driver/mxser.c mxser.c - -3.5.3 Add CAP address list for ISA boards. ------------------------------------------- - - For PCI boards user, please skip this step. - - In module mode, the CAP address for ISA board is given by - parameter. In static driver configuration, you'll have to - assign it within driver's source code. If you will not - install any ISA boards, you may skip to next portion. - The instructions to modify driver source code are as - below. - - a. run:: - - # cd /moxa/mxser/driver - # vi mxser.c - - b. Find the array mxserBoardCAP[] as below:: - - static int mxserBoardCAP[] = {0x00, 0x00, 0x00, 0x00}; - - c. Change the address within this array using vi. For - example, to driver 2 ISA boards with CAP address - 0x280 and 0x180 as 1st and 2nd board. Just to change - the source code as follows:: - - static int mxserBoardCAP[] = {0x280, 0x180, 0x00, 0x00}; - -3.5.4 Setup kernel configuration --------------------------------- - - Configure the kernel:: - - # cd /usr/src/linux - # make menuconfig - - You will go into a menu-driven system. Please select [Character - devices][Non-standard serial port support], enable the [Moxa - SmartIO support] driver with "[*]" for built-in (not "[M]"), then - select [Exit] to exit this program. - -3.5.5 Rebuild kernel --------------------- - - The following are for Linux kernel rebuilding, for your - reference only. - - For appropriate details, please refer to the Linux document: - - a. Run the following commands:: - - cd /usr/src/linux - make clean # take a few minutes - make dep # take a few minutes - make bzImage # take probably 10-20 minutes - make install # copy boot image to correct position - - f. Please make sure the boot kernel (vmlinuz) is in the - correct position. - g. If you use 'lilo' utility, you should check /etc/lilo.conf - 'image' item specified the path which is the 'vmlinuz' path, - or you will load wrong (or old) boot kernel image (vmlinuz). - After checking /etc/lilo.conf, please run "lilo". - - Note that if the result of "make bzImage" is ERROR, then you have to - go back to Linux configuration Setup. Type "make menuconfig" in - directory /usr/src/linux. - - -3.5.6 Make tty device and special file --------------------------------------- - - :: - # cd /moxa/mxser/driver - # ./msmknod - -3.5.7 Make utility ------------------- - - :: - - # cd /moxa/mxser/utility - # make clean; make install - -3.5.8 Reboot ------------- - - - -3.6 Custom configuration -======================== - - Although this driver already provides you default configuration, you - still can change the device name and major number. The instruction to - change these parameters are shown as below. - -a. Change Device name - - If you'd like to use other device names instead of default naming - convention, all you have to do is to modify the internal code - within the shell script "msmknod". First, you have to open "msmknod" - by vi. Locate each line contains "ttyM" and "cum" and change them - to the device name you desired. "msmknod" creates the device names - you need next time executed. - -b. Change Major number - - If major number 30 and 35 had been occupied, you may have to select - 2 free major numbers for this driver. There are 3 steps to change - major numbers. - -3.6.1 Find free major numbers ------------------------------ - - In /proc/devices, you may find all the major numbers occupied - in the system. Please select 2 major numbers that are available. - e.g. 40, 45. - -3.6.2 Create special files --------------------------- - - Run /moxa/mxser/driver/msmknod to create special files with - specified major numbers. - -3.6.3 Modify driver with new major number ------------------------------------------ - - Run vi to open /moxa/mxser/driver/mxser.c. Locate the line - contains "MXSERMAJOR". Change the content as below:: - - #define MXSERMAJOR 40 - #define MXSERCUMAJOR 45 - - 3.6.4 Run "make clean; make install" in /moxa/mxser/driver. - -3.7 Verify driver installation -============================== - - You may refer to /var/log/messages to check the latest status - log reported by this driver whenever it's activated. + ============ =============== + Board Num. Device node + 1st board ttyM0 - ttyM7 + 2nd board ttyM8 - ttyM15 + 3rd board ttyM16 - ttyM23 + 4th board ttyM24 - ttyM31 + ============ =============== 4. Utilities ^^^^^^^^^^^^ @@ -505,14 +128,11 @@ b. Change Major number msterm. These 3 utilities are released in form of source code. They should be compiled into executable file and copied into /usr/bin. - Before using these utilities, please load driver (refer 3.4 & 3.5) and - make sure you had run the "msmknod" utility. - msdiag - Diagnostic =================== This utility provides the function to display what Moxa Smartio/Industio - board found by driver in the system. + board was found by the driver in the system. msmon - Port Monitoring ======================= @@ -542,23 +162,23 @@ msterm - Terminal Emulation Supported Setserial parameters are listed as below. - ============== ========================================================= - uart set UART type(16450-->disable FIFO, 16550A-->enable FIFO) - close_delay set the amount of time(in 1/100 of a second) that DTR + ============== ============================================================= + uart set UART type(16450 --> disable FIFO, 16550A --> enable FIFO) + close_delay set the amount of time (in 1/100 of a second) that DTR should be kept low while being closed. - closing_wait set the amount of time(in 1/100 of a second) that the + closing_wait set the amount of time (in 1/100 of a second) that the serial port should wait for data to be drained while - being closed, before the receiver is disable. - spd_hi Use 57.6kb when the application requests 38.4kb. - spd_vhi Use 115.2kb when the application requests 38.4kb. - spd_shi Use 230.4kb when the application requests 38.4kb. - spd_warp Use 460.8kb when the application requests 38.4kb. - spd_normal Use 38.4kb when the application requests 38.4kb. - spd_cust Use the custom divisor to set the speed when the + being closed, before the receiver is disabled. + spd_hi Use 57.6kb when the application requests 38.4kb. + spd_vhi Use 115.2kb when the application requests 38.4kb. + spd_shi Use 230.4kb when the application requests 38.4kb. + spd_warp Use 460.8kb when the application requests 38.4kb. + spd_normal Use 38.4kb when the application requests 38.4kb. + spd_cust Use the custom divisor to set the speed when the application requests 38.4kb. - divisor This option set the custom division. - baud_base This option set the base baud rate. - ============== ========================================================= + divisor This option sets the custom division. + baud_base This option sets the base baud rate. + ============== ============================================================= 6. Troubleshooting ^^^^^^^^^^^^^^^^^^ @@ -575,41 +195,3 @@ msterm - Terminal Emulation Solution: To avoid this problem, please unplug fifth and after board, because Moxa driver supports up to 4 boards. - - Error msg: - Request_irq fail, IRQ(?) may be conflict with another device. - - Solution: - Other PCI or ISA devices occupy the assigned IRQ. If you are not sure - which device causes the situation, please check /proc/interrupts to find - free IRQ and simply change another free IRQ for Moxa board. - - Error msg: - Board #: C1xx Series(CAP=xxx) interrupt number invalid. - - Solution: - Each port within the same multiport board shares the same IRQ. Please set - one IRQ (IRQ doesn't equal to zero) for one Moxa board. - - Error msg: - No interrupt vector be set for Moxa ISA board(CAP=xxx). - - Solution: - Moxa ISA board needs an interrupt vector.Please refer to user's manual - "Hardware Installation" chapter to set interrupt vector. - - Error msg: - Couldn't install MOXA Smartio/Industio family driver! - - Solution: - Load Moxa driver fail, the major number may conflict with other devices. - Please refer to previous section 3.7 to change a free major number for - Moxa driver. - - Error msg: - Couldn't install MOXA Smartio/Industio family callout driver! - - Solution: - Load Moxa callout driver fail, the callout device major number may - conflict with other devices. Please refer to previous section 3.7 to - change a free callout device major number for Moxa driver. diff --git a/Documentation/driver-api/usb/error-codes.rst b/Documentation/driver-api/usb/error-codes.rst index a3e84bfac776..8f9790c2d6f8 100644 --- a/Documentation/driver-api/usb/error-codes.rst +++ b/Documentation/driver-api/usb/error-codes.rst @@ -61,6 +61,9 @@ USB-specific: (c) requested data transfer length is invalid: negative or too large for the host controller. +``-EBADR`` The wLength value in a control URB's setup packet does + not match the URB's transfer_buffer_length. + ``-ENOSPC`` This request would overcommit the usb bandwidth reserved for periodic transfers (interrupt, isochronous). diff --git a/Documentation/driver-api/vfio-mediated-device.rst b/Documentation/driver-api/vfio-mediated-device.rst index 1779b85f014e..9f26079cacae 100644 --- a/Documentation/driver-api/vfio-mediated-device.rst +++ b/Documentation/driver-api/vfio-mediated-device.rst @@ -93,7 +93,7 @@ interfaces: Registration Interface for a Mediated Bus Driver ------------------------------------------------ -The registration interface for a mediated bus driver provides the following +The registration interface for a mediated device driver provides the following structure to represent a mediated device's driver:: /* @@ -136,37 +136,26 @@ The structures in the mdev_parent_ops structure are as follows: * dev_attr_groups: attributes of the parent device * mdev_attr_groups: attributes of the mediated device * supported_config: attributes to define supported configurations +* device_driver: device driver to bind for mediated device instances -The functions in the mdev_parent_ops structure are as follows: +The mdev_parent_ops also still has various functions pointers. Theses exist +for historical reasons only and shall not be used for new drivers. -* create: allocate basic resources in a driver for a mediated device -* remove: free resources in a driver when a mediated device is destroyed - -(Note that mdev-core provides no implicit serialization of create/remove -callbacks per mdev parent device, per mdev type, or any other categorization. -Vendor drivers are expected to be fully asynchronous in this respect or -provide their own internal resource protection.) - -The callbacks in the mdev_parent_ops structure are as follows: - -* open: open callback of mediated device -* close: close callback of mediated device -* ioctl: ioctl callback of mediated device -* read : read emulation callback -* write: write emulation callback -* mmap: mmap emulation callback - -A driver should use the mdev_parent_ops structure in the function call to -register itself with the mdev core driver:: +When a driver wants to add the GUID creation sysfs to an existing device it has +probe'd to then it should call:: extern int mdev_register_device(struct device *dev, const struct mdev_parent_ops *ops); -However, the mdev_parent_ops structure is not required in the function call -that a driver should use to unregister itself with the mdev core driver:: +This will provide the 'mdev_supported_types/XX/create' files which can then be +used to trigger the creation of a mdev_device. The created mdev_device will be +attached to the specified driver. + +When the driver needs to remove itself it calls:: extern void mdev_unregister_device(struct device *dev); +Which will unbind and destroy all the created mdevs and remove the sysfs files. Mediated Device Management Interface Through sysfs ================================================== diff --git a/Documentation/filesystems/debugfs.rst b/Documentation/filesystems/debugfs.rst index 0f2292e367e6..71b1fee56d2a 100644 --- a/Documentation/filesystems/debugfs.rst +++ b/Documentation/filesystems/debugfs.rst @@ -120,8 +120,8 @@ and hexadecimal:: Boolean values can be placed in debugfs with:: - struct dentry *debugfs_create_bool(const char *name, umode_t mode, - struct dentry *parent, bool *value); + void debugfs_create_bool(const char *name, umode_t mode, + struct dentry *parent, bool *value); A read on the resulting file will yield either Y (for non-zero values) or N, followed by a newline. If written to, it will accept either upper- or diff --git a/Documentation/filesystems/path-lookup.rst b/Documentation/filesystems/path-lookup.rst index a6fa7619b69e..2b2df6aa5432 100644 --- a/Documentation/filesystems/path-lookup.rst +++ b/Documentation/filesystems/path-lookup.rst @@ -1297,18 +1297,18 @@ to lookup: RCU-walk, REF-walk, and REF-walk with forced revalidation. yet. This is primarily used to tell the audit subsystem the full context of a particular access being audited. -``LOOKUP_ROOT`` indicates that the ``root`` field in the ``nameidata`` was +``ND_ROOT_PRESET`` indicates that the ``root`` field in the ``nameidata`` was provided by the caller, so it shouldn't be released when it is no longer needed. -``LOOKUP_JUMPED`` means that the current dentry was chosen not because +``ND_JUMPED`` means that the current dentry was chosen not because it had the right name but for some other reason. This happens when following "``..``", following a symlink to ``/``, crossing a mount point or accessing a "``/proc/$PID/fd/$FD``" symlink (also known as a "magic link"). In this case the filesystem has not been asked to revalidate the name (with ``d_revalidate()``). In such cases the inode may still need to be revalidated, so ``d_op->d_weak_revalidate()`` is called if -``LOOKUP_JUMPED`` is set when the look completes - which may be at the +``ND_JUMPED`` is set when the look completes - which may be at the final component or, when creating, unlinking, or renaming, at the penultimate component. Resolution-restriction flags diff --git a/Documentation/filesystems/porting.rst b/Documentation/filesystems/porting.rst index 0302035781be..bf19fd6b86e7 100644 --- a/Documentation/filesystems/porting.rst +++ b/Documentation/filesystems/porting.rst @@ -890,3 +890,21 @@ been called or returned with non -EIOCBQUEUED code. mnt_want_write_file() can now only be paired with mnt_drop_write_file(), whereas previously it could be paired with mnt_drop_write() as well. + +--- + +**mandatory** + +iov_iter_copy_from_user_atomic() is gone; use copy_page_from_iter_atomic(). +The difference is copy_page_from_iter_atomic() advances the iterator and +you don't need iov_iter_advance() after it. However, if you decide to use +only a part of obtained data, you should do iov_iter_revert(). + +--- + +**mandatory** + +Calling conventions for file_open_root() changed; now it takes struct path * +instead of passing mount and dentry separately. For callers that used to +pass mnt_root> pair (i.e. the root of given mount), a new helper +is provided - file_open_root_mnt(). In-tree users adjusted. diff --git a/Documentation/filesystems/proc.rst b/Documentation/filesystems/proc.rst index c1e5efa60f76..38a951bad741 100644 --- a/Documentation/filesystems/proc.rst +++ b/Documentation/filesystems/proc.rst @@ -939,8 +939,15 @@ meminfo ~~~~~~~ Provides information about distribution and utilization of memory. This -varies by architecture and compile options. The following is from a -16GB PIII, which has highmem enabled. You may not have all of these fields. +varies by architecture and compile options. Some of the counters reported +here overlap. The memory reported by the non overlapping counters may not +add up to the overall memory usage and the difference for some workloads +can be substantial. In many cases there are other means to find out +additional memory using subsystem specific interfaces, for instance +/proc/net/sockstat for TCP memory allocations. + +The following is from a 16GB PIII, which has highmem enabled. +You may not have all of these fields. :: @@ -1919,18 +1926,20 @@ if precise results are needed. 3.8 /proc//fdinfo/ - Information about opened file --------------------------------------------------------------- This file provides information associated with an opened file. The regular -files have at least three fields -- 'pos', 'flags' and 'mnt_id'. The 'pos' -represents the current offset of the opened file in decimal form [see lseek(2) -for details], 'flags' denotes the octal O_xxx mask the file has been -created with [see open(2) for details] and 'mnt_id' represents mount ID of -the file system containing the opened file [see 3.5 /proc//mountinfo -for details]. +files have at least four fields -- 'pos', 'flags', 'mnt_id' and 'ino'. +The 'pos' represents the current offset of the opened file in decimal +form [see lseek(2) for details], 'flags' denotes the octal O_xxx mask the +file has been created with [see open(2) for details] and 'mnt_id' represents +mount ID of the file system containing the opened file [see 3.5 +/proc//mountinfo for details]. 'ino' represents the inode number of +the file. A typical output is:: pos: 0 flags: 0100002 mnt_id: 19 + ino: 63107 All locks associated with a file descriptor are shown in its fdinfo too:: @@ -1947,6 +1956,7 @@ Eventfd files pos: 0 flags: 04002 mnt_id: 9 + ino: 63107 eventfd-count: 5a where 'eventfd-count' is hex value of a counter. @@ -1959,6 +1969,7 @@ Signalfd files pos: 0 flags: 04002 mnt_id: 9 + ino: 63107 sigmask: 0000000000000200 where 'sigmask' is hex value of the signal mask associated @@ -1972,6 +1983,7 @@ Epoll files pos: 0 flags: 02 mnt_id: 9 + ino: 63107 tfd: 5 events: 1d data: ffffffffffffffff pos:0 ino:61af sdev:7 where 'tfd' is a target file descriptor number in decimal form, @@ -1988,6 +2000,8 @@ For inotify files the format is the following:: pos: 0 flags: 02000000 + mnt_id: 9 + ino: 63107 inotify wd:3 ino:9e7e sdev:800013 mask:800afce ignored_mask:0 fhandle-bytes:8 fhandle-type:1 f_handle:7e9e0000640d1b6d where 'wd' is a watch descriptor in decimal form, i.e. a target file @@ -2010,6 +2024,7 @@ For fanotify files the format is:: pos: 0 flags: 02 mnt_id: 9 + ino: 63107 fanotify flags:10 event-flags:0 fanotify mnt_id:12 mflags:40 mask:38 ignored_mask:40000003 fanotify ino:4f969 sdev:800013 mflags:0 mask:3b ignored_mask:40000000 fhandle-bytes:8 fhandle-type:1 f_handle:69f90400c275b5b4 @@ -2034,6 +2049,7 @@ Timerfd files pos: 0 flags: 02 mnt_id: 9 + ino: 63107 clockid: 0 ticks: 0 settime flags: 01 @@ -2048,6 +2064,22 @@ details]. 'it_value' is remaining time until the timer expiration. with TIMER_ABSTIME option which will be shown in 'settime flags', but 'it_value' still exhibits timer's remaining time. +DMA Buffer files +~~~~~~~~~~~~~~~~ + +:: + + pos: 0 + flags: 04002 + mnt_id: 9 + ino: 63107 + size: 32768 + count: 2 + exp_name: system-heap + +where 'size' is the size of the DMA buffer in bytes. 'count' is the file count of +the DMA buffer file. 'exp_name' is the name of the DMA buffer exporter. + 3.9 /proc//map_files - Information about memory mapped files --------------------------------------------------------------------- This directory contains symbolic links which represent memory mapped files diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index f3a1223f2517..75df90d1e54c 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -57,7 +57,7 @@ FPGA Interface Unit (FIU) represents a standalone functional unit for the interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more descriptions on FME and Port in later sections). -Accelerated Function Unit (AFU) represents a FPGA programmable region and +Accelerated Function Unit (AFU) represents an FPGA programmable region and always connects to a FIU (e.g. a Port) as its child as illustrated above. Private Features represent sub features of the FIU and AFU. They could be @@ -311,7 +311,7 @@ The driver organization in virtualization case is illustrated below: | PCI PF Device | | | PCI VF Device | +---------------+ | +---------------+ -FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device +FPGA PCIe device driver is always loaded first once an FPGA PCIe PF or VF device is detected. It: * Finishes enumeration on both FPGA PCIe PF and VF device using common diff --git a/Documentation/gpu/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc.rst index cc89b0fc11df..f7ff7e1309de 100644 --- a/Documentation/gpu/amdgpu-dc.rst +++ b/Documentation/gpu/amdgpu-dc.rst @@ -66,3 +66,9 @@ Display Core ============ **WIP** + +FreeSync Video +-------------- + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :doc: FreeSync Video diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst index 2062a6023678..364680cdad2e 100644 --- a/Documentation/gpu/amdgpu.rst +++ b/Documentation/gpu/amdgpu.rst @@ -300,4 +300,25 @@ pcie_replay_count .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c :doc: pcie_replay_count ++GPU SmartShift Information +============================ +GPU SmartShift information via sysfs + +smartshift_apu_power +-------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c + :doc: smartshift_apu_power + +smartshift_dgpu_power +--------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c + :doc: smartshift_dgpu_power + +smartshift_bias +--------------- + +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c + :doc: smartshift_bias diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst new file mode 100644 index 000000000000..4411e6919a3d --- /dev/null +++ b/Documentation/gpu/driver-uapi.rst @@ -0,0 +1,8 @@ +=============== +DRM Driver uAPI +=============== + +drm/i915 uAPI +============= + +.. kernel-doc:: include/uapi/drm/i915_drm.h diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst index 12272b168580..06af044c882f 100644 --- a/Documentation/gpu/drm-internals.rst +++ b/Documentation/gpu/drm-internals.rst @@ -75,6 +75,18 @@ update it, its value is mostly useless. The DRM core prints it to the kernel log at initialization time and passes it to userspace through the DRM_IOCTL_VERSION ioctl. +Managing Ownership of the Framebuffer Aperture +---------------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_aperture.c + :doc: overview + +.. kernel-doc:: include/drm/drm_aperture.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_aperture.c + :export: + Device Instance and Driver Handling ----------------------------------- diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index 21be6deadc12..d5a73fa2c9ef 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -469,8 +469,8 @@ DRM MM Range Allocator Function References .. kernel-doc:: drivers/gpu/drm/drm_mm.c :export: -DRM Cache Handling -================== +DRM Cache Handling and Fast WC memcpy() +======================================= .. kernel-doc:: drivers/gpu/drm/drm_cache.c :export: diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 486c720f3890..42ce0196930a 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -210,13 +210,13 @@ DPIO .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c :doc: DPIO -CSR firmware support for DMC ----------------------------- +DMC Firmware Support +-------------------- -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c - :doc: csr support for dmc +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :doc: DMC Firmware Support -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c :internal: Video BIOS Table (VBT) @@ -537,7 +537,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ DMC --- -See `CSR firmware support for DMC`_ +See `DMC Firmware Support`_ Tracing ======= diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst index ec4bc72438e4..b9c1214d8f23 100644 --- a/Documentation/gpu/index.rst +++ b/Documentation/gpu/index.rst @@ -10,6 +10,7 @@ Linux GPU Driver Developer's Guide drm-kms drm-kms-helpers drm-uapi + driver-uapi drm-client drivers backlight diff --git a/Documentation/gpu/rfc/i915_gem_lmem.rst b/Documentation/gpu/rfc/i915_gem_lmem.rst new file mode 100644 index 000000000000..675ba8620d66 --- /dev/null +++ b/Documentation/gpu/rfc/i915_gem_lmem.rst @@ -0,0 +1,131 @@ +========================= +I915 DG1/LMEM RFC Section +========================= + +Upstream plan +============= +For upstream the overall plan for landing all the DG1 stuff and turning it for +real, with all the uAPI bits is: + +* Merge basic HW enabling of DG1(still without pciid) +* Merge the uAPI bits behind special CONFIG_BROKEN(or so) flag + * At this point we can still make changes, but importantly this lets us + start running IGTs which can utilize local-memory in CI +* Convert over to TTM, make sure it all keeps working. Some of the work items: + * TTM shrinker for discrete + * dma_resv_lockitem for full dma_resv_lock, i.e not just trylock + * Use TTM CPU pagefault handler + * Route shmem backend over to TTM SYSTEM for discrete + * TTM purgeable object support + * Move i915 buddy allocator over to TTM + * MMAP ioctl mode(see `I915 MMAP`_) + * SET/GET ioctl caching(see `I915 SET/GET CACHING`_) +* Send RFC(with mesa-dev on cc) for final sign off on the uAPI +* Add pciid for DG1 and turn on uAPI for real + +New object placement and region query uAPI +========================================== +Starting from DG1 we need to give userspace the ability to allocate buffers from +device local-memory. Currently the driver supports gem_create, which can place +buffers in system memory via shmem, and the usual assortment of other +interfaces, like dumb buffers and userptr. + +To support this new capability, while also providing a uAPI which will work +beyond just DG1, we propose to offer three new bits of uAPI: + +DRM_I915_QUERY_MEMORY_REGIONS +----------------------------- +New query ID which allows userspace to discover the list of supported memory +regions(like system-memory and local-memory) for a given device. We identify +each region with a class and instance pair, which should be unique. The class +here would be DEVICE or SYSTEM, and the instance would be zero, on platforms +like DG1. + +Side note: The class/instance design is borrowed from our existing engine uAPI, +where we describe every physical engine in terms of its class, and the +particular instance, since we can have more than one per class. + +In the future we also want to expose more information which can further +describe the capabilities of a region. + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions + +GEM_CREATE_EXT +-------------- +New ioctl which is basically just gem_create but now allows userspace to provide +a chain of possible extensions. Note that if we don't provide any extensions and +set flags=0 then we get the exact same behaviour as gem_create. + +Side note: We also need to support PXP[1] in the near future, which is also +applicable to integrated platforms, and adds its own gem_create_ext extension, +which basically lets userspace mark a buffer as "protected". + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :functions: drm_i915_gem_create_ext + +I915_GEM_CREATE_EXT_MEMORY_REGIONS +---------------------------------- +Implemented as an extension for gem_create_ext, we would now allow userspace to +optionally provide an immutable list of preferred placements at creation time, +in priority order, for a given buffer object. For the placements we expect +them each to use the class/instance encoding, as per the output of the regions +query. Having the list in priority order will be useful in the future when +placing an object, say during eviction. + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :functions: drm_i915_gem_create_ext_memory_regions + +One fair criticism here is that this seems a little over-engineered[2]. If we +just consider DG1 then yes, a simple gem_create.flags or something is totally +all that's needed to tell the kernel to allocate the buffer in local-memory or +whatever. However looking to the future we need uAPI which can also support +upcoming Xe HP multi-tile architecture in a sane way, where there can be +multiple local-memory instances for a given device, and so using both class and +instance in our uAPI to describe regions is desirable, although specifically +for DG1 it's uninteresting, since we only have a single local-memory instance. + +Existing uAPI issues +==================== +Some potential issues we still need to resolve. + +I915 MMAP +--------- +In i915 there are multiple ways to MMAP GEM object, including mapping the same +object using different mapping types(WC vs WB), i.e multiple active mmaps per +object. TTM expects one MMAP at most for the lifetime of the object. If it +turns out that we have to backpedal here, there might be some potential +userspace fallout. + +I915 SET/GET CACHING +-------------------- +In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but +DG1 doesn't support non-snooped pcie transactions, so we can just always +allocate as WB for smem-only buffers. If/when our hw gains support for +non-snooped pcie transactions then we must fix this mode at allocation time as +a new GEM extension. + +This is related to the mmap problem, because in general (meaning, when we're +not running on intel cpus) the cpu mmap must not, ever, be inconsistent with +allocation mode. + +Possible idea is to let the kernel picks the mmap mode for userspace from the +following table: + +smem-only: WB. Userspace does not need to call clflush. + +smem+lmem: We only ever allow a single mode, so simply allocate this as uncached +memory, and always give userspace a WC mapping. GPU still does snooped access +here(assuming we can't turn it off like on DG1), which is a bit inefficient. + +lmem only: always WC + +This means on discrete you only get a single mmap mode, all others must be +rejected. That's probably going to be a new default mode or something like +that. + +Links +===== +[1] https://patchwork.freedesktop.org/series/86798/ + +[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791 diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index a8621f7dab8b..05670442ca1b 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -15,3 +15,7 @@ host such documentation: * Once the code has landed move all the documentation to the right places in the main core, helper or driver sections. + +.. toctree:: + + i915_gem_lmem.rst diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 7ff9fac10d8b..12e61869939e 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -546,6 +546,8 @@ There's a bunch of issues with it: this (together with the drm_minor->drm_device move) would allow us to remove debugfs_init. +Previous RFC that hasn't landed yet: https://lore.kernel.org/dri-devel/20200513114130.28641-2-wambui.karugax@gmail.com/ + Contact: Daniel Vetter Level: Intermediate diff --git a/Documentation/i2c/i2c-sysfs.rst b/Documentation/i2c/i2c-sysfs.rst new file mode 100644 index 000000000000..6b68b95cd427 --- /dev/null +++ b/Documentation/i2c/i2c-sysfs.rst @@ -0,0 +1,395 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============== +Linux I2C Sysfs +=============== + +Overview +======== + +I2C topology can be complex because of the existence of I2C MUX +(I2C Multiplexer). The Linux +kernel abstracts the MUX channels into logical I2C bus numbers. However, there +is a gap of knowledge to map from the I2C bus physical number and MUX topology +to logical I2C bus number. This doc is aimed to fill in this gap, so the +audience (hardware engineers and new software developers for example) can learn +the concept of logical I2C buses in the kernel, by knowing the physical I2C +topology and navigating through the I2C sysfs in Linux shell. This knowledge is +useful and essential to use ``i2c-tools`` for the purpose of development and +debugging. + +Target audience +--------------- + +People who need to use Linux shell to interact with I2C subsystem on a system +which the Linux is running on. + +Prerequisites +------------- + +1. Knowledge of general Linux shell file system commands and operations. + +2. General knowledge of I2C, I2C MUX and I2C topology. + +Location of I2C Sysfs +===================== + +Typically, the Linux Sysfs filesystem is mounted at the ``/sys`` directory, +so you can find the I2C Sysfs under ``/sys/bus/i2c/devices`` +where you can directly ``cd`` to it. +There is a list of symbolic links under that directory. The links that +start with ``i2c-`` are I2C buses, which may be either physical or logical. The +other links that begin with numbers and end with numbers are I2C devices, where +the first number is I2C bus number, and the second number is I2C address. + +Google Pixel 3 phone for example:: + + blueline:/sys/bus/i2c/devices $ ls + 0-0008 0-0061 1-0028 3-0043 4-0036 4-0041 i2c-1 i2c-3 + 0-000c 0-0066 2-0049 4-000b 4-0040 i2c-0 i2c-2 i2c-4 + +``i2c-2`` is an I2C bus whose number is 2, and ``2-0049`` is an I2C device +on bus 2 address 0x49 bound with a kernel driver. + +Terminologies +============= + +First, let us define a couple of terminologies to avoid confusions in the later +sections. + +(Physical) I2C Bus Controller +----------------------------- + +The hardware system that the Linux kernel is running on may have multiple +physical I2C bus controllers. The controllers are hardware and physical, and the +system may define multiple registers in the memory space to manipulate the +controllers. Linux kernel has I2C bus drivers under source directory +``drivers/i2c/busses`` to translate kernel I2C API into register +operations for different systems. This terminology is not limited to Linux +kernel only. + +I2C Bus Physical Number +----------------------- + +For each physical I2C bus controller, the system vendor may assign a physical +number to each controller. For example, the first I2C bus controller which has +the lowest register addresses may be called ``I2C-0``. + +Logical I2C Bus +--------------- + +Every I2C bus number you see in Linux I2C Sysfs is a logical I2C bus with a +number assigned. This is similar to the fact that software code is usually +written upon virtual memory space, instead of physical memory space. + +Each logical I2C bus may be an abstraction of a physical I2C bus controller, or +an abstraction of a channel behind an I2C MUX. In case it is an abstraction of a +MUX channel, whenever we access an I2C device via a such logical bus, the kernel +will switch the I2C MUX for you to the proper channel as part of the +abstraction. + +Physical I2C Bus +---------------- + +If the logical I2C bus is a direct abstraction of a physical I2C bus controller, +let us call it a physical I2C bus. + +Caveat +------ + +This may be a confusing part for people who only know about the physical I2C +design of a board. It is actually possible to rename the I2C bus physical number +to a different number in logical I2C bus level in Device Tree Source (DTS) under +section ``aliases``. See +`arch/arm/boot/dts/nuvoton-npcm730-gsj.dts +<../../arch/arm/boot/dts/nuvoton-npcm730-gsj.dts>`_ +for an example of DTS file. + +Best Practice: **(To kernel software developers)** It is better to keep the I2C +bus physical number the same as their corresponding logical I2C bus number, +instead of renaming or mapping them, so that it may be less confusing to other +users. These physical I2C buses can be served as good starting points for I2C +MUX fanouts. For the following examples, we will assume that the physical I2C +bus has a number same as their I2C bus physical number. + +Walk through Logical I2C Bus +============================ + +For the following content, we will use a more complex I2C topology as an +example. Here is a brief graph for the I2C topology. If you do not understand +this graph at the first glance, do not be afraid to continue reading this doc +and review it when you finish reading. + +:: + + i2c-7 (physical I2C bus controller 7) + `-- 7-0071 (4-channel I2C MUX at 0x71) + |-- i2c-60 (channel-0) + |-- i2c-73 (channel-1) + | |-- 73-0040 (I2C sensor device with hwmon directory) + | |-- 73-0070 (I2C MUX at 0x70, exists in DTS, but failed to probe) + | `-- 73-0072 (8-channel I2C MUX at 0x72) + | |-- i2c-78 (channel-0) + | |-- ... (channel-1...6, i2c-79...i2c-84) + | `-- i2c-85 (channel-7) + |-- i2c-86 (channel-2) + `-- i2c-203 (channel-3) + +Distinguish Physical and Logical I2C Bus +---------------------------------------- + +One simple way to distinguish between a physical I2C bus and a logical I2C bus, +is to read the symbolic link ``device`` under the I2C bus directory by using +command ``ls -l`` or ``readlink``. + +An alternative symbolic link to check is ``mux_device``. This link only exists +in logical I2C bus directory which is fanned out from another I2C bus. +Reading this link will also tell you which I2C MUX device created +this logical I2C bus. + +If the symbolic link points to a directory ending with ``.i2c``, it should be a +physical I2C bus, directly abstracting a physical I2C bus controller. For +example:: + + $ readlink /sys/bus/i2c/devices/i2c-7/device + ../../f0087000.i2c + $ ls /sys/bus/i2c/devices/i2c-7/mux_device + ls: /sys/bus/i2c/devices/i2c-7/mux_device: No such file or directory + +In this case, ``i2c-7`` is a physical I2C bus, so it does not have the symbolic +link ``mux_device`` under its directory. And if the kernel software developer +follows the common practice by not renaming physical I2C buses, this should also +mean the physical I2C bus controller 7 of the system. + +On the other hand, if the symbolic link points to another I2C bus, the I2C bus +presented by the current directory has to be a logical bus. The I2C bus pointed +by the link is the parent bus which may be either a physical I2C bus or a +logical one. In this case, the I2C bus presented by the current directory +abstracts an I2C MUX channel under the parent bus. + +For example:: + + $ readlink /sys/bus/i2c/devices/i2c-73/device + ../../i2c-7 + $ readlink /sys/bus/i2c/devices/i2c-73/mux_device + ../7-0071 + +``i2c-73`` is a logical bus fanout by an I2C MUX under ``i2c-7`` +whose I2C address is 0x71. +Whenever we access an I2C device with bus 73, the kernel will always +switch the I2C MUX addressed 0x71 to the proper channel for you as part of the +abstraction. + +Finding out Logical I2C Bus Number +---------------------------------- + +In this section, we will describe how to find out the logical I2C bus number +representing certain I2C MUX channels based on the knowledge of physical +hardware I2C topology. + +In this example, we have a system which has a physical I2C bus 7 and not renamed +in DTS. There is a 4-channel MUX at address 0x71 on that bus. There is another +8-channel MUX at address 0x72 behind the channel 1 of the 0x71 MUX. Let us +navigate through Sysfs and find out the logical I2C bus number of the channel 3 +of the 0x72 MUX. + +First of all, let us go to the directory of ``i2c-7``:: + + ~$ cd /sys/bus/i2c/devices/i2c-7 + /sys/bus/i2c/devices/i2c-7$ ls + 7-0071 i2c-60 name subsystem + delete_device i2c-73 new_device uevent + device i2c-86 of_node + i2c-203 i2c-dev power + +There, we see the 0x71 MUX as ``7-0071``. Go inside it:: + + /sys/bus/i2c/devices/i2c-7$ cd 7-0071/ + /sys/bus/i2c/devices/i2c-7/7-0071$ ls -l + channel-0 channel-3 modalias power + channel-1 driver name subsystem + channel-2 idle_state of_node uevent + +Read the link ``channel-1`` using ``readlink`` or ``ls -l``:: + + /sys/bus/i2c/devices/i2c-7/7-0071$ readlink channel-1 + ../i2c-73 + +We find out that the channel 1 of 0x71 MUX on ``i2c-7`` is assigned +with a logical I2C bus number of 73. +Let us continue the journey to directory ``i2c-73`` in either ways:: + + # cd to i2c-73 under I2C Sysfs root + /sys/bus/i2c/devices/i2c-7/7-0071$ cd /sys/bus/i2c/devices/i2c-73 + /sys/bus/i2c/devices/i2c-73$ + + # cd the channel symbolic link + /sys/bus/i2c/devices/i2c-7/7-0071$ cd channel-1 + /sys/bus/i2c/devices/i2c-7/7-0071/channel-1$ + + # cd the link content + /sys/bus/i2c/devices/i2c-7/7-0071$ cd ../i2c-73 + /sys/bus/i2c/devices/i2c-7/i2c-73$ + +Either ways, you will end up in the directory of ``i2c-73``. Similar to above, +we can now find the 0x72 MUX and what logical I2C bus numbers +that its channels are assigned:: + + /sys/bus/i2c/devices/i2c-73$ ls + 73-0040 device i2c-83 new_device + 73-004e i2c-78 i2c-84 of_node + 73-0050 i2c-79 i2c-85 power + 73-0070 i2c-80 i2c-dev subsystem + 73-0072 i2c-81 mux_device uevent + delete_device i2c-82 name + /sys/bus/i2c/devices/i2c-73$ cd 73-0072 + /sys/bus/i2c/devices/i2c-73/73-0072$ ls + channel-0 channel-4 driver of_node + channel-1 channel-5 idle_state power + channel-2 channel-6 modalias subsystem + channel-3 channel-7 name uevent + /sys/bus/i2c/devices/i2c-73/73-0072$ readlink channel-3 + ../i2c-81 + +There, we find out the logical I2C bus number of the channel 3 of the 0x72 MUX +is 81. We can later use this number to switch to its own I2C Sysfs directory or +issue ``i2c-tools`` commands. + +Tip: Once you understand the I2C topology with MUX, command +`i2cdetect -l +`_ +in +`I2C Tools +`_ +can give you +an overview of the I2C topology easily, if it is available on your system. For +example:: + + $ i2cdetect -l | grep -e '\-73' -e _7 | sort -V + i2c-7 i2c npcm_i2c_7 I2C adapter + i2c-73 i2c i2c-7-mux (chan_id 1) I2C adapter + i2c-78 i2c i2c-73-mux (chan_id 0) I2C adapter + i2c-79 i2c i2c-73-mux (chan_id 1) I2C adapter + i2c-80 i2c i2c-73-mux (chan_id 2) I2C adapter + i2c-81 i2c i2c-73-mux (chan_id 3) I2C adapter + i2c-82 i2c i2c-73-mux (chan_id 4) I2C adapter + i2c-83 i2c i2c-73-mux (chan_id 5) I2C adapter + i2c-84 i2c i2c-73-mux (chan_id 6) I2C adapter + i2c-85 i2c i2c-73-mux (chan_id 7) I2C adapter + +Pinned Logical I2C Bus Number +----------------------------- + +If not specified in DTS, when an I2C MUX driver is applied and the MUX device is +successfully probed, the kernel will assign the MUX channels with a logical bus +number based on the current biggest logical bus number incrementally. For +example, if the system has ``i2c-15`` as the highest logical bus number, and a +4-channel MUX is applied successfully, we will have ``i2c-16`` for the +MUX channel 0, and all the way to ``i2c-19`` for the MUX channel 3. + +The kernel software developer is able to pin the fanout MUX channels to a static +logical I2C bus number in the DTS. This doc will not go through the details on +how to implement this in DTS, but we can see an example in: +`arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts +<../../arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts>`_ + +In the above example, there is an 8-channel I2C MUX at address 0x70 on physical +I2C bus 2. The channel 2 of the MUX is defined as ``imux18`` in DTS, +and pinned to logical I2C bus number 18 with the line of ``i2c18 = &imux18;`` +in section ``aliases``. + +Take it further, it is possible to design a logical I2C bus number schema that +can be easily remembered by humans or calculated arithmetically. For example, we +can pin the fanout channels of a MUX on bus 3 to start at 30. So 30 will be the +logical bus number of the channel 0 of the MUX on bus 3, and 37 will be the +logical bus number of the channel 7 of the MUX on bus 3. + +I2C Devices +=========== + +In previous sections, we mostly covered the I2C bus. In this section, let us see +what we can learn from the I2C device directory whose link name is in the format +of ``${bus}-${addr}``. The ``${bus}`` part in the name is a logical I2C bus +decimal number, while the ``${addr}`` part is a hex number of the I2C address +of each device. + +I2C Device Directory Content +---------------------------- + +Inside each I2C device directory, there is a file named ``name``. +This file tells what device name it was used for the kernel driver to +probe this device. Use command ``cat`` to read its content. For example:: + + /sys/bus/i2c/devices/i2c-73$ cat 73-0040/name + ina230 + /sys/bus/i2c/devices/i2c-73$ cat 73-0070/name + pca9546 + /sys/bus/i2c/devices/i2c-73$ cat 73-0072/name + pca9547 + +There is a symbolic link named ``driver`` to tell what Linux kernel driver was +used to probe this device:: + + /sys/bus/i2c/devices/i2c-73$ readlink -f 73-0040/driver + /sys/bus/i2c/drivers/ina2xx + /sys/bus/i2c/devices/i2c-73$ readlink -f 73-0072/driver + /sys/bus/i2c/drivers/pca954x + +But if the link ``driver`` does not exist at the first place, +it may mean that the kernel driver failed to probe this device due to +some errors. The error may be found in ``dmesg``:: + + /sys/bus/i2c/devices/i2c-73$ ls 73-0070/driver + ls: 73-0070/driver: No such file or directory + /sys/bus/i2c/devices/i2c-73$ dmesg | grep 73-0070 + pca954x 73-0070: probe failed + pca954x 73-0070: probe failed + +Depending on what the I2C device is and what kernel driver was used to probe the +device, we may have different content in the device directory. + +I2C MUX Device +-------------- + +While you may be already aware of this in previous sections, an I2C MUX device +will have symbolic link ``channel-*`` inside its device directory. +These symbolic links point to their logical I2C bus directories:: + + /sys/bus/i2c/devices/i2c-73$ ls -l 73-0072/channel-* + lrwxrwxrwx ... 73-0072/channel-0 -> ../i2c-78 + lrwxrwxrwx ... 73-0072/channel-1 -> ../i2c-79 + lrwxrwxrwx ... 73-0072/channel-2 -> ../i2c-80 + lrwxrwxrwx ... 73-0072/channel-3 -> ../i2c-81 + lrwxrwxrwx ... 73-0072/channel-4 -> ../i2c-82 + lrwxrwxrwx ... 73-0072/channel-5 -> ../i2c-83 + lrwxrwxrwx ... 73-0072/channel-6 -> ../i2c-84 + lrwxrwxrwx ... 73-0072/channel-7 -> ../i2c-85 + +I2C Sensor Device / Hwmon +------------------------- + +I2C sensor device is also common to see. If they are bound by a kernel hwmon +(Hardware Monitoring) driver successfully, you will see a ``hwmon`` directory +inside the I2C device directory. Keep digging into it, you will find the Hwmon +Sysfs for the I2C sensor device:: + + /sys/bus/i2c/devices/i2c-73/73-0040/hwmon/hwmon17$ ls + curr1_input in0_lcrit_alarm name subsystem + device in1_crit power uevent + in0_crit in1_crit_alarm power1_crit update_interval + in0_crit_alarm in1_input power1_crit_alarm + in0_input in1_lcrit power1_input + in0_lcrit in1_lcrit_alarm shunt_resistor + +For more info on the Hwmon Sysfs, refer to the doc: + +`Naming and data format standards for sysfs files +<../hwmon/sysfs-interface.rst>`_ + +Instantiate I2C Devices in I2C Sysfs +------------------------------------ + +Refer to the doc: + +`How to instantiate I2C devices, Method 4: Instantiate from user-space +`_ diff --git a/Documentation/networking/caif/caif.rst b/Documentation/networking/caif/caif.rst index 81a14373d780..d922d419c513 100644 --- a/Documentation/networking/caif/caif.rst +++ b/Documentation/networking/caif/caif.rst @@ -69,9 +69,9 @@ There are debugfs parameters provided for serial communication. - 0x01 - tty->warned is on. - 0x04 - tty->packed is on. - - 0x08 - tty->flow_stopped is on. + - 0x08 - tty->flow.tco_stopped is on. - 0x10 - tty->hw_stopped is on. - - 0x20 - tty->stopped is on. + - 0x20 - tty->flow.stopped is on. * last_tx_msg: Binary blob Prints the last transmitted frame. diff --git a/Documentation/s390/vfio-ap.rst b/Documentation/s390/vfio-ap.rst index e15436599086..f57ae621f33e 100644 --- a/Documentation/s390/vfio-ap.rst +++ b/Documentation/s390/vfio-ap.rst @@ -514,7 +514,6 @@ These are the steps: * S390_AP_IOMMU * VFIO * VFIO_MDEV - * VFIO_MDEV_DEVICE * KVM If using make menuconfig select the following to build the vfio_ap module:: diff --git a/Documentation/scsi/scsi_mid_low_api.rst b/Documentation/scsi/scsi_mid_low_api.rst index 096ffe9cae0e..63ddea2b9640 100644 --- a/Documentation/scsi/scsi_mid_low_api.rst +++ b/Documentation/scsi/scsi_mid_low_api.rst @@ -1172,10 +1172,9 @@ Members of interest: of 0 implies a successfully completed command (and all data (if any) has been transferred to or from the SCSI target device). 'result' is a 32 bit unsigned integer that - can be viewed as 4 related bytes. The SCSI status value is - in the LSB. See include/scsi/scsi.h status_byte(), - msg_byte(), host_byte() and driver_byte() macros and - related constants. + can be viewed as 2 related bytes. The SCSI status value is + in the LSB. See include/scsi/scsi.h status_byte() and + host_byte() macros and related constants. sense_buffer - an array (maximum size: SCSI_SENSE_BUFFERSIZE bytes) that should be written when the SCSI status (LSB of 'result') diff --git a/Documentation/sound/hd-audio/controls.rst b/Documentation/sound/hd-audio/controls.rst index f2ebc4f79b44..dbe6483f4ff4 100644 --- a/Documentation/sound/hd-audio/controls.rst +++ b/Documentation/sound/hd-audio/controls.rst @@ -102,7 +102,7 @@ Conexant codecs --------------- Auto-Mute Mode - See Reatek codecs. + See Realtek codecs. Analog codecs diff --git a/Documentation/sound/kernel-api/writing-an-alsa-driver.rst b/Documentation/sound/kernel-api/writing-an-alsa-driver.rst index e6365836fa8b..01d59b8aea92 100644 --- a/Documentation/sound/kernel-api/writing-an-alsa-driver.rst +++ b/Documentation/sound/kernel-api/writing-an-alsa-driver.rst @@ -3508,14 +3508,15 @@ field must be set, though). “IEC958 Playback Con Mask” is used to return the bit-mask for the IEC958 status bits of consumer mode. Similarly, “IEC958 Playback Pro Mask” -returns the bitmask for professional mode. They are read-only controls, -and are defined as MIXER controls (iface = -``SNDRV_CTL_ELEM_IFACE_MIXER``). +returns the bitmask for professional mode. They are read-only controls. Meanwhile, “IEC958 Playback Default” control is defined for getting and -setting the current default IEC958 bits. Note that this one is usually -defined as a PCM control (iface = ``SNDRV_CTL_ELEM_IFACE_PCM``), -although in some places it's defined as a MIXER control. +setting the current default IEC958 bits. + +Due to historical reasons, both variants of the Playback Mask and the +Playback Default controls can be implemented on either a +``SNDRV_CTL_ELEM_IFACE_PCM`` or a ``SNDRV_CTL_ELEM_IFACE_MIXER`` iface. +Drivers should expose the mask and default on the same iface though. In addition, you can define the control switches to enable/disable or to set the raw bit mode. The implementation will depend on the chip, but diff --git a/Documentation/trace/boottime-trace.rst b/Documentation/trace/boottime-trace.rst index 89b64334929b..8053898cfeb4 100644 --- a/Documentation/trace/boottime-trace.rst +++ b/Documentation/trace/boottime-trace.rst @@ -99,6 +99,12 @@ These options are setting per-event options. ftrace.[instance.INSTANCE.]event.GROUP.EVENT.enable Enable GROUP:EVENT tracing. +ftrace.[instance.INSTANCE.]event.GROUP.enable + Enable all event tracing within GROUP. + +ftrace.[instance.INSTANCE.]event.enable + Enable all event tracing. + ftrace.[instance.INSTANCE.]event.GROUP.EVENT.filter = FILTER Set FILTER rule to the GROUP:EVENT. diff --git a/Documentation/trace/hwlat_detector.rst b/Documentation/trace/hwlat_detector.rst index 5739349649c8..de94b499b0bc 100644 --- a/Documentation/trace/hwlat_detector.rst +++ b/Documentation/trace/hwlat_detector.rst @@ -76,8 +76,13 @@ in /sys/kernel/tracing: - tracing_cpumask - the CPUs to move the hwlat thread across - hwlat_detector/width - specified amount of time to spin within window (usecs) - hwlat_detector/window - amount of time between (width) runs (usecs) + - hwlat_detector/mode - the thread mode -The hwlat detector's kernel thread will migrate across each CPU specified in -tracing_cpumask between each window. To limit the migration, either modify -tracing_cpumask, or modify the hwlat kernel thread (named [hwlatd]) CPU -affinity directly, and the migration will stop. +By default, one hwlat detector's kernel thread will migrate across each CPU +specified in cpumask at the beginning of a new window, in a round-robin +fashion. This behavior can be changed by changing the thread mode, +the available options are: + + - none: do not force migration + - round-robin: migrate across each CPU specified in cpumask [default] + - per-cpu: create one thread for each cpu in tracing_cpumask diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst index f634b36fd3aa..3769b9b7aed8 100644 --- a/Documentation/trace/index.rst +++ b/Documentation/trace/index.rst @@ -23,6 +23,8 @@ Linux Tracing Technologies histogram-design boottime-trace hwlat_detector + osnoise-tracer + timerlat-tracer intel_th ring-buffer-design stm diff --git a/Documentation/trace/osnoise-tracer.rst b/Documentation/trace/osnoise-tracer.rst new file mode 100644 index 000000000000..b648cb9bf1f0 --- /dev/null +++ b/Documentation/trace/osnoise-tracer.rst @@ -0,0 +1,152 @@ +============== +OSNOISE Tracer +============== + +In the context of high-performance computing (HPC), the Operating System +Noise (*osnoise*) refers to the interference experienced by an application +due to activities inside the operating system. In the context of Linux, +NMIs, IRQs, SoftIRQs, and any other system thread can cause noise to the +system. Moreover, hardware-related jobs can also cause noise, for example, +via SMIs. + +hwlat_detector is one of the tools used to identify the most complex +source of noise: *hardware noise*. + +In a nutshell, the hwlat_detector creates a thread that runs +periodically for a given period. At the beginning of a period, the thread +disables interrupt and starts sampling. While running, the hwlatd +thread reads the time in a loop. As interrupts are disabled, threads, +IRQs, and SoftIRQs cannot interfere with the hwlatd thread. Hence, the +cause of any gap between two different reads of the time roots either on +NMI or in the hardware itself. At the end of the period, hwlatd enables +interrupts and reports the max observed gap between the reads. It also +prints a NMI occurrence counter. If the output does not report NMI +executions, the user can conclude that the hardware is the culprit for +the latency. The hwlat detects the NMI execution by observing +the entry and exit of a NMI. + +The osnoise tracer leverages the hwlat_detector by running a +similar loop with preemption, SoftIRQs and IRQs enabled, thus allowing +all the sources of *osnoise* during its execution. Using the same approach +of hwlat, osnoise takes note of the entry and exit point of any +source of interferences, increasing a per-cpu interference counter. The +osnoise tracer also saves an interference counter for each source of +interference. The interference counter for NMI, IRQs, SoftIRQs, and +threads is increased anytime the tool observes these interferences' entry +events. When a noise happens without any interference from the operating +system level, the hardware noise counter increases, pointing to a +hardware-related noise. In this way, osnoise can account for any +source of interference. At the end of the period, the osnoise tracer +prints the sum of all noise, the max single noise, the percentage of CPU +available for the thread, and the counters for the noise sources. + +Usage +----- + +Write the ASCII text "osnoise" into the current_tracer file of the +tracing system (generally mounted at /sys/kernel/tracing). + +For example:: + + [root@f32 ~]# cd /sys/kernel/tracing/ + [root@f32 tracing]# echo osnoise > current_tracer + +It is possible to follow the trace by reading the trace trace file:: + + [root@f32 tracing]# cat trace + # tracer: osnoise + # + # _-----=> irqs-off + # / _----=> need-resched + # | / _---=> hardirq/softirq + # || / _--=> preempt-depth MAX + # || / SINGLE Interference counters: + # |||| RUNTIME NOISE % OF CPU NOISE +-----------------------------+ + # TASK-PID CPU# |||| TIMESTAMP IN US IN US AVAILABLE IN US HW NMI IRQ SIRQ THREAD + # | | | |||| | | | | | | | | | | + <...>-859 [000] .... 81.637220: 1000000 190 99.98100 9 18 0 1007 18 1 + <...>-860 [001] .... 81.638154: 1000000 656 99.93440 74 23 0 1006 16 3 + <...>-861 [002] .... 81.638193: 1000000 5675 99.43250 202 6 0 1013 25 21 + <...>-862 [003] .... 81.638242: 1000000 125 99.98750 45 1 0 1011 23 0 + <...>-863 [004] .... 81.638260: 1000000 1721 99.82790 168 7 0 1002 49 41 + <...>-864 [005] .... 81.638286: 1000000 263 99.97370 57 6 0 1006 26 2 + <...>-865 [006] .... 81.638302: 1000000 109 99.98910 21 3 0 1006 18 1 + <...>-866 [007] .... 81.638326: 1000000 7816 99.21840 107 8 0 1016 39 19 + +In addition to the regular trace fields (from TASK-PID to TIMESTAMP), the +tracer prints a message at the end of each period for each CPU that is +running an osnoise/ thread. The osnoise specific fields report: + + - The RUNTIME IN US reports the amount of time in microseconds that + the osnoise thread kept looping reading the time. + - The NOISE IN US reports the sum of noise in microseconds observed + by the osnoise tracer during the associated runtime. + - The % OF CPU AVAILABLE reports the percentage of CPU available for + the osnoise thread during the runtime window. + - The MAX SINGLE NOISE IN US reports the maximum single noise observed + during the runtime window. + - The Interference counters display how many each of the respective + interference happened during the runtime window. + +Note that the example above shows a high number of HW noise samples. +The reason being is that this sample was taken on a virtual machine, +and the host interference is detected as a hardware interference. + +Tracer options +--------------------- + +The tracer has a set of options inside the osnoise directory, they are: + + - osnoise/cpus: CPUs at which a osnoise thread will execute. + - osnoise/period_us: the period of the osnoise thread. + - osnoise/runtime_us: how long an osnoise thread will look for noise. + - osnoise/stop_tracing_us: stop the system tracing if a single noise + higher than the configured value happens. Writing 0 disables this + option. + - osnoise/stop_tracing_total_us: stop the system tracing if total noise + higher than the configured value happens. Writing 0 disables this + option. + - tracing_threshold: the minimum delta between two time() reads to be + considered as noise, in us. When set to 0, the default value will + will be used, which is currently 5 us. + +Additional Tracing +------------------ + +In addition to the tracer, a set of tracepoints were added to +facilitate the identification of the osnoise source. + + - osnoise:sample_threshold: printed anytime a noise is higher than + the configurable tolerance_ns. + - osnoise:nmi_noise: noise from NMI, including the duration. + - osnoise:irq_noise: noise from an IRQ, including the duration. + - osnoise:softirq_noise: noise from a SoftIRQ, including the + duration. + - osnoise:thread_noise: noise from a thread, including the duration. + +Note that all the values are *net values*. For example, if while osnoise +is running, another thread preempts the osnoise thread, it will start a +thread_noise duration at the start. Then, an IRQ takes place, preempting +the thread_noise, starting a irq_noise. When the IRQ ends its execution, +it will compute its duration, and this duration will be subtracted from +the thread_noise, in such a way as to avoid the double accounting of the +IRQ execution. This logic is valid for all sources of noise. + +Here is one example of the usage of these tracepoints:: + + osnoise/8-961 [008] d.h. 5789.857532: irq_noise: local_timer:236 start 5789.857529929 duration 1845 ns + osnoise/8-961 [008] dNh. 5789.858408: irq_noise: local_timer:236 start 5789.858404871 duration 2848 ns + migration/8-54 [008] d... 5789.858413: thread_noise: migration/8:54 start 5789.858409300 duration 3068 ns + osnoise/8-961 [008] .... 5789.858413: sample_threshold: start 5789.858404555 duration 8812 ns interferences 2 + +In this example, a noise sample of 8 microseconds was reported in the last +line, pointing to two interferences. Looking backward in the trace, the +two previous entries were about the migration thread running after a +timer IRQ execution. The first event is not part of the noise because +it took place one millisecond before. + +It is worth noticing that the sum of the duration reported in the +tracepoints is smaller than eight us reported in the sample_threshold. +The reason roots in the overhead of the entry and exit code that happens +before and after any interference execution. This justifies the dual +approach: measuring thread and tracing. diff --git a/Documentation/trace/timerlat-tracer.rst b/Documentation/trace/timerlat-tracer.rst new file mode 100644 index 000000000000..c7cbb557aee7 --- /dev/null +++ b/Documentation/trace/timerlat-tracer.rst @@ -0,0 +1,181 @@ +############### +Timerlat tracer +############### + +The timerlat tracer aims to help the preemptive kernel developers to +find souces of wakeup latencies of real-time threads. Like cyclictest, +the tracer sets a periodic timer that wakes up a thread. The thread then +computes a *wakeup latency* value as the difference between the *current +time* and the *absolute time* that the timer was set to expire. The main +goal of timerlat is tracing in such a way to help kernel developers. + +Usage +----- + +Write the ASCII text "timerlat" into the current_tracer file of the +tracing system (generally mounted at /sys/kernel/tracing). + +For example:: + + [root@f32 ~]# cd /sys/kernel/tracing/ + [root@f32 tracing]# echo timerlat > current_tracer + +It is possible to follow the trace by reading the trace trace file:: + + [root@f32 tracing]# cat trace + # tracer: timerlat + # + # _-----=> irqs-off + # / _----=> need-resched + # | / _---=> hardirq/softirq + # || / _--=> preempt-depth + # || / + # |||| ACTIVATION + # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY + # | | | |||| | | | | + -0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns + <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns + -0 [001] dNh1 54.029346: #1 context irq timer_latency 2833 ns + <...>-868 [001] .... 54.029353: #1 context thread timer_latency 9820 ns + -0 [000] d.h1 54.030328: #2 context irq timer_latency 769 ns + <...>-867 [000] .... 54.030330: #2 context thread timer_latency 3070 ns + -0 [001] d.h1 54.030344: #2 context irq timer_latency 935 ns + <...>-868 [001] .... 54.030347: #2 context thread timer_latency 4351 ns + + +The tracer creates a per-cpu kernel thread with real-time priority that +prints two lines at every activation. The first is the *timer latency* +observed at the *hardirq* context before the activation of the thread. +The second is the *timer latency* observed by the thread. The ACTIVATION +ID field serves to relate the *irq* execution to its respective *thread* +execution. + +The *irq*/*thread* splitting is important to clarify at which context +the unexpected high value is coming from. The *irq* context can be +delayed by hardware related actions, such as SMIs, NMIs, IRQs +or by a thread masking interrupts. Once the timer happens, the delay +can also be influenced by blocking caused by threads. For example, by +postponing the scheduler execution via preempt_disable(), by the +scheduler execution, or by masking interrupts. Threads can +also be delayed by the interference from other threads and IRQs. + +Tracer options +--------------------- + +The timerlat tracer is built on top of osnoise tracer. +So its configuration is also done in the osnoise/ config +directory. The timerlat configs are: + + - cpus: CPUs at which a timerlat thread will execute. + - timerlat_period_us: the period of the timerlat thread. + - osnoise/stop_tracing_us: stop the system tracing if a + timer latency at the *irq* context higher than the configured + value happens. Writing 0 disables this option. + - stop_tracing_total_us: stop the system tracing if a + timer latency at the *thread* context higher than the configured + value happens. Writing 0 disables this option. + - print_stack: save the stack of the IRQ ocurrence, and print + it afte the *thread context* event". + +timerlat and osnoise +---------------------------- + +The timerlat can also take advantage of the osnoise: traceevents. +For example:: + + [root@f32 ~]# cd /sys/kernel/tracing/ + [root@f32 tracing]# echo timerlat > current_tracer + [root@f32 tracing]# echo 1 > events/osnoise/enable + [root@f32 tracing]# echo 25 > osnoise/stop_tracing_total_us + [root@f32 tracing]# tail -10 trace + cc1-87882 [005] d..h... 548.771078: #402268 context irq timer_latency 13585 ns + cc1-87882 [005] dNLh1.. 548.771082: irq_noise: local_timer:236 start 548.771077442 duration 7597 ns + cc1-87882 [005] dNLh2.. 548.771099: irq_noise: qxl:21 start 548.771085017 duration 7139 ns + cc1-87882 [005] d...3.. 548.771102: thread_noise: cc1:87882 start 548.771078243 duration 9909 ns + timerlat/5-1035 [005] ....... 548.771104: #402268 context thread timer_latency 39960 ns + +In this case, the root cause of the timer latency does not point to a +single cause, but to multiple ones. Firstly, the timer IRQ was delayed +for 13 us, which may point to a long IRQ disabled section (see IRQ +stacktrace section). Then the timer interrupt that wakes up the timerlat +thread took 7597 ns, and the qxl:21 device IRQ took 7139 ns. Finally, +the cc1 thread noise took 9909 ns of time before the context switch. +Such pieces of evidence are useful for the developer to use other +tracing methods to figure out how to debug and optimize the system. + +It is worth mentioning that the *duration* values reported +by the osnoise: events are *net* values. For example, the +thread_noise does not include the duration of the overhead caused +by the IRQ execution (which indeed accounted for 12736 ns). But +the values reported by the timerlat tracer (timerlat_latency) +are *gross* values. + +The art below illustrates a CPU timeline and how the timerlat tracer +observes it at the top and the osnoise: events at the bottom. Each "-" +in the timelines means circa 1 us, and the time moves ==>:: + + External timer irq thread + clock latency latency + event 13585 ns 39960 ns + | ^ ^ + v | | + |-------------| | + |-------------+-------------------------| + ^ ^ + ======================================================================== + [tmr irq] [dev irq] + [another thread...^ v..^ v.......][timerlat/ thread] <-- CPU timeline + ========================================================================= + |-------| |-------| + |--^ v-------| + | | | + | | + thread_noise: 9909 ns + | +-> irq_noise: 6139 ns + +-> irq_noise: 7597 ns + +IRQ stacktrace +--------------------------- + +The osnoise/print_stack option is helpful for the cases in which a thread +noise causes the major factor for the timer latency, because of preempt or +irq disabled. For example:: + + [root@f32 tracing]# echo 500 > osnoise/stop_tracing_total_us + [root@f32 tracing]# echo 500 > osnoise/print_stack + [root@f32 tracing]# echo timerlat > current_tracer + [root@f32 tracing]# tail -21 per_cpu/cpu7/trace + insmod-1026 [007] dN.h1.. 200.201948: irq_noise: local_timer:236 start 200.201939376 duration 7872 ns + insmod-1026 [007] d..h1.. 200.202587: #29800 context irq timer_latency 1616 ns + insmod-1026 [007] dN.h2.. 200.202598: irq_noise: local_timer:236 start 200.202586162 duration 11855 ns + insmod-1026 [007] dN.h3.. 200.202947: irq_noise: local_timer:236 start 200.202939174 duration 7318 ns + insmod-1026 [007] d...3.. 200.203444: thread_noise: insmod:1026 start 200.202586933 duration 838681 ns + timerlat/7-1001 [007] ....... 200.203445: #29800 context thread timer_latency 859978 ns + timerlat/7-1001 [007] ....1.. 200.203446: + => timerlat_irq + => __hrtimer_run_queues + => hrtimer_interrupt + => __sysvec_apic_timer_interrupt + => asm_call_irq_on_stack + => sysvec_apic_timer_interrupt + => asm_sysvec_apic_timer_interrupt + => delay_tsc + => dummy_load_1ms_pd_init + => do_one_initcall + => do_init_module + => __do_sys_finit_module + => do_syscall_64 + => entry_SYSCALL_64_after_hwframe + +In this case, it is possible to see that the thread added the highest +contribution to the *timer latency* and the stack trace, saved during +the timerlat IRQ handler, points to a function named +dummy_load_1ms_pd_init, which had the following code (on purpose):: + + static int __init dummy_load_1ms_pd_init(void) + { + preempt_disable(); + mdelay(1); + preempt_enable(); + return 0; + + } diff --git a/Documentation/usb/gadget-testing.rst b/Documentation/usb/gadget-testing.rst index 2085e7b24eeb..9d6276f82774 100644 --- a/Documentation/usb/gadget-testing.rst +++ b/Documentation/usb/gadget-testing.rst @@ -728,6 +728,8 @@ The uac2 function provides these attributes in its function directory: c_chmask capture channel mask c_srate capture sampling rate c_ssize capture sample size (bytes) + c_sync capture synchronization type (async/adaptive) + fb_max maximum extra bandwidth in async mode p_chmask playback channel mask p_srate playback sampling rate p_ssize playback sample size (bytes) diff --git a/Documentation/userspace-api/accelerators/ocxl.rst b/Documentation/userspace-api/accelerators/ocxl.rst index 14cefc020e2d..db7570d5e50d 100644 --- a/Documentation/userspace-api/accelerators/ocxl.rst +++ b/Documentation/userspace-api/accelerators/ocxl.rst @@ -6,7 +6,7 @@ OpenCAPI is an interface between processors and accelerators. It aims at being low-latency and high-bandwidth. The specification is developed by the `OpenCAPI Consortium `_. -It allows an accelerator (which could be a FPGA, ASICs, ...) to access +It allows an accelerator (which could be an FPGA, ASICs, ...) to access the host memory coherently, using virtual addresses. An OpenCAPI device can also host its own memory, that can be accessed from the host. diff --git a/Documentation/vm/hmm.rst b/Documentation/vm/hmm.rst index 09e28507f5b2..a14c2938e7af 100644 --- a/Documentation/vm/hmm.rst +++ b/Documentation/vm/hmm.rst @@ -332,7 +332,7 @@ between device driver specific code and shared common code: walks to fill in the ``args->src`` array with PFNs to be migrated. The ``invalidate_range_start()`` callback is passed a ``struct mmu_notifier_range`` with the ``event`` field set to - ``MMU_NOTIFY_MIGRATE`` and the ``migrate_pgmap_owner`` field set to + ``MMU_NOTIFY_MIGRATE`` and the ``owner`` field set to the ``args->pgmap_owner`` field passed to migrate_vma_setup(). This is allows the device driver to skip the invalidation callback and only invalidate device private MMU mappings that are actually migrating. @@ -405,6 +405,23 @@ between device driver specific code and shared common code: The lock can now be released. +Exclusive access memory +======================= + +Some devices have features such as atomic PTE bits that can be used to implement +atomic access to system memory. To support atomic operations to a shared virtual +memory page such a device needs access to that page which is exclusive of any +userspace access from the CPU. The ``make_device_exclusive_range()`` function +can be used to make a memory range inaccessible from userspace. + +This replaces all mappings for pages in the given range with special swap +entries. Any attempt to access the swap entry results in a fault which is +resovled by replacing the entry with the original mapping. A driver gets +notified that the mapping has been changed by MMU notifiers, after which point +it will no longer have exclusive access to the page. Exclusive access is +guranteed to last until the driver drops the page lock and page reference, at +which point any CPU faults on the page may proceed as described. + Memory cgroup (memcg) and rss accounting ======================================== diff --git a/Documentation/vm/unevictable-lru.rst b/Documentation/vm/unevictable-lru.rst index 0e1490524f53..eae3af17f2d9 100644 --- a/Documentation/vm/unevictable-lru.rst +++ b/Documentation/vm/unevictable-lru.rst @@ -389,14 +389,14 @@ mlocked, munlock_vma_page() updates that zone statistics for the number of mlocked pages. Note, however, that at this point we haven't checked whether the page is mapped by other VM_LOCKED VMAs. -We can't call try_to_munlock(), the function that walks the reverse map to +We can't call page_mlock(), the function that walks the reverse map to check for other VM_LOCKED VMAs, without first isolating the page from the LRU. -try_to_munlock() is a variant of try_to_unmap() and thus requires that the page +page_mlock() is a variant of try_to_unmap() and thus requires that the page not be on an LRU list [more on these below]. However, the call to -isolate_lru_page() could fail, in which case we couldn't try_to_munlock(). So, +isolate_lru_page() could fail, in which case we can't call page_mlock(). So, we go ahead and clear PG_mlocked up front, as this might be the only chance we -have. If we can successfully isolate the page, we go ahead and -try_to_munlock(), which will restore the PG_mlocked flag and update the zone +have. If we can successfully isolate the page, we go ahead and call +page_mlock(), which will restore the PG_mlocked flag and update the zone page statistics if it finds another VMA holding the page mlocked. If we fail to isolate the page, we'll have left a potentially mlocked page on the LRU. This is fine, because we'll catch it later if and if vmscan tries to reclaim @@ -545,31 +545,24 @@ munlock or munmap system calls, mm teardown (munlock_vma_pages_all), reclaim, holepunching, and truncation of file pages and their anonymous COWed pages. -try_to_munlock() Reverse Map Scan +page_mlock() Reverse Map Scan --------------------------------- -.. warning:: - [!] TODO/FIXME: a better name might be page_mlocked() - analogous to the - page_referenced() reverse map walker. - When munlock_vma_page() [see section :ref:`munlock()/munlockall() System Call Handling ` above] tries to munlock a page, it needs to determine whether or not the page is mapped by any VM_LOCKED VMA without actually attempting to unmap all PTEs from the page. For this purpose, the unevictable/mlock infrastructure -introduced a variant of try_to_unmap() called try_to_munlock(). +introduced a variant of try_to_unmap() called page_mlock(). -try_to_munlock() calls the same functions as try_to_unmap() for anonymous and -mapped file and KSM pages with a flag argument specifying unlock versus unmap -processing. Again, these functions walk the respective reverse maps looking -for VM_LOCKED VMAs. When such a VMA is found, as in the try_to_unmap() case, -the functions mlock the page via mlock_vma_page() and return SWAP_MLOCK. This -undoes the pre-clearing of the page's PG_mlocked done by munlock_vma_page. +page_mlock() walks the respective reverse maps looking for VM_LOCKED VMAs. When +such a VMA is found the page is mlocked via mlock_vma_page(). This undoes the +pre-clearing of the page's PG_mlocked done by munlock_vma_page. -Note that try_to_munlock()'s reverse map walk must visit every VMA in a page's +Note that page_mlock()'s reverse map walk must visit every VMA in a page's reverse map to determine that a page is NOT mapped into any VM_LOCKED VMA. However, the scan can terminate when it encounters a VM_LOCKED VMA. -Although try_to_munlock() might be called a great many times when munlocking a +Although page_mlock() might be called a great many times when munlocking a large region or tearing down a large address space that has been mlocked via mlockall(), overall this is a fairly rare event. @@ -602,7 +595,7 @@ inactive lists to the appropriate node's unevictable list. shrink_inactive_list() should only see SHM_LOCK'd pages that became SHM_LOCK'd after shrink_active_list() had moved them to the inactive list, or pages mapped into VM_LOCKED VMAs that munlock_vma_page() couldn't isolate from the LRU to -recheck via try_to_munlock(). shrink_inactive_list() won't notice the latter, +recheck via page_mlock(). shrink_inactive_list() won't notice the latter, but will pass on to shrink_page_list(). shrink_page_list() again culls obviously unevictable pages that it could diff --git a/Documentation/w1/slaves/w1_ds2438.rst b/Documentation/w1/slaves/w1_ds2438.rst index a29309a3f8e5..4fa671fbc93f 100644 --- a/Documentation/w1/slaves/w1_ds2438.rst +++ b/Documentation/w1/slaves/w1_ds2438.rst @@ -22,7 +22,7 @@ is also often used in weather stations and applications such as: rain gauge, wind speed/direction measuring, humidity sensing, etc. Current support is provided through the following sysfs files (all files -except "iad" are readonly): +except "iad" and "offset" are readonly): "iad" ----- @@ -44,6 +44,23 @@ Internally when this file is read, the additional CRC byte is also obtained from the slave device. If it is correct, the 8 bytes page data are passed to userspace, otherwise an I/O error is returned. +"page1" +------- +This file provides full 8 bytes of the chip Page 1 (01h). +This page contains the ICA, elapsed time meter and current offset data of the DS2438. +Internally when this file is read, the additional CRC byte is also obtained +from the slave device. If it is correct, the 8 bytes page data are passed +to userspace, otherwise an I/O error is returned. + +"offset" +-------- +This file controls the 2-byte Offset Register of the chip. +Writing a 2-byte value will change the Offset Register, which changes the +current measurement done by the chip. Changing this register to the two's complement +of the current register while forcing zero current through the load will calibrate +the chip, canceling offset errors in the current ADC. + + "temperature" ------------- Opening and reading this file initiates the CONVERT_T (temperature conversion) diff --git a/MAINTAINERS b/MAINTAINERS index d810891fd644..17b0c3b3096f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -299,7 +299,6 @@ M: William Breathitt Gray M: Syed Nayyar Waris L: linux-iio@vger.kernel.org S: Maintained -F: Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 F: drivers/counter/104-quad-8.c ACCES PCI-IDIO-16 GPIO DRIVER @@ -431,6 +430,14 @@ W: https://01.org/linux-acpi B: https://bugzilla.kernel.org F: drivers/acpi/acpi_video.c +ACPI VIOT DRIVER +M: Jean-Philippe Brucker +L: linux-acpi@vger.kernel.org +L: iommu@lists.linux-foundation.org +S: Maintained +F: drivers/acpi/viot.c +F: include/linux/acpi_viot.h + ACPI WMI DRIVER L: platform-driver-x86@vger.kernel.org S: Orphan @@ -783,6 +790,14 @@ M: Ley Foon Tan S: Maintained F: drivers/mailbox/mailbox-altera.c +ALTERA MSGDMA IP CORE DRIVER +M: Olivier Dautricourt +R: Stefan Roese +L: dmaengine@vger.kernel.org +S: Odd Fixes +F: Documentation/devicetree/bindings/dma/altr,msgdma.yaml +F: drivers/dma/altera-msgdma.c + ALTERA PIO DRIVER M: Joyce Ooi L: linux-gpio@vger.kernel.org @@ -878,7 +893,7 @@ M: Harry Wentland M: Leo Li L: amd-gfx@lists.freedesktop.org S: Supported -T: git git://people.freedesktop.org/~agd5f/linux +T: git https://gitlab.freedesktop.org/agd5f/linux.git F: drivers/gpu/drm/amd/display/ AMD FAM15H PROCESSOR POWER MONITORING DRIVER @@ -954,7 +969,7 @@ AMD POWERPLAY M: Evan Quan L: amd-gfx@lists.freedesktop.org S: Supported -T: git git://people.freedesktop.org/~agd5f/linux +T: git https://gitlab.freedesktop.org/agd5f/linux.git F: drivers/gpu/drm/amd/pm/powerplay/ AMD SEATTLE DEVICE TREE SUPPORT @@ -1311,6 +1326,7 @@ W: http://www.aquantia.com F: drivers/net/ethernet/aquantia/atlantic/aq_ptp* ARASAN NAND CONTROLLER DRIVER +M: Miquel Raynal M: Naga Sureshkumar Relli L: linux-mtd@lists.infradead.org S: Maintained @@ -1452,6 +1468,22 @@ S: Odd Fixes F: drivers/amba/ F: include/linux/amba/bus.h +ARM PRIMECELL PL35X NAND CONTROLLER DRIVER +M: Miquel Raynal +M: Naga Sureshkumar Relli +L: linux-mtd@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml +F: drivers/mtd/nand/raw/pl35x-nand-controller.c + +ARM PRIMECELL PL35X SMC DRIVER +M: Miquel Raynal +M: Naga Sureshkumar Relli +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/mtd/arm,pl353-smc.yaml +F: drivers/memory/pl353-smc.c + ARM PRIMECELL CLCD PL110 DRIVER M: Russell King S: Odd Fixes @@ -1655,9 +1687,11 @@ C: irc://chat.freenode.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c F: include/dt-bindings/interrupt-controller/apple-aic.h +F: include/dt-bindings/pinctrl/apple.h ARM/ARTPEC MACHINE SUPPORT M: Jesper Nilsson @@ -3737,9 +3771,6 @@ F: drivers/gpio/gpio-bcm-kona.c BROADCOM NETXTREME-E ROCE DRIVER M: Selvin Xavier -M: Devesh Sharma -M: Somnath Kotur -M: Sriharsha Basavapatna M: Naresh Kumar PBS L: linux-rdma@vger.kernel.org S: Supported @@ -4043,7 +4074,9 @@ W: https://github.com/linux-can T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git F: Documentation/devicetree/bindings/net/can/ +F: Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml F: drivers/net/can/ +F: drivers/phy/phy-can-transceiver.c F: include/linux/can/bittiming.h F: include/linux/can/dev.h F: include/linux/can/led.h @@ -4704,7 +4737,7 @@ COUNTER SUBSYSTEM M: William Breathitt Gray L: linux-iio@vger.kernel.org S: Maintained -F: Documentation/ABI/testing/sysfs-bus-counter* +F: Documentation/ABI/testing/sysfs-bus-counter F: Documentation/driver-api/generic-counter.rst F: drivers/counter/ F: include/linux/counter.h @@ -5027,11 +5060,10 @@ S: Maintained F: drivers/input/touchscreen/cy8ctma140.c CYTTSP TOUCHSCREEN DRIVER -M: Ferruh Yigit +M: Linus Walleij L: linux-input@vger.kernel.org -S: Supported +S: Maintained F: drivers/input/touchscreen/cyttsp* -F: include/linux/input/cyttsp.h D-LINK DIR-685 TOUCHKEYS DRIVER M: Linus Walleij @@ -5912,6 +5944,13 @@ S: Orphan / Obsolete F: drivers/gpu/drm/savage/ F: include/uapi/drm/savage_drm.h +DRM DRIVER FOR SIMPLE FRAMEBUFFERS +M: Thomas Zimmermann +L: dri-devel@lists.freedesktop.org +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: drivers/gpu/drm/tiny/simpledrm.c + DRM DRIVER FOR SIS VIDEO CARDS S: Orphan / Obsolete F: drivers/gpu/drm/sis/ @@ -6119,6 +6158,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc F: Documentation/devicetree/bindings/display/hisilicon/ F: drivers/gpu/drm/hisilicon/ +DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE +M: Deepak Rawat +L: linux-hyperv@vger.kernel.org +L: dri-devel@lists.freedesktop.org +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: drivers/gpu/drm/hyperv + DRM DRIVERS FOR LIMA M: Qiang Yu L: dri-devel@lists.freedesktop.org @@ -6281,7 +6328,7 @@ M: Christian Koenig M: Huang Rui L: dri-devel@lists.freedesktop.org S: Maintained -T: git git://people.freedesktop.org/~agd5f/linux +T: git git://anongit.freedesktop.org/drm/drm-misc F: drivers/gpu/drm/ttm/ F: include/drm/ttm/ @@ -6764,7 +6811,6 @@ F: drivers/net/ethernet/emulex/benet/ EMULEX ONECONNECT ROCE DRIVER M: Selvin Xavier -M: Devesh Sharma L: linux-rdma@vger.kernel.org S: Odd Fixes W: http://www.broadcom.com @@ -6779,6 +6825,15 @@ S: Supported W: http://www.broadcom.com F: drivers/scsi/lpfc/ +EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER +M: James Smart +M: Ram Vegesna +L: linux-scsi@vger.kernel.org +L: target-devel@vger.kernel.org +S: Supported +W: http://www.broadcom.com +F: drivers/scsi/elx/ + ENE CB710 FLASH CARD READER DRIVER M: Michał Mirosław S: Maintained @@ -7133,7 +7188,6 @@ FLEXTIMER FTM-QUADDEC DRIVER M: Patrick Havelange L: linux-iio@vger.kernel.org S: Maintained -F: Documentation/ABI/testing/sysfs-bus-counter-ftm-quaddec F: Documentation/devicetree/bindings/counter/ftm-quaddec.txt F: drivers/counter/ftm-quaddec.c @@ -7149,6 +7203,13 @@ L: linux-input@vger.kernel.org S: Maintained F: drivers/input/joystick/fsia6b.c +FOCUSRITE SCARLETT GEN 2/3 MIXER DRIVER +M: Geoffrey D. Bennett +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git +F: sound/usb/mixer_scarlett_gen2.c + FORCEDETH GIGABIT ETHERNET DRIVER M: Rain River M: Zhu Yanjun @@ -7691,6 +7752,14 @@ L: linux-input@vger.kernel.org S: Maintained F: drivers/input/touchscreen/resistive-adc-touch.c +GENERIC STRING LIBRARY +R: Andy Shevchenko +S: Maintained +F: lib/string.c +F: lib/string_helpers.c +F: lib/test_string.c +F: lib/test-string_helpers.c + GENERIC UIO DRIVER FOR PCI DEVICES M: "Michael S. Tsirkin" L: kvm@vger.kernel.org @@ -8326,6 +8395,13 @@ S: Maintained W: http://www.hisilicon.com F: drivers/spi/spi-hisi-kunpeng.c +HISILICON SPMI CONTROLLER DRIVER FOR HIKEY 970 +M: Mauro Carvalho Chehab +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml +F: drivers/spmi/hisi-spmi-controller.c + HISILICON STAGING DRIVERS FOR HIKEY 960/970 M: Mauro Carvalho Chehab S: Maintained @@ -8893,7 +8969,7 @@ IIO MULTIPLEXER M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt +F: Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml F: drivers/iio/multiplexer/iio-mux.c IIO SCMI BASED DRIVER @@ -9174,6 +9250,14 @@ F: drivers/net/ethernet/intel/*/ F: include/linux/avf/virtchnl.h F: include/linux/net/intel/iidc.h +INTEL ETHERNET PROTOCOL DRIVER FOR RDMA +M: Mustafa Ismail +M: Shiraz Saleem +L: linux-rdma@vger.kernel.org +S: Supported +F: drivers/infiniband/hw/irdma/ +F: include/uapi/rdma/irdma-abi.h + INTEL FRAMEBUFFER DRIVER (excluding 810 and 815) M: Maik Broemme L: linux-fbdev@vger.kernel.org @@ -9348,16 +9432,6 @@ F: drivers/hwmon/intel-m10-bmc-hwmon.c F: drivers/mfd/intel-m10-bmc.c F: include/linux/mfd/intel-m10-bmc.h -INTEL MAX 10 BMC MFD DRIVER -M: Xu Yilun -R: Tom Rix -S: Maintained -F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc -F: Documentation/hwmon/intel-m10-bmc-hwmon.rst -F: drivers/hwmon/intel-m10-bmc-hwmon.c -F: drivers/mfd/intel-m10-bmc.c -F: include/linux/mfd/intel-m10-bmc.h - INTEL MENLOW THERMAL DRIVER M: Sujith Thomas L: platform-driver-x86@vger.kernel.org @@ -9413,13 +9487,10 @@ L: linux-pm@vger.kernel.org S: Supported F: drivers/cpufreq/intel_pstate.c -INTEL RDMA RNIC DRIVER -M: Faisal Latif -M: Shiraz Saleem -L: linux-rdma@vger.kernel.org -S: Supported -F: drivers/infiniband/hw/i40iw/ -F: include/uapi/rdma/i40iw-abi.h +INTEL QUADRATURE ENCODER PERIPHERAL DRIVER +M: Jarkko Nikula +L: linux-iio@vger.kernel.org +F: drivers/counter/intel-qep.c INTEL SCU DRIVERS M: Mika Westerberg @@ -9780,6 +9851,14 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ T: git git://linuxtv.org/anttip/media_tree.git F: drivers/media/tuners/it913x* +ITE IT66121 HDMI BRIDGE DRIVER +M: Phong LE +M: Neil Armstrong +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml +F: drivers/gpu/drm/bridge/ite-it66121.c + IVTV VIDEO4LINUX DRIVER M: Andy Walls L: linux-media@vger.kernel.org @@ -10952,7 +11031,7 @@ MARVELL ARMADA 3700 PHY DRIVERS M: Miquel Raynal S: Maintained F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt -F: Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt +F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c @@ -11886,6 +11965,7 @@ F: include/linux/mmzone.h F: include/linux/pagewalk.h F: include/linux/vmalloc.h F: mm/ +F: tools/testing/selftests/vm/ MEMORY TECHNOLOGY DEVICES (MTD) M: Miquel Raynal @@ -12454,7 +12534,8 @@ S: Maintained F: drivers/net/phy/motorcomm.c MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD -S: Orphan +M: Jiri Slaby +S: Maintained F: Documentation/driver-api/serial/moxa-smartio.rst F: drivers/tty/mxser.* @@ -13287,6 +13368,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/tfa9879.txt F: sound/soc/codecs/tfa9879* +NXP/Goodix TFA989X (TFA1) DRIVER +M: Stephan Gerhold +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml +F: sound/soc/codecs/tfa989x.c + NXP-NCI NFC DRIVER R: Charles Gorand L: linux-nfc@lists.01.org (subscribers-only) @@ -13407,7 +13495,7 @@ M: Santosh Shilimkar M: Kevin Hilman L: linux-omap@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/gpio/gpio-omap.txt +F: Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml F: drivers/gpio/gpio-omap.c OMAP HARDWARE SPINLOCK SUPPORT @@ -13446,7 +13534,7 @@ M: Vignesh R L: linux-omap@vger.kernel.org L: linux-i2c@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/i2c/i2c-omap.txt +F: Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml F: drivers/i2c/busses/i2c-omap.c OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS) @@ -15349,6 +15437,7 @@ F: drivers/net/wireless/quantenna RADEON and AMDGPU DRM DRIVERS M: Alex Deucher M: Christian König +M: Pan, Xinhui L: amd-gfx@lists.freedesktop.org S: Supported T: git https://gitlab.freedesktop.org/agd5f/linux.git @@ -15673,8 +15762,9 @@ F: drivers/clk/renesas/ RENESAS EMEV2 I2C DRIVER M: Wolfram Sang +L: linux-renesas-soc@vger.kernel.org S: Supported -F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt +F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml F: drivers/i2c/busses/i2c-emev2.c RENESAS ETHERNET DRIVERS @@ -15694,9 +15784,10 @@ F: drivers/iio/adc/rcar-gyroadc.c RENESAS R-CAR I2C DRIVERS M: Wolfram Sang +L: linux-renesas-soc@vger.kernel.org S: Supported -F: Documentation/devicetree/bindings/i2c/renesas,i2c.txt -F: Documentation/devicetree/bindings/i2c/renesas,iic.txt +F: Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml +F: Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml F: drivers/i2c/busses/i2c-rcar.c F: drivers/i2c/busses/i2c-sh_mobile.c @@ -15711,8 +15802,9 @@ F: drivers/thermal/rcar_thermal.c RENESAS RIIC DRIVER M: Chris Brandt +L: linux-renesas-soc@vger.kernel.org S: Supported -F: Documentation/devicetree/bindings/i2c/renesas,riic.txt +F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml F: drivers/i2c/busses/i2c-riic.c RENESAS USB PHY DRIVER @@ -16593,6 +16685,8 @@ M: Tomasz Duszynski S: Maintained F: Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml F: drivers/iio/chemical/sps30.c +F: drivers/iio/chemical/sps30_i2c.c +F: drivers/iio/chemical/sps30_serial.c SERIAL DEVICE BUS M: Rob Herring @@ -17819,7 +17913,7 @@ M: Sudeep Holla R: Cristian Marussi L: linux-arm-kernel@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt +F: Documentation/devicetree/bindings/firmware/arm,sc[mp]i.yaml F: drivers/clk/clk-sc[mp]i.c F: drivers/cpufreq/sc[mp]i-cpufreq.c F: drivers/firmware/arm_scmi/ @@ -18192,11 +18286,11 @@ L: linux-arm-kernel@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt -F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt +F: Documentation/devicetree/bindings/clock/ti,sci-clk.yaml F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml -F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt -F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +F: Documentation/devicetree/bindings/reset/ti,sci-reset.yaml +F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml F: drivers/clk/keystone/sci-clk.c F: drivers/firmware/ti_sci* F: drivers/irqchip/irq-ti-sci-inta.c @@ -18217,6 +18311,13 @@ F: Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml F: Documentation/hwmon/tps23861.rst F: drivers/hwmon/tps23861.c +TEXAS INSTRUMENTS' TMP117 TEMPERATURE SENSOR DRIVER +M: Puranjay Mohan +L: linux-iio@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml +F: drivers/iio/temperature/tmp117.c + THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org @@ -18380,7 +18481,7 @@ TI DAVINCI SERIES GPIO DRIVER M: Keerthy L: linux-gpio@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/gpio/gpio-davinci.txt +F: Documentation/devicetree/bindings/gpio/gpio-davinci.yaml F: drivers/gpio/gpio-davinci.c TI DAVINCI SERIES MEDIA DRIVER @@ -18453,6 +18554,14 @@ S: Supported F: Documentation/devicetree/bindings/net/nfc/trf7970a.txt F: drivers/nfc/trf7970a.c +TI TSC2046 ADC DRIVER +M: Oleksij Rempel +R: kernel@pengutronix.de +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml +F: drivers/iio/adc/ti-tsc2046.c + TI TWL4030 SERIES SOC CODEC DRIVER M: Peter Ujfalusi L: alsa-devel@alsa-project.org (moderated for non-subscribers) @@ -18676,9 +18785,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git F: Documentation/driver-api/serial/ F: drivers/tty/ F: drivers/tty/serial/serial_core.c +F: include/linux/selection.h F: include/linux/serial.h F: include/linux/serial_core.h -F: include/linux/tty.h +F: include/linux/sysrq.h +F: include/linux/tty*.h +F: include/linux/vt.h +F: include/linux/vt_*.h F: include/uapi/linux/serial.h F: include/uapi/linux/serial_core.h F: include/uapi/linux/tty.h @@ -18969,7 +19082,7 @@ L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/roles/intel-xhci-usb-role-switch.c -USB IP DRIVER FOR HISILICON KIRIN +USB IP DRIVER FOR HISILICON KIRIN 960 M: Yu Chen M: Binghui Wang L: linux-usb@vger.kernel.org @@ -18977,6 +19090,13 @@ S: Maintained F: Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml F: drivers/phy/hisilicon/phy-hi3660-usb3.c +USB IP DRIVER FOR HISILICON KIRIN 970 +M: Mauro Carvalho Chehab +L: linux-usb@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml +F: drivers/phy/hisilicon/phy-kirin970-usb3.c + USB ISP116X DRIVER M: Olav Kongas L: linux-usb@vger.kernel.org @@ -20298,7 +20418,6 @@ M: Seth Jennings M: Dan Streetman L: linux-mm@kvack.org S: Maintained -F: include/linux/zbud.h F: mm/zbud.c ZD1211RW WIRELESS DRIVER diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 8954216b9956..77d3280dc678 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -40,6 +40,7 @@ config ALPHA select MMU_GATHER_NO_RANGE select SET_FS select SPARSEMEM_EXTREME if SPARSEMEM + select ZONE_DMA help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, @@ -65,10 +66,6 @@ config GENERIC_CALIBRATE_DELAY bool default y -config ZONE_DMA - bool - default y - config GENERIC_ISA_DMA bool default y diff --git a/arch/alpha/include/asm/pgalloc.h b/arch/alpha/include/asm/pgalloc.h index 9c6a24fe493d..68be7adbfe58 100644 --- a/arch/alpha/include/asm/pgalloc.h +++ b/arch/alpha/include/asm/pgalloc.h @@ -18,7 +18,6 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) { pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET)); } -#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index e1757b7cfe3d..ff690846465e 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h @@ -46,7 +46,6 @@ struct vm_area_struct; #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3)) #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3)) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL /* Number of pointers that fit on a page: this will go away. */ #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3)) diff --git a/arch/alpha/include/asm/unaligned.h b/arch/alpha/include/asm/unaligned.h deleted file mode 100644 index 863c807b66f8..000000000000 --- a/arch/alpha/include/asm/unaligned.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ALPHA_UNALIGNED_H -#define _ASM_ALPHA_UNALIGNED_H - -#include -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_ALPHA_UNALIGNED_H */ diff --git a/arch/alpha/include/uapi/asm/mman.h b/arch/alpha/include/uapi/asm/mman.h index a18ec7f63888..56b4ee5a6c9e 100644 --- a/arch/alpha/include/uapi/asm/mman.h +++ b/arch/alpha/include/uapi/asm/mman.h @@ -71,6 +71,9 @@ #define MADV_COLD 20 /* deactivate these pages */ #define MADV_PAGEOUT 21 /* reclaim these pages */ +#define MADV_POPULATE_READ 22 /* populate (prefault) page tables readable */ +#define MADV_POPULATE_WRITE 23 /* populate (prefault) page tables writable */ + /* compatibility flags */ #define MAP_FILE 0 diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 5f6858e9dc28..7d56c217b235 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -46,7 +47,6 @@ #include #include -extern struct atomic_notifier_head panic_notifier_list; static int alpha_panic_event(struct notifier_block *, unsigned long, void *); static struct notifier_block alpha_panic_block = { alpha_panic_event, diff --git a/arch/alpha/kernel/srmcons.c b/arch/alpha/kernel/srmcons.c index 438b10c44d73..fc03471a0b0f 100644 --- a/arch/alpha/kernel/srmcons.c +++ b/arch/alpha/kernel/srmcons.c @@ -142,18 +142,12 @@ srmcons_write(struct tty_struct *tty, return count; } -static int +static unsigned int srmcons_write_room(struct tty_struct *tty) { return 512; } -static int -srmcons_chars_in_buffer(struct tty_struct *tty) -{ - return 0; -} - static int srmcons_open(struct tty_struct *tty, struct file *filp) { @@ -200,7 +194,6 @@ static const struct tty_operations srmcons_ops = { .close = srmcons_close, .write = srmcons_write, .write_room = srmcons_write_room, - .chars_in_buffer= srmcons_chars_in_buffer, }; static int __init diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h index 6147db925248..a32ca3104ced 100644 --- a/arch/arc/include/asm/pgalloc.h +++ b/arch/arc/include/asm/pgalloc.h @@ -129,6 +129,4 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptep) #define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, pte) -#define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd)) - #endif /* _ASM_ARC_PGALLOC_H */ diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 5878846f00cf..320cc0ae8a08 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -222,12 +222,6 @@ */ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -/* - * No special requirements for lowest virtual address we permit any user space - * mapping to be mapped at. - */ -#define FIRST_USER_ADDRESS 0UL - /**************************************************************** * Bucket load of VM Helpers @@ -356,6 +350,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, #define kern_addr_valid(addr) (1) +#define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd)) + /* * remap a physical page `pfn' of size `size' with page protection `prot' * into virtual address `from' diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1677d51efd0d..d329c12a359a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -217,9 +217,6 @@ config GENERIC_CALIBRATE_DELAY config ARCH_MAY_HAVE_PC_FDC bool -config ZONE_DMA - bool - config ARCH_SUPPORTS_UPROBES def_bool y @@ -352,7 +349,6 @@ config ARCH_EP93XX select ARM_VIC select GENERIC_IRQ_MULTI_HANDLER select AUTO_ZRELADDR - select CLKDEV_LOOKUP select CLKSRC_MMIO select CPU_ARM920T select GPIOLIB @@ -503,7 +499,6 @@ config ARCH_OMAP1 bool "TI OMAP1" depends on MMU select ARCH_OMAP - select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_IRQ_CHIP select GENERIC_IRQ_MULTI_HANDLER diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index dced92a8970e..b7b7106f2dee 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -164,7 +164,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -220,7 +220,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -244,7 +244,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -261,7 +261,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c726cd8dbdf1..314fc5975acb 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -250,7 +250,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { @@ -276,7 +276,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { @@ -294,7 +294,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { @@ -313,7 +313,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck@2df0 { @@ -557,7 +557,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index a534a8e444d9..04e8a27ba1eb 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -148,7 +148,7 @@ usb: usb@4f000000 { compatible = "nxp,usb-isp1761"; reg = <0x4f000000 0x20000>; - port1-otg; + dr_mode = "peripheral"; }; bridge { diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index f925782f8560..366687fb1ee3 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -166,7 +166,7 @@ reg = <0x3b000000 0x20000>; interrupt-parent = <&intc_fpga1176>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; + dr_mode = "peripheral"; }; bridge { diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 0c7dabef4a5f..228a51a38f95 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -712,7 +712,7 @@ reg = <0x4f000000 0x20000>; interrupt-parent = <&intc_tc11mp>; interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; + dr_mode = "peripheral"; }; }; }; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index ac95667ed781..ccf6f756b6ed 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -164,7 +164,7 @@ usb: usb@4f000000 { compatible = "nxp,usb-isp1761"; reg = <0x4f000000 0x20000>; - port1-otg; + dr_mode = "peripheral"; }; bridge { diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index be040b6a02fa..5a5fa6190a52 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -651,6 +651,7 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + fsl,dma-info = <24 20>; status = "okay"; }; @@ -670,6 +671,7 @@ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; + fsl,dma-info = <4096 4>; status = "okay"; }; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 4f7220b11f2d..2ad9fd7c94ec 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -144,7 +144,7 @@ compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; - port1-otg; + dr_mode = "peripheral"; }; iofpga-bus@300000000 { diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 2ac41ed3a57c..ec13ceb9ed36 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -62,7 +62,7 @@ compatible = "nxp,usb-isp1761"; reg = <3 0x03000000 0x20000>; interrupts = <16>; - port1-otg; + dr_mode = "peripheral"; }; iofpga@7,00000000 { diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index fdee1f04f4f3..a17f01235c29 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -143,7 +143,6 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) __pmd_populate(pmdp, page_to_phys(ptep), prot); } -#define pmd_pgtable(pmd) pmd_page(pmd) #endif /* CONFIG_MMU */ diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h deleted file mode 100644 index ab905ffcf193..000000000000 --- a/arch/arm/include/asm/unaligned.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __ASM_ARM_UNALIGNED_H -#define __ASM_ARM_UNALIGNED_H - -/* - * We generally want to set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS on ARMv6+, - * but we don't want to use linux/unaligned/access_ok.h since that can lead - * to traps on unaligned stm/ldm or strd/ldrd. - */ -#include - -#if defined(__LITTLE_ENDIAN) -# include -# include -# include -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#elif defined(__BIG_ENDIAN) -# include -# include -# include -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#else -# error need to define endianess -#endif - -#endif /* __ASM_ARM_UNALIGNED_H */ diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 9d4744a632c6..6162a070a410 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -125,11 +125,22 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max_low, int pfn_valid(unsigned long pfn) { phys_addr_t addr = __pfn_to_phys(pfn); + unsigned long pageblock_size = PAGE_SIZE * pageblock_nr_pages; if (__phys_to_pfn(addr) != pfn) return 0; - return memblock_is_map_memory(addr); + /* + * If address less than pageblock_size bytes away from a present + * memory chunk there still will be a memory map entry for it + * because we round freed memory map to the pageblock boundaries. + */ + if (memblock_overlaps_region(&memblock.memory, + ALIGN_DOWN(addr, pageblock_size), + pageblock_size)) + return 1; + + return 0; } EXPORT_SYMBOL(pfn_valid); #endif diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index be9083882f97..e07e7de9ac49 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -42,6 +42,7 @@ config ARM64 select ARCH_HAS_SYSCALL_WRAPPER select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST + select ARCH_HAS_ZONE_DMA_SET if EXPERT select ARCH_HAVE_ELF_PROT select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_INLINE_READ_LOCK if !PREEMPTION @@ -155,7 +156,6 @@ config ARM64 select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT - select HAVE_ARCH_PFN_VALID select HAVE_ARCH_PREL32_RELOCATIONS select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET select HAVE_ARCH_SECCOMP_FILTER @@ -308,14 +308,6 @@ config GENERIC_CSUM config GENERIC_CALIBRATE_DELAY def_bool y -config ZONE_DMA - bool "Support DMA zone" if EXPERT - default y - -config ZONE_DMA32 - bool "Support DMA32 zone" if EXPERT - default y - config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE def_bool y @@ -1053,9 +1045,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK def_bool y depends on NUMA -config HOLES_IN_ZONE - def_bool y - source "kernel/Kconfig.hz" config ARCH_SPARSEMEM_ENABLE diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 456dcd4a7793..6ffbb099fcac 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -134,7 +134,7 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; + reg = <0x12000 0x18>; clocks = <&xtalclk>; interrupts = , diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ce430ba9c118..5d06216c5c1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1136,7 +1136,7 @@ }; adreno_smmu: iommu@b40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0x00b40000 0x10000>; #global-interrupts = <1>; diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h index 5abf91e3494c..1242f71937f8 100644 --- a/arch/arm64/include/asm/hugetlb.h +++ b/arch/arm64/include/asm/hugetlb.h @@ -23,8 +23,7 @@ static inline void arch_clear_hugepage_flags(struct page *page) } #define arch_clear_hugepage_flags arch_clear_hugepage_flags -extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, - struct page *page, int writable); +pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags); #define arch_make_huge_pte arch_make_huge_pte #define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT extern void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 1a35a4473598..824a3655dd93 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -351,7 +351,7 @@ static inline void *phys_to_virt(phys_addr_t x) #define virt_addr_valid(addr) ({ \ __typeof__(addr) __addr = __tag_reset(addr); \ - __is_lm_address(__addr) && pfn_valid(virt_to_pfn(__addr)); \ + __is_lm_address(__addr) && pfn_is_map_memory(virt_to_pfn(__addr)); \ }) void dump_mem_limit(void); diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h index ed1b9dcf12b2..993a27ea6f54 100644 --- a/arch/arm64/include/asm/page.h +++ b/arch/arm64/include/asm/page.h @@ -41,7 +41,7 @@ void tag_clear_highpage(struct page *to); typedef struct page *pgtable_t; -extern int pfn_valid(unsigned long); +int pfn_is_map_memory(unsigned long pfn); #include diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h index 31fbab3d6f99..8433a2058eb1 100644 --- a/arch/arm64/include/asm/pgalloc.h +++ b/arch/arm64/include/asm/pgalloc.h @@ -86,6 +86,5 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) VM_BUG_ON(mm == &init_mm); __pmd_populate(pmdp, page_to_phys(ptep), PMD_TYPE_TABLE | PMD_TABLE_PXN); } -#define pmd_pgtable(pmd) pmd_page(pmd) #endif diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index c0ba8cdfa10a..508c7ffad515 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -26,8 +26,6 @@ #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) -#define FIRST_USER_ADDRESS 0UL - #ifndef __ASSEMBLY__ #include diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 8ed66142b088..880f40bae60e 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index f23dfa06433b..3155c9e778f0 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -85,7 +85,7 @@ void kvm_flush_remote_tlbs(struct kvm *kvm) static bool kvm_is_device_pfn(unsigned long pfn) { - return !pfn_valid(pfn); + return !pfn_is_map_memory(pfn); } static void *stage2_memcache_zalloc_page(void *arg) diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 66aea6c4166c..a992fb88cbed 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -51,7 +51,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_coherent = coherent; if (iommu) { - iommu_setup_dma_ops(dev, dma_base, size); + iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); trace_android_vh_iommu_setup_dma_ops(dev, dma_base, size); } diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c index 58987a98e179..23505fc35324 100644 --- a/arch/arm64/mm/hugetlbpage.c +++ b/arch/arm64/mm/hugetlbpage.c @@ -339,10 +339,9 @@ pte_t *huge_pte_offset(struct mm_struct *mm, return NULL; } -pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, - struct page *page, int writable) +pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) { - size_t pagesize = huge_page_size(hstate_vma(vma)); + size_t pagesize = 1UL << shift; if (pagesize == CONT_PTE_SIZE) { entry = pte_mkcont(entry); diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 6e1ca044ca90..8490ed2917ff 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -219,42 +219,17 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max) free_area_init(max_zone_pfns); } -int pfn_valid(unsigned long pfn) +int pfn_is_map_memory(unsigned long pfn) { phys_addr_t addr = PFN_PHYS(pfn); - struct mem_section *ms; - /* - * Ensure the upper PAGE_SHIFT bits are clear in the - * pfn. Else it might lead to false positives when - * some of the upper bits are set, but the lower bits - * match a valid pfn. - */ + /* avoid false positives for bogus PFNs, see comment in pfn_valid() */ if (PHYS_PFN(addr) != pfn) return 0; - if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS) - return 0; - - ms = __pfn_to_section(pfn); - if (!valid_section(ms)) - return 0; - - /* - * ZONE_DEVICE memory does not have the memblock entries. - * memblock_is_map_memory() check for ZONE_DEVICE based - * addresses will always fail. Even the normal hotplugged - * memory will never have MEMBLOCK_NOMAP flag set in their - * memblock entries. Skip memblock search for all non early - * memory sections covering all of hotplug memory including - * both normal and ZONE_DEVICE based. - */ - if (!early_section(ms)) - return pfn_section_valid(ms, pfn); - return memblock_is_map_memory(addr); } -EXPORT_SYMBOL(pfn_valid); +EXPORT_SYMBOL(pfn_is_map_memory); static phys_addr_t memory_limit = PHYS_ADDR_MAX; diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c index b5e83c46b23e..b7c81dacabf0 100644 --- a/arch/arm64/mm/ioremap.c +++ b/arch/arm64/mm/ioremap.c @@ -43,7 +43,7 @@ static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size, /* * Don't allow RAM to be mapped. */ - if (WARN_ON(pfn_valid(__phys_to_pfn(phys_addr)))) + if (WARN_ON(pfn_is_map_memory(__phys_to_pfn(phys_addr)))) return NULL; area = get_vm_area_caller(size, VM_IOREMAP, caller); @@ -84,7 +84,7 @@ EXPORT_SYMBOL(iounmap); void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size) { /* For normal memory we already have a cacheable mapping. */ - if (pfn_valid(__phys_to_pfn(phys_addr))) + if (pfn_is_map_memory(__phys_to_pfn(phys_addr))) return (void __iomem *)__phys_to_virt(phys_addr); return __ioremap_caller(phys_addr, size, __pgprot(PROT_NORMAL), diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 0b28cc218091..595fde9a47dd 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -82,7 +82,7 @@ void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd) pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { - if (!pfn_valid(pfn)) + if (!pfn_is_map_memory(pfn)) return pgprot_noncached(vma_prot); else if (file->f_flags & O_SYNC) return pgprot_writecombine(vma_prot); @@ -1339,6 +1339,7 @@ void *__init fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot) return dt_virt; } +#if CONFIG_PGTABLE_LEVELS > 3 int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) { pud_t new_pud = pfn_pud(__phys_to_pfn(phys), mk_pud_sect_prot(prot)); @@ -1353,6 +1354,16 @@ int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) return 1; } +int pud_clear_huge(pud_t *pudp) +{ + if (!pud_sect(READ_ONCE(*pudp))) + return 0; + pud_clear(pudp); + return 1; +} +#endif + +#if CONFIG_PGTABLE_LEVELS > 2 int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) { pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), mk_pmd_sect_prot(prot)); @@ -1367,14 +1378,6 @@ int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) return 1; } -int pud_clear_huge(pud_t *pudp) -{ - if (!pud_sect(READ_ONCE(*pudp))) - return 0; - pud_clear(pudp); - return 1; -} - int pmd_clear_huge(pmd_t *pmdp) { if (!pmd_sect(READ_ONCE(*pmdp))) @@ -1382,6 +1385,7 @@ int pmd_clear_huge(pmd_t *pmdp) pmd_clear(pmdp); return 1; } +#endif int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) { diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index 8de5b987edb9..2716f6395ba7 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -76,8 +76,6 @@ config CSKY select PERF_USE_VMALLOC if CPU_CK610 select RTC_LIB select TIMER_OF - select USB_ARCH_HAS_EHCI - select USB_ARCH_HAS_OHCI select GENERIC_PCI_IOMAP select HAVE_PCI select PCI_DOMAINS_GENERIC if PCI @@ -245,7 +243,6 @@ endchoice menuconfig HAVE_TCM bool "Tightly-Coupled/Sram Memory" - select GENERIC_ALLOCATOR help The implementation are not only used by TCM (Tightly-Coupled Meory) but also used by sram on SOC bus. It follow existed linux tcm diff --git a/arch/csky/include/asm/pgalloc.h b/arch/csky/include/asm/pgalloc.h index cd211aabbefd..bbbd0698b397 100644 --- a/arch/csky/include/asm/pgalloc.h +++ b/arch/csky/include/asm/pgalloc.h @@ -22,8 +22,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, set_pmd(pmd, __pmd(__pa(page_address(pte)))); } -#define pmd_pgtable(pmd) pmd_page(pmd) - extern void pgd_init(unsigned long *p); static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm) diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h index 0d60367b6bfa..151607ed5158 100644 --- a/arch/csky/include/asm/pgtable.h +++ b/arch/csky/include/asm/pgtable.h @@ -14,7 +14,6 @@ #define PGDIR_MASK (~(PGDIR_SIZE-1)) #define USER_PTRS_PER_PGD (PAGE_OFFSET/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL /* * C-SKY is two-level paging structure: diff --git a/arch/csky/mm/syscache.c b/arch/csky/mm/syscache.c index 4e51d63850c4..cd847ad62c7e 100644 --- a/arch/csky/mm/syscache.c +++ b/arch/csky/mm/syscache.c @@ -12,15 +12,17 @@ SYSCALL_DEFINE3(cacheflush, int, cache) { switch (cache) { - case ICACHE: case BCACHE: - flush_icache_mm_range(current->mm, - (unsigned long)addr, - (unsigned long)addr + bytes); - fallthrough; case DCACHE: dcache_wb_range((unsigned long)addr, (unsigned long)addr + bytes); + if (cache != BCACHE) + break; + fallthrough; + case ICACHE: + flush_icache_mm_range(current->mm, + (unsigned long)addr, + (unsigned long)addr + bytes); break; default: return -EINVAL; diff --git a/arch/hexagon/include/asm/pgtable.h b/arch/hexagon/include/asm/pgtable.h index dbb22b80b8c4..18cd6ea9ab23 100644 --- a/arch/hexagon/include/asm/pgtable.h +++ b/arch/hexagon/include/asm/pgtable.h @@ -155,9 +155,6 @@ extern unsigned long _dflt_cache_att; extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* located in head.S */ -/* Seems to be zero even in architectures where the zero page is firewalled? */ -#define FIRST_USER_ADDRESS 0UL - /* HUGETLB not working currently */ #ifdef CONFIG_HUGETLB_PAGE #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) @@ -242,7 +239,6 @@ static inline int pmd_bad(pmd_t pmd) * pmd_page - converts a PMD entry to a page pointer */ #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) -#define pmd_pgtable(pmd) pmd_page(pmd) /** * pte_none - check if pte is mapped diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index da22a35e6f03..cf425c2c63af 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -60,6 +60,7 @@ config IA64 select NUMA if !FLATMEM select PCI_MSI_ARCH_FALLBACKS if PCI_MSI select SET_FS + select ZONE_DMA32 default y help The Itanium Processor Family is Intel's 64-bit successor to @@ -72,9 +73,6 @@ config 64BIT select ATA_NONSTANDARD if ATA default y -config ZONE_DMA32 - def_bool y - config MMU bool default y @@ -308,9 +306,6 @@ config NODES_SHIFT MAX_NUMNODES will be 2^(This value). If in doubt, use the default. -config HOLES_IN_ZONE - bool - config HAVE_ARCH_NODEDATA_EXTENSION def_bool y depends on NUMA diff --git a/arch/ia64/include/asm/pal.h b/arch/ia64/include/asm/pal.h index 5c51fceedaf9..e6b652f9e45e 100644 --- a/arch/ia64/include/asm/pal.h +++ b/arch/ia64/include/asm/pal.h @@ -99,6 +99,7 @@ #include #include +#include /* * Data types needed to pass information into PAL procedures and diff --git a/arch/ia64/include/asm/pgalloc.h b/arch/ia64/include/asm/pgalloc.h index 9601cfe83c94..0fb2b6291d58 100644 --- a/arch/ia64/include/asm/pgalloc.h +++ b/arch/ia64/include/asm/pgalloc.h @@ -52,7 +52,6 @@ pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte) { pmd_val(*pmd_entry) = page_to_phys(pte); } -#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h index d765fd948fae..3f5dbbd8b9d8 100644 --- a/arch/ia64/include/asm/pgtable.h +++ b/arch/ia64/include/asm/pgtable.h @@ -128,7 +128,6 @@ #define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT #define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ -#define FIRST_USER_ADDRESS 0UL /* * All the normal masks have the "page accessed" bits on, as any time diff --git a/arch/ia64/include/asm/unaligned.h b/arch/ia64/include/asm/unaligned.h deleted file mode 100644 index 328942e3cbce..000000000000 --- a/arch/ia64/include/asm/unaligned.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_IA64_UNALIGNED_H -#define _ASM_IA64_UNALIGNED_H - -#include -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_IA64_UNALIGNED_H */ diff --git a/arch/m68k/68000/dragen2.c b/arch/m68k/68000/dragen2.c index 584893c57c37..62f10a9e1ab7 100644 --- a/arch/m68k/68000/dragen2.c +++ b/arch/m68k/68000/dragen2.c @@ -11,6 +11,7 @@ #include #include #include +#include "screen.h" /***************************************************************************/ /* Init Drangon Engine hardware */ diff --git a/arch/m68k/68000/screen.h b/arch/m68k/68000/screen.h new file mode 100644 index 000000000000..2089bdf02688 --- /dev/null +++ b/arch/m68k/68000/screen.h @@ -0,0 +1,804 @@ +/* Created with The GIMP */ +#define screen_width 320 +#define screen_height 240 +static unsigned char screen_bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x56, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0d, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x5a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x95, 0x6a, 0x00, 0x00, 0x00, 0x03, 0xf8, 0x70, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + 0x01, 0xf8, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x5b, 0x55, 0x00, 0x00, 0x00, 0x0f, + 0xfc, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x38, 0x03, 0xfc, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0xb5, 0x56, + 0x00, 0x00, 0x00, 0x1e, 0x0c, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x03, 0x0e, 0x00, 0x61, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xd7, 0x55, 0x55, 0x00, 0x03, 0x8e, 0x1c, 0x00, 0x70, 0xe1, 0x9e, + 0x0e, 0x38, 0xe1, 0x80, 0x70, 0xc0, 0xf0, 0x73, 0x33, 0xc0, 0x78, 0x38, + 0x00, 0x0e, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0xa9, 0xaa, 0xad, 0x00, 0x03, 0x8e, 0x38, + 0x00, 0x70, 0xe1, 0xff, 0x0e, 0x38, 0xe3, 0x80, 0x71, 0xc3, 0xf8, 0x77, + 0x3f, 0xe1, 0xfc, 0x38, 0x00, 0x0e, 0x00, 0xef, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x2b, 0x55, 0x6a, + 0x00, 0x03, 0x8e, 0x38, 0x00, 0x70, 0xe1, 0xe7, 0x0e, 0x38, 0x73, 0x00, + 0x73, 0x83, 0x9c, 0x7f, 0x3c, 0xe1, 0xce, 0x38, 0x00, 0x1c, 0x00, 0xff, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x15, 0x56, 0xab, 0x55, 0x00, 0x03, 0x8e, 0x38, 0x00, 0x70, 0xe1, 0xc7, + 0x0e, 0x38, 0x76, 0x00, 0x77, 0x07, 0x1c, 0x78, 0x38, 0xe3, 0x8e, 0x38, + 0x00, 0x78, 0x00, 0xf3, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x69, 0x55, 0x5a, 0xb7, 0x00, 0x03, 0x8e, 0x38, + 0x00, 0x70, 0xe1, 0xc7, 0x0e, 0x38, 0x3c, 0x00, 0x7e, 0x07, 0xfc, 0x70, + 0x38, 0xe3, 0xfe, 0x38, 0x00, 0xf0, 0x00, 0xe1, 0xc0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa5, 0x9a, 0xab, 0x6d, + 0x00, 0x03, 0x8e, 0x3c, 0x00, 0x70, 0xe1, 0xc7, 0x0e, 0x38, 0x3e, 0x00, + 0x7f, 0x07, 0xfc, 0x70, 0x38, 0xe3, 0xfe, 0x38, 0x01, 0xc0, 0x00, 0xe1, + 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, + 0x4d, 0x75, 0xb6, 0xd5, 0x00, 0x03, 0x8e, 0x1c, 0x00, 0x70, 0xe1, 0xc7, + 0x0e, 0x38, 0x77, 0x00, 0x77, 0x87, 0x00, 0x70, 0x38, 0xe3, 0x80, 0x38, + 0x03, 0x80, 0x00, 0xe1, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x14, 0xaa, 0xca, 0xd5, 0x5b, 0x00, 0x03, 0x9e, 0x1f, + 0x0c, 0x70, 0xe1, 0xc7, 0x0e, 0x78, 0x67, 0x00, 0x73, 0xc7, 0x8c, 0x70, + 0x38, 0xe3, 0xc6, 0x38, 0x03, 0xfe, 0x38, 0x71, 0xc0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xb5, 0xbb, 0x5b, 0x6a, + 0x00, 0x03, 0xfe, 0x0f, 0xfc, 0x70, 0xe1, 0xc7, 0x0f, 0xf8, 0xe3, 0x80, + 0x71, 0xe3, 0xfc, 0x70, 0x38, 0xe1, 0xfe, 0x38, 0x03, 0xfe, 0x38, 0x7f, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, + 0x6b, 0x56, 0xd6, 0xad, 0x00, 0x01, 0xe6, 0x03, 0xf0, 0x70, 0xe1, 0xc7, + 0x07, 0x98, 0xc3, 0x80, 0x70, 0xe0, 0xf8, 0x70, 0x38, 0xe0, 0x7c, 0x38, + 0x03, 0xfe, 0x38, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x55, 0x55, 0x6a, 0xba, 0xeb, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x56, 0xd5, 0xd5, 0xd5, 0xac, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x5a, + 0xb7, 0x3d, 0x57, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x75, 0x6d, 0xaa, 0xd3, 0xac, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x8b, 0x6a, 0xb6, 0xde, 0x6b, 0xb6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xba, 0xad, + 0xeb, 0x32, 0xda, 0xad, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x1e, 0xaa, 0xb5, 0xad, 0x6e, 0x96, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x86, 0x00, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xfc, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x6b, 0x6f, 0x5a, 0xb5, 0x75, 0x69, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x86, 0x00, 0x00, 0x06, 0x18, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf5, 0xda, 0xd9, + 0x53, 0xeb, 0x6b, 0x4b, 0x00, 0x00, 0xf0, 0xde, 0x03, 0xe6, 0xf0, 0x78, + 0x06, 0x0c, 0x6c, 0x7c, 0x1f, 0x87, 0x86, 0xf0, 0xc0, 0xde, 0x0f, 0xcc, + 0xde, 0x0f, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0xd6, 0xab, 0x57, 0x6e, 0x8a, 0xd6, 0xba, 0x00, 0x01, 0x98, 0xe7, + 0x01, 0x87, 0x38, 0xcc, 0x06, 0x0c, 0x6c, 0x06, 0x31, 0x8c, 0xc7, 0x38, + 0xc0, 0xe7, 0x18, 0xcc, 0xe7, 0x19, 0x80, 0xc3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0e, 0x2d, 0x5e, 0xda, 0x55, 0xbb, 0x59, 0x42, + 0x00, 0x03, 0x0c, 0xc3, 0x01, 0x86, 0x19, 0x8c, 0x06, 0x0c, 0x70, 0x06, + 0x61, 0x98, 0x66, 0x18, 0xf8, 0xc3, 0x30, 0xcc, 0xc3, 0x31, 0x80, 0xc3, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0xf7, 0x6b, 0x6a, + 0xab, 0x56, 0xd6, 0xbf, 0x00, 0x03, 0x0c, 0xc3, 0x01, 0x86, 0x19, 0xfc, + 0x06, 0x0c, 0x60, 0x7e, 0x61, 0x98, 0x66, 0x18, 0xc0, 0xc3, 0x30, 0xcc, + 0xc3, 0x3f, 0x80, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x75, 0x94, 0xdb, 0x75, 0x6e, 0xda, 0xaa, 0xa2, 0x00, 0x03, 0x0c, 0xc3, + 0x01, 0x86, 0x19, 0x80, 0x06, 0x0c, 0x60, 0xc6, 0x61, 0x98, 0x66, 0x18, + 0xc0, 0xc3, 0x30, 0xcc, 0xc3, 0x30, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0xdb, 0x6b, 0xad, 0x9b, 0x27, 0x55, 0x55, 0x55, + 0x00, 0x03, 0x0c, 0xc3, 0x01, 0x86, 0x19, 0x80, 0x06, 0x0c, 0x60, 0xc6, + 0x33, 0x98, 0x66, 0x18, 0xc0, 0xc3, 0x19, 0xcc, 0xc3, 0x30, 0x00, 0xc3, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x36, 0xde, 0xb5, 0x65, + 0x75, 0x5a, 0xd5, 0x56, 0x00, 0x01, 0x98, 0xc3, 0x01, 0x86, 0x18, 0xc4, + 0x06, 0x18, 0x60, 0xce, 0x1d, 0x8c, 0xc6, 0x18, 0xc0, 0xc3, 0x0e, 0xcc, + 0xc3, 0x18, 0x80, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0xed, 0xb5, 0x6d, 0x56, 0x55, 0x55, 0x55, 0xae, 0x00, 0x00, 0xf0, 0xc3, + 0x00, 0xe6, 0x18, 0x78, 0x07, 0xf0, 0x60, 0x77, 0x01, 0x87, 0x86, 0x18, + 0xfc, 0xc3, 0x00, 0xcc, 0xc3, 0x0f, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x7a, 0xab, 0x6d, 0xda, 0xaa, 0xca, 0xd5, 0x6d, 0x58, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x56, 0xda, 0xaa, 0xea, 0xae, + 0x9b, 0x5a, 0xa9, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xd5, + 0xbb, 0xfd, 0xad, 0xad, 0x69, 0xea, 0xcb, 0x55, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x05, 0xaf, 0xb6, 0x8a, 0x6a, 0xb9, 0x5a, 0x2d, 0xba, 0xb6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x7a, 0x75, 0x6e, 0xcd, 0x52, + 0x9b, 0xdb, 0x55, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, 0xad, + 0xaf, 0x95, 0x55, 0xed, 0x55, 0x55, 0x6b, 0x55, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xea, 0xb5, 0xec, 0xfd, 0x59, 0x5a, 0xb5, 0x56, 0xaa, 0xb6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xb7, 0x6b, 0x36, 0x4a, 0xeb, 0xab, + 0x2d, 0x6a, 0x9b, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xad, 0x6f, + 0x6b, 0xeb, 0xdd, 0x7b, 0x6a, 0x55, 0xb5, 0x56, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x17, 0x76, 0xda, 0xd6, 0x5d, 0x62, 0xc6, 0xd5, 0x36, 0xaa, 0xb5, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xdb, 0x56, 0xbc, 0xf2, 0xa5, 0x5d, + 0x96, 0xaa, 0xb6, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xab, 0xee, 0xfd, + 0xd5, 0x2c, 0x6d, 0x9a, 0x75, 0x5b, 0x6a, 0xb5, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0xee, 0xad, 0x55, 0x15, 0xef, 0x54, 0xf6, 0xc5, 0x6a, 0xa9, 0xa6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x5b, 0xd6, 0xad, 0xbe, 0xb0, 0xa6, 0x35, + 0x5b, 0xd5, 0x4a, 0x9b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0xeb, 0x5d, 0xf5, + 0xaa, 0xd7, 0xf4, 0x75, 0xba, 0x55, 0xaf, 0x6e, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x37, 0x5e, 0xf7, 0x55, 0x61, 0xbc, 0x08, 0x5b, 0x55, 0x5a, 0xa9, 0xb5, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0xf6, 0xba, 0xaa, 0xaa, 0x9f, 0x69, 0xec, 0xd5, + 0x4b, 0xa9, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x2d, 0xd5, 0xed, 0x5a, + 0xf2, 0xd6, 0xae, 0xdb, 0x9e, 0x27, 0x5f, 0xb5, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, + 0x6d, 0x5b, 0xaa, 0xda, 0xae, 0x95, 0x58, 0xd5, 0x34, 0x6d, 0x68, 0xad, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x15, 0xdb, 0xd7, 0x56, 0xb5, 0xd5, 0x6d, 0x29, 0x5b, + 0x4b, 0xdb, 0x57, 0xb6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0xda, 0xac, 0xd5, 0x4b, + 0x57, 0x6a, 0x9b, 0x76, 0x5c, 0x95, 0x54, 0x2a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, + 0xb7, 0xfb, 0xab, 0xb6, 0xea, 0xad, 0x62, 0x95, 0xa1, 0xf5, 0xa9, 0xad, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x57, 0xaf, 0x6b, 0x72, 0x54, 0x99, 0xd5, 0x0e, 0xf3, + 0x5f, 0x15, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xea, 0xd4, 0xad, 0x5d, 0x35, + 0xb5, 0x34, 0xb2, 0xaa, 0x54, 0xba, 0xad, 0x55, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x5e, + 0xaf, 0xed, 0xab, 0xea, 0xb3, 0xaa, 0x6a, 0xad, 0xd5, 0xd5, 0xaa, 0xab, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x2a, 0xb9, 0xf5, 0xbb, 0xb5, 0x55, 0x64, 0x57, 0x55, 0x6b, + 0x5d, 0xd0, 0x52, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xab, 0x5b, 0xb6, 0x6d, 0x37, + 0x6f, 0xaa, 0x5b, 0xa2, 0xb5, 0x1f, 0xed, 0x73, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x65, 0xaa, + 0x6e, 0xfb, 0xd3, 0x5a, 0xd4, 0x54, 0xaa, 0x5e, 0xc3, 0xb5, 0x15, 0x56, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x07, 0xaf, 0x7f, 0xea, 0xb6, 0xaa, 0xd6, 0xad, 0xf1, 0xd2, 0xd5, + 0x56, 0x55, 0x6a, 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xbd, 0xda, 0xaf, 0x75, 0x6f, 0x5a, + 0x45, 0x26, 0xb7, 0x5b, 0x20, 0xdd, 0x55, 0x2a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xeb, 0x7f, + 0xf5, 0x4d, 0x95, 0x76, 0xd9, 0x56, 0xb5, 0x52, 0x6d, 0x12, 0xad, 0xaa, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x57, 0x3f, 0xa4, 0x8f, 0xb9, 0x6e, 0xa2, 0x6f, 0x1d, 0x6a, 0xef, + 0xb5, 0x6d, 0xaa, 0xb5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0xfd, 0x75, 0x2f, 0x7c, 0x57, 0x88, 0xf6, + 0x80, 0xb5, 0x57, 0x5c, 0xd7, 0x55, 0x54, 0xae, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x39, 0xff, 0xf6, + 0xab, 0x7a, 0x57, 0x94, 0xef, 0x0d, 0xe4, 0xea, 0xa8, 0xaa, 0xab, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0c, 0xf7, 0xff, 0x6d, 0xb7, 0x4b, 0x39, 0x17, 0x2a, 0xfa, 0xb7, 0x56, + 0xb7, 0xaa, 0xed, 0xd9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x18, 0xbe, 0xfd, 0xda, 0x9e, 0xec, 0xe6, 0xd5, + 0x52, 0x2a, 0x58, 0xa9, 0x54, 0x5a, 0x97, 0xe7, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0xe9, 0xf6, 0xbe, + 0xd4, 0x5b, 0xad, 0x63, 0x61, 0xf7, 0xb7, 0xaf, 0x55, 0x52, 0x9f, 0xee, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + 0xc9, 0xbd, 0xfb, 0x6b, 0xeb, 0xf5, 0x6b, 0x2d, 0x57, 0x52, 0x94, 0xaa, + 0xb1, 0xab, 0x4a, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0xdb, 0xcb, 0xff, 0xf5, 0x3b, 0x55, 0xa0, 0x00, + 0x45, 0x6e, 0xb5, 0xb5, 0x65, 0x52, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x2e, 0x7d, 0xdb, 0xa5, + 0xca, 0xbe, 0x80, 0x00, 0x0a, 0x54, 0xaa, 0xa5, 0x45, 0x08, 0x09, 0x15, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + 0xd8, 0xd3, 0x1b, 0xae, 0xb7, 0xea, 0x00, 0x00, 0x00, 0x95, 0xaa, 0x56, + 0xdc, 0xe1, 0x21, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x53, 0x41, 0xff, 0x77, 0xbd, 0xaa, 0x58, 0x00, 0x00, + 0x00, 0xdb, 0x75, 0xd4, 0xb2, 0xa4, 0x07, 0xea, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xef, 0x07, 0xbd, 0x65, 0xeb, + 0xa2, 0xd0, 0x00, 0x00, 0x00, 0x25, 0x4b, 0x35, 0x56, 0x80, 0x77, 0x6a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x28, + 0x01, 0x28, 0x9a, 0xb6, 0xd7, 0x60, 0x00, 0x00, 0x00, 0x0c, 0xaa, 0xaa, + 0xaa, 0x02, 0x07, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x17, 0xe0, 0x17, 0xb1, 0xbf, 0xee, 0xb4, 0xc0, 0x00, 0x00, + 0x00, 0x08, 0xaa, 0xad, 0x68, 0x54, 0x04, 0x5a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x74, 0x87, 0x77, 0x72, 0x5a, + 0xab, 0x80, 0x00, 0x00, 0x00, 0x02, 0xd4, 0xb5, 0x52, 0x08, 0x5b, 0xd4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, + 0x1f, 0xd6, 0xef, 0xda, 0xd5, 0x00, 0x00, 0x00, 0x0c, 0x01, 0x52, 0xd5, + 0x40, 0xf1, 0x55, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x9b, 0x00, 0x17, 0x4b, 0x92, 0xb7, 0xaf, 0x00, 0x00, 0x00, + 0x0e, 0x01, 0x4e, 0xaa, 0xae, 0x95, 0x55, 0x6d, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xb8, 0x11, 0x2b, 0x13, 0x76, 0xef, + 0x54, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x54, 0xaa, 0xaa, 0xb5, 0xad, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x40, 0x00, + 0x7e, 0x7c, 0x65, 0xf4, 0x78, 0x00, 0x00, 0x00, 0x1f, 0x00, 0xab, 0x56, + 0xd5, 0x55, 0x59, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x0a, 0x40, 0x42, 0x6d, 0xce, 0xe5, 0xae, 0x54, 0x00, 0x00, 0x00, + 0x18, 0x00, 0x6d, 0x75, 0x5d, 0x55, 0x4d, 0x52, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x82, 0x03, 0xdc, 0x54, 0xbf, 0x61, + 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xad, 0xa2, 0xb5, 0x60, 0xad, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 0x00, 0x16, + 0xd9, 0xb5, 0xa4, 0xc7, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 0xea, + 0xae, 0xd5, 0x57, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x54, 0x04, 0x0d, 0x76, 0xbb, 0x4b, 0xbc, 0x58, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x36, 0x95, 0xa9, 0x55, 0x54, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x50, 0x08, 0x5b, 0xc5, 0x3d, 0x97, 0x0a, + 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xb6, 0xab, 0x2b, 0x55, 0xab, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x24, 0x20, 0x3d, + 0x59, 0x7b, 0x76, 0x37, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x6d, + 0x75, 0xb5, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0xf0, 0x01, 0xff, 0x21, 0xa8, 0xc3, 0x74, 0xa8, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x1b, 0xa9, 0x4b, 0x55, 0x55, 0x2a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x25, 0xc0, 0x41, 0xca, 0x9c, 0x77, 0x58, 0x9d, + 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x56, 0xb4, 0xad, 0xb2, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x80, 0x0f, 0xbe, + 0xc0, 0xf6, 0xd5, 0xb3, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x54, + 0xa5, 0xaa, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x17, 0x04, 0x87, 0xbc, 0x6a, 0x3b, 0xac, 0x9d, 0x58, 0x00, 0x00, 0x03, + 0xe0, 0x00, 0x16, 0xab, 0x55, 0x4a, 0xd6, 0xa5, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x5c, 0x00, 0x1f, 0x54, 0xc9, 0x2a, 0xb7, 0xa6, + 0xd8, 0x0f, 0x00, 0x07, 0xf8, 0x00, 0x15, 0x6a, 0x55, 0x5a, 0xa4, 0xaa, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x08, 0x74, 0xca, + 0x9c, 0x5a, 0xa8, 0xc5, 0x30, 0x1f, 0x80, 0x0f, 0xfc, 0x00, 0x0d, 0x55, + 0xaa, 0xa5, 0x55, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0xf0, 0x20, 0xea, 0x5a, 0xb0, 0xe7, 0x95, 0x7d, 0x10, 0x3f, 0xc0, 0x1f, + 0xfe, 0x00, 0x0a, 0xaa, 0xaa, 0xad, 0x4a, 0x95, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0xf4, 0x02, 0x7d, 0xb5, 0x8f, 0x9c, 0xaa, 0xe9, + 0xa0, 0x3f, 0xc0, 0x1f, 0xfe, 0x00, 0x06, 0xb5, 0x54, 0xa9, 0x2a, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x40, 0x47, 0xeb, 0xab, + 0x75, 0x51, 0x55, 0x4d, 0xd8, 0x3f, 0xe0, 0x3f, 0x3f, 0x00, 0x0a, 0xaa, + 0xa9, 0x4a, 0xaa, 0xad, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, + 0xc0, 0x06, 0xff, 0xe5, 0xb6, 0xbb, 0xa9, 0x34, 0x48, 0x30, 0xe0, 0x3c, + 0x0f, 0x00, 0x0a, 0xaa, 0x8a, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xaf, 0x80, 0x9f, 0xa1, 0x8d, 0xb5, 0xd6, 0x93, 0xcd, + 0x90, 0x62, 0x60, 0x3c, 0x27, 0x00, 0x06, 0xaa, 0xb5, 0xaa, 0xaa, 0xa9, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f, 0x92, 0x3f, 0xb5, 0x36, + 0x56, 0xb5, 0x9d, 0x55, 0x90, 0x62, 0x60, 0x38, 0x17, 0x80, 0x0d, 0x54, + 0xaa, 0x54, 0xaa, 0x9a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x7a, + 0x00, 0xba, 0xab, 0x73, 0xe7, 0xa2, 0xb6, 0x55, 0x2c, 0x61, 0x60, 0x38, + 0x17, 0x80, 0x09, 0x6b, 0x4a, 0xd5, 0x4a, 0x92, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0d, 0xfe, 0x03, 0x6d, 0xea, 0x08, 0x51, 0x1d, 0x2b, 0x35, + 0x08, 0x61, 0x60, 0x38, 0x07, 0x80, 0x06, 0xda, 0xaa, 0xa9, 0x55, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x27, 0xf8, 0x4e, 0xfb, 0x89, 0xde, + 0x35, 0xea, 0x6b, 0x72, 0x28, 0x60, 0x70, 0x38, 0x07, 0x80, 0x05, 0x52, + 0xaa, 0xaa, 0x95, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf8, + 0x0d, 0x63, 0xbd, 0xe3, 0x57, 0x55, 0xb6, 0x49, 0xcc, 0x20, 0x7f, 0xf8, + 0x07, 0x80, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xad, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x5d, 0xe1, 0x34, 0xc6, 0xab, 0xa7, 0x91, 0x77, 0x37, 0xcc, + 0x48, 0x30, 0x9f, 0x3c, 0x07, 0x80, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0x69, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x3b, 0xc0, 0x34, 0xdb, 0x4e, 0xf9, + 0xae, 0xd5, 0x54, 0xe1, 0xb4, 0x19, 0x3f, 0xfe, 0x0f, 0x00, 0x05, 0x55, + 0x55, 0x55, 0x52, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x7f, 0x89, + 0xf1, 0xf7, 0xe5, 0x57, 0xea, 0x8d, 0x4c, 0xda, 0xac, 0x13, 0xff, 0xff, + 0x80, 0x00, 0x0a, 0xd5, 0xaa, 0xa4, 0x95, 0x54, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xf7, 0x02, 0x53, 0x6c, 0x72, 0x10, 0xa3, 0x6a, 0x74, 0xea, + 0x34, 0x07, 0xff, 0xff, 0xe0, 0x00, 0x05, 0x4e, 0x54, 0x95, 0x55, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0xfc, 0x97, 0xd6, 0x55, 0xb6, 0xab, + 0xb7, 0x45, 0x46, 0xad, 0xf4, 0x1f, 0xff, 0xff, 0xfe, 0x00, 0x05, 0x2a, + 0xd5, 0x54, 0x95, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xcf, 0x0e, + 0xfb, 0x2d, 0x12, 0xd4, 0xb8, 0xb6, 0xeb, 0x6a, 0x10, 0x3f, 0xff, 0xff, + 0xff, 0x00, 0x02, 0xda, 0x8a, 0xab, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x57, 0xbc, 0x3a, 0xc6, 0x0d, 0x76, 0xb1, 0x77, 0x15, 0x2a, 0x56, + 0x34, 0x7f, 0xff, 0xff, 0xff, 0x80, 0x02, 0xa5, 0x75, 0x2a, 0x52, 0xaa, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x0f, 0xfc, 0xdf, 0x75, 0x9d, 0x5a, 0x67, + 0x15, 0x59, 0xb3, 0x6c, 0x4c, 0x7f, 0xff, 0xff, 0xff, 0x80, 0x05, 0x55, + 0x8a, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf9, 0xdb, + 0xed, 0x36, 0x5a, 0xeb, 0xad, 0x6b, 0x57, 0x5d, 0xa4, 0x7f, 0xff, 0xff, + 0xf3, 0x80, 0x05, 0x54, 0xb2, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x7f, 0xf4, 0x5a, 0xaa, 0xdb, 0x40, 0x20, 0xea, 0xaa, 0xa8, 0x19, + 0xe8, 0x1f, 0xff, 0xff, 0xe7, 0x00, 0x02, 0x55, 0x4b, 0xd5, 0x55, 0x4a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0xff, 0xf2, 0xb5, 0x7d, 0x56, 0xaa, 0x76, + 0xa5, 0xce, 0xb4, 0xd1, 0x2c, 0x0f, 0xff, 0xff, 0x0f, 0x00, 0x02, 0xa5, + 0x5a, 0x2a, 0x55, 0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc1, 0x31, + 0x9a, 0x8d, 0x61, 0x2e, 0xb2, 0xb5, 0x57, 0x59, 0x88, 0x07, 0xff, 0xf8, + 0x7e, 0x06, 0x00, 0xaa, 0x65, 0xd2, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1f, 0x7e, 0x02, 0x55, 0x67, 0xb5, 0x5b, 0x05, 0xfa, 0xab, 0x0a, 0x8d, + 0xe4, 0x03, 0xff, 0xc3, 0xfe, 0x07, 0x01, 0xaa, 0xaa, 0x26, 0xaa, 0xa9, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x16, 0x7d, 0x10, 0x57, 0x9d, 0x4a, 0x8a, 0xd7, + 0x95, 0x5a, 0xd5, 0x4d, 0x58, 0x00, 0xfc, 0x1f, 0xe6, 0x03, 0xc1, 0x55, + 0x52, 0xd5, 0x55, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0xe1, 0x42, 0xa4, + 0x7d, 0xd7, 0xba, 0xb0, 0x24, 0xd5, 0x97, 0xc5, 0xd2, 0x00, 0x00, 0x7f, + 0x87, 0x03, 0xe0, 0x42, 0xaa, 0x95, 0x55, 0x4b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0d, 0x42, 0x17, 0xfb, 0x8c, 0xac, 0x46, 0xae, 0xdd, 0xb3, 0x68, 0x92, + 0x6c, 0x03, 0x03, 0xfe, 0x0f, 0x01, 0xe0, 0x5a, 0x55, 0x62, 0xaa, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x3d, 0x0a, 0x32, 0xd5, 0x7b, 0xc9, 0xde, 0xad, + 0x91, 0x4a, 0xaa, 0xc6, 0x68, 0x21, 0xff, 0xf8, 0x7f, 0x00, 0x60, 0x2a, + 0xa9, 0x2e, 0xa9, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x64, 0xb3, 0x18, + 0x8e, 0xae, 0xb4, 0x46, 0x9a, 0xbb, 0x54, 0xd5, 0xb4, 0x30, 0xff, 0xe0, + 0xff, 0x80, 0x00, 0x52, 0xa5, 0x51, 0x55, 0x4a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, + 0x82, 0xc1, 0x52, 0xb3, 0xcb, 0xc5, 0xd4, 0xda, 0xd3, 0x4a, 0x68, 0x87, + 0x68, 0x30, 0x3f, 0x03, 0xff, 0x80, 0x00, 0x2a, 0xaa, 0x55, 0x45, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x5b, 0xc6, 0xa9, 0x19, 0x74, 0x3d, 0xa9, 0x92, + 0xab, 0x5b, 0x95, 0xb0, 0x28, 0x78, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x15, + 0x2a, 0x95, 0x2a, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x10, 0x0f, 0x6b, 0xa2, + 0xb7, 0x22, 0x61, 0x2b, 0x52, 0xaa, 0x33, 0x1d, 0xa0, 0x7c, 0x00, 0x0f, + 0xff, 0xe0, 0x00, 0x14, 0xa4, 0xaa, 0xa9, 0x52, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, + 0x00, 0x23, 0x27, 0x64, 0x8d, 0xfb, 0x64, 0xa7, 0x5a, 0xaa, 0xd3, 0x5a, + 0xa0, 0x7c, 0x00, 0x3f, 0xff, 0xe0, 0x00, 0x05, 0x29, 0x52, 0x45, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x4a, 0x5f, 0x66, 0x6a, 0xab, 0x22, 0xaf, 0xec, + 0xa9, 0x55, 0x17, 0x17, 0xa0, 0xfe, 0x00, 0x7f, 0xff, 0xf0, 0x00, 0x02, + 0xaa, 0x4a, 0xaa, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x8d, 0x83, 0x49, 0xad, + 0x9a, 0x57, 0x50, 0x6b, 0x6b, 0x5a, 0xd1, 0x1a, 0x80, 0xff, 0x00, 0xff, + 0xff, 0xf0, 0x00, 0x05, 0x52, 0x95, 0x29, 0x55, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c, + 0x1b, 0x4b, 0xcb, 0x45, 0x7b, 0x4e, 0x4b, 0x5d, 0x2a, 0xd5, 0x16, 0x29, + 0x41, 0xff, 0x87, 0xff, 0xff, 0xf8, 0x00, 0x01, 0x2a, 0xa5, 0x4a, 0x52, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x52, 0x98, 0x9d, 0x0e, 0x95, 0x65, 0x38, 0x95, + 0x55, 0x6a, 0xab, 0x35, 0x81, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x01, + 0xa9, 0x14, 0xa9, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0xe3, 0x2b, 0x74, 0x4d, + 0xb5, 0x55, 0xd5, 0x95, 0x69, 0x4a, 0xac, 0x6e, 0x03, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0x00, 0x01, 0x25, 0x65, 0x2a, 0x95, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x9a, 0xb7, 0x0b, 0xb0, 0x6f, 0xfc, 0xfd, 0x6a, 0x8b, 0xd5, 0x4e, 0xa8, + 0x03, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0x01, 0x49, 0x14, 0xa5, 0x6a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x02, 0x94, 0xab, 0x3d, 0xc9, 0x6b, 0xb5, 0x43, 0xee, + 0xb6, 0x95, 0x54, 0x9a, 0x07, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, + 0xaa, 0x54, 0xaa, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x13, 0x9f, 0x68, 0x5b, + 0xff, 0xfa, 0xd7, 0xfa, 0xa5, 0x6a, 0xac, 0xd4, 0x07, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x00, 0x00, 0x55, 0x53, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04, + 0x65, 0x3c, 0x8b, 0x93, 0x87, 0x76, 0x75, 0xf5, 0x57, 0x55, 0x5c, 0xa8, + 0x0f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x0b, 0x54, 0x95, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x2a, 0x7b, 0xfd, 0x75, 0xba, 0xae, 0xfe, 0x44, 0x5a, + 0x8a, 0xca, 0x9c, 0xf0, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, + 0x14, 0x4a, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0xd8, 0xa2, 0xbd, 0x59, 0x52, + 0x8e, 0xec, 0x48, 0xf1, 0x2d, 0x52, 0x9c, 0xa0, 0x0f, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x02, 0x00, 0x02, 0x95, 0x54, 0x92, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x35, + 0x5f, 0xed, 0x6a, 0xf2, 0x95, 0x19, 0x09, 0xaa, 0x6a, 0x5d, 0x48, 0xc0, + 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x02, 0xaa, 0x52, 0xaa, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x04, 0x22, 0xa6, 0xc3, 0xdf, 0xd0, 0x66, 0x29, 0xf0, 0x01, 0x6a, + 0xca, 0xd5, 0x59, 0x80, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x80, + 0x05, 0x2a, 0xaa, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xa4, 0x03, 0xf2, 0x61, 0xed, + 0x17, 0xe2, 0x02, 0xaa, 0x99, 0x2a, 0x98, 0x80, 0x07, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x40, 0x02, 0x55, 0x55, 0x2a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x09, 0x05, + 0x88, 0xa7, 0x47, 0xdc, 0xc0, 0x00, 0x2a, 0x6b, 0x4a, 0x6a, 0xb0, 0x00, + 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x20, 0x01, 0x55, 0x55, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x2e, 0x89, 0x11, 0xfb, 0x87, 0x9c, 0x90, 0x64, 0xaa, 0x9a, + 0x4a, 0xa9, 0x1a, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x30, + 0x00, 0xa8, 0x42, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x2b, 0x16, 0x2b, 0x85, 0x09, 0xf8, + 0x83, 0x45, 0x5d, 0xad, 0x95, 0x49, 0x5c, 0x08, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xe0, 0x10, 0x00, 0xae, 0xea, 0x4a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x49, 0x28, + 0x3b, 0xf5, 0xbd, 0x30, 0x14, 0x96, 0x95, 0x6a, 0xd2, 0xb5, 0xaa, 0x10, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x18, 0x00, 0xa9, 0x15, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x19, 0x26, 0x58, 0x76, 0x4a, 0x1e, 0xe1, 0x7a, 0xba, 0xb1, 0x5b, + 0x4a, 0xab, 0x2c, 0x10, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x08, + 0x00, 0x2b, 0x6a, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x11, 0x21, 0x4d, 0x78, 0x6d, 0x20, + 0x0a, 0x84, 0xda, 0xaf, 0x55, 0x56, 0x52, 0x20, 0x3f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0c, 0x00, 0x54, 0xaa, 0xa5, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xe8, 0x62, + 0xcd, 0x49, 0xd8, 0x42, 0xb4, 0xb8, 0x96, 0x3a, 0xa5, 0x54, 0xd4, 0x00, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x04, 0x00, 0x14, 0xaa, 0x4a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x2d, 0x18, 0x4e, 0x0e, 0x61, 0xb0, 0x0a, 0xab, 0x6b, 0xaa, 0x37, + 0x0d, 0x5a, 0xa8, 0x00, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x06, + 0x00, 0x2b, 0x4a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0xb1, 0xd8, 0x5f, 0xc1, 0x90, 0x55, + 0x55, 0x4a, 0x32, 0xed, 0x79, 0x49, 0x50, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x06, 0x00, 0x12, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x16, 0x00, 0xd1, + 0xac, 0x89, 0x91, 0x4a, 0xaa, 0xaa, 0xa9, 0xb2, 0xc5, 0x65, 0x68, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x15, 0x2a, 0x4a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + 0x64, 0x54, 0x81, 0xcf, 0x89, 0x00, 0x1f, 0xf2, 0xaa, 0xd5, 0x6b, 0x35, + 0x5a, 0xad, 0xa8, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x03, + 0x00, 0x05, 0x6a, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x23, 0xf6, 0x52, 0x28, 0x19, 0xd5, + 0x45, 0x55, 0x49, 0x54, 0xa5, 0x6a, 0xa0, 0x01, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x03, 0x00, 0x15, 0x24, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x09, 0x18, 0x04, 0x6c, + 0x64, 0x61, 0x21, 0x95, 0xad, 0x56, 0xaa, 0xd7, 0xab, 0x55, 0x50, 0x03, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x01, 0x80, 0x04, 0xaa, 0x94, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + 0x12, 0x46, 0x20, 0xdc, 0xc4, 0x01, 0x01, 0xaa, 0xaa, 0xa9, 0x5b, 0x49, + 0x2a, 0xad, 0xa0, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x01, + 0x80, 0x02, 0xa4, 0xa5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x44, 0x08, 0x00, 0xd1, 0x84, 0x20, 0x05, 0xaa, + 0xaa, 0x95, 0x66, 0xaa, 0xaa, 0xaa, 0xa0, 0x03, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x01, 0x80, 0x05, 0x55, 0x29, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0c, 0xa8, 0x89, 0x99, + 0x00, 0x22, 0x03, 0xd5, 0x4a, 0xaa, 0xa7, 0x4d, 0x5a, 0xd5, 0x40, 0x07, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x01, 0x80, 0x02, 0x49, 0x4a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, + 0x18, 0x02, 0x03, 0x24, 0x10, 0xa8, 0x2f, 0x6a, 0xaa, 0xaa, 0x45, 0x51, + 0x4a, 0xb5, 0x40, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, + 0x80, 0x04, 0x95, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x01, 0x05, 0x48, 0x07, 0xae, 0x83, 0x02, 0x8c, 0x2a, + 0x95, 0x52, 0xcd, 0x56, 0xad, 0x56, 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x00, 0xc0, 0x01, 0x52, 0x52, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x58, 0x98, 0x2f, 0x30, + 0x02, 0x82, 0x01, 0x6a, 0xaa, 0xaa, 0x8d, 0x29, 0x35, 0xb5, 0x04, 0x07, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, 0xc0, 0x02, 0x94, 0x95, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x45, 0x30, 0x1f, 0xa0, 0x25, 0x1d, 0x15, 0x4a, 0xa5, 0x51, 0xad, 0x55, + 0x6d, 0x6a, 0x84, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, + 0xc0, 0x01, 0x29, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0xa1, 0x2d, 0x21, 0x7f, 0x40, 0x4d, 0xb0, 0x35, 0x55, + 0x15, 0x15, 0x79, 0x25, 0x4a, 0xca, 0x04, 0x0f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x00, 0xc0, 0x02, 0x52, 0x96, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x40, 0x7f, 0x24, + 0x8a, 0x58, 0xad, 0x55, 0x55, 0x52, 0x0a, 0x5a, 0xaa, 0xbb, 0x04, 0x0f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xc0, 0x00, 0xa5, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x09, + 0x50, 0x42, 0xfd, 0xc0, 0x59, 0x53, 0x53, 0x4c, 0xaa, 0x54, 0x5a, 0xa2, + 0xad, 0xaa, 0x04, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0xc0, 0x01, 0x4d, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x02, 0x15, 0x90, 0x7d, 0x15, 0x76, 0xac, 0xad, 0x52, + 0x95, 0x55, 0xaa, 0x4c, 0xa5, 0x54, 0x04, 0x0f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x00, 0xc0, 0x00, 0xa5, 0x12, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0c, 0x83, 0x01, 0xff, 0xf9, + 0x15, 0x29, 0x51, 0x55, 0x52, 0x2c, 0xa2, 0x54, 0xab, 0x6c, 0x04, 0x0f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x80, 0x01, 0x28, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, + 0x06, 0x01, 0xff, 0xe9, 0x55, 0xd5, 0x56, 0xa5, 0x55, 0xaa, 0xad, 0x51, + 0x35, 0x54, 0x04, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x80, 0x00, 0x4a, 0xa9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x08, 0x31, 0x1c, 0x12, 0xf4, 0xc5, 0x44, 0x5a, 0xaa, 0x49, + 0xaa, 0xa9, 0xa8, 0x95, 0x55, 0x50, 0x04, 0x0f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x01, 0x80, 0x01, 0x52, 0x82, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x40, 0x48, 0x1c, 0x41, 0x3e, 0x2e, + 0x8b, 0x54, 0xaa, 0xab, 0x52, 0xa5, 0x45, 0x24, 0x95, 0x50, 0x06, 0x0f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x01, 0x24, 0x5a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x00, + 0x38, 0x01, 0x1d, 0x64, 0x9a, 0xa9, 0x2a, 0x94, 0xaa, 0xab, 0x55, 0x55, + 0xaa, 0xd8, 0x02, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03, + 0x00, 0x01, 0x4a, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x13, 0xc8, 0x00, 0xb0, 0x02, 0x3e, 0x96, 0x35, 0x6a, 0xaa, 0x55, + 0x4a, 0x95, 0x4a, 0x54, 0x55, 0x28, 0x03, 0x0f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xc0, 0x01, 0x29, 0x4a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x83, 0x49, 0x20, 0x8c, 0x78, 0xb5, + 0x65, 0x4a, 0xaa, 0xa6, 0xaa, 0xa5, 0x29, 0x45, 0xaa, 0xa8, 0x03, 0x0f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x70, 0x01, 0x45, 0x28, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x03, 0x20, + 0x00, 0x30, 0x75, 0x4c, 0x95, 0x55, 0x54, 0xa9, 0x52, 0x95, 0x52, 0x95, + 0x2a, 0xa8, 0x01, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x18, 0x00, 0x94, 0xa5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x0d, 0x0c, 0x0c, 0x44, 0x18, 0xe5, 0xb9, 0xb5, 0x54, 0x92, 0x96, + 0xaa, 0x55, 0x4a, 0x69, 0x55, 0x20, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x29, 0x29, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x2e, 0x08, 0x1c, 0x01, 0x7b, 0xdc, 0x96, + 0x4a, 0xaa, 0xaa, 0xa9, 0x4a, 0xaa, 0x95, 0x0a, 0x73, 0x50, 0x00, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x01, 0x52, 0x52, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x20, 0x30, + 0x44, 0x79, 0x88, 0xd4, 0x95, 0x49, 0x54, 0xab, 0x52, 0x94, 0xa4, 0xaa, + 0xc6, 0x51, 0xe0, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, + 0x00, 0x00, 0x8a, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x38, 0x2a, 0x21, 0x01, 0xfb, 0xa0, 0x7d, 0x54, 0xb5, 0x55, 0x54, + 0x95, 0x55, 0x29, 0x55, 0x29, 0x57, 0xf8, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x00, 0x00, 0x02, 0x50, 0x52, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x78, 0x90, 0x00, 0x0d, 0xfb, 0xca, 0xd2, + 0xaa, 0x92, 0x49, 0x55, 0x55, 0x2a, 0x4a, 0x4a, 0xd3, 0x57, 0xfc, 0x1f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x00, 0x00, 0x02, 0x95, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39, 0x20, 0xa4, + 0x13, 0xfd, 0xab, 0x2a, 0x52, 0xa5, 0x52, 0x55, 0x52, 0xa9, 0x55, 0x55, + 0x2a, 0x57, 0xff, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc6, 0x00, + 0x00, 0x0d, 0x24, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x30, 0xc0, 0x00, 0x77, 0xb5, 0x55, 0x69, 0x4a, 0xaa, 0x96, 0xaa, + 0x94, 0xaa, 0x91, 0x45, 0x55, 0x4f, 0xff, 0x03, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xcf, 0x00, 0x00, 0x1e, 0x55, 0x2a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x30, 0x81, 0x00, 0x67, 0xb4, 0x74, 0x52, + 0x55, 0x55, 0x2a, 0xaa, 0xaa, 0x52, 0x55, 0x35, 0x52, 0xaf, 0xff, 0x81, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x1e, 0xa0, 0x48, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xe3, 0x00, 0x08, + 0x86, 0x4a, 0xd4, 0xd5, 0x54, 0x91, 0x49, 0x55, 0x51, 0x54, 0x95, 0x49, + 0x56, 0x4f, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0x80, + 0x00, 0x3e, 0x0b, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0xc4, 0x02, 0x00, 0x7f, 0xbd, 0x8a, 0x25, 0x49, 0x55, 0x2a, 0xb5, + 0x55, 0x52, 0xa4, 0x96, 0xac, 0x8f, 0xff, 0xe0, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0x80, 0x00, 0x7e, 0x54, 0xa4, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x43, 0x80, 0x20, 0x21, 0x4d, 0x3f, 0x52, 0xb4, + 0x55, 0x2a, 0x55, 0x55, 0x4a, 0xa4, 0x95, 0x32, 0xa5, 0x4f, 0xff, 0xe0, + 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xc0, 0x00, 0xfe, 0x49, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe8, 0x04, 0x08, + 0x1a, 0x46, 0xd4, 0x49, 0xaa, 0xa4, 0xaa, 0xaa, 0x54, 0x95, 0x2a, 0xc4, + 0x94, 0x8f, 0xff, 0xf0, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xe0, + 0x01, 0xfe, 0x92, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x8e, 0x40, 0x80, 0x00, 0x74, 0x44, 0x51, 0x55, 0x64, 0xa9, 0x49, 0x55, + 0x49, 0x51, 0x52, 0x5a, 0x2a, 0x1f, 0xff, 0xf8, 0x07, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0xf0, 0x07, 0xfe, 0x24, 0x52, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x90, 0x00, 0x41, 0xeb, 0x12, 0xab, 0x52, + 0xa9, 0x4a, 0xaa, 0xa5, 0x52, 0x95, 0x2a, 0xa2, 0xa8, 0x1f, 0xff, 0xf8, + 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xf8, 0x1f, 0xfe, 0x52, 0x8a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x3b, 0x81, 0x08, 0x05, + 0xe3, 0x15, 0xa5, 0x36, 0x95, 0x4a, 0x4a, 0xaa, 0x45, 0x2a, 0xa2, 0xac, + 0x00, 0x3f, 0xff, 0xfc, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff, + 0xff, 0xfe, 0x04, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xb2, 0x00, 0x00, 0x80, 0xe8, 0x52, 0xac, 0xa8, 0xa4, 0x92, 0xa9, 0x4a, + 0x95, 0x51, 0x2d, 0x50, 0xe1, 0xff, 0xff, 0xfe, 0x00, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0xff, 0xff, 0xfe, 0x29, 0x05, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x35, 0x10, 0x09, 0xa9, 0x4a, 0xaa, 0xaa, + 0xa9, 0x54, 0x95, 0x2a, 0xa4, 0x8a, 0xa9, 0x43, 0xff, 0xff, 0xff, 0xfe, + 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff, 0xff, 0xfe, 0x12, 0xa9, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2e, 0x01, 0x03, + 0x34, 0xa5, 0x19, 0x25, 0x55, 0x55, 0x55, 0x55, 0x15, 0x55, 0x45, 0x53, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x1f, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff, + 0xff, 0xfe, 0x04, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x49, 0x3c, 0x00, 0x34, 0x75, 0x4a, 0xa2, 0xaa, 0x92, 0x92, 0x92, 0x54, + 0x52, 0x54, 0x99, 0x53, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0f, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0xff, 0xff, 0xff, 0x14, 0x94, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x78, 0x12, 0xfc, 0xaa, 0x92, 0x2d, 0x54, + 0xa4, 0xa5, 0x2a, 0x92, 0x94, 0x92, 0xa2, 0xa3, 0xff, 0xff, 0xff, 0xff, + 0x80, 0x0f, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff, 0xff, 0xff, 0x01, 0x51, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x16, 0xf0, 0x80, 0x71, + 0xc5, 0x2a, 0x65, 0x25, 0x55, 0x4a, 0x52, 0xaa, 0x51, 0x52, 0x95, 0x21, + 0xff, 0xff, 0xff, 0xff, 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0x81, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x8e, 0xa0, 0x00, 0xb3, 0x94, 0xa4, 0xa9, 0x55, 0x45, 0x54, 0xa5, 0x25, + 0x25, 0x2a, 0x65, 0x41, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x07, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x80, 0x4a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xa0, 0x0f, 0x42, 0x13, 0x46, 0x94, 0x94, 0xa5, 0x4a, + 0x54, 0x92, 0x88, 0xa8, 0x49, 0x55, 0x4a, 0x51, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x07, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xe0, 0x52, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x2d, 0x00, 0x87, 0x56, + 0x4b, 0x2a, 0x99, 0x55, 0x4a, 0xaa, 0x55, 0x4a, 0x92, 0xa2, 0x54, 0xa8, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x07, 0xff, 0xff, 0xff, 0xfd, 0x8f, 0xff, + 0xff, 0xff, 0xfe, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x88, + 0x18, 0x04, 0x1f, 0x11, 0x51, 0x51, 0x0b, 0x54, 0x94, 0xa5, 0x52, 0x92, + 0x55, 0x54, 0x95, 0x20, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0f, 0xff, 0xff, + 0xff, 0xf9, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x89, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x11, 0xe0, 0x38, 0x01, 0x3e, 0x4d, 0x0a, 0x55, 0x5a, 0x55, + 0x55, 0x4a, 0x25, 0x24, 0x81, 0x25, 0x29, 0x48, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0x1f, 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xc2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x80, 0xf0, 0x90, 0x7e, 0xd4, + 0x68, 0x92, 0xaa, 0x54, 0x92, 0x92, 0xa9, 0x55, 0x2e, 0xaa, 0xa2, 0x58, + 0x7f, 0xff, 0xff, 0xff, 0xfc, 0x3f, 0xff, 0xff, 0xff, 0xe0, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x04, + 0x40, 0x00, 0x49, 0xe2, 0x8a, 0xa9, 0x54, 0x95, 0x2a, 0x54, 0x4a, 0x48, + 0x91, 0x51, 0x2a, 0xc8, 0x7f, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, + 0xff, 0xc0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xe2, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x2e, 0x00, 0x00, 0x03, 0x79, 0x4a, 0xa9, 0x45, 0x49, 0x54, + 0xa4, 0x89, 0x49, 0x52, 0x8a, 0x85, 0x4a, 0x98, 0x7f, 0xff, 0xff, 0xff, + 0xfe, 0x7f, 0xff, 0xff, 0xff, 0x80, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xc4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x48, 0x44, 0x91, 0x65, 0x55, + 0x4a, 0x54, 0x96, 0x85, 0x55, 0x52, 0xaa, 0x8a, 0x1a, 0xaa, 0x59, 0x30, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0xff, 0xff, 0xfe, 0x01, 0x0f, 0xff, + 0xff, 0xff, 0xff, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x20, 0x00, + 0x00, 0x02, 0xc3, 0x50, 0x29, 0x49, 0x2d, 0x35, 0x24, 0x54, 0x89, 0x32, + 0x52, 0x91, 0x49, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xff, + 0xfc, 0x01, 0x0f, 0xff, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x20, 0x08, 0x80, 0x00, 0x87, 0x4b, 0x42, 0x95, 0x2a, 0x4a, + 0x4a, 0x89, 0x52, 0x44, 0x45, 0x25, 0x55, 0x10, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x98, 0x7f, 0xff, 0xf0, 0x01, 0x0f, 0xff, 0xff, 0xff, 0xfc, 0x09, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x40, 0x40, 0x11, 0x15, 0x6a, 0x92, + 0x4d, 0x29, 0x4a, 0xaa, 0xa4, 0xaa, 0x55, 0x54, 0x9a, 0x74, 0x44, 0xb1, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8c, 0x1f, 0xff, 0x00, 0x01, 0x0f, 0xff, + 0xff, 0xff, 0xf0, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x80, 0x01, 0x48, 0x54, 0x94, 0xa6, 0xa9, 0x52, 0x45, 0x24, 0x84, 0x92, + 0xa4, 0x85, 0x2a, 0x43, 0xff, 0xff, 0xff, 0xff, 0xff, 0x84, 0x00, 0x00, + 0x00, 0x01, 0x1f, 0xff, 0xff, 0xff, 0xc0, 0x92, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x09, 0x02, 0x03, 0x53, 0x15, 0x2a, 0x49, 0x4a, 0xa5, + 0x49, 0x29, 0x29, 0x24, 0x2a, 0xd5, 0x54, 0xa3, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xc6, 0x00, 0x00, 0x00, 0x03, 0x1f, 0xff, 0xff, 0xfe, 0x01, 0x24, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x20, 0x26, 0xd4, 0xa2, + 0x49, 0xb5, 0x15, 0x4a, 0x52, 0xa9, 0x4a, 0x92, 0xa5, 0x12, 0x52, 0xa3, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc6, 0x00, 0x00, 0x00, 0x03, 0x1f, 0xff, + 0xff, 0xf0, 0x14, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x44, + 0x00, 0x0c, 0xc4, 0xa4, 0xa8, 0x25, 0x2a, 0xaa, 0x84, 0x45, 0x28, 0xa4, + 0xa8, 0xa5, 0x4a, 0x43, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc2, 0x00, 0x00, + 0x00, 0x06, 0x1f, 0xff, 0xff, 0xc0, 0x25, 0x24, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x80, 0x12, 0x01, 0x11, 0x12, 0x8a, 0x95, 0x49, 0x55, 0x49, + 0x2a, 0xaa, 0x45, 0x0a, 0x4a, 0x94, 0xaa, 0x90, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xc2, 0x00, 0x00, 0x00, 0x06, 0x1f, 0xff, 0xff, 0x02, 0x48, 0x92, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x08, 0x00, 0x22, 0x01, 0x24, 0x95, + 0x21, 0x55, 0x55, 0x2a, 0x54, 0x92, 0x94, 0xa8, 0xa9, 0x2a, 0x92, 0xa8, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0x82, 0x00, 0x00, 0x00, 0x06, 0x0f, 0xff, + 0xfe, 0x02, 0x49, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 0x40, + 0x00, 0xc4, 0x89, 0x11, 0x54, 0x95, 0x29, 0x49, 0x49, 0x24, 0x29, 0x12, + 0x92, 0xa5, 0x55, 0x28, 0x01, 0xff, 0xff, 0xff, 0xff, 0x82, 0x00, 0x00, + 0x00, 0x02, 0x0f, 0xff, 0xfc, 0x14, 0x92, 0x49, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x42, 0x06, 0x44, 0x45, 0x08, 0x92, 0x24, 0x95, 0xaa, 0xa5, 0x52, + 0x92, 0x55, 0x42, 0x52, 0xaa, 0x4a, 0x49, 0x4a, 0x80, 0x0f, 0xff, 0xff, + 0xff, 0x84, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x04, 0x92, 0x49, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x2a, 0x80, 0x01, 0x95, 0x2a, 0x8a, + 0xa0, 0x95, 0x2a, 0x95, 0x54, 0xa4, 0x54, 0x84, 0x44, 0x95, 0x55, 0x29, + 0x54, 0x00, 0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, + 0xe0, 0x29, 0x24, 0x92, 0x00, 0x00, 0x00, 0x00, 0x22, 0x04, 0x03, 0x03, + 0x42, 0x12, 0x52, 0x2a, 0x15, 0x55, 0x54, 0xa8, 0x92, 0xa9, 0x49, 0x29, + 0x54, 0xaa, 0x92, 0x52, 0xa5, 0x40, 0x07, 0xff, 0xff, 0x00, 0x15, 0x50, + 0x92, 0x44, 0x07, 0xff, 0xc0, 0x52, 0x54, 0xaa, 0x00, 0x00, 0x00, 0x00, + 0x84, 0x02, 0x86, 0x03, 0x08, 0x41, 0x48, 0x94, 0xa5, 0x52, 0xaa, 0x8a, + 0x49, 0x52, 0x92, 0x45, 0x49, 0x55, 0x2a, 0xaa, 0x94, 0x96, 0x00, 0x7f, + 0xfe, 0x01, 0x55, 0x2b, 0x25, 0x50, 0x03, 0xff, 0x00, 0xa4, 0x91, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x88, 0x2c, 0x18, 0x14, 0x0a, 0xaa, 0x92, 0x55, + 0x49, 0x55, 0x4a, 0xa9, 0x52, 0x44, 0x92, 0x94, 0x92, 0x92, 0xca, 0x4a, + 0x55, 0x27, 0xa0, 0x0f, 0xf8, 0x05, 0x35, 0x49, 0x68, 0x91, 0x00, 0xf8, + 0x04, 0x95, 0x25, 0x29, 0x00, 0x00, 0x00, 0x01, 0x08, 0x04, 0x18, 0x00, + 0x08, 0x04, 0x49, 0x08, 0x55, 0x4a, 0xa9, 0x12, 0x95, 0x55, 0x49, 0x22, + 0x65, 0x2a, 0x5a, 0x92, 0xa9, 0x49, 0x54, 0x00, 0xe0, 0x24, 0xb2, 0x55, + 0x15, 0x4c, 0x00, 0x00, 0x02, 0x48, 0x52, 0x52, 0x00, 0x00, 0x00, 0x02, + 0x21, 0x09, 0x50, 0x81, 0x51, 0x69, 0x48, 0x52, 0x92, 0x94, 0xaa, 0x54, + 0x25, 0x54, 0x92, 0x4a, 0x89, 0x54, 0x82, 0xaa, 0x4a, 0x53, 0x55, 0x00, + 0x00, 0x49, 0x65, 0x52, 0x51, 0x12, 0x80, 0x00, 0x14, 0x92, 0x92, 0x42, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, 0x50, 0x24, 0x2a, 0x95, 0x25, 0x29, + 0x4a, 0xb5, 0x48, 0xa5, 0x52, 0x49, 0x24, 0x94, 0xaa, 0xab, 0x15, 0x24, + 0x92, 0xa5, 0x54, 0x40, 0x00, 0xaa, 0xb5, 0x25, 0x4a, 0xa4, 0x80, 0x00, + 0x21, 0x24, 0xa8, 0x94, 0x00, 0x00, 0x00, 0x0a, 0x44, 0x02, 0xb1, 0x01, + 0x24, 0x80, 0x48, 0xa2, 0x55, 0x55, 0x52, 0x8a, 0x94, 0xaa, 0x49, 0x22, + 0x8a, 0x49, 0x49, 0x55, 0x4a, 0x51, 0x25, 0x48, 0x02, 0xa8, 0x6a, 0x69, + 0x12, 0x29, 0x50, 0x00, 0x55, 0x24, 0x81, 0x24, 0x00, 0x00, 0x00, 0x23, + 0x80, 0x90, 0x70, 0x14, 0x82, 0x55, 0x22, 0x8a, 0xa9, 0x14, 0xaa, 0xa9, + 0x25, 0x51, 0x2a, 0x55, 0x21, 0x55, 0x55, 0x12, 0x55, 0x32, 0xaa, 0x94, + 0xa5, 0x55, 0x5a, 0x92, 0x54, 0xa5, 0x52, 0x24, 0xa2, 0x49, 0x2a, 0x92, + 0x00, 0x00, 0x00, 0x0e, 0x08, 0x00, 0xe2, 0xa0, 0x04, 0x54, 0x84, 0x52, + 0x4a, 0xa4, 0xaa, 0x2a, 0xa9, 0x25, 0x45, 0x42, 0xae, 0x92, 0x44, 0xa4, + 0x91, 0x24, 0xaa, 0xaa, 0xaa, 0x91, 0x55, 0x55, 0x51, 0x55, 0x54, 0xa9, + 0x14, 0x92, 0x49, 0x24, 0x00, 0x00, 0x00, 0x24, 0x01, 0x82, 0x70, 0x09, + 0x2a, 0x41, 0x2a, 0x89, 0x14, 0x49, 0x29, 0x52, 0x4a, 0xaa, 0x2a, 0x15, + 0x12, 0xaa, 0xa9, 0x2a, 0xaa, 0xba, 0xa4, 0x94, 0x95, 0x55, 0x5a, 0x49, + 0x25, 0x20, 0x49, 0x22, 0xa5, 0x24, 0x92, 0x92, 0x00, 0x00, 0x01, 0x0c, + 0x93, 0x10, 0xe2, 0x11, 0x00, 0x94, 0x22, 0x52, 0x69, 0x53, 0x52, 0x45, + 0x49, 0x22, 0xa4, 0x4a, 0x55, 0x29, 0x2a, 0xa4, 0x52, 0x42, 0xaa, 0xa5, + 0x52, 0xa8, 0xaa, 0x55, 0x4a, 0xab, 0xa9, 0x4a, 0x54, 0x49, 0x32, 0x24 }; diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 372e4e69c43a..96989ad46f66 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -21,6 +21,7 @@ config M68K select HAVE_AOUT if MMU select HAVE_ASM_MODVERSIONS select HAVE_DEBUG_BUGVERBOSE + select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED select HAVE_FUTEX_CMPXCHG if MMU && FUTEX select HAVE_IDE select HAVE_MOD_ARCH_SPECIFIC @@ -34,6 +35,7 @@ config M68K select SET_FS select UACCESS_MEMCPY if !MMU select VIRT_TO_BUS + select ZONE_DMA config CPU_BIG_ENDIAN def_bool y @@ -62,10 +64,6 @@ config TIME_LOW_RES config NO_IOPORT_MAP def_bool y -config ZONE_DMA - bool - default y - config HZ int default 1000 if CLEOPATRA diff --git a/arch/m68k/coldfire/clk.c b/arch/m68k/coldfire/clk.c index 076a9caa9557..2ed841e94111 100644 --- a/arch/m68k/coldfire/clk.c +++ b/arch/m68k/coldfire/clk.c @@ -73,20 +73,6 @@ struct clk_ops clk_ops1 = { #endif /* MCFPM_PPMCR1 */ #endif /* MCFPM_PPMCR0 */ -struct clk *clk_get(struct device *dev, const char *id) -{ - const char *clk_name = dev ? dev_name(dev) : id ? id : NULL; - struct clk *clk; - unsigned i; - - for (i = 0; (clk = mcf_clks[i]) != NULL; ++i) - if (!strcmp(clk->name, clk_name)) - return clk; - pr_warn("clk_get: didn't find clock %s\n", clk_name); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - int clk_enable(struct clk *clk) { unsigned long flags; @@ -117,13 +103,6 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); -void clk_put(struct clk *clk) -{ - if (clk->enabled != 0) - pr_warn("clk_put %s still enabled\n", clk->name); -} -EXPORT_SYMBOL(clk_put); - unsigned long clk_get_rate(struct clk *clk) { if (!clk) diff --git a/arch/m68k/coldfire/m5206.c b/arch/m68k/coldfire/m5206.c index 2f14ea95c391..5e726e94b5ab 100644 --- a/arch/m68k/coldfire/m5206.c +++ b/arch/m68k/coldfire/m5206.c @@ -10,6 +10,7 @@ /***************************************************************************/ +#include #include #include #include @@ -23,21 +24,15 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfi2c0, - NULL +static struct clk_lookup m5206_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -66,6 +61,8 @@ void __init config_BSP(char *commandp, int size) mcf_mapirq2imr(28, MCFINTC_EINT4); mcf_mapirq2imr(31, MCFINTC_EINT7); m5206_i2c_init(); + + clkdev_add_table(m5206_clk_lookup, ARRAY_SIZE(m5206_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m520x.c b/arch/m68k/coldfire/m520x.c index b5b2a267dada..d2f96b40aee1 100644 --- a/arch/m68k/coldfire/m520x.c +++ b/arch/m68k/coldfire/m520x.c @@ -12,6 +12,7 @@ /***************************************************************************/ +#include #include #include #include @@ -48,31 +49,29 @@ DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK); DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK); DEFINE_CLK(0, "sdram.0", 42, MCF_CLK); -struct clk *mcf_clks[] = { - &__clk_0_2, /* flexbus */ - &__clk_0_12, /* fec.0 */ - &__clk_0_17, /* edma */ - &__clk_0_18, /* intc.0 */ - &__clk_0_21, /* iack.0 */ - &__clk_0_22, /* imx1-i2c.0 */ - &__clk_0_23, /* mcfqspi.0 */ - &__clk_0_24, /* mcfuart.0 */ - &__clk_0_25, /* mcfuart.1 */ - &__clk_0_26, /* mcfuart.2 */ - &__clk_0_28, /* mcftmr.0 */ - &__clk_0_29, /* mcftmr.1 */ - &__clk_0_30, /* mcftmr.2 */ - &__clk_0_31, /* mcftmr.3 */ - - &__clk_0_32, /* mcfpit.0 */ - &__clk_0_33, /* mcfpit.1 */ - &__clk_0_34, /* mcfeport.0 */ - &__clk_0_35, /* mcfwdt.0 */ - &__clk_0_36, /* pll.0 */ - &__clk_0_40, /* sys.0 */ - &__clk_0_41, /* gpio.0 */ - &__clk_0_42, /* sdram.0 */ - NULL, +static struct clk_lookup m520x_clk_lookup[] = { + CLKDEV_INIT(NULL, "flexbus", &__clk_0_2), + CLKDEV_INIT("fec.0", NULL, &__clk_0_12), + CLKDEV_INIT("edma", NULL, &__clk_0_17), + CLKDEV_INIT("intc.0", NULL, &__clk_0_18), + CLKDEV_INIT("iack.0", NULL, &__clk_0_21), + CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22), + CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23), + CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24), + CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25), + CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26), + CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28), + CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29), + CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30), + CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31), + CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32), + CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33), + CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34), + CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35), + CLKDEV_INIT(NULL, "pll.0", &__clk_0_36), + CLKDEV_INIT(NULL, "sys.0", &__clk_0_40), + CLKDEV_INIT("gpio.0", NULL, &__clk_0_41), + CLKDEV_INIT("sdram.0", NULL, &__clk_0_42), }; static struct clk * const enable_clks[] __initconst = { @@ -115,6 +114,8 @@ static void __init m520x_clk_init(void) /* make sure these clocks are disabled */ for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) __clk_init_disabled(disable_clks[i]); + + clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m523x.c b/arch/m68k/coldfire/m523x.c index ddf2496ed117..193c178162c1 100644 --- a/arch/m68k/coldfire/m523x.c +++ b/arch/m68k/coldfire/m523x.c @@ -13,6 +13,7 @@ /***************************************************************************/ +#include #include #include #include @@ -26,31 +27,20 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); -DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); -DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); -DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcfpit0, - &clk_mcfpit1, - &clk_mcfpit2, - &clk_mcfpit3, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfuart2, - &clk_mcfqspi0, - &clk_fec0, - &clk_mcfi2c0, - NULL +struct clk_lookup m523x_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcfpit.0", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.1", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.2", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.3", NULL, &clk_pll), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.2", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("fec.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -100,6 +90,8 @@ void __init config_BSP(char *commandp, int size) m523x_fec_init(); m523x_qspi_init(); m523x_i2c_init(); + + clkdev_add_table(m523x_clk_lookup, ARRAY_SIZE(m523x_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m5249.c b/arch/m68k/coldfire/m5249.c index 0590f8c421f1..6d66972de214 100644 --- a/arch/m68k/coldfire/m5249.c +++ b/arch/m68k/coldfire/m5249.c @@ -9,6 +9,7 @@ /***************************************************************************/ +#include #include #include #include @@ -23,25 +24,17 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfqspi0, - &clk_mcfi2c0, - &clk_mcfi2c1, - NULL +struct clk_lookup m5249_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys), }; /***************************************************************************/ @@ -137,6 +130,8 @@ void __init config_BSP(char *commandp, int size) #endif m5249_qspi_init(); m5249_i2c_init(); + + clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m525x.c b/arch/m68k/coldfire/m525x.c index 1772359c416c..2c4d2ca2f20d 100644 --- a/arch/m68k/coldfire/m525x.c +++ b/arch/m68k/coldfire/m525x.c @@ -9,6 +9,7 @@ /***************************************************************************/ +#include #include #include #include @@ -23,25 +24,17 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfqspi0, - &clk_mcfi2c0, - &clk_mcfi2c1, - NULL +static struct clk_lookup m525x_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys), }; /***************************************************************************/ @@ -88,6 +81,8 @@ void __init config_BSP(char *commandp, int size) m525x_qspi_init(); m525x_i2c_init(); + + clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m5272.c b/arch/m68k/coldfire/m5272.c index 6b3ab583c698..734dab657fe3 100644 --- a/arch/m68k/coldfire/m5272.c +++ b/arch/m68k/coldfire/m5272.c @@ -10,6 +10,7 @@ /***************************************************************************/ +#include #include #include #include @@ -34,27 +35,18 @@ unsigned char ledbank = 0xff; DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK); -DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcftmr2, - &clk_mcftmr3, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfqspi0, - &clk_fec0, - NULL +static struct clk_lookup m5272_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.2", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.3", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("fec.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -128,6 +120,7 @@ static int __init init_BSP(void) { m5272_uarts_init(); fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status); + clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup)); return 0; } diff --git a/arch/m68k/coldfire/m527x.c b/arch/m68k/coldfire/m527x.c index cad462df6861..037f3e520acc 100644 --- a/arch/m68k/coldfire/m527x.c +++ b/arch/m68k/coldfire/m527x.c @@ -13,6 +13,7 @@ /***************************************************************************/ +#include #include #include #include @@ -27,33 +28,21 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); -DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); -DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); -DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); -DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcfpit0, - &clk_mcfpit1, - &clk_mcfpit2, - &clk_mcfpit3, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfuart2, - &clk_mcfqspi0, - &clk_fec0, - &clk_fec1, - &clk_mcfi2c0, - NULL +static struct clk_lookup m527x_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcfpit.0", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.1", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.2", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.3", NULL, &clk_pll), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.2", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("fec.0", NULL, &clk_sys), + CLKDEV_INIT("fec.1", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -151,6 +140,7 @@ void __init config_BSP(char *commandp, int size) m527x_fec_init(); m527x_qspi_init(); m527x_i2c_init(); + clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m528x.c b/arch/m68k/coldfire/m528x.c index 7ad3193887e8..51a6a6236e12 100644 --- a/arch/m68k/coldfire/m528x.c +++ b/arch/m68k/coldfire/m528x.c @@ -13,6 +13,7 @@ /***************************************************************************/ +#include #include #include #include @@ -28,31 +29,20 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); -DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); -DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); -DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); -DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); -DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcfpit0, - &clk_mcfpit1, - &clk_mcfpit2, - &clk_mcfpit3, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfuart2, - &clk_mcfqspi0, - &clk_fec0, - &clk_mcfi2c0, - NULL +static struct clk_lookup m528x_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcfpit.0", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.1", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.2", NULL, &clk_pll), + CLKDEV_INIT("mcfpit.3", NULL, &clk_pll), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.2", NULL, &clk_sys), + CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), + CLKDEV_INIT("fec.0", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -146,6 +136,8 @@ void __init config_BSP(char *commandp, int size) m528x_fec_init(); m528x_qspi_init(); m528x_i2c_init(); + + clkdev_add_table(m528x_clk_lookup, ARRAY_SIZE(m528x_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m5307.c b/arch/m68k/coldfire/m5307.c index 64b4b1fd34ff..4ed2e43ab3ad 100644 --- a/arch/m68k/coldfire/m5307.c +++ b/arch/m68k/coldfire/m5307.c @@ -10,6 +10,7 @@ /***************************************************************************/ +#include #include #include #include @@ -32,21 +33,15 @@ unsigned char ledbank = 0xff; DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfi2c0, - NULL +static struct clk_lookup m5307_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -88,6 +83,8 @@ void __init config_BSP(char *commandp, int size) wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); #endif m5307_i2c_init(); + + clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m53xx.c b/arch/m68k/coldfire/m53xx.c index 075722c0c4f0..bd033e1975bf 100644 --- a/arch/m68k/coldfire/m53xx.c +++ b/arch/m68k/coldfire/m53xx.c @@ -13,6 +13,7 @@ /***************************************************************************/ +#include #include #include #include @@ -65,45 +66,42 @@ DEFINE_CLK(1, "mdha.0", 32, MCF_CLK); DEFINE_CLK(1, "skha.0", 33, MCF_CLK); DEFINE_CLK(1, "rng.0", 34, MCF_CLK); -struct clk *mcf_clks[] = { - &__clk_0_2, /* flexbus */ - &__clk_0_8, /* mcfcan.0 */ - &__clk_0_12, /* fec.0 */ - &__clk_0_17, /* edma */ - &__clk_0_18, /* intc.0 */ - &__clk_0_19, /* intc.1 */ - &__clk_0_21, /* iack.0 */ - &__clk_0_22, /* imx1-i2c.0 */ - &__clk_0_23, /* mcfqspi.0 */ - &__clk_0_24, /* mcfuart.0 */ - &__clk_0_25, /* mcfuart.1 */ - &__clk_0_26, /* mcfuart.2 */ - &__clk_0_28, /* mcftmr.0 */ - &__clk_0_29, /* mcftmr.1 */ - &__clk_0_30, /* mcftmr.2 */ - &__clk_0_31, /* mcftmr.3 */ - - &__clk_0_32, /* mcfpit.0 */ - &__clk_0_33, /* mcfpit.1 */ - &__clk_0_34, /* mcfpit.2 */ - &__clk_0_35, /* mcfpit.3 */ - &__clk_0_36, /* mcfpwm.0 */ - &__clk_0_37, /* mcfeport.0 */ - &__clk_0_38, /* mcfwdt.0 */ - &__clk_0_40, /* sys.0 */ - &__clk_0_41, /* gpio.0 */ - &__clk_0_42, /* mcfrtc.0 */ - &__clk_0_43, /* mcflcd.0 */ - &__clk_0_44, /* mcfusb-otg.0 */ - &__clk_0_45, /* mcfusb-host.0 */ - &__clk_0_46, /* sdram.0 */ - &__clk_0_47, /* ssi.0 */ - &__clk_0_48, /* pll.0 */ - - &__clk_1_32, /* mdha.0 */ - &__clk_1_33, /* skha.0 */ - &__clk_1_34, /* rng.0 */ - NULL, +static struct clk_lookup m53xx_clk_lookup[] = { + CLKDEV_INIT("flexbus", NULL, &__clk_0_2), + CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8), + CLKDEV_INIT("fec.0", NULL, &__clk_0_12), + CLKDEV_INIT("edma", NULL, &__clk_0_17), + CLKDEV_INIT("intc.0", NULL, &__clk_0_18), + CLKDEV_INIT("intc.1", NULL, &__clk_0_19), + CLKDEV_INIT("iack.0", NULL, &__clk_0_21), + CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22), + CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23), + CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24), + CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25), + CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26), + CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28), + CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29), + CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30), + CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31), + CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32), + CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33), + CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34), + CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35), + CLKDEV_INIT("mcfpwm.0", NULL, &__clk_0_36), + CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37), + CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_38), + CLKDEV_INIT(NULL, "sys.0", &__clk_0_40), + CLKDEV_INIT("gpio.0", NULL, &__clk_0_41), + CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42), + CLKDEV_INIT("mcflcd.0", NULL, &__clk_0_43), + CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44), + CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45), + CLKDEV_INIT("sdram.0", NULL, &__clk_0_46), + CLKDEV_INIT("ssi.0", NULL, &__clk_0_47), + CLKDEV_INIT(NULL, "pll.0", &__clk_0_48), + CLKDEV_INIT("mdha.0", NULL, &__clk_1_32), + CLKDEV_INIT("skha.0", NULL, &__clk_1_33), + CLKDEV_INIT("rng.0", NULL, &__clk_1_34), }; static struct clk * const enable_clks[] __initconst = { @@ -158,6 +156,8 @@ static void __init m53xx_clk_init(void) /* make sure these clocks are disabled */ for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) __clk_init_disabled(disable_clks[i]); + + clkdev_add_table(m53xx_clk_lookup, ARRAY_SIZE(m53xx_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m5407.c b/arch/m68k/coldfire/m5407.c index 0400d76115a1..b32efb3042a2 100644 --- a/arch/m68k/coldfire/m5407.c +++ b/arch/m68k/coldfire/m5407.c @@ -10,6 +10,7 @@ /***************************************************************************/ +#include #include #include #include @@ -23,21 +24,15 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); -DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcftmr0, - &clk_mcftmr1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfi2c0, - NULL +static struct clk_lookup m5407_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), + CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -63,6 +58,8 @@ void __init config_BSP(char *commandp, int size) mcf_mapirq2imr(29, MCFINTC_EINT5); mcf_mapirq2imr(31, MCFINTC_EINT7); m5407_i2c_init(); + + clkdev_add_table(m5407_clk_lookup, ARRAY_SIZE(m5407_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c index 1e5259a652d1..ce14693d18b6 100644 --- a/arch/m68k/coldfire/m5441x.c +++ b/arch/m68k/coldfire/m5441x.c @@ -5,6 +5,7 @@ * (C) Copyright Steven King */ +#include #include #include #include @@ -78,72 +79,67 @@ DEFINE_CLK(2, "ipg.0", 0, MCF_CLK); DEFINE_CLK(2, "ahb.0", 1, MCF_CLK); DEFINE_CLK(2, "per.0", 2, MCF_CLK); -struct clk *mcf_clks[] = { - &__clk_0_2, - &__clk_0_8, - &__clk_0_9, - &__clk_0_14, - &__clk_0_15, - &__clk_0_17, - &__clk_0_18, - &__clk_0_19, - &__clk_0_20, - &__clk_0_22, - &__clk_0_23, - &__clk_0_24, - &__clk_0_25, - &__clk_0_26, - &__clk_0_27, - &__clk_0_28, - &__clk_0_29, - &__clk_0_30, - &__clk_0_31, - &__clk_0_32, - &__clk_0_33, - &__clk_0_34, - &__clk_0_35, - &__clk_0_37, - &__clk_0_38, - &__clk_0_39, - &__clk_0_42, - &__clk_0_43, - &__clk_0_44, - &__clk_0_45, - &__clk_0_46, - &__clk_0_47, - &__clk_0_48, - &__clk_0_49, - &__clk_0_50, - &__clk_0_51, - &__clk_0_53, - &__clk_0_54, - &__clk_0_55, - &__clk_0_56, - &__clk_0_63, - - &__clk_1_2, - &__clk_1_4, - &__clk_1_5, - &__clk_1_6, - &__clk_1_7, - &__clk_1_24, - &__clk_1_25, - &__clk_1_26, - &__clk_1_27, - &__clk_1_28, - &__clk_1_29, - &__clk_1_34, - &__clk_1_36, - &__clk_1_37, - - &__clk_2_0, - &__clk_2_1, - &__clk_2_2, - - NULL, +static struct clk_lookup m5411x_clk_lookup[] = { + CLKDEV_INIT("flexbus", NULL, &__clk_0_2), + CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8), + CLKDEV_INIT("mcfcan.1", NULL, &__clk_0_9), + CLKDEV_INIT("imx1-i2c.1", NULL, &__clk_0_14), + CLKDEV_INIT("mcfdspi.1", NULL, &__clk_0_15), + CLKDEV_INIT("edma", NULL, &__clk_0_17), + CLKDEV_INIT("intc.0", NULL, &__clk_0_18), + CLKDEV_INIT("intc.1", NULL, &__clk_0_19), + CLKDEV_INIT("intc.2", NULL, &__clk_0_20), + CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22), + CLKDEV_INIT("fsl-dspi.0", NULL, &__clk_0_23), + CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24), + CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25), + CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26), + CLKDEV_INIT("mcfuart.3", NULL, &__clk_0_27), + CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28), + CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29), + CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30), + CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31), + CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32), + CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33), + CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34), + CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35), + CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37), + CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_38), + CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_39), + CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42), + CLKDEV_INIT("mcfsim.0", NULL, &__clk_0_43), + CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44), + CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45), + CLKDEV_INIT("mcfddr-sram.0", NULL, &__clk_0_46), + CLKDEV_INIT("mcfssi.0", NULL, &__clk_0_47), + CLKDEV_INIT(NULL, "pll.0", &__clk_0_48), + CLKDEV_INIT("mcfrng.0", NULL, &__clk_0_49), + CLKDEV_INIT("mcfssi.1", NULL, &__clk_0_50), + CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51), + CLKDEV_INIT("enet-fec.0", NULL, &__clk_0_53), + CLKDEV_INIT("enet-fec.1", NULL, &__clk_0_54), + CLKDEV_INIT("switch.0", NULL, &__clk_0_55), + CLKDEV_INIT("switch.1", NULL, &__clk_0_56), + CLKDEV_INIT("nand.0", NULL, &__clk_0_63), + CLKDEV_INIT("mcfow.0", NULL, &__clk_1_2), + CLKDEV_INIT("imx1-i2c.2", NULL, &__clk_1_4), + CLKDEV_INIT("imx1-i2c.3", NULL, &__clk_1_5), + CLKDEV_INIT("imx1-i2c.4", NULL, &__clk_1_6), + CLKDEV_INIT("imx1-i2c.5", NULL, &__clk_1_7), + CLKDEV_INIT("mcfuart.4", NULL, &__clk_1_24), + CLKDEV_INIT("mcfuart.5", NULL, &__clk_1_25), + CLKDEV_INIT("mcfuart.6", NULL, &__clk_1_26), + CLKDEV_INIT("mcfuart.7", NULL, &__clk_1_27), + CLKDEV_INIT("mcfuart.8", NULL, &__clk_1_28), + CLKDEV_INIT("mcfuart.9", NULL, &__clk_1_29), + CLKDEV_INIT("mcfpwm.0", NULL, &__clk_1_34), + CLKDEV_INIT(NULL, "sys.0", &__clk_1_36), + CLKDEV_INIT("gpio.0", NULL, &__clk_1_37), + CLKDEV_INIT("ipg.0", NULL, &__clk_2_0), + CLKDEV_INIT("ahb.0", NULL, &__clk_2_1), + CLKDEV_INIT("per.0", NULL, &__clk_2_2), }; - static struct clk * const enable_clks[] __initconst = { /* make sure these clocks are enabled */ &__clk_0_15, /* dspi.1 */ @@ -228,6 +224,8 @@ static void __init m5441x_clk_init(void) /* make sure these clocks are disabled */ for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) __clk_init_disabled(disable_clks[i]); + + clkdev_add_table(m5411x_clk_lookup, ARRAY_SIZE(m5411x_clk_lookup)); } static void __init m5441x_uarts_init(void) diff --git a/arch/m68k/coldfire/m54xx.c b/arch/m68k/coldfire/m54xx.c index 360c723c0ae6..8e3c8fee8327 100644 --- a/arch/m68k/coldfire/m54xx.c +++ b/arch/m68k/coldfire/m54xx.c @@ -9,6 +9,7 @@ /***************************************************************************/ +#include #include #include #include @@ -32,25 +33,17 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); -DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK); -DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); -DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); -DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); -DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); -DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); -struct clk *mcf_clks[] = { - &clk_pll, - &clk_sys, - &clk_mcfslt0, - &clk_mcfslt1, - &clk_mcfuart0, - &clk_mcfuart1, - &clk_mcfuart2, - &clk_mcfuart3, - &clk_mcfi2c0, - NULL +static struct clk_lookup m54xx_clk_lookup[] = { + CLKDEV_INIT(NULL, "pll.0", &clk_pll), + CLKDEV_INIT(NULL, "sys.0", &clk_sys), + CLKDEV_INIT("mcfslt.0", NULL, &clk_sys), + CLKDEV_INIT("mcfslt.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.2", NULL, &clk_sys), + CLKDEV_INIT("mcfuart.3", NULL, &clk_sys), + CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), }; /***************************************************************************/ @@ -100,6 +93,8 @@ void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m54xx_uarts_init(); m54xx_i2c_init(); + + clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup)); } /***************************************************************************/ diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c index 57e8c8fb5eba..92636c89d65b 100644 --- a/arch/m68k/emu/nfcon.c +++ b/arch/m68k/emu/nfcon.c @@ -85,7 +85,7 @@ static int nfcon_tty_put_char(struct tty_struct *tty, unsigned char ch) return 1; } -static int nfcon_tty_write_room(struct tty_struct *tty) +static unsigned int nfcon_tty_write_room(struct tty_struct *tty) { return 64; } diff --git a/arch/m68k/include/asm/mcf_pgalloc.h b/arch/m68k/include/asm/mcf_pgalloc.h index bc1228e00518..5c2c0a864524 100644 --- a/arch/m68k/include/asm/mcf_pgalloc.h +++ b/arch/m68k/include/asm/mcf_pgalloc.h @@ -32,8 +32,6 @@ extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address) #define pmd_populate_kernel pmd_populate -#define pmd_pgtable(pmd) pfn_to_virt(pmd_val(pmd) >> PAGE_SHIFT) - static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pgtable, unsigned long address) { diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h index 8d4ec05996c5..6f2b87d7a50d 100644 --- a/arch/m68k/include/asm/mcf_pgtable.h +++ b/arch/m68k/include/asm/mcf_pgtable.h @@ -150,6 +150,8 @@ #ifndef __ASSEMBLY__ +#define pmd_pgtable(pmd) pfn_to_virt(pmd_val(pmd) >> PAGE_SHIFT) + /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h index 722627e06d66..4e9a6b827a14 100644 --- a/arch/m68k/include/asm/mcfclk.h +++ b/arch/m68k/include/asm/mcfclk.h @@ -15,15 +15,12 @@ struct clk_ops { }; struct clk { - const char *name; struct clk_ops *clk_ops; unsigned long rate; unsigned long enabled; u8 slot; }; -extern struct clk *mcf_clks[]; - #ifdef MCFPM_PPMCR0 extern struct clk_ops clk_ops0; #ifdef MCFPM_PPMCR1 @@ -34,7 +31,6 @@ extern struct clk_ops clk_ops2; #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ static struct clk __clk_##clk_bank##_##clk_slot = { \ - .name = clk_name, \ .clk_ops = &clk_ops##clk_bank, \ .rate = clk_rate, \ .slot = clk_slot, \ @@ -45,7 +41,6 @@ void __clk_init_disabled(struct clk *); #else #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ static struct clk clk_##clk_ref = { \ - .name = clk_name, \ .rate = clk_rate, \ } #endif /* MCFPM_PPMCR0 */ diff --git a/arch/m68k/include/asm/motorola_pgalloc.h b/arch/m68k/include/asm/motorola_pgalloc.h index b4fc3b4f6bb3..74a817d9387f 100644 --- a/arch/m68k/include/asm/motorola_pgalloc.h +++ b/arch/m68k/include/asm/motorola_pgalloc.h @@ -88,7 +88,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page { pmd_set(pmd, page); } -#define pmd_pgtable(pmd) ((pgtable_t)pmd_page_vaddr(pmd)) static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) { diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h index 8076467eff4b..a2908164ee6f 100644 --- a/arch/m68k/include/asm/motorola_pgtable.h +++ b/arch/m68k/include/asm/motorola_pgtable.h @@ -105,6 +105,8 @@ extern unsigned long mm_cachebits; #define __S110 PAGE_SHARED_C #define __S111 PAGE_SHARED_C +#define pmd_pgtable(pmd) ((pgtable_t)pmd_page_vaddr(pmd)) + /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h index aca22c2c1ee2..143ba7de9bda 100644 --- a/arch/m68k/include/asm/pgtable_mm.h +++ b/arch/m68k/include/asm/pgtable_mm.h @@ -72,7 +72,6 @@ #define PTRS_PER_PGD 128 #endif #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL /* Virtual address region for use by kernel_map() */ #ifdef CONFIG_SUN3 diff --git a/arch/m68k/include/asm/sun3_pgalloc.h b/arch/m68k/include/asm/sun3_pgalloc.h index 000f64869b91..198036aff519 100644 --- a/arch/m68k/include/asm/sun3_pgalloc.h +++ b/arch/m68k/include/asm/sun3_pgalloc.h @@ -32,7 +32,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page { pmd_val(*pmd) = __pa((unsigned long)page_address(page)); } -#define pmd_pgtable(pmd) pmd_page(pmd) /* * allocating and freeing a pmd is trivial: the 1-entry pmd is diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h deleted file mode 100644 index 98c8930d3d35..000000000000 --- a/arch/m68k/include/asm/unaligned.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_M68K_UNALIGNED_H -#define _ASM_M68K_UNALIGNED_H - - -#ifdef CONFIG_CPU_HAS_NO_UNALIGNED -#include -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#else -/* - * The m68k can do unaligned accesses itself. - */ -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif - -#endif /* _ASM_M68K_UNALIGNED_H */ diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 0660f47012bc..14a67a42fcae 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -43,6 +43,7 @@ config MICROBLAZE select MMU_GATHER_NO_RANGE select SPARSE_IRQ select SET_FS + select ZONE_DMA # Endianness selection choice @@ -60,9 +61,6 @@ config CPU_LITTLE_ENDIAN endchoice -config ZONE_DMA - def_bool y - config ARCH_HAS_ILOG2_U32 def_bool n diff --git a/arch/microblaze/include/asm/pgalloc.h b/arch/microblaze/include/asm/pgalloc.h index d56b9f670ad1..6c33b05f730f 100644 --- a/arch/microblaze/include/asm/pgalloc.h +++ b/arch/microblaze/include/asm/pgalloc.h @@ -28,8 +28,6 @@ static inline pgd_t *get_pgd(void) #define pgd_alloc(mm) get_pgd() -#define pmd_pgtable(pmd) pmd_page(pmd) - extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm); #define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, (pte)) diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index 9ae8d2c17dd5..71cd547655d9 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -25,8 +25,6 @@ extern int mem_init_done; #include #include -#define FIRST_USER_ADDRESS 0UL - extern unsigned long va_to_phys(unsigned long address); extern pte_t *va_to_pte(unsigned long address); diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h deleted file mode 100644 index 448299beab69..000000000000 --- a/arch/microblaze/include/asm/unaligned.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2008 Michal Simek - * Copyright (C) 2006 Atmark Techno, Inc. - */ - -#ifndef _ASM_MICROBLAZE_UNALIGNED_H -#define _ASM_MICROBLAZE_UNALIGNED_H - -# ifdef __KERNEL__ - -# ifdef __MICROBLAZEEL__ -# include -# include -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -# else -# include -# include -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -# endif - -# include - -# endif /* __KERNEL__ */ -#endif /* _ASM_MICROBLAZE_UNALIGNED_H */ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4704a16c2e44..cee6087cd686 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -112,6 +112,7 @@ config MACH_INGENIC select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT select DMA_NONCOHERENT + select ARCH_HAS_SYNC_DMA_FOR_CPU select IRQ_MIPS_CPU select PINCTRL select GPIOLIB @@ -201,6 +202,7 @@ config MIPS_ALCHEMY config AR7 bool "Texas Instruments AR7" select BOOT_ELF32 + select COMMON_CLK select DMA_NONCOHERENT select CEVT_R4K select CSRC_R4K @@ -215,7 +217,6 @@ config AR7 select SYS_SUPPORTS_ZBOOT_UART16550 select GPIOLIB select VLYNQ - select HAVE_LEGACY_CLK help Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. @@ -332,7 +333,6 @@ config BCM63XX select SWAP_IO_SPACE select GPIOLIB select MIPS_L1_CACHE_SHIFT_4 - select CLKDEV_LOOKUP select HAVE_LEGACY_CLK help Support for BCM63XX based boards @@ -428,6 +428,8 @@ config MACH_INGENIC_SOC select MIPS_GENERIC select MACH_INGENIC select SYS_SUPPORTS_ZBOOT_UART16550 + select CPU_SUPPORTS_CPUFREQ + select MIPS_EXTERNAL_TIMER config LANTIQ bool "Lantiq based platforms" @@ -446,7 +448,6 @@ config LANTIQ select GPIOLIB select SWAP_IO_SPACE select BOOT_RAW - select CLKDEV_LOOKUP select HAVE_LEGACY_CLK select USE_OF select PINCTRL @@ -630,6 +631,7 @@ config MACH_NINTENDO64 config RALINK bool "Ralink based machines" select CEVT_R4K + select COMMON_CLK select CSRC_R4K select BOOT_RAW select DMA_NONCOHERENT @@ -642,7 +644,6 @@ config RALINK select SYS_SUPPORTS_MIPS16 select SYS_SUPPORTS_ZBOOT select SYS_HAS_EARLY_PRINTK - select CLKDEV_LOOKUP select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER @@ -996,7 +997,6 @@ config CAVIUM_OCTEON_SOC select HAVE_PLAT_FW_INIT_CMDLINE select HAVE_PLAT_MEMCPY select ZONE_DMA32 - select HOLES_IN_ZONE select GPIOLIB select USE_OF select ARCH_SPARSEMEM_ENABLE @@ -1233,9 +1233,6 @@ config HAVE_PLAT_MEMCPY config ISA_DMA_API bool -config HOLES_IN_ZONE - bool - config SYS_SUPPORTS_RELOCATABLE bool help @@ -3277,13 +3274,6 @@ config I8253 select CLKSRC_I8253 select CLKEVT_I8253 select MIPS_EXTERNAL_TIMER - -config ZONE_DMA - bool - -config ZONE_DMA32 - bool - endmenu config TRAD_SIGNALS diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index f5832a49a881..43dbf5930796 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -102,6 +102,14 @@ config DEBUG_ZBOOT to reduce the kernel image size and speed up the booting procedure a little. +config ZBOOT_INGENIC_UART + int "UART to use for compressed kernel debugging" + depends on DEBUG_ZBOOT && MACH_INGENIC_SOC + default 0 + range 0 4 + help + Specify the UART that should be used for compressed kernel debugging. + config SPINLOCK_TEST bool "Enable spinlock timing tests in debugfs" depends on DEBUG_FS diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c index 95def949c971..c717acbc5506 100644 --- a/arch/mips/ar7/clock.c +++ b/arch/mips/ar7/clock.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include #include @@ -84,17 +86,17 @@ struct tnetd7200_clocks { struct tnetd7200_clock usb; }; -static struct clk bus_clk = { +struct clk_rate { + u32 rate; +}; +static struct clk_rate bus_clk = { .rate = 125000000, }; -static struct clk cpu_clk = { +static struct clk_rate cpu_clk = { .rate = 150000000, }; -static struct clk dsp_clk; -static struct clk vbus_clk; - static void approximate(int base, int target, int *prediv, int *postdiv, int *mul) { @@ -240,6 +242,8 @@ static void __init tnetd7300_init_clocks(void) struct tnetd7300_clocks *clocks = ioremap(UR8_REGS_CLOCKS, sizeof(struct tnetd7300_clocks)); + u32 dsp_clk; + struct clk *clk; bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, &clocks->bus, bootcr, AR7_AFE_CLOCK); @@ -250,12 +254,18 @@ static void __init tnetd7300_init_clocks(void) else cpu_clk.rate = bus_clk.rate; - if (dsp_clk.rate == 250000000) + dsp_clk = tnetd7300_dsp_clock(); + if (dsp_clk == 250000000) tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, - bootcr, dsp_clk.rate); + bootcr, dsp_clk); iounmap(clocks); iounmap(bootcr); + + clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate); + clkdev_create(clk, "cpu", NULL); + clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk); + clkdev_create(clk, "dsp", NULL); } static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, @@ -327,6 +337,7 @@ static void __init tnetd7200_init_clocks(void) int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv; int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv; int usb_base, usb_mul, usb_prediv, usb_postdiv; + struct clk *clk; cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); @@ -395,100 +406,34 @@ static void __init tnetd7200_init_clocks(void) usb_prediv, usb_postdiv, -1, usb_mul, TNETD7200_DEF_USB_CLK); - dsp_clk.rate = cpu_clk.rate; - iounmap(clocks); iounmap(bootcr); -} -/* - * Linux clock API - */ -int clk_enable(struct clk *clk) -{ - return 0; + clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate); + clkdev_create(clk, "cpu", NULL); + clkdev_create(clk, "dsp", NULL); } -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "bus")) - return &bus_clk; - /* cpmac and vbus share the same rate */ - if (!strcmp(id, "cpmac")) - return &vbus_clk; - if (!strcmp(id, "cpu")) - return &cpu_clk; - if (!strcmp(id, "dsp")) - return &dsp_clk; - if (!strcmp(id, "vbus")) - return &vbus_clk; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); void __init ar7_init_clocks(void) { + struct clk *clk; + switch (ar7_chip_id()) { case AR7_CHIP_7100: case AR7_CHIP_7200: tnetd7200_init_clocks(); break; case AR7_CHIP_7300: - dsp_clk.rate = tnetd7300_dsp_clock(); tnetd7300_init_clocks(); break; default: break; } + clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate); + clkdev_create(clk, "bus", NULL); /* adjust vbus clock rate */ - vbus_clk.rate = bus_clk.rate / 2; + clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2); + clkdev_create(clk, "vbus", NULL); + clkdev_create(clk, "cpmac", "cpmac.1"); + clkdev_create(clk, "cpmac", "cpmac.1"); } - -/* dummy functions, should not be called */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - WARN_ON(clk); - return 0; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - WARN_ON(clk); - return NULL; -} -EXPORT_SYMBOL(clk_get_parent); diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index aee8d7b8f091..c18d7f72d9d9 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -19,8 +19,8 @@ #endif #ifdef CONFIG_MACH_INGENIC -#define INGENIC_UART0_BASE_ADDR 0x10030000 -#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) +#define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART) +#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset)) #endif #ifdef CONFIG_CPU_XLR diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 8877c62609de..a688809beebc 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -118,6 +118,20 @@ assigned-clock-rates = <48000000>; }; +&tcu { + /* + * 750 kHz for the system timers and clocksource, + * use channel #0 and #1 for the per cpu system timers, + * and use channel #2 for the clocksource. + * + * 3000 kHz for the OST timer to provide a higher + * precision clocksource. + */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; + assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; +}; + &mmc0 { status = "okay"; @@ -522,13 +536,3 @@ bias-disable; }; }; - -&tcu { - /* - * 750 kHz for the system timer and 3 MHz for the clocksource, - * use channel #0 for the system timer, #1 for the clocksource. - */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, - <&tcu TCU_CLK_OST>; - assigned-clock-rates = <750000>, <3000000>, <3000000>; -}; diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts index f4c04f2263ea..4abb0318416c 100644 --- a/arch/mips/boot/dts/ingenic/gcw0.dts +++ b/arch/mips/boot/dts/ingenic/gcw0.dts @@ -74,7 +74,6 @@ simple-audio-card,widgets = "Speaker", "Speaker", "Headphone", "Headphones", - "Line", "FM Radio", "Microphone", "Built-in Mic"; simple-audio-card,routing = "Headphones Amp INL", "LHPOUT", @@ -85,8 +84,8 @@ "Speaker Amp INR", "ROUT", "Speaker", "Speaker Amp OUTL", "Speaker", "Speaker Amp OUTR", - "LLINEIN", "FM Radio", - "RLINEIN", "FM Radio", + "LLINEIN", "Cap-less", + "RLINEIN", "Cap-less", "Built-in Mic", "MICBIAS", "MIC1P", "Built-in Mic", "MIC1N", "Built-in Mic"; diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index 8d01feef7ff5..9e34f433b9b5 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -339,7 +339,7 @@ }; i2c0: i2c@10050000 { - compatible = "ingenic,jz4780-i2c"; + compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -357,7 +357,7 @@ }; i2c1: i2c@10051000 { - compatible = "ingenic,jz4780-i2c"; + compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x10051000 0x1000>; @@ -374,7 +374,7 @@ }; i2c2: i2c@10052000 { - compatible = "ingenic,jz4780-i2c"; + compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x10052000 0x1000>; @@ -391,7 +391,7 @@ }; i2c3: i2c@10053000 { - compatible = "ingenic,jz4780-i2c"; + compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x10053000 0x1000>; @@ -408,7 +408,7 @@ }; i2c4: i2c@10054000 { - compatible = "ingenic,jz4780-i2c"; + compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x10054000 0x1000>; diff --git a/arch/mips/boot/dts/ingenic/rs90.dts b/arch/mips/boot/dts/ingenic/rs90.dts index 4eb1edbfc155..74fee7f01352 100644 --- a/arch/mips/boot/dts/ingenic/rs90.dts +++ b/arch/mips/boot/dts/ingenic/rs90.dts @@ -16,6 +16,18 @@ reg = <0x0 0x2000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vmem: video-memory@1f00000 { + compatible = "shared-dma-pool"; + reg = <0x1f00000 0x100000>; + reusable; + }; + }; + vcc: regulator { compatible = "regulator-fixed"; @@ -300,6 +312,8 @@ }; &lcd { + memory-region = <&vmem>; + pinctrl-names = "default"; pinctrl-0 = <&pins_lcd>; }; diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index aac9dedaf334..dec7909d4baa 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -80,6 +80,11 @@ status = "disabled"; }; + + mac_phy_ctrl: mac-phy-ctrl@e8 { + compatible = "syscon"; + reg = <0xe8 0x4>; + }; }; ost: timer@12000000 { @@ -347,6 +352,8 @@ clocks = <&cgu X1000_CLK_MAC>; clock-names = "stmmaceth"; + mode-reg = <&mac_phy_ctrl>; + status = "disabled"; mdio: mdio { diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi index b21c93057356..215257f8bb1a 100644 --- a/arch/mips/boot/dts/ingenic/x1830.dtsi +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi @@ -73,6 +73,11 @@ status = "disabled"; }; + + mac_phy_ctrl: mac-phy-ctrl@e8 { + compatible = "syscon"; + reg = <0xe8 0x4>; + }; }; ost: timer@12000000 { @@ -97,9 +102,9 @@ #clock-cells = <1>; - clocks = <&cgu X1830_CLK_RTCLK - &cgu X1830_CLK_EXCLK - &cgu X1830_CLK_PCLK>; + clocks = <&cgu X1830_CLK_RTCLK>, + <&cgu X1830_CLK_EXCLK>, + <&cgu X1830_CLK_PCLK>; clock-names = "rtc", "ext", "pclk"; interrupt-controller; @@ -274,8 +279,7 @@ pdma: dma-controller@13420000 { compatible = "ingenic,x1830-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; + reg = <0x13420000 0x400>, <0x13421000 0x40>; #dma-cells = <2>; interrupt-parent = <&intc>; @@ -337,6 +341,8 @@ clocks = <&cgu X1830_CLK_MAC>; clock-names = "stmmaceth"; + mode-reg = <&mac_phy_ctrl>; + status = "disabled"; mdio: mdio { diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile index 72267bfda9b4..5c6433e441ee 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -1,4 +1,4 @@ -# SPDX_License_Identifier: GPL_2.0 +# SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_MACH_LOONGSON64) += loongson64_2core_2k1000.dtb dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index 5747f171de29..bfc3d3243ee7 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -23,7 +23,7 @@ }; }; - memory { + memory@200000 { compatible = "memory"; device_type = "memory"; reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */ @@ -209,8 +209,8 @@ }; pci_bridge@a,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -224,8 +224,8 @@ }; pci_bridge@b,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -239,8 +239,8 @@ }; pci_bridge@c,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -269,8 +269,8 @@ }; pci_bridge@e,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; diff --git a/arch/mips/boot/dts/loongson/loongson64g-package.dtsi b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi index 38abc570cd82..d4314f62ccc2 100644 --- a/arch/mips/boot/dts/loongson/loongson64g-package.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi @@ -39,7 +39,7 @@ }; - cpu_uart0: serial@1fe001e0 { + cpu_uart0: serial@1fe00100 { compatible = "ns16550a"; reg = <0 0x1fe00100 0x10>; clock-frequency = <100000000>; @@ -48,7 +48,7 @@ no-loopback-test; }; - cpu_uart1: serial@1fe001e8 { + cpu_uart1: serial@1fe00110 { status = "disabled"; compatible = "ns16550a"; reg = <0 0x1fe00110 0x10>; diff --git a/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts b/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts index 41f0b110d455..d0588d81e0c2 100644 --- a/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts +++ b/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts @@ -88,7 +88,7 @@ interrupt-map-mask = <0x1800 0x0 0x0 0x7>; }; - isa { + isa@18000000 { compatible = "isa"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi index 58b9bb47c58a..2f45fce2cdc4 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -409,7 +409,7 @@ }; }; - isa { + isa@18000000 { compatible = "isa"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi index 871c866e0423..6f459511e6c9 100644 --- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi @@ -21,7 +21,7 @@ <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>; }; - isa { + isa@18000000 { compatible = "isa"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index 1cf6728af8fe..046c97a29710 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -244,7 +244,7 @@ no-loopback-test; }; - eth@1f010000 { + ethernet@1f010000 { compatible = "smsc,lan9115"; reg = <0x1f010000 0x10000>; reg-io-width = <4>; diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile index 4451cf45b0ad..6749f77068a8 100644 --- a/arch/mips/boot/dts/qca/Makefile +++ b/arch/mips/boot/dts/qca/Makefile @@ -4,4 +4,5 @@ dtb-$(CONFIG_ATH79) += ar9132_tl_wr1043nd_v1.dtb dtb-$(CONFIG_ATH79) += ar9331_dpt_module.dtb dtb-$(CONFIG_ATH79) += ar9331_dragino_ms14.dtb dtb-$(CONFIG_ATH79) += ar9331_omega.dtb +dtb-$(CONFIG_ATH79) += ar9331_openembed_som9331_board.dtb dtb-$(CONFIG_ATH79) += ar9331_tl_mr3020.dtb diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi index 83b3c0ce135a..c4102b280b47 100644 --- a/arch/mips/boot/dts/qca/ar9331.dtsi +++ b/arch/mips/boot/dts/qca/ar9331.dtsi @@ -148,6 +148,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; mdio { @@ -183,6 +184,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; diff --git a/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts b/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts new file mode 100644 index 000000000000..e6622f8e8c2b --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include +#include +#include + +#include "ar9331.dtsi" + +/ { + model = "OpenEmbed SOM9331 Board"; + compatible = "openembed,som9331"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "reset"; + linux,code = ; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond 25Q64FVSIG SPI flash */ + spiflash: w25q64@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; +}; + +ð1 { + status = "okay"; +}; + +&switch_port1 { + label = "lan0"; + status = "okay"; +}; + +&switch_port3 { + label = "lan1"; + status = "okay"; +}; + +&phy_port0 { + status = "okay"; +}; + +&phy_port2 { + status = "okay"; +}; + +&phy_port4 { + status = "okay"; +}; diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 950e6c6e8629..6e4d3619137a 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -516,20 +516,13 @@ static int __init dwc3_octeon_device_init(void) if (!pdev) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - put_device(&pdev->dev); - dev_err(&pdev->dev, "No memory resources\n"); - return -ENXIO; - } - /* * The code below maps in the registers necessary for * setting up the clocks and reseting PHYs. We must * release the resources so the dwc3 subsystem doesn't * know the difference. */ - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) { put_device(&pdev->dev); return PTR_ERR(base); diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index a18609cf0e5e..f02101ff04b3 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -13,7 +13,6 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_FREEZER=y @@ -31,9 +30,8 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y CONFIG_MACH_LOONGSON64=y CONFIG_CPU_HAS_MSA=y -CONFIG_NR_CPUS=16 CONFIG_NUMA=y -CONFIG_SMP=y +CONFIG_NR_CPUS=16 CONFIG_HZ_256=y CONFIG_KEXEC=y CONFIG_MIPS32_O32=y @@ -206,7 +204,6 @@ CONFIG_VIRTIO_NET=m # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_HP is not set # CONFIG_NET_VENDOR_I825XX is not set CONFIG_E1000=y CONFIG_E1000E=y @@ -248,7 +245,6 @@ CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m CONFIG_ATH9K=m CONFIG_HOSTAP=m -CONFIG_INPUT_POLLDEV=m CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y @@ -280,7 +276,6 @@ CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM93=m CONFIG_SENSORS_W83627HF=m CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_DRM=y @@ -391,18 +386,13 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEFLATE=m CONFIG_PRINTK_TIME=y diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c index faa88a6a74c0..0a03529cf317 100644 --- a/arch/mips/crypto/crc32-mips.c +++ b/arch/mips/crypto/crc32-mips.c @@ -8,13 +8,13 @@ * Copyright (C) 2018 MIPS Tech, LLC */ -#include #include #include #include #include #include #include +#include #include diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 336e02b3b3ce..3d71081afc55 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -64,6 +64,8 @@ ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) #define __isa_range_or_flag(ge, lt, flag) \ (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) +#define __isa_range_and_ase(ge, lt, ase) \ + (__isa_range(ge, lt) && __ase(ase)) /* * SMP assumption: Options of CPU 0 are a superset of all processors. @@ -421,7 +423,7 @@ #endif #ifndef cpu_has_mipsmt -#define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) +#define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) #endif #ifndef cpu_has_vp diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h index 292d0425717f..92a380210017 100644 --- a/arch/mips/include/asm/highmem.h +++ b/arch/mips/include/asm/highmem.h @@ -36,7 +36,7 @@ extern pte_t *pkmap_page_table; * easily, subsequent pte tables have to be allocated in one physical * chunk of RAM. */ -#ifdef CONFIG_PHYS_ADDR_T_64BIT +#if defined(CONFIG_PHYS_ADDR_T_64BIT) || defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) #define LAST_PKMAP 512 #else #define LAST_PKMAP 1024 diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h index 10e3be870df7..c2144409c0c4 100644 --- a/arch/mips/include/asm/hugetlb.h +++ b/arch/mips/include/asm/hugetlb.h @@ -46,7 +46,13 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) { - flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma))); + /* + * clear the huge pte entry firstly, so that the other smp threads will + * not get old pte entry after finishing flush_tlb_page and before + * setting new huge pte entry + */ + huge_ptep_get_and_clear(vma->vm_mm, addr, ptep); + flush_tlb_page(vma, addr); } #define __HAVE_ARCH_HUGE_PTE_NONE diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index dd09c3bf0601..cbe75ade3277 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -131,10 +131,6 @@ static inline u8 ar7_chip_rev(void) 0x14))) >> 16) & 0xff; } -struct clk { - unsigned int rate; -}; - static inline int ar7_has_high_cpmac(void) { u16 chip_id = ar7_chip_id(); diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 757ce53d00e6..d51dfad8f543 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -83,52 +83,13 @@ #define MT7620_DDR2_SIZE_MIN 32 #define MT7620_DDR2_SIZE_MAX 256 -#define MT7620_GPIO_MODE_UART0_SHIFT 2 -#define MT7620_GPIO_MODE_UART0_MASK 0x7 -#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) -#define MT7620_GPIO_MODE_UARTF 0x0 -#define MT7620_GPIO_MODE_PCM_UARTF 0x1 -#define MT7620_GPIO_MODE_PCM_I2S 0x2 -#define MT7620_GPIO_MODE_I2S_UARTF 0x3 -#define MT7620_GPIO_MODE_PCM_GPIO 0x4 -#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 -#define MT7620_GPIO_MODE_GPIO_I2S 0x6 -#define MT7620_GPIO_MODE_GPIO 0x7 +extern enum ralink_soc_type ralink_soc; -#define MT7620_GPIO_MODE_NAND 0 -#define MT7620_GPIO_MODE_SD 1 -#define MT7620_GPIO_MODE_ND_SD_GPIO 2 -#define MT7620_GPIO_MODE_ND_SD_MASK 0x3 -#define MT7620_GPIO_MODE_ND_SD_SHIFT 18 - -#define MT7620_GPIO_MODE_PCIE_RST 0 -#define MT7620_GPIO_MODE_PCIE_REF 1 -#define MT7620_GPIO_MODE_PCIE_GPIO 2 -#define MT7620_GPIO_MODE_PCIE_MASK 0x3 -#define MT7620_GPIO_MODE_PCIE_SHIFT 16 - -#define MT7620_GPIO_MODE_WDT_RST 0 -#define MT7620_GPIO_MODE_WDT_REF 1 -#define MT7620_GPIO_MODE_WDT_GPIO 2 -#define MT7620_GPIO_MODE_WDT_MASK 0x3 -#define MT7620_GPIO_MODE_WDT_SHIFT 21 - -#define MT7620_GPIO_MODE_MDIO 0 -#define MT7620_GPIO_MODE_MDIO_REFCLK 1 -#define MT7620_GPIO_MODE_MDIO_GPIO 2 -#define MT7620_GPIO_MODE_MDIO_MASK 0x3 -#define MT7620_GPIO_MODE_MDIO_SHIFT 7 - -#define MT7620_GPIO_MODE_I2C 0 -#define MT7620_GPIO_MODE_UART1 5 -#define MT7620_GPIO_MODE_RGMII1 9 -#define MT7620_GPIO_MODE_RGMII2 10 -#define MT7620_GPIO_MODE_SPI 11 -#define MT7620_GPIO_MODE_SPI_REF_CLK 12 -#define MT7620_GPIO_MODE_WLED 13 -#define MT7620_GPIO_MODE_JTAG 15 -#define MT7620_GPIO_MODE_EPHY 15 -#define MT7620_GPIO_MODE_PA 20 +static inline int is_mt76x8(void) +{ + return ralink_soc == MT762X_SOC_MT7628AN || + ralink_soc == MT762X_SOC_MT7688; +} static inline int mt7620_get_eco(void) { diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h index 5d10178f26af..5f213534f0f5 100644 --- a/arch/mips/include/asm/mach-ralink/rt288x.h +++ b/arch/mips/include/asm/mach-ralink/rt288x.h @@ -33,15 +33,6 @@ #define SYSTEM_CONFIG_CPUCLK_280 0x2 #define SYSTEM_CONFIG_CPUCLK_300 0x3 -#define RT2880_GPIO_MODE_I2C BIT(0) -#define RT2880_GPIO_MODE_UART0 BIT(1) -#define RT2880_GPIO_MODE_SPI BIT(2) -#define RT2880_GPIO_MODE_UART1 BIT(3) -#define RT2880_GPIO_MODE_JTAG BIT(4) -#define RT2880_GPIO_MODE_MDIO BIT(5) -#define RT2880_GPIO_MODE_SDRAM BIT(6) -#define RT2880_GPIO_MODE_PCI BIT(7) - #define CLKCFG_SRAM_CS_N_WDT BIT(9) #define RT2880_SDRAM_BASE 0x08000000 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index b54619dc4b88..4d8e8c8d83ce 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -114,30 +114,6 @@ static inline int soc_is_rt5350(void) #define RT305X_GPIO_GE0_TXD0 40 #define RT305X_GPIO_GE0_RXCLK 51 -#define RT305X_GPIO_MODE_UART0_SHIFT 2 -#define RT305X_GPIO_MODE_UART0_MASK 0x7 -#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) -#define RT305X_GPIO_MODE_UARTF 0 -#define RT305X_GPIO_MODE_PCM_UARTF 1 -#define RT305X_GPIO_MODE_PCM_I2S 2 -#define RT305X_GPIO_MODE_I2S_UARTF 3 -#define RT305X_GPIO_MODE_PCM_GPIO 4 -#define RT305X_GPIO_MODE_GPIO_UARTF 5 -#define RT305X_GPIO_MODE_GPIO_I2S 6 -#define RT305X_GPIO_MODE_GPIO 7 - -#define RT305X_GPIO_MODE_I2C 0 -#define RT305X_GPIO_MODE_SPI 1 -#define RT305X_GPIO_MODE_UART1 5 -#define RT305X_GPIO_MODE_JTAG 6 -#define RT305X_GPIO_MODE_MDIO 7 -#define RT305X_GPIO_MODE_SDRAM 8 -#define RT305X_GPIO_MODE_RGMII 9 -#define RT5350_GPIO_MODE_PHY_LED 14 -#define RT5350_GPIO_MODE_SPI_CS1 21 -#define RT3352_GPIO_MODE_LNA 18 -#define RT3352_GPIO_MODE_PA 20 - #define RT3352_SYSC_REG_SYSCFG0 0x010 #define RT3352_SYSC_REG_SYSCFG1 0x014 #define RT3352_SYSC_REG_CLKCFG1 0x030 diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h index 565f2548496a..f250de9c055b 100644 --- a/arch/mips/include/asm/mach-ralink/rt3883.h +++ b/arch/mips/include/asm/mach-ralink/rt3883.h @@ -109,40 +109,6 @@ #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) -#define RT3883_GPIO_MODE_UART0_SHIFT 2 -#define RT3883_GPIO_MODE_UART0_MASK 0x7 -#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) -#define RT3883_GPIO_MODE_UARTF 0x0 -#define RT3883_GPIO_MODE_PCM_UARTF 0x1 -#define RT3883_GPIO_MODE_PCM_I2S 0x2 -#define RT3883_GPIO_MODE_I2S_UARTF 0x3 -#define RT3883_GPIO_MODE_PCM_GPIO 0x4 -#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 -#define RT3883_GPIO_MODE_GPIO_I2S 0x6 -#define RT3883_GPIO_MODE_GPIO 0x7 - -#define RT3883_GPIO_MODE_I2C 0 -#define RT3883_GPIO_MODE_SPI 1 -#define RT3883_GPIO_MODE_UART1 5 -#define RT3883_GPIO_MODE_JTAG 6 -#define RT3883_GPIO_MODE_MDIO 7 -#define RT3883_GPIO_MODE_GE1 9 -#define RT3883_GPIO_MODE_GE2 10 - -#define RT3883_GPIO_MODE_PCI_SHIFT 11 -#define RT3883_GPIO_MODE_PCI_MASK 0x7 -#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) -#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 -#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 -#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) -#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 -#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK) -#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 -#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 -#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) -#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 -#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) - #define RT3883_GPIO_I2C_SD 1 #define RT3883_GPIO_I2C_SCLK 2 #define RT3883_GPIO_SPI_CS0 3 diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h new file mode 100644 index 000000000000..87d085c9ad61 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_RALINK_SPACES_H_ +#define __ASM_MACH_RALINK_SPACES_H_ + +#define PCI_IOBASE _AC(0xa0000000, UL) +#define PCI_IOSIZE SZ_16M +#define IO_SPACE_LIMIT (PCI_IOSIZE - 1) + +#include +#endif diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9c8099a6ffed..acdf8c69220b 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -2077,7 +2077,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) ({ int __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r2\n\t" \ + ".set\tmips32r5\n\t" \ _ASM_SET_VIRT \ "mfgc0\t%0, " #source ", %1\n\t" \ ".set\tpop" \ @@ -2090,7 +2090,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) ({ unsigned long long __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r2\n\t" \ + ".set\tmips64r5\n\t" \ _ASM_SET_VIRT \ "dmfgc0\t%0, " #source ", %1\n\t" \ ".set\tpop" \ @@ -2103,7 +2103,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r2\n\t" \ + ".set\tmips32r5\n\t" \ _ASM_SET_VIRT \ "mtgc0\t%z0, " #register ", %1\n\t" \ ".set\tpop" \ @@ -2115,7 +2115,7 @@ do { \ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r2\n\t" \ + ".set\tmips64r5\n\t" \ _ASM_SET_VIRT \ "dmtgc0\t%z0, " #register ", %1\n\t" \ ".set\tpop" \ diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index 8b18424b3120..4b2567d6b2df 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -28,7 +28,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } -#define pmd_pgtable(pmd) pmd_page(pmd) /* * Initialize a new pmd table with invalid pointers. @@ -59,11 +58,15 @@ do { \ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { - pmd_t *pmd; + pmd_t *pmd = NULL; + struct page *pg; - pmd = (pmd_t *) __get_free_pages(GFP_KERNEL, PMD_ORDER); - if (pmd) + pg = alloc_pages(GFP_KERNEL | __GFP_ACCOUNT, PMD_ORDER); + if (pg) { + pgtable_pmd_page_ctor(pg); + pmd = (pmd_t *)page_address(pg); pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table); + } return pmd; } diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 6c0532d7b211..95df9c293d8d 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -93,7 +93,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #endif #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL #define VMALLOC_START MAP_BASE diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 1e7d6ce9d8d6..046465906c82 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -137,7 +137,6 @@ #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1) -#define FIRST_USER_ADDRESS 0UL /* * TLB refill handlers also map the vmalloc area into xuseg. Avoid diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index 5d70babfc9ee..c2196b1b6604 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -17,6 +17,10 @@ #include #include +#define __NR_N32_Linux 6000 +#define __NR_64_Linux 5000 +#define __NR_O32_Linux 4000 + #ifdef CONFIG_MIPS32_N32 #define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls) #elif defined(CONFIG_64BIT) diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h index 57dc2ac4f8bd..40b210c65a5a 100644 --- a/arch/mips/include/uapi/asm/mman.h +++ b/arch/mips/include/uapi/asm/mman.h @@ -98,6 +98,9 @@ #define MADV_COLD 20 /* deactivate these pages */ #define MADV_PAGEOUT 21 /* reclaim these pages */ +#define MADV_POPULATE_READ 22 /* populate (prefault) page tables readable */ +#define MADV_POPULATE_WRITE 23 /* populate (prefault) page tables writable */ + /* compatibility flags */ #define MAP_FILE 0 diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig index 3238e16febd5..f595b339a4b8 100644 --- a/arch/mips/ingenic/Kconfig +++ b/arch/mips/ingenic/Kconfig @@ -4,9 +4,11 @@ config MACH_INGENIC_GENERIC bool select MACH_INGENIC select MACH_JZ4740 + select MACH_JZ4725B select MACH_JZ4770 select MACH_JZ4780 select MACH_X1000 + select MACH_X1830 choice prompt "Machine type" diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0ef240adefb5..630fcb4cb30e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1840,6 +1840,11 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) */ case PRID_COMP_INGENIC_D0: c->isa_level &= ~MIPS_CPU_ISA_M32R2; + + /* FPU is not properly detected on JZ4760(B). */ + if (c->processor_id == 0x2ed0024f) + c->options |= MIPS_CPU_FPU; + fallthrough; /* diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 499a5357c09f..56b51de2dc51 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/kernel/syscalls/Makefile b/arch/mips/kernel/syscalls/Makefile index 904452992992..10bf90dc02c0 100644 --- a/arch/mips/kernel/syscalls/Makefile +++ b/arch/mips/kernel/syscalls/Makefile @@ -5,9 +5,6 @@ uapi := arch/$(SRCARCH)/include/generated/uapi/asm _dummy := $(shell [ -d '$(uapi)' ] || mkdir -p '$(uapi)') \ $(shell [ -d '$(kapi)' ] || mkdir -p '$(kapi)') -syscalln32 := $(src)/syscall_n32.tbl -syscalln64 := $(src)/syscall_n64.tbl -syscallo32 := $(src)/syscall_o32.tbl syshdr := $(srctree)/scripts/syscallhdr.sh sysnr := $(srctree)/$(src)/syscallnr.sh systbl := $(srctree)/scripts/syscalltbl.sh @@ -18,43 +15,22 @@ quiet_cmd_syshdr = SYSHDR $@ quiet_cmd_sysnr = SYSNR $@ cmd_sysnr = $(CONFIG_SHELL) '$(sysnr)' '$<' '$@' \ '$(sysnr_abis_$(basetarget))' \ - '$(sysnr_pfx_$(basetarget))' \ - '$(sysnr_offset_$(basetarget))' + '$(sysnr_pfx_$(basetarget))' quiet_cmd_systbl = SYSTBL $@ cmd_systbl = $(CONFIG_SHELL) $(systbl) $< $@ -$(uapi)/unistd_n32.h: $(syscalln32) $(syshdr) FORCE - $(call if_changed,syshdr) - -$(uapi)/unistd_n64.h: $(syscalln64) $(syshdr) FORCE - $(call if_changed,syshdr) - -$(uapi)/unistd_o32.h: $(syscallo32) $(syshdr) FORCE +$(uapi)/unistd_%.h: $(src)/syscall_%.tbl $(syshdr) FORCE $(call if_changed,syshdr) sysnr_pfx_unistd_nr_n32 := N32 -sysnr_offset_unistd_nr_n32 := 6000 -$(kapi)/unistd_nr_n32.h: $(syscalln32) $(sysnr) FORCE - $(call if_changed,sysnr) - sysnr_pfx_unistd_nr_n64 := 64 -sysnr_offset_unistd_nr_n64 := 5000 -$(kapi)/unistd_nr_n64.h: $(syscalln64) $(sysnr) FORCE - $(call if_changed,sysnr) - sysnr_pfx_unistd_nr_o32 := O32 -sysnr_offset_unistd_nr_o32 := 4000 -$(kapi)/unistd_nr_o32.h: $(syscallo32) $(sysnr) FORCE + +$(kapi)/unistd_nr_%.h: $(src)/syscall_%.tbl $(sysnr) FORCE $(call if_changed,sysnr) -$(kapi)/syscall_table_n32.h: $(syscalln32) $(systbl) FORCE - $(call if_changed,systbl) - -$(kapi)/syscall_table_n64.h: $(syscalln64) $(systbl) FORCE - $(call if_changed,systbl) - -$(kapi)/syscall_table_o32.h: $(syscallo32) $(systbl) FORCE +$(kapi)/syscall_table_%.h: $(src)/syscall_%.tbl $(systbl) FORCE $(call if_changed,systbl) uapisyshdr-y += unistd_n32.h \ diff --git a/arch/mips/kernel/syscalls/syscallnr.sh b/arch/mips/kernel/syscalls/syscallnr.sh index 60bbdb3fe03a..c190bbefbfc2 100644 --- a/arch/mips/kernel/syscalls/syscallnr.sh +++ b/arch/mips/kernel/syscalls/syscallnr.sh @@ -5,7 +5,6 @@ in="$1" out="$2" my_abis=`echo "($3)" | tr ',' '|'` prefix="$4" -offset="$5" fileguard=_UAPI_ASM_MIPS_`basename "$out" | sed \ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/' \ @@ -20,7 +19,6 @@ grep -E "^[0-9A-Fa-fXx]+[[:space:]]+${my_abis}" "$in" | sort -n | ( nxt=$((nr+1)) done - printf "#define __NR_%s_Linux\t%s\n" "${prefix}" "${offset}" printf "#define __NR_%s_Linux_syscalls\t%s\n" "${prefix}" "${nxt}" printf "\n" printf "#endif /* %s */" "${fileguard}" diff --git a/arch/mips/kvm/tlb.c b/arch/mips/kvm/tlb.c index 1088114e5482..a3b50d5e3b25 100644 --- a/arch/mips/kvm/tlb.c +++ b/arch/mips/kvm/tlb.c @@ -58,8 +58,7 @@ static int _kvm_mips_host_tlb_inv(unsigned long entryhi) tlb_probe_hazard(); idx = read_c0_index(); - if (idx >= current_cpu_data.tlbsize) - BUG(); + BUG_ON(idx >= current_cpu_data.tlbsize); if (idx >= 0) { write_c0_entryhi(UNIQUE_ENTRYHI(idx)); diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index c8bb75d58f17..c961e2999f15 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -62,7 +62,7 @@ void __init prom_lefi_init_env(void) struct efi_cpuinfo_loongson *ecpu; struct irq_source_routing_table *eirq_source; u32 id; - u16 vendor, device; + u16 vendor; /* firmware arguments are initialized in head.S */ boot_p = (struct boot_params *)fw_arg2; @@ -166,7 +166,6 @@ void __init prom_lefi_init_env(void) /* Read the ID of PCI host bridge to detect bridge type */ id = readl(HOST_BRIDGE_CONFIG_ADDR); vendor = id & 0xffff; - device = (id >> 16) & 0xffff; switch (vendor) { case PCI_VENDOR_ID_LOONGSON: diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index fa9b4a487a47..e8e3e48c5333 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -129,6 +129,9 @@ static void __init node_mem_init(unsigned int node) if (node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT)) memblock_reserve((node_addrspace_offset | 0xfe000000), 32 << 20); + + /* Reserve pfn range 0~node[0]->node_start_pfn */ + memblock_reserve(0, PAGE_SIZE * start_pfn); } } diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c index c97bfdc8c922..758d5d26aaaa 100644 --- a/arch/mips/loongson64/reset.c +++ b/arch/mips/loongson64/reset.c @@ -126,11 +126,12 @@ static void loongson_kexec_shutdown(void) for_each_possible_cpu(cpu) if (!cpu_online(cpu)) cpu_device_up(get_cpu_device(cpu)); + + secondary_kexec_args[0] = TO_UNCAC(0x3ff01000); #endif kexec_args[0] = kexec_argc; kexec_args[1] = fw_arg1; kexec_args[2] = fw_arg2; - secondary_kexec_args[0] = TO_UNCAC(0x3ff01000); memcpy((void *)fw_arg1, kexec_argv, KEXEC_ARGV_SIZE); memcpy((void *)fw_arg2, kexec_envp, KEXEC_ENVP_SIZE); } @@ -141,7 +142,9 @@ static void loongson_crash_shutdown(struct pt_regs *regs) kexec_args[0] = kdump_argc; kexec_args[1] = fw_arg1; kexec_args[2] = fw_arg2; +#ifdef CONFIG_SMP secondary_kexec_args[0] = TO_UNCAC(0x3ff01000); +#endif memcpy((void *)fw_arg1, kdump_argv, KEXEC_ARGV_SIZE); memcpy((void *)fw_arg2, kexec_envp, KEXEC_ENVP_SIZE); } diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 6acde65f601b..09ebe84a17fe 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -51,11 +51,11 @@ static uint32_t core0_c0count[NR_CPUS]; __wbflush(); \ } while (0) -u32 (*ipi_read_clear)(int cpu); -void (*ipi_write_action)(int cpu, u32 action); -void (*ipi_write_enable)(int cpu); -void (*ipi_clear_buf)(int cpu); -void (*ipi_write_buf)(int cpu, struct task_struct *idle); +static u32 (*ipi_read_clear)(int cpu); +static void (*ipi_write_action)(int cpu, u32 action); +static void (*ipi_write_enable)(int cpu); +static void (*ipi_clear_buf)(int cpu); +static void (*ipi_write_buf)(int cpu, struct task_struct *idle); /* send mail via Mail_Send register for 3A4000+ CPU */ static void csr_mail_send(uint64_t data, int cpu, int mailbox) diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 212f3ce75a6b..3c4fc97b9f39 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void) case CPU_R12000: case CPU_BMIPS5000: case CPU_LOONGSON2EF: + case CPU_XBURST: return true; default: /* diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c index 11e9527c6e44..ee7471984fe7 100644 --- a/arch/mips/mti-malta/malta-platform.c +++ b/arch/mips/mti-malta/malta-platform.c @@ -33,7 +33,8 @@ .irq = int, \ .uartclk = 1843200, \ .iotype = UPIO_PORT, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | \ + UPF_MAGIC_MULTIPLIER, \ .regshift = 0, \ } diff --git a/arch/mips/pic32/Kconfig b/arch/mips/pic32/Kconfig index 7acbb50c1dcd..bb6ab1f3e80d 100644 --- a/arch/mips/pic32/Kconfig +++ b/arch/mips/pic32/Kconfig @@ -17,7 +17,6 @@ config PIC32MZDA select SYS_SUPPORTS_LITTLE_ENDIAN select GPIOLIB select COMMON_CLK - select CLKDEV_LOOKUP select LIBFDT select USE_OF select PINCTRL diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index ec4daa63c5e3..c800bf5559b5 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -28,22 +28,18 @@ choice bool "RT288x" select MIPS_AUTO_PFN_OFFSET select MIPS_L1_CACHE_SHIFT_4 - select HAVE_LEGACY_CLK select HAVE_PCI config SOC_RT305X bool "RT305x" - select HAVE_LEGACY_CLK config SOC_RT3883 bool "RT3883" - select HAVE_LEGACY_CLK select HAVE_PCI config SOC_MT7620 bool "MT7620/8" select CPU_MIPSR2_IRQ_VI - select HAVE_LEGACY_CLK select HAVE_PCI config SOC_MT7621 @@ -54,7 +50,6 @@ choice select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_HIGHMEM select MIPS_GIC - select COMMON_CLK select CLKSRC_MIPS_GIC select HAVE_PCI if PCI_MT7621 select SOC_BUS diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index f0bcb1051c30..5b02bb7e0829 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -10,80 +10,22 @@ #include #include #include +#include #include #include "common.h" -struct clk { - struct clk_lookup cl; - unsigned long rate; -}; - void ralink_clk_add(const char *dev, unsigned long rate) { - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate); if (!clk) panic("failed to add clock"); - clk->cl.dev_id = dev; - clk->cl.clk = clk; - - clk->rate = rate; - - clkdev_add(&clk->cl); + clkdev_create(clk, NULL, "%s", dev); } -/* - * Linux clock API - */ -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL_GPL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL_GPL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->rate; -} -EXPORT_SYMBOL_GPL(clk_get_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return -1; -} -EXPORT_SYMBOL_GPL(clk_set_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - return -1; -} -EXPORT_SYMBOL_GPL(clk_round_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - WARN_ON(clk); - return -1; -} -EXPORT_SYMBOL_GPL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - WARN_ON(clk); - return NULL; -} -EXPORT_SYMBOL_GPL(clk_get_parent); - void __init plat_time_init(void) { struct clk *clk; diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 53a5969e61af..ae1fa0391c88 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "common.h" @@ -50,320 +49,6 @@ /* does the board have sdram or ddram */ static int dram_type; -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func mdio_grp[] = { - FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), - FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), -}; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct rt2880_pmx_func uartf_grp[] = { - FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func wdt_grp[] = { - FUNC("wdt rst", 0, 17, 1), - FUNC("wdt refclk", 0, 17, 1), - }; -static struct rt2880_pmx_func pcie_rst_grp[] = { - FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), - FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) -}; -static struct rt2880_pmx_func nd_sd_grp[] = { - FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), - FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) -}; - -static struct rt2880_pmx_group mt7620a_pinmux_data[] = { - GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), - GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, - MT7620_GPIO_MODE_UART0_SHIFT), - GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), - GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), - GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, - MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), - GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, - MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), - GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), - GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, - MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), - GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, - MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), - GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), - GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), - GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), - { 0 } -}; - -static struct rt2880_pmx_func pwm1_grp_mt7628[] = { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct rt2880_pmx_func pwm0_grp_mt7628[] = { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct rt2880_pmx_func uart2_grp_mt7628[] = { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct rt2880_pmx_func uart1_grp_mt7628[] = { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct rt2880_pmx_func i2c_grp_mt7628[] = { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) }; -static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) }; -static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; -static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; - -static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct rt2880_pmx_func uart0_grp_mt7628[] = { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct rt2880_pmx_func i2s_grp_mt7628[] = { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct rt2880_pmx_func spis_grp_mt7628[] = { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct rt2880_pmx_func gpio_grp_mt7628[] = { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct rt2880_pmx_func wled_an_grp_mt7628[] = { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT7628_GPIO_MODE_MASK 0x3 - -#define MT7628_GPIO_MODE_P4LED_KN 58 -#define MT7628_GPIO_MODE_P3LED_KN 56 -#define MT7628_GPIO_MODE_P2LED_KN 54 -#define MT7628_GPIO_MODE_P1LED_KN 52 -#define MT7628_GPIO_MODE_P0LED_KN 50 -#define MT7628_GPIO_MODE_WLED_KN 48 -#define MT7628_GPIO_MODE_P4LED_AN 42 -#define MT7628_GPIO_MODE_P3LED_AN 40 -#define MT7628_GPIO_MODE_P2LED_AN 38 -#define MT7628_GPIO_MODE_P1LED_AN 36 -#define MT7628_GPIO_MODE_P0LED_AN 34 -#define MT7628_GPIO_MODE_WLED_AN 32 -#define MT7628_GPIO_MODE_PWM1 30 -#define MT7628_GPIO_MODE_PWM0 28 -#define MT7628_GPIO_MODE_UART2 26 -#define MT7628_GPIO_MODE_UART1 24 -#define MT7628_GPIO_MODE_I2C 20 -#define MT7628_GPIO_MODE_REFCLK 18 -#define MT7628_GPIO_MODE_PERST 16 -#define MT7628_GPIO_MODE_WDT 14 -#define MT7628_GPIO_MODE_SPI 12 -#define MT7628_GPIO_MODE_SDMODE 10 -#define MT7628_GPIO_MODE_UART0 8 -#define MT7628_GPIO_MODE_I2S 6 -#define MT7628_GPIO_MODE_CS1 4 -#define MT7628_GPIO_MODE_SPIS 2 -#define MT7628_GPIO_MODE_GPIO 0 - -static struct rt2880_pmx_group mt7628an_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_KN), - { 0 } -}; - -static inline int is_mt76x8(void) -{ - return ralink_soc == MT762X_SOC_MT7628AN || - ralink_soc == MT762X_SOC_MT7688; -} - static __init u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { @@ -710,9 +395,4 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - - if (is_mt76x8()) - rt2880_pinmux_data = mt7628an_pinmux_data; - else - rt2880_pinmux_data = mt7620a_pinmux_data; } diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index f82ad2a621f6..bd71f5b14238 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -18,97 +18,10 @@ #include #include -#include - #include "common.h" -#define MT7621_GPIO_MODE_UART1 1 -#define MT7621_GPIO_MODE_I2C 2 -#define MT7621_GPIO_MODE_UART3_MASK 0x3 -#define MT7621_GPIO_MODE_UART3_SHIFT 3 -#define MT7621_GPIO_MODE_UART3_GPIO 1 -#define MT7621_GPIO_MODE_UART2_MASK 0x3 -#define MT7621_GPIO_MODE_UART2_SHIFT 5 -#define MT7621_GPIO_MODE_UART2_GPIO 1 -#define MT7621_GPIO_MODE_JTAG 7 -#define MT7621_GPIO_MODE_WDT_MASK 0x3 -#define MT7621_GPIO_MODE_WDT_SHIFT 8 -#define MT7621_GPIO_MODE_WDT_GPIO 1 -#define MT7621_GPIO_MODE_PCIE_RST 0 -#define MT7621_GPIO_MODE_PCIE_REF 2 -#define MT7621_GPIO_MODE_PCIE_MASK 0x3 -#define MT7621_GPIO_MODE_PCIE_SHIFT 10 -#define MT7621_GPIO_MODE_PCIE_GPIO 1 -#define MT7621_GPIO_MODE_MDIO_MASK 0x3 -#define MT7621_GPIO_MODE_MDIO_SHIFT 12 -#define MT7621_GPIO_MODE_MDIO_GPIO 1 -#define MT7621_GPIO_MODE_RGMII1 14 -#define MT7621_GPIO_MODE_RGMII2 15 -#define MT7621_GPIO_MODE_SPI_MASK 0x3 -#define MT7621_GPIO_MODE_SPI_SHIFT 16 -#define MT7621_GPIO_MODE_SPI_GPIO 1 -#define MT7621_GPIO_MODE_SDHCI_MASK 0x3 -#define MT7621_GPIO_MODE_SDHCI_SHIFT 18 -#define MT7621_GPIO_MODE_SDHCI_GPIO 1 - static void *detect_magic __initdata = detect_memory_region; -static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct rt2880_pmx_func uart3_grp[] = { - FUNC("uart3", 0, 5, 4), - FUNC("i2s", 2, 5, 4), - FUNC("spdif3", 3, 5, 4), -}; -static struct rt2880_pmx_func uart2_grp[] = { - FUNC("uart2", 0, 9, 4), - FUNC("pcm", 2, 9, 4), - FUNC("spdif2", 3, 9, 4), -}; -static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct rt2880_pmx_func wdt_grp[] = { - FUNC("wdt rst", 0, 18, 1), - FUNC("wdt refclk", 2, 18, 1), -}; -static struct rt2880_pmx_func pcie_rst_grp[] = { - FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), - FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) -}; -static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct rt2880_pmx_func spi_grp[] = { - FUNC("spi", 0, 34, 7), - FUNC("nand1", 2, 34, 7), -}; -static struct rt2880_pmx_func sdhci_grp[] = { - FUNC("sdhci", 0, 41, 8), - FUNC("nand2", 2, 41, 8), -}; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; - -static struct rt2880_pmx_group mt7621_pinmux_data[] = { - GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), - GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), - GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, - MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), - GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, - MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), - GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), - GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, - MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), - GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, - MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), - GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, - MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), - GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, - MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), - GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, - MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), - { 0 } -}; - phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); @@ -219,7 +132,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); soc_info->mem_detect = mt7621_memory_detect; - rt2880_pinmux_data = mt7621_pinmux_data; soc_dev_init(soc_info, rev); diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c index 25728def3503..aaac1e6ec7d9 100644 --- a/arch/mips/ralink/prom.c +++ b/arch/mips/ralink/prom.c @@ -18,7 +18,6 @@ #include "common.h" struct ralink_soc_info soc_info; -struct rt2880_pmx_group *rt2880_pinmux_data = NULL; enum ralink_soc_type ralink_soc; EXPORT_SYMBOL_GPL(ralink_soc); diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 34083c70ec68..493335db2fe1 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -14,29 +14,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; - -static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { - GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), - GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), - GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO), - GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM), - GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI), - { 0 } -}; - void __init ralink_clk_init(void) { unsigned long cpu_rate, wmac_rate = 40000000; @@ -106,6 +86,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; - rt2880_pinmux_data = rt2880_pinmux_data_act; ralink_soc = RT2880_SOC; } diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index c5b63c142705..8b095a9dcb15 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -16,83 +16,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { - FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; -static struct rt2880_pmx_func rt5350_cs1_func[] = { - FUNC("spi_cs1", 0, 27, 1), - FUNC("wdg_cs1", 1, 27, 1), -}; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func rt3352_rgmii_func[] = { - FUNC("rgmii", 0, 24, 12) -}; -static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; -static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; -static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; -static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; -static struct rt2880_pmx_func rt3352_cs1_func[] = { - FUNC("spi_cs1", 0, 45, 1), - FUNC("wdg_cs1", 1, 45, 1), -}; - -static struct rt2880_pmx_group rt3050_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), - { 0 } -}; - -static struct rt2880_pmx_group rt3352_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), - GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), - GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), - { 0 } -}; - -static struct rt2880_pmx_group rt5350_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), - { 0 } -}; - static unsigned long rt5350_get_mem_size(void) { void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); @@ -265,14 +191,11 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_base = RT305X_SDRAM_BASE; if (soc_is_rt5350()) { soc_info->mem_size = rt5350_get_mem_size(); - rt2880_pinmux_data = rt5350_pinmux_data; } else if (soc_is_rt305x() || soc_is_rt3350()) { soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3050_pinmux_data; } else if (soc_is_rt3352()) { soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3352_pinmux_data; } } diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index ff91f3531ad0..d9875f146d66 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -14,52 +14,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { - FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; -static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; -static struct rt2880_pmx_func pci_func[] = { - FUNC("pci-dev", 0, 40, 32), - FUNC("pci-host2", 1, 40, 32), - FUNC("pci-host1", 2, 40, 32), - FUNC("pci-fnc", 3, 40, 32) -}; -static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; -static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; - -static struct rt2880_pmx_group rt3883_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, - RT3883_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO), - GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A), - GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G), - GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK, - RT3883_GPIO_MODE_PCI_SHIFT), - GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1), - GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2), - { 0 } -}; - void __init ralink_clk_init(void) { unsigned long cpu_rate, sys_rate; @@ -142,7 +99,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3883_pinmux_data; - ralink_soc = RT3883_SOC; } diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index c374f3ceec38..9028dbbb45dd 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 20d8637340be..18d1c115cd53 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/nds32/include/asm/pgalloc.h b/arch/nds32/include/asm/pgalloc.h index 85c117347c86..a08e1ebca70e 100644 --- a/arch/nds32/include/asm/pgalloc.h +++ b/arch/nds32/include/asm/pgalloc.h @@ -12,11 +12,6 @@ #define __HAVE_ARCH_PTE_ALLOC_ONE #include /* for pte_{alloc,free}_one */ -/* - * Since we have only two-level page tables, these are trivial - */ -#define pmd_pgtable(pmd) pmd_page(pmd) - extern pgd_t *pgd_alloc(struct mm_struct *mm); extern void pgd_free(struct mm_struct *mm, pgd_t * pgd); diff --git a/arch/nios2/include/asm/pgalloc.h b/arch/nios2/include/asm/pgalloc.h index e6600d2a5ae0..3c4ae74d5798 100644 --- a/arch/nios2/include/asm/pgalloc.h +++ b/arch/nios2/include/asm/pgalloc.h @@ -25,7 +25,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } -#define pmd_pgtable(pmd) pmd_page(pmd) /* * Initialize a new pmd table with invalid pointers. diff --git a/arch/nios2/include/asm/pgtable.h b/arch/nios2/include/asm/pgtable.h index 2600d76c310c..4a995fa628ee 100644 --- a/arch/nios2/include/asm/pgtable.h +++ b/arch/nios2/include/asm/pgtable.h @@ -24,8 +24,6 @@ #include #include -#define FIRST_USER_ADDRESS 0UL - #define VMALLOC_START CONFIG_NIOS2_KERNEL_MMU_REGION_BASE #define VMALLOC_END (CONFIG_NIOS2_KERNEL_REGION_BASE - 1) diff --git a/arch/openrisc/include/asm/pgalloc.h b/arch/openrisc/include/asm/pgalloc.h index 88820299ecc4..b7b2b8d16fad 100644 --- a/arch/openrisc/include/asm/pgalloc.h +++ b/arch/openrisc/include/asm/pgalloc.h @@ -72,6 +72,4 @@ do { \ tlb_remove_page((tlb), (pte)); \ } while (0) -#define pmd_pgtable(pmd) pmd_page(pmd) - #endif diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h index 9425bedab4fc..4ac591c9ca33 100644 --- a/arch/openrisc/include/asm/pgtable.h +++ b/arch/openrisc/include/asm/pgtable.h @@ -73,7 +73,6 @@ extern void paging_init(void); */ #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL /* * Kernels own virtual memory area. diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h deleted file mode 100644 index 14353f2101f2..000000000000 --- a/arch/openrisc/include/asm/unaligned.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * OpenRISC Linux - * - * Linux architectural port borrowing liberally from similar works of - * others. All original copyrights apply as per the original source - * declaration. - * - * OpenRISC implementation: - * Copyright (C) 2003 Matjaz Breskvar - * Copyright (C) 2010-2011 Jonas Bonn - * et al. - */ - -#ifndef __ASM_OPENRISC_UNALIGNED_H -#define __ASM_OPENRISC_UNALIGNED_H - -/* - * This is copied from the generic implementation and the C-struct - * variant replaced with the memmove variant. The GCC compiler - * for the OR32 arch optimizes too aggressively for the C-struct - * variant to work, so use the memmove variant instead. - * - * It may be worth considering implementing the unaligned access - * exception handler and allowing unaligned accesses (access_ok.h)... - * not sure if it would be much of a performance win without further - * investigation. - */ -#include - -#if defined(__LITTLE_ENDIAN) -# include -# include -# include -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#elif defined(__BIG_ENDIAN) -# include -# include -# include -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#else -# error need to define endianess -#endif - -#endif /* __ASM_OPENRISC_UNALIGNED_H */ diff --git a/arch/parisc/include/asm/pgalloc.h b/arch/parisc/include/asm/pgalloc.h index dda557085311..6a7e98e71f1d 100644 --- a/arch/parisc/include/asm/pgalloc.h +++ b/arch/parisc/include/asm/pgalloc.h @@ -69,6 +69,5 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) #define pmd_populate(mm, pmd, pte_page) \ pmd_populate_kernel(mm, pmd, page_address(pte_page)) -#define pmd_pgtable(pmd) pmd_page(pmd) #endif diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index 39017210dbf0..7f33c29764cc 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h @@ -171,8 +171,6 @@ static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr) * pgd entries used up by user/kernel: */ -#define FIRST_USER_ADDRESS 0UL - /* NB: The tlb miss handlers make certain assumptions about the order */ /* of the following bits, so be careful (One example, bits 25-31 */ /* are moved together in one instruction). */ diff --git a/arch/parisc/include/asm/unaligned.h b/arch/parisc/include/asm/unaligned.h index e9029c7c2a69..3bda16773ba6 100644 --- a/arch/parisc/include/asm/unaligned.h +++ b/arch/parisc/include/asm/unaligned.h @@ -2,11 +2,7 @@ #ifndef _ASM_PARISC_UNALIGNED_H #define _ASM_PARISC_UNALIGNED_H -#include -#include -#include -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be +#include #ifdef __KERNEL__ struct pt_regs; diff --git a/arch/parisc/include/uapi/asm/mman.h b/arch/parisc/include/uapi/asm/mman.h index ab78cba446ed..9e3c010c0f61 100644 --- a/arch/parisc/include/uapi/asm/mman.h +++ b/arch/parisc/include/uapi/asm/mman.h @@ -52,6 +52,9 @@ #define MADV_COLD 20 /* deactivate these pages */ #define MADV_PAGEOUT 21 /* reclaim these pages */ +#define MADV_POPULATE_READ 22 /* populate (prefault) page tables readable */ +#define MADV_POPULATE_WRITE 23 /* populate (prefault) page tables writable */ + #define MADV_MERGEABLE 65 /* KSM may merge identical pages */ #define MADV_UNMERGEABLE 66 /* KSM may not merge identical pages */ diff --git a/arch/parisc/kernel/pdc_chassis.c b/arch/parisc/kernel/pdc_chassis.c index 75ae88d13909..da154406d368 100644 --- a/arch/parisc/kernel/pdc_chassis.c +++ b/arch/parisc/kernel/pdc_chassis.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c index 7ed404c60a9e..39ccad063533 100644 --- a/arch/parisc/kernel/pdc_cons.c +++ b/arch/parisc/kernel/pdc_cons.c @@ -103,22 +103,16 @@ static int pdc_console_tty_write(struct tty_struct *tty, const unsigned char *bu return count; } -static int pdc_console_tty_write_room(struct tty_struct *tty) +static unsigned int pdc_console_tty_write_room(struct tty_struct *tty) { return 32768; /* no limit, no buffer used */ } -static int pdc_console_tty_chars_in_buffer(struct tty_struct *tty) -{ - return 0; /* no buffer */ -} - static const struct tty_operations pdc_console_tty_ops = { .open = pdc_console_tty_open, .close = pdc_console_tty_close, .write = pdc_console_tty_write, .write_room = pdc_console_tty_write_room, - .chars_in_buffer = pdc_console_tty_chars_in_buffer, }; static void pdc_console_poll(struct timer_list *unused) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 14b132cf95e2..d01e3401581d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -140,7 +140,9 @@ config PPC select ARCH_HAS_PTE_DEVMAP if PPC_BOOK3S_64 select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64 + select ARCH_HAS_SET_MEMORY select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION) + select ARCH_HAS_STRICT_MODULE_RWX if ARCH_HAS_STRICT_KERNEL_RWX && !PPC_BOOK3S_32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UACCESS_FLUSHCACHE select ARCH_HAS_UBSAN_SANITIZE_ALL @@ -187,7 +189,7 @@ config PPC select GENERIC_VDSO_TIME_NS select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP - select HAVE_ARCH_HUGE_VMAP if PPC_BOOK3S_64 && PPC_RADIX_MMU + select HAVE_ARCH_HUGE_VMAP if PPC_RADIX_MMU || PPC_8xx select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_ARCH_KASAN if PPC32 && PPC_PAGE_SHIFT <= 14 @@ -266,6 +268,7 @@ config PPC select PPC_DAWR if PPC64 select RTC_LIB select SPARSE_IRQ + select STRICT_KERNEL_RWX if STRICT_MODULE_RWX select SYSCTL_EXCEPTION_TRACE select THREAD_INFO_IN_TASK select VIRT_TO_BUS if !PPC64 @@ -289,6 +292,7 @@ config PANIC_TIMEOUT config COMPAT bool "Enable support for 32bit binaries" depends on PPC64 + depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 default y if !CPU_LITTLE_ENDIAN select ARCH_WANT_OLD_COMPAT_IPC select COMPAT_OLD_SIGACTION @@ -403,10 +407,6 @@ config PPC_ADV_DEBUG_DAC_RANGE config PPC_DAWR bool -config ZONE_DMA - bool - default y if PPC_BOOK3E_64 - config PGTABLE_LEVELS int default 2 if !PPC64 @@ -426,7 +426,7 @@ source "kernel/Kconfig.hz" config MATH_EMULATION bool "Math emulation" - depends on 4xx || PPC_8xx || PPC_MPC832x || BOOKE + depends on 4xx || PPC_8xx || PPC_MPC832x || BOOKE || PPC_MICROWATT select PPC_FPU_REGS help Some PowerPC chips designed for embedded applications do not have diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index 6342f9da4545..205cd77f321f 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -84,6 +84,11 @@ config MSI_BITMAP_SELFTEST config PPC_IRQ_SOFT_MASK_DEBUG bool "Include extra checks for powerpc irq soft masking" + depends on PPC64 + +config PPC_RFI_SRR_DEBUG + bool "Include extra checks for RFI SRR register validity" + depends on PPC_BOOK3S_64 config XMON bool "Include xmon kernel debugger" diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 3212d076ac6a..712c5e8768ce 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -376,6 +376,16 @@ ppc64_book3e_allmodconfig: $(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/85xx-64bit.config \ -f $(srctree)/Makefile allmodconfig +PHONY += ppc32_randconfig +ppc32_randconfig: + $(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/32-bit.config \ + -f $(srctree)/Makefile randconfig + +PHONY += ppc64_randconfig +ppc64_randconfig: + $(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/64-bit.config \ + -f $(srctree)/Makefile randconfig + define archhelp @echo '* zImage - Build default images selected by kernel config' @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)' diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 2b8da923ceca..e312ea802aa6 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -163,6 +163,8 @@ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c +src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c + src-wlib := $(sort $(src-wlib-y)) src-plat := $(sort $(src-plat-y)) src-boot := $(src-wlib) $(src-plat) empty.c @@ -227,7 +229,7 @@ $(obj)/wrapper.a: $(obj-wlib) FORCE hostprogs := addnote hack-coff mktree -targets += $(patsubst $(obj)/%,%,$(obj-boot) wrapper.a) +targets += $(patsubst $(obj)/%,%,$(obj-boot) wrapper.a) zImage.lds extra-y := $(obj)/wrapper.a $(obj-plat) $(obj)/empty.o \ $(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds @@ -355,6 +357,8 @@ image-$(CONFIG_MVME5100) += dtbImage.mvme5100 # Board port in arch/powerpc/platform/amigaone/Kconfig image-$(CONFIG_AMIGAONE) += cuImage.amigaone +image-$(CONFIG_PPC_MICROWATT) += dtbImage.microwatt + # For 32-bit powermacs, build the COFF and miboot images # as well as the ELF images. ifdef CONFIG_PPC32 diff --git a/arch/powerpc/boot/decompress.c b/arch/powerpc/boot/decompress.c index 6098b879ac97..977eb15a6d17 100644 --- a/arch/powerpc/boot/decompress.c +++ b/arch/powerpc/boot/decompress.c @@ -99,8 +99,8 @@ static void print_err(char *s) * partial_decompress - decompresses part or all of a compressed buffer * @inbuf: input buffer * @input_size: length of the input buffer - * @outbuf: input buffer - * @output_size: length of the input buffer + * @outbuf: output buffer + * @output_size: length of the output buffer * @skip number of output bytes to ignore * * This function takes compressed data from inbuf, decompresses and write it to diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c index 5d91036ad626..58fbcfcc98c9 100644 --- a/arch/powerpc/boot/devtree.c +++ b/arch/powerpc/boot/devtree.c @@ -13,6 +13,7 @@ #include "string.h" #include "stdio.h" #include "ops.h" +#include "of.h" void dt_fixup_memory(u64 start, u64 size) { @@ -23,21 +24,25 @@ void dt_fixup_memory(u64 start, u64 size) root = finddevice("/"); if (getprop(root, "#address-cells", &naddr, sizeof(naddr)) < 0) naddr = 2; + else + naddr = be32_to_cpu(naddr); if (naddr < 1 || naddr > 2) fatal("Can't cope with #address-cells == %d in /\n\r", naddr); if (getprop(root, "#size-cells", &nsize, sizeof(nsize)) < 0) nsize = 1; + else + nsize = be32_to_cpu(nsize); if (nsize < 1 || nsize > 2) fatal("Can't cope with #size-cells == %d in /\n\r", nsize); i = 0; if (naddr == 2) - memreg[i++] = start >> 32; - memreg[i++] = start & 0xffffffff; + memreg[i++] = cpu_to_be32(start >> 32); + memreg[i++] = cpu_to_be32(start & 0xffffffff); if (nsize == 2) - memreg[i++] = size >> 32; - memreg[i++] = size & 0xffffffff; + memreg[i++] = cpu_to_be32(size >> 32); + memreg[i++] = cpu_to_be32(size & 0xffffffff); memory = finddevice("/memory"); if (! memory) { @@ -45,9 +50,9 @@ void dt_fixup_memory(u64 start, u64 size) setprop_str(memory, "device_type", "memory"); } - printf("Memory <- <0x%x", memreg[0]); + printf("Memory <- <0x%x", be32_to_cpu(memreg[0])); for (i = 1; i < (naddr + nsize); i++) - printf(" 0x%x", memreg[i]); + printf(" 0x%x", be32_to_cpu(memreg[i])); printf("> (%ldMB)\n\r", (unsigned long)(size >> 20)); setprop(memory, "reg", memreg, (naddr + nsize)*sizeof(u32)); @@ -65,10 +70,10 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus) printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); while ((devp = find_node_by_devtype(devp, "cpu"))) { - setprop_val(devp, "clock-frequency", cpu); - setprop_val(devp, "timebase-frequency", tb); + setprop_val(devp, "clock-frequency", cpu_to_be32(cpu)); + setprop_val(devp, "timebase-frequency", cpu_to_be32(tb)); if (bus > 0) - setprop_val(devp, "bus-frequency", bus); + setprop_val(devp, "bus-frequency", cpu_to_be32(bus)); } timebase_period_ns = 1000000000 / tb; @@ -80,7 +85,7 @@ void dt_fixup_clock(const char *path, u32 freq) if (devp) { printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); - setprop_val(devp, "clock-frequency", freq); + setprop_val(devp, "clock-frequency", cpu_to_be32(freq)); } } @@ -133,8 +138,12 @@ void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize) { if (getprop(node, "#address-cells", naddr, 4) != 4) *naddr = 2; + else + *naddr = be32_to_cpu(*naddr); if (getprop(node, "#size-cells", nsize, 4) != 4) *nsize = 1; + else + *nsize = be32_to_cpu(*nsize); } static void copy_val(u32 *dest, u32 *src, int naddr) @@ -163,9 +172,9 @@ static int add_reg(u32 *reg, u32 *add, int naddr) int i, carry = 0; for (i = MAX_ADDR_CELLS - 1; i >= MAX_ADDR_CELLS - naddr; i--) { - u64 tmp = (u64)reg[i] + add[i] + carry; + u64 tmp = (u64)be32_to_cpu(reg[i]) + be32_to_cpu(add[i]) + carry; carry = tmp >> 32; - reg[i] = (u32)tmp; + reg[i] = cpu_to_be32((u32)tmp); } return !carry; @@ -180,18 +189,18 @@ static int compare_reg(u32 *reg, u32 *range, u32 *rangesize) u32 end; for (i = 0; i < MAX_ADDR_CELLS; i++) { - if (reg[i] < range[i]) + if (be32_to_cpu(reg[i]) < be32_to_cpu(range[i])) return 0; - if (reg[i] > range[i]) + if (be32_to_cpu(reg[i]) > be32_to_cpu(range[i])) break; } for (i = 0; i < MAX_ADDR_CELLS; i++) { - end = range[i] + rangesize[i]; + end = be32_to_cpu(range[i]) + be32_to_cpu(rangesize[i]); - if (reg[i] < end) + if (be32_to_cpu(reg[i]) < end) break; - if (reg[i] > end) + if (be32_to_cpu(reg[i]) > end) return 0; } @@ -240,7 +249,6 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr, return 0; dt_get_reg_format(parent, &naddr, &nsize); - if (nsize > 2) return 0; @@ -252,10 +260,10 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr, copy_val(last_addr, prop_buf + offset, naddr); - ret_size = prop_buf[offset + naddr]; + ret_size = be32_to_cpu(prop_buf[offset + naddr]); if (nsize == 2) { ret_size <<= 32; - ret_size |= prop_buf[offset + naddr + 1]; + ret_size |= be32_to_cpu(prop_buf[offset + naddr + 1]); } for (;;) { @@ -278,7 +286,6 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr, offset = find_range(last_addr, prop_buf, prev_naddr, naddr, prev_nsize, buflen / 4); - if (offset < 0) return 0; @@ -296,8 +303,7 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr, if (naddr > 2) return 0; - ret_addr = ((u64)last_addr[2] << 32) | last_addr[3]; - + ret_addr = ((u64)be32_to_cpu(last_addr[2]) << 32) | be32_to_cpu(last_addr[3]); if (sizeof(void *) == 4 && (ret_addr >= 0x100000000ULL || ret_size > 0x100000000ULL || ret_addr + ret_size > 0x100000000ULL)) @@ -350,11 +356,14 @@ int dt_is_compatible(void *node, const char *compat) int dt_get_virtual_reg(void *node, void **addr, int nres) { unsigned long xaddr; - int n; + int n, i; n = getprop(node, "virtual-reg", addr, nres * 4); - if (n > 0) + if (n > 0) { + for (i = 0; i < n/4; i ++) + ((u32 *)addr)[i] = be32_to_cpu(((u32 *)addr)[i]); return n / 4; + } for (n = 0; n < nres; n++) { if (!dt_xlate_reg(node, n, &xaddr, NULL)) diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts new file mode 100644 index 000000000000..974abbdda249 --- /dev/null +++ b/arch/powerpc/boot/dts/microwatt.dts @@ -0,0 +1,138 @@ +/dts-v1/; + +/ { + #size-cells = <0x02>; + #address-cells = <0x02>; + model-name = "microwatt"; + compatible = "microwatt-soc"; + + aliases { + serial0 = &UART0; + }; + + reserved-memory { + #size-cells = <0x02>; + #address-cells = <0x02>; + ranges; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x10000000>; + }; + + cpus { + #size-cells = <0x00>; + #address-cells = <0x01>; + + ibm,powerpc-cpu-features { + display-name = "Microwatt"; + isa = <3000>; + device_type = "cpu-features"; + compatible = "ibm,powerpc-cpu-features"; + + mmu-radix { + isa = <3000>; + usable-privilege = <2>; + }; + + little-endian { + isa = <2050>; + usable-privilege = <3>; + hwcap-bit-nr = <1>; + }; + + cache-inhibited-large-page { + isa = <2040>; + usable-privilege = <2>; + }; + + fixed-point-v3 { + isa = <3000>; + usable-privilege = <3>; + }; + + no-execute { + isa = <2010>; + usable-privilege = <2>; + }; + + floating-point { + hwcap-bit-nr = <27>; + isa = <0>; + usable-privilege = <3>; + }; + }; + + PowerPC,Microwatt@0 { + i-cache-sets = <2>; + ibm,dec-bits = <64>; + reservation-granule-size = <64>; + clock-frequency = <100000000>; + timebase-frequency = <100000000>; + i-tlb-sets = <1>; + ibm,ppc-interrupt-server#s = <0>; + i-cache-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <2>; + i-tlb-size = <64>; + cpu-version = <0x990000>; + status = "okay"; + i-cache-size = <0x1000>; + ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>; + tlb-size = <0>; + tlb-sets = <0>; + device_type = "cpu"; + d-tlb-size = <128>; + d-tlb-sets = <2>; + reg = <0>; + general-purpose; + 64-bit; + d-cache-size = <0x1000>; + ibm,chip-id = <0>; + }; + }; + + soc@c0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&ICS>; + + ranges = <0 0 0xc0000000 0x40000000>; + + interrupt-controller@4000 { + compatible = "openpower,xics-presentation", "ibm,ppc-xicp"; + ibm,interrupt-server-ranges = <0x0 0x1>; + reg = <0x4000 0x100>; + }; + + ICS: interrupt-controller@5000 { + compatible = "openpower,xics-sources"; + interrupt-controller; + interrupt-ranges = <0x10 0x10>; + reg = <0x5000 0x100>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UART0: serial@2000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x2000 0x8>; + clock-frequency = <100000000>; + current-speed = <115200>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0x10 0x1>; + }; + }; + + chosen { + bootargs = ""; + ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 40 00 40]; + stdout-path = &UART0; + }; +}; diff --git a/arch/powerpc/boot/microwatt.c b/arch/powerpc/boot/microwatt.c new file mode 100644 index 000000000000..ca9d83617fc1 --- /dev/null +++ b/arch/powerpc/boot/microwatt.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include "stdio.h" +#include "types.h" +#include "io.h" +#include "ops.h" + +BSS_STACK(8192); + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5) +{ + unsigned long heapsize = 16*1024*1024 - (unsigned long)_end; + + /* + * Disable interrupts and turn off MSR_RI, since we'll + * shortly be overwriting the interrupt vectors. + */ + __asm__ volatile("mtmsrd %0,1" : : "r" (0)); + + simple_alloc_init(_end, heapsize, 32, 64); + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/ns16550.c b/arch/powerpc/boot/ns16550.c index b0da4466d419..f16d2be1d0f3 100644 --- a/arch/powerpc/boot/ns16550.c +++ b/arch/powerpc/boot/ns16550.c @@ -15,6 +15,7 @@ #include "stdio.h" #include "io.h" #include "ops.h" +#include "of.h" #define UART_DLL 0 /* Out: Divisor Latch Low */ #define UART_DLM 1 /* Out: Divisor Latch High */ @@ -58,16 +59,20 @@ int ns16550_console_init(void *devp, struct serial_console_data *scdp) int n; u32 reg_offset; - if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) + if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) { + printf("virt reg parse fail...\r\n"); return -1; + } n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset)); if (n == sizeof(reg_offset)) - reg_base += reg_offset; + reg_base += be32_to_cpu(reg_offset); n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift)); if (n != sizeof(reg_shift)) reg_shift = 0; + else + reg_shift = be32_to_cpu(reg_shift); scdp->open = ns16550_open; scdp->putc = ns16550_putc; diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index cdb796b76e2e..1f4676bab786 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -342,6 +342,11 @@ gamecube|wii) link_address='0x600000' platformo="$object/$platform-head.o $object/$platform.o" ;; +microwatt) + link_address='0x500000' + platformo="$object/fixed-head.o $object/$platform.o" + binary=y + ;; treeboot-currituck) link_address='0x1000000' ;; diff --git a/arch/powerpc/boot/zImage.ps3.lds.S b/arch/powerpc/boot/zImage.ps3.lds.S index 7b2ff2eaa73a..d0ffb493614d 100644 --- a/arch/powerpc/boot/zImage.ps3.lds.S +++ b/arch/powerpc/boot/zImage.ps3.lds.S @@ -8,7 +8,7 @@ SECTIONS .kernel:vmlinux.bin : { *(.kernel:vmlinux.bin) } _vmlinux_end = .; - . = ALIGN(4096); + . = ALIGN(8); _dtb_start = .; .kernel:dtb : { *(.kernel:dtb) } _dtb_end = .; diff --git a/arch/powerpc/configs/32-bit.config b/arch/powerpc/configs/32-bit.config new file mode 100644 index 000000000000..ad6546850c68 --- /dev/null +++ b/arch/powerpc/configs/32-bit.config @@ -0,0 +1 @@ +# CONFIG_PPC64 is not set diff --git a/arch/powerpc/configs/64-bit.config b/arch/powerpc/configs/64-bit.config new file mode 100644 index 000000000000..0fe6406929e2 --- /dev/null +++ b/arch/powerpc/configs/64-bit.config @@ -0,0 +1 @@ +CONFIG_PPC64=y diff --git a/arch/powerpc/configs/microwatt_defconfig b/arch/powerpc/configs/microwatt_defconfig new file mode 100644 index 000000000000..a08b739123da --- /dev/null +++ b/arch/powerpc/configs/microwatt_defconfig @@ -0,0 +1,98 @@ +# CONFIG_SWAP is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12 +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_PPC64=y +# CONFIG_PPC_KUEP is not set +# CONFIG_PPC_KUAP is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_NR_IRQS=64 +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_PPC_POWERNV is not set +# CONFIG_PPC_PSERIES is not set +CONFIG_PPC_MICROWATT=y +# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set +CONFIG_CPU_FREQ=y +CONFIG_HZ_100=y +# CONFIG_PPC_MEM_KEYS is not set +# CONFIG_SECCOMP is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_COREDUMP is not set +# CONFIG_COMPACTION is not set +# CONFIG_MIGRATION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_INET=y +CONFIG_INET_UDP_DIAG=y +CONFIG_INET_RAW_DIAG=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_PARTITIONED_MASTER=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_NVRAM is not set +CONFIG_RANDOM_TRUST_CPU=y +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_SPIDEV=y +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_VIRTIO_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_PRINTK_TIME=y +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MISC is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_FTRACE is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_PPC_DISABLE_WERROR=y +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +# CONFIG_XMON_DEFAULT_RO_MODE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig index 949ff9ccda5e..d21f266cea9a 100644 --- a/arch/powerpc/configs/mpc885_ads_defconfig +++ b/arch/powerpc/configs/mpc885_ads_defconfig @@ -57,3 +57,28 @@ CONFIG_CRC32_SLICEBY4=y CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DETECT_HUNG_TASK=y +CONFIG_PPC_16K_PAGES=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_FS=y +CONFIG_PPC_PTDUMP=y +CONFIG_MODULES=y +CONFIG_SPI=y +CONFIG_SPI_FSL_SPI=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_DEV_TALITOS=y +CONFIG_8xx_GPIO=y +CONFIG_WATCHDOG=y +CONFIG_8xxx_WDT=y +CONFIG_SMC_UCODE_PATCH=y +CONFIG_ADVANCED_OPTIONS=y +CONFIG_PIN_TLB=y +CONFIG_PERF_EVENTS=y +CONFIG_MATH_EMULATION=y +CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_IPV6=y +CONFIG_BPF_JIT=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_BDI_SWITCH=y +CONFIG_PPC_EARLY_DEBUG=y +CONFIG_PPC_EARLY_DEBUG_CPM_ADDR=0xff002008 diff --git a/arch/powerpc/configs/powernv_defconfig b/arch/powerpc/configs/powernv_defconfig index 2c87e856d839..8bfeea6c7de7 100644 --- a/arch/powerpc/configs/powernv_defconfig +++ b/arch/powerpc/configs/powernv_defconfig @@ -309,6 +309,7 @@ CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_HARDLOCKUP_DETECTOR=y CONFIG_FUNCTION_TRACER=y CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y CONFIG_FTRACE_SYSCALLS=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_PPC_EMULATED_STATS=y diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index 701811c91a6f..0ad2291337a7 100644 --- a/arch/powerpc/configs/ppc64_defconfig +++ b/arch/powerpc/configs/ppc64_defconfig @@ -368,7 +368,9 @@ CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_HARDLOCKUP_DETECTOR=y CONFIG_DEBUG_MUTEXES=y CONFIG_FUNCTION_TRACER=y +CONFIG_FTRACE_SYSCALLS=y CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_CODE_PATCHING_SELFTEST=y CONFIG_FTR_FIXUP_SELFTEST=y diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 1fd9d1260f9e..ee09f7bb6ea9 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -621,7 +621,6 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=m CONFIG_NVRAM=y CONFIG_DTLK=m -CONFIG_R3964=m CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=m CONFIG_IPWIRELESS=m diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 50168dde4ea5..b183629f1bcf 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -289,7 +289,9 @@ CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_HARDLOCKUP_DETECTOR=y CONFIG_FUNCTION_TRACER=y +CONFIG_FTRACE_SYSCALLS=y CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_CODE_PATCHING_SELFTEST=y CONFIG_FTR_FIXUP_SELFTEST=y diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h index 02ee6f5ac9fe..222823861a67 100644 --- a/arch/powerpc/include/asm/asm-prototypes.h +++ b/arch/powerpc/include/asm/asm-prototypes.h @@ -71,8 +71,13 @@ void __init machine_init(u64 dt_ptr); #endif long system_call_exception(long r3, long r4, long r5, long r6, long r7, long r8, unsigned long r0, struct pt_regs *regs); notrace unsigned long syscall_exit_prepare(unsigned long r3, struct pt_regs *regs, long scv); -notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned long msr); -notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsigned long msr); +notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs); +notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs); +#ifdef CONFIG_PPC64 +unsigned long syscall_exit_restart(unsigned long r3, struct pt_regs *regs); +unsigned long interrupt_exit_user_restart(struct pt_regs *regs); +unsigned long interrupt_exit_kernel_restart(struct pt_regs *regs); +#endif long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low, u32 len_high, u32 len_low); diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index 7ae29cfb06c0..f0e687236484 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -46,6 +46,8 @@ # define SMPWMB eieio #endif +/* clang defines this macro for a builtin, which will not work with runtime patching */ +#undef __lwsync #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") #define dma_rmb() __lwsync() #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") diff --git a/arch/powerpc/include/asm/book3s/32/hash.h b/arch/powerpc/include/asm/book3s/32/hash.h deleted file mode 100644 index 2a0a467d2985..000000000000 --- a/arch/powerpc/include/asm/book3s/32/hash.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_POWERPC_BOOK3S_32_HASH_H -#define _ASM_POWERPC_BOOK3S_32_HASH_H -#ifdef __KERNEL__ - -/* - * The "classic" 32-bit implementation of the PowerPC MMU uses a hash - * table containing PTEs, together with a set of 16 segment registers, - * to define the virtual to physical address mapping. - * - * We use the hash table as an extended TLB, i.e. a cache of currently - * active mappings. We maintain a two-level page table tree, much - * like that used by the i386, for the sake of the Linux memory - * management code. Low-level assembler code in hash_low_32.S - * (procedure hash_page) is responsible for extracting ptes from the - * tree and putting them into the hash table when necessary, and - * updating the accessed and modified bits in the page table tree. - */ - -#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ -#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ -#define _PAGE_USER 0x004 /* usermode access allowed */ -#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ -#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ -#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ -#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ -#define _PAGE_DIRTY 0x080 /* C: page changed */ -#define _PAGE_ACCESSED 0x100 /* R: page referenced */ -#define _PAGE_EXEC 0x200 /* software: exec allowed */ -#define _PAGE_RW 0x400 /* software: user write access allowed */ -#define _PAGE_SPECIAL 0x800 /* software: Special page */ - -#ifdef CONFIG_PTE_64BIT -/* We never clear the high word of the pte */ -#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE) -#else -#define _PTE_NONE_MASK _PAGE_HASHPTE -#endif - -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) - -#endif /* __KERNEL__ */ -#endif /* _ASM_POWERPC_BOOK3S_32_HASH_H */ diff --git a/arch/powerpc/include/asm/book3s/32/kup.h b/arch/powerpc/include/asm/book3s/32/kup.h index 1670dfe9d4f1..64201125a287 100644 --- a/arch/powerpc/include/asm/book3s/32/kup.h +++ b/arch/powerpc/include/asm/book3s/32/kup.h @@ -7,35 +7,104 @@ #ifndef __ASSEMBLY__ +#include + +extern struct static_key_false disable_kuap_key; +extern struct static_key_false disable_kuep_key; + +static __always_inline bool kuap_is_disabled(void) +{ + return !IS_ENABLED(CONFIG_PPC_KUAP) || static_branch_unlikely(&disable_kuap_key); +} + +static __always_inline bool kuep_is_disabled(void) +{ + return !IS_ENABLED(CONFIG_PPC_KUEP) || static_branch_unlikely(&disable_kuep_key); +} + +static inline void kuep_lock(void) +{ + if (kuep_is_disabled()) + return; + + update_user_segments(mfsr(0) | SR_NX); +} + +static inline void kuep_unlock(void) +{ + if (kuep_is_disabled()) + return; + + update_user_segments(mfsr(0) & ~SR_NX); +} + #ifdef CONFIG_PPC_KUAP #include -static inline void kuap_update_sr(u32 sr, u32 addr, u32 end) +#define KUAP_NONE (~0UL) +#define KUAP_ALL (~1UL) + +static inline void kuap_lock_one(unsigned long addr) { - addr &= 0xf0000000; /* align addr to start of segment */ - barrier(); /* make sure thread.kuap is updated before playing with SRs */ - while (addr < end) { - mtsr(sr, addr); - sr += 0x111; /* next VSID */ - sr &= 0xf0ffffff; /* clear VSID overflow */ - addr += 0x10000000; /* address of next segment */ - } + mtsr(mfsr(addr) | SR_KS, addr); isync(); /* Context sync required after mtsr() */ } +static inline void kuap_unlock_one(unsigned long addr) +{ + mtsr(mfsr(addr) & ~SR_KS, addr); + isync(); /* Context sync required after mtsr() */ +} + +static inline void kuap_lock_all(void) +{ + update_user_segments(mfsr(0) | SR_KS); + isync(); /* Context sync required after mtsr() */ +} + +static inline void kuap_unlock_all(void) +{ + update_user_segments(mfsr(0) & ~SR_KS); + isync(); /* Context sync required after mtsr() */ +} + +void kuap_lock_all_ool(void); +void kuap_unlock_all_ool(void); + +static inline void kuap_lock(unsigned long addr, bool ool) +{ + if (likely(addr != KUAP_ALL)) + kuap_lock_one(addr); + else if (!ool) + kuap_lock_all(); + else + kuap_lock_all_ool(); +} + +static inline void kuap_unlock(unsigned long addr, bool ool) +{ + if (likely(addr != KUAP_ALL)) + kuap_unlock_one(addr); + else if (!ool) + kuap_unlock_all(); + else + kuap_unlock_all_ool(); +} + static inline void kuap_save_and_lock(struct pt_regs *regs) { unsigned long kuap = current->thread.kuap; - u32 addr = kuap & 0xf0000000; - u32 end = kuap << 28; - regs->kuap = kuap; - if (unlikely(!kuap)) + if (kuap_is_disabled()) return; - current->thread.kuap = 0; - kuap_update_sr(mfsr(addr) | SR_KS, addr, end); /* Set Ks */ + regs->kuap = kuap; + if (unlikely(kuap == KUAP_NONE)) + return; + + current->thread.kuap = KUAP_NONE; + kuap_lock(kuap, false); } static inline void kuap_user_restore(struct pt_regs *regs) @@ -44,22 +113,22 @@ static inline void kuap_user_restore(struct pt_regs *regs) static inline void kuap_kernel_restore(struct pt_regs *regs, unsigned long kuap) { - u32 addr = regs->kuap & 0xf0000000; - u32 end = regs->kuap << 28; + if (kuap_is_disabled()) + return; current->thread.kuap = regs->kuap; - if (unlikely(regs->kuap == kuap)) - return; - - kuap_update_sr(mfsr(addr) & ~SR_KS, addr, end); /* Clear Ks */ + kuap_unlock(regs->kuap, false); } static inline unsigned long kuap_get_and_assert_locked(void) { unsigned long kuap = current->thread.kuap; - WARN_ON_ONCE(IS_ENABLED(CONFIG_PPC_KUAP_DEBUG) && kuap != 0); + if (kuap_is_disabled()) + return KUAP_NONE; + + WARN_ON_ONCE(IS_ENABLED(CONFIG_PPC_KUAP_DEBUG) && kuap != KUAP_NONE); return kuap; } @@ -72,84 +141,78 @@ static inline void kuap_assert_locked(void) static __always_inline void allow_user_access(void __user *to, const void __user *from, u32 size, unsigned long dir) { - u32 addr, end; + if (kuap_is_disabled()) + return; BUILD_BUG_ON(!__builtin_constant_p(dir)); - BUILD_BUG_ON(dir & ~KUAP_READ_WRITE); if (!(dir & KUAP_WRITE)) return; - addr = (__force u32)to; - - if (unlikely(addr >= TASK_SIZE || !size)) - return; - - end = min(addr + size, TASK_SIZE); - - current->thread.kuap = (addr & 0xf0000000) | ((((end - 1) >> 28) + 1) & 0xf); - kuap_update_sr(mfsr(addr) & ~SR_KS, addr, end); /* Clear Ks */ + current->thread.kuap = (__force u32)to; + kuap_unlock_one((__force u32)to); } -static __always_inline void prevent_user_access(void __user *to, const void __user *from, - u32 size, unsigned long dir) +static __always_inline void prevent_user_access(unsigned long dir) { - u32 addr, end; + u32 kuap = current->thread.kuap; + + if (kuap_is_disabled()) + return; BUILD_BUG_ON(!__builtin_constant_p(dir)); - if (dir & KUAP_CURRENT_WRITE) { - u32 kuap = current->thread.kuap; - - if (unlikely(!kuap)) - return; - - addr = kuap & 0xf0000000; - end = kuap << 28; - } else if (dir & KUAP_WRITE) { - addr = (__force u32)to; - end = min(addr + size, TASK_SIZE); - - if (unlikely(addr >= TASK_SIZE || !size)) - return; - } else { + if (!(dir & KUAP_WRITE)) return; - } - current->thread.kuap = 0; - kuap_update_sr(mfsr(addr) | SR_KS, addr, end); /* set Ks */ + current->thread.kuap = KUAP_NONE; + kuap_lock(kuap, true); } static inline unsigned long prevent_user_access_return(void) { unsigned long flags = current->thread.kuap; - unsigned long addr = flags & 0xf0000000; - unsigned long end = flags << 28; - void __user *to = (__force void __user *)addr; - if (flags) - prevent_user_access(to, to, end - addr, KUAP_READ_WRITE); + if (kuap_is_disabled()) + return KUAP_NONE; + + if (flags != KUAP_NONE) { + current->thread.kuap = KUAP_NONE; + kuap_lock(flags, true); + } return flags; } static inline void restore_user_access(unsigned long flags) { - unsigned long addr = flags & 0xf0000000; - unsigned long end = flags << 28; - void __user *to = (__force void __user *)addr; + if (kuap_is_disabled()) + return; - if (flags) - allow_user_access(to, to, end - addr, KUAP_READ_WRITE); + if (flags != KUAP_NONE) { + current->thread.kuap = flags; + kuap_unlock(flags, true); + } } static inline bool bad_kuap_fault(struct pt_regs *regs, unsigned long address, bool is_write) { - unsigned long begin = regs->kuap & 0xf0000000; - unsigned long end = regs->kuap << 28; + unsigned long kuap = regs->kuap; - return is_write && (address < begin || address >= end); + if (kuap_is_disabled()) + return false; + + if (!is_write || kuap == KUAP_ALL) + return false; + if (kuap == KUAP_NONE) + return true; + + /* If faulting address doesn't match unlocked segment, unlock all */ + if ((kuap ^ address) & 0xf0000000) + regs->kuap = KUAP_ALL; + + return false; } #endif /* CONFIG_PPC_KUAP */ diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h b/arch/powerpc/include/asm/book3s/32/mmu-hash.h index b85f8e114a9c..f5be185cbdf8 100644 --- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h +++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h @@ -66,6 +66,16 @@ struct ppc_bat { #ifndef __ASSEMBLY__ +/* + * This macro defines the mapping from contexts to VSIDs (virtual + * segment IDs). We use a skew on both the context and the high 4 bits + * of the 32-bit virtual address (the "effective segment ID") in order + * to spread out the entries in the MMU hash table. Note, if this + * function is changed then hash functions will have to be + * changed to correspond. + */ +#define CTX_TO_VSID(c, id) ((((c) * (897 * 16)) + (id * 0x111)) & 0xffffff) + /* * Hardware Page Table Entry * Note that the xpn and x bitfields are used only by processors that @@ -102,6 +112,37 @@ extern s32 patch__hash_page_B, patch__hash_page_C; extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2; extern s32 patch__flush_hash_B; +#include +#include + +static __always_inline void update_user_segment(u32 n, u32 val) +{ + if (n << 28 < TASK_SIZE) + mtsr(val + n * 0x111, n << 28); +} + +static __always_inline void update_user_segments(u32 val) +{ + val &= 0xf0ffffff; + + update_user_segment(0, val); + update_user_segment(1, val); + update_user_segment(2, val); + update_user_segment(3, val); + update_user_segment(4, val); + update_user_segment(5, val); + update_user_segment(6, val); + update_user_segment(7, val); + update_user_segment(8, val); + update_user_segment(9, val); + update_user_segment(10, val); + update_user_segment(11, val); + update_user_segment(12, val); + update_user_segment(13, val); + update_user_segment(14, val); + update_user_segment(15, val); +} + #endif /* !__ASSEMBLY__ */ /* We happily ignore the smaller BATs on 601, we don't actually use diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h index 83c65845a1a9..609c80f67194 100644 --- a/arch/powerpc/include/asm/book3s/32/pgtable.h +++ b/arch/powerpc/include/asm/book3s/32/pgtable.h @@ -4,7 +4,43 @@ #include -#include +/* + * The "classic" 32-bit implementation of the PowerPC MMU uses a hash + * table containing PTEs, together with a set of 16 segment registers, + * to define the virtual to physical address mapping. + * + * We use the hash table as an extended TLB, i.e. a cache of currently + * active mappings. We maintain a two-level page table tree, much + * like that used by the i386, for the sake of the Linux memory + * management code. Low-level assembler code in hash_low_32.S + * (procedure hash_page) is responsible for extracting ptes from the + * tree and putting them into the hash table when necessary, and + * updating the accessed and modified bits in the page table tree. + */ + +#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ +#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ +#define _PAGE_USER 0x004 /* usermode access allowed */ +#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ +#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ +#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ +#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ +#define _PAGE_DIRTY 0x080 /* C: page changed */ +#define _PAGE_ACCESSED 0x100 /* R: page referenced */ +#define _PAGE_EXEC 0x200 /* software: exec allowed */ +#define _PAGE_RW 0x400 /* software: user write access allowed */ +#define _PAGE_SPECIAL 0x800 /* software: Special page */ + +#ifdef CONFIG_PTE_64BIT +/* We never clear the high word of the pte */ +#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE) +#else +#define _PTE_NONE_MASK _PAGE_HASHPTE +#endif + +#define _PMD_PRESENT 0 +#define _PMD_PRESENT_MASK (PAGE_MASK) +#define _PMD_BAD (~PAGE_MASK) /* And here we include common definitions */ diff --git a/arch/powerpc/include/asm/book3s/64/kup.h b/arch/powerpc/include/asm/book3s/64/kup.h index 9700da3a4093..a1cc73a88710 100644 --- a/arch/powerpc/include/asm/book3s/64/kup.h +++ b/arch/powerpc/include/asm/book3s/64/kup.h @@ -398,8 +398,7 @@ static __always_inline void allow_user_access(void __user *to, const void __user #endif /* !CONFIG_PPC_KUAP */ -static inline void prevent_user_access(void __user *to, const void __user *from, - unsigned long size, unsigned long dir) +static inline void prevent_user_access(unsigned long dir) { set_kuap(AMR_KUAP_BLOCKED); if (static_branch_unlikely(&uaccess_flush_key)) diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index a666d561b44d..4d9941b2fe51 100644 --- a/arch/powerpc/include/asm/book3s/64/pgtable.h +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h @@ -232,6 +232,9 @@ extern unsigned long __pmd_frag_size_shift; #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) +#define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ + H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) + /* PMD_SHIFT determines what a second-level page table entry can map */ #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) #define PMD_SIZE (1UL << PMD_SHIFT) diff --git a/arch/powerpc/include/asm/book3s/pgtable.h b/arch/powerpc/include/asm/book3s/pgtable.h index 0e1263455d73..ad130e15a126 100644 --- a/arch/powerpc/include/asm/book3s/pgtable.h +++ b/arch/powerpc/include/asm/book3s/pgtable.h @@ -8,7 +8,6 @@ #include #endif -#define FIRST_USER_ADDRESS 0UL #ifndef __ASSEMBLY__ /* Insert a PTE, top-level function is out of line. It uses an inline * low level function in the respective pgtable-* files diff --git a/arch/powerpc/include/asm/checksum.h b/arch/powerpc/include/asm/checksum.h index d5da7ddbf0fc..350de8f90250 100644 --- a/arch/powerpc/include/asm/checksum.h +++ b/arch/powerpc/include/asm/checksum.h @@ -91,7 +91,7 @@ static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len, } #define HAVE_ARCH_CSUM_ADD -static inline __wsum csum_add(__wsum csum, __wsum addend) +static __always_inline __wsum csum_add(__wsum csum, __wsum addend) { #ifdef __powerpc64__ u64 res = (__force u64)csum; diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h index f1d029bf906e..a95f63788c6b 100644 --- a/arch/powerpc/include/asm/code-patching.h +++ b/arch/powerpc/include/asm/code-patching.h @@ -23,13 +23,13 @@ #define BRANCH_ABSOLUTE 0x2 bool is_offset_in_branch_range(long offset); -int create_branch(struct ppc_inst *instr, const struct ppc_inst *addr, +int create_branch(struct ppc_inst *instr, const u32 *addr, unsigned long target, int flags); -int create_cond_branch(struct ppc_inst *instr, const struct ppc_inst *addr, +int create_cond_branch(struct ppc_inst *instr, const u32 *addr, unsigned long target, int flags); -int patch_branch(struct ppc_inst *addr, unsigned long target, int flags); -int patch_instruction(struct ppc_inst *addr, struct ppc_inst instr); -int raw_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr); +int patch_branch(u32 *addr, unsigned long target, int flags); +int patch_instruction(u32 *addr, struct ppc_inst instr); +int raw_patch_instruction(u32 *addr, struct ppc_inst instr); static inline unsigned long patch_site_addr(s32 *site) { @@ -38,18 +38,18 @@ static inline unsigned long patch_site_addr(s32 *site) static inline int patch_instruction_site(s32 *site, struct ppc_inst instr) { - return patch_instruction((struct ppc_inst *)patch_site_addr(site), instr); + return patch_instruction((u32 *)patch_site_addr(site), instr); } static inline int patch_branch_site(s32 *site, unsigned long target, int flags) { - return patch_branch((struct ppc_inst *)patch_site_addr(site), target, flags); + return patch_branch((u32 *)patch_site_addr(site), target, flags); } static inline int modify_instruction(unsigned int *addr, unsigned int clr, unsigned int set) { - return patch_instruction((struct ppc_inst *)addr, ppc_inst((*addr & ~clr) | set)); + return patch_instruction(addr, ppc_inst((*addr & ~clr) | set)); } static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) @@ -59,10 +59,8 @@ static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int instr_is_relative_branch(struct ppc_inst instr); int instr_is_relative_link_branch(struct ppc_inst instr); -int instr_is_branch_to_addr(const struct ppc_inst *instr, unsigned long addr); -unsigned long branch_target(const struct ppc_inst *instr); -int translate_branch(struct ppc_inst *instr, const struct ppc_inst *dest, - const struct ppc_inst *src); +unsigned long branch_target(const u32 *instr); +int translate_branch(struct ppc_inst *instr, const u32 *dest, const u32 *src); extern bool is_conditional_branch(struct ppc_inst instr); #ifdef CONFIG_PPC_BOOK3E_64 void __patch_exception(int exc, unsigned long addr); @@ -73,9 +71,9 @@ void __patch_exception(int exc, unsigned long addr); #endif #define OP_RT_RA_MASK 0xffff0000UL -#define LIS_R2 (PPC_INST_ADDIS | __PPC_RT(R2)) -#define ADDIS_R2_R12 (PPC_INST_ADDIS | __PPC_RT(R2) | __PPC_RA(R12)) -#define ADDI_R2_R2 (PPC_INST_ADDI | __PPC_RT(R2) | __PPC_RA(R2)) +#define LIS_R2 (PPC_RAW_LIS(_R2, 0)) +#define ADDIS_R2_R12 (PPC_RAW_ADDIS(_R2, _R12, 0)) +#define ADDI_R2_R2 (PPC_RAW_ADDI(_R2, _R2, 0)) static inline unsigned long ppc_function_entry(void *func) @@ -180,12 +178,10 @@ static inline unsigned long ppc_kallsyms_lookup_name(const char *name) #define R2_STACK_OFFSET 40 #endif -#define PPC_INST_LD_TOC (PPC_INST_LD | ___PPC_RT(__REG_R2) | \ - ___PPC_RA(__REG_R1) | R2_STACK_OFFSET) +#define PPC_INST_LD_TOC PPC_RAW_LD(_R2, _R1, R2_STACK_OFFSET) /* usually preceded by a mflr r0 */ -#define PPC_INST_STD_LR (PPC_INST_STD | ___PPC_RS(__REG_R0) | \ - ___PPC_RA(__REG_R1) | PPC_LR_STKOFF) +#define PPC_INST_STD_LR PPC_RAW_STD(_R0, _R1, PPC_LR_STKOFF) #endif /* CONFIG_PPC64 */ #endif /* _ASM_POWERPC_CODE_PATCHING_H */ diff --git a/arch/powerpc/include/asm/head-64.h b/arch/powerpc/include/asm/head-64.h index 4cb9efa2eb21..242204e12993 100644 --- a/arch/powerpc/include/asm/head-64.h +++ b/arch/powerpc/include/asm/head-64.h @@ -16,7 +16,7 @@ .section ".head.data.\name\()","a",@progbits .endm .macro use_ftsec name - .section ".head.text.\name\()" + .section ".head.text.\name\()","ax",@progbits .endm /* diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index 7e4b2cef40c2..9bcf345cb208 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -294,6 +294,13 @@ #define H_RESIZE_HPT_COMMIT 0x370 #define H_REGISTER_PROC_TBL 0x37C #define H_SIGNAL_SYS_RESET 0x380 +#define H_ALLOCATE_VAS_WINDOW 0x388 +#define H_MODIFY_VAS_WINDOW 0x38C +#define H_DEALLOCATE_VAS_WINDOW 0x390 +#define H_QUERY_VAS_WINDOW 0x394 +#define H_QUERY_VAS_CAPABILITIES 0x398 +#define H_QUERY_NX_CAPABILITIES 0x39C +#define H_GET_NX_FAULT 0x3A0 #define H_INT_GET_SOURCE_INFO 0x3A8 #define H_INT_SET_SOURCE_CONFIG 0x3AC #define H_INT_GET_SOURCE_CONFIG 0x3B0 @@ -393,6 +400,9 @@ #define H_CPU_BEHAV_FAVOUR_SECURITY_H (1ull << 60) // IBM bit 3 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58) // IBM bit 5 #define H_CPU_BEHAV_FLUSH_LINK_STACK (1ull << 57) // IBM bit 6 +#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY (1ull << 56) // IBM bit 7 +#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS (1ull << 55) // IBM bit 8 +#define H_CPU_BEHAV_NO_STF_BARRIER (1ull << 54) // IBM bit 9 /* Flag values used in H_REGISTER_PROC_TBL hcall */ #define PROC_TABLE_OP_MASK 0x18 diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index 56a98936a6a9..21cc571ea9c2 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -18,8 +18,17 @@ * PACA flags in paca->irq_happened. * * This bits are set when interrupts occur while soft-disabled - * and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS - * is set whenever we manually hard disable. + * and allow a proper replay. + * + * The PACA_IRQ_HARD_DIS is set whenever we hard disable. It is almost + * always in synch with the MSR[EE] state, except: + * - A window in interrupt entry, where hardware disables MSR[EE] and that + * must be "reconciled" with the soft mask state. + * - NMI interrupts that hit in awkward places, until they fix the state. + * - When local irqs are being enabled and state is being fixed up. + * - When returning from an interrupt there are some windows where this + * can become out of synch, but gets fixed before the RFI or before + * executing the next user instruction (see arch/powerpc/kernel/interrupt.c). */ #define PACA_IRQ_HARD_DIS 0x01 #define PACA_IRQ_DBELL 0x02 @@ -389,7 +398,15 @@ static inline bool arch_irq_disabled_regs(struct pt_regs *regs) return !(regs->msr & MSR_EE); } -static inline void may_hard_irq_enable(void) { } +static inline bool may_hard_irq_enable(void) +{ + return false; +} + +static inline void do_hard_irq_enable(void) +{ + BUILD_BUG(); +} static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned long val) { diff --git a/arch/powerpc/include/asm/inst.h b/arch/powerpc/include/asm/inst.h index 268d3bd073c8..b11c0e2f9639 100644 --- a/arch/powerpc/include/asm/inst.h +++ b/arch/powerpc/include/asm/inst.h @@ -8,17 +8,17 @@ #define ___get_user_instr(gu_op, dest, ptr) \ ({ \ - long __gui_ret = 0; \ - unsigned long __gui_ptr = (unsigned long)ptr; \ + long __gui_ret; \ + u32 __user *__gui_ptr = (u32 __user *)ptr; \ struct ppc_inst __gui_inst; \ unsigned int __prefix, __suffix; \ - __gui_ret = gu_op(__prefix, (unsigned int __user *)__gui_ptr); \ + \ + __chk_user_ptr(ptr); \ + __gui_ret = gu_op(__prefix, __gui_ptr); \ if (__gui_ret == 0) { \ if ((__prefix >> 26) == OP_PREFIX) { \ - __gui_ret = gu_op(__suffix, \ - (unsigned int __user *)__gui_ptr + 1); \ - __gui_inst = ppc_inst_prefix(__prefix, \ - __suffix); \ + __gui_ret = gu_op(__suffix, __gui_ptr + 1); \ + __gui_inst = ppc_inst_prefix(__prefix, __suffix); \ } else { \ __gui_inst = ppc_inst(__prefix); \ } \ @@ -29,14 +29,15 @@ }) #else /* !CONFIG_PPC64 */ #define ___get_user_instr(gu_op, dest, ptr) \ - gu_op((dest).val, (u32 __user *)(ptr)) +({ \ + __chk_user_ptr(ptr); \ + gu_op((dest).val, (u32 __user *)(ptr)); \ +}) #endif /* CONFIG_PPC64 */ -#define get_user_instr(x, ptr) \ - ___get_user_instr(get_user, x, ptr) +#define get_user_instr(x, ptr) ___get_user_instr(get_user, x, ptr) -#define __get_user_instr(x, ptr) \ - ___get_user_instr(__get_user, x, ptr) +#define __get_user_instr(x, ptr) ___get_user_instr(__get_user, x, ptr) /* * Instruction data type for POWER @@ -59,9 +60,9 @@ static inline int ppc_inst_primary_opcode(struct ppc_inst x) return ppc_inst_val(x) >> 26; } -#ifdef CONFIG_PPC64 -#define ppc_inst(x) ((struct ppc_inst){ .val = (x), .suffix = 0xff }) +#define ppc_inst(x) ((struct ppc_inst){ .val = (x) }) +#ifdef CONFIG_PPC64 #define ppc_inst_prefix(x, y) ((struct ppc_inst){ .val = (x), .suffix = (y) }) static inline u32 ppc_inst_suffix(struct ppc_inst x) @@ -69,68 +70,43 @@ static inline u32 ppc_inst_suffix(struct ppc_inst x) return x.suffix; } -static inline bool ppc_inst_prefixed(struct ppc_inst x) -{ - return (ppc_inst_primary_opcode(x) == 1) && ppc_inst_suffix(x) != 0xff; -} - -static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x) -{ - return ppc_inst_prefix(swab32(ppc_inst_val(x)), - swab32(ppc_inst_suffix(x))); -} - -static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr) -{ - u32 val, suffix; - - val = *(u32 *)ptr; - if ((val >> 26) == OP_PREFIX) { - suffix = *((u32 *)ptr + 1); - return ppc_inst_prefix(val, suffix); - } else { - return ppc_inst(val); - } -} - -static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y) -{ - return *(u64 *)&x == *(u64 *)&y; -} - #else - -#define ppc_inst(x) ((struct ppc_inst){ .val = x }) - #define ppc_inst_prefix(x, y) ppc_inst(x) -static inline bool ppc_inst_prefixed(struct ppc_inst x) -{ - return false; -} - static inline u32 ppc_inst_suffix(struct ppc_inst x) { return 0; } -static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x) +#endif /* CONFIG_PPC64 */ + +static inline struct ppc_inst ppc_inst_read(const u32 *ptr) { - return ppc_inst(swab32(ppc_inst_val(x))); + if (IS_ENABLED(CONFIG_PPC64) && (*ptr >> 26) == OP_PREFIX) + return ppc_inst_prefix(*ptr, *(ptr + 1)); + else + return ppc_inst(*ptr); } -static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr) +static inline bool ppc_inst_prefixed(struct ppc_inst x) { - return *ptr; + return IS_ENABLED(CONFIG_PPC64) && ppc_inst_primary_opcode(x) == OP_PREFIX; +} + +static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x) +{ + return ppc_inst_prefix(swab32(ppc_inst_val(x)), swab32(ppc_inst_suffix(x))); } static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y) { - return ppc_inst_val(x) == ppc_inst_val(y); + if (ppc_inst_val(x) != ppc_inst_val(y)) + return false; + if (!ppc_inst_prefixed(x)) + return true; + return ppc_inst_suffix(x) == ppc_inst_suffix(y); } -#endif /* CONFIG_PPC64 */ - static inline int ppc_inst_len(struct ppc_inst x) { return ppc_inst_prefixed(x) ? 8 : 4; @@ -140,13 +116,13 @@ static inline int ppc_inst_len(struct ppc_inst x) * Return the address of the next instruction, if the instruction @value was * located at @location. */ -static inline struct ppc_inst *ppc_inst_next(void *location, struct ppc_inst *value) +static inline u32 *ppc_inst_next(u32 *location, u32 *value) { struct ppc_inst tmp; tmp = ppc_inst_read(value); - return location + ppc_inst_len(tmp); + return (void *)location + ppc_inst_len(tmp); } static inline unsigned long ppc_inst_as_ulong(struct ppc_inst x) @@ -178,6 +154,6 @@ static inline char *__ppc_inst_as_str(char str[PPC_INST_STR_LEN], struct ppc_ins __str; \ }) -int copy_inst_from_kernel_nofault(struct ppc_inst *inst, struct ppc_inst *src); +int copy_inst_from_kernel_nofault(struct ppc_inst *inst, u32 *src); #endif /* _ASM_POWERPC_INST_H */ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h index 59f704408d65..d4bdf7d274ac 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -73,13 +73,47 @@ #include #include +#ifdef CONFIG_PPC_BOOK3S_64 +extern char __end_soft_masked[]; +bool search_kernel_soft_mask_table(unsigned long addr); +unsigned long search_kernel_restart_table(unsigned long addr); + +DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); + +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + if (regs->msr & MSR_PR) + return false; + + if (regs->nip >= (unsigned long)__end_soft_masked) + return false; + + return search_kernel_soft_mask_table(regs->nip); +} + +static inline void srr_regs_clobbered(void) +{ + local_paca->srr_valid = 0; + local_paca->hsrr_valid = 0; +} +#else +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + return false; +} + +static inline void srr_regs_clobbered(void) +{ +} +#endif + static inline void nap_adjust_return(struct pt_regs *regs) { #ifdef CONFIG_PPC_970_NAP if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { /* Can avoid a test-and-clear because NMIs do not call this */ clear_thread_local_flags(_TLF_NAPPING); - regs->nip = (unsigned long)power4_idle_nap_return; + regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return); } #endif } @@ -129,9 +163,18 @@ static inline void interrupt_enter_prepare(struct pt_regs *regs, struct interrup * CT_WARN_ON comes here via program_check_exception, * so avoid recursion. */ - if (TRAP(regs) != INTERRUPT_PROGRAM) + if (TRAP(regs) != INTERRUPT_PROGRAM) { CT_WARN_ON(ct_state() != CONTEXT_KERNEL); + BUG_ON(is_implicit_soft_masked(regs)); + } +#ifdef CONFIG_PPC_BOOK3S + /* Move this under a debugging check */ + if (arch_irq_disabled_regs(regs)) + BUG_ON(search_kernel_restart_table(regs->nip)); +#endif } + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + BUG_ON(!arch_irq_disabled_regs(regs) && !(regs->msr & MSR_EE)); #endif booke_restore_dbcr0(); @@ -186,6 +229,7 @@ struct interrupt_nmi_state { u8 irq_soft_mask; u8 irq_happened; u8 ftrace_enabled; + u64 softe; #endif }; @@ -211,6 +255,7 @@ static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struct inte #ifdef CONFIG_PPC64 state->irq_soft_mask = local_paca->irq_soft_mask; state->irq_happened = local_paca->irq_happened; + state->softe = regs->softe; /* * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does @@ -220,12 +265,13 @@ static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struct inte local_paca->irq_soft_mask = IRQS_ALL_DISABLED; local_paca->irq_happened |= PACA_IRQ_HARD_DIS; - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !(regs->msr & MSR_PR) && - regs->nip < (unsigned long)__end_interrupts) { - // Kernel code running below __end_interrupts is - // implicitly soft-masked. + if (is_implicit_soft_masked(regs)) { + // Adjust regs->softe soft implicit soft-mask, so + // arch_irq_disabled_regs(regs) behaves as expected. regs->softe = IRQS_ALL_DISABLED; } + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + BUG_ON(!arch_irq_disabled_regs(regs) && !(regs->msr & MSR_EE)); /* Don't do any per-CPU operations until interrupt state is fixed */ @@ -258,11 +304,20 @@ static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct inter */ #ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S + if (arch_irq_disabled_regs(regs)) { + unsigned long rst = search_kernel_restart_table(regs->nip); + if (rst) + regs_set_return_ip(regs, rst); + } +#endif + if (nmi_disables_ftrace(regs)) this_cpu_set_ftrace_enabled(state->ftrace_enabled); /* Check we didn't change the pending interrupt mask. */ WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) != local_paca->irq_happened); + regs->softe = state->softe; local_paca->irq_happened = state->irq_happened; local_paca->irq_soft_mask = state->irq_soft_mask; #endif diff --git a/arch/powerpc/include/asm/kup.h b/arch/powerpc/include/asm/kup.h index ec96232529ac..1df763002726 100644 --- a/arch/powerpc/include/asm/kup.h +++ b/arch/powerpc/include/asm/kup.h @@ -5,14 +5,6 @@ #define KUAP_READ 1 #define KUAP_WRITE 2 #define KUAP_READ_WRITE (KUAP_READ | KUAP_WRITE) -/* - * For prevent_user_access() only. - * Use the current saved situation instead of the to/from/size params. - * Used on book3s/32 - */ -#define KUAP_CURRENT_READ 4 -#define KUAP_CURRENT_WRITE 8 -#define KUAP_CURRENT (KUAP_CURRENT_READ | KUAP_CURRENT_WRITE) #ifdef CONFIG_PPC_BOOK3S_64 #include @@ -46,10 +38,7 @@ void setup_kuep(bool disabled); static inline void setup_kuep(bool disabled) { } #endif /* CONFIG_PPC_KUEP */ -#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32) -void kuep_lock(void); -void kuep_unlock(void); -#else +#ifndef CONFIG_PPC_BOOK3S_32 static inline void kuep_lock(void) { } static inline void kuep_unlock(void) { } #endif @@ -83,8 +72,7 @@ static inline unsigned long kuap_get_and_assert_locked(void) #ifndef CONFIG_PPC_BOOK3S_64 static inline void allow_user_access(void __user *to, const void __user *from, unsigned long size, unsigned long dir) { } -static inline void prevent_user_access(void __user *to, const void __user *from, - unsigned long size, unsigned long dir) { } +static inline void prevent_user_access(unsigned long dir) { } static inline unsigned long prevent_user_access_return(void) { return 0UL; } static inline void restore_user_access(unsigned long flags) { } #endif /* CONFIG_PPC_BOOK3S_64 */ @@ -96,53 +84,53 @@ static __always_inline void setup_kup(void) setup_kuap(disable_kuap); } -static inline void allow_read_from_user(const void __user *from, unsigned long size) +static __always_inline void allow_read_from_user(const void __user *from, unsigned long size) { barrier_nospec(); allow_user_access(NULL, from, size, KUAP_READ); } -static inline void allow_write_to_user(void __user *to, unsigned long size) +static __always_inline void allow_write_to_user(void __user *to, unsigned long size) { allow_user_access(to, NULL, size, KUAP_WRITE); } -static inline void allow_read_write_user(void __user *to, const void __user *from, - unsigned long size) +static __always_inline void allow_read_write_user(void __user *to, const void __user *from, + unsigned long size) { barrier_nospec(); allow_user_access(to, from, size, KUAP_READ_WRITE); } -static inline void prevent_read_from_user(const void __user *from, unsigned long size) +static __always_inline void prevent_read_from_user(const void __user *from, unsigned long size) { - prevent_user_access(NULL, from, size, KUAP_READ); + prevent_user_access(KUAP_READ); } -static inline void prevent_write_to_user(void __user *to, unsigned long size) +static __always_inline void prevent_write_to_user(void __user *to, unsigned long size) { - prevent_user_access(to, NULL, size, KUAP_WRITE); + prevent_user_access(KUAP_WRITE); } -static inline void prevent_read_write_user(void __user *to, const void __user *from, - unsigned long size) +static __always_inline void prevent_read_write_user(void __user *to, const void __user *from, + unsigned long size) { - prevent_user_access(to, from, size, KUAP_READ_WRITE); + prevent_user_access(KUAP_READ_WRITE); } -static inline void prevent_current_access_user(void) +static __always_inline void prevent_current_access_user(void) { - prevent_user_access(NULL, NULL, ~0UL, KUAP_CURRENT); + prevent_user_access(KUAP_READ_WRITE); } -static inline void prevent_current_read_from_user(void) +static __always_inline void prevent_current_read_from_user(void) { - prevent_user_access(NULL, NULL, ~0UL, KUAP_CURRENT_READ); + prevent_user_access(KUAP_READ); } -static inline void prevent_current_write_to_user(void) +static __always_inline void prevent_current_write_to_user(void) { - prevent_user_access(NULL, NULL, ~0UL, KUAP_CURRENT_WRITE); + prevent_user_access(KUAP_WRITE); } #endif /* !__ASSEMBLY__ */ diff --git a/arch/powerpc/include/asm/kvm_guest.h b/arch/powerpc/include/asm/kvm_guest.h index 2fca299f7e19..c63105d2c9e7 100644 --- a/arch/powerpc/include/asm/kvm_guest.h +++ b/arch/powerpc/include/asm/kvm_guest.h @@ -16,10 +16,10 @@ static inline bool is_kvm_guest(void) return static_branch_unlikely(&kvm_guest); } -bool check_kvm_guest(void); +int check_kvm_guest(void); #else static inline bool is_kvm_guest(void) { return false; } -static inline bool check_kvm_guest(void) { return false; } +static inline int check_kvm_guest(void) { return 0; } #endif #endif /* _ASM_POWERPC_KVM_GUEST_H_ */ diff --git a/arch/powerpc/include/asm/livepatch.h b/arch/powerpc/include/asm/livepatch.h index ae25e6e72997..4fe018cc207b 100644 --- a/arch/powerpc/include/asm/livepatch.h +++ b/arch/powerpc/include/asm/livepatch.h @@ -16,7 +16,7 @@ static inline void klp_arch_set_pc(struct ftrace_regs *fregs, unsigned long ip) { struct pt_regs *regs = ftrace_get_regs(fregs); - regs->nip = ip; + regs_set_return_ip(regs, ip); } #define klp_get_ftrace_location klp_get_ftrace_location diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 607168b1aef4..27016b98ecb2 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -220,7 +220,7 @@ enum { #elif defined(CONFIG_44x) #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x #endif -#if defined(CONFIG_E200) || defined(CONFIG_E500) +#ifdef CONFIG_E500 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E #endif @@ -324,7 +324,6 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) } #endif /* !CONFIG_DEBUG_VM */ -#ifdef CONFIG_PPC_RADIX_MMU static inline bool radix_enabled(void) { return mmu_has_feature(MMU_FTR_TYPE_RADIX); @@ -334,17 +333,6 @@ static inline bool early_radix_enabled(void) { return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); } -#else -static inline bool radix_enabled(void) -{ - return false; -} - -static inline bool early_radix_enabled(void) -{ - return false; -} -#endif #ifdef CONFIG_STRICT_KERNEL_RWX static inline bool strict_kernel_rwx_enabled(void) @@ -357,6 +345,11 @@ static inline bool strict_kernel_rwx_enabled(void) return false; } #endif + +static inline bool strict_module_rwx_enabled(void) +{ + return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled(); +} #endif /* !__ASSEMBLY__ */ /* The kernel use the constants below to index in the page sizes array. diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h index db186c539d37..9ba6b585337f 100644 --- a/arch/powerpc/include/asm/mmu_context.h +++ b/arch/powerpc/include/asm/mmu_context.h @@ -57,7 +57,6 @@ static inline bool mm_iommu_is_devmem(struct mm_struct *mm, unsigned long hpa, static inline void mm_iommu_init(struct mm_struct *mm) { } #endif extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm); -extern void set_context(unsigned long id, pgd_t *pgd); #ifdef CONFIG_PPC_BOOK3S_64 extern void radix__switch_mmu_context(struct mm_struct *prev, diff --git a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h index 39be9aea86db..64b6c608eca4 100644 --- a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h @@ -66,10 +66,9 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, } #ifdef CONFIG_PPC_4K_PAGES -static inline pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, - struct page *page, int writable) +static inline pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) { - size_t size = huge_page_size(hstate_vma(vma)); + size_t size = 1UL << shift; if (size == SZ_16K) return __pte(pte_val(entry) & ~_PAGE_HUGE); diff --git a/arch/powerpc/include/asm/nohash/32/kup-8xx.h b/arch/powerpc/include/asm/nohash/32/kup-8xx.h index 295ef5639609..882a0bc7887a 100644 --- a/arch/powerpc/include/asm/nohash/32/kup-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/kup-8xx.h @@ -9,10 +9,22 @@ #ifndef __ASSEMBLY__ +#include + #include +extern struct static_key_false disable_kuap_key; + +static __always_inline bool kuap_is_disabled(void) +{ + return static_branch_unlikely(&disable_kuap_key); +} + static inline void kuap_save_and_lock(struct pt_regs *regs) { + if (kuap_is_disabled()) + return; + regs->kuap = mfspr(SPRN_MD_AP); mtspr(SPRN_MD_AP, MD_APG_KUAP); } @@ -23,12 +35,20 @@ static inline void kuap_user_restore(struct pt_regs *regs) static inline void kuap_kernel_restore(struct pt_regs *regs, unsigned long kuap) { + if (kuap_is_disabled()) + return; + mtspr(SPRN_MD_AP, regs->kuap); } static inline unsigned long kuap_get_and_assert_locked(void) { - unsigned long kuap = mfspr(SPRN_MD_AP); + unsigned long kuap; + + if (kuap_is_disabled()) + return MD_APG_INIT; + + kuap = mfspr(SPRN_MD_AP); if (IS_ENABLED(CONFIG_PPC_KUAP_DEBUG)) WARN_ON_ONCE(kuap >> 16 != MD_APG_KUAP >> 16); @@ -38,25 +58,35 @@ static inline unsigned long kuap_get_and_assert_locked(void) static inline void kuap_assert_locked(void) { - if (IS_ENABLED(CONFIG_PPC_KUAP_DEBUG)) + if (IS_ENABLED(CONFIG_PPC_KUAP_DEBUG) && !kuap_is_disabled()) kuap_get_and_assert_locked(); } static inline void allow_user_access(void __user *to, const void __user *from, unsigned long size, unsigned long dir) { + if (kuap_is_disabled()) + return; + mtspr(SPRN_MD_AP, MD_APG_INIT); } -static inline void prevent_user_access(void __user *to, const void __user *from, - unsigned long size, unsigned long dir) +static inline void prevent_user_access(unsigned long dir) { + if (kuap_is_disabled()) + return; + mtspr(SPRN_MD_AP, MD_APG_KUAP); } static inline unsigned long prevent_user_access_return(void) { - unsigned long flags = mfspr(SPRN_MD_AP); + unsigned long flags; + + if (kuap_is_disabled()) + return MD_APG_INIT; + + flags = mfspr(SPRN_MD_AP); mtspr(SPRN_MD_AP, MD_APG_KUAP); @@ -65,12 +95,18 @@ static inline unsigned long prevent_user_access_return(void) static inline void restore_user_access(unsigned long flags) { + if (kuap_is_disabled()) + return; + mtspr(SPRN_MD_AP, flags); } static inline bool bad_kuap_fault(struct pt_regs *regs, unsigned long address, bool is_write) { + if (kuap_is_disabled()) + return false; + return !((regs->kuap ^ MD_APG_KUAP) & 0xff000000); } diff --git a/arch/powerpc/include/asm/nohash/32/mmu-44x.h b/arch/powerpc/include/asm/nohash/32/mmu-44x.h index 2d92a39d8f2e..43ceca128531 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu-44x.h +++ b/arch/powerpc/include/asm/nohash/32/mmu-44x.h @@ -113,6 +113,7 @@ typedef struct { /* patch sites */ extern s32 patch__tlb_44x_hwater_D, patch__tlb_44x_hwater_I; +extern s32 patch__tlb_44x_kuep, patch__tlb_47x_kuep; #endif /* !__ASSEMBLY__ */ diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h index 6e4faa0a9b35..997cec973406 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h @@ -178,6 +178,7 @@ #ifndef __ASSEMBLY__ #include +#include void mmu_pin_tlb(unsigned long top, bool readonly); @@ -225,6 +226,48 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) BUG(); } +static inline bool arch_vmap_try_size(unsigned long addr, unsigned long end, u64 pfn, + unsigned int max_page_shift, unsigned long size) +{ + if (end - addr < size) + return false; + + if ((1UL << max_page_shift) < size) + return false; + + if (!IS_ALIGNED(addr, size)) + return false; + + if (!IS_ALIGNED(PFN_PHYS(pfn), size)) + return false; + + return true; +} + +static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end, + u64 pfn, unsigned int max_page_shift) +{ + if (arch_vmap_try_size(addr, end, pfn, max_page_shift, SZ_512K)) + return SZ_512K; + if (PAGE_SIZE == SZ_16K) + return SZ_16K; + if (arch_vmap_try_size(addr, end, pfn, max_page_shift, SZ_16K)) + return SZ_16K; + return PAGE_SIZE; +} +#define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size + +static inline int arch_vmap_pte_supported_shift(unsigned long size) +{ + if (size >= SZ_512K) + return 19; + else if (size >= SZ_16K) + return 14; + else + return PAGE_SHIFT; +} +#define arch_vmap_pte_supported_shift arch_vmap_pte_supported_shift + /* patch sites */ extern s32 patch__itlbmiss_exit_1, patch__dtlbmiss_exit_1; extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h index 96522f7f0618..f06ae00f2a65 100644 --- a/arch/powerpc/include/asm/nohash/32/pgtable.h +++ b/arch/powerpc/include/asm/nohash/32/pgtable.h @@ -54,7 +54,6 @@ extern int icache_44x_need_flush; #define PGD_MASKED_BITS 0 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL #define pte_ERROR(e) \ pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h index 57cd3892bfe0..53fbfdfac93d 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable.h @@ -12,8 +12,6 @@ #include #include -#define FIRST_USER_ADDRESS 0UL - /* * Size of EA range mapped by our pagetables. */ diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index ec18ac818e3a..dc05a862e72a 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h @@ -149,11 +149,9 @@ struct paca_struct { #endif /* CONFIG_PPC_BOOK3E */ #ifdef CONFIG_PPC_BOOK3S - mm_context_id_t mm_ctx_id; #ifdef CONFIG_PPC_MM_SLICES unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE]; unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE]; - unsigned long mm_ctx_slb_addr_limit; #else u16 mm_ctx_user_psize; u16 mm_ctx_sllp; @@ -167,8 +165,15 @@ struct paca_struct { u64 kstack; /* Saved Kernel stack addr */ u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */ u64 saved_msr; /* MSR saved here by enter_rtas */ +#ifdef CONFIG_PPC64 + u64 exit_save_r1; /* Syscall/interrupt R1 save */ +#endif #ifdef CONFIG_PPC_BOOK3E u16 trap_save; /* Used when bad stack is encountered */ +#endif +#ifdef CONFIG_PPC_BOOK3S_64 + u8 hsrr_valid; /* HSRRs set for HRFID */ + u8 srr_valid; /* SRRs set for RFID */ #endif u8 irq_soft_mask; /* mask for irq soft masking */ u8 irq_happened; /* irq happened while soft-disabled */ diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h index 6dd78a2dc03a..3360cad78ace 100644 --- a/arch/powerpc/include/asm/pgalloc.h +++ b/arch/powerpc/include/asm/pgalloc.h @@ -70,9 +70,4 @@ extern struct kmem_cache *pgtable_cache[]; #include #endif -static inline pgtable_t pmd_pgtable(pmd_t pmd) -{ - return (pgtable_t)pmd_page_vaddr(pmd); -} - #endif /* _ASM_POWERPC_PGALLOC_H */ diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h index c6a676714f04..d564d0ecd4cd 100644 --- a/arch/powerpc/include/asm/pgtable.h +++ b/arch/powerpc/include/asm/pgtable.h @@ -41,6 +41,10 @@ struct mm_struct; #ifndef __ASSEMBLY__ +#ifndef MAX_PTRS_PER_PGD +#define MAX_PTRS_PER_PGD PTRS_PER_PGD +#endif + /* Keep these as a macros to avoid include dependency mess */ #define pte_page(x) pfn_to_page(pte_pfn(x)) #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) @@ -72,6 +76,7 @@ extern unsigned long empty_zero_page[]; extern pgd_t swapper_pg_dir[]; extern void paging_init(void); +void poking_init(void); extern unsigned long ioremap_bot; @@ -152,6 +157,12 @@ static inline bool p4d_is_leaf(p4d_t p4d) } #endif +#define pmd_pgtable pmd_pgtable +static inline pgtable_t pmd_pgtable(pmd_t pmd) +{ + return (pgtable_t)pmd_page_vaddr(pmd); +} + #ifdef CONFIG_PPC64 #define is_ioremap_addr is_ioremap_addr static inline bool is_ioremap_addr(const void *x) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ac41776661e9..bede76dd3db7 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -76,6 +76,40 @@ #define __REGA0_R30 30 #define __REGA0_R31 31 +/* For use with PPC_RAW_() macros */ +#define _R0 0 +#define _R1 1 +#define _R2 2 +#define _R3 3 +#define _R4 4 +#define _R5 5 +#define _R6 6 +#define _R7 7 +#define _R8 8 +#define _R9 9 +#define _R10 10 +#define _R11 11 +#define _R12 12 +#define _R13 13 +#define _R14 14 +#define _R15 15 +#define _R16 16 +#define _R17 17 +#define _R18 18 +#define _R19 19 +#define _R20 20 +#define _R21 21 +#define _R22 22 +#define _R23 23 +#define _R24 24 +#define _R25 25 +#define _R26 26 +#define _R27 27 +#define _R28 28 +#define _R29 29 +#define _R30 30 +#define _R31 31 + #define IMM_L(i) ((uintptr_t)(i) & 0xffff) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0) @@ -222,13 +256,11 @@ #define PPC_INST_LWSYNC 0x7c2004ac #define PPC_INST_SYNC 0x7c0004ac #define PPC_INST_SYNC_MASK 0xfc0007fe -#define PPC_INST_ISYNC 0x4c00012c #define PPC_INST_MCRXR 0x7c000400 #define PPC_INST_MCRXR_MASK 0xfc0007fe #define PPC_INST_MFSPR_PVR 0x7c1f42a6 #define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe #define PPC_INST_MTMSRD 0x7c000164 -#define PPC_INST_NOP 0x60000000 #define PPC_INST_POPCNTB 0x7c0000f4 #define PPC_INST_POPCNTB_MASK 0xfc0007fe #define PPC_INST_RFEBB 0x4c000124 @@ -241,10 +273,10 @@ #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe -#define PPC_INST_SC 0x44000002 #define PPC_INST_STRING 0x7c00042a #define PPC_INST_STRING_MASK 0xfc0007fe #define PPC_INST_STRING_GEN_MASK 0xfc00067e +#define PPC_INST_SETB 0x7c000100 #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a #define PPC_INST_TRECHKPT 0x7c0007dd @@ -252,18 +284,9 @@ #define PPC_INST_TSR 0x7c0005dd #define PPC_INST_LD 0xe8000000 #define PPC_INST_STD 0xf8000000 -#define PPC_INST_MFLR 0x7c0802a6 -#define PPC_INST_MTCTR 0x7c0903a6 -#define PPC_INST_ADDI 0x38000000 #define PPC_INST_ADDIS 0x3c000000 #define PPC_INST_ADD 0x7c000214 -#define PPC_INST_BLR 0x4e800020 -#define PPC_INST_BCTR 0x4e800420 -#define PPC_INST_BCTRL 0x4e800421 #define PPC_INST_DIVD 0x7c0003d2 -#define PPC_INST_RLDICR 0x78000004 -#define PPC_INST_ORI 0x60000000 -#define PPC_INST_ORIS 0x64000000 #define PPC_INST_BRANCH 0x48000000 #define PPC_INST_BL 0x48000001 #define PPC_INST_BRANCH_COND 0x40800000 @@ -323,6 +346,8 @@ #define PPC_LO(v) ((v) & 0xffff) #define PPC_HI(v) (((v) >> 16) & 0xffff) #define PPC_HA(v) PPC_HI((v) + 0x8000) +#define PPC_HIGHER(v) (((v) >> 32) & 0xffff) +#define PPC_HIGHEST(v) (((v) >> 48) & 0xffff) /* * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a @@ -383,6 +408,10 @@ #define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) #define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21)) #define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21)) +#define PPC_RAW_SC() (0x44000002) +#define PPC_RAW_SYNC() (0x7c0004ac) +#define PPC_RAW_ISYNC() (0x4c00012c) + /* * Define what the VSX XX1 form instructions will look like, then add * the 128 bit load store instructions based on that. @@ -404,10 +433,10 @@ #define PPC_RAW_STXVP(xsp, a, i) (0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i)) #define PPC_RAW_LXVPX(xtp, a, b) (0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b)) #define PPC_RAW_STXVPX(xsp, a, b) (0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_RAW_PLXVP(xtp, i, a, pr) \ - ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i))) -#define PPC_RAW_PSTXVP(xsp, i, a, pr) \ - ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i))) +#define PPC_RAW_PLXVP_P(xtp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) +#define PPC_RAW_PLXVP_S(xtp, i, a, pr) (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i)) +#define PPC_RAW_PSTXVP_P(xsp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) +#define PPC_RAW_PSTXVP_S(xsp, i, a, pr) (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i)) #define PPC_RAW_NAP (0x4c000364) #define PPC_RAW_SLEEP (0x4c0003a4) #define PPC_RAW_WINKLE (0x4c0003e4) @@ -445,16 +474,17 @@ #define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) #define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) #define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) -#define PPC_RAW_NOP() (PPC_INST_NOP) -#define PPC_RAW_BLR() (PPC_INST_BLR) +#define PPC_RAW_NOP() PPC_RAW_ORI(0, 0, 0) +#define PPC_RAW_BLR() (0x4e800020) #define PPC_RAW_BLRL() (0x4e800021) #define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r)) -#define PPC_RAW_MFLR(t) (PPC_INST_MFLR | ___PPC_RT(t)) -#define PPC_RAW_BCTR() (PPC_INST_BCTR) -#define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r)) -#define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_MFLR(t) (0x7c0802a6 | ___PPC_RT(t)) +#define PPC_RAW_BCTR() (0x4e800420) +#define PPC_RAW_BCTRL() (0x4e800421) +#define PPC_RAW_MTCTR(r) (0x7c0903a6 | ___PPC_RT(r)) +#define PPC_RAW_ADDI(d, a, i) (0x38000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) #define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i) -#define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_ADDIS(d, a, i) (0x3c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) #define PPC_RAW_ADDIC(d, a, i) (0x30000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) #define PPC_RAW_ADDIC_DOT(d, a, i) (0x34000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) #define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i) @@ -499,8 +529,8 @@ #define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) #define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) #define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a) -#define PPC_RAW_ORI(d, a, i) (PPC_INST_ORI | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) -#define PPC_RAW_ORIS(d, a, i) (PPC_INST_ORIS | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) +#define PPC_RAW_ORI(d, a, i) (0x60000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) +#define PPC_RAW_ORIS(d, a, i) (0x64000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) #define PPC_RAW_NOR(d, a, b) (0x7c0000f8 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) #define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) #define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) @@ -519,7 +549,7 @@ (0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me)) #define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me)) #define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb)) -#define PPC_RAW_RLDICR(d, a, i, me) (PPC_INST_RLDICR | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me)) +#define PPC_RAW_RLDICR(d, a, i, me) (0x78000004 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me)) /* slwi = rlwinm Rx, Ry, n, 0, 31-n */ #define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i)) @@ -533,6 +563,8 @@ #define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a)) #define PPC_RAW_MFSPR(d, spr) (0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr)) +#define PPC_RAW_MTSPR(spr, d) (0x7c0003a6 | ___PPC_RS(d) | __PPC_SPR(spr)) +#define PPC_RAW_EIEIO() (0x7c0006ac) /* Deal with instructions that older assemblers aren't aware of */ #define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index d6739d700f0a..116c1519728a 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -762,6 +762,21 @@ END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) stringify_in_c(.long (_target) - . ;) \ stringify_in_c(.previous) +#define SOFT_MASK_TABLE(_start, _end) \ + stringify_in_c(.section __soft_mask_table,"a";)\ + stringify_in_c(.balign 8;) \ + stringify_in_c(.llong (_start);) \ + stringify_in_c(.llong (_end);) \ + stringify_in_c(.previous) + +#define RESTART_TABLE(_start, _end, _target) \ + stringify_in_c(.section __restart_table,"a";)\ + stringify_in_c(.balign 8;) \ + stringify_in_c(.llong (_start);) \ + stringify_in_c(.llong (_end);) \ + stringify_in_c(.llong (_target);) \ + stringify_in_c(.previous) + #ifdef CONFIG_PPC_FSL_BOOK3E #define BTB_FLUSH(reg) \ lis reg,BUCSR_INIT@h; \ diff --git a/arch/powerpc/include/asm/probes.h b/arch/powerpc/include/asm/probes.h index 84dd1addd434..c5d984700d24 100644 --- a/arch/powerpc/include/asm/probes.h +++ b/arch/powerpc/include/asm/probes.h @@ -34,14 +34,14 @@ typedef u32 ppc_opcode_t; /* Enable single stepping for the current task */ static inline void enable_single_step(struct pt_regs *regs) { - regs->msr |= MSR_SINGLESTEP; + regs_set_return_msr(regs, regs->msr | MSR_SINGLESTEP); #ifdef CONFIG_PPC_ADV_DEBUG_REGS /* * We turn off Critical Input Exception(CE) to ensure that the single * step will be for the instruction we have the probe on; if we don't, * it is possible we'd get the single step reported for CE. */ - regs->msr &= ~MSR_CE; + regs_set_return_msr(regs, regs->msr & ~MSR_CE); mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM); #ifdef CONFIG_PPC_47x isync(); diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 7bf8a15af224..f348e564f7dd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -276,7 +276,15 @@ struct thread_struct { #define SPEFSCR_INIT #endif -#ifdef CONFIG_PPC32 +#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) +#define INIT_THREAD { \ + .ksp = INIT_SP, \ + .pgdir = swapper_pg_dir, \ + .kuap = ~0UL, /* KUAP_NONE */ \ + .fpexc_mode = MSR_FE0 | MSR_FE1, \ + SPEFSCR_INIT \ +} +#elif defined(CONFIG_PPC32) #define INIT_THREAD { \ .ksp = INIT_SP, \ .pgdir = swapper_pg_dir, \ @@ -339,17 +347,6 @@ static inline unsigned long __pack_fe01(unsigned int fpmode) #define spin_end() HMT_medium() -#define spin_until_cond(cond) \ -do { \ - if (unlikely(!(cond))) { \ - spin_begin(); \ - do { \ - spin_cpu_relax(); \ - } while (!(cond)); \ - spin_end(); \ - } \ -} while (0) - #endif /* Check that a certain kernel stack pointer is valid in task_struct p */ diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h index e646c7f218bc..8a0d8fb35328 100644 --- a/arch/powerpc/include/asm/ps3.h +++ b/arch/powerpc/include/asm/ps3.h @@ -71,6 +71,7 @@ struct ps3_dma_region_ops; * @bus_addr: The 'translated' bus address of the region. * @len: The length in bytes of the region. * @offset: The offset from the start of memory of the region. + * @dma_mask: Device dma_mask. * @ioid: The IOID of the device who owns this region * @chunk_list: Opaque variable used by the ioc page manager. * @region_ops: struct ps3_dma_region_ops - dma region operations @@ -85,6 +86,7 @@ struct ps3_dma_region { enum ps3_dma_region_type region_type; unsigned long len; unsigned long offset; + u64 dma_mask; /* driver variables (set by ps3_dma_region_create) */ unsigned long bus_addr; @@ -232,7 +234,7 @@ enum lv1_result { static inline const char* ps3_result(int result) { -#if defined(DEBUG) || defined(PS3_VERBOSE_RESULT) +#if defined(DEBUG) || defined(PS3_VERBOSE_RESULT) || defined(CONFIG_PS3_VERBOSE_RESULT) switch (result) { case LV1_SUCCESS: return "LV1_SUCCESS (0)"; diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index b476a685f066..3e5d470a6155 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -48,11 +48,12 @@ struct pt_regs unsigned long result; }; }; - +#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_KUAP) union { struct { #ifdef CONFIG_PPC64 unsigned long ppr; + unsigned long exit_result; #endif union { #ifdef CONFIG_PPC_KUAP @@ -68,6 +69,7 @@ struct pt_regs }; unsigned long __pad[4]; /* Maintain 16 byte interrupt stack alignment */ }; +#endif }; #endif @@ -122,6 +124,41 @@ struct pt_regs #endif /* __powerpc64__ */ #ifndef __ASSEMBLY__ +#include + +#ifdef CONFIG_SMP +extern unsigned long profile_pc(struct pt_regs *regs); +#else +#define profile_pc(regs) instruction_pointer(regs) +#endif + +long do_syscall_trace_enter(struct pt_regs *regs); +void do_syscall_trace_leave(struct pt_regs *regs); + +static inline void set_return_regs_changed(void) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + local_paca->hsrr_valid = 0; + local_paca->srr_valid = 0; +#endif +} + +static inline void regs_set_return_ip(struct pt_regs *regs, unsigned long ip) +{ + regs->nip = ip; + set_return_regs_changed(); +} + +static inline void regs_set_return_msr(struct pt_regs *regs, unsigned long msr) +{ + regs->msr = msr; + set_return_regs_changed(); +} + +static inline void regs_add_return_ip(struct pt_regs *regs, long offset) +{ + regs_set_return_ip(regs, regs->nip + offset); +} static inline unsigned long instruction_pointer(struct pt_regs *regs) { @@ -131,7 +168,7 @@ static inline unsigned long instruction_pointer(struct pt_regs *regs) static inline void instruction_pointer_set(struct pt_regs *regs, unsigned long val) { - regs->nip = val; + regs_set_return_ip(regs, val); } static inline unsigned long user_stack_pointer(struct pt_regs *regs) @@ -144,15 +181,6 @@ static inline unsigned long frame_pointer(struct pt_regs *regs) return 0; } -#ifdef CONFIG_SMP -extern unsigned long profile_pc(struct pt_regs *regs); -#else -#define profile_pc(regs) instruction_pointer(regs) -#endif - -long do_syscall_trace_enter(struct pt_regs *regs); -void do_syscall_trace_leave(struct pt_regs *regs); - #ifdef __powerpc64__ #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) #else diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 7c81d3e563b2..be85cf156a1f 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -393,6 +393,7 @@ #define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */ #define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ #define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */ +#define SPRN_TRIG2 0x372 #define SPRN_PMCR 0x374 /* Power Management Control Register */ #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */ @@ -1435,8 +1436,6 @@ static inline void mtsr(u32 val, u32 idx) } #endif -#define proc_trap() asm volatile("trap") - extern unsigned long current_stack_frame(void); register unsigned long current_stack_pointer asm("r1"); @@ -1447,16 +1446,6 @@ extern void scom970_write(unsigned int address, unsigned long value); struct pt_regs; extern void ppc_save_regs(struct pt_regs *regs); - -static inline void update_power8_hid0(unsigned long hid0) -{ - /* - * The HID0 update on Power8 should at the very least be - * preceded by a SYNC instruction followed by an ISYNC - * instruction - */ - asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); -} #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_REG_H */ diff --git a/arch/powerpc/include/asm/security_features.h b/arch/powerpc/include/asm/security_features.h index b774a4477d5f..792eefaf230b 100644 --- a/arch/powerpc/include/asm/security_features.h +++ b/arch/powerpc/include/asm/security_features.h @@ -92,6 +92,9 @@ static inline bool security_ftr_enabled(u64 feature) // The L1-D cache should be flushed after user accesses from the kernel #define SEC_FTR_L1D_FLUSH_UACCESS 0x0000000000008000ull +// The STF flush should be executed on privilege state switch +#define SEC_FTR_STF_BARRIER 0x0000000000010000ull + // Features enabled by default #define SEC_FTR_DEFAULT \ (SEC_FTR_L1D_FLUSH_HV | \ @@ -99,6 +102,7 @@ static inline bool security_ftr_enabled(u64 feature) SEC_FTR_BNDS_CHK_SPEC_BAR | \ SEC_FTR_L1D_FLUSH_ENTRY | \ SEC_FTR_L1D_FLUSH_UACCESS | \ + SEC_FTR_STF_BARRIER | \ SEC_FTR_FAVOUR_SECURITY) #endif /* _ASM_POWERPC_SECURITY_FEATURES_H */ diff --git a/arch/powerpc/include/asm/set_memory.h b/arch/powerpc/include/asm/set_memory.h new file mode 100644 index 000000000000..b040094f7920 --- /dev/null +++ b/arch/powerpc/include/asm/set_memory.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_SET_MEMORY_H +#define _ASM_POWERPC_SET_MEMORY_H + +#define SET_MEMORY_RO 0 +#define SET_MEMORY_RW 1 +#define SET_MEMORY_NX 2 +#define SET_MEMORY_X 3 + +int change_memory_attr(unsigned long addr, int numpages, long action); + +static inline int set_memory_ro(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_RO); +} + +static inline int set_memory_rw(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_RW); +} + +static inline int set_memory_nx(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_NX); +} + +static inline int set_memory_x(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_X); +} + +int set_memory_attr(unsigned long addr, int numpages, pgprot_t prot); + +#endif diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h index e89bfebd4e00..6c1a7d217d1a 100644 --- a/arch/powerpc/include/asm/setup.h +++ b/arch/powerpc/include/asm/setup.h @@ -10,7 +10,6 @@ extern void ppc_printk_progress(char *s, unsigned short hex); extern unsigned int rtas_data; extern unsigned long long memory_limit; extern bool init_mem_is_free; -extern unsigned long klimit; extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); struct device_node; diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h index 972ed0df154d..1df867c2e054 100644 --- a/arch/powerpc/include/asm/sstep.h +++ b/arch/powerpc/include/asm/sstep.h @@ -13,12 +13,11 @@ struct pt_regs; * we don't allow putting a breakpoint on an mtmsrd instruction. * Similarly we don't allow breakpoints on rfid instructions. * These macros tell us if an instruction is a mtmsrd or rfid. - * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) - * and an mtmsrd (64-bit). + * Note that these return true for both mtmsr/rfi (32-bit) + * and mtmsrd/rfid (64-bit). */ #define IS_MTMSRD(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124) -#define IS_RFID(instr) ((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000024) -#define IS_RFI(instr) ((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000064) +#define IS_RFID(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x4c000024) enum instruction_type { COMPUTE, /* arith/logical/CR op, etc. */ diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h deleted file mode 100644 index ce69c5eff95e..000000000000 --- a/arch/powerpc/include/asm/unaligned.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_POWERPC_UNALIGNED_H -#define _ASM_POWERPC_UNALIGNED_H - -#ifdef __KERNEL__ - -/* - * The PowerPC can do unaligned accesses itself based on its endian mode. - */ -#include -#include - -#ifdef __LITTLE_ENDIAN__ -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#endif - -#endif /* __KERNEL__ */ -#endif /* _ASM_POWERPC_UNALIGNED_H */ diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h index 5bf65f5d44a9..fe683371336f 100644 --- a/arch/powerpc/include/asm/uprobes.h +++ b/arch/powerpc/include/asm/uprobes.h @@ -24,8 +24,8 @@ typedef ppc_opcode_t uprobe_opcode_t; struct arch_uprobe { union { - struct ppc_inst insn; - struct ppc_inst ixol; + u32 insn[2]; + u32 ixol[2]; }; }; diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h index e33f80b0ea81..57573d9c1e09 100644 --- a/arch/powerpc/include/asm/vas.h +++ b/arch/powerpc/include/asm/vas.h @@ -5,8 +5,10 @@ #ifndef _ASM_POWERPC_VAS_H #define _ASM_POWERPC_VAS_H - -struct vas_window; +#include +#include +#include +#include /* * Min and max FIFO sizes are based on Version 1.05 Section 3.1.4.25 @@ -48,6 +50,64 @@ enum vas_cop_type { VAS_COP_TYPE_MAX, }; +/* + * User space VAS windows are opened by tasks and take references + * to pid and mm until windows are closed. + * Stores pid, mm, and tgid for each window. + */ +struct vas_user_win_ref { + struct pid *pid; /* PID of owner */ + struct pid *tgid; /* Thread group ID of owner */ + struct mm_struct *mm; /* Linux process mm_struct */ +}; + +/* + * Common VAS window struct on PowerNV and PowerVM + */ +struct vas_window { + u32 winid; + u32 wcreds_max; /* Window credits */ + enum vas_cop_type cop; + struct vas_user_win_ref task_ref; + char *dbgname; + struct dentry *dbgdir; +}; + +/* + * User space window operations used for powernv and powerVM + */ +struct vas_user_win_ops { + struct vas_window * (*open_win)(int vas_id, u64 flags, + enum vas_cop_type); + u64 (*paste_addr)(struct vas_window *); + int (*close_win)(struct vas_window *); +}; + +static inline void put_vas_user_win_ref(struct vas_user_win_ref *ref) +{ + /* Drop references to pid, tgid, and mm */ + put_pid(ref->pid); + put_pid(ref->tgid); + if (ref->mm) + mmdrop(ref->mm); +} + +static inline void vas_user_win_add_mm_context(struct vas_user_win_ref *ref) +{ + mm_context_add_vas_window(ref->mm); + /* + * Even a process that has no foreign real address mapping can + * use an unpaired COPY instruction (to no real effect). Issue + * CP_ABORT to clear any pending COPY and prevent a covert + * channel. + * + * __switch_to() will issue CP_ABORT on future context switches + * if process / thread has any open VAS window (Use + * current->mm->context.vas_windows). + */ + asm volatile(PPC_CP_ABORT); +} + /* * Receive window attributes specified by the (in-kernel) owner of window. */ @@ -100,6 +160,7 @@ struct vas_tx_win_attr { bool rx_win_ord_mode; }; +#ifdef CONFIG_PPC_POWERNV /* * Helper to map a chip id to VAS id. * For POWER9, this is a 1:1 mapping. In the future this maybe a 1:N @@ -162,6 +223,43 @@ int vas_copy_crb(void *crb, int offset); */ int vas_paste_crb(struct vas_window *win, int offset, bool re); +int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type, + const char *name); +void vas_unregister_api_powernv(void); +#endif + +#ifdef CONFIG_PPC_PSERIES + +/* VAS Capabilities */ +#define VAS_GZIP_QOS_FEAT 0x1 +#define VAS_GZIP_DEF_FEAT 0x2 +#define VAS_GZIP_QOS_FEAT_BIT PPC_BIT(VAS_GZIP_QOS_FEAT) /* Bit 1 */ +#define VAS_GZIP_DEF_FEAT_BIT PPC_BIT(VAS_GZIP_DEF_FEAT) /* Bit 2 */ + +/* NX Capabilities */ +#define VAS_NX_GZIP_FEAT 0x1 +#define VAS_NX_GZIP_FEAT_BIT PPC_BIT(VAS_NX_GZIP_FEAT) /* Bit 1 */ + +/* + * These structs are used to retrieve overall VAS capabilities that + * the hypervisor provides. + */ +struct hv_vas_all_caps { + __be64 descriptor; + __be64 feat_type; +} __packed __aligned(0x1000); + +struct vas_all_caps { + u64 descriptor; + u64 feat_type; +}; + +int h_query_vas_capabilities(const u64 hcall, u8 query_type, u64 result); +int vas_register_api_pseries(struct module *mod, + enum vas_cop_type cop_type, const char *name); +void vas_unregister_api_pseries(void); +#endif + /* * Register / unregister coprocessor type to VAS API which will be exported * to user space. Applications can use this API to open / close window @@ -171,7 +269,12 @@ int vas_paste_crb(struct vas_window *win, int offset, bool re); * used for others in future. */ int vas_register_coproc_api(struct module *mod, enum vas_cop_type cop_type, - const char *name); + const char *name, + const struct vas_user_win_ops *vops); void vas_unregister_coproc_api(void); +int get_vas_user_win_ref(struct vas_user_win_ref *task_ref); +void vas_update_csb(struct coprocessor_request_block *crb, + struct vas_user_win_ref *task_ref); +void vas_dump_crb(struct coprocessor_request_block *crb); #endif /* __ASM_POWERPC_VAS_H */ diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h index 8e903b3f9c24..d9cf192368ad 100644 --- a/arch/powerpc/include/asm/xics.h +++ b/arch/powerpc/include/asm/xics.h @@ -65,8 +65,12 @@ struct icp_ops { extern const struct icp_ops *icp_ops; +#ifdef CONFIG_PPC_ICS_NATIVE /* Native ICS */ extern int ics_native_init(void); +#else +static inline int ics_native_init(void) { return -ENODEV; } +#endif /* RTAS ICS */ #ifdef CONFIG_PPC_ICS_RTAS diff --git a/arch/powerpc/include/uapi/asm/papr_pdsm.h b/arch/powerpc/include/uapi/asm/papr_pdsm.h index 50ef95e2f5b1..82488b1e7276 100644 --- a/arch/powerpc/include/uapi/asm/papr_pdsm.h +++ b/arch/powerpc/include/uapi/asm/papr_pdsm.h @@ -77,6 +77,9 @@ /* Indicate that the 'dimm_fuel_gauge' field is valid */ #define PDSM_DIMM_HEALTH_RUN_GAUGE_VALID 1 +/* Indicate that the 'dimm_dsc' field is valid */ +#define PDSM_DIMM_DSC_VALID 2 + /* * Struct exchanged between kernel & ndctl in for PAPR_PDSM_HEALTH * Various flags indicate the health status of the dimm. @@ -105,6 +108,9 @@ struct nd_papr_pdsm_health { /* Extension flag PDSM_DIMM_HEALTH_RUN_GAUGE_VALID */ __u16 dimm_fuel_gauge; + + /* Extension flag PDSM_DIMM_DSC_VALID */ + __u64 dimm_dsc; }; __u8 buf[ND_PDSM_PAYLOAD_MAX_SIZE]; }; diff --git a/arch/powerpc/include/uapi/asm/vas-api.h b/arch/powerpc/include/uapi/asm/vas-api.h index ebd4b2424785..7c81301ecdba 100644 --- a/arch/powerpc/include/uapi/asm/vas-api.h +++ b/arch/powerpc/include/uapi/asm/vas-api.h @@ -13,11 +13,15 @@ #define VAS_MAGIC 'v' #define VAS_TX_WIN_OPEN _IOW(VAS_MAGIC, 0x20, struct vas_tx_win_open_attr) +/* Flags to VAS TX open window ioctl */ +/* To allocate a window with QoS credit, otherwise use default credit */ +#define VAS_TX_WIN_FLAG_QOS_CREDIT 0x0000000000000001 + struct vas_tx_win_open_attr { __u32 version; __s16 vas_id; /* specific instance of vas or -1 for default */ __u16 reserved1; - __u64 flags; /* Future use */ + __u64 flags; __u64 reserved2[6]; }; diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index aa267d173ded..a47eefa09bcb 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -86,11 +86,7 @@ int main(void) OFFSET(PACA_CANARY, paca_struct, canary); #endif #endif - OFFSET(MMCONTEXTID, mm_struct, context.id); -#ifdef CONFIG_PPC64 - DEFINE(SIGSEGV, SIGSEGV); - DEFINE(NMI_MASK, NMI_MASK); -#else +#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC_RTAS OFFSET(RTAS_SP, thread_struct, rtas_sp); #endif @@ -119,7 +115,6 @@ int main(void) #ifdef CONFIG_ALTIVEC OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr); OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area); - OFFSET(THREAD_VRSAVE, thread_struct, vrsave); OFFSET(THREAD_USED_VR, thread_struct, used_vr); OFFSET(VRSTATE_VSCR, thread_vr_state, vscr); OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec); @@ -150,22 +145,15 @@ int main(void) #ifdef CONFIG_SPE OFFSET(THREAD_EVR0, thread_struct, evr[0]); OFFSET(THREAD_ACC, thread_struct, acc); - OFFSET(THREAD_SPEFSCR, thread_struct, spefscr); OFFSET(THREAD_USED_SPE, thread_struct, used_spe); #endif /* CONFIG_SPE */ #endif /* CONFIG_PPC64 */ -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) - OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0); -#endif #ifdef CONFIG_KVM_BOOK3S_32_HANDLER OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu); #endif #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu); #endif -#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) - OFFSET(KUAP, thread_struct, kuap); -#endif #ifdef CONFIG_PPC_TRANSACTIONAL_MEM OFFSET(PACATMSCRATCH, paca_struct, tm_scratch); @@ -185,19 +173,12 @@ int main(void) sizeof(struct pt_regs) + 16); #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ - OFFSET(TI_FLAGS, thread_info, flags); OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags); - OFFSET(TI_PREEMPT, thread_info, preempt_count); #ifdef CONFIG_PPC64 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size); OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size); - OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page); - OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size); - OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size); - OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page); /* paca */ - DEFINE(PACA_SIZE, sizeof(struct paca_struct)); OFFSET(PACAPACAINDEX, paca_struct, paca_index); OFFSET(PACAPROCSTART, paca_struct, cpu_start); OFFSET(PACAKSAVE, paca_struct, kstack); @@ -209,18 +190,13 @@ int main(void) OFFSET(PACATOC, paca_struct, kernel_toc); OFFSET(PACAKBASE, paca_struct, kernelbase); OFFSET(PACAKMSR, paca_struct, kernel_msr); +#ifdef CONFIG_PPC_BOOK3S_64 + OFFSET(PACAHSRR_VALID, paca_struct, hsrr_valid); + OFFSET(PACASRR_VALID, paca_struct, srr_valid); +#endif OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask); OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); -#ifdef CONFIG_PPC_BOOK3S - OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id); -#ifdef CONFIG_PPC_MM_SLICES - OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize); - OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize); - OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit); - DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); -#endif /* CONFIG_PPC_MM_SLICES */ -#endif #ifdef CONFIG_PPC_BOOK3E OFFSET(PACAPGD, paca_struct, pgd); @@ -241,21 +217,9 @@ int main(void) #endif /* CONFIG_PPC_BOOK3E */ #ifdef CONFIG_PPC_BOOK3S_64 - OFFSET(PACASLBCACHE, paca_struct, slb_cache); - OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr); - OFFSET(PACASTABRR, paca_struct, stab_rr); - OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp); -#ifdef CONFIG_PPC_MM_SLICES - OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp); -#else - OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp); -#endif /* CONFIG_PPC_MM_SLICES */ OFFSET(PACA_EXGEN, paca_struct, exgen); OFFSET(PACA_EXMC, paca_struct, exmc); OFFSET(PACA_EXNMI, paca_struct, exnmi); -#ifdef CONFIG_PPC_PSERIES - OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr); -#endif OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr); OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid); OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid); @@ -264,9 +228,7 @@ int main(void) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use); #endif - OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx); OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count); - OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx); #endif /* CONFIG_PPC_BOOK3S_64 */ OFFSET(PACAEMERGSP, paca_struct, emergency_sp); #ifdef CONFIG_PPC_BOOK3S_64 @@ -282,6 +244,9 @@ int main(void) OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id); OFFSET(PACAKEXECSTATE, paca_struct, kexec_state); OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default); +#ifdef CONFIG_PPC64 + OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1); +#endif #ifdef CONFIG_PPC_BOOK3E OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); #endif @@ -343,10 +308,6 @@ int main(void) STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr); STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr); #endif -#ifdef CONFIG_PPC_KUAP - STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap); -#endif - #if defined(CONFIG_PPC32) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) @@ -368,10 +329,6 @@ int main(void) #endif #endif -#ifndef CONFIG_PPC64 - OFFSET(MM_PGD, mm_struct, pgd); -#endif /* ! CONFIG_PPC64 */ - /* About the CPU features table */ OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); @@ -404,13 +361,6 @@ int main(void) DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); #endif -#ifdef CONFIG_PPC_BOOK3S_64 - DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE))); -#else - DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); -#endif - DEFINE(PTE_SIZE, sizeof(pte_t)); - #ifdef CONFIG_KVM OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack); OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid); @@ -482,11 +432,9 @@ int main(void) OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid); OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr); OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1); - OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits); OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls); OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); OFFSET(KVM_RADIX, kvm, arch.radix); - OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest); OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); @@ -514,7 +462,6 @@ int main(void) OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1); OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr); OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags); - OFFSET(VCPU_DEC, kvm_vcpu, arch.dec); OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires); OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions); OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded); @@ -525,7 +472,6 @@ int main(void) OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra); OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs); OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc); - OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc); OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar); OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar); OFFSET(VCPU_SIER, kvm_vcpu, arch.sier); @@ -645,10 +591,8 @@ int main(void) HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); - HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys); HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys); HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt); - HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr); HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi); HSTATE_FIELD(HSTATE_PTID, ptid); HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend); @@ -756,7 +700,6 @@ int main(void) #endif DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); - DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE); #ifdef CONFIG_PPC_8xx DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 735e89337398..5693e1c67c2b 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -35,7 +35,7 @@ void __init reserve_kdump_trampoline(void) static void __init create_trampoline(unsigned long addr) { - struct ppc_inst *p = (struct ppc_inst *)addr; + u32 *p = (u32 *)addr; /* The maximum range of a single instruction branch, is the current * instruction's address + (32 MB - 4) bytes. For the trampoline we @@ -45,8 +45,8 @@ static void __init create_trampoline(unsigned long addr) * branch to "addr" we jump to ("addr" + 32 MB). Although it requires * two instructions it doesn't require any registers. */ - patch_instruction(p, ppc_inst(PPC_INST_NOP)); - patch_branch((void *)p + 4, addr + PHYSICAL_START, 0); + patch_instruction(p, ppc_inst(PPC_RAW_NOP())); + patch_branch(p + 1, addr + PHYSICAL_START, 0); } void __init setup_kdump_trampoline(void) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 9160285cb2f4..0273a1349006 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -32,6 +32,7 @@ #include #include #include +#include #include "head_32.h" @@ -74,6 +75,24 @@ _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) .globl transfer_to_syscall transfer_to_syscall: + stw r11, GPR1(r1) + stw r11, 0(r1) + mflr r12 + stw r12, _LINK(r1) +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) + rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ +#endif + lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ + SAVE_GPR(2, r1) + addi r12,r12,STACK_FRAME_REGS_MARKER@l + stw r9,_MSR(r1) + li r2, INTERRUPT_SYSCALL + stw r12,8(r1) + stw r2,_TRAP(r1) + SAVE_GPR(0, r1) + SAVE_4GPRS(3, r1) + SAVE_2GPRS(7, r1) + addi r2,r10,-THREAD SAVE_NVGPRS(r1) /* Calling convention has r9 = orig r0, r10 = regs */ @@ -176,28 +195,6 @@ _GLOBAL(_switch) /* r3-r12 are caller saved -- Cort */ SAVE_NVGPRS(r1) stw r0,_NIP(r1) /* Return to switch caller */ - mfmsr r11 - li r0,MSR_FP /* Disable floating-point */ -#ifdef CONFIG_ALTIVEC -BEGIN_FTR_SECTION - oris r0,r0,MSR_VEC@h /* Disable altivec */ - mfspr r12,SPRN_VRSAVE /* save vrsave register value */ - stw r12,THREAD+THREAD_VRSAVE(r2) -END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) -#endif /* CONFIG_ALTIVEC */ -#ifdef CONFIG_SPE -BEGIN_FTR_SECTION - oris r0,r0,MSR_SPE@h /* Disable SPE */ - mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ - stw r12,THREAD+THREAD_SPEFSCR(r2) -END_FTR_SECTION_IFSET(CPU_FTR_SPE) -#endif /* CONFIG_SPE */ - and. r0,r0,r11 /* FP or altivec or SPE enabled? */ - beq+ 1f - andc r11,r11,r0 - mtmsr r11 - isync -1: stw r11,_MSR(r1) mfcr r10 stw r10,_CCR(r1) stw r1,KSP(r3) /* Set old stack pointer */ @@ -218,19 +215,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE) mr r3,r2 addi r2,r4,-THREAD /* Update current */ -#ifdef CONFIG_ALTIVEC -BEGIN_FTR_SECTION - lwz r0,THREAD+THREAD_VRSAVE(r2) - mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ -END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) -#endif /* CONFIG_ALTIVEC */ -#ifdef CONFIG_SPE -BEGIN_FTR_SECTION - lwz r0,THREAD+THREAD_SPEFSCR(r2) - mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ -END_FTR_SECTION_IFSET(CPU_FTR_SPE) -#endif /* CONFIG_SPE */ - lwz r0,_CCR(r1) mtcrf 0xFF,r0 /* r3-r12 are destroyed -- Cort */ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 03727308d8cc..15720f8661a1 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -48,372 +47,7 @@ /* * System calls. */ - .section ".toc","aw" -SYS_CALL_TABLE: - .tc sys_call_table[TC],sys_call_table - -#ifdef CONFIG_COMPAT -COMPAT_SYS_CALL_TABLE: - .tc compat_sys_call_table[TC],compat_sys_call_table -#endif - -/* This value is used to mark exception frames on the stack. */ -exception_marker: - .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER - .section ".text" - .align 7 - -#ifdef CONFIG_PPC_BOOK3S -.macro system_call_vectored name trapnr - .globl system_call_vectored_\name -system_call_vectored_\name: -_ASM_NOKPROBE_SYMBOL(system_call_vectored_\name) -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM -BEGIN_FTR_SECTION - extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ - bne .Ltabort_syscall -END_FTR_SECTION_IFSET(CPU_FTR_TM) -#endif - SCV_INTERRUPT_TO_KERNEL - mr r10,r1 - ld r1,PACAKSAVE(r13) - std r10,0(r1) - std r11,_NIP(r1) - std r12,_MSR(r1) - std r0,GPR0(r1) - std r10,GPR1(r1) - std r2,GPR2(r1) - ld r2,PACATOC(r13) - mfcr r12 - li r11,0 - /* Can we avoid saving r3-r8 in common case? */ - std r3,GPR3(r1) - std r4,GPR4(r1) - std r5,GPR5(r1) - std r6,GPR6(r1) - std r7,GPR7(r1) - std r8,GPR8(r1) - /* Zero r9-r12, this should only be required when restoring all GPRs */ - std r11,GPR9(r1) - std r11,GPR10(r1) - std r11,GPR11(r1) - std r11,GPR12(r1) - std r9,GPR13(r1) - SAVE_NVGPRS(r1) - std r11,_XER(r1) - std r11,_LINK(r1) - std r11,_CTR(r1) - - li r11,\trapnr - std r11,_TRAP(r1) - std r12,_CCR(r1) - addi r10,r1,STACK_FRAME_OVERHEAD - ld r11,exception_marker@toc(r2) - std r11,-16(r10) /* "regshere" marker */ - -BEGIN_FTR_SECTION - HMT_MEDIUM -END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) - - /* - * scv enters with MSR[EE]=1 and is immediately considered soft-masked. - * The entry vector already sets PACAIRQSOFTMASK to IRQS_ALL_DISABLED, - * and interrupts may be masked and pending already. - * system_call_exception() will call trace_hardirqs_off() which means - * interrupts could already have been blocked before trace_hardirqs_off, - * but this is the best we can do. - */ - - /* Calling convention has r9 = orig r0, r10 = regs */ - mr r9,r0 - bl system_call_exception - -.Lsyscall_vectored_\name\()_exit: - addi r4,r1,STACK_FRAME_OVERHEAD - li r5,1 /* scv */ - bl syscall_exit_prepare - - ld r2,_CCR(r1) - ld r4,_NIP(r1) - ld r5,_MSR(r1) - -BEGIN_FTR_SECTION - stdcx. r0,0,r1 /* to clear the reservation */ -END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) - -BEGIN_FTR_SECTION - HMT_MEDIUM_LOW -END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) - - cmpdi r3,0 - bne .Lsyscall_vectored_\name\()_restore_regs - - /* rfscv returns with LR->NIA and CTR->MSR */ - mtlr r4 - mtctr r5 - - /* Could zero these as per ABI, but we may consider a stricter ABI - * which preserves these if libc implementations can benefit, so - * restore them for now until further measurement is done. */ - ld r0,GPR0(r1) - ld r4,GPR4(r1) - ld r5,GPR5(r1) - ld r6,GPR6(r1) - ld r7,GPR7(r1) - ld r8,GPR8(r1) - /* Zero volatile regs that may contain sensitive kernel data */ - li r9,0 - li r10,0 - li r11,0 - li r12,0 - mtspr SPRN_XER,r0 - - /* - * We don't need to restore AMR on the way back to userspace for KUAP. - * The value of AMR only matters while we're in the kernel. - */ - mtcr r2 - ld r2,GPR2(r1) - ld r3,GPR3(r1) - ld r13,GPR13(r1) - ld r1,GPR1(r1) - RFSCV_TO_USER - b . /* prevent speculative execution */ - -.Lsyscall_vectored_\name\()_restore_regs: - li r3,0 - mtmsrd r3,1 - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r5 - - ld r3,_CTR(r1) - ld r4,_LINK(r1) - ld r5,_XER(r1) - - REST_NVGPRS(r1) - ld r0,GPR0(r1) - mtcr r2 - mtctr r3 - mtlr r4 - mtspr SPRN_XER,r5 - REST_10GPRS(2, r1) - REST_2GPRS(12, r1) - ld r1,GPR1(r1) - RFI_TO_USER -.endm - -system_call_vectored common 0x3000 -/* - * We instantiate another entry copy for the SIGILL variant, with TRAP=0x7ff0 - * which is tested by system_call_exception when r0 is -1 (as set by vector - * entry code). - */ -system_call_vectored sigill 0x7ff0 - - -/* - * Entered via kernel return set up by kernel/sstep.c, must match entry regs - */ - .globl system_call_vectored_emulate -system_call_vectored_emulate: -_ASM_NOKPROBE_SYMBOL(system_call_vectored_emulate) - li r10,IRQS_ALL_DISABLED - stb r10,PACAIRQSOFTMASK(r13) - b system_call_vectored_common -#endif - - .balign IFETCH_ALIGN_BYTES - .globl system_call_common_real -system_call_common_real: - ld r10,PACAKMSR(r13) /* get MSR value for kernel */ - mtmsrd r10 - - .balign IFETCH_ALIGN_BYTES - .globl system_call_common -system_call_common: -_ASM_NOKPROBE_SYMBOL(system_call_common) -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM -BEGIN_FTR_SECTION - extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ - bne .Ltabort_syscall -END_FTR_SECTION_IFSET(CPU_FTR_TM) -#endif - mr r10,r1 - ld r1,PACAKSAVE(r13) - std r10,0(r1) - std r11,_NIP(r1) - std r12,_MSR(r1) - std r0,GPR0(r1) - std r10,GPR1(r1) - std r2,GPR2(r1) -#ifdef CONFIG_PPC_FSL_BOOK3E -START_BTB_FLUSH_SECTION - BTB_FLUSH(r10) -END_BTB_FLUSH_SECTION -#endif - ld r2,PACATOC(r13) - mfcr r12 - li r11,0 - /* Can we avoid saving r3-r8 in common case? */ - std r3,GPR3(r1) - std r4,GPR4(r1) - std r5,GPR5(r1) - std r6,GPR6(r1) - std r7,GPR7(r1) - std r8,GPR8(r1) - /* Zero r9-r12, this should only be required when restoring all GPRs */ - std r11,GPR9(r1) - std r11,GPR10(r1) - std r11,GPR11(r1) - std r11,GPR12(r1) - std r9,GPR13(r1) - SAVE_NVGPRS(r1) - std r11,_XER(r1) - std r11,_CTR(r1) - mflr r10 - - /* - * This clears CR0.SO (bit 28), which is the error indication on - * return from this system call. - */ - rldimi r12,r11,28,(63-28) - li r11,0xc00 - std r10,_LINK(r1) - std r11,_TRAP(r1) - std r12,_CCR(r1) - addi r10,r1,STACK_FRAME_OVERHEAD - ld r11,exception_marker@toc(r2) - std r11,-16(r10) /* "regshere" marker */ - - /* - * We always enter kernel from userspace with irq soft-mask enabled and - * nothing pending. system_call_exception() will call - * trace_hardirqs_off(). - */ - li r11,IRQS_ALL_DISABLED - li r12,PACA_IRQ_HARD_DIS - stb r11,PACAIRQSOFTMASK(r13) - stb r12,PACAIRQHAPPENED(r13) - - /* Calling convention has r9 = orig r0, r10 = regs */ - mr r9,r0 - bl system_call_exception - -.Lsyscall_exit: - addi r4,r1,STACK_FRAME_OVERHEAD - li r5,0 /* !scv */ - bl syscall_exit_prepare - - ld r2,_CCR(r1) - ld r4,_NIP(r1) - ld r5,_MSR(r1) - ld r6,_LINK(r1) - -BEGIN_FTR_SECTION - stdcx. r0,0,r1 /* to clear the reservation */ -END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) - - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r5 - mtlr r6 - - cmpdi r3,0 - bne .Lsyscall_restore_regs - /* Zero volatile regs that may contain sensitive kernel data */ - li r0,0 - li r4,0 - li r5,0 - li r6,0 - li r7,0 - li r8,0 - li r9,0 - li r10,0 - li r11,0 - li r12,0 - mtctr r0 - mtspr SPRN_XER,r0 -.Lsyscall_restore_regs_cont: - -BEGIN_FTR_SECTION - HMT_MEDIUM_LOW -END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) - - /* - * We don't need to restore AMR on the way back to userspace for KUAP. - * The value of AMR only matters while we're in the kernel. - */ - mtcr r2 - ld r2,GPR2(r1) - ld r3,GPR3(r1) - ld r13,GPR13(r1) - ld r1,GPR1(r1) - RFI_TO_USER - b . /* prevent speculative execution */ - -.Lsyscall_restore_regs: - ld r3,_CTR(r1) - ld r4,_XER(r1) - REST_NVGPRS(r1) - mtctr r3 - mtspr SPRN_XER,r4 - ld r0,GPR0(r1) - REST_8GPRS(4, r1) - ld r12,GPR12(r1) - b .Lsyscall_restore_regs_cont - -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM -.Ltabort_syscall: - /* Firstly we need to enable TM in the kernel */ - mfmsr r10 - li r9, 1 - rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG - mtmsrd r10, 0 - - /* tabort, this dooms the transaction, nothing else */ - li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT) - TABORT(R9) - - /* - * Return directly to userspace. We have corrupted user register state, - * but userspace will never see that register state. Execution will - * resume after the tbegin of the aborted transaction with the - * checkpointed register state. - */ - li r9, MSR_RI - andc r10, r10, r9 - mtmsrd r10, 1 - mtspr SPRN_SRR0, r11 - mtspr SPRN_SRR1, r12 - RFI_TO_USER - b . /* prevent speculative execution */ -#endif - -#ifdef CONFIG_PPC_BOOK3S -_GLOBAL(ret_from_fork_scv) - bl schedule_tail - REST_NVGPRS(r1) - li r3,0 /* fork() return value */ - b .Lsyscall_vectored_common_exit -#endif - -_GLOBAL(ret_from_fork) - bl schedule_tail - REST_NVGPRS(r1) - li r3,0 /* fork() return value */ - b .Lsyscall_exit - -_GLOBAL(ret_from_kernel_thread) - bl schedule_tail - REST_NVGPRS(r1) - mtctr r14 - mr r3,r15 -#ifdef PPC64_ELF_ABI_v2 - mr r12,r14 -#endif - bctrl - li r3,0 - b .Lsyscall_exit #ifdef CONFIG_PPC_BOOK3S_64 @@ -630,156 +264,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) addi r1,r1,SWITCH_FRAME_SIZE blr - /* - * If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not - * touched, no exit work created, then this can be used. - */ - .balign IFETCH_ALIGN_BYTES - .globl fast_interrupt_return -fast_interrupt_return: -_ASM_NOKPROBE_SYMBOL(fast_interrupt_return) - kuap_check_amr r3, r4 - ld r5,_MSR(r1) - andi. r0,r5,MSR_PR -#ifdef CONFIG_PPC_BOOK3S - bne .Lfast_user_interrupt_return_amr - kuap_kernel_restore r3, r4 - andi. r0,r5,MSR_RI - li r3,0 /* 0 return value, no EMULATE_STACK_STORE */ - bne+ .Lfast_kernel_interrupt_return - addi r3,r1,STACK_FRAME_OVERHEAD - bl unrecoverable_exception - b . /* should not get here */ -#else - bne .Lfast_user_interrupt_return - b .Lfast_kernel_interrupt_return -#endif - - .balign IFETCH_ALIGN_BYTES - .globl interrupt_return -interrupt_return: -_ASM_NOKPROBE_SYMBOL(interrupt_return) - ld r4,_MSR(r1) - andi. r0,r4,MSR_PR - beq .Lkernel_interrupt_return - addi r3,r1,STACK_FRAME_OVERHEAD - bl interrupt_exit_user_prepare - cmpdi r3,0 - bne- .Lrestore_nvgprs - -#ifdef CONFIG_PPC_BOOK3S -.Lfast_user_interrupt_return_amr: - kuap_user_restore r3, r4 -#endif -.Lfast_user_interrupt_return: - ld r11,_NIP(r1) - ld r12,_MSR(r1) -BEGIN_FTR_SECTION - ld r10,_PPR(r1) - mtspr SPRN_PPR,r10 -END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r12 - -BEGIN_FTR_SECTION - stdcx. r0,0,r1 /* to clear the reservation */ -FTR_SECTION_ELSE - ldarx r0,0,r1 -ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) - - ld r3,_CCR(r1) - ld r4,_LINK(r1) - ld r5,_CTR(r1) - ld r6,_XER(r1) - li r0,0 - - REST_4GPRS(7, r1) - REST_2GPRS(11, r1) - REST_GPR(13, r1) - - mtcr r3 - mtlr r4 - mtctr r5 - mtspr SPRN_XER,r6 - - REST_4GPRS(2, r1) - REST_GPR(6, r1) - REST_GPR(0, r1) - REST_GPR(1, r1) - RFI_TO_USER - b . /* prevent speculative execution */ - -.Lrestore_nvgprs: - REST_NVGPRS(r1) - b .Lfast_user_interrupt_return - - .balign IFETCH_ALIGN_BYTES -.Lkernel_interrupt_return: - addi r3,r1,STACK_FRAME_OVERHEAD - bl interrupt_exit_kernel_prepare - -.Lfast_kernel_interrupt_return: - cmpdi cr1,r3,0 - ld r11,_NIP(r1) - ld r12,_MSR(r1) - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r12 - -BEGIN_FTR_SECTION - stdcx. r0,0,r1 /* to clear the reservation */ -FTR_SECTION_ELSE - ldarx r0,0,r1 -ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) - - ld r3,_LINK(r1) - ld r4,_CTR(r1) - ld r5,_XER(r1) - ld r6,_CCR(r1) - li r0,0 - - REST_4GPRS(7, r1) - REST_2GPRS(11, r1) - - mtlr r3 - mtctr r4 - mtspr SPRN_XER,r5 - - /* - * Leaving a stale exception_marker on the stack can confuse - * the reliable stack unwinder later on. Clear it. - */ - std r0,STACK_FRAME_OVERHEAD-16(r1) - - REST_4GPRS(2, r1) - - bne- cr1,1f /* emulate stack store */ - mtcr r6 - REST_GPR(6, r1) - REST_GPR(0, r1) - REST_GPR(1, r1) - RFI_TO_KERNEL - b . /* prevent speculative execution */ - -1: /* - * Emulate stack store with update. New r1 value was already calculated - * and updated in our interrupt regs by emulate_loadstore, but we can't - * store the previous value of r1 to the stack before re-loading our - * registers from it, otherwise they could be clobbered. Use - * PACA_EXGEN as temporary storage to hold the store data, as - * interrupts are disabled here so it won't be clobbered. - */ - mtcr r6 - std r9,PACA_EXGEN+0(r13) - addi r9,r1,INT_FRAME_SIZE /* get original r1 */ - REST_GPR(6, r1) - REST_GPR(0, r1) - REST_GPR(1, r1) - std r9,0(r1) /* perform store component of stdu */ - ld r9,PACA_EXGEN+0(r13) - - RFI_TO_KERNEL - b . /* prevent speculative execution */ - #ifdef CONFIG_PPC_RTAS /* * On CHRP, the Run-Time Abstraction Services (RTAS) have to be diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c index 2ed14d4a47f5..93b0f3ec8fb0 100644 --- a/arch/powerpc/kernel/epapr_paravirt.c +++ b/arch/powerpc/kernel/epapr_paravirt.c @@ -38,9 +38,9 @@ static int __init early_init_dt_scan_epapr(unsigned long node, for (i = 0; i < (len / 4); i++) { struct ppc_inst inst = ppc_inst(be32_to_cpu(insts[i])); - patch_instruction((struct ppc_inst *)(epapr_hypercall_start + i), inst); + patch_instruction(epapr_hypercall_start + i, inst); #if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64) - patch_instruction((struct ppc_inst *)(epapr_ev_idle_start + i), inst); + patch_instruction(epapr_ev_idle_start + i, inst); #endif } diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index f1ae710274bc..1401787b0b93 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -26,6 +26,10 @@ #include #include +/* 64e interrupt returns always use SRR registers */ +#define fast_interrupt_return fast_interrupt_return_srr +#define interrupt_return interrupt_return_srr + /* XXX This will ultimately add space for a special exception save * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... * when taking special interrupts. For now we don't support that, @@ -897,6 +901,34 @@ kernel_dbg_exc: bl unknown_exception b interrupt_return +.macro SEARCH_RESTART_TABLE +#ifdef CONFIG_RELOCATABLE + ld r11,PACATOC(r13) + ld r14,__start___restart_table@got(r11) + ld r15,__stop___restart_table@got(r11) +#else + LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table) + LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table) +#endif +300: + cmpd r14,r15 + beq 302f + ld r11,0(r14) + cmpld r10,r11 + blt 301f + ld r11,8(r14) + cmpld r10,r11 + bge 301f + ld r11,16(r14) + b 303f +301: + addi r14,r14,24 + b 300b +302: + li r11,0 +303: +.endm + /* * An interrupt came in while soft-disabled; We mark paca->irq_happened * accordingly and if the interrupt is level sensitive, we hard disable @@ -905,6 +937,9 @@ kernel_dbg_exc: */ .macro masked_interrupt_book3e paca_irq full_mask + std r14,PACA_EXGEN+EX_R14(r13) + std r15,PACA_EXGEN+EX_R15(r13) + lbz r10,PACAIRQHAPPENED(r13) .if \full_mask == 1 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS @@ -914,15 +949,23 @@ kernel_dbg_exc: stb r10,PACAIRQHAPPENED(r13) .if \full_mask == 1 - rldicl r10,r11,48,1 /* clear MSR_EE */ - rotldi r11,r10,16 + xori r11,r11,MSR_EE /* clear MSR_EE */ mtspr SPRN_SRR1,r11 .endif + mfspr r10,SPRN_SRR0 + SEARCH_RESTART_TABLE + cmpdi r11,0 + beq 1f + mtspr SPRN_SRR0,r11 /* return to restart address */ +1: + lwz r11,PACA_EXGEN+EX_CR(r13) mtcr r11 ld r10,PACA_EXGEN+EX_R10(r13) ld r11,PACA_EXGEN+EX_R11(r13) + ld r14,PACA_EXGEN+EX_R14(r13) + ld r15,PACA_EXGEN+EX_R15(r13) mfspr r13,SPRN_SPRG_GEN_SCRATCH rfi b . @@ -1282,7 +1325,12 @@ a2_tlbinit_code_start: a2_tlbinit_after_linear_map: /* Now we branch the new virtual address mapped by this entry */ +#ifdef CONFIG_RELOCATABLE + ld r5,PACATOC(r13) + ld r3,1f@got(r5) +#else LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f) +#endif mtctr r3 bctr diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index f7fc6e078d4e..4aec59a77d4c 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -428,18 +428,31 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) /* If coming from user, skip soft-mask tests. */ andi. r10,r12,MSR_PR - bne 2f + bne 3f - /* Kernel code running below __end_interrupts is implicitly - * soft-masked */ - LOAD_HANDLER(r10, __end_interrupts) + /* + * Kernel code running below __end_soft_masked may be + * implicitly soft-masked if it is within the regions + * in the soft mask table. + */ + LOAD_HANDLER(r10, __end_soft_masked) cmpld r11,r10 + bge+ 1f + + /* SEARCH_SOFT_MASK_TABLE clobbers r9,r10,r12 */ + mtctr r12 + stw r9,PACA_EXGEN+EX_CCR(r13) + SEARCH_SOFT_MASK_TABLE + cmpdi r12,0 + mfctr r12 /* Restore r12 to SRR1 */ + lwz r9,PACA_EXGEN+EX_CCR(r13) + beq 1f /* Not in soft-mask table */ li r10,IMASK - blt- 1f + b 2f /* In soft-mask table, always mask */ /* Test the soft mask state against our interrupt's bit */ - lbz r10,PACAIRQSOFTMASK(r13) -1: andi. r10,r10,IMASK +1: lbz r10,PACAIRQSOFTMASK(r13) +2: andi. r10,r10,IMASK /* Associate vector numbers with bits in paca->irq_happened */ .if IVEC == 0x500 || IVEC == 0xea0 li r10,PACA_IRQ_EE @@ -470,7 +483,7 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) .if ISTACK andi. r10,r12,MSR_PR /* See if coming from user */ -2: mr r10,r1 /* Save r1 */ +3: mr r10,r1 /* Save r1 */ subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */ beq- 100f ld r1,PACAKSAVE(r13) /* kernel stack to use */ @@ -485,6 +498,20 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) std r0,GPR0(r1) /* save r0 in stackframe */ std r10,GPR1(r1) /* save r1 in stackframe */ + /* Mark our [H]SRRs valid for return */ + li r10,1 + .if IHSRR_IF_HVMODE + BEGIN_FTR_SECTION + stb r10,PACAHSRR_VALID(r13) + FTR_SECTION_ELSE + stb r10,PACASRR_VALID(r13) + ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) + .elseif IHSRR + stb r10,PACAHSRR_VALID(r13) + .else + stb r10,PACASRR_VALID(r13) + .endif + .if ISET_RI li r10,MSR_RI mtmsrd r10,1 /* Set MSR_RI */ @@ -577,6 +604,66 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR) __GEN_COMMON_BODY \name .endm +.macro SEARCH_RESTART_TABLE +#ifdef CONFIG_RELOCATABLE + mr r12,r2 + ld r2,PACATOC(r13) + LOAD_REG_ADDR(r9, __start___restart_table) + LOAD_REG_ADDR(r10, __stop___restart_table) + mr r2,r12 +#else + LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___restart_table) + LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___restart_table) +#endif +300: + cmpd r9,r10 + beq 302f + ld r12,0(r9) + cmpld r11,r12 + blt 301f + ld r12,8(r9) + cmpld r11,r12 + bge 301f + ld r12,16(r9) + b 303f +301: + addi r9,r9,24 + b 300b +302: + li r12,0 +303: +.endm + +.macro SEARCH_SOFT_MASK_TABLE +#ifdef CONFIG_RELOCATABLE + mr r12,r2 + ld r2,PACATOC(r13) + LOAD_REG_ADDR(r9, __start___soft_mask_table) + LOAD_REG_ADDR(r10, __stop___soft_mask_table) + mr r2,r12 +#else + LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___soft_mask_table) + LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___soft_mask_table) +#endif +300: + cmpd r9,r10 + beq 302f + ld r12,0(r9) + cmpld r11,r12 + blt 301f + ld r12,8(r9) + cmpld r11,r12 + bge 301f + li r12,1 + b 303f +301: + addi r9,r9,16 + b 300b +302: + li r12,0 +303: +.endm + /* * Restore all registers including H/SRR0/1 saved in a stack frame of a * standard exception. @@ -584,10 +671,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR) .macro EXCEPTION_RESTORE_REGS hsrr=0 /* Move original SRR0 and SRR1 into the respective regs */ ld r9,_MSR(r1) + li r10,0 .if \hsrr mtspr SPRN_HSRR1,r9 + stb r10,PACAHSRR_VALID(r13) .else mtspr SPRN_SRR1,r9 + stb r10,PACASRR_VALID(r13) .endif ld r9,_NIP(r1) .if \hsrr @@ -704,17 +794,17 @@ __start_interrupts: * scv instructions enter the kernel without changing EE, RI, ME, or HV. * In particular, this means we can take a maskable interrupt at any point * in the scv handler, which is unlike any other interrupt. This is solved - * by treating the instruction addresses below __end_interrupts as being - * soft-masked. + * by treating the instruction addresses in the handler as being soft-masked, + * by adding a SOFT_MASK_TABLE entry for them. * * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and * ensure scv is never executed with relocation off, which means AIL-0 * should never happen. * - * Before leaving the below __end_interrupts text, at least of the following - * must be true: + * Before leaving the following inside-__end_soft_masked text, at least of the + * following must be true: * - MSR[PR]=1 (i.e., return to userspace) - * - MSR_EE|MSR_RI is set (no reentrant exceptions) + * - MSR_EE|MSR_RI is clear (no reentrant exceptions) * - Standard kernel environment is set up (stack, paca, etc) * * Call convention: @@ -722,6 +812,7 @@ __start_interrupts: * syscall register convention is in Documentation/powerpc/syscall64-abi.rst */ EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000) +1: /* SCV 0 */ mr r9,r13 GET_PACA(r13) @@ -751,8 +842,11 @@ EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000) b system_call_vectored_sigill #endif .endr +2: EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000) +SOFT_MASK_TABLE(1b, 2b) // Treat scv vectors as soft-masked, see comment above. + #ifdef CONFIG_RELOCATABLE TRAMP_VIRT_BEGIN(system_call_vectored_tramp) __LOAD_HANDLER(r10, system_call_vectored_common) @@ -1149,7 +1243,7 @@ EXC_COMMON_BEGIN(machine_check_common) mtmsrd r10,1 addi r3,r1,STACK_FRAME_OVERHEAD bl machine_check_exception - b interrupt_return + b interrupt_return_srr #ifdef CONFIG_PPC_P7_NAP @@ -1275,7 +1369,7 @@ BEGIN_MMU_FTR_SECTION MMU_FTR_SECTION_ELSE bl do_page_fault ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) - b interrupt_return + b interrupt_return_srr 1: bl do_break /* @@ -1283,7 +1377,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) * If so, we need to restore them with their updated values. */ REST_NVGPRS(r1) - b interrupt_return + b interrupt_return_srr /** @@ -1323,7 +1417,7 @@ BEGIN_MMU_FTR_SECTION bl do_slb_fault cmpdi r3,0 bne- 1f - b fast_interrupt_return + b fast_interrupt_return_srr 1: /* Error case */ MMU_FTR_SECTION_ELSE /* Radix case, access is outside page table range */ @@ -1332,7 +1426,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) std r3,RESULT(r1) addi r3,r1,STACK_FRAME_OVERHEAD bl do_bad_slb_fault - b interrupt_return + b interrupt_return_srr /** @@ -1368,7 +1462,7 @@ BEGIN_MMU_FTR_SECTION MMU_FTR_SECTION_ELSE bl do_page_fault ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) - b interrupt_return + b interrupt_return_srr /** @@ -1403,7 +1497,7 @@ BEGIN_MMU_FTR_SECTION bl do_slb_fault cmpdi r3,0 bne- 1f - b fast_interrupt_return + b fast_interrupt_return_srr 1: /* Error case */ MMU_FTR_SECTION_ELSE /* Radix case, access is outside page table range */ @@ -1412,7 +1506,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) std r3,RESULT(r1) addi r3,r1,STACK_FRAME_OVERHEAD bl do_bad_slb_fault - b interrupt_return + b interrupt_return_srr /** @@ -1456,7 +1550,11 @@ EXC_COMMON_BEGIN(hardware_interrupt_common) GEN_COMMON hardware_interrupt addi r3,r1,STACK_FRAME_OVERHEAD bl do_IRQ - b interrupt_return + BEGIN_FTR_SECTION + b interrupt_return_hsrr + FTR_SECTION_ELSE + b interrupt_return_srr + ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) /** @@ -1483,7 +1581,7 @@ EXC_COMMON_BEGIN(alignment_common) addi r3,r1,STACK_FRAME_OVERHEAD bl alignment_exception REST_NVGPRS(r1) /* instruction emulation may change GPRs */ - b interrupt_return + b interrupt_return_srr /** @@ -1590,7 +1688,7 @@ EXC_COMMON_BEGIN(program_check_common) addi r3,r1,STACK_FRAME_OVERHEAD bl program_check_exception REST_NVGPRS(r1) /* instruction emulation may change GPRs */ - b interrupt_return + b interrupt_return_srr /* @@ -1633,12 +1731,12 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif bl load_up_fpu - b fast_interrupt_return + b fast_interrupt_return_srr #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2: /* User process was in a transaction */ addi r3,r1,STACK_FRAME_OVERHEAD bl fp_unavailable_tm - b interrupt_return + b interrupt_return_srr #endif @@ -1677,7 +1775,7 @@ EXC_COMMON_BEGIN(decrementer_common) GEN_COMMON decrementer addi r3,r1,STACK_FRAME_OVERHEAD bl timer_interrupt - b interrupt_return + b interrupt_return_srr /** @@ -1714,6 +1812,8 @@ EXC_COMMON_BEGIN(hdecrementer_common) * * Be careful to avoid touching the kernel stack. */ + li r10,0 + stb r10,PACAHSRR_VALID(r13) ld r10,PACA_EXGEN+EX_CTR(r13) mtctr r10 mtcrf 0x80,r9 @@ -1761,7 +1861,7 @@ EXC_COMMON_BEGIN(doorbell_super_common) #else bl unknown_async_exception #endif - b interrupt_return + b interrupt_return_srr EXC_REAL_NONE(0xb00, 0x100) @@ -1838,8 +1938,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) mtctr r10 bctr .else - li r10,MSR_RI - mtmsrd r10,1 /* Set RI (EE=0) */ #ifdef CONFIG_RELOCATABLE __LOAD_HANDLER(r10, system_call_common) mtctr r10 @@ -1925,7 +2023,7 @@ EXC_COMMON_BEGIN(single_step_common) GEN_COMMON single_step addi r3,r1,STACK_FRAME_OVERHEAD bl single_step_exception - b interrupt_return + b interrupt_return_srr /** @@ -1963,7 +2061,7 @@ BEGIN_MMU_FTR_SECTION MMU_FTR_SECTION_ELSE bl unknown_exception ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) - b interrupt_return + b interrupt_return_hsrr /** @@ -1988,7 +2086,7 @@ EXC_COMMON_BEGIN(h_instr_storage_common) GEN_COMMON h_instr_storage addi r3,r1,STACK_FRAME_OVERHEAD bl unknown_exception - b interrupt_return + b interrupt_return_hsrr /** @@ -2012,7 +2110,7 @@ EXC_COMMON_BEGIN(emulation_assist_common) addi r3,r1,STACK_FRAME_OVERHEAD bl emulation_assist_interrupt REST_NVGPRS(r1) /* instruction emulation may change GPRs */ - b interrupt_return + b interrupt_return_hsrr /** @@ -2089,7 +2187,7 @@ EXC_COMMON_BEGIN(hmi_exception_common) GEN_COMMON hmi_exception addi r3,r1,STACK_FRAME_OVERHEAD bl handle_hmi_exception - b interrupt_return + b interrupt_return_hsrr /** @@ -2119,7 +2217,7 @@ EXC_COMMON_BEGIN(h_doorbell_common) #else bl unknown_async_exception #endif - b interrupt_return + b interrupt_return_hsrr /** @@ -2145,7 +2243,7 @@ EXC_COMMON_BEGIN(h_virt_irq_common) GEN_COMMON h_virt_irq addi r3,r1,STACK_FRAME_OVERHEAD bl do_IRQ - b interrupt_return + b interrupt_return_hsrr EXC_REAL_NONE(0xec0, 0x20) @@ -2188,7 +2286,7 @@ EXC_COMMON_BEGIN(performance_monitor_common) GEN_COMMON performance_monitor addi r3,r1,STACK_FRAME_OVERHEAD bl performance_monitor_exception - b interrupt_return + b interrupt_return_srr /** @@ -2225,19 +2323,19 @@ BEGIN_FTR_SECTION END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) #endif bl load_up_altivec - b fast_interrupt_return + b fast_interrupt_return_srr #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2: /* User process was in a transaction */ addi r3,r1,STACK_FRAME_OVERHEAD bl altivec_unavailable_tm - b interrupt_return + b interrupt_return_srr #endif 1: END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif addi r3,r1,STACK_FRAME_OVERHEAD bl altivec_unavailable_exception - b interrupt_return + b interrupt_return_srr /** @@ -2278,14 +2376,14 @@ BEGIN_FTR_SECTION 2: /* User process was in a transaction */ addi r3,r1,STACK_FRAME_OVERHEAD bl vsx_unavailable_tm - b interrupt_return + b interrupt_return_srr #endif 1: END_FTR_SECTION_IFSET(CPU_FTR_VSX) #endif addi r3,r1,STACK_FRAME_OVERHEAD bl vsx_unavailable_exception - b interrupt_return + b interrupt_return_srr /** @@ -2313,7 +2411,7 @@ EXC_COMMON_BEGIN(facility_unavailable_common) addi r3,r1,STACK_FRAME_OVERHEAD bl facility_unavailable_exception REST_NVGPRS(r1) /* instruction emulation may change GPRs */ - b interrupt_return + b interrupt_return_srr /** @@ -2341,7 +2439,7 @@ EXC_COMMON_BEGIN(h_facility_unavailable_common) addi r3,r1,STACK_FRAME_OVERHEAD bl facility_unavailable_exception REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */ - b interrupt_return + b interrupt_return_hsrr EXC_REAL_NONE(0xfa0, 0x20) @@ -2370,7 +2468,7 @@ EXC_COMMON_BEGIN(cbe_system_error_common) GEN_COMMON cbe_system_error addi r3,r1,STACK_FRAME_OVERHEAD bl cbe_system_error_exception - b interrupt_return + b interrupt_return_hsrr #else /* CONFIG_CBE_RAS */ EXC_REAL_NONE(0x1200, 0x100) @@ -2401,7 +2499,7 @@ EXC_COMMON_BEGIN(instruction_breakpoint_common) GEN_COMMON instruction_breakpoint addi r3,r1,STACK_FRAME_OVERHEAD bl instruction_breakpoint_exception - b interrupt_return + b interrupt_return_srr EXC_REAL_NONE(0x1400, 0x100) @@ -2509,6 +2607,8 @@ BEGIN_FTR_SECTION ld r10,PACA_EXGEN+EX_CFAR(r13) mtspr SPRN_CFAR,r10 END_FTR_SECTION_IFSET(CPU_FTR_CFAR) + li r10,0 + stb r10,PACAHSRR_VALID(r13) ld r10,PACA_EXGEN+EX_R10(r13) ld r11,PACA_EXGEN+EX_R11(r13) ld r12,PACA_EXGEN+EX_R12(r13) @@ -2521,7 +2621,7 @@ EXC_COMMON_BEGIN(denorm_exception_common) GEN_COMMON denorm_exception addi r3,r1,STACK_FRAME_OVERHEAD bl unknown_exception - b interrupt_return + b interrupt_return_hsrr #ifdef CONFIG_CBE_RAS @@ -2538,7 +2638,7 @@ EXC_COMMON_BEGIN(cbe_maintenance_common) GEN_COMMON cbe_maintenance addi r3,r1,STACK_FRAME_OVERHEAD bl cbe_maintenance_exception - b interrupt_return + b interrupt_return_hsrr #else /* CONFIG_CBE_RAS */ EXC_REAL_NONE(0x1600, 0x100) @@ -2568,7 +2668,7 @@ EXC_COMMON_BEGIN(altivec_assist_common) #else bl unknown_exception #endif - b interrupt_return + b interrupt_return_srr #ifdef CONFIG_CBE_RAS @@ -2585,7 +2685,7 @@ EXC_COMMON_BEGIN(cbe_thermal_common) GEN_COMMON cbe_thermal addi r3,r1,STACK_FRAME_OVERHEAD bl cbe_thermal_exception - b interrupt_return + b interrupt_return_hsrr #else /* CONFIG_CBE_RAS */ EXC_REAL_NONE(0x1800, 0x100) @@ -2610,7 +2710,6 @@ INT_DEFINE_END(soft_nmi) * and run it entirely with interrupts hard disabled. */ EXC_COMMON_BEGIN(soft_nmi_common) - mfspr r11,SPRN_SRR0 mr r10,r1 ld r1,PACAEMERGSP(r13) subi r1,r1,INT_FRAME_SIZE @@ -2624,6 +2723,7 @@ EXC_COMMON_BEGIN(soft_nmi_common) mtmsrd r9,1 kuap_kernel_restore r9, r10 + EXCEPTION_RESTORE_REGS hsrr=0 RFI_TO_KERNEL @@ -2645,19 +2745,24 @@ masked_Hinterrupt: .else masked_interrupt: .endif - lbz r11,PACAIRQHAPPENED(r13) - or r11,r11,r10 - stb r11,PACAIRQHAPPENED(r13) + stw r9,PACA_EXGEN+EX_CCR(r13) + lbz r9,PACAIRQHAPPENED(r13) + or r9,r9,r10 + stb r9,PACAIRQHAPPENED(r13) + + .if ! \hsrr cmpwi r10,PACA_IRQ_DEC bne 1f - lis r10,0x7fff - ori r10,r10,0xffff - mtspr SPRN_DEC,r10 + LOAD_REG_IMMEDIATE(r9, 0x7fffffff) + mtspr SPRN_DEC,r9 #ifdef CONFIG_PPC_WATCHDOG + lwz r9,PACA_EXGEN+EX_CCR(r13) b soft_nmi_common #else b 2f #endif + .endif + 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK beq 2f xori r12,r12,MSR_EE /* clear MSR_EE */ @@ -2666,11 +2771,29 @@ masked_interrupt: .else mtspr SPRN_SRR1,r12 .endif - ori r11,r11,PACA_IRQ_HARD_DIS - stb r11,PACAIRQHAPPENED(r13) + ori r9,r9,PACA_IRQ_HARD_DIS + stb r9,PACAIRQHAPPENED(r13) 2: /* done */ - ld r10,PACA_EXGEN+EX_CTR(r13) - mtctr r10 + li r9,0 + .if \hsrr + stb r9,PACAHSRR_VALID(r13) + .else + stb r9,PACASRR_VALID(r13) + .endif + + SEARCH_RESTART_TABLE + cmpdi r12,0 + beq 3f + .if \hsrr + mtspr SPRN_HSRR0,r12 + .else + mtspr SPRN_SRR0,r12 + .endif +3: + + ld r9,PACA_EXGEN+EX_CTR(r13) + mtctr r9 + lwz r9,PACA_EXGEN+EX_CCR(r13) mtcrf 0x80,r9 std r1,PACAR1(r13) ld r9,PACA_EXGEN+EX_R9(r13) @@ -2881,7 +3004,7 @@ MASKED_INTERRUPT hsrr=1 USE_FIXED_SECTION(virt_trampolines) /* - * All code below __end_interrupts is treated as soft-masked. If + * All code below __end_soft_masked is treated as soft-masked. If * any code runs here with MSR[EE]=1, it must then cope with pending * soft interrupt being raised (i.e., by ensuring it is replayed). * diff --git a/arch/powerpc/kernel/firmware.c b/arch/powerpc/kernel/firmware.c index c9e2819b095a..c7022c41cc31 100644 --- a/arch/powerpc/kernel/firmware.c +++ b/arch/powerpc/kernel/firmware.c @@ -23,18 +23,20 @@ EXPORT_SYMBOL_GPL(powerpc_firmware_features); #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_KVM_GUEST) DEFINE_STATIC_KEY_FALSE(kvm_guest); -bool check_kvm_guest(void) +int __init check_kvm_guest(void) { struct device_node *hyper_node; hyper_node = of_find_node_by_path("/hypervisor"); if (!hyper_node) - return false; + return 0; if (!of_device_is_compatible(hyper_node, "linux,kvm")) - return false; + return 0; static_branch_enable(&kvm_guest); - return true; + + return 0; } +core_initcall(check_kvm_guest); // before kvm_guest_init() #endif diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 2c57ece6671c..6010adcee16e 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -103,6 +103,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX) ori r12,r12,MSR_FP or r12,r12,r4 std r12,_MSR(r1) +#ifdef CONFIG_PPC_BOOK3S_64 + li r4,0 + stb r4,PACASRR_VALID(r13) +#endif #endif li r4,1 stb r4,THREAD_LOAD_FP(r5) diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h index a8221ddcbd66..6b1ec9e3541b 100644 --- a/arch/powerpc/kernel/head_32.h +++ b/arch/powerpc/kernel/head_32.h @@ -142,42 +142,23 @@ _ASM_NOKPROBE_SYMBOL(\name\()_virt) .macro SYSCALL_ENTRY trapno mfspr r9, SPRN_SRR1 - mfspr r10, SPRN_SRR0 + mfspr r12, SPRN_SRR0 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL) /* can take exceptions */ - lis r12, 1f@h - ori r12, r12, 1f@l + lis r10, 1f@h + ori r10, r10, 1f@l mtspr SPRN_SRR1, r11 - mtspr SPRN_SRR0, r12 - mfspr r12,SPRN_SPRG_THREAD + mtspr SPRN_SRR0, r10 + mfspr r10,SPRN_SPRG_THREAD mr r11, r1 - lwz r1,TASK_STACK-THREAD(r12) - tovirt(r12, r12) + lwz r1,TASK_STACK-THREAD(r10) + tovirt(r10, r10) addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE rfi 1: - stw r11,GPR1(r1) - stw r11,0(r1) - mr r11, r1 - stw r10,_NIP(r11) - mflr r10 - stw r10, _LINK(r11) - mfcr r10 - rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */ - stw r10,_CCR(r11) /* save registers */ -#ifdef CONFIG_40x - rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ -#endif - lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ - stw r2,GPR2(r11) - addi r10,r10,STACK_FRAME_REGS_MARKER@l - stw r9,_MSR(r11) - li r2, \trapno - stw r10,8(r11) - stw r2,_TRAP(r11) - SAVE_GPR(0, r11) - SAVE_4GPRS(3, r11) - SAVE_2GPRS(7, r11) - addi r2,r12,-THREAD + stw r12,_NIP(r1) + mfcr r12 + rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */ + stw r12,_CCR(r1) b transfer_to_syscall /* jump to handler */ .endm diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S index e1360b88b6cb..7d72ee5ab387 100644 --- a/arch/powerpc/kernel/head_40x.S +++ b/arch/powerpc/kernel/head_40x.S @@ -701,39 +701,3 @@ _GLOBAL(abort) mfspr r13,SPRN_DBCR0 oris r13,r13,DBCR0_RST_SYSTEM@h mtspr SPRN_DBCR0,r13 - -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, abatron_pteptrs@ha - stw r4, abatron_pteptrs@l + 0x4(r5) -#endif - sync - mtspr SPRN_PID,r3 - isync /* Need an isync to flush shadow */ - /* TLBs after changing PID */ - blr - -/* We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align 12 - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 -EXPORT_SYMBOL(empty_zero_page) - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - -/* Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 5c106ac36626..ddc978a2d381 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -532,6 +532,10 @@ finish_tlb_load_44x: andi. r10,r12,_PAGE_USER /* User page ? */ beq 1f /* nope, leave U bits empty */ rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ +#ifdef CONFIG_PPC_KUEP +0: rlwinm r11,r11,0,~PPC44x_TLB_SX /* Clear SX if User page */ + patch_site 0b, patch__tlb_44x_kuep +#endif 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ /* Done...restore registers and get out of here. @@ -743,6 +747,10 @@ finish_tlb_load_47x: andi. r10,r12,_PAGE_USER /* User page ? */ beq 1f /* nope, leave U bits empty */ rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ +#ifdef CONFIG_PPC_KUEP +0: rlwinm r11,r11,0,~PPC47x_TLB2_SX /* Clear SX if User page */ + patch_site 0b, patch__tlb_47x_kuep +#endif 1: tlbwe r11,r13,2 /* Done...restore registers and get out of here. @@ -780,20 +788,6 @@ _GLOBAL(__fixup_440A_mcheck) sync blr -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r4, 0x4(r5) -#endif - mtspr SPRN_PID,r3 - isync /* Force context change */ - blr - /* * Init CPU state. This is called at boot time or for secondary CPUs * to setup initial TLB entries, setup IVORs, etc... @@ -1239,34 +1233,8 @@ head_start_common: isync blr -/* - * We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align PAGE_SHIFT - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space PAGE_SIZE -EXPORT_SYMBOL(empty_zero_page) - -/* - * To support >32-bit physical addresses, we use an 8KB pgdir. - */ - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - -/* - * Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 - #ifdef CONFIG_SMP + .data .align 12 temp_boot_stack: .space 1024 diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index ece7f97bafff..79930b0bc781 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -194,8 +194,9 @@ CLOSE_FIXED_SECTION(first_256B) /* This value is used to mark exception frames on the stack. */ .section ".toc","aw" +/* This value is used to mark exception frames on the stack. */ exception_marker: - .tc ID_72656773_68657265[TC],0x7265677368657265 + .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER .previous /* @@ -211,6 +212,8 @@ OPEN_TEXT_SECTION(0x100) USE_TEXT_SECTION() +#include "interrupt_64.S" + #ifdef CONFIG_PPC_BOOK3E /* * The booting_thread_hwid holds the thread id we want to boot in cpu @@ -997,23 +1000,3 @@ start_here_common: 0: trap EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 .previous - -/* - * We put a few things here that have to be page-aligned. - * This stuff goes at the beginning of the bss, which is page-aligned. - */ - .section ".bss" -/* - * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. - * We will need to find a better way to fix this - */ - .align 16 - - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - - .globl empty_zero_page -empty_zero_page: - .space PAGE_SIZE -EXPORT_SYMBOL(empty_zero_page) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 7d445e4342c0..9bdb95f5694f 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -786,28 +786,3 @@ _GLOBAL(mmu_pin_tlb) mtspr SPRN_SRR1, r10 mtspr SPRN_SRR0, r11 rfi - -/* - * We put a few things here that have to be page-aligned. - * This stuff goes at the beginning of the data segment, - * which is page-aligned. - */ - .data - .globl sdata -sdata: - .globl empty_zero_page - .align PAGE_SHIFT -empty_zero_page: - .space PAGE_SIZE -EXPORT_SYMBOL(empty_zero_page) - - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - -/* Room for two PTE table pointers, usually the kernel and current user - * pointer to their respective root page table (pgdir). - */ - .globl abatron_pteptrs -abatron_pteptrs: - .space 8 diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/head_book3s_32.S index 065178f19a3d..764edd860ed4 100644 --- a/arch/powerpc/kernel/head_book3s_32.S +++ b/arch/powerpc/kernel/head_book3s_32.S @@ -518,8 +518,6 @@ BEGIN_FTR_SECTION rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 - mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r2 BEGIN_MMU_FTR_SECTION li r0,1 mfspr r1,SPRN_SPRG_603_LRU @@ -531,9 +529,15 @@ BEGIN_MMU_FTR_SECTION mfspr r2,SPRN_SRR1 rlwimi r2,r0,31-14,14,14 mtspr SPRN_SRR1,r2 -END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) + mtcrf 0x80,r2 tlbld r3 rfi +MMU_FTR_SECTION_ELSE + mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r2 + tlbld r3 + rfi +ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) DataAddressInvalid: mfspr r3,SPRN_SRR1 rlwinm r1,r3,9,6,6 /* Get load/store bit */ @@ -607,9 +611,15 @@ BEGIN_MMU_FTR_SECTION mfspr r2,SPRN_SRR1 rlwimi r2,r0,31-14,14,14 mtspr SPRN_SRR1,r2 -END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) + mtcrf 0x80,r2 tlbld r3 rfi +MMU_FTR_SECTION_ELSE + mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r2 + tlbld r3 + rfi +ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) #ifndef CONFIG_ALTIVEC #define altivec_assist_exception unknown_exception @@ -756,9 +766,6 @@ PerformanceMonitor: * the kernel image to physical address PHYSICAL_START. */ relocate_kernel: - addis r9,r26,klimit@ha /* fetch klimit */ - lwz r25,klimit@l(r9) - addis r25,r25,-KERNELBASE@h lis r3,PHYSICAL_START@h /* Destination base address */ li r6,0 /* Destination offset */ li r5,0x4000 /* # bytes of memory to copy */ @@ -766,7 +773,8 @@ relocate_kernel: addi r0,r3,4f@l /* jump to the address of 4f */ mtctr r0 /* in copy and do the rest. */ bctr /* jump to the copy */ -4: mr r5,r25 +4: lis r5,_end-KERNELBASE@h + ori r5,r5,_end-KERNELBASE@l bl copy_and_flush /* copy the rest */ b turn_on_mmu @@ -924,12 +932,6 @@ _GLOBAL(load_segment_registers) li r0, NUM_USER_SEGMENTS /* load up user segment register values */ mtctr r0 /* for context 0 */ li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */ -#ifdef CONFIG_PPC_KUEP - oris r3, r3, SR_NX@h /* Set Nx */ -#endif -#ifdef CONFIG_PPC_KUAP - oris r3, r3, SR_KS@h /* Set Ks */ -#endif li r4, 0 3: mtsrin r3, r4 addi r3, r3, 0x111 /* increment VSID */ @@ -1023,58 +1025,6 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE) mtspr SPRN_SRR1,r4 rfi -/* - * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next); - * - * Set up the segment registers for a new context. - */ -_ENTRY(switch_mmu_context) - lwz r3,MMCONTEXTID(r4) - cmpwi cr0,r3,0 - blt- 4f - mulli r3,r3,897 /* multiply context by skew factor */ - rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ -#ifdef CONFIG_PPC_KUEP - oris r3, r3, SR_NX@h /* Set Nx */ -#endif -#ifdef CONFIG_PPC_KUAP - oris r3, r3, SR_KS@h /* Set Ks */ -#endif - li r0,NUM_USER_SEGMENTS - mtctr r0 - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is passed as second argument. - */ - lwz r4, MM_PGD(r4) - lis r5, abatron_pteptrs@ha - stw r4, abatron_pteptrs@l + 0x4(r5) -#endif -BEGIN_MMU_FTR_SECTION -#ifndef CONFIG_BDI_SWITCH - lwz r4, MM_PGD(r4) -#endif - tophys(r4, r4) - rlwinm r4, r4, 4, 0xffff01ff - mtspr SPRN_SDR1, r4 -END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE) - li r4,0 - isync -3: - mtsrin r3,r4 - addi r3,r3,0x111 /* next VSID */ - rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ - addis r4,r4,0x1000 /* address of next segment */ - bdnz 3b - sync - isync - blr -4: trap - EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0 - blr -EXPORT_SYMBOL(switch_mmu_context) - /* * An undocumented "feature" of 604e requires that the v bit * be cleared before changing BAT values. @@ -1256,61 +1206,4 @@ setup_usbgecko_bat: blr #endif -#ifdef CONFIG_8260 -/* Jump into the system reset for the rom. - * We first disable the MMU, and then jump to the ROM reset address. - * - * r3 is the board info structure, r4 is the location for starting. - * I use this for building a small kernel that can load other kernels, - * rather than trying to write or rely on a rom monitor that can tftp load. - */ - .globl m8260_gorom -m8260_gorom: - mfmsr r0 - rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ - sync - mtmsr r0 - sync - mfspr r11, SPRN_HID0 - lis r10, 0 - ori r10,r10,HID0_ICE|HID0_DCE - andc r11, r11, r10 - mtspr SPRN_HID0, r11 - isync - li r5, MSR_ME|MSR_RI - lis r6,2f@h - addis r6,r6,-KERNELBASE@h - ori r6,r6,2f@l - mtspr SPRN_SRR0,r6 - mtspr SPRN_SRR1,r5 - isync - sync - rfi -2: - mtlr r4 - blr -#endif - - -/* - * We put a few things here that have to be page-aligned. - * This stuff goes at the beginning of the data segment, - * which is page-aligned. - */ .data - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 -EXPORT_SYMBOL(empty_zero_page) - - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - -/* Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index f82470091697..87b806e8eded 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -128,37 +128,20 @@ BEGIN_FTR_SECTION mr r12, r13 lwz r13, THREAD_NORMSAVE(2)(r10) FTR_SECTION_ELSE -#endif mfcr r12 -#ifdef CONFIG_KVM_BOOKE_HV ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) +#else + mfcr r12 #endif mfspr r9, SPRN_SRR1 BOOKE_CLEAR_BTB(r11) - lwz r11, TASK_STACK - THREAD(r10) + mr r11, r1 + lwz r1, TASK_STACK - THREAD(r10) rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */ - ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE) - stw r12, _CCR(r11) /* save various registers */ - mflr r12 - stw r12,_LINK(r11) + ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE) + stw r12, _CCR(r1) mfspr r12,SPRN_SRR0 - stw r1, GPR1(r11) - stw r1, 0(r11) - mr r1, r11 - stw r12,_NIP(r11) - rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ - lis r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ - stw r2,GPR2(r11) - addi r12, r12, STACK_FRAME_REGS_MARKER@l - stw r9,_MSR(r11) - li r2, \trapno - stw r12, 8(r11) - stw r2,_TRAP(r11) - SAVE_GPR(0, r11) - SAVE_4GPRS(3, r11) - SAVE_2GPRS(7, r11) - - addi r2,r10,-THREAD + stw r12,_NIP(r1) b transfer_to_syscall /* jump to handler */ .endm diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index a1a5c3f10dc4..0f9642f36b49 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -985,20 +985,6 @@ _GLOBAL(abort) mtspr SPRN_DBCR0,r13 isync -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r4, 0x4(r5) -#endif - mtspr SPRN_PID,r3 - isync /* Force context change */ - blr - #ifdef CONFIG_SMP /* When we get here, r24 needs to hold the CPU # */ .globl __secondary_start @@ -1226,26 +1212,3 @@ _GLOBAL(restore_to_as0) */ 3: mr r3,r5 bl _start - -/* - * We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align 12 - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 -EXPORT_SYMBOL(empty_zero_page) - .globl swapper_pg_dir -swapper_pg_dir: - .space PGD_TABLE_SIZE - -/* - * Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 8fc7a14e4d71..21a638aff72f 100644 --- a/arch/powerpc/kernel/hw_breakpoint.c +++ b/arch/powerpc/kernel/hw_breakpoint.c @@ -486,7 +486,7 @@ void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs) return; reset: - regs->msr &= ~MSR_SE; + regs_set_return_msr(regs, regs->msr & ~MSR_SE); for (i = 0; i < nr_wp_slots(); i++) { info = counter_arch_bp(__this_cpu_read(bp_per_reg[i])); __set_breakpoint(i, info); @@ -537,7 +537,7 @@ static bool stepping_handler(struct pt_regs *regs, struct perf_event **bp, current->thread.last_hit_ubp[i] = bp[i]; info[i] = NULL; } - regs->msr |= MSR_SE; + regs_set_return_msr(regs, regs->msr | MSR_SE); return false; } diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c index e0938ba298f2..21bbd615ca41 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -3,6 +3,7 @@ #include #include #include +#include /* for show_regs */ #include #include @@ -26,6 +27,53 @@ unsigned long global_dbcr0[NR_CPUS]; typedef long (*syscall_fn)(long, long, long, long, long, long); +#ifdef CONFIG_PPC_BOOK3S_64 +DEFINE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); +static inline bool exit_must_hard_disable(void) +{ + return static_branch_unlikely(&interrupt_exit_not_reentrant); +} +#else +static inline bool exit_must_hard_disable(void) +{ + return true; +} +#endif + +/* + * local irqs must be disabled. Returns false if the caller must re-enable + * them, check for new work, and try again. + * + * This should be called with local irqs disabled, but if they were previously + * enabled when the interrupt handler returns (indicating a process-context / + * synchronous interrupt) then irqs_enabled should be true. + * + * restartable is true then EE/RI can be left on because interrupts are handled + * with a restart sequence. + */ +static notrace __always_inline bool prep_irq_for_enabled_exit(bool restartable) +{ + /* This must be done with RI=1 because tracing may touch vmaps */ + trace_hardirqs_on(); + + if (exit_must_hard_disable() || !restartable) + __hard_EE_RI_disable(); + +#ifdef CONFIG_PPC64 + /* This pattern matches prep_irq_for_idle */ + if (unlikely(lazy_irq_pending_nocheck())) { + if (exit_must_hard_disable() || !restartable) { + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; + __hard_RI_enable(); + } + trace_hardirqs_off(); + + return false; + } +#endif + return true; +} + /* Has to run notrace because it is entered not completely "reconciled" */ notrace long system_call_exception(long r3, long r4, long r5, long r6, long r7, long r8, @@ -144,71 +192,6 @@ notrace long system_call_exception(long r3, long r4, long r5, return f(r3, r4, r5, r6, r7, r8); } -/* - * local irqs must be disabled. Returns false if the caller must re-enable - * them, check for new work, and try again. - * - * This should be called with local irqs disabled, but if they were previously - * enabled when the interrupt handler returns (indicating a process-context / - * synchronous interrupt) then irqs_enabled should be true. - */ -static notrace __always_inline bool __prep_irq_for_enabled_exit(bool clear_ri) -{ - /* This must be done with RI=1 because tracing may touch vmaps */ - trace_hardirqs_on(); - - /* This pattern matches prep_irq_for_idle */ - if (clear_ri) - __hard_EE_RI_disable(); - else - __hard_irq_disable(); -#ifdef CONFIG_PPC64 - if (unlikely(lazy_irq_pending_nocheck())) { - /* Took an interrupt, may have more exit work to do. */ - if (clear_ri) - __hard_RI_enable(); - trace_hardirqs_off(); - local_paca->irq_happened |= PACA_IRQ_HARD_DIS; - - return false; - } - local_paca->irq_happened = 0; - irq_soft_mask_set(IRQS_ENABLED); -#endif - return true; -} - -static notrace inline bool prep_irq_for_enabled_exit(bool clear_ri, bool irqs_enabled) -{ - if (__prep_irq_for_enabled_exit(clear_ri)) - return true; - - /* - * Must replay pending soft-masked interrupts now. Don't just - * local_irq_enabe(); local_irq_disable(); because if we are - * returning from an asynchronous interrupt here, another one - * might hit after irqs are enabled, and it would exit via this - * same path allowing another to fire, and so on unbounded. - * - * If interrupts were enabled when this interrupt exited, - * indicating a process context (synchronous) interrupt, - * local_irq_enable/disable can be used, which will enable - * interrupts rather than keeping them masked (unclear how - * much benefit this is over just replaying for all cases, - * because we immediately disable again, so all we're really - * doing is allowing hard interrupts to execute directly for - * a very small time, rather than being masked and replayed). - */ - if (irqs_enabled) { - local_irq_enable(); - local_irq_disable(); - } else { - replay_soft_interrupts(); - } - - return false; -} - static notrace void booke_load_dbcr0(void) { #ifdef CONFIG_PPC_ADV_DEBUG_REGS @@ -231,6 +214,162 @@ static notrace void booke_load_dbcr0(void) #endif } +static void check_return_regs_valid(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + unsigned long trap, srr0, srr1; + static bool warned; + u8 *validp; + char *h; + + if (trap_is_scv(regs)) + return; + + trap = regs->trap; + // EE in HV mode sets HSRRs like 0xea0 + if (cpu_has_feature(CPU_FTR_HVMODE) && trap == INTERRUPT_EXTERNAL) + trap = 0xea0; + + switch (trap) { + case 0x980: + case INTERRUPT_H_DATA_STORAGE: + case 0xe20: + case 0xe40: + case INTERRUPT_HMI: + case 0xe80: + case 0xea0: + case INTERRUPT_H_FAC_UNAVAIL: + case 0x1200: + case 0x1500: + case 0x1600: + case 0x1800: + validp = &local_paca->hsrr_valid; + if (!*validp) + return; + + srr0 = mfspr(SPRN_HSRR0); + srr1 = mfspr(SPRN_HSRR1); + h = "H"; + + break; + default: + validp = &local_paca->srr_valid; + if (!*validp) + return; + + srr0 = mfspr(SPRN_SRR0); + srr1 = mfspr(SPRN_SRR1); + h = ""; + break; + } + + if (srr0 == regs->nip && srr1 == regs->msr) + return; + + /* + * A NMI / soft-NMI interrupt may have come in after we found + * srr_valid and before the SRRs are loaded. The interrupt then + * comes in and clobbers SRRs and clears srr_valid. Then we load + * the SRRs here and test them above and find they don't match. + * + * Test validity again after that, to catch such false positives. + * + * This test in general will have some window for false negatives + * and may not catch and fix all such cases if an NMI comes in + * later and clobbers SRRs without clearing srr_valid, but hopefully + * such things will get caught most of the time, statistically + * enough to be able to get a warning out. + */ + barrier(); + + if (!*validp) + return; + + if (!warned) { + warned = true; + printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); + printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); + show_regs(regs); + } + + *validp = 0; /* fixup */ +#endif +} + +static notrace unsigned long +interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs) +{ + unsigned long ti_flags; + +again: + ti_flags = READ_ONCE(current_thread_info()->flags); + while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) { + local_irq_enable(); + if (ti_flags & _TIF_NEED_RESCHED) { + schedule(); + } else { + /* + * SIGPENDING must restore signal handler function + * argument GPRs, and some non-volatiles (e.g., r1). + * Restore all for now. This could be made lighter. + */ + if (ti_flags & _TIF_SIGPENDING) + ret |= _TIF_RESTOREALL; + do_notify_resume(regs, ti_flags); + } + local_irq_disable(); + ti_flags = READ_ONCE(current_thread_info()->flags); + } + + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely((ti_flags & _TIF_RESTORE_TM))) { + restore_tm_state(regs); + } else { + unsigned long mathflags = MSR_FP; + + if (cpu_has_feature(CPU_FTR_VSX)) + mathflags |= MSR_VEC | MSR_VSX; + else if (cpu_has_feature(CPU_FTR_ALTIVEC)) + mathflags |= MSR_VEC; + + /* + * If userspace MSR has all available FP bits set, + * then they are live and no need to restore. If not, + * it means the regs were given up and restore_math + * may decide to restore them (to avoid taking an FP + * fault). + */ + if ((regs->msr & mathflags) != mathflags) + restore_math(regs); + } + } + + check_return_regs_valid(regs); + + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + local_paca->tm_scratch = regs->msr; +#endif + + booke_load_dbcr0(); + + account_cpu_user_exit(); + + /* Restore user access locks last */ + kuap_user_restore(regs); + kuep_unlock(); + + return ret; +} + /* * This should be called after a syscall returns, with r3 the return value * from the syscall. If this function returns non-zero, the system call @@ -282,81 +421,47 @@ notrace unsigned long syscall_exit_prepare(unsigned long r3, } local_irq_disable(); + ret = interrupt_exit_user_prepare_main(ret, regs); -again: - ti_flags = READ_ONCE(current_thread_info()->flags); - while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) { - local_irq_enable(); - if (ti_flags & _TIF_NEED_RESCHED) { - schedule(); - } else { - /* - * SIGPENDING must restore signal handler function - * argument GPRs, and some non-volatiles (e.g., r1). - * Restore all for now. This could be made lighter. - */ - if (ti_flags & _TIF_SIGPENDING) - ret |= _TIF_RESTOREALL; - do_notify_resume(regs, ti_flags); - } - local_irq_disable(); - ti_flags = READ_ONCE(current_thread_info()->flags); - } - - if (IS_ENABLED(CONFIG_PPC_BOOK3S) && IS_ENABLED(CONFIG_PPC_FPU)) { - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely((ti_flags & _TIF_RESTORE_TM))) { - restore_tm_state(regs); - } else { - unsigned long mathflags = MSR_FP; - - if (cpu_has_feature(CPU_FTR_VSX)) - mathflags |= MSR_VEC | MSR_VSX; - else if (cpu_has_feature(CPU_FTR_ALTIVEC)) - mathflags |= MSR_VEC; - - /* - * If userspace MSR has all available FP bits set, - * then they are live and no need to restore. If not, - * it means the regs were given up and restore_math - * may decide to restore them (to avoid taking an FP - * fault). - */ - if ((regs->msr & mathflags) != mathflags) - restore_math(regs); - } - } - - user_enter_irqoff(); - - /* scv need not set RI=0 because SRRs are not used */ - if (unlikely(!__prep_irq_for_enabled_exit(is_not_scv))) { - user_exit_irqoff(); - local_irq_enable(); - local_irq_disable(); - goto again; - } - -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - local_paca->tm_scratch = regs->msr; +#ifdef CONFIG_PPC64 + regs->exit_result = ret; #endif - booke_load_dbcr0(); - - account_cpu_user_exit(); - - /* Restore user access locks last */ - kuap_user_restore(regs); - kuep_unlock(); - return ret; } -notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned long msr) +#ifdef CONFIG_PPC64 +notrace unsigned long syscall_exit_restart(unsigned long r3, struct pt_regs *regs) { - unsigned long ti_flags; - unsigned long flags; - unsigned long ret = 0; + /* + * This is called when detecting a soft-pending interrupt as well as + * an alternate-return interrupt. So we can't just have the alternate + * return path clear SRR1[MSR] and set PACA_IRQ_HARD_DIS (unless + * the soft-pending case were to fix things up as well). RI might be + * disabled, in which case it gets re-enabled by __hard_irq_disable(). + */ + __hard_irq_disable(); + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; + +#ifdef CONFIG_PPC_BOOK3S_64 + set_kuap(AMR_KUAP_BLOCKED); +#endif + + trace_hardirqs_off(); + user_exit_irqoff(); + account_cpu_user_entry(); + + BUG_ON(!user_mode(regs)); + + regs->exit_result = interrupt_exit_user_prepare_main(regs->exit_result, regs); + + return regs->exit_result; +} +#endif + +notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs) +{ + unsigned long ret; if (!IS_ENABLED(CONFIG_BOOKE) && !IS_ENABLED(CONFIG_40x)) BUG_ON(!(regs->msr & MSR_RI)); @@ -370,72 +475,26 @@ notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned */ kuap_assert_locked(); - local_irq_save(flags); + local_irq_disable(); -again: - ti_flags = READ_ONCE(current_thread_info()->flags); - while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) { - local_irq_enable(); /* returning to user: may enable */ - if (ti_flags & _TIF_NEED_RESCHED) { - schedule(); - } else { - if (ti_flags & _TIF_SIGPENDING) - ret |= _TIF_RESTOREALL; - do_notify_resume(regs, ti_flags); - } - local_irq_disable(); - ti_flags = READ_ONCE(current_thread_info()->flags); - } + ret = interrupt_exit_user_prepare_main(0, regs); - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely((ti_flags & _TIF_RESTORE_TM))) { - restore_tm_state(regs); - } else { - unsigned long mathflags = MSR_FP; - - if (cpu_has_feature(CPU_FTR_VSX)) - mathflags |= MSR_VEC | MSR_VSX; - else if (cpu_has_feature(CPU_FTR_ALTIVEC)) - mathflags |= MSR_VEC; - - /* See above restore_math comment */ - if ((regs->msr & mathflags) != mathflags) - restore_math(regs); - } - } - - user_enter_irqoff(); - - if (unlikely(!__prep_irq_for_enabled_exit(true))) { - user_exit_irqoff(); - local_irq_enable(); - local_irq_disable(); - goto again; - } - - booke_load_dbcr0(); - -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - local_paca->tm_scratch = regs->msr; +#ifdef CONFIG_PPC64 + regs->exit_result = ret; #endif - account_cpu_user_exit(); - - /* Restore user access locks last */ - kuap_user_restore(regs); - kuep_unlock(); - return ret; } void preempt_schedule_irq(void); -notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsigned long msr) +notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs) { unsigned long flags; unsigned long ret = 0; unsigned long kuap; + bool stack_store = current_thread_info()->flags & + _TIF_EMULATE_STACK_STORE; if (!IS_ENABLED(CONFIG_BOOKE) && !IS_ENABLED(CONFIG_40x) && unlikely(!(regs->msr & MSR_RI))) @@ -450,11 +509,6 @@ notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsign kuap = kuap_get_and_assert_locked(); - if (unlikely(current_thread_info()->flags & _TIF_EMULATE_STACK_STORE)) { - clear_bits(_TIF_EMULATE_STACK_STORE, ¤t_thread_info()->flags); - ret = 1; - } - local_irq_save(flags); if (!arch_irq_disabled_regs(regs)) { @@ -469,17 +523,58 @@ again: } } - if (unlikely(!prep_irq_for_enabled_exit(true, !irqs_disabled_flags(flags)))) + check_return_regs_valid(regs); + + /* + * Stack store exit can't be restarted because the interrupt + * stack frame might have been clobbered. + */ + if (!prep_irq_for_enabled_exit(unlikely(stack_store))) { + /* + * Replay pending soft-masked interrupts now. Don't + * just local_irq_enabe(); local_irq_disable(); because + * if we are returning from an asynchronous interrupt + * here, another one might hit after irqs are enabled, + * and it would exit via this same path allowing + * another to fire, and so on unbounded. + */ + hard_irq_disable(); + replay_soft_interrupts(); + /* Took an interrupt, may have more exit work to do. */ goto again; - } else { - /* Returning to a kernel context with local irqs disabled. */ - __hard_EE_RI_disable(); + } #ifdef CONFIG_PPC64 + /* + * An interrupt may clear MSR[EE] and set this concurrently, + * but it will be marked pending and the exit will be retried. + * This leaves a racy window where MSR[EE]=0 and HARD_DIS is + * clear, until interrupt_exit_kernel_restart() calls + * hard_irq_disable(), which will set HARD_DIS again. + */ + local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; + + } else { + check_return_regs_valid(regs); + + if (unlikely(stack_store)) + __hard_EE_RI_disable(); + /* + * Returning to a kernel context with local irqs disabled. + * Here, if EE was enabled in the interrupted context, enable + * it on return as well. A problem exists here where a soft + * masked interrupt may have cleared MSR[EE] and set HARD_DIS + * here, and it will still exist on return to the caller. This + * will be resolved by the masked interrupt firing again. + */ if (regs->msr & MSR_EE) local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; -#endif +#endif /* CONFIG_PPC64 */ } + if (unlikely(stack_store)) { + clear_bits(_TIF_EMULATE_STACK_STORE, ¤t_thread_info()->flags); + ret = 1; + } #ifdef CONFIG_PPC_TRANSACTIONAL_MEM local_paca->tm_scratch = regs->msr; @@ -494,3 +589,46 @@ again: return ret; } + +#ifdef CONFIG_PPC64 +notrace unsigned long interrupt_exit_user_restart(struct pt_regs *regs) +{ + __hard_irq_disable(); + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; + +#ifdef CONFIG_PPC_BOOK3S_64 + set_kuap(AMR_KUAP_BLOCKED); +#endif + + trace_hardirqs_off(); + user_exit_irqoff(); + account_cpu_user_entry(); + + BUG_ON(!user_mode(regs)); + + regs->exit_result |= interrupt_exit_user_prepare(regs); + + return regs->exit_result; +} + +/* + * No real need to return a value here because the stack store case does not + * get restarted. + */ +notrace unsigned long interrupt_exit_kernel_restart(struct pt_regs *regs) +{ + __hard_irq_disable(); + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; + +#ifdef CONFIG_PPC_BOOK3S_64 + set_kuap(AMR_KUAP_BLOCKED); +#endif + + if (regs->softe == IRQS_ENABLED) + trace_hardirqs_off(); + + BUG_ON(user_mode(regs)); + + return interrupt_exit_kernel_prepare(regs); +} +#endif diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/interrupt_64.S new file mode 100644 index 000000000000..4063e8a3f704 --- /dev/null +++ b/arch/powerpc/kernel/interrupt_64.S @@ -0,0 +1,770 @@ +#include +#include +#ifdef CONFIG_PPC_BOOK3S +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + + .section ".toc","aw" +SYS_CALL_TABLE: + .tc sys_call_table[TC],sys_call_table + +#ifdef CONFIG_COMPAT +COMPAT_SYS_CALL_TABLE: + .tc compat_sys_call_table[TC],compat_sys_call_table +#endif + .previous + + .align 7 + +.macro DEBUG_SRR_VALID srr +#ifdef CONFIG_PPC_RFI_SRR_DEBUG + .ifc \srr,srr + mfspr r11,SPRN_SRR0 + ld r12,_NIP(r1) +100: tdne r11,r12 + EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE) + mfspr r11,SPRN_SRR1 + ld r12,_MSR(r1) +100: tdne r11,r12 + EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE) + .else + mfspr r11,SPRN_HSRR0 + ld r12,_NIP(r1) +100: tdne r11,r12 + EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE) + mfspr r11,SPRN_HSRR1 + ld r12,_MSR(r1) +100: tdne r11,r12 + EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE) + .endif +#endif +.endm + +#ifdef CONFIG_PPC_BOOK3S +.macro system_call_vectored name trapnr + .globl system_call_vectored_\name +system_call_vectored_\name: +_ASM_NOKPROBE_SYMBOL(system_call_vectored_\name) +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +BEGIN_FTR_SECTION + extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ + bne tabort_syscall +END_FTR_SECTION_IFSET(CPU_FTR_TM) +#endif + SCV_INTERRUPT_TO_KERNEL + mr r10,r1 + ld r1,PACAKSAVE(r13) + std r10,0(r1) + std r11,_NIP(r1) + std r12,_MSR(r1) + std r0,GPR0(r1) + std r10,GPR1(r1) + std r2,GPR2(r1) + ld r2,PACATOC(r13) + mfcr r12 + li r11,0 + /* Can we avoid saving r3-r8 in common case? */ + std r3,GPR3(r1) + std r4,GPR4(r1) + std r5,GPR5(r1) + std r6,GPR6(r1) + std r7,GPR7(r1) + std r8,GPR8(r1) + /* Zero r9-r12, this should only be required when restoring all GPRs */ + std r11,GPR9(r1) + std r11,GPR10(r1) + std r11,GPR11(r1) + std r11,GPR12(r1) + std r9,GPR13(r1) + SAVE_NVGPRS(r1) + std r11,_XER(r1) + std r11,_LINK(r1) + std r11,_CTR(r1) + + li r11,\trapnr + std r11,_TRAP(r1) + std r12,_CCR(r1) + addi r10,r1,STACK_FRAME_OVERHEAD + ld r11,exception_marker@toc(r2) + std r11,-16(r10) /* "regshere" marker */ + +BEGIN_FTR_SECTION + HMT_MEDIUM +END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) + + /* + * scv enters with MSR[EE]=1 and is immediately considered soft-masked. + * The entry vector already sets PACAIRQSOFTMASK to IRQS_ALL_DISABLED, + * and interrupts may be masked and pending already. + * system_call_exception() will call trace_hardirqs_off() which means + * interrupts could already have been blocked before trace_hardirqs_off, + * but this is the best we can do. + */ + + /* Calling convention has r9 = orig r0, r10 = regs */ + mr r9,r0 + bl system_call_exception + +.Lsyscall_vectored_\name\()_exit: + addi r4,r1,STACK_FRAME_OVERHEAD + li r5,1 /* scv */ + bl syscall_exit_prepare + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ +.Lsyscall_vectored_\name\()_rst_start: + lbz r11,PACAIRQHAPPENED(r13) + andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l + bne- syscall_vectored_\name\()_restart + li r11,IRQS_ENABLED + stb r11,PACAIRQSOFTMASK(r13) + li r11,0 + stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS + + ld r2,_CCR(r1) + ld r4,_NIP(r1) + ld r5,_MSR(r1) + +BEGIN_FTR_SECTION + stdcx. r0,0,r1 /* to clear the reservation */ +END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) + +BEGIN_FTR_SECTION + HMT_MEDIUM_LOW +END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) + + cmpdi r3,0 + bne .Lsyscall_vectored_\name\()_restore_regs + + /* rfscv returns with LR->NIA and CTR->MSR */ + mtlr r4 + mtctr r5 + + /* Could zero these as per ABI, but we may consider a stricter ABI + * which preserves these if libc implementations can benefit, so + * restore them for now until further measurement is done. */ + ld r0,GPR0(r1) + ld r4,GPR4(r1) + ld r5,GPR5(r1) + ld r6,GPR6(r1) + ld r7,GPR7(r1) + ld r8,GPR8(r1) + /* Zero volatile regs that may contain sensitive kernel data */ + li r9,0 + li r10,0 + li r11,0 + li r12,0 + mtspr SPRN_XER,r0 + + /* + * We don't need to restore AMR on the way back to userspace for KUAP. + * The value of AMR only matters while we're in the kernel. + */ + mtcr r2 + ld r2,GPR2(r1) + ld r3,GPR3(r1) + ld r13,GPR13(r1) + ld r1,GPR1(r1) + RFSCV_TO_USER + b . /* prevent speculative execution */ + +.Lsyscall_vectored_\name\()_restore_regs: + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r5 + + ld r3,_CTR(r1) + ld r4,_LINK(r1) + ld r5,_XER(r1) + + REST_NVGPRS(r1) + ld r0,GPR0(r1) + mtcr r2 + mtctr r3 + mtlr r4 + mtspr SPRN_XER,r5 + REST_10GPRS(2, r1) + REST_2GPRS(12, r1) + ld r1,GPR1(r1) + RFI_TO_USER +.Lsyscall_vectored_\name\()_rst_end: + +syscall_vectored_\name\()_restart: +_ASM_NOKPROBE_SYMBOL(syscall_vectored_\name\()_restart) + GET_PACA(r13) + ld r1,PACA_EXIT_SAVE_R1(r13) + ld r2,PACATOC(r13) + ld r3,RESULT(r1) + addi r4,r1,STACK_FRAME_OVERHEAD + li r11,IRQS_ALL_DISABLED + stb r11,PACAIRQSOFTMASK(r13) + bl syscall_exit_restart + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ + b .Lsyscall_vectored_\name\()_rst_start +1: + +SOFT_MASK_TABLE(.Lsyscall_vectored_\name\()_rst_start, 1b) +RESTART_TABLE(.Lsyscall_vectored_\name\()_rst_start, .Lsyscall_vectored_\name\()_rst_end, syscall_vectored_\name\()_restart) + +.endm + +system_call_vectored common 0x3000 + +/* + * We instantiate another entry copy for the SIGILL variant, with TRAP=0x7ff0 + * which is tested by system_call_exception when r0 is -1 (as set by vector + * entry code). + */ +system_call_vectored sigill 0x7ff0 + + +/* + * Entered via kernel return set up by kernel/sstep.c, must match entry regs + */ + .globl system_call_vectored_emulate +system_call_vectored_emulate: +_ASM_NOKPROBE_SYMBOL(system_call_vectored_emulate) + li r10,IRQS_ALL_DISABLED + stb r10,PACAIRQSOFTMASK(r13) + b system_call_vectored_common +#endif /* CONFIG_PPC_BOOK3S */ + + .balign IFETCH_ALIGN_BYTES + .globl system_call_common_real +system_call_common_real: +_ASM_NOKPROBE_SYMBOL(system_call_common_real) + ld r10,PACAKMSR(r13) /* get MSR value for kernel */ + mtmsrd r10 + + .balign IFETCH_ALIGN_BYTES + .globl system_call_common +system_call_common: +_ASM_NOKPROBE_SYMBOL(system_call_common) +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +BEGIN_FTR_SECTION + extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ + bne tabort_syscall +END_FTR_SECTION_IFSET(CPU_FTR_TM) +#endif + mr r10,r1 + ld r1,PACAKSAVE(r13) + std r10,0(r1) + std r11,_NIP(r1) + std r12,_MSR(r1) + std r0,GPR0(r1) + std r10,GPR1(r1) + std r2,GPR2(r1) +#ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION +#endif + ld r2,PACATOC(r13) + mfcr r12 + li r11,0 + /* Can we avoid saving r3-r8 in common case? */ + std r3,GPR3(r1) + std r4,GPR4(r1) + std r5,GPR5(r1) + std r6,GPR6(r1) + std r7,GPR7(r1) + std r8,GPR8(r1) + /* Zero r9-r12, this should only be required when restoring all GPRs */ + std r11,GPR9(r1) + std r11,GPR10(r1) + std r11,GPR11(r1) + std r11,GPR12(r1) + std r9,GPR13(r1) + SAVE_NVGPRS(r1) + std r11,_XER(r1) + std r11,_CTR(r1) + mflr r10 + + /* + * This clears CR0.SO (bit 28), which is the error indication on + * return from this system call. + */ + rldimi r12,r11,28,(63-28) + li r11,0xc00 + std r10,_LINK(r1) + std r11,_TRAP(r1) + std r12,_CCR(r1) + addi r10,r1,STACK_FRAME_OVERHEAD + ld r11,exception_marker@toc(r2) + std r11,-16(r10) /* "regshere" marker */ + +#ifdef CONFIG_PPC_BOOK3S + li r11,1 + stb r11,PACASRR_VALID(r13) +#endif + + /* + * We always enter kernel from userspace with irq soft-mask enabled and + * nothing pending. system_call_exception() will call + * trace_hardirqs_off(). + */ + li r11,IRQS_ALL_DISABLED + li r12,-1 /* Set MSR_EE and MSR_RI */ + stb r11,PACAIRQSOFTMASK(r13) + mtmsrd r12,1 + + /* Calling convention has r9 = orig r0, r10 = regs */ + mr r9,r0 + bl system_call_exception + +.Lsyscall_exit: + addi r4,r1,STACK_FRAME_OVERHEAD + li r5,0 /* !scv */ + bl syscall_exit_prepare + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ +#ifdef CONFIG_PPC_BOOK3S +.Lsyscall_rst_start: + lbz r11,PACAIRQHAPPENED(r13) + andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l + bne- syscall_restart +#endif + li r11,IRQS_ENABLED + stb r11,PACAIRQSOFTMASK(r13) + li r11,0 + stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS + + ld r2,_CCR(r1) + ld r6,_LINK(r1) + mtlr r6 + +#ifdef CONFIG_PPC_BOOK3S + lbz r4,PACASRR_VALID(r13) + cmpdi r4,0 + bne 1f + li r4,0 + stb r4,PACASRR_VALID(r13) +#endif + ld r4,_NIP(r1) + ld r5,_MSR(r1) + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r5 +1: + DEBUG_SRR_VALID srr + +BEGIN_FTR_SECTION + stdcx. r0,0,r1 /* to clear the reservation */ +END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) + + cmpdi r3,0 + bne .Lsyscall_restore_regs + /* Zero volatile regs that may contain sensitive kernel data */ + li r0,0 + li r4,0 + li r5,0 + li r6,0 + li r7,0 + li r8,0 + li r9,0 + li r10,0 + li r11,0 + li r12,0 + mtctr r0 + mtspr SPRN_XER,r0 +.Lsyscall_restore_regs_cont: + +BEGIN_FTR_SECTION + HMT_MEDIUM_LOW +END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) + + /* + * We don't need to restore AMR on the way back to userspace for KUAP. + * The value of AMR only matters while we're in the kernel. + */ + mtcr r2 + ld r2,GPR2(r1) + ld r3,GPR3(r1) + ld r13,GPR13(r1) + ld r1,GPR1(r1) + RFI_TO_USER + b . /* prevent speculative execution */ + +.Lsyscall_restore_regs: + ld r3,_CTR(r1) + ld r4,_XER(r1) + REST_NVGPRS(r1) + mtctr r3 + mtspr SPRN_XER,r4 + ld r0,GPR0(r1) + REST_8GPRS(4, r1) + ld r12,GPR12(r1) + b .Lsyscall_restore_regs_cont +.Lsyscall_rst_end: + +#ifdef CONFIG_PPC_BOOK3S +syscall_restart: +_ASM_NOKPROBE_SYMBOL(syscall_restart) + GET_PACA(r13) + ld r1,PACA_EXIT_SAVE_R1(r13) + ld r2,PACATOC(r13) + ld r3,RESULT(r1) + addi r4,r1,STACK_FRAME_OVERHEAD + li r11,IRQS_ALL_DISABLED + stb r11,PACAIRQSOFTMASK(r13) + bl syscall_exit_restart + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ + b .Lsyscall_rst_start +1: + +SOFT_MASK_TABLE(.Lsyscall_rst_start, 1b) +RESTART_TABLE(.Lsyscall_rst_start, .Lsyscall_rst_end, syscall_restart) +#endif + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +tabort_syscall: +_ASM_NOKPROBE_SYMBOL(tabort_syscall) + /* Firstly we need to enable TM in the kernel */ + mfmsr r10 + li r9, 1 + rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG + mtmsrd r10, 0 + + /* tabort, this dooms the transaction, nothing else */ + li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT) + TABORT(R9) + + /* + * Return directly to userspace. We have corrupted user register state, + * but userspace will never see that register state. Execution will + * resume after the tbegin of the aborted transaction with the + * checkpointed register state. + */ + li r9, MSR_RI + andc r10, r10, r9 + mtmsrd r10, 1 + mtspr SPRN_SRR0, r11 + mtspr SPRN_SRR1, r12 + RFI_TO_USER + b . /* prevent speculative execution */ +#endif + + /* + * If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not + * touched, no exit work created, then this can be used. + */ + .balign IFETCH_ALIGN_BYTES + .globl fast_interrupt_return_srr +fast_interrupt_return_srr: +_ASM_NOKPROBE_SYMBOL(fast_interrupt_return_srr) + kuap_check_amr r3, r4 + ld r5,_MSR(r1) + andi. r0,r5,MSR_PR +#ifdef CONFIG_PPC_BOOK3S + beq 1f + kuap_user_restore r3, r4 + b .Lfast_user_interrupt_return_srr +1: kuap_kernel_restore r3, r4 + andi. r0,r5,MSR_RI + li r3,0 /* 0 return value, no EMULATE_STACK_STORE */ + bne+ .Lfast_kernel_interrupt_return_srr + addi r3,r1,STACK_FRAME_OVERHEAD + bl unrecoverable_exception + b . /* should not get here */ +#else + bne .Lfast_user_interrupt_return_srr + b .Lfast_kernel_interrupt_return_srr +#endif + +.macro interrupt_return_macro srr + .balign IFETCH_ALIGN_BYTES + .globl interrupt_return_\srr +interrupt_return_\srr\(): +_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()) + ld r4,_MSR(r1) + andi. r0,r4,MSR_PR + beq interrupt_return_\srr\()_kernel +interrupt_return_\srr\()_user: /* make backtraces match the _kernel variant */ +_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user) + addi r3,r1,STACK_FRAME_OVERHEAD + bl interrupt_exit_user_prepare + cmpdi r3,0 + bne- .Lrestore_nvgprs_\srr +.Lrestore_nvgprs_\srr\()_cont: + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ +#ifdef CONFIG_PPC_BOOK3S +.Linterrupt_return_\srr\()_user_rst_start: + lbz r11,PACAIRQHAPPENED(r13) + andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l + bne- interrupt_return_\srr\()_user_restart +#endif + li r11,IRQS_ENABLED + stb r11,PACAIRQSOFTMASK(r13) + li r11,0 + stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS + +.Lfast_user_interrupt_return_\srr\(): +#ifdef CONFIG_PPC_BOOK3S + .ifc \srr,srr + lbz r4,PACASRR_VALID(r13) + .else + lbz r4,PACAHSRR_VALID(r13) + .endif + cmpdi r4,0 + li r4,0 + bne 1f +#endif + ld r11,_NIP(r1) + ld r12,_MSR(r1) + .ifc \srr,srr + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 +1: +#ifdef CONFIG_PPC_BOOK3S + stb r4,PACASRR_VALID(r13) +#endif + .else + mtspr SPRN_HSRR0,r11 + mtspr SPRN_HSRR1,r12 +1: +#ifdef CONFIG_PPC_BOOK3S + stb r4,PACAHSRR_VALID(r13) +#endif + .endif + DEBUG_SRR_VALID \srr + +#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG + lbz r4,PACAIRQSOFTMASK(r13) + tdnei r4,IRQS_ENABLED +#endif + +BEGIN_FTR_SECTION + ld r10,_PPR(r1) + mtspr SPRN_PPR,r10 +END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) + +BEGIN_FTR_SECTION + stdcx. r0,0,r1 /* to clear the reservation */ +FTR_SECTION_ELSE + ldarx r0,0,r1 +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) + + ld r3,_CCR(r1) + ld r4,_LINK(r1) + ld r5,_CTR(r1) + ld r6,_XER(r1) + li r0,0 + + REST_4GPRS(7, r1) + REST_2GPRS(11, r1) + REST_GPR(13, r1) + + mtcr r3 + mtlr r4 + mtctr r5 + mtspr SPRN_XER,r6 + + REST_4GPRS(2, r1) + REST_GPR(6, r1) + REST_GPR(0, r1) + REST_GPR(1, r1) + .ifc \srr,srr + RFI_TO_USER + .else + HRFI_TO_USER + .endif + b . /* prevent speculative execution */ +.Linterrupt_return_\srr\()_user_rst_end: + +.Lrestore_nvgprs_\srr\(): + REST_NVGPRS(r1) + b .Lrestore_nvgprs_\srr\()_cont + +#ifdef CONFIG_PPC_BOOK3S +interrupt_return_\srr\()_user_restart: +_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user_restart) + GET_PACA(r13) + ld r1,PACA_EXIT_SAVE_R1(r13) + ld r2,PACATOC(r13) + addi r3,r1,STACK_FRAME_OVERHEAD + li r11,IRQS_ALL_DISABLED + stb r11,PACAIRQSOFTMASK(r13) + bl interrupt_exit_user_restart + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ + b .Linterrupt_return_\srr\()_user_rst_start +1: + +SOFT_MASK_TABLE(.Linterrupt_return_\srr\()_user_rst_start, 1b) +RESTART_TABLE(.Linterrupt_return_\srr\()_user_rst_start, .Linterrupt_return_\srr\()_user_rst_end, interrupt_return_\srr\()_user_restart) +#endif + + .balign IFETCH_ALIGN_BYTES +interrupt_return_\srr\()_kernel: +_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel) + addi r3,r1,STACK_FRAME_OVERHEAD + bl interrupt_exit_kernel_prepare + + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ +.Linterrupt_return_\srr\()_kernel_rst_start: + ld r11,SOFTE(r1) + cmpwi r11,IRQS_ENABLED + stb r11,PACAIRQSOFTMASK(r13) + bne 1f +#ifdef CONFIG_PPC_BOOK3S + lbz r11,PACAIRQHAPPENED(r13) + andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l + bne- interrupt_return_\srr\()_kernel_restart +#endif + li r11,0 + stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS +1: + +.Lfast_kernel_interrupt_return_\srr\(): + cmpdi cr1,r3,0 +#ifdef CONFIG_PPC_BOOK3S + .ifc \srr,srr + lbz r4,PACASRR_VALID(r13) + .else + lbz r4,PACAHSRR_VALID(r13) + .endif + cmpdi r4,0 + li r4,0 + bne 1f +#endif + ld r11,_NIP(r1) + ld r12,_MSR(r1) + .ifc \srr,srr + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 +1: +#ifdef CONFIG_PPC_BOOK3S + stb r4,PACASRR_VALID(r13) +#endif + .else + mtspr SPRN_HSRR0,r11 + mtspr SPRN_HSRR1,r12 +1: +#ifdef CONFIG_PPC_BOOK3S + stb r4,PACAHSRR_VALID(r13) +#endif + .endif + DEBUG_SRR_VALID \srr + +BEGIN_FTR_SECTION + stdcx. r0,0,r1 /* to clear the reservation */ +FTR_SECTION_ELSE + ldarx r0,0,r1 +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) + + ld r3,_LINK(r1) + ld r4,_CTR(r1) + ld r5,_XER(r1) + ld r6,_CCR(r1) + li r0,0 + + REST_4GPRS(7, r1) + REST_2GPRS(11, r1) + + mtlr r3 + mtctr r4 + mtspr SPRN_XER,r5 + + /* + * Leaving a stale exception_marker on the stack can confuse + * the reliable stack unwinder later on. Clear it. + */ + std r0,STACK_FRAME_OVERHEAD-16(r1) + + REST_4GPRS(2, r1) + + bne- cr1,1f /* emulate stack store */ + mtcr r6 + REST_GPR(6, r1) + REST_GPR(0, r1) + REST_GPR(1, r1) + .ifc \srr,srr + RFI_TO_KERNEL + .else + HRFI_TO_KERNEL + .endif + b . /* prevent speculative execution */ + +1: /* + * Emulate stack store with update. New r1 value was already calculated + * and updated in our interrupt regs by emulate_loadstore, but we can't + * store the previous value of r1 to the stack before re-loading our + * registers from it, otherwise they could be clobbered. Use + * PACA_EXGEN as temporary storage to hold the store data, as + * interrupts are disabled here so it won't be clobbered. + */ + mtcr r6 + std r9,PACA_EXGEN+0(r13) + addi r9,r1,INT_FRAME_SIZE /* get original r1 */ + REST_GPR(6, r1) + REST_GPR(0, r1) + REST_GPR(1, r1) + std r9,0(r1) /* perform store component of stdu */ + ld r9,PACA_EXGEN+0(r13) + + .ifc \srr,srr + RFI_TO_KERNEL + .else + HRFI_TO_KERNEL + .endif + b . /* prevent speculative execution */ +.Linterrupt_return_\srr\()_kernel_rst_end: + +#ifdef CONFIG_PPC_BOOK3S +interrupt_return_\srr\()_kernel_restart: +_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel_restart) + GET_PACA(r13) + ld r1,PACA_EXIT_SAVE_R1(r13) + ld r2,PACATOC(r13) + addi r3,r1,STACK_FRAME_OVERHEAD + li r11,IRQS_ALL_DISABLED + stb r11,PACAIRQSOFTMASK(r13) + bl interrupt_exit_kernel_restart + std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */ + b .Linterrupt_return_\srr\()_kernel_rst_start +1: + +SOFT_MASK_TABLE(.Linterrupt_return_\srr\()_kernel_rst_start, 1b) +RESTART_TABLE(.Linterrupt_return_\srr\()_kernel_rst_start, .Linterrupt_return_\srr\()_kernel_rst_end, interrupt_return_\srr\()_kernel_restart) +#endif + +.endm + +interrupt_return_macro srr +#ifdef CONFIG_PPC_BOOK3S +interrupt_return_macro hsrr + + .globl __end_soft_masked +__end_soft_masked: +DEFINE_FIXED_SYMBOL(__end_soft_masked) +#endif /* CONFIG_PPC_BOOK3S */ + +#ifdef CONFIG_PPC_BOOK3S +_GLOBAL(ret_from_fork_scv) + bl schedule_tail + REST_NVGPRS(r1) + li r3,0 /* fork() return value */ + b .Lsyscall_vectored_common_exit +#endif + +_GLOBAL(ret_from_fork) + bl schedule_tail + REST_NVGPRS(r1) + li r3,0 /* fork() return value */ + b .Lsyscall_exit + +_GLOBAL(ret_from_kernel_thread) + bl schedule_tail + REST_NVGPRS(r1) + mtctr r14 + mr r3,r15 +#ifdef PPC64_ELF_ABI_v2 + mr r12,r14 +#endif + bctrl + li r3,0 + b .Lsyscall_exit diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 72cb45393ef2..91e63eac4e8f 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -121,6 +121,7 @@ void replay_soft_interrupts(void) ppc_save_regs(®s); regs.softe = IRQS_ENABLED; + regs.msr |= MSR_EE; again: if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) @@ -217,6 +218,100 @@ static inline void replay_soft_interrupts_irqrestore(void) #define replay_soft_interrupts_irqrestore() replay_soft_interrupts() #endif +#ifdef CONFIG_CC_HAS_ASM_GOTO +notrace void arch_local_irq_restore(unsigned long mask) +{ + unsigned char irq_happened; + + /* Write the new soft-enabled value if it is a disable */ + if (mask) { + irq_soft_mask_set(mask); + return; + } + + /* + * After the stb, interrupts are unmasked and there are no interrupts + * pending replay. The restart sequence makes this atomic with + * respect to soft-masked interrupts. If this was just a simple code + * sequence, a soft-masked interrupt could become pending right after + * the comparison and before the stb. + * + * This allows interrupts to be unmasked without hard disabling, and + * also without new hard interrupts coming in ahead of pending ones. + */ + asm_volatile_goto( +"1: \n" +" lbz 9,%0(13) \n" +" cmpwi 9,0 \n" +" bne %l[happened] \n" +" stb 9,%1(13) \n" +"2: \n" + RESTART_TABLE(1b, 2b, 1b) + : : "i" (offsetof(struct paca_struct, irq_happened)), + "i" (offsetof(struct paca_struct, irq_soft_mask)) + : "cr0", "r9" + : happened); + + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + WARN_ON_ONCE(!(mfmsr() & MSR_EE)); + + return; + +happened: + irq_happened = get_irq_happened(); + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + WARN_ON_ONCE(!irq_happened); + + if (irq_happened == PACA_IRQ_HARD_DIS) { + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + WARN_ON_ONCE(mfmsr() & MSR_EE); + irq_soft_mask_set(IRQS_ENABLED); + local_paca->irq_happened = 0; + __hard_irq_enable(); + return; + } + + /* Have interrupts to replay, need to hard disable first */ + if (!(irq_happened & PACA_IRQ_HARD_DIS)) { + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) { + if (!(mfmsr() & MSR_EE)) { + /* + * An interrupt could have come in and cleared + * MSR[EE] and set IRQ_HARD_DIS, so check + * IRQ_HARD_DIS again and warn if it is still + * clear. + */ + irq_happened = get_irq_happened(); + WARN_ON_ONCE(!(irq_happened & PACA_IRQ_HARD_DIS)); + } + } + __hard_irq_disable(); + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; + } else { + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) { + if (WARN_ON_ONCE(mfmsr() & MSR_EE)) + __hard_irq_disable(); + } + } + + /* + * Disable preempt here, so that the below preempt_enable will + * perform resched if required (a replayed interrupt may set + * need_resched). + */ + preempt_disable(); + irq_soft_mask_set(IRQS_ALL_DISABLED); + trace_hardirqs_off(); + + replay_soft_interrupts_irqrestore(); + local_paca->irq_happened = 0; + + trace_hardirqs_on(); + irq_soft_mask_set(IRQS_ENABLED); + __hard_irq_enable(); + preempt_enable(); +} +#else notrace void arch_local_irq_restore(unsigned long mask) { unsigned char irq_happened; @@ -288,6 +383,7 @@ notrace void arch_local_irq_restore(unsigned long mask) __hard_irq_enable(); preempt_enable(); } +#endif EXPORT_SYMBOL(arch_local_irq_restore); /* diff --git a/arch/powerpc/kernel/jump_label.c b/arch/powerpc/kernel/jump_label.c index ce87dc5ea23c..5277cf582c16 100644 --- a/arch/powerpc/kernel/jump_label.c +++ b/arch/powerpc/kernel/jump_label.c @@ -11,10 +11,10 @@ void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type type) { - struct ppc_inst *addr = (struct ppc_inst *)jump_entry_code(entry); + u32 *addr = (u32 *)jump_entry_code(entry); if (type == JUMP_LABEL_JMP) patch_branch(addr, jump_entry_target(entry), 0); else - patch_instruction(addr, ppc_inst(PPC_INST_NOP)); + patch_instruction(addr, ppc_inst(PPC_RAW_NOP())); } diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c index 7dd2ad3603ad..bdee7262c080 100644 --- a/arch/powerpc/kernel/kgdb.c +++ b/arch/powerpc/kernel/kgdb.c @@ -147,7 +147,7 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs) return 0; if (*(u32 *)regs->nip == BREAK_INSTR) - regs->nip += BREAK_INSTR_SIZE; + regs_add_return_ip(regs, BREAK_INSTR_SIZE); return 1; } @@ -372,7 +372,7 @@ int dbg_set_reg(int regno, void *mem, struct pt_regs *regs) void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) { - regs->nip = pc; + regs_set_return_ip(regs, pc); } /* @@ -394,7 +394,7 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, case 'c': /* handle the optional parameter */ if (kgdb_hex2long(&ptr, &addr)) - linux_regs->nip = addr; + regs_set_return_ip(linux_regs, addr); atomic_set(&kgdb_cpu_doing_single_step, -1); /* set the trace bit if we're stepping */ @@ -402,9 +402,9 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, #ifdef CONFIG_PPC_ADV_DEBUG_REGS mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM); - linux_regs->msr |= MSR_DE; + regs_set_return_msr(linux_regs, linux_regs->msr | MSR_DE); #else - linux_regs->msr |= MSR_SE; + regs_set_return_msr(linux_regs, linux_regs->msr | MSR_SE); #endif atomic_set(&kgdb_cpu_doing_single_step, raw_smp_processor_id()); @@ -417,11 +417,10 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) { + u32 instr, *addr = (u32 *)bpt->bpt_addr; int err; - unsigned int instr; - struct ppc_inst *addr = (struct ppc_inst *)bpt->bpt_addr; - err = get_kernel_nofault(instr, (unsigned *) addr); + err = get_kernel_nofault(instr, addr); if (err) return err; @@ -429,7 +428,7 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) if (err) return -EFAULT; - *(unsigned int *)bpt->saved_instr = instr; + *(u32 *)bpt->saved_instr = instr; return 0; } @@ -438,7 +437,7 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt) { int err; unsigned int instr = *(unsigned int *)bpt->saved_instr; - struct ppc_inst *addr = (struct ppc_inst *)bpt->bpt_addr; + u32 *addr = (u32 *)bpt->bpt_addr; err = patch_instruction(addr, ppc_inst(instr)); if (err) diff --git a/arch/powerpc/kernel/kprobes-ftrace.c b/arch/powerpc/kernel/kprobes-ftrace.c index 660138f6c4b2..7154d58338cc 100644 --- a/arch/powerpc/kernel/kprobes-ftrace.c +++ b/arch/powerpc/kernel/kprobes-ftrace.c @@ -39,7 +39,7 @@ void kprobe_ftrace_handler(unsigned long nip, unsigned long parent_nip, * On powerpc, NIP is *before* this instruction for the * pre handler */ - regs->nip -= MCOUNT_INSN_SIZE; + regs_add_return_ip(regs, -MCOUNT_INSN_SIZE); __this_cpu_write(current_kprobe, p); kcb->kprobe_status = KPROBE_HIT_ACTIVE; @@ -48,7 +48,7 @@ void kprobe_ftrace_handler(unsigned long nip, unsigned long parent_nip, * Emulate singlestep (and also recover regs->nip) * as if there is a nop */ - regs->nip += MCOUNT_INSN_SIZE; + regs_add_return_ip(regs, MCOUNT_INSN_SIZE); if (unlikely(p->post_handler)) { kcb->kprobe_status = KPROBE_HIT_SSDONE; p->post_handler(p, regs, 0); diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c index c64a5feaebbe..cbc28d1a2e1b 100644 --- a/arch/powerpc/kernel/kprobes.c +++ b/arch/powerpc/kernel/kprobes.c @@ -19,11 +19,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; @@ -103,28 +105,42 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, unsigned int offset) return addr; } +void *alloc_insn_page(void) +{ + void *page; + + page = module_alloc(PAGE_SIZE); + if (!page) + return NULL; + + if (strict_module_rwx_enabled()) { + set_memory_ro((unsigned long)page, 1); + set_memory_x((unsigned long)page, 1); + } + return page; +} + int arch_prepare_kprobe(struct kprobe *p) { int ret = 0; struct kprobe *prev; - struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->addr); + struct ppc_inst insn = ppc_inst_read(p->addr); if ((unsigned long)p->addr & 0x03) { printk("Attempt to register kprobe at an unaligned address\n"); ret = -EINVAL; - } else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) { - printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n"); + } else if (IS_MTMSRD(insn) || IS_RFID(insn)) { + printk("Cannot register a kprobe on mtmsr[d]/rfi[d]\n"); ret = -EINVAL; } else if ((unsigned long)p->addr & ~PAGE_MASK && - ppc_inst_prefixed(ppc_inst_read((struct ppc_inst *)(p->addr - 1)))) { + ppc_inst_prefixed(ppc_inst_read(p->addr - 1))) { printk("Cannot register a kprobe on the second word of prefixed instruction\n"); ret = -EINVAL; } preempt_disable(); prev = get_kprobe(p->addr - 1); preempt_enable_no_resched(); - if (prev && - ppc_inst_prefixed(ppc_inst_read((struct ppc_inst *)prev->ainsn.insn))) { + if (prev && ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) { printk("Cannot register a kprobe on the second word of prefixed instruction\n"); ret = -EINVAL; } @@ -138,7 +154,7 @@ int arch_prepare_kprobe(struct kprobe *p) } if (!ret) { - patch_instruction((struct ppc_inst *)p->ainsn.insn, insn); + patch_instruction(p->ainsn.insn, insn); p->opcode = ppc_inst_val(insn); } @@ -149,13 +165,13 @@ NOKPROBE_SYMBOL(arch_prepare_kprobe); void arch_arm_kprobe(struct kprobe *p) { - patch_instruction((struct ppc_inst *)p->addr, ppc_inst(BREAKPOINT_INSTRUCTION)); + WARN_ON_ONCE(patch_instruction(p->addr, ppc_inst(BREAKPOINT_INSTRUCTION))); } NOKPROBE_SYMBOL(arch_arm_kprobe); void arch_disarm_kprobe(struct kprobe *p) { - patch_instruction((struct ppc_inst *)p->addr, ppc_inst(p->opcode)); + WARN_ON_ONCE(patch_instruction(p->addr, ppc_inst(p->opcode))); } NOKPROBE_SYMBOL(arch_disarm_kprobe); @@ -178,7 +194,7 @@ static nokprobe_inline void prepare_singlestep(struct kprobe *p, struct pt_regs * variant as values in regs could play a part in * if the trap is taken or not */ - regs->nip = (unsigned long)p->ainsn.insn; + regs_set_return_ip(regs, (unsigned long)p->ainsn.insn); } static nokprobe_inline void save_previous_kprobe(struct kprobe_ctlblk *kcb) @@ -228,7 +244,7 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe); static int try_to_emulate(struct kprobe *p, struct pt_regs *regs) { int ret; - struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->ainsn.insn); + struct ppc_inst insn = ppc_inst_read(p->ainsn.insn); /* regs->nip is also adjusted if emulate_step returns 1 */ ret = emulate_step(regs, insn); @@ -319,8 +335,9 @@ int kprobe_handler(struct pt_regs *regs) kprobe_opcode_t insn = *p->ainsn.insn; if (kcb->kprobe_status == KPROBE_HIT_SS && is_trap(insn)) { /* Turn off 'trace' bits */ - regs->msr &= ~MSR_SINGLESTEP; - regs->msr |= kcb->kprobe_saved_msr; + regs_set_return_msr(regs, + (regs->msr & ~MSR_SINGLESTEP) | + kcb->kprobe_saved_msr); goto no_kprobe; } @@ -415,7 +432,7 @@ static int trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs) * we end up emulating it in kprobe_handler(), which increments the nip * again. */ - regs->nip = orig_ret_address - 4; + regs_set_return_ip(regs, orig_ret_address - 4); regs->link = orig_ret_address; return 0; @@ -439,7 +456,7 @@ int kprobe_post_handler(struct pt_regs *regs) if (!cur || user_mode(regs)) return 0; - len = ppc_inst_len(ppc_inst_read((struct ppc_inst *)cur->ainsn.insn)); + len = ppc_inst_len(ppc_inst_read(cur->ainsn.insn)); /* make sure we got here for instruction we have a kprobe on */ if (((unsigned long)cur->ainsn.insn + len) != regs->nip) return 0; @@ -450,8 +467,8 @@ int kprobe_post_handler(struct pt_regs *regs) } /* Adjust nip to after the single-stepped instruction */ - regs->nip = (unsigned long)cur->addr + len; - regs->msr |= kcb->kprobe_saved_msr; + regs_set_return_ip(regs, (unsigned long)cur->addr + len); + regs_set_return_msr(regs, regs->msr | kcb->kprobe_saved_msr); /*Restore back the original saved kprobes variables and continue. */ if (kcb->kprobe_status == KPROBE_REENTER) { @@ -490,9 +507,11 @@ int kprobe_fault_handler(struct pt_regs *regs, int trapnr) * and allow the page fault handler to continue as a * normal page fault. */ - regs->nip = (unsigned long)cur->addr; - regs->msr &= ~MSR_SINGLESTEP; /* Turn off 'trace' bits */ - regs->msr |= kcb->kprobe_saved_msr; + regs_set_return_ip(regs, (unsigned long)cur->addr); + /* Turn off 'trace' bits */ + regs_set_return_msr(regs, + (regs->msr & ~MSR_SINGLESTEP) | + kcb->kprobe_saved_msr); if (kcb->kprobe_status == KPROBE_REENTER) restore_previous_kprobe(kcb); else @@ -506,7 +525,7 @@ int kprobe_fault_handler(struct pt_regs *regs, int trapnr) * zero, try to fix up. */ if ((entry = search_exception_tables(regs->nip)) != NULL) { - regs->nip = extable_fixup(entry); + regs_set_return_ip(regs, extable_fixup(entry)); return 1; } diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c index 15e7b4900689..47a683cd00d2 100644 --- a/arch/powerpc/kernel/mce.c +++ b/arch/powerpc/kernel/mce.c @@ -274,7 +274,7 @@ void mce_common_process_ue(struct pt_regs *regs, entry = search_kernel_exception_table(regs->nip); if (entry) { mce_err->ignore_event = true; - regs->nip = extable_fixup(entry); + regs_set_return_ip(regs, extable_fixup(entry)); } } diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index 667104d4c455..c2f55fe7092d 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -463,7 +463,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, uint64_t *addr, pfn = addr_to_pfn(regs, regs->nip); if (pfn != ULONG_MAX) { instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK); - instr = ppc_inst_read((struct ppc_inst *)instr_addr); + instr = ppc_inst_read((u32 *)instr_addr); if (!analyse_instr(&op, &tmp, instr)) { pfn = addr_to_pfn(regs, op.ea); *addr = op.ea; @@ -481,12 +481,11 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, uint64_t *addr, return -1; } -static int mce_handle_ierror(struct pt_regs *regs, +static int mce_handle_ierror(struct pt_regs *regs, unsigned long srr1, const struct mce_ierror_table table[], struct mce_error_info *mce_err, uint64_t *addr, uint64_t *phys_addr) { - uint64_t srr1 = regs->msr; int handled = 0; int i; @@ -695,19 +694,19 @@ static long mce_handle_ue_error(struct pt_regs *regs, } static long mce_handle_error(struct pt_regs *regs, + unsigned long srr1, const struct mce_derror_table dtable[], const struct mce_ierror_table itable[]) { struct mce_error_info mce_err = { 0 }; uint64_t addr, phys_addr = ULONG_MAX; - uint64_t srr1 = regs->msr; long handled; if (SRR1_MC_LOADSTORE(srr1)) handled = mce_handle_derror(regs, dtable, &mce_err, &addr, &phys_addr); else - handled = mce_handle_ierror(regs, itable, &mce_err, &addr, + handled = mce_handle_ierror(regs, srr1, itable, &mce_err, &addr, &phys_addr); if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE) @@ -723,16 +722,20 @@ long __machine_check_early_realmode_p7(struct pt_regs *regs) /* P7 DD1 leaves top bits of DSISR undefined */ regs->dsisr &= 0x0000ffff; - return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table); + return mce_handle_error(regs, regs->msr, + mce_p7_derror_table, mce_p7_ierror_table); } long __machine_check_early_realmode_p8(struct pt_regs *regs) { - return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table); + return mce_handle_error(regs, regs->msr, + mce_p8_derror_table, mce_p8_ierror_table); } long __machine_check_early_realmode_p9(struct pt_regs *regs) { + unsigned long srr1 = regs->msr; + /* * On POWER9 DD2.1 and below, it's possible to get a machine check * caused by a paste instruction where only DSISR bit 25 is set. This @@ -746,10 +749,39 @@ long __machine_check_early_realmode_p9(struct pt_regs *regs) if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) return 1; - return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); + /* + * Async machine check due to bad real address from store or foreign + * link time out comes with the load/store bit (PPC bit 42) set in + * SRR1, but the cause comes in SRR1 not DSISR. Clear bit 42 so we're + * directed to the ierror table so it will find the cause (which + * describes it correctly as a store error). + */ + if (SRR1_MC_LOADSTORE(srr1) && + ((srr1 & 0x081c0000) == 0x08140000 || + (srr1 & 0x081c0000) == 0x08180000)) { + srr1 &= ~PPC_BIT(42); + } + + return mce_handle_error(regs, srr1, + mce_p9_derror_table, mce_p9_ierror_table); } long __machine_check_early_realmode_p10(struct pt_regs *regs) { - return mce_handle_error(regs, mce_p10_derror_table, mce_p10_ierror_table); + unsigned long srr1 = regs->msr; + + /* + * Async machine check due to bad real address from store comes with + * the load/store bit (PPC bit 42) set in SRR1, but the cause comes in + * SRR1 not DSISR. Clear bit 42 so we're directed to the ierror table + * so it will find the cause (which describes it correctly as a store + * error). + */ + if (SRR1_MC_LOADSTORE(srr1) && + (srr1 & 0x081c0000) == 0x08140000) { + srr1 &= ~PPC_BIT(42); + } + + return mce_handle_error(regs, srr1, + mce_p10_derror_table, mce_p10_ierror_table); } diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 6a076bef2932..39ab15419592 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -388,9 +388,3 @@ _GLOBAL(start_secondary_resume) bl start_secondary b . #endif /* CONFIG_SMP */ - -/* - * This routine is just here to keep GCC happy - sigh... - */ -_GLOBAL(__main) - blr diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c index 3f35c8d20be7..ed04a3ba66fe 100644 --- a/arch/powerpc/kernel/module.c +++ b/arch/powerpc/kernel/module.c @@ -92,12 +92,14 @@ int module_finalize(const Elf_Ehdr *hdr, static __always_inline void * __module_alloc(unsigned long size, unsigned long start, unsigned long end) { + pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC; + /* * Don't do huge page allocations for modules yet until more testing * is done. STRICT_MODULE_RWX may require extra work to support this * too. */ - return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, PAGE_KERNEL_EXEC, + return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, prot, VM_FLUSH_RESET_PERMS | VM_NO_HUGE_VMAP, NUMA_NO_NODE, __builtin_return_address(0)); } diff --git a/arch/powerpc/kernel/module_32.c b/arch/powerpc/kernel/module_32.c index c27b8687b82a..f417afc08d33 100644 --- a/arch/powerpc/kernel/module_32.c +++ b/arch/powerpc/kernel/module_32.c @@ -145,10 +145,9 @@ int module_frob_arch_sections(Elf32_Ehdr *hdr, static inline int entry_matches(struct ppc_plt_entry *entry, Elf32_Addr val) { - if (entry->jump[0] != (PPC_INST_ADDIS | __PPC_RT(R12) | PPC_HA(val))) + if (entry->jump[0] != PPC_RAW_LIS(_R12, PPC_HA(val))) return 0; - if (entry->jump[1] != (PPC_INST_ADDI | __PPC_RT(R12) | __PPC_RA(R12) | - PPC_LO(val))) + if (entry->jump[1] != PPC_RAW_ADDI(_R12, _R12, PPC_LO(val))) return 0; return 1; } @@ -175,16 +174,10 @@ static uint32_t do_plt_call(void *location, entry++; } - /* - * lis r12, sym@ha - * addi r12, r12, sym@l - * mtctr r12 - * bctr - */ - entry->jump[0] = PPC_INST_ADDIS | __PPC_RT(R12) | PPC_HA(val); - entry->jump[1] = PPC_INST_ADDI | __PPC_RT(R12) | __PPC_RA(R12) | PPC_LO(val); - entry->jump[2] = PPC_INST_MTCTR | __PPC_RS(R12); - entry->jump[3] = PPC_INST_BCTR; + entry->jump[0] = PPC_RAW_LIS(_R12, PPC_HA(val)); + entry->jump[1] = PPC_RAW_ADDI(_R12, _R12, PPC_LO(val)); + entry->jump[2] = PPC_RAW_MTCTR(_R12); + entry->jump[3] = PPC_RAW_BCTR(); pr_debug("Initialized plt for 0x%x at %p\n", val, entry); return (uint32_t)entry; diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c index ae2b188365b1..6baa676e7cb6 100644 --- a/arch/powerpc/kernel/module_64.c +++ b/arch/powerpc/kernel/module_64.c @@ -122,27 +122,19 @@ struct ppc64_stub_entry * the stub, but it's significantly shorter to put these values at the * end of the stub code, and patch the stub address (32-bits relative * to the TOC ptr, r2) into the stub. - * - * addis r11,r2, - * addi r11,r11, - * std r2,R2_STACK_OFFSET(r1) - * ld r12,32(r11) - * ld r2,40(r11) - * mtctr r12 - * bctr */ static u32 ppc64_stub_insns[] = { - PPC_INST_ADDIS | __PPC_RT(R11) | __PPC_RA(R2), - PPC_INST_ADDI | __PPC_RT(R11) | __PPC_RA(R11), + PPC_RAW_ADDIS(_R11, _R2, 0), + PPC_RAW_ADDI(_R11, _R11, 0), /* Save current r2 value in magic place on the stack. */ - PPC_INST_STD | __PPC_RS(R2) | __PPC_RA(R1) | R2_STACK_OFFSET, - PPC_INST_LD | __PPC_RT(R12) | __PPC_RA(R11) | 32, + PPC_RAW_STD(_R2, _R1, R2_STACK_OFFSET), + PPC_RAW_LD(_R12, _R11, 32), #ifdef PPC64_ELF_ABI_v1 /* Set up new r2 from function descriptor */ - PPC_INST_LD | __PPC_RT(R2) | __PPC_RA(R11) | 40, + PPC_RAW_LD(_R2, _R11, 40), #endif - PPC_INST_MTCTR | __PPC_RS(R12), - PPC_INST_BCTR, + PPC_RAW_MTCTR(_R12), + PPC_RAW_BCTR(), }; /* Count how many different 24-bit relocations (different symbol, @@ -336,21 +328,12 @@ int module_frob_arch_sections(Elf64_Ehdr *hdr, #ifdef CONFIG_MPROFILE_KERNEL -#define PACATOC offsetof(struct paca_struct, kernel_toc) - -/* - * ld r12,PACATOC(r13) - * addis r12,r12, - * addi r12,r12, - * mtctr r12 - * bctr - */ static u32 stub_insns[] = { - PPC_INST_LD | __PPC_RT(R12) | __PPC_RA(R13) | PACATOC, - PPC_INST_ADDIS | __PPC_RT(R12) | __PPC_RA(R12), - PPC_INST_ADDI | __PPC_RT(R12) | __PPC_RA(R12), - PPC_INST_MTCTR | __PPC_RS(R12), - PPC_INST_BCTR, + PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernel_toc)), + PPC_RAW_ADDIS(_R12, _R12, 0), + PPC_RAW_ADDI(_R12, _R12, 0), + PPC_RAW_MTCTR(_R12), + PPC_RAW_BCTR(), }; /* @@ -507,7 +490,7 @@ static int restore_r2(const char *name, u32 *instruction, struct module *me) if (!instr_is_relative_link_branch(ppc_inst(*prev_insn))) return 1; - if (*instruction != PPC_INST_NOP) { + if (*instruction != PPC_RAW_NOP()) { pr_err("%s: Expected nop after call, got %08x at %pS\n", me->name, *instruction, instruction); return 0; @@ -696,21 +679,17 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, * ld r2, ...(r12) * add r2, r2, r12 */ - if ((((uint32_t *)location)[0] & ~0xfffc) != - (PPC_INST_LD | __PPC_RT(R2) | __PPC_RA(R12))) + if ((((uint32_t *)location)[0] & ~0xfffc) != PPC_RAW_LD(_R2, _R12, 0)) break; - if (((uint32_t *)location)[1] != - (PPC_INST_ADD | __PPC_RT(R2) | __PPC_RA(R2) | __PPC_RB(R12))) + if (((uint32_t *)location)[1] != PPC_RAW_ADD(_R2, _R2, _R12)) break; /* * If found, replace it with: * addis r2, r12, (.TOC.-func)@ha * addi r2, r2, (.TOC.-func)@l */ - ((uint32_t *)location)[0] = PPC_INST_ADDIS | __PPC_RT(R2) | - __PPC_RA(R12) | PPC_HA(value); - ((uint32_t *)location)[1] = PPC_INST_ADDI | __PPC_RT(R2) | - __PPC_RA(R2) | PPC_LO(value); + ((uint32_t *)location)[0] = PPC_RAW_ADDIS(_R2, _R12, PPC_HA(value)); + ((uint32_t *)location)[1] = PPC_RAW_ADDI(_R2, _R2, PPC_LO(value)); break; case R_PPC64_REL16_HA: diff --git a/arch/powerpc/kernel/optprobes.c b/arch/powerpc/kernel/optprobes.c index cdf87086fa33..c79899abcec8 100644 --- a/arch/powerpc/kernel/optprobes.c +++ b/arch/powerpc/kernel/optprobes.c @@ -18,24 +18,16 @@ #include #include -#define TMPL_CALL_HDLR_IDX \ - (optprobe_template_call_handler - optprobe_template_entry) -#define TMPL_EMULATE_IDX \ - (optprobe_template_call_emulate - optprobe_template_entry) -#define TMPL_RET_IDX \ - (optprobe_template_ret - optprobe_template_entry) -#define TMPL_OP_IDX \ - (optprobe_template_op_address - optprobe_template_entry) -#define TMPL_INSN_IDX \ - (optprobe_template_insn - optprobe_template_entry) -#define TMPL_END_IDX \ - (optprobe_template_end - optprobe_template_entry) - -DEFINE_INSN_CACHE_OPS(ppc_optinsn); +#define TMPL_CALL_HDLR_IDX (optprobe_template_call_handler - optprobe_template_entry) +#define TMPL_EMULATE_IDX (optprobe_template_call_emulate - optprobe_template_entry) +#define TMPL_RET_IDX (optprobe_template_ret - optprobe_template_entry) +#define TMPL_OP_IDX (optprobe_template_op_address - optprobe_template_entry) +#define TMPL_INSN_IDX (optprobe_template_insn - optprobe_template_entry) +#define TMPL_END_IDX (optprobe_template_end - optprobe_template_entry) static bool insn_page_in_use; -static void *__ppc_alloc_insn_page(void) +void *alloc_optinsn_page(void) { if (insn_page_in_use) return NULL; @@ -43,20 +35,11 @@ static void *__ppc_alloc_insn_page(void) return &optinsn_slot; } -static void __ppc_free_insn_page(void *page __maybe_unused) +void free_optinsn_page(void *page) { insn_page_in_use = false; } -struct kprobe_insn_cache kprobe_ppc_optinsn_slots = { - .mutex = __MUTEX_INITIALIZER(kprobe_ppc_optinsn_slots.mutex), - .pages = LIST_HEAD_INIT(kprobe_ppc_optinsn_slots.pages), - /* insn_size initialized later */ - .alloc = __ppc_alloc_insn_page, - .free = __ppc_free_insn_page, - .nr_garbage = 0, -}; - /* * Check if we can optimize this probe. Returns NIP post-emulation if this can * be optimized and 0 otherwise. @@ -66,6 +49,7 @@ static unsigned long can_optimize(struct kprobe *p) struct pt_regs regs; struct instruction_op op; unsigned long nip = 0; + unsigned long addr = (unsigned long)p->addr; /* * kprobe placed for kretprobe during boot time @@ -73,7 +57,7 @@ static unsigned long can_optimize(struct kprobe *p) * So further checks can be skipped. */ if (p->addr == (kprobe_opcode_t *)&kretprobe_trampoline) - return (unsigned long)p->addr + sizeof(kprobe_opcode_t); + return addr + sizeof(kprobe_opcode_t); /* * We only support optimizing kernel addresses, but not @@ -81,11 +65,11 @@ static unsigned long can_optimize(struct kprobe *p) * * FIXME: Optimize kprobes placed in module addresses. */ - if (!is_kernel_addr((unsigned long)p->addr)) + if (!is_kernel_addr(addr)) return 0; memset(®s, 0, sizeof(struct pt_regs)); - regs.nip = (unsigned long)p->addr; + regs.nip = addr; regs.trap = 0x0; regs.msr = MSR_KERNEL; @@ -100,9 +84,8 @@ static unsigned long can_optimize(struct kprobe *p) * Ensure that the instruction is not a conditional branch, * and that can be emulated. */ - if (!is_conditional_branch(ppc_inst_read((struct ppc_inst *)p->ainsn.insn)) && - analyse_instr(&op, ®s, - ppc_inst_read((struct ppc_inst *)p->ainsn.insn)) == 1) { + if (!is_conditional_branch(ppc_inst_read(p->ainsn.insn)) && + analyse_instr(&op, ®s, ppc_inst_read(p->ainsn.insn)) == 1) { emulate_update_regs(®s, &op); nip = regs.nip; } @@ -123,7 +106,7 @@ static void optimized_callback(struct optimized_kprobe *op, kprobes_inc_nmissed_count(&op->kp); } else { __this_cpu_write(current_kprobe, &op->kp); - regs->nip = (unsigned long)op->kp.addr; + regs_set_return_ip(regs, (unsigned long)op->kp.addr); get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE; opt_pre_handler(&op->kp, regs); __this_cpu_write(current_kprobe, NULL); @@ -136,19 +119,15 @@ NOKPROBE_SYMBOL(optimized_callback); void arch_remove_optimized_kprobe(struct optimized_kprobe *op) { if (op->optinsn.insn) { - free_ppc_optinsn_slot(op->optinsn.insn, 1); + free_optinsn_slot(op->optinsn.insn, 1); op->optinsn.insn = NULL; } } static void patch_imm32_load_insns(unsigned long val, int reg, kprobe_opcode_t *addr) { - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_RAW_LIS(reg, IMM_H(val)))); - addr++; - - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_RAW_ORI(reg, reg, IMM_L(val)))); + patch_instruction(addr++, ppc_inst(PPC_RAW_LIS(reg, PPC_HI(val)))); + patch_instruction(addr, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_LO(val)))); } /* @@ -157,34 +136,11 @@ static void patch_imm32_load_insns(unsigned long val, int reg, kprobe_opcode_t * */ static void patch_imm64_load_insns(unsigned long long val, int reg, kprobe_opcode_t *addr) { - /* lis reg,(op)@highest */ - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_INST_ADDIS | ___PPC_RT(reg) | - ((val >> 48) & 0xffff))); - addr++; - - /* ori reg,reg,(op)@higher */ - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_INST_ORI | ___PPC_RA(reg) | - ___PPC_RS(reg) | ((val >> 32) & 0xffff))); - addr++; - - /* rldicr reg,reg,32,31 */ - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_INST_RLDICR | ___PPC_RA(reg) | - ___PPC_RS(reg) | __PPC_SH64(32) | __PPC_ME64(31))); - addr++; - - /* oris reg,reg,(op)@h */ - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_INST_ORIS | ___PPC_RA(reg) | - ___PPC_RS(reg) | ((val >> 16) & 0xffff))); - addr++; - - /* ori reg,reg,(op)@l */ - patch_instruction((struct ppc_inst *)addr, - ppc_inst(PPC_INST_ORI | ___PPC_RA(reg) | - ___PPC_RS(reg) | (val & 0xffff))); + patch_instruction(addr++, ppc_inst(PPC_RAW_LIS(reg, PPC_HIGHEST(val)))); + patch_instruction(addr++, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_HIGHER(val)))); + patch_instruction(addr++, ppc_inst(PPC_RAW_SLDI(reg, reg, 32))); + patch_instruction(addr++, ppc_inst(PPC_RAW_ORIS(reg, reg, PPC_HI(val)))); + patch_instruction(addr, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_LO(val)))); } static void patch_imm_load_insns(unsigned long val, int reg, kprobe_opcode_t *addr) @@ -198,19 +154,18 @@ static void patch_imm_load_insns(unsigned long val, int reg, kprobe_opcode_t *ad int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *p) { struct ppc_inst branch_op_callback, branch_emulate_step, temp; - kprobe_opcode_t *op_callback_addr, *emulate_step_addr, *buff; + unsigned long op_callback_addr, emulate_step_addr; + kprobe_opcode_t *buff; long b_offset; unsigned long nip, size; int rc, i; - kprobe_ppc_optinsn_slots.insn_size = MAX_OPTINSN_SIZE; - nip = can_optimize(p); if (!nip) return -EILSEQ; /* Allocate instruction slot for detour buffer */ - buff = get_ppc_optinsn_slot(); + buff = get_optinsn_slot(); if (!buff) return -ENOMEM; @@ -228,8 +183,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *p) goto error; /* Check if the return address is also within 32MB range */ - b_offset = (unsigned long)(buff + TMPL_RET_IDX) - - (unsigned long)nip; + b_offset = (unsigned long)(buff + TMPL_RET_IDX) - nip; if (!is_offset_in_branch_range(b_offset)) goto error; @@ -238,8 +192,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *p) size = (TMPL_END_IDX * sizeof(kprobe_opcode_t)) / sizeof(int); pr_devel("Copying template to %p, size %lu\n", buff, size); for (i = 0; i < size; i++) { - rc = patch_instruction((struct ppc_inst *)(buff + i), - ppc_inst(*(optprobe_template_entry + i))); + rc = patch_instruction(buff + i, ppc_inst(*(optprobe_template_entry + i))); if (rc < 0) goto error; } @@ -253,51 +206,48 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *p) /* * 2. branch to optimized_callback() and emulate_step() */ - op_callback_addr = (kprobe_opcode_t *)ppc_kallsyms_lookup_name("optimized_callback"); - emulate_step_addr = (kprobe_opcode_t *)ppc_kallsyms_lookup_name("emulate_step"); + op_callback_addr = ppc_kallsyms_lookup_name("optimized_callback"); + emulate_step_addr = ppc_kallsyms_lookup_name("emulate_step"); if (!op_callback_addr || !emulate_step_addr) { WARN(1, "Unable to lookup optimized_callback()/emulate_step()\n"); goto error; } - rc = create_branch(&branch_op_callback, - (struct ppc_inst *)(buff + TMPL_CALL_HDLR_IDX), - (unsigned long)op_callback_addr, - BRANCH_SET_LINK); + rc = create_branch(&branch_op_callback, buff + TMPL_CALL_HDLR_IDX, + op_callback_addr, BRANCH_SET_LINK); - rc |= create_branch(&branch_emulate_step, - (struct ppc_inst *)(buff + TMPL_EMULATE_IDX), - (unsigned long)emulate_step_addr, - BRANCH_SET_LINK); + rc |= create_branch(&branch_emulate_step, buff + TMPL_EMULATE_IDX, + emulate_step_addr, BRANCH_SET_LINK); if (rc) goto error; - patch_instruction((struct ppc_inst *)(buff + TMPL_CALL_HDLR_IDX), - branch_op_callback); - patch_instruction((struct ppc_inst *)(buff + TMPL_EMULATE_IDX), - branch_emulate_step); + patch_instruction(buff + TMPL_CALL_HDLR_IDX, branch_op_callback); + patch_instruction(buff + TMPL_EMULATE_IDX, branch_emulate_step); /* * 3. load instruction to be emulated into relevant register, and */ - temp = ppc_inst_read((struct ppc_inst *)p->ainsn.insn); - patch_imm_load_insns(ppc_inst_as_ulong(temp), 4, buff + TMPL_INSN_IDX); + if (IS_ENABLED(CONFIG_PPC64)) { + temp = ppc_inst_read(p->ainsn.insn); + patch_imm_load_insns(ppc_inst_as_ulong(temp), 4, buff + TMPL_INSN_IDX); + } else { + patch_imm_load_insns((unsigned long)p->ainsn.insn, 4, buff + TMPL_INSN_IDX); + } /* * 4. branch back from trampoline */ - patch_branch((struct ppc_inst *)(buff + TMPL_RET_IDX), (unsigned long)nip, 0); + patch_branch(buff + TMPL_RET_IDX, nip, 0); - flush_icache_range((unsigned long)buff, - (unsigned long)(&buff[TMPL_END_IDX])); + flush_icache_range((unsigned long)buff, (unsigned long)(&buff[TMPL_END_IDX])); op->optinsn.insn = buff; return 0; error: - free_ppc_optinsn_slot(buff, 0); + free_optinsn_slot(buff, 0); return -ERANGE; } @@ -328,12 +278,9 @@ void arch_optimize_kprobes(struct list_head *oplist) * Backup instructions which will be replaced * by jump address */ - memcpy(op->optinsn.copied_insn, op->kp.addr, - RELATIVEJUMP_SIZE); - create_branch(&instr, - (struct ppc_inst *)op->kp.addr, - (unsigned long)op->optinsn.insn, 0); - patch_instruction((struct ppc_inst *)op->kp.addr, instr); + memcpy(op->optinsn.copied_insn, op->kp.addr, RELATIVEJUMP_SIZE); + create_branch(&instr, op->kp.addr, (unsigned long)op->optinsn.insn, 0); + patch_instruction(op->kp.addr, instr); list_del_init(&op->list); } } @@ -343,8 +290,7 @@ void arch_unoptimize_kprobe(struct optimized_kprobe *op) arch_arm_kprobe(&op->kp); } -void arch_unoptimize_kprobes(struct list_head *oplist, - struct list_head *done_list) +void arch_unoptimize_kprobes(struct list_head *oplist, struct list_head *done_list) { struct optimized_kprobe *op; struct optimized_kprobe *tmp; @@ -355,8 +301,7 @@ void arch_unoptimize_kprobes(struct list_head *oplist, } } -int arch_within_optimized_kprobe(struct optimized_kprobe *op, - unsigned long addr) +int arch_within_optimized_kprobe(struct optimized_kprobe *op, unsigned long addr) { return ((unsigned long)op->kp.addr <= addr && (unsigned long)op->kp.addr + RELATIVEJUMP_SIZE > addr); diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c index 7f5aae3c387d..9bd30cac852b 100644 --- a/arch/powerpc/kernel/paca.c +++ b/arch/powerpc/kernel/paca.c @@ -346,10 +346,8 @@ void copy_mm_to_paca(struct mm_struct *mm) #ifdef CONFIG_PPC_BOOK3S mm_context_t *context = &mm->context; - get_paca()->mm_ctx_id = context->id; #ifdef CONFIG_PPC_MM_SLICES VM_BUG_ON(!mm_ctx_slb_addr_limit(context)); - get_paca()->mm_ctx_slb_addr_limit = mm_ctx_slb_addr_limit(context); memcpy(&get_paca()->mm_ctx_low_slices_psize, mm_ctx_low_slices(context), LOW_SLICE_ARRAY_SZ); memcpy(&get_paca()->mm_ctx_high_slices_psize, mm_ctx_high_slices(context), diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8935c5696bce..185beb290580 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -96,7 +96,8 @@ static void check_if_tm_restore_required(struct task_struct *tsk) if (tsk == current && tsk->thread.regs && MSR_TM_ACTIVE(tsk->thread.regs->msr) && !test_thread_flag(TIF_RESTORE_TM)) { - tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; + regs_set_return_msr(&tsk->thread.ckpt_regs, + tsk->thread.regs->msr); set_thread_flag(TIF_RESTORE_TM); } } @@ -161,7 +162,7 @@ static void __giveup_fpu(struct task_struct *tsk) msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); if (cpu_has_feature(CPU_FTR_VSX)) msr &= ~MSR_VSX; - tsk->thread.regs->msr = msr; + regs_set_return_msr(tsk->thread.regs, msr); } void giveup_fpu(struct task_struct *tsk) @@ -244,7 +245,7 @@ static void __giveup_altivec(struct task_struct *tsk) msr &= ~MSR_VEC; if (cpu_has_feature(CPU_FTR_VSX)) msr &= ~MSR_VSX; - tsk->thread.regs->msr = msr; + regs_set_return_msr(tsk->thread.regs, msr); } void giveup_altivec(struct task_struct *tsk) @@ -559,7 +560,7 @@ void notrace restore_math(struct pt_regs *regs) msr_check_and_clear(new_msr); - regs->msr |= new_msr | fpexc_mode; + regs_set_return_msr(regs, regs->msr | new_msr | fpexc_mode); } } #endif /* CONFIG_PPC_BOOK3S_64 */ @@ -1114,7 +1115,7 @@ void restore_tm_state(struct pt_regs *regs) #endif restore_math(regs); - regs->msr |= msr_diff; + regs_set_return_msr(regs, regs->msr | msr_diff); } #else /* !CONFIG_PPC_TRANSACTIONAL_MEM */ @@ -1129,6 +1130,10 @@ static inline void save_sprs(struct thread_struct *t) if (cpu_has_feature(CPU_FTR_ALTIVEC)) t->vrsave = mfspr(SPRN_VRSAVE); #endif +#ifdef CONFIG_SPE + if (cpu_has_feature(CPU_FTR_SPE)) + t->spefscr = mfspr(SPRN_SPEFSCR); +#endif #ifdef CONFIG_PPC_BOOK3S_64 if (cpu_has_feature(CPU_FTR_DSCR)) t->dscr = mfspr(SPRN_DSCR); @@ -1159,6 +1164,11 @@ static inline void restore_sprs(struct thread_struct *old_thread, old_thread->vrsave != new_thread->vrsave) mtspr(SPRN_VRSAVE, new_thread->vrsave); #endif +#ifdef CONFIG_SPE + if (cpu_has_feature(CPU_FTR_SPE) && + old_thread->spefscr != new_thread->spefscr) + mtspr(SPRN_SPEFSCR, new_thread->spefscr); +#endif #ifdef CONFIG_PPC_BOOK3S_64 if (cpu_has_feature(CPU_FTR_DSCR)) { u64 dscr = get_paca()->dscr_default; @@ -1213,6 +1223,19 @@ struct task_struct *__switch_to(struct task_struct *prev, __flush_tlb_pending(batch); batch->active = 0; } + + /* + * On POWER9 the copy-paste buffer can only paste into + * foreign real addresses, so unprivileged processes can not + * see the data or use it in any way unless they have + * foreign real mappings. If the new process has the foreign + * real address mappings, we must issue a cp_abort to clear + * any state and prevent snooping, corruption or a covert + * channel. ISA v3.1 supports paste into local memory. + */ + if (new->mm && (cpu_has_feature(CPU_FTR_ARCH_31) || + atomic_read(&new->mm->context.vas_windows))) + asm volatile(PPC_CP_ABORT); #endif /* CONFIG_PPC_BOOK3S_64 */ #ifdef CONFIG_PPC_ADV_DEBUG_REGS @@ -1248,43 +1271,48 @@ struct task_struct *__switch_to(struct task_struct *prev, } /* - * Call restore_sprs() before calling _switch(). If we move it after - * _switch() then we miss out on calling it for new tasks. The reason - * for this is we manually create a stack frame for new tasks that - * directly returns through ret_from_fork() or + * Call restore_sprs() and set_return_regs_changed() before calling + * _switch(). If we move it after _switch() then we miss out on calling + * it for new tasks. The reason for this is we manually create a stack + * frame for new tasks that directly returns through ret_from_fork() or * ret_from_kernel_thread(). See copy_thread() for details. */ restore_sprs(old_thread, new_thread); + set_return_regs_changed(); /* _switch changes stack (and regs) */ + #ifdef CONFIG_PPC32 kuap_assert_locked(); #endif last = _switch(old_thread, new_thread); + /* + * Nothing after _switch will be run for newly created tasks, + * because they switch directly to ret_from_fork/ret_from_kernel_thread + * etc. Code added here should have a comment explaining why that is + * okay. + */ + #ifdef CONFIG_PPC_BOOK3S_64 + /* + * This applies to a process that was context switched while inside + * arch_enter_lazy_mmu_mode(), to re-activate the batch that was + * deactivated above, before _switch(). This will never be the case + * for new tasks. + */ if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; batch = this_cpu_ptr(&ppc64_tlb_batch); batch->active = 1; } - if (current->thread.regs) { + /* + * Math facilities are masked out of the child MSR in copy_thread. + * A new task does not need to restore_math because it will + * demand fault them. + */ + if (current->thread.regs) restore_math(current->thread.regs); - - /* - * On POWER9 the copy-paste buffer can only paste into - * foreign real addresses, so unprivileged processes can not - * see the data or use it in any way unless they have - * foreign real mappings. If the new process has the foreign - * real address mappings, we must issue a cp_abort to clear - * any state and prevent snooping, corruption or a covert - * channel. ISA v3.1 supports paste into local memory. - */ - if (current->mm && - (cpu_has_feature(CPU_FTR_ARCH_31) || - atomic_read(¤t->mm->context.vas_windows))) - asm volatile(PPC_CP_ABORT); - } #endif /* CONFIG_PPC_BOOK3S_64 */ return last; @@ -1736,6 +1764,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, #ifdef CONFIG_ALTIVEC p->thread.vr_save_area = NULL; #endif +#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) + p->thread.kuap = KUAP_NONE; +#endif setup_ksp_vsid(p, sp); @@ -1838,13 +1869,14 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) } regs->gpr[2] = toc; } - regs->nip = entry; - regs->msr = MSR_USER64; + regs_set_return_ip(regs, entry); + regs_set_return_msr(regs, MSR_USER64); } else { - regs->nip = start; regs->gpr[2] = 0; - regs->msr = MSR_USER32; + regs_set_return_ip(regs, start); + regs_set_return_msr(regs, MSR_USER32); } + #endif #ifdef CONFIG_VSX current->thread.used_vsr = 0; @@ -1875,7 +1907,6 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) current->thread.tm_tfiar = 0; current->thread.load_tm = 0; #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ - } EXPORT_SYMBOL(start_thread); @@ -1923,9 +1954,10 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int val) if (val > PR_FP_EXC_PRECISE) return -EINVAL; tsk->thread.fpexc_mode = __pack_fe01(val); - if (regs != NULL && (regs->msr & MSR_FP) != 0) - regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) - | tsk->thread.fpexc_mode; + if (regs != NULL && (regs->msr & MSR_FP) != 0) { + regs_set_return_msr(regs, (regs->msr & ~(MSR_FE0|MSR_FE1)) + | tsk->thread.fpexc_mode); + } return 0; } @@ -1971,9 +2003,9 @@ int set_endian(struct task_struct *tsk, unsigned int val) return -EINVAL; if (val == PR_ENDIAN_BIG) - regs->msr &= ~MSR_LE; + regs_set_return_msr(regs, regs->msr & ~MSR_LE); else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) - regs->msr |= MSR_LE; + regs_set_return_msr(regs, regs->msr | MSR_LE); else return -EINVAL; @@ -2121,8 +2153,9 @@ unsigned long get_wchan(struct task_struct *p) static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; -void show_stack(struct task_struct *tsk, unsigned long *stack, - const char *loglvl) +void __no_sanitize_address show_stack(struct task_struct *tsk, + unsigned long *stack, + const char *loglvl) { unsigned long sp, ip, lr, newsp; int count = 0; diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index fbe9deebc8e1..f620e04dc9bf 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -758,7 +758,7 @@ void __init early_init_devtree(void *params) first_memblock_size = min_t(u64, first_memblock_size, memory_limit); setup_initial_memory_limit(memstart_addr, first_memblock_size); /* Reserve MEMBLOCK regions used by kernel, initrd, dt, etc... */ - memblock_reserve(PHYSICAL_START, __pa(klimit) - PHYSICAL_START); + memblock_reserve(PHYSICAL_START, __pa(_end) - PHYSICAL_START); /* If relocatable, reserve first 32k for interrupt vectors etc. */ if (PHYSICAL_START > MEMORY_START) memblock_reserve(MEMORY_START, 0x8000); diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 41ed7e33d897..a5bf355ce1d6 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -27,10 +27,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -242,13 +244,31 @@ static int __init prom_strcmp(const char *cs, const char *ct) return 0; } -static char __init *prom_strcpy(char *dest, const char *src) +static ssize_t __init prom_strscpy_pad(char *dest, const char *src, size_t n) { - char *tmp = dest; + ssize_t rc; + size_t i; - while ((*dest++ = *src++) != '\0') - /* nothing */; - return tmp; + if (n == 0 || n > INT_MAX) + return -E2BIG; + + // Copy up to n bytes + for (i = 0; i < n && src[i] != '\0'; i++) + dest[i] = src[i]; + + rc = i; + + // If we copied all n then we have run out of space for the nul + if (rc == n) { + // Rewind by one character to ensure nul termination + i--; + rc = -E2BIG; + } + + for (; i < n; i++) + dest[i] = '\0'; + + return rc; } static int __init prom_strncmp(const char *cs, const char *ct, size_t count) @@ -701,13 +721,12 @@ static int __init prom_setprop(phandle node, const char *nodename, } /* We can't use the standard versions because of relocation headaches. */ -#define isxdigit(c) (('0' <= (c) && (c) <= '9') \ - || ('a' <= (c) && (c) <= 'f') \ - || ('A' <= (c) && (c) <= 'F')) +#define prom_isxdigit(c) \ + (('0' <= (c) && (c) <= '9') || ('a' <= (c) && (c) <= 'f') || ('A' <= (c) && (c) <= 'F')) -#define isdigit(c) ('0' <= (c) && (c) <= '9') -#define islower(c) ('a' <= (c) && (c) <= 'z') -#define toupper(c) (islower(c) ? ((c) - 'a' + 'A') : (c)) +#define prom_isdigit(c) ('0' <= (c) && (c) <= '9') +#define prom_islower(c) ('a' <= (c) && (c) <= 'z') +#define prom_toupper(c) (prom_islower(c) ? ((c) - 'a' + 'A') : (c)) static unsigned long prom_strtoul(const char *cp, const char **endp) { @@ -716,14 +735,14 @@ static unsigned long prom_strtoul(const char *cp, const char **endp) if (*cp == '0') { base = 8; cp++; - if (toupper(*cp) == 'X') { + if (prom_toupper(*cp) == 'X') { cp++; base = 16; } } - while (isxdigit(*cp) && - (value = isdigit(*cp) ? *cp - '0' : toupper(*cp) - 'A' + 10) < base) { + while (prom_isxdigit(*cp) && + (value = prom_isdigit(*cp) ? *cp - '0' : prom_toupper(*cp) - 'A' + 10) < base) { result = result * base + value; cp++; } @@ -927,6 +946,10 @@ struct option_vector6 { u8 os_name; } __packed; +struct option_vector7 { + u8 os_id[256]; +} __packed; + struct ibm_arch_vec { struct { u32 mask, val; } pvrs[14]; @@ -949,6 +972,9 @@ struct ibm_arch_vec { u8 vec6_len; struct option_vector6 vec6; + + u8 vec7_len; + struct option_vector7 vec7; } __packed; static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = { @@ -1095,6 +1121,9 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = { .secondary_pteg = 0, .os_name = OV6_LINUX, }, + + /* option vector 7: OS Identification */ + .vec7_len = VECTOR_LENGTH(sizeof(struct option_vector7)), }; static struct ibm_arch_vec __prombss ibm_architecture_vec ____cacheline_aligned; @@ -1323,6 +1352,8 @@ static void __init prom_check_platform_support(void) memcpy(&ibm_architecture_vec, &ibm_architecture_vec_template, sizeof(ibm_architecture_vec)); + prom_strscpy_pad(ibm_architecture_vec.vec7.os_id, linux_banner, 256); + if (prop_len > 1) { int i; u8 vec[8]; @@ -1762,6 +1793,8 @@ static int prom_rtas_hcall(uint64_t args) asm volatile("sc 1\n" : "=r" (arg1) : "r" (arg1), "r" (arg2) :); + srr_regs_clobbered(); + return arg1; } @@ -2702,7 +2735,7 @@ static void __init flatten_device_tree(void) /* Add "phandle" in there, we'll need it */ namep = make_room(&mem_start, &mem_end, 16, 1); - prom_strcpy(namep, "phandle"); + prom_strscpy_pad(namep, "phandle", sizeof("phandle")); mem_start = (unsigned long)namep + prom_strlen(namep) + 1; /* Build string array */ @@ -3210,54 +3243,6 @@ static void __init prom_check_initrd(unsigned long r3, unsigned long r4) #endif /* CONFIG_BLK_DEV_INITRD */ } -#ifdef CONFIG_PPC64 -#ifdef CONFIG_RELOCATABLE -static void reloc_toc(void) -{ -} - -static void unreloc_toc(void) -{ -} -#else -static void __reloc_toc(unsigned long offset, unsigned long nr_entries) -{ - unsigned long i; - unsigned long *toc_entry; - - /* Get the start of the TOC by using r2 directly. */ - asm volatile("addi %0,2,-0x8000" : "=b" (toc_entry)); - - for (i = 0; i < nr_entries; i++) { - *toc_entry = *toc_entry + offset; - toc_entry++; - } -} - -static void reloc_toc(void) -{ - unsigned long offset = reloc_offset(); - unsigned long nr_entries = - (__prom_init_toc_end - __prom_init_toc_start) / sizeof(long); - - __reloc_toc(offset, nr_entries); - - mb(); -} - -static void unreloc_toc(void) -{ - unsigned long offset = reloc_offset(); - unsigned long nr_entries = - (__prom_init_toc_end - __prom_init_toc_start) / sizeof(long); - - mb(); - - __reloc_toc(-offset, nr_entries); -} -#endif -#endif - #ifdef CONFIG_PPC_SVM /* * Perform the Enter Secure Mode ultracall. @@ -3291,14 +3276,12 @@ static void __init setup_secure_guest(unsigned long kbase, unsigned long fdt) * relocated it so the check will fail. Restore the original image by * relocating it back to the kernel virtual base address. */ - if (IS_ENABLED(CONFIG_RELOCATABLE)) - relocate(KERNELBASE); + relocate(KERNELBASE); ret = enter_secure_mode(kbase, fdt); /* Relocate the kernel again. */ - if (IS_ENABLED(CONFIG_RELOCATABLE)) - relocate(kbase); + relocate(kbase); if (ret != U_SUCCESS) { prom_printf("Returned %d from switching to secure mode.\n", ret); @@ -3326,8 +3309,6 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4, #ifdef CONFIG_PPC32 unsigned long offset = reloc_offset(); reloc_got2(offset); -#else - reloc_toc(); #endif /* @@ -3504,8 +3485,6 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4, #ifdef CONFIG_PPC32 reloc_got2(-offset); -#else - unreloc_toc(); #endif /* Move to secure memory if we're supposed to be secure guests. */ diff --git a/arch/powerpc/kernel/ptrace/ptrace-adv.c b/arch/powerpc/kernel/ptrace/ptrace-adv.c index 3990c01ef8cf..399f5d94a3df 100644 --- a/arch/powerpc/kernel/ptrace/ptrace-adv.c +++ b/arch/powerpc/kernel/ptrace/ptrace-adv.c @@ -12,7 +12,7 @@ void user_enable_single_step(struct task_struct *task) if (regs != NULL) { task->thread.debug.dbcr0 &= ~DBCR0_BT; task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); } set_tsk_thread_flag(task, TIF_SINGLESTEP); } @@ -24,7 +24,7 @@ void user_enable_block_step(struct task_struct *task) if (regs != NULL) { task->thread.debug.dbcr0 &= ~DBCR0_IC; task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); } set_tsk_thread_flag(task, TIF_SINGLESTEP); } @@ -50,7 +50,7 @@ void user_disable_single_step(struct task_struct *task) * All debug events were off..... */ task->thread.debug.dbcr0 &= ~DBCR0_IDM; - regs->msr &= ~MSR_DE; + regs_set_return_msr(regs, regs->msr & ~MSR_DE); } } clear_tsk_thread_flag(task, TIF_SINGLESTEP); @@ -82,6 +82,7 @@ int ptrace_get_debugreg(struct task_struct *child, unsigned long addr, int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data) { + struct pt_regs *regs = task->thread.regs; #ifdef CONFIG_HAVE_HW_BREAKPOINT int ret; struct thread_struct *thread = &task->thread; @@ -112,7 +113,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned l dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, task->thread.debug.dbcr1)) { - task->thread.regs->msr &= ~MSR_DE; + regs_set_return_msr(regs, regs->msr & ~MSR_DE); task->thread.debug.dbcr0 &= ~DBCR0_IDM; } return 0; @@ -132,7 +133,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned l dbcr_dac(task) |= DBCR_DAC1R; if (data & 0x2UL) dbcr_dac(task) |= DBCR_DAC1W; - task->thread.regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); return 0; } @@ -220,7 +221,7 @@ static long set_instruction_bp(struct task_struct *child, } out: child->thread.debug.dbcr0 |= DBCR0_IDM; - child->thread.regs->msr |= MSR_DE; + regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); return slot; } @@ -336,7 +337,7 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) return -ENOSPC; } child->thread.debug.dbcr0 |= DBCR0_IDM; - child->thread.regs->msr |= MSR_DE; + regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); return slot + 4; } @@ -430,7 +431,7 @@ static int set_dac_range(struct task_struct *child, child->thread.debug.dbcr2 |= DBCR2_DAC12MX; else /* PPC_BREAKPOINT_MODE_MASK */ child->thread.debug.dbcr2 |= DBCR2_DAC12MM; - child->thread.regs->msr |= MSR_DE; + regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); return 5; } @@ -485,7 +486,8 @@ long ppc_del_hwdebug(struct task_struct *child, long data) if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, child->thread.debug.dbcr1)) { child->thread.debug.dbcr0 &= ~DBCR0_IDM; - child->thread.regs->msr &= ~MSR_DE; + regs_set_return_msr(child->thread.regs, + child->thread.regs->msr & ~MSR_DE); } } return rc; diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c b/arch/powerpc/kernel/ptrace/ptrace-noadv.c index aa36fcad36cd..a5dd7d2e2c9e 100644 --- a/arch/powerpc/kernel/ptrace/ptrace-noadv.c +++ b/arch/powerpc/kernel/ptrace/ptrace-noadv.c @@ -11,10 +11,8 @@ void user_enable_single_step(struct task_struct *task) { struct pt_regs *regs = task->thread.regs; - if (regs != NULL) { - regs->msr &= ~MSR_BE; - regs->msr |= MSR_SE; - } + if (regs != NULL) + regs_set_return_msr(regs, (regs->msr & ~MSR_BE) | MSR_SE); set_tsk_thread_flag(task, TIF_SINGLESTEP); } @@ -22,10 +20,8 @@ void user_enable_block_step(struct task_struct *task) { struct pt_regs *regs = task->thread.regs; - if (regs != NULL) { - regs->msr &= ~MSR_SE; - regs->msr |= MSR_BE; - } + if (regs != NULL) + regs_set_return_msr(regs, (regs->msr & ~MSR_SE) | MSR_BE); set_tsk_thread_flag(task, TIF_SINGLESTEP); } @@ -34,7 +30,7 @@ void user_disable_single_step(struct task_struct *task) struct pt_regs *regs = task->thread.regs; if (regs != NULL) - regs->msr &= ~(MSR_SE | MSR_BE); + regs_set_return_msr(regs, regs->msr & ~(MSR_SE | MSR_BE)); clear_tsk_thread_flag(task, TIF_SINGLESTEP); } diff --git a/arch/powerpc/kernel/ptrace/ptrace-view.c b/arch/powerpc/kernel/ptrace/ptrace-view.c index 773bcc4ca843..b8be1d6668b5 100644 --- a/arch/powerpc/kernel/ptrace/ptrace-view.c +++ b/arch/powerpc/kernel/ptrace/ptrace-view.c @@ -113,8 +113,9 @@ static unsigned long get_user_msr(struct task_struct *task) static __always_inline int set_user_msr(struct task_struct *task, unsigned long msr) { - task->thread.regs->msr &= ~MSR_DEBUGCHANGE; - task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; + unsigned long newmsr = (task->thread.regs->msr & ~MSR_DEBUGCHANGE) | + (msr & MSR_DEBUGCHANGE); + regs_set_return_msr(task->thread.regs, newmsr); return 0; } diff --git a/arch/powerpc/kernel/rtas-rtc.c b/arch/powerpc/kernel/rtas-rtc.c index a28239b8b0c0..33c07c8af6c8 100644 --- a/arch/powerpc/kernel/rtas-rtc.c +++ b/arch/powerpc/kernel/rtas-rtc.c @@ -12,7 +12,7 @@ #define MAX_RTC_WAIT 5000 /* 5 sec */ -#define RTAS_CLOCK_BUSY (-2) + time64_t __init rtas_get_boot_time(void) { int ret[8]; diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 6bada744402b..99f2cce635fb 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -46,6 +47,13 @@ /* This is here deliberately so it's only used in this file */ void enter_rtas(unsigned long); +static inline void do_enter_rtas(unsigned long args) +{ + enter_rtas(args); + + srr_regs_clobbered(); /* rtas uses SRRs, invalidate */ +} + struct rtas_t rtas = { .lock = __ARCH_SPIN_LOCK_UNLOCKED }; @@ -384,7 +392,7 @@ static char *__fetch_rtas_last_error(char *altbuf) save_args = rtas.args; rtas.args = err_args; - enter_rtas(__pa(&rtas.args)); + do_enter_rtas(__pa(&rtas.args)); err_args = rtas.args; rtas.args = save_args; @@ -430,7 +438,7 @@ va_rtas_call_unlocked(struct rtas_args *args, int token, int nargs, int nret, for (i = 0; i < nret; ++i) args->rets[i] = 0; - enter_rtas(__pa(args)); + do_enter_rtas(__pa(args)); } void rtas_call_unlocked(struct rtas_args *args, int token, int nargs, int nret, ...) @@ -1138,7 +1146,7 @@ SYSCALL_DEFINE1(rtas, struct rtas_args __user *, uargs) flags = lock_rtas(); rtas.args = args; - enter_rtas(__pa(&rtas.args)); + do_enter_rtas(__pa(&rtas.args)); args = rtas.args; /* A -1 return code indicates that the last command couldn't diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c index c17d1c9362b5..cc51fa52e783 100644 --- a/arch/powerpc/kernel/security.c +++ b/arch/powerpc/kernel/security.c @@ -300,9 +300,7 @@ static void stf_barrier_enable(bool enable) void setup_stf_barrier(void) { enum stf_barrier_type type; - bool enable, hv; - - hv = cpu_has_feature(CPU_FTR_HVMODE); + bool enable; /* Default to fallback in case fw-features are not available */ if (cpu_has_feature(CPU_FTR_ARCH_300)) @@ -315,8 +313,7 @@ void setup_stf_barrier(void) type = STF_BARRIER_NONE; enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && - (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || - (security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) && hv)); + security_ftr_enabled(SEC_FTR_STF_BARRIER); if (type == STF_BARRIER_FALLBACK) { pr_info("stf-barrier: fallback barrier available\n"); @@ -439,8 +436,8 @@ static void update_branch_cache_flush(void) site2 = &patch__call_kvm_flush_link_stack_p9; // This controls the branch from guest_exit_cont to kvm_flush_link_stack if (link_stack_flush_type == BRANCH_CACHE_FLUSH_NONE) { - patch_instruction_site(site, ppc_inst(PPC_INST_NOP)); - patch_instruction_site(site2, ppc_inst(PPC_INST_NOP)); + patch_instruction_site(site, ppc_inst(PPC_RAW_NOP())); + patch_instruction_site(site2, ppc_inst(PPC_RAW_NOP())); } else { // Could use HW flush, but that could also flush count cache patch_branch_site(site, (u64)&kvm_flush_link_stack, BRANCH_SET_LINK); @@ -450,11 +447,11 @@ static void update_branch_cache_flush(void) // Patch out the bcctr first, then nop the rest site = &patch__call_flush_branch_caches3; - patch_instruction_site(site, ppc_inst(PPC_INST_NOP)); + patch_instruction_site(site, ppc_inst(PPC_RAW_NOP())); site = &patch__call_flush_branch_caches2; - patch_instruction_site(site, ppc_inst(PPC_INST_NOP)); + patch_instruction_site(site, ppc_inst(PPC_RAW_NOP())); site = &patch__call_flush_branch_caches1; - patch_instruction_site(site, ppc_inst(PPC_INST_NOP)); + patch_instruction_site(site, ppc_inst(PPC_RAW_NOP())); // This controls the branch from _switch to flush_branch_caches if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE && @@ -477,12 +474,12 @@ static void update_branch_cache_flush(void) // If we just need to flush the link stack, early return if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE) { patch_instruction_site(&patch__flush_link_stack_return, - ppc_inst(PPC_INST_BLR)); + ppc_inst(PPC_RAW_BLR())); // If we have flush instruction, early return } else if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW) { patch_instruction_site(&patch__flush_count_cache_return, - ppc_inst(PPC_INST_BLR)); + ppc_inst(PPC_RAW_BLR())); } } } diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 74a98fff2c2f..26328fd2990c 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -9,6 +9,7 @@ #undef DEBUG #include +#include #include #include #include @@ -91,8 +92,6 @@ EXPORT_SYMBOL_GPL(boot_cpuid); int dcache_bsize; int icache_bsize; -unsigned long klimit = (unsigned long) _end; - /* * This still seems to be needed... -- paulus */ @@ -930,7 +929,7 @@ void __init setup_arch(char **cmdline_p) init_mm.start_code = (unsigned long)_stext; init_mm.end_code = (unsigned long) _etext; init_mm.end_data = (unsigned long) _edata; - init_mm.brk = klimit; + init_mm.brk = (unsigned long)_end; mm_iommu_init(&init_mm); irqstack_early_init(); diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index d7c1f92152af..7ec5c47fce0e 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -74,7 +74,7 @@ EXPORT_SYMBOL(DMA_MODE_WRITE); */ notrace void __init machine_init(u64 dt_ptr) { - struct ppc_inst *addr = (struct ppc_inst *)patch_site_addr(&patch__memset_nocache); + u32 *addr = (u32 *)patch_site_addr(&patch__memset_nocache); struct ppc_inst insn; /* Configure static keys first, now that we're relocated. */ @@ -85,7 +85,7 @@ notrace void __init machine_init(u64 dt_ptr) /* Enable early debugging if any specified (see udbg.h) */ udbg_early_init(); - patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_INST_NOP)); + patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_RAW_NOP())); create_cond_branch(&insn, addr, branch_target(addr), 0x820000); patch_instruction(addr, insn); /* replace b by bne cr0 */ diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index a35fbf4d0bce..1ff258f6c76c 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -939,16 +940,20 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh) * disable it by default. Book3S has a soft-nmi hardlockup detector based * on the decrementer interrupt, so it does not suffer from this problem. * - * It is likely to get false positives in VM guests, so disable it there - * by default too. + * It is likely to get false positives in KVM guests, so disable it there + * by default too. PowerVM will not stop or arbitrarily oversubscribe + * CPUs, but give a minimum regular allotment even with SPLPAR, so enable + * the detector for non-KVM guests, assume PowerVM. */ static int __init disable_hardlockup_detector(void) { #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF hardlockup_detector_disable(); #else - if (firmware_has_feature(FW_FEATURE_LPAR)) - hardlockup_detector_disable(); + if (firmware_has_feature(FW_FEATURE_LPAR)) { + if (is_kvm_guest()) + hardlockup_detector_disable(); + } #endif return 0; diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index 9ded046edb0e..e600764a926c 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -214,7 +214,7 @@ static void check_syscall_restart(struct pt_regs *regs, struct k_sigaction *ka, regs->gpr[0] = __NR_restart_syscall; else regs->gpr[3] = regs->orig_gpr3; - regs->nip -= 4; + regs_add_return_ip(regs, -4); regs->result = 0; } else { if (trap_is_scv(regs)) { @@ -322,16 +322,16 @@ static unsigned long get_tm_stackpointer(struct task_struct *tsk) * For signals taken in non-TM or suspended mode, we use the * normal/non-checkpointed stack pointer. */ - - unsigned long ret = tsk->thread.regs->gpr[1]; + struct pt_regs *regs = tsk->thread.regs; + unsigned long ret = regs->gpr[1]; #ifdef CONFIG_PPC_TRANSACTIONAL_MEM BUG_ON(tsk != current); - if (MSR_TM_ACTIVE(tsk->thread.regs->msr)) { + if (MSR_TM_ACTIVE(regs->msr)) { preempt_disable(); tm_reclaim_current(TM_CAUSE_SIGNAL); - if (MSR_TM_TRANSACTIONAL(tsk->thread.regs->msr)) + if (MSR_TM_TRANSACTIONAL(regs->msr)) ret = tsk->thread.ckpt_regs.gpr[1]; /* @@ -341,7 +341,7 @@ static unsigned long get_tm_stackpointer(struct task_struct *tsk) * (tm_recheckpoint_new_task() would recheckpoint). Besides, we * enter the signal handler in non-transactional state. */ - tsk->thread.regs->msr &= ~MSR_TS_MASK; + regs_set_return_msr(regs, regs->msr & ~MSR_TS_MASK); preempt_enable(); } #endif diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 8f05ed0da292..0608581967f0 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -354,14 +354,8 @@ static void prepare_save_tm_user_regs(void) { WARN_ON(tm_suspend_disabled); -#ifdef CONFIG_ALTIVEC if (cpu_has_feature(CPU_FTR_ALTIVEC)) current->thread.ckvrsave = mfspr(SPRN_VRSAVE); -#endif -#ifdef CONFIG_SPE - if (current->thread.used_spe) - flush_spe_to_thread(current); -#endif } static int save_tm_user_regs_unsafe(struct pt_regs *regs, struct mcontext __user *frame, @@ -379,7 +373,6 @@ static int save_tm_user_regs_unsafe(struct pt_regs *regs, struct mcontext __user */ unsafe_put_user((msr >> 32), &tm_frame->mc_gregs[PT_MSR], failed); -#ifdef CONFIG_ALTIVEC /* save altivec registers */ if (current->thread.used_vr) { unsafe_copy_to_user(&frame->mc_vregs, ¤t->thread.ckvr_state, @@ -412,7 +405,6 @@ static int save_tm_user_regs_unsafe(struct pt_regs *regs, struct mcontext __user else unsafe_put_user(current->thread.ckvrsave, (u32 __user *)&tm_frame->mc_vregs[32], failed); -#endif /* CONFIG_ALTIVEC */ unsafe_copy_ckfpr_to_user(&frame->mc_fregs, current, failed); if (msr & MSR_FP) @@ -420,7 +412,6 @@ static int save_tm_user_regs_unsafe(struct pt_regs *regs, struct mcontext __user else unsafe_copy_ckfpr_to_user(&tm_frame->mc_fregs, current, failed); -#ifdef CONFIG_VSX /* * Copy VSR 0-31 upper half from thread_struct to local * buffer, then write that to userspace. Also set MSR_VSX in @@ -436,23 +427,6 @@ static int save_tm_user_regs_unsafe(struct pt_regs *regs, struct mcontext __user msr |= MSR_VSX; } -#endif /* CONFIG_VSX */ -#ifdef CONFIG_SPE - /* SPE regs are not checkpointed with TM, so this section is - * simply the same as in __unsafe_save_user_regs(). - */ - if (current->thread.used_spe) { - unsafe_copy_to_user(&frame->mc_vregs, current->thread.evr, - ELF_NEVRREG * sizeof(u32), failed); - /* set MSR_SPE in the saved MSR value to indicate that - * frame->mc_vregs contains valid data */ - msr |= MSR_SPE; - } - - /* We always copy to/from spefscr */ - unsafe_put_user(current->thread.spefscr, - (u32 __user *)&frame->mc_vregs + ELF_NEVRREG, failed); -#endif /* CONFIG_SPE */ unsafe_put_user(msr, &frame->mc_gregs[PT_MSR], failed); @@ -505,14 +479,14 @@ static long restore_user_regs(struct pt_regs *regs, /* if doing signal return, restore the previous little-endian mode */ if (sig) - regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (msr & MSR_LE)); #ifdef CONFIG_ALTIVEC /* * Force the process to reload the altivec registers from * current->thread when it next does altivec instructions */ - regs->msr &= ~MSR_VEC; + regs_set_return_msr(regs, regs->msr & ~MSR_VEC); if (msr & MSR_VEC) { /* restore altivec registers from the stack */ unsafe_copy_from_user(¤t->thread.vr_state, &sr->mc_vregs, @@ -534,7 +508,7 @@ static long restore_user_regs(struct pt_regs *regs, * Force the process to reload the VSX registers from * current->thread when it next does VSX instruction. */ - regs->msr &= ~MSR_VSX; + regs_set_return_msr(regs, regs->msr & ~MSR_VSX); if (msr & MSR_VSX) { /* * Restore altivec registers from the stack to a local @@ -550,12 +524,12 @@ static long restore_user_regs(struct pt_regs *regs, * force the process to reload the FP registers from * current->thread when it next does FP instructions */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); + regs_set_return_msr(regs, regs->msr & ~(MSR_FP | MSR_FE0 | MSR_FE1)); #ifdef CONFIG_SPE /* force the process to reload the spe registers from current->thread when it next does spe instructions */ - regs->msr &= ~MSR_SPE; + regs_set_return_msr(regs, regs->msr & ~MSR_SPE); if (msr & MSR_SPE) { /* restore spe registers from the stack */ unsafe_copy_from_user(current->thread.evr, &sr->mc_vregs, @@ -587,9 +561,7 @@ static long restore_tm_user_regs(struct pt_regs *regs, struct mcontext __user *tm_sr) { unsigned long msr, msr_hi; -#ifdef CONFIG_VSX int i; -#endif if (tm_suspend_disabled) return 1; @@ -608,10 +580,9 @@ static long restore_tm_user_regs(struct pt_regs *regs, unsafe_get_user(msr, &sr->mc_gregs[PT_MSR], failed); /* Restore the previous little-endian mode */ - regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (msr & MSR_LE)); -#ifdef CONFIG_ALTIVEC - regs->msr &= ~MSR_VEC; + regs_set_return_msr(regs, regs->msr & ~MSR_VEC); if (msr & MSR_VEC) { /* restore altivec registers from the stack */ unsafe_copy_from_user(¤t->thread.ckvr_state, &sr->mc_vregs, @@ -629,14 +600,12 @@ static long restore_tm_user_regs(struct pt_regs *regs, (u32 __user *)&sr->mc_vregs[32], failed); if (cpu_has_feature(CPU_FTR_ALTIVEC)) mtspr(SPRN_VRSAVE, current->thread.ckvrsave); -#endif /* CONFIG_ALTIVEC */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); + regs_set_return_msr(regs, regs->msr & ~(MSR_FP | MSR_FE0 | MSR_FE1)); unsafe_copy_fpr_from_user(current, &sr->mc_fregs, failed); -#ifdef CONFIG_VSX - regs->msr &= ~MSR_VSX; + regs_set_return_msr(regs, regs->msr & ~MSR_VSX); if (msr & MSR_VSX) { /* * Restore altivec registers from the stack to a local @@ -649,24 +618,6 @@ static long restore_tm_user_regs(struct pt_regs *regs, current->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = 0; current->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = 0; } -#endif /* CONFIG_VSX */ - -#ifdef CONFIG_SPE - /* SPE regs are not checkpointed with TM, so this section is - * simply the same as in restore_user_regs(). - */ - regs->msr &= ~MSR_SPE; - if (msr & MSR_SPE) { - unsafe_copy_from_user(current->thread.evr, &sr->mc_vregs, - ELF_NEVRREG * sizeof(u32), failed); - current->thread.used_spe = true; - } else if (current->thread.used_spe) - memset(current->thread.evr, 0, ELF_NEVRREG * sizeof(u32)); - - /* Always get SPEFSCR back */ - unsafe_get_user(current->thread.spefscr, - (u32 __user *)&sr->mc_vregs + ELF_NEVRREG, failed); -#endif /* CONFIG_SPE */ user_read_access_end(); @@ -675,7 +626,6 @@ static long restore_tm_user_regs(struct pt_regs *regs, unsafe_restore_general_regs(regs, tm_sr, failed); -#ifdef CONFIG_ALTIVEC /* restore altivec registers from the stack */ if (msr & MSR_VEC) unsafe_copy_from_user(¤t->thread.vr_state, &tm_sr->mc_vregs, @@ -684,11 +634,9 @@ static long restore_tm_user_regs(struct pt_regs *regs, /* Always get VRSAVE back */ unsafe_get_user(current->thread.vrsave, (u32 __user *)&tm_sr->mc_vregs[32], failed); -#endif /* CONFIG_ALTIVEC */ unsafe_copy_ckfpr_from_user(current, &tm_sr->mc_fregs, failed); -#ifdef CONFIG_VSX if (msr & MSR_VSX) { /* * Restore altivec registers from the stack to a local @@ -697,7 +645,6 @@ static long restore_tm_user_regs(struct pt_regs *regs, unsafe_copy_vsx_from_user(current, &tm_sr->mc_vsregs, failed); current->thread.used_vsr = true; } -#endif /* CONFIG_VSX */ /* Get the top half of the MSR from the user context */ unsafe_get_user(msr_hi, &tm_sr->mc_gregs[PT_MSR], failed); @@ -725,7 +672,7 @@ static long restore_tm_user_regs(struct pt_regs *regs, * * Pull in the MSR TM bits from the user context */ - regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr_hi & MSR_TS_MASK); + regs_set_return_msr(regs, (regs->msr & ~MSR_TS_MASK) | (msr_hi & MSR_TS_MASK)); /* Now, recheckpoint. This loads up all of the checkpointed (older) * registers, including FP and V[S]Rs. After recheckpointing, the * transactional versions should be loaded. @@ -740,14 +687,12 @@ static long restore_tm_user_regs(struct pt_regs *regs, msr_check_and_set(msr & (MSR_FP | MSR_VEC)); if (msr & MSR_FP) { load_fp_state(¤t->thread.fp_state); - regs->msr |= (MSR_FP | current->thread.fpexc_mode); + regs_set_return_msr(regs, regs->msr | (MSR_FP | current->thread.fpexc_mode)); } -#ifdef CONFIG_ALTIVEC if (msr & MSR_VEC) { load_vr_state(¤t->thread.vr_state); - regs->msr |= MSR_VEC; + regs_set_return_msr(regs, regs->msr | MSR_VEC); } -#endif preempt_enable(); @@ -828,10 +773,8 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset, tramp = VDSO32_SYMBOL(tsk->mm->context.vdso, sigtramp_rt32); } else { tramp = (unsigned long)mctx->mc_pad; - /* Set up the sigreturn trampoline: li r0,sigret; sc */ - unsafe_put_user(PPC_INST_ADDI + __NR_rt_sigreturn, &mctx->mc_pad[0], - failed); - unsafe_put_user(PPC_INST_SC, &mctx->mc_pad[1], failed); + unsafe_put_user(PPC_RAW_LI(_R0, __NR_rt_sigreturn), &mctx->mc_pad[0], failed); + unsafe_put_user(PPC_RAW_SC(), &mctx->mc_pad[1], failed); asm("dcbst %y0; sync; icbi %y0; sync" :: "Z" (mctx->mc_pad[0])); } unsafe_put_sigset_t(&frame->uc.uc_sigmask, oldset, failed); @@ -858,10 +801,10 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset, regs->gpr[4] = (unsigned long)&frame->info; regs->gpr[5] = (unsigned long)&frame->uc; regs->gpr[6] = (unsigned long)frame; - regs->nip = (unsigned long) ksig->ka.sa.sa_handler; + regs_set_return_ip(regs, (unsigned long) ksig->ka.sa.sa_handler); /* enter the signal handler in native-endian mode */ - regs->msr &= ~MSR_LE; - regs->msr |= (MSR_KERNEL & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (MSR_KERNEL & MSR_LE)); + return 0; failed: @@ -926,9 +869,8 @@ int handle_signal32(struct ksignal *ksig, sigset_t *oldset, tramp = VDSO32_SYMBOL(tsk->mm->context.vdso, sigtramp32); } else { tramp = (unsigned long)mctx->mc_pad; - /* Set up the sigreturn trampoline: li r0,sigret; sc */ - unsafe_put_user(PPC_INST_ADDI + __NR_sigreturn, &mctx->mc_pad[0], failed); - unsafe_put_user(PPC_INST_SC, &mctx->mc_pad[1], failed); + unsafe_put_user(PPC_RAW_LI(_R0, __NR_sigreturn), &mctx->mc_pad[0], failed); + unsafe_put_user(PPC_RAW_SC(), &mctx->mc_pad[1], failed); asm("dcbst %y0; sync; icbi %y0; sync" :: "Z" (mctx->mc_pad[0])); } user_access_end(); @@ -947,10 +889,10 @@ int handle_signal32(struct ksignal *ksig, sigset_t *oldset, regs->gpr[1] = newsp; regs->gpr[3] = ksig->sig; regs->gpr[4] = (unsigned long) sc; - regs->nip = (unsigned long)ksig->ka.sa.sa_handler; + regs_set_return_ip(regs, (unsigned long) ksig->ka.sa.sa_handler); /* enter the signal handler in native-endian mode */ - regs->msr &= ~MSR_LE; - regs->msr |= (MSR_KERNEL & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (MSR_KERNEL & MSR_LE)); + return 0; failed: @@ -1200,7 +1142,7 @@ SYSCALL_DEFINE0(rt_sigreturn) * set, and recheckpoint was not called. This avoid * hitting a TM Bad thing at RFID */ - regs->msr &= ~MSR_TS_MASK; + regs_set_return_msr(regs, regs->msr & ~MSR_TS_MASK); } /* Fall through, for non-TM restore */ #endif @@ -1289,7 +1231,7 @@ SYSCALL_DEFINE3(debug_setcontext, struct ucontext __user *, ctx, affect the contents of these registers. After this point, failure is a problem, anyway, and it's very unlikely unless the user is really doing something wrong. */ - regs->msr = new_msr; + regs_set_return_msr(regs, new_msr); #ifdef CONFIG_PPC_ADV_DEBUG_REGS current->thread.debug.dbcr0 = new_dbcr0; #endif diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index f9e1f5428b9e..1831bba0582e 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -354,7 +354,7 @@ static long notrace __unsafe_restore_sigcontext(struct task_struct *tsk, sigset_ /* get MSR separately, transfer the LE bit if doing signal return */ unsafe_get_user(msr, &sc->gp_regs[PT_MSR], efault_out); if (sig) - regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (msr & MSR_LE)); unsafe_get_user(regs->orig_gpr3, &sc->gp_regs[PT_ORIG_R3], efault_out); unsafe_get_user(regs->ctr, &sc->gp_regs[PT_CTR], efault_out); unsafe_get_user(regs->link, &sc->gp_regs[PT_LNK], efault_out); @@ -376,7 +376,7 @@ static long notrace __unsafe_restore_sigcontext(struct task_struct *tsk, sigset_ * This has to be done before copying stuff into tsk->thread.fpr/vr * for the reasons explained in the previous comment. */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); + regs_set_return_msr(regs, regs->msr & ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX)); #ifdef CONFIG_ALTIVEC unsafe_get_user(v_regs, &sc->v_regs, efault_out); @@ -468,7 +468,7 @@ static long restore_tm_sigcontexts(struct task_struct *tsk, return -EINVAL; /* pull in MSR LE from user context */ - regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (msr & MSR_LE)); /* The following non-GPR non-FPR non-VR state is also checkpointed: */ err |= __get_user(regs->ctr, &tm_sc->gp_regs[PT_CTR]); @@ -495,7 +495,7 @@ static long restore_tm_sigcontexts(struct task_struct *tsk, * This has to be done before copying stuff into tsk->thread.fpr/vr * for the reasons explained in the previous comment. */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); + regs_set_return_msr(regs, regs->msr & ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX)); #ifdef CONFIG_ALTIVEC err |= __get_user(v_regs, &sc->v_regs); @@ -565,7 +565,7 @@ static long restore_tm_sigcontexts(struct task_struct *tsk, preempt_disable(); /* pull in MSR TS bits from user context */ - regs->msr |= msr & MSR_TS_MASK; + regs_set_return_msr(regs, regs->msr | (msr & MSR_TS_MASK)); /* * Ensure that TM is enabled in regs->msr before we leave the signal @@ -583,7 +583,7 @@ static long restore_tm_sigcontexts(struct task_struct *tsk, * to be de-scheduled with MSR[TS] set but without calling * tm_recheckpoint(). This can cause a bug. */ - regs->msr |= MSR_TM; + regs_set_return_msr(regs, regs->msr | MSR_TM); /* This loads the checkpointed FP/VEC state, if used */ tm_recheckpoint(&tsk->thread); @@ -591,11 +591,11 @@ static long restore_tm_sigcontexts(struct task_struct *tsk, msr_check_and_set(msr & (MSR_FP | MSR_VEC)); if (msr & MSR_FP) { load_fp_state(&tsk->thread.fp_state); - regs->msr |= (MSR_FP | tsk->thread.fpexc_mode); + regs_set_return_msr(regs, regs->msr | (MSR_FP | tsk->thread.fpexc_mode)); } if (msr & MSR_VEC) { load_vr_state(&tsk->thread.vr_state); - regs->msr |= MSR_VEC; + regs_set_return_msr(regs, regs->msr | MSR_VEC); } preempt_enable(); @@ -618,15 +618,12 @@ static long setup_trampoline(unsigned int syscall, unsigned int __user *tramp) int i; long err = 0; - /* bctrl # call the handler */ - err |= __put_user(PPC_INST_BCTRL, &tramp[0]); - /* addi r1, r1, __SIGNAL_FRAMESIZE # Pop the dummy stackframe */ - err |= __put_user(PPC_INST_ADDI | __PPC_RT(R1) | __PPC_RA(R1) | - (__SIGNAL_FRAMESIZE & 0xffff), &tramp[1]); - /* li r0, __NR_[rt_]sigreturn| */ - err |= __put_user(PPC_INST_ADDI | (syscall & 0xffff), &tramp[2]); - /* sc */ - err |= __put_user(PPC_INST_SC, &tramp[3]); + /* Call the handler and pop the dummy stackframe*/ + err |= __put_user(PPC_RAW_BCTRL(), &tramp[0]); + err |= __put_user(PPC_RAW_ADDI(_R1, _R1, __SIGNAL_FRAMESIZE), &tramp[1]); + + err |= __put_user(PPC_RAW_LI(_R0, syscall), &tramp[2]); + err |= __put_user(PPC_RAW_SC(), &tramp[3]); /* Minimal traceback info */ for (i=TRAMP_TRACEBACK; i < TRAMP_SIZE ;i++) @@ -720,6 +717,7 @@ SYSCALL_DEFINE3(swapcontext, struct ucontext __user *, old_ctx, /* This returns like rt_sigreturn */ set_thread_flag(TIF_RESTOREALL); + return 0; efault_out: @@ -786,7 +784,7 @@ SYSCALL_DEFINE0(rt_sigreturn) * the MSR[TS] that came from user context later, at * restore_tm_sigcontexts. */ - regs->msr &= ~MSR_TS_MASK; + regs_set_return_msr(regs, regs->msr & ~MSR_TS_MASK); if (__get_user(msr, &uc->uc_mcontext.gp_regs[PT_MSR])) goto badframe; @@ -818,7 +816,8 @@ SYSCALL_DEFINE0(rt_sigreturn) * MSR[TS] set, but without CPU in the proper state, * causing a TM bad thing. */ - current->thread.regs->msr &= ~MSR_TS_MASK; + regs_set_return_msr(current->thread.regs, + current->thread.regs->msr & ~MSR_TS_MASK); if (!user_read_access_begin(&uc->uc_mcontext, sizeof(uc->uc_mcontext))) goto badframe; @@ -832,6 +831,7 @@ SYSCALL_DEFINE0(rt_sigreturn) goto badframe; set_thread_flag(TIF_RESTOREALL); + return 0; badframe_block: @@ -911,12 +911,12 @@ int handle_rt_signal64(struct ksignal *ksig, sigset_t *set, /* Set up to return from userspace. */ if (tsk->mm->context.vdso) { - regs->nip = VDSO64_SYMBOL(tsk->mm->context.vdso, sigtramp_rt64); + regs_set_return_ip(regs, VDSO64_SYMBOL(tsk->mm->context.vdso, sigtramp_rt64)); } else { err |= setup_trampoline(__NR_rt_sigreturn, &frame->tramp[0]); if (err) goto badframe; - regs->nip = (unsigned long) &frame->tramp[0]; + regs_set_return_ip(regs, (unsigned long) &frame->tramp[0]); } /* Allocate a dummy caller frame for the signal handler. */ @@ -941,14 +941,13 @@ int handle_rt_signal64(struct ksignal *ksig, sigset_t *set, } /* enter the signal handler in native-endian mode */ - regs->msr &= ~MSR_LE; - regs->msr |= (MSR_KERNEL & MSR_LE); + regs_set_return_msr(regs, (regs->msr & ~MSR_LE) | (MSR_KERNEL & MSR_LE)); regs->gpr[1] = newsp; regs->gpr[3] = ksig->sig; regs->result = 0; if (ksig->ka.sa.sa_flags & SA_SIGINFO) { - err |= get_user(regs->gpr[4], (unsigned long __user *)&frame->pinfo); - err |= get_user(regs->gpr[5], (unsigned long __user *)&frame->puc); + regs->gpr[4] = (unsigned long)&frame->info; + regs->gpr[5] = (unsigned long)&frame->uc; regs->gpr[6] = (unsigned long) frame; } else { regs->gpr[4] = (unsigned long)&frame->uc.uc_mcontext; diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 7ddc2d32c39e..447b78a87c8f 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -619,6 +619,8 @@ static void nmi_stop_this_cpu(struct pt_regs *regs) /* * IRQs are already hard disabled by the smp_handle_nmi_ipi. */ + set_cpu_online(smp_processor_id(), false); + spin_begin(); while (1) spin_cpu_relax(); @@ -634,6 +636,15 @@ void smp_send_stop(void) static void stop_this_cpu(void *dummy) { hard_irq_disable(); + + /* + * Offlining CPUs in stop_this_cpu can result in scheduler warnings, + * (see commit de6e5d38417e), but printk_safe_flush_on_panic() wants + * to know other CPUs are offline before it breaks locks to flush + * printk buffers, in case we panic()ed while holding the lock. + */ + set_cpu_online(smp_processor_id(), false); + spin_begin(); while (1) spin_cpu_relax(); @@ -1541,6 +1552,10 @@ void start_secondary(void *unused) { unsigned int cpu = raw_smp_processor_id(); + /* PPC64 calls setup_kup() in early_setup_secondary() */ + if (IS_ENABLED(CONFIG_PPC32)) + setup_kup(); + mmgrab(&init_mm); current->active_mm = &init_mm; diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c index 1deb1bf331dd..2b0d04a1b7d2 100644 --- a/arch/powerpc/kernel/stacktrace.c +++ b/arch/powerpc/kernel/stacktrace.c @@ -23,8 +23,8 @@ #include -void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, - struct task_struct *task, struct pt_regs *regs) +void __no_sanitize_address arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, + struct task_struct *task, struct pt_regs *regs) { unsigned long sp; @@ -61,8 +61,8 @@ void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, * * If the task is not 'current', the caller *must* ensure the task is inactive. */ -int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, - void *cookie, struct task_struct *task) +int __no_sanitize_address arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, + void *cookie, struct task_struct *task) { unsigned long sp; unsigned long newsp; @@ -172,17 +172,31 @@ static void handle_backtrace_ipi(struct pt_regs *regs) static void raise_backtrace_ipi(cpumask_t *mask) { + struct paca_struct *p; unsigned int cpu; + u64 delay_us; for_each_cpu(cpu, mask) { - if (cpu == smp_processor_id()) + if (cpu == smp_processor_id()) { handle_backtrace_ipi(NULL); - else - smp_send_safe_nmi_ipi(cpu, handle_backtrace_ipi, 5 * USEC_PER_SEC); - } + continue; + } - for_each_cpu(cpu, mask) { - struct paca_struct *p = paca_ptrs[cpu]; + delay_us = 5 * USEC_PER_SEC; + + if (smp_send_safe_nmi_ipi(cpu, handle_backtrace_ipi, delay_us)) { + // Now wait up to 5s for the other CPU to do its backtrace + while (cpumask_test_cpu(cpu, mask) && delay_us) { + udelay(1); + delay_us--; + } + + // Other CPU cleared itself from the mask + if (delay_us) + continue; + } + + p = paca_ptrs[cpu]; cpumask_clear_cpu(cpu, mask); diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c index a552c9e68d7e..bf4ae0f0e36c 100644 --- a/arch/powerpc/kernel/syscalls.c +++ b/arch/powerpc/kernel/syscalls.c @@ -114,7 +114,8 @@ SYSCALL_DEFINE0(switch_endian) { struct thread_info *ti; - current->thread.regs->msr ^= MSR_LE; + regs_set_return_msr(current->thread.regs, + current->thread.regs->msr ^ MSR_LE); /* * Set TIF_RESTOREALL so that r3 isn't clobbered on return to diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c index 2e08640bb3b4..5ff0e55d0db1 100644 --- a/arch/powerpc/kernel/sysfs.c +++ b/arch/powerpc/kernel/sysfs.c @@ -843,14 +843,14 @@ static int register_cpu_online(unsigned int cpu) #ifdef HAS_PPC_PMC_IBM case PPC_PMC_IBM: attrs = ibm_common_attrs; - nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(ibm_common_attrs); pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_IBM */ #ifdef HAS_PPC_PMC_G4 case PPC_PMC_G4: attrs = g4_common_attrs; - nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(g4_common_attrs); pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_G4 */ @@ -858,7 +858,7 @@ static int register_cpu_online(unsigned int cpu) case PPC_PMC_PA6T: /* PA Semi starts counting at PMC0 */ attrs = pa6t_attrs; - nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(pa6t_attrs); pmc_attrs = NULL; break; #endif @@ -940,14 +940,14 @@ static int unregister_cpu_online(unsigned int cpu) #ifdef HAS_PPC_PMC_IBM case PPC_PMC_IBM: attrs = ibm_common_attrs; - nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(ibm_common_attrs); pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_IBM */ #ifdef HAS_PPC_PMC_G4 case PPC_PMC_G4: attrs = g4_common_attrs; - nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(g4_common_attrs); pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_G4 */ @@ -955,7 +955,7 @@ static int unregister_cpu_online(unsigned int cpu) case PPC_PMC_PA6T: /* PA Semi starts counting at PMC0 */ attrs = pa6t_attrs; - nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute); + nattrs = ARRAY_SIZE(pa6t_attrs); pmc_attrs = NULL; break; #endif diff --git a/arch/powerpc/kernel/tau_6xx.c b/arch/powerpc/kernel/tau_6xx.c index 6c31af7f4fa8..b9a047d92ec0 100644 --- a/arch/powerpc/kernel/tau_6xx.c +++ b/arch/powerpc/kernel/tau_6xx.c @@ -201,7 +201,7 @@ static int __init TAU_init(void) tau_int_enable = IS_ENABLED(CONFIG_TAU_INT) && !strcmp(cur_cpu_spec->platform, "ppc750"); - tau_workq = alloc_workqueue("tau", WQ_UNBOUND, 1, 0); + tau_workq = alloc_workqueue("tau", WQ_UNBOUND, 1); if (!tau_workq) return -ENOMEM; diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index da995c5fb97d..e45ce427bffb 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -231,24 +231,13 @@ static u64 scan_dispatch_log(u64 stop_tb) void notrace accumulate_stolen_time(void) { u64 sst, ust; - unsigned long save_irq_soft_mask = irq_soft_mask_return(); struct cpu_accounting_data *acct = &local_paca->accounting; - /* We are called early in the exception entry, before - * soft/hard_enabled are sync'ed to the expected state - * for the exception. We are hard disabled but the PACA - * needs to reflect that so various debug stuff doesn't - * complain - */ - irq_soft_mask_set(IRQS_DISABLED); - sst = scan_dispatch_log(acct->starttime_user); ust = scan_dispatch_log(acct->starttime); acct->stime -= sst; acct->utime -= ust; acct->steal_time += ust + sst; - - irq_soft_mask_set(save_irq_soft_mask); } static inline u64 calculate_stolen_time(u64 stop_tb) diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c index ffe9537195aa..d89c5df4f206 100644 --- a/arch/powerpc/kernel/trace/ftrace.c +++ b/arch/powerpc/kernel/trace/ftrace.c @@ -49,7 +49,7 @@ ftrace_call_replace(unsigned long ip, unsigned long addr, int link) addr = ppc_function_entry((void *)addr); /* if (link) set op to 'bl' else 'b' */ - create_branch(&op, (struct ppc_inst *)ip, addr, link ? 1 : 0); + create_branch(&op, (u32 *)ip, addr, link ? 1 : 0); return op; } @@ -79,7 +79,7 @@ ftrace_modify_code(unsigned long ip, struct ppc_inst old, struct ppc_inst new) } /* replace the text with the new text */ - if (patch_instruction((struct ppc_inst *)ip, new)) + if (patch_instruction((u32 *)ip, new)) return -EPERM; return 0; @@ -94,7 +94,7 @@ static int test_24bit_addr(unsigned long ip, unsigned long addr) addr = ppc_function_entry((void *)addr); /* use the create_branch to verify that this offset can be branched */ - return create_branch(&op, (struct ppc_inst *)ip, addr, 0) == 0; + return create_branch(&op, (u32 *)ip, addr, 0) == 0; } static int is_bl_op(struct ppc_inst op) @@ -162,7 +162,7 @@ __ftrace_make_nop(struct module *mod, #ifdef CONFIG_MPROFILE_KERNEL /* When using -mkernel_profile there is no load to jump over */ - pop = ppc_inst(PPC_INST_NOP); + pop = ppc_inst(PPC_RAW_NOP()); if (copy_inst_from_kernel_nofault(&op, (void *)(ip - 4))) { pr_err("Fetching instruction at %lx failed.\n", ip - 4); @@ -170,7 +170,7 @@ __ftrace_make_nop(struct module *mod, } /* We expect either a mflr r0, or a std r0, LRSAVE(r1) */ - if (!ppc_inst_equal(op, ppc_inst(PPC_INST_MFLR)) && + if (!ppc_inst_equal(op, ppc_inst(PPC_RAW_MFLR(_R0))) && !ppc_inst_equal(op, ppc_inst(PPC_INST_STD_LR))) { pr_err("Unexpected instruction %s around bl _mcount\n", ppc_inst_as_str(op)); @@ -203,12 +203,12 @@ __ftrace_make_nop(struct module *mod, } if (!ppc_inst_equal(op, ppc_inst(PPC_INST_LD_TOC))) { - pr_err("Expected %08x found %s\n", PPC_INST_LD_TOC, ppc_inst_as_str(op)); + pr_err("Expected %08lx found %s\n", PPC_INST_LD_TOC, ppc_inst_as_str(op)); return -EINVAL; } #endif /* CONFIG_MPROFILE_KERNEL */ - if (patch_instruction((struct ppc_inst *)ip, pop)) { + if (patch_instruction((u32 *)ip, pop)) { pr_err("Patching NOP failed.\n"); return -EPERM; } @@ -278,9 +278,9 @@ __ftrace_make_nop(struct module *mod, return -EINVAL; } - op = ppc_inst(PPC_INST_NOP); + op = ppc_inst(PPC_RAW_NOP()); - if (patch_instruction((struct ppc_inst *)ip, op)) + if (patch_instruction((u32 *)ip, op)) return -EPERM; return 0; @@ -380,7 +380,7 @@ static int setup_mcount_compiler_tramp(unsigned long tramp) return -1; } - if (patch_branch((struct ppc_inst *)tramp, ptr, 0)) { + if (patch_branch((u32 *)tramp, ptr, 0)) { pr_debug("REL24 out of range!\n"); return -1; } @@ -424,7 +424,7 @@ static int __ftrace_make_nop_kernel(struct dyn_ftrace *rec, unsigned long addr) } } - if (patch_instruction((struct ppc_inst *)ip, ppc_inst(PPC_INST_NOP))) { + if (patch_instruction((u32 *)ip, ppc_inst(PPC_RAW_NOP()))) { pr_err("Patching NOP failed.\n"); return -EPERM; } @@ -446,7 +446,7 @@ int ftrace_make_nop(struct module *mod, if (test_24bit_addr(ip, addr)) { /* within range */ old = ftrace_call_replace(ip, addr, 1); - new = ppc_inst(PPC_INST_NOP); + new = ppc_inst(PPC_RAW_NOP()); return ftrace_modify_code(ip, old, new); } else if (core_kernel_text(ip)) return __ftrace_make_nop_kernel(rec, addr); @@ -510,7 +510,7 @@ static int expected_nop_sequence(void *ip, struct ppc_inst op0, struct ppc_inst op1) { /* look for patched "NOP" on ppc64 with -mprofile-kernel */ - if (!ppc_inst_equal(op0, ppc_inst(PPC_INST_NOP))) + if (!ppc_inst_equal(op0, ppc_inst(PPC_RAW_NOP()))) return 0; return 1; } @@ -589,14 +589,14 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) { int err; struct ppc_inst op; - unsigned long ip = rec->ip; + u32 *ip = (u32 *)rec->ip; /* read where this goes */ - if (copy_inst_from_kernel_nofault(&op, (void *)ip)) + if (copy_inst_from_kernel_nofault(&op, ip)) return -EFAULT; /* It should be pointing to a nop */ - if (!ppc_inst_equal(op, ppc_inst(PPC_INST_NOP))) { + if (!ppc_inst_equal(op, ppc_inst(PPC_RAW_NOP()))) { pr_err("Expected NOP but have %s\n", ppc_inst_as_str(op)); return -EINVAL; } @@ -608,8 +608,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) } /* create the branch to the trampoline */ - err = create_branch(&op, (struct ppc_inst *)ip, - rec->arch.mod->arch.tramp, BRANCH_SET_LINK); + err = create_branch(&op, ip, rec->arch.mod->arch.tramp, BRANCH_SET_LINK); if (err) { pr_err("REL24 out of range!\n"); return -EINVAL; @@ -617,7 +616,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) pr_devel("write to %lx\n", rec->ip); - if (patch_instruction((struct ppc_inst *)ip, op)) + if (patch_instruction(ip, op)) return -EPERM; return 0; @@ -653,7 +652,7 @@ static int __ftrace_make_call_kernel(struct dyn_ftrace *rec, unsigned long addr) return -EFAULT; } - if (!ppc_inst_equal(op, ppc_inst(PPC_INST_NOP))) { + if (!ppc_inst_equal(op, ppc_inst(PPC_RAW_NOP()))) { pr_err("Unexpected call sequence at %p: %s\n", ip, ppc_inst_as_str(op)); return -EINVAL; } @@ -684,7 +683,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) */ if (test_24bit_addr(ip, addr)) { /* within range */ - old = ppc_inst(PPC_INST_NOP); + old = ppc_inst(PPC_RAW_NOP()); new = ftrace_call_replace(ip, addr, 1); return ftrace_modify_code(ip, old, new); } else if (core_kernel_text(ip)) @@ -762,7 +761,7 @@ __ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, /* The new target may be within range */ if (test_24bit_addr(ip, addr)) { /* within range */ - if (patch_branch((struct ppc_inst *)ip, addr, BRANCH_SET_LINK)) { + if (patch_branch((u32 *)ip, addr, BRANCH_SET_LINK)) { pr_err("REL24 out of range!\n"); return -EINVAL; } @@ -790,12 +789,12 @@ __ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, } /* Ensure branch is within 24 bits */ - if (create_branch(&op, (struct ppc_inst *)ip, tramp, BRANCH_SET_LINK)) { + if (create_branch(&op, (u32 *)ip, tramp, BRANCH_SET_LINK)) { pr_err("Branch out of range\n"); return -EINVAL; } - if (patch_branch((struct ppc_inst *)ip, tramp, BRANCH_SET_LINK)) { + if (patch_branch((u32 *)ip, tramp, BRANCH_SET_LINK)) { pr_err("REL24 out of range!\n"); return -EINVAL; } @@ -851,7 +850,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func) struct ppc_inst old, new; int ret; - old = ppc_inst_read((struct ppc_inst *)&ftrace_call); + old = ppc_inst_read((u32 *)&ftrace_call); new = ftrace_call_replace(ip, (unsigned long)func, 1); ret = ftrace_modify_code(ip, old, new); @@ -859,7 +858,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func) /* Also update the regs callback function */ if (!ret) { ip = (unsigned long)(&ftrace_regs_call); - old = ppc_inst_read((struct ppc_inst *)&ftrace_regs_call); + old = ppc_inst_read((u32 *)&ftrace_regs_call); new = ftrace_call_replace(ip, (unsigned long)func, 1); ret = ftrace_modify_code(ip, old, new); } diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index b4ab95c9e94a..dfbce527c98e 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -67,6 +67,7 @@ #include #include #include +#include #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) int (*__debugger)(struct pt_regs *regs) __read_mostly; @@ -427,7 +428,7 @@ void hv_nmi_check_nonrecoverable(struct pt_regs *regs) return; nonrecoverable: - regs->msr &= ~MSR_RI; + regs_set_return_msr(regs, regs->msr & ~MSR_RI); #endif } DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) @@ -537,11 +538,11 @@ static inline int check_io_access(struct pt_regs *regs) * For the debug message, we look at the preceding * load or store. */ - if (*nip == PPC_INST_NOP) + if (*nip == PPC_RAW_NOP()) nip -= 2; - else if (*nip == PPC_INST_ISYNC) + else if (*nip == PPC_RAW_ISYNC()) --nip; - if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { + if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) { unsigned int rb; --nip; @@ -549,8 +550,8 @@ static inline int check_io_access(struct pt_regs *regs) printk(KERN_DEBUG "%s bad port %lx at %p\n", (*nip & 0x100)? "OUT to": "IN from", regs->gpr[rb] - _IO_BASE, nip); - regs->msr |= MSR_RI; - regs->nip = extable_fixup(entry); + regs_set_return_msr(regs, regs->msr | MSR_RI); + regs_set_return_ip(regs, extable_fixup(entry)); return 1; } } @@ -586,8 +587,8 @@ static inline int check_io_access(struct pt_regs *regs) #define REASON_BOUNDARY SRR1_BOUNDARY #define single_stepping(regs) ((regs)->msr & MSR_SE) -#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) -#define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) +#define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE)) +#define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE)) #endif #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) @@ -1031,7 +1032,7 @@ static void p9_hmi_special_emu(struct pt_regs *regs) #endif /* !__LITTLE_ENDIAN__ */ /* Go to next instruction */ - regs->nip += 4; + regs_add_return_ip(regs, 4); } #endif /* CONFIG_VSX */ @@ -1476,7 +1477,7 @@ static void do_program_check(struct pt_regs *regs) if (!(regs->msr & MSR_PR) && /* not user-mode */ report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { - regs->nip += 4; + regs_add_return_ip(regs, 4); return; } _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); @@ -1538,7 +1539,7 @@ static void do_program_check(struct pt_regs *regs) if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { switch (emulate_instruction(regs)) { case 0: - regs->nip += 4; + regs_add_return_ip(regs, 4); emulate_single_step(regs); return; case -EFAULT: @@ -1566,7 +1567,7 @@ DEFINE_INTERRUPT_HANDLER(program_check_exception) */ DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) { - regs->msr |= REASON_ILLEGAL; + regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL); do_program_check(regs); } @@ -1593,7 +1594,7 @@ DEFINE_INTERRUPT_HANDLER(alignment_exception) if (fixed == 1) { /* skip over emulated instruction */ - regs->nip += inst_length(reason); + regs_add_return_ip(regs, inst_length(reason)); emulate_single_step(regs); return; } @@ -1659,7 +1660,7 @@ static void tm_unavailable(struct pt_regs *regs) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM if (user_mode(regs)) { current->thread.load_tm++; - regs->msr |= MSR_TM; + regs_set_return_msr(regs, regs->msr | MSR_TM); tm_enable(); tm_restore_sprs(¤t->thread); return; @@ -1751,7 +1752,7 @@ DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) pr_err("DSCR based mfspr emulation failed\n"); return; } - regs->nip += 4; + regs_add_return_ip(regs, 4); emulate_single_step(regs); } return; @@ -1948,7 +1949,7 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status) */ if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, current->thread.debug.dbcr1)) - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); else /* Make sure the IDM flag is off */ current->thread.debug.dbcr0 &= ~DBCR0_IDM; @@ -1969,7 +1970,7 @@ DEFINE_INTERRUPT_HANDLER(DebugException) * instead of stopping here when hitting a BT */ if (debug_status & DBSR_BT) { - regs->msr &= ~MSR_DE; + regs_set_return_msr(regs, regs->msr & ~MSR_DE); /* Disable BT */ mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); @@ -1980,7 +1981,7 @@ DEFINE_INTERRUPT_HANDLER(DebugException) if (user_mode(regs)) { current->thread.debug.dbcr0 &= ~DBCR0_BT; current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); return; } @@ -1994,7 +1995,7 @@ DEFINE_INTERRUPT_HANDLER(DebugException) if (debugger_sstep(regs)) return; } else if (debug_status & DBSR_IC) { /* Instruction complete */ - regs->msr &= ~MSR_DE; + regs_set_return_msr(regs, regs->msr & ~MSR_DE); /* Disable instruction completion */ mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); @@ -2016,7 +2017,7 @@ DEFINE_INTERRUPT_HANDLER(DebugException) current->thread.debug.dbcr0 &= ~DBCR0_IC; if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, current->thread.debug.dbcr1)) - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); else /* Make sure the IDM bit is off */ current->thread.debug.dbcr0 &= ~DBCR0_IDM; @@ -2044,7 +2045,7 @@ DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) PPC_WARN_EMULATED(altivec, regs); err = emulate_altivec(regs); if (err == 0) { - regs->nip += 4; /* skip emulated instruction */ + regs_add_return_ip(regs, 4); /* skip emulated instruction */ emulate_single_step(regs); return; } @@ -2109,7 +2110,7 @@ DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) err = do_spe_mathemu(regs); if (err == 0) { - regs->nip += 4; /* skip emulated instruction */ + regs_add_return_ip(regs, 4); /* skip emulated instruction */ emulate_single_step(regs); return; } @@ -2140,10 +2141,10 @@ DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) giveup_spe(current); preempt_enable(); - regs->nip -= 4; + regs_add_return_ip(regs, -4); err = speround_handler(regs); if (err == 0) { - regs->nip += 4; /* skip emulated instruction */ + regs_add_return_ip(regs, 4); /* skip emulated instruction */ emulate_single_step(regs); return; } diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c index 9356b60d6030..8513aa49614e 100644 --- a/arch/powerpc/kernel/udbg_16550.c +++ b/arch/powerpc/kernel/udbg_16550.c @@ -296,3 +296,42 @@ void __init udbg_init_40x_realmode(void) } #endif /* CONFIG_PPC_EARLY_DEBUG_40x */ + +#ifdef CONFIG_PPC_EARLY_DEBUG_MICROWATT + +#define UDBG_UART_MW_ADDR ((void __iomem *)0xc0002000) + +static u8 udbg_uart_in_isa300_rm(unsigned int reg) +{ + uint64_t msr = mfmsr(); + uint8_t c; + + mtmsr(msr & ~(MSR_EE|MSR_DR)); + isync(); + eieio(); + c = __raw_rm_readb(UDBG_UART_MW_ADDR + (reg << 2)); + mtmsr(msr); + isync(); + return c; +} + +static void udbg_uart_out_isa300_rm(unsigned int reg, u8 val) +{ + uint64_t msr = mfmsr(); + + mtmsr(msr & ~(MSR_EE|MSR_DR)); + isync(); + eieio(); + __raw_rm_writeb(val, UDBG_UART_MW_ADDR + (reg << 2)); + mtmsr(msr); + isync(); +} + +void __init udbg_init_debug_microwatt(void) +{ + udbg_uart_in = udbg_uart_in_isa300_rm; + udbg_uart_out = udbg_uart_out_isa300_rm; + udbg_use_uart(); +} + +#endif /* CONFIG_PPC_EARLY_DEBUG_MICROWATT */ diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c index 186f69b11e94..c6975467d9ff 100644 --- a/arch/powerpc/kernel/uprobes.c +++ b/arch/powerpc/kernel/uprobes.c @@ -42,7 +42,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, return -EINVAL; if (cpu_has_feature(CPU_FTR_ARCH_31) && - ppc_inst_prefixed(auprobe->insn) && + ppc_inst_prefixed(ppc_inst_read(auprobe->insn)) && (addr & 0x3f) == 60) { pr_info_ratelimited("Cannot register a uprobe on 64 byte unaligned prefixed instruction\n"); return -EINVAL; @@ -62,7 +62,7 @@ int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) autask->saved_trap_nr = current->thread.trap_nr; current->thread.trap_nr = UPROBE_TRAP_NR; - regs->nip = current->utask->xol_vaddr; + regs_set_return_ip(regs, current->utask->xol_vaddr); user_enable_single_step(current); return 0; @@ -119,7 +119,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) * support doesn't exist and have to fix-up the next instruction * to be executed. */ - regs->nip = (unsigned long)ppc_inst_next((void *)utask->vaddr, &auprobe->insn); + regs_set_return_ip(regs, (unsigned long)ppc_inst_next((void *)utask->vaddr, auprobe->insn)); user_disable_single_step(current); return 0; @@ -182,7 +182,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) * emulate_step() returns 1 if the insn was successfully emulated. * For all other cases, we need to single-step in hardware. */ - ret = emulate_step(regs, ppc_inst_read(&auprobe->insn)); + ret = emulate_step(regs, ppc_inst_read(auprobe->insn)); if (ret > 0) return true; diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S index f5a52f444e36..fc120fac1910 100644 --- a/arch/powerpc/kernel/vector.S +++ b/arch/powerpc/kernel/vector.S @@ -73,6 +73,10 @@ _GLOBAL(load_up_altivec) addi r5,r4,THREAD /* Get THREAD */ oris r12,r12,MSR_VEC@h std r12,_MSR(r1) +#ifdef CONFIG_PPC_BOOK3S_64 + li r4,0 + stb r4,PACASRR_VALID(r13) +#endif #endif li r4,1 stb r4,THREAD_LOAD_VEC(r5) @@ -131,7 +135,9 @@ _GLOBAL(load_up_vsx) /* enable use of VSX after return */ oris r12,r12,MSR_VSX@h std r12,_MSR(r1) - b fast_interrupt_return + li r4,0 + stb r4,PACASRR_VALID(r13) + b fast_interrupt_return_srr #endif /* CONFIG_VSX */ diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 4a1f494ef03f..efe7073f2705 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -9,6 +9,22 @@ #define EMITS_PT_NOTE #define RO_EXCEPTION_TABLE_ALIGN 0 +#define SOFT_MASK_TABLE(align) \ + . = ALIGN(align); \ + __soft_mask_table : AT(ADDR(__soft_mask_table) - LOAD_OFFSET) { \ + __start___soft_mask_table = .; \ + KEEP(*(__soft_mask_table)) \ + __stop___soft_mask_table = .; \ + } + +#define RESTART_TABLE(align) \ + . = ALIGN(align); \ + __restart_table : AT(ADDR(__restart_table) - LOAD_OFFSET) { \ + __start___restart_table = .; \ + KEEP(*(__restart_table)) \ + __stop___restart_table = .; \ + } + #include #include #include @@ -124,6 +140,9 @@ SECTIONS RO_DATA(PAGE_SIZE) #ifdef CONFIG_PPC64 + SOFT_MASK_TABLE(8) + RESTART_TABLE(8) + . = ALIGN(8); __stf_entry_barrier_fixup : AT(ADDR(__stf_entry_barrier_fixup) - LOAD_OFFSET) { __start___stf_entry_barrier_fixup = .; diff --git a/arch/powerpc/kernel/watchdog.c b/arch/powerpc/kernel/watchdog.c index c9a8f4781a10..a165635fd214 100644 --- a/arch/powerpc/kernel/watchdog.c +++ b/arch/powerpc/kernel/watchdog.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include diff --git a/arch/powerpc/kexec/crash.c b/arch/powerpc/kexec/crash.c index 0196d0c211ac..10f997e6bb95 100644 --- a/arch/powerpc/kexec/crash.c +++ b/arch/powerpc/kexec/crash.c @@ -105,8 +105,8 @@ void crash_ipi_callback(struct pt_regs *regs) static void crash_kexec_prepare_cpus(int cpu) { unsigned int msecs; - unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */ - int tries = 0; + volatile unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */ + volatile int tries = 0; int (*old_handler)(struct pt_regs *regs); printk(KERN_EMERG "Sending IPI to other CPUs\n"); diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c index e8e7b2c530d1..4b3a8d80cfa3 100644 --- a/arch/powerpc/kvm/book3s_32_mmu_host.c +++ b/arch/powerpc/kvm/book3s_32_mmu_host.c @@ -353,9 +353,6 @@ void kvmppc_mmu_destroy_pr(struct kvm_vcpu *vcpu) preempt_enable(); } -/* From mm/mmu_context_hash32.c */ -#define CTX_TO_VSID(c, id) ((((c) * (897 * 16)) + (id * 0x111)) & 0xffffff) - int kvmppc_mmu_init_pr(struct kvm_vcpu *vcpu) { struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 260e860d53a2..1d1fcc290fca 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -4626,6 +4626,9 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu) vcpu->arch.state = KVMPPC_VCPU_NOTREADY; atomic_dec(&kvm->arch.vcpus_running); + + srr_regs_clobbered(); + return r; } diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 71bcb0140461..6bc9425acb32 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1848,6 +1849,7 @@ static int kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu) /* Make sure we save the guest TAR/EBB/DSCR state */ kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); + srr_regs_clobbered(); out: vcpu->mode = OUTSIDE_GUEST_MODE; return ret; diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index cc1a8a0f311e..99a7c9132422 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -39,7 +39,7 @@ extra-$(CONFIG_PPC64) += crtsavres.o endif obj-$(CONFIG_PPC_BOOK3S_64) += copyuser_power7.o copypage_power7.o \ - memcpy_power7.o + memcpy_power7.o restart_table.o obj64-y += copypage_64.o copyuser_64.o mem_64.o hweight_64.o \ memcpy_64.o copy_mc_64.o diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c index 870b30d9be2f..f9a3019e37b4 100644 --- a/arch/powerpc/lib/code-patching.c +++ b/arch/powerpc/lib/code-patching.c @@ -18,8 +18,7 @@ #include #include -static int __patch_instruction(struct ppc_inst *exec_addr, struct ppc_inst instr, - struct ppc_inst *patch_addr) +static int __patch_instruction(u32 *exec_addr, struct ppc_inst instr, u32 *patch_addr) { if (!ppc_inst_prefixed(instr)) { u32 val = ppc_inst_val(instr); @@ -40,7 +39,7 @@ failed: return -EFAULT; } -int raw_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) +int raw_patch_instruction(u32 *addr, struct ppc_inst instr) { return __patch_instruction(addr, instr, addr); } @@ -70,22 +69,16 @@ static int text_area_cpu_down(unsigned int cpu) } /* - * Run as a late init call. This allows all the boot time patching to be done - * simply by patching the code, and then we're called here prior to - * mark_rodata_ro(), which happens after all init calls are run. Although - * BUG_ON() is rude, in this case it should only happen if ENOMEM, and we judge - * it as being preferable to a kernel that will crash later when someone tries - * to use patch_instruction(). + * Although BUG_ON() is rude, in this case it should only happen if ENOMEM, and + * we judge it as being preferable to a kernel that will crash later when + * someone tries to use patch_instruction(). */ -static int __init setup_text_poke_area(void) +void __init poking_init(void) { BUG_ON(!cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/text_poke:online", text_area_cpu_up, text_area_cpu_down)); - - return 0; } -late_initcall(setup_text_poke_area); /* * This can be called for kernel text or a module. @@ -148,10 +141,10 @@ static inline int unmap_patch_area(unsigned long addr) return 0; } -static int do_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) +static int do_patch_instruction(u32 *addr, struct ppc_inst instr) { int err; - struct ppc_inst *patch_addr = NULL; + u32 *patch_addr = NULL; unsigned long flags; unsigned long text_poke_addr; unsigned long kaddr = (unsigned long)addr; @@ -172,7 +165,7 @@ static int do_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) goto out; } - patch_addr = (struct ppc_inst *)(text_poke_addr + (kaddr & ~PAGE_MASK)); + patch_addr = (u32 *)(text_poke_addr + (kaddr & ~PAGE_MASK)); __patch_instruction(addr, instr, patch_addr); @@ -187,14 +180,14 @@ out: } #else /* !CONFIG_STRICT_KERNEL_RWX */ -static int do_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) +static int do_patch_instruction(u32 *addr, struct ppc_inst instr) { return raw_patch_instruction(addr, instr); } #endif /* CONFIG_STRICT_KERNEL_RWX */ -int patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) +int patch_instruction(u32 *addr, struct ppc_inst instr) { /* Make sure we aren't patching a freed init section */ if (init_mem_is_free && init_section_contains(addr, 4)) { @@ -205,7 +198,7 @@ int patch_instruction(struct ppc_inst *addr, struct ppc_inst instr) } NOKPROBE_SYMBOL(patch_instruction); -int patch_branch(struct ppc_inst *addr, unsigned long target, int flags) +int patch_branch(u32 *addr, unsigned long target, int flags) { struct ppc_inst instr; @@ -257,8 +250,7 @@ bool is_conditional_branch(struct ppc_inst instr) } NOKPROBE_SYMBOL(is_conditional_branch); -int create_branch(struct ppc_inst *instr, - const struct ppc_inst *addr, +int create_branch(struct ppc_inst *instr, const u32 *addr, unsigned long target, int flags) { long offset; @@ -278,7 +270,7 @@ int create_branch(struct ppc_inst *instr, return 0; } -int create_cond_branch(struct ppc_inst *instr, const struct ppc_inst *addr, +int create_cond_branch(struct ppc_inst *instr, const u32 *addr, unsigned long target, int flags) { long offset; @@ -325,39 +317,39 @@ int instr_is_relative_link_branch(struct ppc_inst instr) return instr_is_relative_branch(instr) && (ppc_inst_val(instr) & BRANCH_SET_LINK); } -static unsigned long branch_iform_target(const struct ppc_inst *instr) +static unsigned long branch_iform_target(const u32 *instr) { signed long imm; - imm = ppc_inst_val(*instr) & 0x3FFFFFC; + imm = ppc_inst_val(ppc_inst_read(instr)) & 0x3FFFFFC; /* If the top bit of the immediate value is set this is negative */ if (imm & 0x2000000) imm -= 0x4000000; - if ((ppc_inst_val(*instr) & BRANCH_ABSOLUTE) == 0) + if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0) imm += (unsigned long)instr; return (unsigned long)imm; } -static unsigned long branch_bform_target(const struct ppc_inst *instr) +static unsigned long branch_bform_target(const u32 *instr) { signed long imm; - imm = ppc_inst_val(*instr) & 0xFFFC; + imm = ppc_inst_val(ppc_inst_read(instr)) & 0xFFFC; /* If the top bit of the immediate value is set this is negative */ if (imm & 0x8000) imm -= 0x10000; - if ((ppc_inst_val(*instr) & BRANCH_ABSOLUTE) == 0) + if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0) imm += (unsigned long)instr; return (unsigned long)imm; } -unsigned long branch_target(const struct ppc_inst *instr) +unsigned long branch_target(const u32 *instr) { if (instr_is_branch_iform(ppc_inst_read(instr))) return branch_iform_target(instr); @@ -367,17 +359,7 @@ unsigned long branch_target(const struct ppc_inst *instr) return 0; } -int instr_is_branch_to_addr(const struct ppc_inst *instr, unsigned long addr) -{ - if (instr_is_branch_iform(ppc_inst_read(instr)) || - instr_is_branch_bform(ppc_inst_read(instr))) - return branch_target(instr) == addr; - - return 0; -} - -int translate_branch(struct ppc_inst *instr, const struct ppc_inst *dest, - const struct ppc_inst *src) +int translate_branch(struct ppc_inst *instr, const u32 *dest, const u32 *src) { unsigned long target; target = branch_target(src); @@ -404,12 +386,21 @@ void __patch_exception(int exc, unsigned long addr) * instruction of the exception, not the first one */ - patch_branch((struct ppc_inst *)(ibase + (exc / 4) + 1), addr, 0); + patch_branch(ibase + (exc / 4) + 1, addr, 0); } #endif #ifdef CONFIG_CODE_PATCHING_SELFTEST +static int instr_is_branch_to_addr(const u32 *instr, unsigned long addr) +{ + if (instr_is_branch_iform(ppc_inst_read(instr)) || + instr_is_branch_bform(ppc_inst_read(instr))) + return branch_target(instr) == addr; + + return 0; +} + static void __init test_trampoline(void) { asm ("nop;\n"); @@ -422,9 +413,9 @@ static void __init test_branch_iform(void) { int err; struct ppc_inst instr; - unsigned long addr; - - addr = (unsigned long)&instr; + u32 tmp[2]; + u32 *iptr = tmp; + unsigned long addr = (unsigned long)tmp; /* The simplest case, branch to self, no flags */ check(instr_is_branch_iform(ppc_inst(0x48000000))); @@ -445,63 +436,68 @@ static void __init test_branch_iform(void) check(!instr_is_branch_iform(ppc_inst(0x7bfffffd))); /* Absolute branch to 0x100 */ - instr = ppc_inst(0x48000103); - check(instr_is_branch_to_addr(&instr, 0x100)); + patch_instruction(iptr, ppc_inst(0x48000103)); + check(instr_is_branch_to_addr(iptr, 0x100)); /* Absolute branch to 0x420fc */ - instr = ppc_inst(0x480420ff); - check(instr_is_branch_to_addr(&instr, 0x420fc)); + patch_instruction(iptr, ppc_inst(0x480420ff)); + check(instr_is_branch_to_addr(iptr, 0x420fc)); /* Maximum positive relative branch, + 20MB - 4B */ - instr = ppc_inst(0x49fffffc); - check(instr_is_branch_to_addr(&instr, addr + 0x1FFFFFC)); + patch_instruction(iptr, ppc_inst(0x49fffffc)); + check(instr_is_branch_to_addr(iptr, addr + 0x1FFFFFC)); /* Smallest negative relative branch, - 4B */ - instr = ppc_inst(0x4bfffffc); - check(instr_is_branch_to_addr(&instr, addr - 4)); + patch_instruction(iptr, ppc_inst(0x4bfffffc)); + check(instr_is_branch_to_addr(iptr, addr - 4)); /* Largest negative relative branch, - 32 MB */ - instr = ppc_inst(0x4a000000); - check(instr_is_branch_to_addr(&instr, addr - 0x2000000)); + patch_instruction(iptr, ppc_inst(0x4a000000)); + check(instr_is_branch_to_addr(iptr, addr - 0x2000000)); /* Branch to self, with link */ - err = create_branch(&instr, &instr, addr, BRANCH_SET_LINK); - check(instr_is_branch_to_addr(&instr, addr)); + err = create_branch(&instr, iptr, addr, BRANCH_SET_LINK); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr)); /* Branch to self - 0x100, with link */ - err = create_branch(&instr, &instr, addr - 0x100, BRANCH_SET_LINK); - check(instr_is_branch_to_addr(&instr, addr - 0x100)); + err = create_branch(&instr, iptr, addr - 0x100, BRANCH_SET_LINK); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr - 0x100)); /* Branch to self + 0x100, no link */ - err = create_branch(&instr, &instr, addr + 0x100, 0); - check(instr_is_branch_to_addr(&instr, addr + 0x100)); + err = create_branch(&instr, iptr, addr + 0x100, 0); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr + 0x100)); /* Maximum relative negative offset, - 32 MB */ - err = create_branch(&instr, &instr, addr - 0x2000000, BRANCH_SET_LINK); - check(instr_is_branch_to_addr(&instr, addr - 0x2000000)); + err = create_branch(&instr, iptr, addr - 0x2000000, BRANCH_SET_LINK); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr - 0x2000000)); /* Out of range relative negative offset, - 32 MB + 4*/ - err = create_branch(&instr, &instr, addr - 0x2000004, BRANCH_SET_LINK); + err = create_branch(&instr, iptr, addr - 0x2000004, BRANCH_SET_LINK); check(err); /* Out of range relative positive offset, + 32 MB */ - err = create_branch(&instr, &instr, addr + 0x2000000, BRANCH_SET_LINK); + err = create_branch(&instr, iptr, addr + 0x2000000, BRANCH_SET_LINK); check(err); /* Unaligned target */ - err = create_branch(&instr, &instr, addr + 3, BRANCH_SET_LINK); + err = create_branch(&instr, iptr, addr + 3, BRANCH_SET_LINK); check(err); /* Check flags are masked correctly */ - err = create_branch(&instr, &instr, addr, 0xFFFFFFFC); - check(instr_is_branch_to_addr(&instr, addr)); + err = create_branch(&instr, iptr, addr, 0xFFFFFFFC); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr)); check(ppc_inst_equal(instr, ppc_inst(0x48000000))); } static void __init test_create_function_call(void) { - struct ppc_inst *iptr; + u32 *iptr; unsigned long dest; struct ppc_inst instr; /* Check we can create a function call */ - iptr = (struct ppc_inst *)ppc_function_entry(test_trampoline); + iptr = (u32 *)ppc_function_entry(test_trampoline); dest = ppc_function_entry(test_create_function_call); create_branch(&instr, iptr, dest, BRANCH_SET_LINK); patch_instruction(iptr, instr); @@ -512,10 +508,11 @@ static void __init test_branch_bform(void) { int err; unsigned long addr; - struct ppc_inst *iptr, instr; + struct ppc_inst instr; + u32 tmp[2]; + u32 *iptr = tmp; unsigned int flags; - iptr = &instr; addr = (unsigned long)iptr; /* The simplest case, branch to self, no flags */ @@ -528,39 +525,43 @@ static void __init test_branch_bform(void) check(!instr_is_branch_bform(ppc_inst(0x7bffffff))); /* Absolute conditional branch to 0x100 */ - instr = ppc_inst(0x43ff0103); - check(instr_is_branch_to_addr(&instr, 0x100)); + patch_instruction(iptr, ppc_inst(0x43ff0103)); + check(instr_is_branch_to_addr(iptr, 0x100)); /* Absolute conditional branch to 0x20fc */ - instr = ppc_inst(0x43ff20ff); - check(instr_is_branch_to_addr(&instr, 0x20fc)); + patch_instruction(iptr, ppc_inst(0x43ff20ff)); + check(instr_is_branch_to_addr(iptr, 0x20fc)); /* Maximum positive relative conditional branch, + 32 KB - 4B */ - instr = ppc_inst(0x43ff7ffc); - check(instr_is_branch_to_addr(&instr, addr + 0x7FFC)); + patch_instruction(iptr, ppc_inst(0x43ff7ffc)); + check(instr_is_branch_to_addr(iptr, addr + 0x7FFC)); /* Smallest negative relative conditional branch, - 4B */ - instr = ppc_inst(0x43fffffc); - check(instr_is_branch_to_addr(&instr, addr - 4)); + patch_instruction(iptr, ppc_inst(0x43fffffc)); + check(instr_is_branch_to_addr(iptr, addr - 4)); /* Largest negative relative conditional branch, - 32 KB */ - instr = ppc_inst(0x43ff8000); - check(instr_is_branch_to_addr(&instr, addr - 0x8000)); + patch_instruction(iptr, ppc_inst(0x43ff8000)); + check(instr_is_branch_to_addr(iptr, addr - 0x8000)); /* All condition code bits set & link */ flags = 0x3ff000 | BRANCH_SET_LINK; /* Branch to self */ err = create_cond_branch(&instr, iptr, addr, flags); - check(instr_is_branch_to_addr(&instr, addr)); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr)); /* Branch to self - 0x100 */ err = create_cond_branch(&instr, iptr, addr - 0x100, flags); - check(instr_is_branch_to_addr(&instr, addr - 0x100)); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr - 0x100)); /* Branch to self + 0x100 */ err = create_cond_branch(&instr, iptr, addr + 0x100, flags); - check(instr_is_branch_to_addr(&instr, addr + 0x100)); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr + 0x100)); /* Maximum relative negative offset, - 32 KB */ err = create_cond_branch(&instr, iptr, addr - 0x8000, flags); - check(instr_is_branch_to_addr(&instr, addr - 0x8000)); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr - 0x8000)); /* Out of range relative negative offset, - 32 KB + 4*/ err = create_cond_branch(&instr, iptr, addr - 0x8004, flags); @@ -576,7 +577,8 @@ static void __init test_branch_bform(void) /* Check flags are masked correctly */ err = create_cond_branch(&instr, iptr, addr, 0xFFFFFFFC); - check(instr_is_branch_to_addr(&instr, addr)); + patch_instruction(iptr, instr); + check(instr_is_branch_to_addr(iptr, addr)); check(ppc_inst_equal(instr, ppc_inst(0x43FF0000))); } @@ -715,9 +717,9 @@ static void __init test_prefixed_patching(void) extern unsigned int code_patching_test1_expected[]; extern unsigned int end_code_patching_test1[]; - __patch_instruction((struct ppc_inst *)code_patching_test1, + __patch_instruction(code_patching_test1, ppc_inst_prefix(OP_PREFIX << 26, 0x00000000), - (struct ppc_inst *)code_patching_test1); + code_patching_test1); check(!memcmp(code_patching_test1, code_patching_test1_expected, diff --git a/arch/powerpc/lib/error-inject.c b/arch/powerpc/lib/error-inject.c index 407b992fb02f..e834079d2b5c 100644 --- a/arch/powerpc/lib/error-inject.c +++ b/arch/powerpc/lib/error-inject.c @@ -11,6 +11,6 @@ void override_function_with_return(struct pt_regs *regs) * function in the kernel/module, captured on a kprobe. We don't need * to worry about 32-bit userspace on a 64-bit kernel. */ - regs->nip = regs->link; + regs_set_return_ip(regs, regs->link); } NOKPROBE_SYMBOL(override_function_with_return); diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c index fe26f2fa0f3f..cda17bee5afe 100644 --- a/arch/powerpc/lib/feature-fixups.c +++ b/arch/powerpc/lib/feature-fixups.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,26 +34,25 @@ struct fixup_entry { long alt_end_off; }; -static struct ppc_inst *calc_addr(struct fixup_entry *fcur, long offset) +static u32 *calc_addr(struct fixup_entry *fcur, long offset) { /* * We store the offset to the code as a negative offset from * the start of the alt_entry, to support the VDSO. This * routine converts that back into an actual address. */ - return (struct ppc_inst *)((unsigned long)fcur + offset); + return (u32 *)((unsigned long)fcur + offset); } -static int patch_alt_instruction(struct ppc_inst *src, struct ppc_inst *dest, - struct ppc_inst *alt_start, struct ppc_inst *alt_end) +static int patch_alt_instruction(u32 *src, u32 *dest, u32 *alt_start, u32 *alt_end) { int err; struct ppc_inst instr; instr = ppc_inst_read(src); - if (instr_is_relative_branch(*src)) { - struct ppc_inst *target = (struct ppc_inst *)branch_target(src); + if (instr_is_relative_branch(ppc_inst_read(src))) { + u32 *target = (u32 *)branch_target(src); /* Branch within the section doesn't need translating */ if (target < alt_start || target > alt_end) { @@ -69,7 +69,7 @@ static int patch_alt_instruction(struct ppc_inst *src, struct ppc_inst *dest, static int patch_feature_section(unsigned long value, struct fixup_entry *fcur) { - struct ppc_inst *start, *end, *alt_start, *alt_end, *src, *dest, nop; + u32 *start, *end, *alt_start, *alt_end, *src, *dest; start = calc_addr(fcur, fcur->start_off); end = calc_addr(fcur, fcur->end_off); @@ -91,9 +91,8 @@ static int patch_feature_section(unsigned long value, struct fixup_entry *fcur) return 1; } - nop = ppc_inst(PPC_INST_NOP); - for (; dest < end; dest = ppc_inst_next(dest, &nop)) - raw_patch_instruction(dest, nop); + for (; dest < end; dest++) + raw_patch_instruction(dest, ppc_inst(PPC_RAW_NOP())); return 0; } @@ -128,21 +127,21 @@ static void do_stf_entry_barrier_fixups(enum stf_barrier_type types) start = PTRRELOC(&__start___stf_entry_barrier_fixup); end = PTRRELOC(&__stop___stf_entry_barrier_fixup); - instrs[0] = 0x60000000; /* nop */ - instrs[1] = 0x60000000; /* nop */ - instrs[2] = 0x60000000; /* nop */ + instrs[0] = PPC_RAW_NOP(); + instrs[1] = PPC_RAW_NOP(); + instrs[2] = PPC_RAW_NOP(); i = 0; if (types & STF_BARRIER_FALLBACK) { - instrs[i++] = 0x7d4802a6; /* mflr r10 */ - instrs[i++] = 0x60000000; /* branch patched below */ - instrs[i++] = 0x7d4803a6; /* mtlr r10 */ + instrs[i++] = PPC_RAW_MFLR(_R10); + instrs[i++] = PPC_RAW_NOP(); /* branch patched below */ + instrs[i++] = PPC_RAW_MTLR(_R10); } else if (types & STF_BARRIER_EIEIO) { - instrs[i++] = 0x7e0006ac; /* eieio + bit 6 hint */ + instrs[i++] = PPC_RAW_EIEIO() | 0x02000000; /* eieio + bit 6 hint */ } else if (types & STF_BARRIER_SYNC_ORI) { - instrs[i++] = 0x7c0004ac; /* hwsync */ - instrs[i++] = 0xe94d0000; /* ld r10,0(r13) */ - instrs[i++] = 0x63ff0000; /* ori 31,31,0 speculation barrier */ + instrs[i++] = PPC_RAW_SYNC(); + instrs[i++] = PPC_RAW_LD(_R10, _R13, 0); + instrs[i++] = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ } for (i = 0; start < end; start++, i++) { @@ -152,14 +151,14 @@ static void do_stf_entry_barrier_fixups(enum stf_barrier_type types) // See comment in do_entry_flush_fixups() RE order of patching if (types & STF_BARRIER_FALLBACK) { - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_branch((struct ppc_inst *)(dest + 1), + patch_instruction(dest, ppc_inst(instrs[0])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_branch(dest + 1, (unsigned long)&stf_barrier_fallback, BRANCH_SET_LINK); } else { - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_instruction(dest, ppc_inst(instrs[0])); } } @@ -180,32 +179,31 @@ static void do_stf_exit_barrier_fixups(enum stf_barrier_type types) start = PTRRELOC(&__start___stf_exit_barrier_fixup); end = PTRRELOC(&__stop___stf_exit_barrier_fixup); - instrs[0] = 0x60000000; /* nop */ - instrs[1] = 0x60000000; /* nop */ - instrs[2] = 0x60000000; /* nop */ - instrs[3] = 0x60000000; /* nop */ - instrs[4] = 0x60000000; /* nop */ - instrs[5] = 0x60000000; /* nop */ + instrs[0] = PPC_RAW_NOP(); + instrs[1] = PPC_RAW_NOP(); + instrs[2] = PPC_RAW_NOP(); + instrs[3] = PPC_RAW_NOP(); + instrs[4] = PPC_RAW_NOP(); + instrs[5] = PPC_RAW_NOP(); i = 0; if (types & STF_BARRIER_FALLBACK || types & STF_BARRIER_SYNC_ORI) { if (cpu_has_feature(CPU_FTR_HVMODE)) { - instrs[i++] = 0x7db14ba6; /* mtspr 0x131, r13 (HSPRG1) */ - instrs[i++] = 0x7db04aa6; /* mfspr r13, 0x130 (HSPRG0) */ + instrs[i++] = PPC_RAW_MTSPR(SPRN_HSPRG1, _R13); + instrs[i++] = PPC_RAW_MFSPR(_R13, SPRN_HSPRG0); } else { - instrs[i++] = 0x7db243a6; /* mtsprg 2,r13 */ - instrs[i++] = 0x7db142a6; /* mfsprg r13,1 */ + instrs[i++] = PPC_RAW_MTSPR(SPRN_SPRG2, _R13); + instrs[i++] = PPC_RAW_MFSPR(_R13, SPRN_SPRG1); } - instrs[i++] = 0x7c0004ac; /* hwsync */ - instrs[i++] = 0xe9ad0000; /* ld r13,0(r13) */ - instrs[i++] = 0x63ff0000; /* ori 31,31,0 speculation barrier */ - if (cpu_has_feature(CPU_FTR_HVMODE)) { - instrs[i++] = 0x7db14aa6; /* mfspr r13, 0x131 (HSPRG1) */ - } else { - instrs[i++] = 0x7db242a6; /* mfsprg r13,2 */ - } + instrs[i++] = PPC_RAW_SYNC(); + instrs[i++] = PPC_RAW_LD(_R13, _R13, 0); + instrs[i++] = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ + if (cpu_has_feature(CPU_FTR_HVMODE)) + instrs[i++] = PPC_RAW_MFSPR(_R13, SPRN_HSPRG1); + else + instrs[i++] = PPC_RAW_MFSPR(_R13, SPRN_SPRG2); } else if (types & STF_BARRIER_EIEIO) { - instrs[i++] = 0x7e0006ac; /* eieio + bit 6 hint */ + instrs[i++] = PPC_RAW_EIEIO() | 0x02000000; /* eieio + bit 6 hint */ } for (i = 0; start < end; start++, i++) { @@ -213,12 +211,12 @@ static void do_stf_exit_barrier_fixups(enum stf_barrier_type types) pr_devel("patching dest %lx\n", (unsigned long)dest); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_instruction((struct ppc_inst *)(dest + 3), ppc_inst(instrs[3])); - patch_instruction((struct ppc_inst *)(dest + 4), ppc_inst(instrs[4])); - patch_instruction((struct ppc_inst *)(dest + 5), ppc_inst(instrs[5])); + patch_instruction(dest, ppc_inst(instrs[0])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_instruction(dest + 3, ppc_inst(instrs[3])); + patch_instruction(dest + 4, ppc_inst(instrs[4])); + patch_instruction(dest + 5, ppc_inst(instrs[5])); } printk(KERN_DEBUG "stf-barrier: patched %d exit locations (%s barrier)\n", i, (types == STF_BARRIER_NONE) ? "no" : @@ -228,6 +226,9 @@ static void do_stf_exit_barrier_fixups(enum stf_barrier_type types) : "unknown"); } +static bool stf_exit_reentrant = false; +static bool rfi_exit_reentrant = false; + static int __do_stf_barrier_fixups(void *data) { enum stf_barrier_type *types = data; @@ -242,11 +243,27 @@ void do_stf_barrier_fixups(enum stf_barrier_type types) { /* * The call to the fallback entry flush, and the fallback/sync-ori exit - * flush can not be safely patched in/out while other CPUs are executing - * them. So call __do_stf_barrier_fixups() on one CPU while all other CPUs - * spin in the stop machine core with interrupts hard disabled. + * flush can not be safely patched in/out while other CPUs are + * executing them. So call __do_stf_barrier_fixups() on one CPU while + * all other CPUs spin in the stop machine core with interrupts hard + * disabled. + * + * The branch to mark interrupt exits non-reentrant is enabled first, + * then stop_machine runs which will ensure all CPUs are out of the + * low level interrupt exit code before patching. After the patching, + * if allowed, then flip the branch to allow fast exits. */ + static_branch_enable(&interrupt_exit_not_reentrant); + stop_machine(__do_stf_barrier_fixups, &types, NULL); + + if ((types & STF_BARRIER_FALLBACK) || (types & STF_BARRIER_SYNC_ORI)) + stf_exit_reentrant = false; + else + stf_exit_reentrant = true; + + if (stf_exit_reentrant && rfi_exit_reentrant) + static_branch_disable(&interrupt_exit_not_reentrant); } void do_uaccess_flush_fixups(enum l1d_flush_type types) @@ -258,35 +275,35 @@ void do_uaccess_flush_fixups(enum l1d_flush_type types) start = PTRRELOC(&__start___uaccess_flush_fixup); end = PTRRELOC(&__stop___uaccess_flush_fixup); - instrs[0] = 0x60000000; /* nop */ - instrs[1] = 0x60000000; /* nop */ - instrs[2] = 0x60000000; /* nop */ - instrs[3] = 0x4e800020; /* blr */ + instrs[0] = PPC_RAW_NOP(); + instrs[1] = PPC_RAW_NOP(); + instrs[2] = PPC_RAW_NOP(); + instrs[3] = PPC_RAW_BLR(); i = 0; if (types == L1D_FLUSH_FALLBACK) { - instrs[3] = 0x60000000; /* nop */ + instrs[3] = PPC_RAW_NOP(); /* fallthrough to fallback flush */ } if (types & L1D_FLUSH_ORI) { - instrs[i++] = 0x63ff0000; /* ori 31,31,0 speculation barrier */ - instrs[i++] = 0x63de0000; /* ori 30,30,0 L1d flush*/ + instrs[i++] = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ + instrs[i++] = PPC_RAW_ORI(_R30, _R30, 0); /* L1d flush */ } if (types & L1D_FLUSH_MTTRIG) - instrs[i++] = 0x7c12dba6; /* mtspr TRIG2,r0 (SPR #882) */ + instrs[i++] = PPC_RAW_MTSPR(SPRN_TRIG2, _R0); for (i = 0; start < end; start++, i++) { dest = (void *)start + *start; pr_devel("patching dest %lx\n", (unsigned long)dest); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); + patch_instruction(dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_instruction((struct ppc_inst *)(dest + 3), ppc_inst(instrs[3])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_instruction(dest + 3, ppc_inst(instrs[3])); } printk(KERN_DEBUG "uaccess-flush: patched %d locations (%s flush)\n", i, @@ -306,24 +323,24 @@ static int __do_entry_flush_fixups(void *data) long *start, *end; int i; - instrs[0] = 0x60000000; /* nop */ - instrs[1] = 0x60000000; /* nop */ - instrs[2] = 0x60000000; /* nop */ + instrs[0] = PPC_RAW_NOP(); + instrs[1] = PPC_RAW_NOP(); + instrs[2] = PPC_RAW_NOP(); i = 0; if (types == L1D_FLUSH_FALLBACK) { - instrs[i++] = 0x7d4802a6; /* mflr r10 */ - instrs[i++] = 0x60000000; /* branch patched below */ - instrs[i++] = 0x7d4803a6; /* mtlr r10 */ + instrs[i++] = PPC_RAW_MFLR(_R10); + instrs[i++] = PPC_RAW_NOP(); /* branch patched below */ + instrs[i++] = PPC_RAW_MTLR(_R10); } if (types & L1D_FLUSH_ORI) { - instrs[i++] = 0x63ff0000; /* ori 31,31,0 speculation barrier */ - instrs[i++] = 0x63de0000; /* ori 30,30,0 L1d flush*/ + instrs[i++] = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ + instrs[i++] = PPC_RAW_ORI(_R30, _R30, 0); /* L1d flush */ } if (types & L1D_FLUSH_MTTRIG) - instrs[i++] = 0x7c12dba6; /* mtspr TRIG2,r0 (SPR #882) */ + instrs[i++] = PPC_RAW_MTSPR(SPRN_TRIG2, _R0); /* * If we're patching in or out the fallback flush we need to be careful about the @@ -358,14 +375,14 @@ static int __do_entry_flush_fixups(void *data) pr_devel("patching dest %lx\n", (unsigned long)dest); if (types == L1D_FLUSH_FALLBACK) { - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_branch((struct ppc_inst *)(dest + 1), + patch_instruction(dest, ppc_inst(instrs[0])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_branch(dest + 1, (unsigned long)&entry_flush_fallback, BRANCH_SET_LINK); } else { - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_instruction(dest, ppc_inst(instrs[0])); } } @@ -377,14 +394,14 @@ static int __do_entry_flush_fixups(void *data) pr_devel("patching dest %lx\n", (unsigned long)dest); if (types == L1D_FLUSH_FALLBACK) { - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_branch((struct ppc_inst *)(dest + 1), + patch_instruction(dest, ppc_inst(instrs[0])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_branch(dest + 1, (unsigned long)&scv_entry_flush_fallback, BRANCH_SET_LINK); } else { - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); + patch_instruction(dest, ppc_inst(instrs[0])); } } @@ -412,8 +429,9 @@ void do_entry_flush_fixups(enum l1d_flush_type types) stop_machine(__do_entry_flush_fixups, &types, NULL); } -void do_rfi_flush_fixups(enum l1d_flush_type types) +static int __do_rfi_flush_fixups(void *data) { + enum l1d_flush_type types = *(enum l1d_flush_type *)data; unsigned int instrs[3], *dest; long *start, *end; int i; @@ -421,31 +439,31 @@ void do_rfi_flush_fixups(enum l1d_flush_type types) start = PTRRELOC(&__start___rfi_flush_fixup); end = PTRRELOC(&__stop___rfi_flush_fixup); - instrs[0] = 0x60000000; /* nop */ - instrs[1] = 0x60000000; /* nop */ - instrs[2] = 0x60000000; /* nop */ + instrs[0] = PPC_RAW_NOP(); + instrs[1] = PPC_RAW_NOP(); + instrs[2] = PPC_RAW_NOP(); if (types & L1D_FLUSH_FALLBACK) /* b .+16 to fallback flush */ - instrs[0] = 0x48000010; + instrs[0] = PPC_INST_BRANCH | 16; i = 0; if (types & L1D_FLUSH_ORI) { - instrs[i++] = 0x63ff0000; /* ori 31,31,0 speculation barrier */ - instrs[i++] = 0x63de0000; /* ori 30,30,0 L1d flush*/ + instrs[i++] = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ + instrs[i++] = PPC_RAW_ORI(_R30, _R30, 0); /* L1d flush */ } if (types & L1D_FLUSH_MTTRIG) - instrs[i++] = 0x7c12dba6; /* mtspr TRIG2,r0 (SPR #882) */ + instrs[i++] = PPC_RAW_MTSPR(SPRN_TRIG2, _R0); for (i = 0; start < end; start++, i++) { dest = (void *)start + *start; pr_devel("patching dest %lx\n", (unsigned long)dest); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instrs[0])); - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instrs[1])); - patch_instruction((struct ppc_inst *)(dest + 2), ppc_inst(instrs[2])); + patch_instruction(dest, ppc_inst(instrs[0])); + patch_instruction(dest + 1, ppc_inst(instrs[1])); + patch_instruction(dest + 2, ppc_inst(instrs[2])); } printk(KERN_DEBUG "rfi-flush: patched %d locations (%s flush)\n", i, @@ -456,6 +474,29 @@ void do_rfi_flush_fixups(enum l1d_flush_type types) : "ori type" : (types & L1D_FLUSH_MTTRIG) ? "mttrig type" : "unknown"); + + return 0; +} + +void do_rfi_flush_fixups(enum l1d_flush_type types) +{ + /* + * stop_machine gets all CPUs out of the interrupt exit handler same + * as do_stf_barrier_fixups. do_rfi_flush_fixups patching can run + * without stop_machine, so this could be achieved with a broadcast + * IPI instead, but this matches the stf sequence. + */ + static_branch_enable(&interrupt_exit_not_reentrant); + + stop_machine(__do_rfi_flush_fixups, &types, NULL); + + if (types & L1D_FLUSH_FALLBACK) + rfi_exit_reentrant = false; + else + rfi_exit_reentrant = true; + + if (stf_exit_reentrant && rfi_exit_reentrant) + static_branch_disable(&interrupt_exit_not_reentrant); } void do_barrier_nospec_fixups_range(bool enable, void *fixup_start, void *fixup_end) @@ -467,18 +508,18 @@ void do_barrier_nospec_fixups_range(bool enable, void *fixup_start, void *fixup_ start = fixup_start; end = fixup_end; - instr = 0x60000000; /* nop */ + instr = PPC_RAW_NOP(); if (enable) { pr_info("barrier-nospec: using ORI speculation barrier\n"); - instr = 0x63ff0000; /* ori 31,31,0 speculation barrier */ + instr = PPC_RAW_ORI(_R31, _R31, 0); /* speculation barrier */ } for (i = 0; start < end; start++, i++) { dest = (void *)start + *start; pr_devel("patching dest %lx\n", (unsigned long)dest); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instr)); + patch_instruction(dest, ppc_inst(instr)); } printk(KERN_DEBUG "barrier-nospec: patched %d locations\n", i); @@ -508,21 +549,21 @@ void do_barrier_nospec_fixups_range(bool enable, void *fixup_start, void *fixup_ start = fixup_start; end = fixup_end; - instr[0] = PPC_INST_NOP; - instr[1] = PPC_INST_NOP; + instr[0] = PPC_RAW_NOP(); + instr[1] = PPC_RAW_NOP(); if (enable) { pr_info("barrier-nospec: using isync; sync as speculation barrier\n"); - instr[0] = PPC_INST_ISYNC; - instr[1] = PPC_INST_SYNC; + instr[0] = PPC_RAW_ISYNC(); + instr[1] = PPC_RAW_SYNC(); } for (i = 0; start < end; start++, i++) { dest = (void *)start + *start; pr_devel("patching dest %lx\n", (unsigned long)dest); - patch_instruction((struct ppc_inst *)dest, ppc_inst(instr[0])); - patch_instruction((struct ppc_inst *)(dest + 1), ppc_inst(instr[1])); + patch_instruction(dest, ppc_inst(instr[0])); + patch_instruction(dest + 1, ppc_inst(instr[1])); } printk(KERN_DEBUG "barrier-nospec: patched %d locations\n", i); @@ -536,7 +577,7 @@ static void patch_btb_flush_section(long *curr) end = (void *)curr + *(curr + 1); for (; start < end; start++) { pr_devel("patching dest %lx\n", (unsigned long)start); - patch_instruction((struct ppc_inst *)start, ppc_inst(PPC_INST_NOP)); + patch_instruction(start, ppc_inst(PPC_RAW_NOP())); } } @@ -555,7 +596,7 @@ void do_btb_flush_fixups(void) void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end) { long *start, *end; - struct ppc_inst *dest; + u32 *dest; if (!(value & CPU_FTR_LWSYNC)) return ; @@ -572,13 +613,14 @@ void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end) static void do_final_fixups(void) { #if defined(CONFIG_PPC64) && defined(CONFIG_RELOCATABLE) - struct ppc_inst inst, *src, *dest, *end; + struct ppc_inst inst; + u32 *src, *dest, *end; if (PHYSICAL_START == 0) return; - src = (struct ppc_inst *)(KERNELBASE + PHYSICAL_START); - dest = (struct ppc_inst *)KERNELBASE; + src = (u32 *)(KERNELBASE + PHYSICAL_START); + dest = (u32 *)KERNELBASE; end = (void *)src + (__end_interrupts - _stext); while (src < end) { diff --git a/arch/powerpc/lib/restart_table.c b/arch/powerpc/lib/restart_table.c new file mode 100644 index 000000000000..bccb662c1b7b --- /dev/null +++ b/arch/powerpc/lib/restart_table.c @@ -0,0 +1,56 @@ +#include +#include + +struct soft_mask_table_entry { + unsigned long start; + unsigned long end; +}; + +struct restart_table_entry { + unsigned long start; + unsigned long end; + unsigned long fixup; +}; + +extern struct soft_mask_table_entry __start___soft_mask_table[]; +extern struct soft_mask_table_entry __stop___soft_mask_table[]; + +extern struct restart_table_entry __start___restart_table[]; +extern struct restart_table_entry __stop___restart_table[]; + +/* Given an address, look for it in the soft mask table */ +bool search_kernel_soft_mask_table(unsigned long addr) +{ + struct soft_mask_table_entry *smte = __start___soft_mask_table; + + while (smte < __stop___soft_mask_table) { + unsigned long start = smte->start; + unsigned long end = smte->end; + + if (addr >= start && addr < end) + return true; + + smte++; + } + return false; +} +NOKPROBE_SYMBOL(search_kernel_soft_mask_table); + +/* Given an address, look for it in the kernel exception table */ +unsigned long search_kernel_restart_table(unsigned long addr) +{ + struct restart_table_entry *rte = __start___restart_table; + + while (rte < __stop___restart_table) { + unsigned long start = rte->start; + unsigned long end = rte->end; + unsigned long fixup = rte->fixup; + + if (addr >= start && addr < end) + return fixup; + + rte++; + } + return 0; +} +NOKPROBE_SYMBOL(search_kernel_restart_table); diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 45bda2520755..d8d5f901cee1 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1700,6 +1700,28 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->val = regs->ccr & imm; goto compute_done; + case 128: /* setb */ + if (!cpu_has_feature(CPU_FTR_ARCH_300)) + goto unknown_opcode; + /* + * 'ra' encodes the CR field number (bfa) in the top 3 bits. + * Since each CR field is 4 bits, + * we can simply mask off the bottom two bits (bfa * 4) + * to yield the first bit in the CR field. + */ + ra = ra & ~0x3; + /* 'val' stores bits of the CR field (bfa) */ + val = regs->ccr >> (CR0_SHIFT - ra); + /* checks if the LT bit of CR field (bfa) is set */ + if (val & 8) + op->val = -1; + /* checks if the GT bit of CR field (bfa) is set */ + else if (val & 4) + op->val = 1; + else + op->val = 0; + goto compute_done; + case 144: /* mtcrf */ op->type = COMPUTE + SETCC; imm = 0xf0000000UL; @@ -3203,7 +3225,7 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) default: WARN_ON_ONCE(1); } - regs->nip = next_pc; + regs_set_return_ip(regs, next_pc); } NOKPROBE_SYMBOL(emulate_update_regs); @@ -3541,7 +3563,7 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr) /* can't step mtmsr[d] that would clear MSR_RI */ return -1; /* here op.val is the mask of bits to change */ - regs->msr = (regs->msr & ~op.val) | (val & op.val); + regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val)); goto instr_done; #ifdef CONFIG_PPC64 @@ -3554,7 +3576,7 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr) if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) && cpu_has_feature(CPU_FTR_REAL_LE) && regs->gpr[0] == 0x1ebe) { - regs->msr ^= MSR_LE; + regs_set_return_msr(regs, regs->msr ^ MSR_LE); goto instr_done; } regs->gpr[9] = regs->gpr[13]; @@ -3562,8 +3584,8 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr) regs->gpr[11] = regs->nip + 4; regs->gpr[12] = regs->msr & MSR_MASK; regs->gpr[13] = (unsigned long) get_paca(); - regs->nip = (unsigned long) &system_call_common; - regs->msr = MSR_KERNEL; + regs_set_return_ip(regs, (unsigned long) &system_call_common); + regs_set_return_msr(regs, MSR_KERNEL); return 1; #ifdef CONFIG_PPC_BOOK3S_64 @@ -3573,8 +3595,8 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr) regs->gpr[11] = regs->nip + 4; regs->gpr[12] = regs->msr & MSR_MASK; regs->gpr[13] = (unsigned long) get_paca(); - regs->nip = (unsigned long) &system_call_vectored_emulate; - regs->msr = MSR_KERNEL; + regs_set_return_ip(regs, (unsigned long) &system_call_vectored_emulate); + regs_set_return_msr(regs, MSR_KERNEL); return 1; #endif @@ -3585,7 +3607,8 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr) return 0; instr_done: - regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)); + regs_set_return_ip(regs, + truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type))); return 1; } NOKPROBE_SYMBOL(emulate_step); diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 783d1b85ecfe..8b4f6b3e96c4 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -53,6 +53,8 @@ ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | IMM_H(i), \ PPC_RAW_ADDI(t, a, i)) +#define TEST_SETB(t, bfa) ppc_inst(PPC_INST_SETB | ___PPC_RT(t) | ___PPC_RA((bfa & 0x7) << 2)) + static void __init init_pt_regs(struct pt_regs *regs) { @@ -824,8 +826,7 @@ static void __init test_plxvp_pstxvp(void) * XTp = 32xTX + 2xTp * let RA=3 R=0 D=d0||d1=0 R=0 Tp=1 TX=1 */ - instr = ppc_inst_prefix(PPC_RAW_PLXVP(34, 0, 3, 0) >> 32, - PPC_RAW_PLXVP(34, 0, 3, 0) & 0xffffffff); + instr = ppc_inst_prefix(PPC_RAW_PLXVP_P(34, 0, 3, 0), PPC_RAW_PLXVP_S(34, 0, 3, 0)); stepped = emulate_step(®s, instr); if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) { @@ -853,8 +854,7 @@ static void __init test_plxvp_pstxvp(void) * XSp = 32xSX + 2xSp * let RA=3 D=d0||d1=0 R=0 Sp=1 SX=1 */ - instr = ppc_inst_prefix(PPC_RAW_PSTXVP(34, 0, 3, 0) >> 32, - PPC_RAW_PSTXVP(34, 0, 3, 0) & 0xffffffff); + instr = ppc_inst_prefix(PPC_RAW_PSTXVP_P(34, 0, 3, 0), PPC_RAW_PSTXVP_S(34, 0, 3, 0)); stepped = emulate_step(®s, instr); @@ -922,13 +922,40 @@ static struct compute_test compute_tests[] = { .subtests = { { .descr = "R0 = LONG_MAX", - .instr = ppc_inst(PPC_INST_NOP), + .instr = ppc_inst(PPC_RAW_NOP()), .regs = { .gpr[0] = LONG_MAX, } } } }, + { + .mnemonic = "setb", + .cpu_feature = CPU_FTR_ARCH_300, + .subtests = { + { + .descr = "BFA = 1, CR = GT", + .instr = TEST_SETB(20, 1), + .regs = { + .ccr = 0x4000000, + } + }, + { + .descr = "BFA = 4, CR = LT", + .instr = TEST_SETB(20, 4), + .regs = { + .ccr = 0x8000, + } + }, + { + .descr = "BFA = 5, CR = EQ", + .instr = TEST_SETB(20, 5), + .regs = { + .ccr = 0x200, + } + } + } + }, { .mnemonic = "add", .subtests = { @@ -1582,6 +1609,7 @@ static int __init emulate_compute_instr(struct pt_regs *regs, if (!regs || !ppc_inst_val(instr)) return -EINVAL; + /* This is not a return frame regs */ regs->nip = patch_site_addr(&patch__exec_instr); analysed = analyse_instr(&op, regs, instr); diff --git a/arch/powerpc/math-emu/math.c b/arch/powerpc/math-emu/math.c index 327165f26ca6..36761bd00f38 100644 --- a/arch/powerpc/math-emu/math.c +++ b/arch/powerpc/math-emu/math.c @@ -453,7 +453,7 @@ do_mathemu(struct pt_regs *regs) break; } - regs->nip += 4; + regs_add_return_ip(regs, 4); return 0; illegal: diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c index 0a05e51964c1..39b84e7452e1 100644 --- a/arch/powerpc/math-emu/math_efp.c +++ b/arch/powerpc/math-emu/math_efp.c @@ -710,7 +710,7 @@ update_regs: illegal: if (have_e500_cpu_a005_erratum) { /* according to e500 cpu a005 erratum, reissue efp inst */ - regs->nip -= 4; + regs_add_return_ip(regs, -4); pr_debug("re-issue efp inst: %08lx\n", speinsn); return 0; } diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 2ffcf540f08b..eae4ec2988fc 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -5,7 +5,7 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) -obj-y := fault.o mem.o pgtable.o mmap.o maccess.o \ +obj-y := fault.o mem.o pgtable.o mmap.o maccess.o pageattr.o \ init_$(BITS).o pgtable_$(BITS).o \ pgtable-frag.o ioremap.o ioremap_$(BITS).o \ init-common.o mmu_context.o drmem.o \ diff --git a/arch/powerpc/mm/book3s32/Makefile b/arch/powerpc/mm/book3s32/Makefile index 7f0c8a78ba0c..15f4773643d2 100644 --- a/arch/powerpc/mm/book3s32/Makefile +++ b/arch/powerpc/mm/book3s32/Makefile @@ -10,3 +10,4 @@ obj-y += mmu.o mmu_context.o obj-$(CONFIG_PPC_BOOK3S_603) += nohash_low.o obj-$(CONFIG_PPC_BOOK3S_604) += hash_low.o tlb.o obj-$(CONFIG_PPC_KUEP) += kuep.o +obj-$(CONFIG_PPC_KUAP) += kuap.o diff --git a/arch/powerpc/mm/book3s32/hash_low.S b/arch/powerpc/mm/book3s32/hash_low.S index fb4233a5bdf7..6925ce998557 100644 --- a/arch/powerpc/mm/book3s32/hash_low.S +++ b/arch/powerpc/mm/book3s32/hash_low.S @@ -27,8 +27,10 @@ #include #ifdef CONFIG_PTE_64BIT +#define PTE_T_SIZE 8 #define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ #else +#define PTE_T_SIZE 4 #define PTE_FLAGS_OFFSET 0 #endif @@ -488,7 +490,7 @@ _GLOBAL(flush_hash_pages) bne 2f ble cr1,19f addi r4,r4,0x1000 - addi r5,r5,PTE_SIZE + addi r5,r5,PTE_T_SIZE addi r6,r6,-1 b 1b @@ -573,7 +575,7 @@ _GLOBAL(flush_hash_pages) 8: ble cr1,9f /* if all ptes checked */ 81: addi r6,r6,-1 - addi r5,r5,PTE_SIZE + addi r5,r5,PTE_T_SIZE addi r4,r4,0x1000 lwz r0,0(r5) /* check next pte */ cmpwi cr1,r6,1 diff --git a/arch/powerpc/mm/book3s32/kuap.c b/arch/powerpc/mm/book3s32/kuap.c new file mode 100644 index 000000000000..0f920f09af57 --- /dev/null +++ b/arch/powerpc/mm/book3s32/kuap.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include + +struct static_key_false disable_kuap_key; +EXPORT_SYMBOL(disable_kuap_key); + +void kuap_lock_all_ool(void) +{ + kuap_lock_all(); +} +EXPORT_SYMBOL(kuap_lock_all_ool); + +void kuap_unlock_all_ool(void) +{ + kuap_unlock_all(); +} +EXPORT_SYMBOL(kuap_unlock_all_ool); + +void setup_kuap(bool disabled) +{ + if (!disabled) + kuap_lock_all_ool(); + + if (smp_processor_id() != boot_cpuid) + return; + + if (disabled) + static_branch_enable(&disable_kuap_key); + else + pr_info("Activating Kernel Userspace Access Protection\n"); +} diff --git a/arch/powerpc/mm/book3s32/kuep.c b/arch/powerpc/mm/book3s32/kuep.c index 8ed1b8634839..c20733d6e02c 100644 --- a/arch/powerpc/mm/book3s32/kuep.c +++ b/arch/powerpc/mm/book3s32/kuep.c @@ -1,40 +1,20 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include -#include -#include -#include +#include -#define KUEP_UPDATE_TWO_USER_SEGMENTS(n) do { \ - if (TASK_SIZE > ((n) << 28)) \ - mtsr(val1, (n) << 28); \ - if (TASK_SIZE > (((n) + 1) << 28)) \ - mtsr(val2, ((n) + 1) << 28); \ - val1 = (val1 + 0x222) & 0xf0ffffff; \ - val2 = (val2 + 0x222) & 0xf0ffffff; \ -} while (0) +struct static_key_false disable_kuep_key; -static __always_inline void kuep_update(u32 val) +void setup_kuep(bool disabled) { - int val1 = val; - int val2 = (val + 0x111) & 0xf0ffffff; + if (!disabled) + kuep_lock(); - KUEP_UPDATE_TWO_USER_SEGMENTS(0); - KUEP_UPDATE_TWO_USER_SEGMENTS(2); - KUEP_UPDATE_TWO_USER_SEGMENTS(4); - KUEP_UPDATE_TWO_USER_SEGMENTS(6); - KUEP_UPDATE_TWO_USER_SEGMENTS(8); - KUEP_UPDATE_TWO_USER_SEGMENTS(10); - KUEP_UPDATE_TWO_USER_SEGMENTS(12); - KUEP_UPDATE_TWO_USER_SEGMENTS(14); -} + if (smp_processor_id() != boot_cpuid) + return; -void kuep_lock(void) -{ - kuep_update(mfsr(0) | SR_NX); -} - -void kuep_unlock(void) -{ - kuep_update(mfsr(0) & ~SR_NX); + if (disabled) + static_branch_enable(&disable_kuep_key); + else + pr_info("Activating Kernel Userspace Execution Prevention\n"); } diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c index 159930351d9f..27061583a010 100644 --- a/arch/powerpc/mm/book3s32/mmu.c +++ b/arch/powerpc/mm/book3s32/mmu.c @@ -445,26 +445,6 @@ void __init print_system_hash_info(void) pr_info("Hash_mask = 0x%lx\n", Hash_mask); } -#ifdef CONFIG_PPC_KUEP -void __init setup_kuep(bool disabled) -{ - pr_info("Activating Kernel Userspace Execution Prevention\n"); - - if (disabled) - pr_warn("KUEP cannot be disabled yet on 6xx when compiled in\n"); -} -#endif - -#ifdef CONFIG_PPC_KUAP -void __init setup_kuap(bool disabled) -{ - pr_info("Activating Kernel Userspace Access Protection\n"); - - if (disabled) - pr_warn("KUAP cannot be disabled yet on 6xx when compiled in\n"); -} -#endif - void __init early_init_mmu(void) { } diff --git a/arch/powerpc/mm/book3s32/mmu_context.c b/arch/powerpc/mm/book3s32/mmu_context.c index 218996e40a8e..e2708e387dc3 100644 --- a/arch/powerpc/mm/book3s32/mmu_context.c +++ b/arch/powerpc/mm/book3s32/mmu_context.c @@ -23,6 +23,12 @@ #include +/* + * Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +void *abatron_pteptrs[2]; + /* * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs * (virtual segment identifiers) for each context. Although the @@ -39,19 +45,6 @@ #define LAST_CONTEXT 32767 #define FIRST_CONTEXT 1 -/* - * This function defines the mapping from contexts to VSIDs (virtual - * segment IDs). We use a skew on both the context and the high 4 bits - * of the 32-bit virtual address (the "effective segment ID") in order - * to spread out the entries in the MMU hash table. Note, if this - * function is changed then arch/ppc/mm/hashtable.S will have to be - * changed to correspond. - * - * - * CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ - * & 0xffffff) - */ - static unsigned long next_mmu_context; static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; @@ -111,3 +104,32 @@ void __init mmu_context_init(void) context_map[0] = (1 << FIRST_CONTEXT) - 1; next_mmu_context = FIRST_CONTEXT; } + +void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) +{ + long id = next->context.id; + unsigned long val; + + if (id < 0) + panic("mm_struct %p has no context ID", next); + + isync(); + + val = CTX_TO_VSID(id, 0); + if (!kuep_is_disabled()) + val |= SR_NX; + if (!kuap_is_disabled()) + val |= SR_KS; + + update_user_segments(val); + + if (IS_ENABLED(CONFIG_BDI_SWITCH)) + abatron_pteptrs[1] = next->pgd; + + if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) + mtspr(SPRN_SDR1, rol32(__pa(next->pgd), 4) & 0xffff01ff); + + mb(); /* sync */ + isync(); +} +EXPORT_SYMBOL(switch_mmu_context); diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c index 96d9aa164007..ac5720371c0d 100644 --- a/arch/powerpc/mm/book3s64/hash_utils.c +++ b/arch/powerpc/mm/book3s64/hash_utils.c @@ -1522,8 +1522,8 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap, } EXPORT_SYMBOL_GPL(hash_page); -DECLARE_INTERRUPT_HANDLER_RET(__do_hash_fault); -DEFINE_INTERRUPT_HANDLER_RET(__do_hash_fault) +DECLARE_INTERRUPT_HANDLER(__do_hash_fault); +DEFINE_INTERRUPT_HANDLER(__do_hash_fault) { unsigned long ea = regs->dar; unsigned long dsisr = regs->dsisr; @@ -1533,6 +1533,11 @@ DEFINE_INTERRUPT_HANDLER_RET(__do_hash_fault) unsigned int region_id; long err; + if (unlikely(dsisr & (DSISR_BAD_FAULT_64S | DSISR_KEYFAULT))) { + hash__do_page_fault(regs); + return; + } + region_id = get_region_id(ea); if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) mm = &init_mm; @@ -1571,9 +1576,10 @@ DEFINE_INTERRUPT_HANDLER_RET(__do_hash_fault) bad_page_fault(regs, SIGBUS); } err = 0; - } - return err; + } else if (err) { + hash__do_page_fault(regs); + } } /* @@ -1582,13 +1588,6 @@ DEFINE_INTERRUPT_HANDLER_RET(__do_hash_fault) */ DEFINE_INTERRUPT_HANDLER_RAW(do_hash_fault) { - unsigned long dsisr = regs->dsisr; - - if (unlikely(dsisr & (DSISR_BAD_FAULT_64S | DSISR_KEYFAULT))) { - hash__do_page_fault(regs); - return 0; - } - /* * If we are in an "NMI" (e.g., an interrupt when soft-disabled), then * don't call hash_page, just fail the fault. This is required to @@ -1607,8 +1606,7 @@ DEFINE_INTERRUPT_HANDLER_RAW(do_hash_fault) return 0; } - if (__do_hash_fault(regs)) - hash__do_page_fault(regs); + __do_hash_fault(regs); return 0; } diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index 318ec4f33661..ae12fb5559cb 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -354,22 +354,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) /* * We use 128 set in radix mode and 256 set in hpt mode. */ -static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) +static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) { int set; asm volatile("ptesync": : :"memory"); - /* - * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL, - * also flush the entire Page Walk Cache. - */ - __tlbiel_pid(pid, 0, ric); + switch (ric) { + case RIC_FLUSH_PWC: - /* For PWC, only one flush is needed */ - if (ric == RIC_FLUSH_PWC) { + /* For PWC, only one flush is needed */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); ppc_after_tlbiel_barrier(); return; + case RIC_FLUSH_TLB: + __tlbiel_pid(pid, 0, RIC_FLUSH_TLB); + break; + case RIC_FLUSH_ALL: + default: + /* + * Flush the first set of the TLB, and if + * we're doing a RIC_FLUSH_ALL, also flush + * the entire Page Walk Cache. + */ + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); } if (!cpu_has_feature(CPU_FTR_ARCH_31)) { @@ -1290,7 +1298,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) } } -static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, +static void __radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, unsigned long end, int psize, bool also_pwc) { diff --git a/arch/powerpc/mm/ioremap_32.c b/arch/powerpc/mm/ioremap_32.c index 743e11384dea..9d13143b8be4 100644 --- a/arch/powerpc/mm/ioremap_32.c +++ b/arch/powerpc/mm/ioremap_32.c @@ -70,10 +70,10 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, pgprot_t prot, void *call */ pr_warn("ioremap() called early from %pS. Use early_ioremap() instead\n", caller); - err = early_ioremap_range(ioremap_bot - size, p, size, prot); + err = early_ioremap_range(ioremap_bot - size - PAGE_SIZE, p, size, prot); if (err) return NULL; - ioremap_bot -= size; + ioremap_bot -= size + PAGE_SIZE; return (void __iomem *)ioremap_bot + offset; } diff --git a/arch/powerpc/mm/ioremap_64.c b/arch/powerpc/mm/ioremap_64.c index ba5cbb0d66bd..3acece00b33e 100644 --- a/arch/powerpc/mm/ioremap_64.c +++ b/arch/powerpc/mm/ioremap_64.c @@ -38,7 +38,7 @@ void __iomem *__ioremap_caller(phys_addr_t addr, unsigned long size, return NULL; ret = (void __iomem *)ioremap_bot + offset; - ioremap_bot += size; + ioremap_bot += size + PAGE_SIZE; return ret; } diff --git a/arch/powerpc/mm/maccess.c b/arch/powerpc/mm/maccess.c index a3c30a884076..aad7c47e0030 100644 --- a/arch/powerpc/mm/maccess.c +++ b/arch/powerpc/mm/maccess.c @@ -12,7 +12,7 @@ bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) return is_kernel_addr((unsigned long)unsafe_src); } -int copy_inst_from_kernel_nofault(struct ppc_inst *inst, struct ppc_inst *src) +int copy_inst_from_kernel_nofault(struct ppc_inst *inst, u32 *src) { unsigned int val, suffix; int err; @@ -21,7 +21,7 @@ int copy_inst_from_kernel_nofault(struct ppc_inst *inst, struct ppc_inst *src) if (err) return err; if (IS_ENABLED(CONFIG_PPC64) && get_op(val) == OP_PREFIX) { - err = copy_from_kernel_nofault(&suffix, (void *)src + 4, 4); + err = copy_from_kernel_nofault(&suffix, src + 1, sizeof(suffix)); *inst = ppc_inst_prefix(val, suffix); } else { *inst = ppc_inst(val); diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index c5e520c6f13b..ad198b439222 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -28,6 +28,9 @@ unsigned long long memory_limit; bool init_mem_is_free; +unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] __page_aligned_bss; +EXPORT_SYMBOL(empty_zero_page); + pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { @@ -299,6 +302,10 @@ void __init mem_init(void) ioremap_bot, IOREMAP_TOP); pr_info(" * 0x%08lx..0x%08lx : vmalloc & ioremap\n", VMALLOC_START, VMALLOC_END); +#ifdef MODULES_VADDR + pr_info(" * 0x%08lx..0x%08lx : modules\n", + MODULES_VADDR, MODULES_END); +#endif #endif /* CONFIG_PPC32 */ } diff --git a/arch/powerpc/mm/nohash/44x.c b/arch/powerpc/mm/nohash/44x.c index 3d6ae7c72412..e079f26b267e 100644 --- a/arch/powerpc/mm/nohash/44x.c +++ b/arch/powerpc/mm/nohash/44x.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -239,3 +240,19 @@ void __init mmu_init_secondary(int cpu) } } #endif /* CONFIG_SMP */ + +#ifdef CONFIG_PPC_KUEP +void setup_kuep(bool disabled) +{ + if (smp_processor_id() != boot_cpuid) + return; + + if (disabled) + patch_instruction_site(&patch__tlb_44x_kuep, ppc_inst(PPC_RAW_NOP())); + else + pr_info("Activating Kernel Userspace Execution Prevention\n"); + + if (IS_ENABLED(CONFIG_PPC_47x) && disabled) + patch_instruction_site(&patch__tlb_47x_kuep, ppc_inst(PPC_RAW_NOP())); +} +#endif diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index 71bfdbedacee..60780e089118 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -212,37 +212,6 @@ void __init setup_initial_memory_limit(phys_addr_t first_memblock_base, memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M)); } -/* - * Set up to use a given MMU context. - * id is context number, pgd is PGD pointer. - * - * We place the physical address of the new task page directory loaded - * into the MMU base register, and set the ASID compare register with - * the new "context." - */ -void set_context(unsigned long id, pgd_t *pgd) -{ - s16 offset = (s16)(__pa(swapper_pg_dir)); - - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is passed as second argument. - */ - if (IS_ENABLED(CONFIG_BDI_SWITCH)) - abatron_pteptrs[1] = pgd; - - /* Register M_TWB will contain base address of level 1 table minus the - * lower part of the kernel PGDIR base address, so that all accesses to - * level 1 table are done relative to lower part of kernel PGDIR base - * address. - */ - mtspr(SPRN_M_TWB, __pa(pgd) - offset); - - /* Update context */ - mtspr(SPRN_M_CASID, id - 1); - /* sync */ - mb(); -} - #ifdef CONFIG_PPC_KUEP void __init setup_kuep(bool disabled) { @@ -256,12 +225,17 @@ void __init setup_kuep(bool disabled) #endif #ifdef CONFIG_PPC_KUAP +struct static_key_false disable_kuap_key; +EXPORT_SYMBOL(disable_kuap_key); + void __init setup_kuap(bool disabled) { - pr_info("Activating Kernel Userspace Access Protection\n"); + if (disabled) { + static_branch_enable(&disable_kuap_key); + return; + } - if (disabled) - pr_warn("KUAP cannot be disabled yet on 8xx when compiled in\n"); + pr_info("Activating Kernel Userspace Access Protection\n"); mtspr(SPRN_MD_AP, MD_APG_KUAP); } diff --git a/arch/powerpc/mm/nohash/mmu_context.c b/arch/powerpc/mm/nohash/mmu_context.c index aac81c9f84a5..44b2b5e7cabe 100644 --- a/arch/powerpc/mm/nohash/mmu_context.c +++ b/arch/powerpc/mm/nohash/mmu_context.c @@ -21,21 +21,6 @@ * also clear mm->cpu_vm_mask bits when processes are migrated */ -//#define DEBUG_MAP_CONSISTENCY -//#define DEBUG_CLAMP_LAST_CONTEXT 31 -//#define DEBUG_HARDER - -/* We don't use DEBUG because it tends to be compiled in always nowadays - * and this would generate way too much output - */ -#ifdef DEBUG_HARDER -#define pr_hard(args...) printk(KERN_DEBUG args) -#define pr_hardcont(args...) printk(KERN_CONT args) -#else -#define pr_hard(args...) do { } while(0) -#define pr_hardcont(args...) do { } while(0) -#endif - #include #include #include @@ -47,9 +32,16 @@ #include #include +#include #include +/* + * Room for two PTE table pointers, usually the kernel and current user + * pointer to their respective root page table (pgdir). + */ +void *abatron_pteptrs[2]; + /* * The MPC8xx has only 16 contexts. We rotate through them on each task switch. * A better way would be to keep track of tasks that own contexts, and implement @@ -68,9 +60,7 @@ * -- BenH */ #define FIRST_CONTEXT 1 -#ifdef DEBUG_CLAMP_LAST_CONTEXT -#define LAST_CONTEXT DEBUG_CLAMP_LAST_CONTEXT -#elif defined(CONFIG_PPC_8xx) +#if defined(CONFIG_PPC_8xx) #define LAST_CONTEXT 16 #elif defined(CONFIG_PPC_47x) #define LAST_CONTEXT 65535 @@ -80,9 +70,7 @@ static unsigned int next_context, nr_free_contexts; static unsigned long *context_map; -#ifdef CONFIG_SMP static unsigned long *stale_map[NR_CPUS]; -#endif static struct mm_struct **context_mm; static DEFINE_RAW_SPINLOCK(context_lock); @@ -105,7 +93,6 @@ static DEFINE_RAW_SPINLOCK(context_lock); * the stale map as we can just flush the local CPU * -- benh */ -#ifdef CONFIG_SMP static unsigned int steal_context_smp(unsigned int id) { struct mm_struct *mm; @@ -127,7 +114,6 @@ static unsigned int steal_context_smp(unsigned int id) id = FIRST_CONTEXT; continue; } - pr_hardcont(" | steal %d from 0x%p", id, mm); /* Mark this mm has having no context anymore */ mm->context.id = MMU_NO_CONTEXT; @@ -158,34 +144,25 @@ static unsigned int steal_context_smp(unsigned int id) /* This will cause the caller to try again */ return MMU_NO_CONTEXT; } -#endif /* CONFIG_SMP */ static unsigned int steal_all_contexts(void) { struct mm_struct *mm; -#ifdef CONFIG_SMP int cpu = smp_processor_id(); -#endif unsigned int id; for (id = FIRST_CONTEXT; id <= LAST_CONTEXT; id++) { /* Pick up the victim mm */ mm = context_mm[id]; - pr_hardcont(" | steal %d from 0x%p", id, mm); - /* Mark this mm as having no context anymore */ mm->context.id = MMU_NO_CONTEXT; if (id != FIRST_CONTEXT) { context_mm[id] = NULL; __clear_bit(id, context_map); -#ifdef DEBUG_MAP_CONSISTENCY - mm->context.active = 0; -#endif } -#ifdef CONFIG_SMP - __clear_bit(id, stale_map[cpu]); -#endif + if (IS_ENABLED(CONFIG_SMP)) + __clear_bit(id, stale_map[cpu]); } /* Flush the TLB for all contexts (not to be used on SMP) */ @@ -204,15 +181,11 @@ static unsigned int steal_all_contexts(void) static unsigned int steal_context_up(unsigned int id) { struct mm_struct *mm; -#ifdef CONFIG_SMP int cpu = smp_processor_id(); -#endif /* Pick up the victim mm */ mm = context_mm[id]; - pr_hardcont(" | steal %d from 0x%p", id, mm); - /* Flush the TLB for that context */ local_flush_tlb_mm(mm); @@ -220,81 +193,64 @@ static unsigned int steal_context_up(unsigned int id) mm->context.id = MMU_NO_CONTEXT; /* XXX This clear should ultimately be part of local_flush_tlb_mm */ -#ifdef CONFIG_SMP - __clear_bit(id, stale_map[cpu]); -#endif + if (IS_ENABLED(CONFIG_SMP)) + __clear_bit(id, stale_map[cpu]); return id; } -#ifdef DEBUG_MAP_CONSISTENCY -static void context_check_map(void) +static void set_context(unsigned long id, pgd_t *pgd) { - unsigned int id, nrf, nact; + if (IS_ENABLED(CONFIG_PPC_8xx)) { + s16 offset = (s16)(__pa(swapper_pg_dir)); - nrf = nact = 0; - for (id = FIRST_CONTEXT; id <= LAST_CONTEXT; id++) { - int used = test_bit(id, context_map); - if (!used) - nrf++; - if (used != (context_mm[id] != NULL)) - pr_err("MMU: Context %d is %s and MM is %p !\n", - id, used ? "used" : "free", context_mm[id]); - if (context_mm[id] != NULL) - nact += context_mm[id]->context.active; + /* + * Register M_TWB will contain base address of level 1 table minus the + * lower part of the kernel PGDIR base address, so that all accesses to + * level 1 table are done relative to lower part of kernel PGDIR base + * address. + */ + mtspr(SPRN_M_TWB, __pa(pgd) - offset); + + /* Update context */ + mtspr(SPRN_M_CASID, id - 1); + + /* sync */ + mb(); + } else { + if (IS_ENABLED(CONFIG_40x)) + mb(); /* sync */ + + mtspr(SPRN_PID, id); + isync(); } - if (nrf != nr_free_contexts) { - pr_err("MMU: Free context count out of sync ! (%d vs %d)\n", - nr_free_contexts, nrf); - nr_free_contexts = nrf; - } - if (nact > num_online_cpus()) - pr_err("MMU: More active contexts than CPUs ! (%d vs %d)\n", - nact, num_online_cpus()); - if (FIRST_CONTEXT > 0 && !test_bit(0, context_map)) - pr_err("MMU: Context 0 has been freed !!!\n"); } -#else -static void context_check_map(void) { } -#endif void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { unsigned int id; -#ifdef CONFIG_SMP unsigned int i, cpu = smp_processor_id(); -#endif unsigned long *map; /* No lockless fast path .. yet */ raw_spin_lock(&context_lock); - pr_hard("[%d] activating context for mm @%p, active=%d, id=%d", - cpu, next, next->context.active, next->context.id); - -#ifdef CONFIG_SMP - /* Mark us active and the previous one not anymore */ - next->context.active++; - if (prev) { - pr_hardcont(" (old=0x%p a=%d)", prev, prev->context.active); - WARN_ON(prev->context.active < 1); - prev->context.active--; + if (IS_ENABLED(CONFIG_SMP)) { + /* Mark us active and the previous one not anymore */ + next->context.active++; + if (prev) { + WARN_ON(prev->context.active < 1); + prev->context.active--; + } } again: -#endif /* CONFIG_SMP */ /* If we already have a valid assigned context, skip all that */ id = next->context.id; - if (likely(id != MMU_NO_CONTEXT)) { -#ifdef DEBUG_MAP_CONSISTENCY - if (context_mm[id] != next) - pr_err("MMU: mm 0x%p has id %d but context_mm[%d] says 0x%p\n", - next, id, id, context_mm[id]); -#endif + if (likely(id != MMU_NO_CONTEXT)) goto ctxt_ok; - } /* We really don't have a context, let's try to acquire one */ id = next_context; @@ -304,14 +260,12 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, /* No more free contexts, let's try to steal one */ if (nr_free_contexts == 0) { -#ifdef CONFIG_SMP if (num_online_cpus() > 1) { id = steal_context_smp(id); if (id == MMU_NO_CONTEXT) goto again; goto stolen; } -#endif /* CONFIG_SMP */ if (IS_ENABLED(CONFIG_PPC_8xx)) id = steal_all_contexts(); else @@ -330,20 +284,13 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, next_context = id + 1; context_mm[id] = next; next->context.id = id; - pr_hardcont(" | new id=%d,nrf=%d", id, nr_free_contexts); - context_check_map(); ctxt_ok: /* If that context got marked stale on this CPU, then flush the * local TLB for it and unmark it before we use it */ -#ifdef CONFIG_SMP - if (test_bit(id, stale_map[cpu])) { - pr_hardcont(" | stale flush %d [%d..%d]", - id, cpu_first_thread_sibling(cpu), - cpu_last_thread_sibling(cpu)); - + if (IS_ENABLED(CONFIG_SMP) && test_bit(id, stale_map[cpu])) { local_flush_tlb_mm(next); /* XXX This clear should ultimately be part of local_flush_tlb_mm */ @@ -353,10 +300,10 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, __clear_bit(id, stale_map[i]); } } -#endif /* Flick the MMU and release lock */ - pr_hardcont(" -> %d\n", id); + if (IS_ENABLED(CONFIG_BDI_SWITCH)) + abatron_pteptrs[1] = next->pgd; set_context(id, next->pgd); raw_spin_unlock(&context_lock); } @@ -366,8 +313,6 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next, */ int init_new_context(struct task_struct *t, struct mm_struct *mm) { - pr_hard("initing context for mm @%p\n", mm); - /* * We have MMU_NO_CONTEXT set to be ~0. Hence check * explicitly against context.id == 0. This ensures that we properly @@ -401,16 +346,12 @@ void destroy_context(struct mm_struct *mm) if (id != MMU_NO_CONTEXT) { __clear_bit(id, context_map); mm->context.id = MMU_NO_CONTEXT; -#ifdef DEBUG_MAP_CONSISTENCY - mm->context.active = 0; -#endif context_mm[id] = NULL; nr_free_contexts++; } raw_spin_unlock_irqrestore(&context_lock, flags); } -#ifdef CONFIG_SMP static int mmu_ctx_cpu_prepare(unsigned int cpu) { /* We don't touch CPU 0 map, it's allocated at aboot and kept @@ -419,7 +360,6 @@ static int mmu_ctx_cpu_prepare(unsigned int cpu) if (cpu == boot_cpuid) return 0; - pr_devel("MMU: Allocating stale context map for CPU %d\n", cpu); stale_map[cpu] = kzalloc(CTX_MAP_SIZE, GFP_KERNEL); return 0; } @@ -430,7 +370,6 @@ static int mmu_ctx_cpu_dead(unsigned int cpu) if (cpu == boot_cpuid) return 0; - pr_devel("MMU: Freeing stale context map for CPU %d\n", cpu); kfree(stale_map[cpu]); stale_map[cpu] = NULL; @@ -440,8 +379,6 @@ static int mmu_ctx_cpu_dead(unsigned int cpu) return 0; } -#endif /* CONFIG_SMP */ - /* * Initialize the context management stuff. */ @@ -465,16 +402,16 @@ void __init mmu_context_init(void) if (!context_mm) panic("%s: Failed to allocate %zu bytes\n", __func__, sizeof(void *) * (LAST_CONTEXT + 1)); -#ifdef CONFIG_SMP - stale_map[boot_cpuid] = memblock_alloc(CTX_MAP_SIZE, SMP_CACHE_BYTES); - if (!stale_map[boot_cpuid]) - panic("%s: Failed to allocate %zu bytes\n", __func__, - CTX_MAP_SIZE); + if (IS_ENABLED(CONFIG_SMP)) { + stale_map[boot_cpuid] = memblock_alloc(CTX_MAP_SIZE, SMP_CACHE_BYTES); + if (!stale_map[boot_cpuid]) + panic("%s: Failed to allocate %zu bytes\n", __func__, + CTX_MAP_SIZE); - cpuhp_setup_state_nocalls(CPUHP_POWERPC_MMU_CTX_PREPARE, - "powerpc/mmu/ctx:prepare", - mmu_ctx_cpu_prepare, mmu_ctx_cpu_dead); -#endif + cpuhp_setup_state_nocalls(CPUHP_POWERPC_MMU_CTX_PREPARE, + "powerpc/mmu/ctx:prepare", + mmu_ctx_cpu_prepare, mmu_ctx_cpu_dead); + } printk(KERN_INFO "MMU: Allocated %zu bytes of context maps for %d contexts\n", diff --git a/arch/powerpc/mm/nohash/tlb_low.S b/arch/powerpc/mm/nohash/tlb_low.S index 68797e072f55..4613bf8e9aae 100644 --- a/arch/powerpc/mm/nohash/tlb_low.S +++ b/arch/powerpc/mm/nohash/tlb_low.S @@ -360,19 +360,6 @@ _GLOBAL(_tlbivax_bcast) sync wrtee r10 blr - -_GLOBAL(set_context) -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r4, 0x4(r5) -#endif - mtspr SPRN_PID,r3 - isync /* Force context change */ - blr #else #error Unsupported processor type ! #endif diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c new file mode 100644 index 000000000000..0876216ceee6 --- /dev/null +++ b/arch/powerpc/mm/pageattr.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * MMU-generic set_memory implementation for powerpc + * + * Copyright 2019-2021, IBM Corporation. + */ + +#include +#include +#include + +#include +#include +#include + + +/* + * Updates the attributes of a page in three steps: + * + * 1. invalidate the page table entry + * 2. flush the TLB + * 3. install the new entry with the updated attributes + * + * Invalidating the pte means there are situations where this will not work + * when in theory it should. + * For example: + * - removing write from page whilst it is being executed + * - setting a page read-only whilst it is being read by another CPU + * + */ +static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) +{ + long action = (long)data; + pte_t pte; + + spin_lock(&init_mm.page_table_lock); + + /* invalidate the PTE so it's safe to modify */ + pte = ptep_get_and_clear(&init_mm, addr, ptep); + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); + + /* modify the PTE bits as desired, then apply */ + switch (action) { + case SET_MEMORY_RO: + pte = pte_wrprotect(pte); + break; + case SET_MEMORY_RW: + pte = pte_mkwrite(pte_mkdirty(pte)); + break; + case SET_MEMORY_NX: + pte = pte_exprotect(pte); + break; + case SET_MEMORY_X: + pte = pte_mkexec(pte); + break; + default: + WARN_ON_ONCE(1); + break; + } + + set_pte_at(&init_mm, addr, ptep, pte); + + /* See ptesync comment in radix__set_pte_at() */ + if (radix_enabled()) + asm volatile("ptesync": : :"memory"); + spin_unlock(&init_mm.page_table_lock); + + return 0; +} + +int change_memory_attr(unsigned long addr, int numpages, long action) +{ + unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE); + unsigned long size = numpages * PAGE_SIZE; + + if (!numpages) + return 0; + + if (WARN_ON_ONCE(is_vmalloc_or_module_addr((void *)addr) && + is_vm_area_hugepages((void *)addr))) + return -EINVAL; + +#ifdef CONFIG_PPC_BOOK3S_64 + /* + * On hash, the linear mapping is not in the Linux page table so + * apply_to_existing_page_range() will have no effect. If in the future + * the set_memory_* functions are used on the linear map this will need + * to be updated. + */ + if (!radix_enabled()) { + int region = get_region_id(addr); + + if (WARN_ON_ONCE(region != VMALLOC_REGION_ID && region != IO_REGION_ID)) + return -EINVAL; + } +#endif + + return apply_to_existing_page_range(&init_mm, start, size, + change_page_attr, (void *)action); +} + +/* + * Set the attributes of a page: + * + * This function is used by PPC32 at the end of init to set final kernel memory + * protection. It includes changing the maping of the page it is executing from + * and data pages it is using. + */ +static int set_page_attr(pte_t *ptep, unsigned long addr, void *data) +{ + pgprot_t prot = __pgprot((unsigned long)data); + + spin_lock(&init_mm.page_table_lock); + + set_pte_at(&init_mm, addr, ptep, pte_modify(*ptep, prot)); + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); + + spin_unlock(&init_mm.page_table_lock); + + return 0; +} + +int set_memory_attr(unsigned long addr, int numpages, pgprot_t prot) +{ + unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE); + unsigned long sz = numpages * PAGE_SIZE; + + if (numpages <= 0) + return 0; + + return apply_to_existing_page_range(&init_mm, start, sz, set_page_attr, + (void *)pgprot_val(prot)); +} diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c index 354611940118..cd16b407f47e 100644 --- a/arch/powerpc/mm/pgtable.c +++ b/arch/powerpc/mm/pgtable.c @@ -28,6 +28,14 @@ #include #include +#ifdef CONFIG_PPC64 +#define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD) +#else +#define PGD_ALIGN PAGE_SIZE +#endif + +pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN); + static inline int is_exec_fault(void) { return current->thread.regs && TRAP(current->thread.regs) == 0x400; diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index e0ec67a16887..dcf5ecca19d9 100644 --- a/arch/powerpc/mm/pgtable_32.c +++ b/arch/powerpc/mm/pgtable_32.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -132,64 +133,20 @@ void __init mapin_ram(void) } } -static int __change_page_attr_noflush(struct page *page, pgprot_t prot) -{ - pte_t *kpte; - unsigned long address; - - BUG_ON(PageHighMem(page)); - address = (unsigned long)page_address(page); - - if (v_block_mapped(address)) - return 0; - kpte = virt_to_kpte(address); - if (!kpte) - return -EINVAL; - __set_pte_at(&init_mm, address, kpte, mk_pte(page, prot), 0); - - return 0; -} - -/* - * Change the page attributes of an page in the linear mapping. - * - * THIS DOES NOTHING WITH BAT MAPPINGS, DEBUG USE ONLY - */ -static int change_page_attr(struct page *page, int numpages, pgprot_t prot) -{ - int i, err = 0; - unsigned long flags; - struct page *start = page; - - local_irq_save(flags); - for (i = 0; i < numpages; i++, page++) { - err = __change_page_attr_noflush(page, prot); - if (err) - break; - } - wmb(); - local_irq_restore(flags); - flush_tlb_kernel_range((unsigned long)page_address(start), - (unsigned long)page_address(page)); - return err; -} - void mark_initmem_nx(void) { - struct page *page = virt_to_page(_sinittext); unsigned long numpages = PFN_UP((unsigned long)_einittext) - PFN_DOWN((unsigned long)_sinittext); if (v_block_mapped((unsigned long)_sinittext)) mmu_mark_initmem_nx(); else - change_page_attr(page, numpages, PAGE_KERNEL); + set_memory_attr((unsigned long)_sinittext, numpages, PAGE_KERNEL); } #ifdef CONFIG_STRICT_KERNEL_RWX void mark_rodata_ro(void) { - struct page *page; unsigned long numpages; if (v_block_mapped((unsigned long)_stext + 1)) { @@ -198,20 +155,18 @@ void mark_rodata_ro(void) return; } - page = virt_to_page(_stext); numpages = PFN_UP((unsigned long)_etext) - PFN_DOWN((unsigned long)_stext); - change_page_attr(page, numpages, PAGE_KERNEL_ROX); + set_memory_attr((unsigned long)_stext, numpages, PAGE_KERNEL_ROX); /* * mark .rodata as read only. Use __init_begin rather than __end_rodata * to cover NOTES and EXCEPTION_TABLE. */ - page = virt_to_page(__start_rodata); numpages = PFN_UP((unsigned long)__init_begin) - PFN_DOWN((unsigned long)__start_rodata); - change_page_attr(page, numpages, PAGE_KERNEL_RO); + set_memory_attr((unsigned long)__start_rodata, numpages, PAGE_KERNEL_RO); // mark_initmem_nx() should have already run by now ptdump_check_wx(); @@ -221,9 +176,14 @@ void mark_rodata_ro(void) #ifdef CONFIG_DEBUG_PAGEALLOC void __kernel_map_pages(struct page *page, int numpages, int enable) { + unsigned long addr = (unsigned long)page_address(page); + if (PageHighMem(page)) return; - change_page_attr(page, numpages, enable ? PAGE_KERNEL : __pgprot(0)); + if (enable) + set_memory_attr(addr, numpages, PAGE_KERNEL); + else + set_memory_attr(addr, numpages, __pgprot(0)); } #endif /* CONFIG_DEBUG_PAGEALLOC */ diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c index aca354fb670b..5062c58b1e5b 100644 --- a/arch/powerpc/mm/ptdump/ptdump.c +++ b/arch/powerpc/mm/ptdump/ptdump.c @@ -58,8 +58,6 @@ struct pg_state { const struct addr_marker *marker; unsigned long start_address; unsigned long start_pa; - unsigned long last_pa; - unsigned long page_size; unsigned int level; u64 current_flags; bool check_wx; @@ -163,8 +161,6 @@ static void dump_flag_info(struct pg_state *st, const struct flag_info static void dump_addr(struct pg_state *st, unsigned long addr) { - unsigned long delta; - #ifdef CONFIG_PPC64 #define REG "0x%016lx" #else @@ -172,14 +168,8 @@ static void dump_addr(struct pg_state *st, unsigned long addr) #endif pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr - 1); - if (st->start_pa == st->last_pa && st->start_address + st->page_size != addr) { - pt_dump_seq_printf(st->seq, "[" REG "]", st->start_pa); - delta = st->page_size >> 10; - } else { - pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa); - delta = (addr - st->start_address) >> 10; - } - pt_dump_size(st->seq, delta); + pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa); + pt_dump_size(st->seq, (addr - st->start_address) >> 10); } static void note_prot_wx(struct pg_state *st, unsigned long addr) @@ -208,7 +198,6 @@ static void note_page_update_state(struct pg_state *st, unsigned long addr, st->current_flags = flag; st->start_address = addr; st->start_pa = pa; - st->page_size = page_size; while (addr >= st->marker[1].start_address) { st->marker++; @@ -220,7 +209,6 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned int level, u64 val, unsigned long page_size) { u64 flag = val & pg_level[level].mask; - u64 pa = val & PTE_RPN_MASK; /* At first no level is set */ if (!st->level) { @@ -232,12 +220,9 @@ static void note_page(struct pg_state *st, unsigned long addr, * - we change levels in the tree. * - the address is in a different section of memory and is thus * used for a different purpose, regardless of the flags. - * - the pa of this page is not adjacent to the last inspected page */ } else if (flag != st->current_flags || level != st->level || - addr >= st->marker[1].start_address || - (pa != st->last_pa + st->page_size && - (pa != st->start_pa || st->start_pa != st->last_pa))) { + addr >= st->marker[1].start_address) { /* Check the PTE flags */ if (st->current_flags) { @@ -259,7 +244,6 @@ static void note_page(struct pg_state *st, unsigned long addr, */ note_page_update_state(st, addr, level, val, page_size); } - st->last_pa = pa; } static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start) diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c index 798ac4350a82..53aefee3fe70 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -237,6 +237,7 @@ skip_codegen_passes: fp->jited_len = alloclen; bpf_flush_icache(bpf_hdr, (u8 *)bpf_hdr + (bpf_hdr->pages * PAGE_SIZE)); + bpf_jit_binary_lock_ro(bpf_hdr); if (!fp->is_func || extra_pass) { bpf_prog_fill_jited_linfo(fp, addrs); out_addrs: @@ -257,15 +258,3 @@ out: return fp; } - -/* Overriding bpf_jit_free() as we don't set images read-only. */ -void bpf_jit_free(struct bpf_prog *fp) -{ - unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK; - struct bpf_binary_header *bpf_hdr = (void *)addr; - - if (fp->jited) - bpf_jit_binary_free(bpf_hdr); - - bpf_prog_unlock_free(fp); -} diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c index bbb16099e8c7..cbe5b399ed86 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -108,20 +108,20 @@ void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) int i; /* First arg comes in as a 32 bits pointer. */ - EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_1), __REG_R3)); + EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_1), _R3)); EMIT(PPC_RAW_LI(bpf_to_ppc(ctx, BPF_REG_1) - 1, 0)); - EMIT(PPC_RAW_STWU(__REG_R1, __REG_R1, -BPF_PPC_STACKFRAME(ctx))); + EMIT(PPC_RAW_STWU(_R1, _R1, -BPF_PPC_STACKFRAME(ctx))); /* * Initialize tail_call_cnt in stack frame if we do tail calls. * Otherwise, put in NOPs so that it can be skipped when we are * invoked through a tail call. */ - if (ctx->seen & SEEN_TAILCALL) { - EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_1) - 1, __REG_R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); - } else { + if (ctx->seen & SEEN_TAILCALL) + EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_1) - 1, _R1, + bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); + else EMIT(PPC_RAW_NOP()); - } #define BPF_TAILCALL_PROLOGUE_SIZE 16 @@ -130,30 +130,30 @@ void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) * save/restore LR unless we call other functions */ if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_MFLR(__REG_R0)); + EMIT(PPC_RAW_MFLR(_R0)); /* * Back up non-volatile regs -- registers r18-r31 */ for (i = BPF_PPC_NVR_MIN; i <= 31; i++) if (bpf_is_seen_register(ctx, i)) - EMIT(PPC_RAW_STW(i, __REG_R1, bpf_jit_stack_offsetof(ctx, i))); + EMIT(PPC_RAW_STW(i, _R1, bpf_jit_stack_offsetof(ctx, i))); /* If needed retrieve arguments 9 and 10, ie 5th 64 bits arg.*/ if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_5))) { - EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5) - 1, __REG_R1, BPF_PPC_STACKFRAME(ctx)) + 8); - EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5), __REG_R1, BPF_PPC_STACKFRAME(ctx)) + 12); + EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5) - 1, _R1, BPF_PPC_STACKFRAME(ctx)) + 8); + EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5), _R1, BPF_PPC_STACKFRAME(ctx)) + 12); } /* Setup frame pointer to point to the bpf stack area */ if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_FP))) { EMIT(PPC_RAW_LI(bpf_to_ppc(ctx, BPF_REG_FP) - 1, 0)); - EMIT(PPC_RAW_ADDI(bpf_to_ppc(ctx, BPF_REG_FP), __REG_R1, + EMIT(PPC_RAW_ADDI(bpf_to_ppc(ctx, BPF_REG_FP), _R1, STACK_FRAME_MIN_SIZE + ctx->stack_size)); } if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_STW(__REG_R0, __REG_R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); + EMIT(PPC_RAW_STW(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); } static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx) @@ -163,24 +163,24 @@ static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx /* Restore NVRs */ for (i = BPF_PPC_NVR_MIN; i <= 31; i++) if (bpf_is_seen_register(ctx, i)) - EMIT(PPC_RAW_LWZ(i, __REG_R1, bpf_jit_stack_offsetof(ctx, i))); + EMIT(PPC_RAW_LWZ(i, _R1, bpf_jit_stack_offsetof(ctx, i))); } void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) { - EMIT(PPC_RAW_MR(__REG_R3, bpf_to_ppc(ctx, BPF_REG_0))); + EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(ctx, BPF_REG_0))); bpf_jit_emit_common_epilogue(image, ctx); /* Tear down our stack frame */ if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_LWZ(__REG_R0, __REG_R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); + EMIT(PPC_RAW_LWZ(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); - EMIT(PPC_RAW_ADDI(__REG_R1, __REG_R1, BPF_PPC_STACKFRAME(ctx))); + EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME(ctx))); if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_MTLR(__REG_R0)); + EMIT(PPC_RAW_MTLR(_R0)); EMIT(PPC_RAW_BLR()); } @@ -193,10 +193,10 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun PPC_BL_ABS(func); } else { /* Load function address into r0 */ - EMIT(PPC_RAW_LIS(__REG_R0, IMM_H(func))); - EMIT(PPC_RAW_ORI(__REG_R0, __REG_R0, IMM_L(func))); - EMIT(PPC_RAW_MTLR(__REG_R0)); - EMIT(PPC_RAW_BLRL()); + EMIT(PPC_RAW_LIS(_R0, IMM_H(func))); + EMIT(PPC_RAW_ORI(_R0, _R0, IMM_L(func))); + EMIT(PPC_RAW_MTCTR(_R0)); + EMIT(PPC_RAW_BCTRL()); } } @@ -215,47 +215,47 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 * if (index >= array->map.max_entries) * goto out; */ - EMIT(PPC_RAW_LWZ(__REG_R0, b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); - EMIT(PPC_RAW_CMPLW(b2p_index, __REG_R0)); - EMIT(PPC_RAW_LWZ(__REG_R0, __REG_R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); + EMIT(PPC_RAW_LWZ(_R0, b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); + EMIT(PPC_RAW_CMPLW(b2p_index, _R0)); + EMIT(PPC_RAW_LWZ(_R0, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); PPC_BCC(COND_GE, out); /* * if (tail_call_cnt > MAX_TAIL_CALL_CNT) * goto out; */ - EMIT(PPC_RAW_CMPLWI(__REG_R0, MAX_TAIL_CALL_CNT)); + EMIT(PPC_RAW_CMPLWI(_R0, MAX_TAIL_CALL_CNT)); /* tail_call_cnt++; */ - EMIT(PPC_RAW_ADDIC(__REG_R0, __REG_R0, 1)); + EMIT(PPC_RAW_ADDIC(_R0, _R0, 1)); PPC_BCC(COND_GT, out); /* prog = array->ptrs[index]; */ - EMIT(PPC_RAW_RLWINM(__REG_R3, b2p_index, 2, 0, 29)); - EMIT(PPC_RAW_ADD(__REG_R3, __REG_R3, b2p_bpf_array)); - EMIT(PPC_RAW_LWZ(__REG_R3, __REG_R3, offsetof(struct bpf_array, ptrs))); - EMIT(PPC_RAW_STW(__REG_R0, __REG_R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); + EMIT(PPC_RAW_RLWINM(_R3, b2p_index, 2, 0, 29)); + EMIT(PPC_RAW_ADD(_R3, _R3, b2p_bpf_array)); + EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_array, ptrs))); + EMIT(PPC_RAW_STW(_R0, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); /* * if (prog == NULL) * goto out; */ - EMIT(PPC_RAW_CMPLWI(__REG_R3, 0)); + EMIT(PPC_RAW_CMPLWI(_R3, 0)); PPC_BCC(COND_EQ, out); /* goto *(prog->bpf_func + prologue_size); */ - EMIT(PPC_RAW_LWZ(__REG_R3, __REG_R3, offsetof(struct bpf_prog, bpf_func))); + EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_prog, bpf_func))); if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_LWZ(__REG_R0, __REG_R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); + EMIT(PPC_RAW_LWZ(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); - EMIT(PPC_RAW_ADDIC(__REG_R3, __REG_R3, BPF_TAILCALL_PROLOGUE_SIZE)); + EMIT(PPC_RAW_ADDIC(_R3, _R3, BPF_TAILCALL_PROLOGUE_SIZE)); if (ctx->seen & SEEN_FUNC) - EMIT(PPC_RAW_MTLR(__REG_R0)); + EMIT(PPC_RAW_MTLR(_R0)); - EMIT(PPC_RAW_MTCTR(__REG_R3)); + EMIT(PPC_RAW_MTCTR(_R3)); - EMIT(PPC_RAW_MR(__REG_R3, bpf_to_ppc(ctx, BPF_REG_1))); + EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(ctx, BPF_REG_1))); /* tear restore NVRs, ... */ bpf_jit_emit_common_epilogue(image, ctx); @@ -352,8 +352,8 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * if (imm >= -32768 && imm < 32768) { EMIT(PPC_RAW_ADDIC(dst_reg, dst_reg, imm)); } else { - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, _R0)); } if (imm >= 0) EMIT(PPC_RAW_ADDZE(dst_reg_h, dst_reg_h)); @@ -362,11 +362,11 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */ bpf_set_seen_register(ctx, tmp_reg); - EMIT(PPC_RAW_MULW(__REG_R0, dst_reg, src_reg_h)); + EMIT(PPC_RAW_MULW(_R0, dst_reg, src_reg_h)); EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, src_reg)); EMIT(PPC_RAW_MULHWU(tmp_reg, dst_reg, src_reg)); EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); - EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, __REG_R0)); + EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0)); EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, tmp_reg)); break; case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */ @@ -376,8 +376,8 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * if (imm >= -32768 && imm < 32768) { EMIT(PPC_RAW_MULI(dst_reg, dst_reg, imm)); } else { - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_MULW(dst_reg, dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_MULW(dst_reg, dst_reg, _R0)); } break; case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */ @@ -398,17 +398,17 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, tmp_reg)); if (imm < 0) EMIT(PPC_RAW_SUB(dst_reg_h, dst_reg_h, dst_reg)); - EMIT(PPC_RAW_MULHWU(__REG_R0, dst_reg, tmp_reg)); + EMIT(PPC_RAW_MULHWU(_R0, dst_reg, tmp_reg)); EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp_reg)); - EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, __REG_R0)); + EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0)); break; case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */ EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg)); break; case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */ - EMIT(PPC_RAW_DIVWU(__REG_R0, dst_reg, src_reg)); - EMIT(PPC_RAW_MULW(__REG_R0, src_reg, __REG_R0)); - EMIT(PPC_RAW_SUB(dst_reg, dst_reg, __REG_R0)); + EMIT(PPC_RAW_DIVWU(_R0, dst_reg, src_reg)); + EMIT(PPC_RAW_MULW(_R0, src_reg, _R0)); + EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0)); break; case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */ return -EOPNOTSUPP; @@ -420,8 +420,8 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * if (imm == 1) break; - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, _R0)); break; case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */ if (!imm) @@ -430,9 +430,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * if (!is_power_of_2((u32)imm)) { bpf_set_seen_register(ctx, tmp_reg); PPC_LI32(tmp_reg, imm); - EMIT(PPC_RAW_DIVWU(__REG_R0, dst_reg, tmp_reg)); - EMIT(PPC_RAW_MULW(__REG_R0, tmp_reg, __REG_R0)); - EMIT(PPC_RAW_SUB(dst_reg, dst_reg, __REG_R0)); + EMIT(PPC_RAW_DIVWU(_R0, dst_reg, tmp_reg)); + EMIT(PPC_RAW_MULW(_R0, tmp_reg, _R0)); + EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0)); break; } if (imm == 1) @@ -503,8 +503,8 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - fls(imm), 32 - ffs(imm))); } else { - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_AND(dst_reg, dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_AND(dst_reg, dst_reg, _R0)); } break; case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ @@ -555,12 +555,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */ bpf_set_seen_register(ctx, tmp_reg); - EMIT(PPC_RAW_SUBFIC(__REG_R0, src_reg, 32)); + EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); EMIT(PPC_RAW_SLW(dst_reg_h, dst_reg_h, src_reg)); EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); - EMIT(PPC_RAW_SRW(__REG_R0, dst_reg, __REG_R0)); + EMIT(PPC_RAW_SRW(_R0, dst_reg, _R0)); EMIT(PPC_RAW_SLW(tmp_reg, dst_reg, tmp_reg)); - EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, __REG_R0)); + EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, _R0)); EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, tmp_reg)); break; @@ -591,12 +591,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */ bpf_set_seen_register(ctx, tmp_reg); - EMIT(PPC_RAW_SUBFIC(__REG_R0, src_reg, 32)); + EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); - EMIT(PPC_RAW_SLW(__REG_R0, dst_reg_h, __REG_R0)); + EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0)); EMIT(PPC_RAW_SRW(tmp_reg, dst_reg_h, tmp_reg)); - EMIT(PPC_RAW_OR(dst_reg, dst_reg, __REG_R0)); + EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0)); EMIT(PPC_RAW_SRW(dst_reg_h, dst_reg_h, src_reg)); EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg)); break; @@ -627,15 +627,15 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ bpf_set_seen_register(ctx, tmp_reg); - EMIT(PPC_RAW_SUBFIC(__REG_R0, src_reg, 32)); + EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); - EMIT(PPC_RAW_SLW(__REG_R0, dst_reg_h, __REG_R0)); + EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0)); EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); - EMIT(PPC_RAW_OR(dst_reg, dst_reg, __REG_R0)); - EMIT(PPC_RAW_RLWINM(__REG_R0, tmp_reg, 0, 26, 26)); + EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0)); + EMIT(PPC_RAW_RLWINM(_R0, tmp_reg, 0, 26, 26)); EMIT(PPC_RAW_SRAW(tmp_reg, dst_reg_h, tmp_reg)); EMIT(PPC_RAW_SRAW(dst_reg_h, dst_reg_h, src_reg)); - EMIT(PPC_RAW_SLW(tmp_reg, tmp_reg, __REG_R0)); + EMIT(PPC_RAW_SLW(tmp_reg, tmp_reg, _R0)); EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg)); break; case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ @@ -702,24 +702,24 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * * 2 bytes are already in their final position * -- byte 2 and 4 (of bytes 1, 2, 3 and 4) */ - EMIT(PPC_RAW_RLWINM(__REG_R0, dst_reg, 8, 0, 31)); + EMIT(PPC_RAW_RLWINM(_R0, dst_reg, 8, 0, 31)); /* Rotate 24 bits and insert byte 1 */ - EMIT(PPC_RAW_RLWIMI(__REG_R0, dst_reg, 24, 0, 7)); + EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 0, 7)); /* Rotate 24 bits and insert byte 3 */ - EMIT(PPC_RAW_RLWIMI(__REG_R0, dst_reg, 24, 16, 23)); - EMIT(PPC_RAW_MR(dst_reg, __REG_R0)); + EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 16, 23)); + EMIT(PPC_RAW_MR(dst_reg, _R0)); break; case 64: bpf_set_seen_register(ctx, tmp_reg); EMIT(PPC_RAW_RLWINM(tmp_reg, dst_reg, 8, 0, 31)); - EMIT(PPC_RAW_RLWINM(__REG_R0, dst_reg_h, 8, 0, 31)); + EMIT(PPC_RAW_RLWINM(_R0, dst_reg_h, 8, 0, 31)); /* Rotate 24 bits and insert byte 1 */ EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 0, 7)); - EMIT(PPC_RAW_RLWIMI(__REG_R0, dst_reg_h, 24, 0, 7)); + EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 0, 7)); /* Rotate 24 bits and insert byte 3 */ EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 16, 23)); - EMIT(PPC_RAW_RLWIMI(__REG_R0, dst_reg_h, 24, 16, 23)); - EMIT(PPC_RAW_MR(dst_reg, __REG_R0)); + EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 16, 23)); + EMIT(PPC_RAW_MR(dst_reg, _R0)); EMIT(PPC_RAW_MR(dst_reg_h, tmp_reg)); break; } @@ -744,32 +744,32 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); break; case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_STB(__REG_R0, dst_reg, off)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_STB(_R0, dst_reg, off)); break; case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); break; case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_STH(__REG_R0, dst_reg, off)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_STH(_R0, dst_reg, off)); break; case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); break; case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_STW(__REG_R0, dst_reg, off)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_STW(_R0, dst_reg, off)); break; case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ EMIT(PPC_RAW_STW(src_reg_h, dst_reg, off)); EMIT(PPC_RAW_STW(src_reg, dst_reg, off + 4)); break; case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_STW(__REG_R0, dst_reg, off + 4)); - PPC_EX32(__REG_R0, imm); - EMIT(PPC_RAW_STW(__REG_R0, dst_reg, off)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_STW(_R0, dst_reg, off + 4)); + PPC_EX32(_R0, imm); + EMIT(PPC_RAW_STW(_R0, dst_reg, off)); break; /* @@ -780,11 +780,11 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * /* Get offset into TMP_REG */ EMIT(PPC_RAW_LI(tmp_reg, off)); /* load value from memory into r0 */ - EMIT(PPC_RAW_LWARX(__REG_R0, tmp_reg, dst_reg, 0)); + EMIT(PPC_RAW_LWARX(_R0, tmp_reg, dst_reg, 0)); /* add value from src_reg into this */ - EMIT(PPC_RAW_ADD(__REG_R0, __REG_R0, src_reg)); + EMIT(PPC_RAW_ADD(_R0, _R0, src_reg)); /* store result back */ - EMIT(PPC_RAW_STWCX(__REG_R0, tmp_reg, dst_reg)); + EMIT(PPC_RAW_STWCX(_R0, tmp_reg, dst_reg)); /* we're done if this succeeded */ PPC_BCC_SHORT(COND_NE, (ctx->idx - 3) * 4); break; @@ -852,14 +852,14 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * return ret; if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_5))) { - EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5) - 1, __REG_R1, 8)); - EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5), __REG_R1, 12)); + EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5) - 1, _R1, 8)); + EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5), _R1, 12)); } bpf_jit_emit_func_call_rel(image, ctx, func_addr); - EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0) - 1, __REG_R3)); - EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0), __REG_R4)); + EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0) - 1, _R3)); + EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0), _R4)); break; /* @@ -967,12 +967,12 @@ cond_branch: EMIT(PPC_RAW_CMPW(dst_reg, src_reg)); break; case BPF_JMP | BPF_JSET | BPF_X: - EMIT(PPC_RAW_AND_DOT(__REG_R0, dst_reg_h, src_reg_h)); + EMIT(PPC_RAW_AND_DOT(_R0, dst_reg_h, src_reg_h)); PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); - EMIT(PPC_RAW_AND_DOT(__REG_R0, dst_reg, src_reg)); + EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg)); break; case BPF_JMP32 | BPF_JSET | BPF_X: { - EMIT(PPC_RAW_AND_DOT(__REG_R0, dst_reg, src_reg)); + EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg)); break; case BPF_JMP | BPF_JNE | BPF_K: case BPF_JMP | BPF_JEQ | BPF_K: @@ -990,11 +990,11 @@ cond_branch: EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); } else { /* sign-extending load ... but unsigned comparison */ - PPC_EX32(__REG_R0, imm); - EMIT(PPC_RAW_CMPLW(dst_reg_h, __REG_R0)); - PPC_LI32(__REG_R0, imm); + PPC_EX32(_R0, imm); + EMIT(PPC_RAW_CMPLW(dst_reg_h, _R0)); + PPC_LI32(_R0, imm); PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); - EMIT(PPC_RAW_CMPLW(dst_reg, __REG_R0)); + EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); } break; case BPF_JMP32 | BPF_JNE | BPF_K: @@ -1006,8 +1006,8 @@ cond_branch: if (imm >= 0 && imm < 65536) { EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); } else { - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_CMPLW(dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); } break; } @@ -1022,9 +1022,9 @@ cond_branch: } else { /* sign-extending load */ EMIT(PPC_RAW_CMPWI(dst_reg_h, imm < 0 ? -1 : 0)); - PPC_LI32(__REG_R0, imm); + PPC_LI32(_R0, imm); PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); - EMIT(PPC_RAW_CMPLW(dst_reg, __REG_R0)); + EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); } break; case BPF_JMP32 | BPF_JSGT | BPF_K: @@ -1039,32 +1039,32 @@ cond_branch: EMIT(PPC_RAW_CMPWI(dst_reg, imm)); } else { /* sign-extending load */ - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_CMPW(dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_CMPW(dst_reg, _R0)); } break; case BPF_JMP | BPF_JSET | BPF_K: /* andi does not sign-extend the immediate */ if (imm >= 0 && imm < 32768) { /* PPC_ANDI is _only/always_ dot-form */ - EMIT(PPC_RAW_ANDI(__REG_R0, dst_reg, imm)); + EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm)); } else { - PPC_LI32(__REG_R0, imm); + PPC_LI32(_R0, imm); if (imm < 0) { EMIT(PPC_RAW_CMPWI(dst_reg_h, 0)); PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); } - EMIT(PPC_RAW_AND_DOT(__REG_R0, dst_reg, __REG_R0)); + EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0)); } break; case BPF_JMP32 | BPF_JSET | BPF_K: /* andi does not sign-extend the immediate */ if (imm >= -32768 && imm < 32768) { /* PPC_ANDI is _only/always_ dot-form */ - EMIT(PPC_RAW_ANDI(__REG_R0, dst_reg, imm)); + EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm)); } else { - PPC_LI32(__REG_R0, imm); - EMIT(PPC_RAW_AND_DOT(__REG_R0, dst_reg, __REG_R0)); + PPC_LI32(_R0, imm); + EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0)); } break; } diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index 57a8c1153851..5cad5b5a7e97 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -94,7 +94,7 @@ void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) * save/restore LR unless we call other functions */ if (ctx->seen & SEEN_FUNC) { - EMIT(PPC_INST_MFLR | __PPC_RT(R0)); + EMIT(PPC_RAW_MFLR(_R0)); PPC_BPF_STL(0, 1, PPC_LR_STKOFF); } @@ -153,8 +153,8 @@ static void bpf_jit_emit_func_call_hlp(u32 *image, struct codegen_context *ctx, PPC_LI64(b2p[TMP_REG_2], func); /* Load actual entry point from function descriptor */ PPC_BPF_LL(b2p[TMP_REG_1], b2p[TMP_REG_2], 0); - /* ... and move it to LR */ - EMIT(PPC_RAW_MTLR(b2p[TMP_REG_1])); + /* ... and move it to CTR */ + EMIT(PPC_RAW_MTCTR(b2p[TMP_REG_1])); /* * Load TOC from function descriptor at offset 8. * We can clobber r2 since we get called through a @@ -165,9 +165,9 @@ static void bpf_jit_emit_func_call_hlp(u32 *image, struct codegen_context *ctx, #else /* We can clobber r12 */ PPC_FUNC_ADDR(12, func); - EMIT(PPC_RAW_MTLR(12)); + EMIT(PPC_RAW_MTCTR(12)); #endif - EMIT(PPC_RAW_BLRL()); + EMIT(PPC_RAW_BCTRL()); } void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func) @@ -202,8 +202,8 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun PPC_BPF_LL(12, 12, 0); #endif - EMIT(PPC_RAW_MTLR(12)); - EMIT(PPC_RAW_BLRL()); + EMIT(PPC_RAW_MTCTR(12)); + EMIT(PPC_RAW_BCTRL()); } static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out) diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index c02854dea2b2..2f46e31c7612 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -1,9 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PERF_EVENTS) += callchain.o callchain_$(BITS).o perf_regs.o -ifdef CONFIG_COMPAT -obj-$(CONFIG_PERF_EVENTS) += callchain_32.o -endif +obj-y += callchain.o callchain_$(BITS).o perf_regs.o +obj-$(CONFIG_COMPAT) += callchain_32.o obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o bhrb.o obj64-$(CONFIG_PPC_PERF_CTRS) += ppc970-pmu.o power5-pmu.o \ diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c index 6c028ee513c0..082f6d0308a4 100644 --- a/arch/powerpc/perf/callchain.c +++ b/arch/powerpc/perf/callchain.c @@ -40,7 +40,7 @@ static int valid_next_sp(unsigned long sp, unsigned long prev_sp) return 0; } -void +void __no_sanitize_address perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { unsigned long sp, next_sp; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 51622411a7cc..bb0ee716de91 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -460,7 +460,7 @@ static __u64 power_pmu_bhrb_to(u64 addr) sizeof(instr))) return 0; - return branch_target((struct ppc_inst *)&instr); + return branch_target(&instr); } /* Userspace: need copy instruction here then translate it */ @@ -468,7 +468,7 @@ static __u64 power_pmu_bhrb_to(u64 addr) sizeof(instr))) return 0; - target = branch_target((struct ppc_inst *)&instr); + target = branch_target(&instr); if ((!target) || (instr & BRANCH_ABSOLUTE)) return target; diff --git a/arch/powerpc/perf/generic-compat-pmu.c b/arch/powerpc/perf/generic-compat-pmu.c index eb8a6aaf4cc1..695975227e60 100644 --- a/arch/powerpc/perf/generic-compat-pmu.c +++ b/arch/powerpc/perf/generic-compat-pmu.c @@ -14,45 +14,119 @@ * * 28 24 20 16 12 8 4 0 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - * [ pmc ] [unit ] [ ] m [ pmcxsel ] - * | | - * | *- mark - * | - * | - * *- combine - * - * Below uses IBM bit numbering. - * - * MMCR1[x:y] = unit (PMCxUNIT) - * MMCR1[24] = pmc1combine[0] - * MMCR1[25] = pmc1combine[1] - * MMCR1[26] = pmc2combine[0] - * MMCR1[27] = pmc2combine[1] - * MMCR1[28] = pmc3combine[0] - * MMCR1[29] = pmc3combine[1] - * MMCR1[30] = pmc4combine[0] - * MMCR1[31] = pmc4combine[1] - * + * [ pmc ] [ pmcxsel ] */ /* - * Some power9 event codes. + * Event codes defined in ISA v3.0B */ #define EVENT(_name, _code) _name = _code, enum { -EVENT(PM_CYC, 0x0001e) -EVENT(PM_INST_CMPL, 0x00002) + /* Cycles, alternate code */ + EVENT(PM_CYC_ALT, 0x100f0) + /* One or more instructions completed in a cycle */ + EVENT(PM_CYC_INST_CMPL, 0x100f2) + /* Floating-point instruction completed */ + EVENT(PM_FLOP_CMPL, 0x100f4) + /* Instruction ERAT/L1-TLB miss */ + EVENT(PM_L1_ITLB_MISS, 0x100f6) + /* All instructions completed and none available */ + EVENT(PM_NO_INST_AVAIL, 0x100f8) + /* A load-type instruction completed (ISA v3.0+) */ + EVENT(PM_LD_CMPL, 0x100fc) + /* Instruction completed, alternate code (ISA v3.0+) */ + EVENT(PM_INST_CMPL_ALT, 0x100fe) + /* A store-type instruction completed */ + EVENT(PM_ST_CMPL, 0x200f0) + /* Instruction Dispatched */ + EVENT(PM_INST_DISP, 0x200f2) + /* Run_cycles */ + EVENT(PM_RUN_CYC, 0x200f4) + /* Data ERAT/L1-TLB miss/reload */ + EVENT(PM_L1_DTLB_RELOAD, 0x200f6) + /* Taken branch completed */ + EVENT(PM_BR_TAKEN_CMPL, 0x200fa) + /* Demand iCache Miss */ + EVENT(PM_L1_ICACHE_MISS, 0x200fc) + /* L1 Dcache reload from memory */ + EVENT(PM_L1_RELOAD_FROM_MEM, 0x200fe) + /* L1 Dcache store miss */ + EVENT(PM_ST_MISS_L1, 0x300f0) + /* Alternate code for PM_INST_DISP */ + EVENT(PM_INST_DISP_ALT, 0x300f2) + /* Branch direction or target mispredicted */ + EVENT(PM_BR_MISPREDICT, 0x300f6) + /* Data TLB miss/reload */ + EVENT(PM_DTLB_MISS, 0x300fc) + /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ + EVENT(PM_DATA_FROM_L3MISS, 0x300fe) + /* L1 Dcache load miss */ + EVENT(PM_LD_MISS_L1, 0x400f0) + /* Cycle when instruction(s) dispatched */ + EVENT(PM_CYC_INST_DISP, 0x400f2) + /* Branch or branch target mispredicted */ + EVENT(PM_BR_MPRED_CMPL, 0x400f6) + /* Instructions completed with run latch set */ + EVENT(PM_RUN_INST_CMPL, 0x400fa) + /* Instruction TLB miss/reload */ + EVENT(PM_ITLB_MISS, 0x400fc) + /* Load data not cached */ + EVENT(PM_LD_NOT_CACHED, 0x400fe) + /* Instructions */ + EVENT(PM_INST_CMPL, 0x500fa) + /* Cycles */ + EVENT(PM_CYC, 0x600f4) }; #undef EVENT +/* Table of alternatives, sorted in increasing order of column 0 */ +/* Note that in each row, column 0 must be the smallest */ +static const unsigned int generic_event_alternatives[][MAX_ALT] = { + { PM_CYC_ALT, PM_CYC }, + { PM_INST_CMPL_ALT, PM_INST_CMPL }, + { PM_INST_DISP, PM_INST_DISP_ALT }, +}; + +static int generic_get_alternatives(u64 event, unsigned int flags, u64 alt[]) +{ + int num_alt = 0; + + num_alt = isa207_get_alternatives(event, alt, + ARRAY_SIZE(generic_event_alternatives), flags, + generic_event_alternatives); + + return num_alt; +} + GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); +GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_NO_INST_AVAIL); +GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); +GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); + +CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); +CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); +CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); +CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); +CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); +CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); +CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); static struct attribute *generic_compat_events_attr[] = { GENERIC_EVENT_PTR(PM_CYC), GENERIC_EVENT_PTR(PM_INST_CMPL), + GENERIC_EVENT_PTR(PM_NO_INST_AVAIL), + GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), + GENERIC_EVENT_PTR(PM_LD_MISS_L1), + CACHE_EVENT_PTR(PM_LD_MISS_L1), + CACHE_EVENT_PTR(PM_ST_MISS_L1), + CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), + CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), + CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), + CACHE_EVENT_PTR(PM_DTLB_MISS), + CACHE_EVENT_PTR(PM_ITLB_MISS), NULL }; @@ -63,17 +137,11 @@ static struct attribute_group generic_compat_pmu_events_group = { PMU_FORMAT_ATTR(event, "config:0-19"); PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); -PMU_FORMAT_ATTR(mark, "config:8"); -PMU_FORMAT_ATTR(combine, "config:10-11"); -PMU_FORMAT_ATTR(unit, "config:12-15"); PMU_FORMAT_ATTR(pmc, "config:16-19"); static struct attribute *generic_compat_pmu_format_attr[] = { &format_attr_event.attr, &format_attr_pmcxsel.attr, - &format_attr_mark.attr, - &format_attr_combine.attr, - &format_attr_unit.attr, &format_attr_pmc.attr, NULL, }; @@ -92,6 +160,9 @@ static const struct attribute_group *generic_compat_pmu_attr_groups[] = { static int compat_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_NO_INST_AVAIL, + [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, + [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, }; #define C(x) PERF_COUNT_HW_CACHE_##x @@ -105,11 +176,11 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(L1D) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_LD_MISS_L1, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_ST_MISS_L1, }, [ C(OP_PREFETCH) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -119,7 +190,7 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(L1I) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -133,7 +204,7 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(LL) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -147,7 +218,7 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(DTLB) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_DTLB_MISS, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = -1, @@ -161,7 +232,7 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(ITLB) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_ITLB_MISS, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = -1, @@ -175,7 +246,7 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [ C(BPU) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = -1, @@ -204,13 +275,30 @@ static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { #undef C +/* + * We set MMCR0[CC5-6RUN] so we can use counters 5 and 6 for + * PM_INST_CMPL and PM_CYC. + */ +static int generic_compute_mmcr(u64 event[], int n_ev, + unsigned int hwc[], struct mmcr_regs *mmcr, + struct perf_event *pevents[], u32 flags) +{ + int ret; + + ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags); + if (!ret) + mmcr->mmcr0 |= MMCR0_C56RUN; + return ret; +} + static struct power_pmu generic_compat_pmu = { .name = "GENERIC_COMPAT", .n_counter = MAX_PMU_COUNTERS, .add_fields = ISA207_ADD_FIELDS, .test_adder = ISA207_TEST_ADDER, - .compute_mmcr = isa207_compute_mmcr, + .compute_mmcr = generic_compute_mmcr, .get_constraint = isa207_get_constraint, + .get_alternatives = generic_get_alternatives, .disable_pmc = isa207_disable_pmc, .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, .n_generic = ARRAY_SIZE(compat_generic_events), @@ -223,6 +311,16 @@ int init_generic_compat_pmu(void) { int rc = 0; + /* + * From ISA v2.07 on, PMU features are architected; + * we require >= v3.0 because (a) that has PM_LD_CMPL and + * PM_INST_CMPL_ALT, which v2.07 doesn't have, and + * (b) we don't expect any non-IBM Power ISA + * implementations that conform to v2.07 but not v3.0. + */ + if (!cpu_has_feature(CPU_FTR_ARCH_300)) + return -ENODEV; + rc = register_power_pmu(&generic_compat_pmu); if (rc) return rc; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 8c0d324f657e..3823df235f25 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -582,6 +582,7 @@ static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd, if (ret) break; /* fall through and return the timeout */ + fallthrough; case WDIOC_GETTIMEOUT: /* we need to round here as to avoid e.g. the following diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c index 87f524e4b09c..8a7e55acf090 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c @@ -73,7 +73,7 @@ smp_86xx_kick_cpu(int nr) /* Setup fake reset vector to call __secondary_start_mpc86xx. */ target = (unsigned long) __secondary_start_mpc86xx; - patch_branch((struct ppc_inst *)vector, target, BRANCH_SET_LINK); + patch_branch(vector, target, BRANCH_SET_LINK); /* Kick that CPU */ smp_86xx_release_core(nr); @@ -83,7 +83,7 @@ smp_86xx_kick_cpu(int nr) mdelay(1); /* Restore the exception vector */ - patch_instruction((struct ppc_inst *)vector, ppc_inst(save_vector)); + patch_instruction(vector, ppc_inst(save_vector)); local_irq_restore(flags); diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index 7a5e8f4541e3..e02d29a9d12f 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -20,6 +20,8 @@ source "arch/powerpc/platforms/embedded6xx/Kconfig" source "arch/powerpc/platforms/44x/Kconfig" source "arch/powerpc/platforms/40x/Kconfig" source "arch/powerpc/platforms/amigaone/Kconfig" +source "arch/powerpc/platforms/book3s/Kconfig" +source "arch/powerpc/platforms/microwatt/Kconfig" config KVM_GUEST bool "KVM Guest support" @@ -49,6 +51,7 @@ config PPC_NATIVE config PPC_OF_BOOT_TRAMPOLINE bool "Support booting from Open Firmware or yaboot" depends on PPC_BOOK3S_32 || PPC64 + select RELOCATABLE if PPC64 default y help Support from booting from Open Firmware or yaboot using an diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index f998e655b570..0e1bb1cedd13 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -61,6 +61,7 @@ config 44x select 4xx_SOC select HAVE_PCI select PHYS_64BIT + select PPC_HAVE_KUEP endchoice @@ -111,6 +112,7 @@ config PPC_BOOK3E_64 select PPC_FPU # Make it a choice ? select PPC_SMP_MUXED_IPI select PPC_DOORBELL + select ZONE_DMA endchoice @@ -389,7 +391,7 @@ config PPC_HAVE_KUEP config PPC_KUEP bool "Kernel Userspace Execution Prevention" depends on PPC_HAVE_KUEP - default y if !PPC_BOOK3S_32 + default y help Enable support for Kernel Userspace Execution Prevention (KUEP) @@ -401,7 +403,7 @@ config PPC_HAVE_KUAP config PPC_KUAP bool "Kernel Userspace Access Protection" depends on PPC_HAVE_KUAP - default y if !PPC_BOOK3S_32 + default y help Enable support for Kernel Userspace Access Protection (KUAP) @@ -424,10 +426,6 @@ config PPC_MMU_NOHASH def_bool y depends on !PPC_BOOK3S -config PPC_MMU_NOHASH_32 - def_bool y - depends on PPC_MMU_NOHASH && PPC32 - config PPC_BOOK3E_MMU def_bool y depends on FSL_BOOKE || PPC_BOOK3E @@ -476,9 +474,9 @@ config SMP If you don't know what to do here, say N. config NR_CPUS - int "Maximum number of CPUs (2-8192)" - range 2 8192 - depends on SMP + int "Maximum number of CPUs (2-8192)" if SMP + range 2 8192 if SMP + default "1" if !SMP default "32" if PPC64 default "4" diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile index 143d4417f6cc..94470fb27c99 100644 --- a/arch/powerpc/platforms/Makefile +++ b/arch/powerpc/platforms/Makefile @@ -22,3 +22,5 @@ obj-$(CONFIG_PPC_CELL) += cell/ obj-$(CONFIG_PPC_PS3) += ps3/ obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/ obj-$(CONFIG_AMIGAONE) += amigaone/ +obj-$(CONFIG_PPC_BOOK3S) += book3s/ +obj-$(CONFIG_PPC_MICROWATT) += microwatt/ diff --git a/arch/powerpc/platforms/book3s/Kconfig b/arch/powerpc/platforms/book3s/Kconfig new file mode 100644 index 000000000000..34c931592ef0 --- /dev/null +++ b/arch/powerpc/platforms/book3s/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +config PPC_VAS + bool "IBM Virtual Accelerator Switchboard (VAS)" + depends on (PPC_POWERNV || PPC_PSERIES) && PPC_64K_PAGES + default y + help + This enables support for IBM Virtual Accelerator Switchboard (VAS). + + VAS devices are found in POWER9-based and later systems, they + provide access to accelerator coprocessors such as NX-GZIP and + NX-842. This config allows the kernel to use NX-842 accelerators, + and user-mode APIs for the NX-GZIP accelerator on POWER9 PowerNV + and POWER10 PowerVM platforms. + + If unsure, say "N". diff --git a/arch/powerpc/platforms/book3s/Makefile b/arch/powerpc/platforms/book3s/Makefile new file mode 100644 index 000000000000..e790f1910f61 --- /dev/null +++ b/arch/powerpc/platforms/book3s/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PPC_VAS) += vas-api.o diff --git a/arch/powerpc/platforms/book3s/vas-api.c b/arch/powerpc/platforms/book3s/vas-api.c new file mode 100644 index 000000000000..30172e52e16b --- /dev/null +++ b/arch/powerpc/platforms/book3s/vas-api.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * VAS user space API for its accelerators (Only NX-GZIP is supported now) + * Copyright (C) 2019 Haren Myneni, IBM Corp + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The driver creates the device node that can be used as follows: + * For NX-GZIP + * + * fd = open("/dev/crypto/nx-gzip", O_RDWR); + * rc = ioctl(fd, VAS_TX_WIN_OPEN, &attr); + * paste_addr = mmap(NULL, PAGE_SIZE, prot, MAP_SHARED, fd, 0ULL). + * vas_copy(&crb, 0, 1); + * vas_paste(paste_addr, 0, 1); + * close(fd) or exit process to close window. + * + * where "vas_copy" and "vas_paste" are defined in copy-paste.h. + * copy/paste returns to the user space directly. So refer NX hardware + * documententation for exact copy/paste usage and completion / error + * conditions. + */ + +/* + * Wrapper object for the nx-gzip device - there is just one instance of + * this node for the whole system. + */ +static struct coproc_dev { + struct cdev cdev; + struct device *device; + char *name; + dev_t devt; + struct class *class; + enum vas_cop_type cop_type; + const struct vas_user_win_ops *vops; +} coproc_device; + +struct coproc_instance { + struct coproc_dev *coproc; + struct vas_window *txwin; +}; + +static char *coproc_devnode(struct device *dev, umode_t *mode) +{ + return kasprintf(GFP_KERNEL, "crypto/%s", dev_name(dev)); +} + +/* + * Take reference to pid and mm + */ +int get_vas_user_win_ref(struct vas_user_win_ref *task_ref) +{ + /* + * Window opened by a child thread may not be closed when + * it exits. So take reference to its pid and release it + * when the window is free by parent thread. + * Acquire a reference to the task's pid to make sure + * pid will not be re-used - needed only for multithread + * applications. + */ + task_ref->pid = get_task_pid(current, PIDTYPE_PID); + /* + * Acquire a reference to the task's mm. + */ + task_ref->mm = get_task_mm(current); + if (!task_ref->mm) { + put_pid(task_ref->pid); + pr_err("VAS: pid(%d): mm_struct is not found\n", + current->pid); + return -EPERM; + } + + mmgrab(task_ref->mm); + mmput(task_ref->mm); + /* + * Process closes window during exit. In the case of + * multithread application, the child thread can open + * window and can exit without closing it. So takes tgid + * reference until window closed to make sure tgid is not + * reused. + */ + task_ref->tgid = find_get_pid(task_tgid_vnr(current)); + + return 0; +} + +/* + * Successful return must release the task reference with + * put_task_struct + */ +static bool ref_get_pid_and_task(struct vas_user_win_ref *task_ref, + struct task_struct **tskp, struct pid **pidp) +{ + struct task_struct *tsk; + struct pid *pid; + + pid = task_ref->pid; + tsk = get_pid_task(pid, PIDTYPE_PID); + if (!tsk) { + pid = task_ref->tgid; + tsk = get_pid_task(pid, PIDTYPE_PID); + /* + * Parent thread (tgid) will be closing window when it + * exits. So should not get here. + */ + if (WARN_ON_ONCE(!tsk)) + return false; + } + + /* Return if the task is exiting. */ + if (tsk->flags & PF_EXITING) { + put_task_struct(tsk); + return false; + } + + *tskp = tsk; + *pidp = pid; + + return true; +} + +/* + * Update the CSB to indicate a translation error. + * + * User space will be polling on CSB after the request is issued. + * If NX can handle the request without any issues, it updates CSB. + * Whereas if NX encounters page fault, the kernel will handle the + * fault and update CSB with translation error. + * + * If we are unable to update the CSB means copy_to_user failed due to + * invalid csb_addr, send a signal to the process. + */ +void vas_update_csb(struct coprocessor_request_block *crb, + struct vas_user_win_ref *task_ref) +{ + struct coprocessor_status_block csb; + struct kernel_siginfo info; + struct task_struct *tsk; + void __user *csb_addr; + struct pid *pid; + int rc; + + /* + * NX user space windows can not be opened for task->mm=NULL + * and faults will not be generated for kernel requests. + */ + if (WARN_ON_ONCE(!task_ref->mm)) + return; + + csb_addr = (void __user *)be64_to_cpu(crb->csb_addr); + + memset(&csb, 0, sizeof(csb)); + csb.cc = CSB_CC_FAULT_ADDRESS; + csb.ce = CSB_CE_TERMINATION; + csb.cs = 0; + csb.count = 0; + + /* + * NX operates and returns in BE format as defined CRB struct. + * So saves fault_storage_addr in BE as NX pastes in FIFO and + * expects user space to convert to CPU format. + */ + csb.address = crb->stamp.nx.fault_storage_addr; + csb.flags = 0; + + /* + * Process closes send window after all pending NX requests are + * completed. In multi-thread applications, a child thread can + * open a window and can exit without closing it. May be some + * requests are pending or this window can be used by other + * threads later. We should handle faults if NX encounters + * pages faults on these requests. Update CSB with translation + * error and fault address. If csb_addr passed by user space is + * invalid, send SEGV signal to pid saved in window. If the + * child thread is not running, send the signal to tgid. + * Parent thread (tgid) will close this window upon its exit. + * + * pid and mm references are taken when window is opened by + * process (pid). So tgid is used only when child thread opens + * a window and exits without closing it. + */ + + if (!ref_get_pid_and_task(task_ref, &tsk, &pid)) + return; + + kthread_use_mm(task_ref->mm); + rc = copy_to_user(csb_addr, &csb, sizeof(csb)); + /* + * User space polls on csb.flags (first byte). So add barrier + * then copy first byte with csb flags update. + */ + if (!rc) { + csb.flags = CSB_V; + /* Make sure update to csb.flags is visible now */ + smp_mb(); + rc = copy_to_user(csb_addr, &csb, sizeof(u8)); + } + kthread_unuse_mm(task_ref->mm); + put_task_struct(tsk); + + /* Success */ + if (!rc) + return; + + + pr_debug("Invalid CSB address 0x%p signalling pid(%d)\n", + csb_addr, pid_vnr(pid)); + + clear_siginfo(&info); + info.si_signo = SIGSEGV; + info.si_errno = EFAULT; + info.si_code = SEGV_MAPERR; + info.si_addr = csb_addr; + /* + * process will be polling on csb.flags after request is sent to + * NX. So generally CSB update should not fail except when an + * application passes invalid csb_addr. So an error message will + * be displayed and leave it to user space whether to ignore or + * handle this signal. + */ + rcu_read_lock(); + rc = kill_pid_info(SIGSEGV, &info, pid); + rcu_read_unlock(); + + pr_devel("%s(): pid %d kill_proc_info() rc %d\n", __func__, + pid_vnr(pid), rc); +} + +void vas_dump_crb(struct coprocessor_request_block *crb) +{ + struct data_descriptor_entry *dde; + struct nx_fault_stamp *nx; + + dde = &crb->source; + pr_devel("SrcDDE: addr 0x%llx, len %d, count %d, idx %d, flags %d\n", + be64_to_cpu(dde->address), be32_to_cpu(dde->length), + dde->count, dde->index, dde->flags); + + dde = &crb->target; + pr_devel("TgtDDE: addr 0x%llx, len %d, count %d, idx %d, flags %d\n", + be64_to_cpu(dde->address), be32_to_cpu(dde->length), + dde->count, dde->index, dde->flags); + + nx = &crb->stamp.nx; + pr_devel("NX Stamp: PSWID 0x%x, FSA 0x%llx, flags 0x%x, FS 0x%x\n", + be32_to_cpu(nx->pswid), + be64_to_cpu(crb->stamp.nx.fault_storage_addr), + nx->flags, nx->fault_status); +} + +static int coproc_open(struct inode *inode, struct file *fp) +{ + struct coproc_instance *cp_inst; + + cp_inst = kzalloc(sizeof(*cp_inst), GFP_KERNEL); + if (!cp_inst) + return -ENOMEM; + + cp_inst->coproc = container_of(inode->i_cdev, struct coproc_dev, + cdev); + fp->private_data = cp_inst; + + return 0; +} + +static int coproc_ioc_tx_win_open(struct file *fp, unsigned long arg) +{ + void __user *uptr = (void __user *)arg; + struct vas_tx_win_open_attr uattr; + struct coproc_instance *cp_inst; + struct vas_window *txwin; + int rc; + + cp_inst = fp->private_data; + + /* + * One window for file descriptor + */ + if (cp_inst->txwin) + return -EEXIST; + + rc = copy_from_user(&uattr, uptr, sizeof(uattr)); + if (rc) { + pr_err("%s(): copy_from_user() returns %d\n", __func__, rc); + return -EFAULT; + } + + if (uattr.version != 1) { + pr_err("Invalid window open API version\n"); + return -EINVAL; + } + + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops->open_win) { + pr_err("VAS API is not registered\n"); + return -EACCES; + } + + txwin = cp_inst->coproc->vops->open_win(uattr.vas_id, uattr.flags, + cp_inst->coproc->cop_type); + if (IS_ERR(txwin)) { + pr_err("%s() VAS window open failed, %ld\n", __func__, + PTR_ERR(txwin)); + return PTR_ERR(txwin); + } + + cp_inst->txwin = txwin; + + return 0; +} + +static int coproc_release(struct inode *inode, struct file *fp) +{ + struct coproc_instance *cp_inst = fp->private_data; + int rc; + + if (cp_inst->txwin) { + if (cp_inst->coproc->vops && + cp_inst->coproc->vops->close_win) { + rc = cp_inst->coproc->vops->close_win(cp_inst->txwin); + if (rc) + return rc; + } + cp_inst->txwin = NULL; + } + + kfree(cp_inst); + fp->private_data = NULL; + + /* + * We don't know here if user has other receive windows + * open, so we can't really call clear_thread_tidr(). + * So, once the process calls set_thread_tidr(), the + * TIDR value sticks around until process exits, resulting + * in an extra copy in restore_sprs(). + */ + + return 0; +} + +static int coproc_mmap(struct file *fp, struct vm_area_struct *vma) +{ + struct coproc_instance *cp_inst = fp->private_data; + struct vas_window *txwin; + unsigned long pfn; + u64 paste_addr; + pgprot_t prot; + int rc; + + txwin = cp_inst->txwin; + + if ((vma->vm_end - vma->vm_start) > PAGE_SIZE) { + pr_debug("%s(): size 0x%zx, PAGE_SIZE 0x%zx\n", __func__, + (vma->vm_end - vma->vm_start), PAGE_SIZE); + return -EINVAL; + } + + /* Ensure instance has an open send window */ + if (!txwin) { + pr_err("%s(): No send window open?\n", __func__); + return -EINVAL; + } + + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops->paste_addr) { + pr_err("%s(): VAS API is not registered\n", __func__); + return -EACCES; + } + + paste_addr = cp_inst->coproc->vops->paste_addr(txwin); + if (!paste_addr) { + pr_err("%s(): Window paste address failed\n", __func__); + return -EINVAL; + } + + pfn = paste_addr >> PAGE_SHIFT; + + /* flags, page_prot from cxl_mmap(), except we want cachable */ + vma->vm_flags |= VM_IO | VM_PFNMAP; + vma->vm_page_prot = pgprot_cached(vma->vm_page_prot); + + prot = __pgprot(pgprot_val(vma->vm_page_prot) | _PAGE_DIRTY); + + rc = remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, + vma->vm_end - vma->vm_start, prot); + + pr_devel("%s(): paste addr %llx at %lx, rc %d\n", __func__, + paste_addr, vma->vm_start, rc); + + return rc; +} + +static long coproc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + switch (cmd) { + case VAS_TX_WIN_OPEN: + return coproc_ioc_tx_win_open(fp, arg); + default: + return -EINVAL; + } +} + +static struct file_operations coproc_fops = { + .open = coproc_open, + .release = coproc_release, + .mmap = coproc_mmap, + .unlocked_ioctl = coproc_ioctl, +}; + +/* + * Supporting only nx-gzip coprocessor type now, but this API code + * extended to other coprocessor types later. + */ +int vas_register_coproc_api(struct module *mod, enum vas_cop_type cop_type, + const char *name, + const struct vas_user_win_ops *vops) +{ + int rc = -EINVAL; + dev_t devno; + + rc = alloc_chrdev_region(&coproc_device.devt, 1, 1, name); + if (rc) { + pr_err("Unable to allocate coproc major number: %i\n", rc); + return rc; + } + + pr_devel("%s device allocated, dev [%i,%i]\n", name, + MAJOR(coproc_device.devt), MINOR(coproc_device.devt)); + + coproc_device.class = class_create(mod, name); + if (IS_ERR(coproc_device.class)) { + rc = PTR_ERR(coproc_device.class); + pr_err("Unable to create %s class %d\n", name, rc); + goto err_class; + } + coproc_device.class->devnode = coproc_devnode; + coproc_device.cop_type = cop_type; + coproc_device.vops = vops; + + coproc_fops.owner = mod; + cdev_init(&coproc_device.cdev, &coproc_fops); + + devno = MKDEV(MAJOR(coproc_device.devt), 0); + rc = cdev_add(&coproc_device.cdev, devno, 1); + if (rc) { + pr_err("cdev_add() failed %d\n", rc); + goto err_cdev; + } + + coproc_device.device = device_create(coproc_device.class, NULL, + devno, NULL, name, MINOR(devno)); + if (IS_ERR(coproc_device.device)) { + rc = PTR_ERR(coproc_device.device); + pr_err("Unable to create coproc-%d %d\n", MINOR(devno), rc); + goto err; + } + + pr_devel("%s: Added dev [%d,%d]\n", __func__, MAJOR(devno), + MINOR(devno)); + + return 0; + +err: + cdev_del(&coproc_device.cdev); +err_cdev: + class_destroy(coproc_device.class); +err_class: + unregister_chrdev_region(coproc_device.devt, 1); + return rc; +} + +void vas_unregister_coproc_api(void) +{ + dev_t devno; + + cdev_del(&coproc_device.cdev); + devno = MKDEV(MAJOR(coproc_device.devt), 0); + device_destroy(coproc_device.class, devno); + + class_destroy(coproc_device.class); + unregister_chrdev_region(coproc_device.devt, 1); +} diff --git a/arch/powerpc/platforms/cell/spider-pci.c b/arch/powerpc/platforms/cell/spider-pci.c index 93ea41680f54..a1c293f42a1f 100644 --- a/arch/powerpc/platforms/cell/spider-pci.c +++ b/arch/powerpc/platforms/cell/spider-pci.c @@ -25,10 +25,9 @@ struct spiderpci_iowa_private { static void spiderpci_io_flush(struct iowa_bus *bus) { struct spiderpci_iowa_private *priv; - u32 val; priv = bus->private; - val = in_be32(priv->regs + SPIDER_PCI_DUMMY_READ); + in_be32(priv->regs + SPIDER_PCI_DUMMY_READ); iosync(); } diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c index d56b4e3241cd..b41e81b22fdc 100644 --- a/arch/powerpc/platforms/cell/spufs/switch.c +++ b/arch/powerpc/platforms/cell/spufs/switch.c @@ -1657,14 +1657,13 @@ static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu) static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu) { struct spu_problem __iomem *prob = spu->problem; - u32 dummy = 0; /* Restore, Step 66: * If CSA.MB_Stat[P]=0 (mailbox empty) then * read from the PPU_MB register. */ if ((csa->prob.mb_stat_R & 0xFF) == 0) { - dummy = in_be32(&prob->pu_mb_R); + in_be32(&prob->pu_mb_R); eieio(); } } @@ -1672,14 +1671,13 @@ static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu) static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu) { struct spu_priv2 __iomem *priv2 = spu->priv2; - u64 dummy = 0UL; /* Restore, Step 66: * If CSA.MB_Stat[I]=0 (mailbox empty) then * read from the PPUINT_MB register. */ if ((csa->prob.mb_stat_R & 0xFF0000) == 0) { - dummy = in_be64(&priv2->puint_mb_R); + in_be64(&priv2->puint_mb_R); eieio(); spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); eieio(); diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c index 53065d564161..85521b3e7098 100644 --- a/arch/powerpc/platforms/embedded6xx/holly.c +++ b/arch/powerpc/platforms/embedded6xx/holly.c @@ -251,8 +251,8 @@ static int ppc750_machine_check_exception(struct pt_regs *regs) /* Are we prepared to handle this fault */ if ((entry = search_exception_tables(regs->nip)) != NULL) { tsi108_clear_pci_cfg_error(); - regs->msr |= MSR_RI; - regs->nip = extable_fixup(entry); + regs_set_return_msr(regs, regs->msr | MSR_RI); + regs_set_return_ip(regs, extable_fixup(entry)); return 1; } return 0; diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c index 5565647dc879..d8da6a483e59 100644 --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c @@ -173,8 +173,8 @@ static int mpc7448_machine_check_exception(struct pt_regs *regs) /* Are we prepared to handle this fault */ if ((entry = search_exception_tables(regs->nip)) != NULL) { tsi108_clear_pci_cfg_error(); - regs->msr |= MSR_RI; - regs->nip = extable_fixup(entry); + regs_set_return_msr(regs, regs->msr | MSR_RI); + regs_set_return_ip(regs, extable_fixup(entry)); return 1; } return 0; diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig new file mode 100644 index 000000000000..8f6a81978461 --- /dev/null +++ b/arch/powerpc/platforms/microwatt/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +config PPC_MICROWATT + depends on PPC_BOOK3S_64 && !SMP + bool "Microwatt SoC platform" + select PPC_XICS + select PPC_ICS_NATIVE + select PPC_ICP_NATIVE + select PPC_NATIVE + select PPC_UDBG_16550 + select ARCH_RANDOM + help + This option enables support for FPGA-based Microwatt implementations. + diff --git a/arch/powerpc/platforms/microwatt/Makefile b/arch/powerpc/platforms/microwatt/Makefile new file mode 100644 index 000000000000..116d6d3ad3f0 --- /dev/null +++ b/arch/powerpc/platforms/microwatt/Makefile @@ -0,0 +1 @@ +obj-y += setup.o rng.o diff --git a/arch/powerpc/platforms/microwatt/rng.c b/arch/powerpc/platforms/microwatt/rng.c new file mode 100644 index 000000000000..3d8ee6eb7dad --- /dev/null +++ b/arch/powerpc/platforms/microwatt/rng.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Derived from arch/powerpc/platforms/powernv/rng.c, which is: + * Copyright 2013, Michael Ellerman, IBM Corporation. + */ + +#define pr_fmt(fmt) "microwatt-rng: " fmt + +#include +#include +#include +#include +#include + +#define DARN_ERR 0xFFFFFFFFFFFFFFFFul + +int microwatt_get_random_darn(unsigned long *v) +{ + unsigned long val; + + /* Using DARN with L=1 - 64-bit conditioned random number */ + asm volatile(PPC_DARN(%0, 1) : "=r"(val)); + + if (val == DARN_ERR) + return 0; + + *v = val; + + return 1; +} + +static __init int rng_init(void) +{ + unsigned long val; + int i; + + for (i = 0; i < 10; i++) { + if (microwatt_get_random_darn(&val)) { + ppc_md.get_random_seed = microwatt_get_random_darn; + return 0; + } + } + + pr_warn("Unable to use DARN for get_random_seed()\n"); + + return -EIO; +} +machine_subsys_initcall(, rng_init); diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c new file mode 100644 index 000000000000..0b02603bdb74 --- /dev/null +++ b/arch/powerpc/platforms/microwatt/setup.c @@ -0,0 +1,41 @@ +/* + * Microwatt FPGA-based SoC platform setup code. + * + * Copyright 2020 Paul Mackerras (paulus@ozlabs.org), IBM Corp. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static void __init microwatt_init_IRQ(void) +{ + xics_init(); +} + +static int __init microwatt_probe(void) +{ + return of_machine_is_compatible("microwatt-soc"); +} + +static int __init microwatt_populate(void) +{ + return of_platform_default_populate(NULL, NULL, NULL); +} +machine_arch_initcall(microwatt, microwatt_populate); + +define_machine(microwatt) { + .name = "microwatt", + .probe = microwatt_probe, + .init_IRQ = microwatt_init_IRQ, + .progress = udbg_progress, + .calibrate_decr = generic_calibrate_decr, +}; diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c index 1c954c90b0f4..9b88e3cded7d 100644 --- a/arch/powerpc/platforms/pasemi/idle.c +++ b/arch/powerpc/platforms/pasemi/idle.c @@ -37,7 +37,7 @@ static int pasemi_system_reset_exception(struct pt_regs *regs) */ if (regs->msr & SRR1_WAKEMASK) - regs->nip = regs->link; + regs_set_return_ip(regs, regs->link); switch (regs->msr & SRR1_WAKEMASK) { case SRR1_WAKEDEC: @@ -58,7 +58,7 @@ static int pasemi_system_reset_exception(struct pt_regs *regs) restore_astate(hard_smp_processor_id()); /* everything handled */ - regs->msr |= MSR_RI; + regs_set_return_msr(regs, regs->msr | MSR_RI); return 1; } diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c index 9d4ecd292255..d20ef35e6d9d 100644 --- a/arch/powerpc/platforms/powermac/bootx_init.c +++ b/arch/powerpc/platforms/powermac/bootx_init.c @@ -433,7 +433,7 @@ static void __init btext_welcome(boot_infos_t *bi) bootx_printf("\nframe buffer at : 0x%x", bi->dispDeviceBase); bootx_printf(" (phys), 0x%x", bi->logicalDisplayBase); bootx_printf(" (log)"); - bootx_printf("\nklimit : 0x%x",(unsigned long)klimit); + bootx_printf("\nklimit : 0x%x",(unsigned long)_end); bootx_printf("\nboot_info at : 0x%x", bi); __asm__ __volatile__ ("mfmsr %0" : "=r" (flags)); bootx_printf("\nMSR : 0x%x", flags); diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index adae2a6712e1..bdfea6d6ab69 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -810,7 +810,7 @@ static int smp_core99_kick_cpu(int nr) * b __secondary_start_pmac_0 + nr*8 */ target = (unsigned long) __secondary_start_pmac_0 + nr * 8; - patch_branch((struct ppc_inst *)vector, target, BRANCH_SET_LINK); + patch_branch(vector, target, BRANCH_SET_LINK); /* Put some life in our friend */ pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); @@ -823,7 +823,7 @@ static int smp_core99_kick_cpu(int nr) mdelay(1); /* Restore our exception vector */ - patch_instruction((struct ppc_inst *)vector, ppc_inst(save_vector)); + patch_instruction(vector, ppc_inst(save_vector)); local_irq_restore(flags); if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig index 619b093a0657..043eefbbdd28 100644 --- a/arch/powerpc/platforms/powernv/Kconfig +++ b/arch/powerpc/platforms/powernv/Kconfig @@ -33,20 +33,6 @@ config PPC_MEMTRACE Enabling this option allows for runtime allocation of memory (RAM) for hardware tracing. -config PPC_VAS - bool "IBM Virtual Accelerator Switchboard (VAS)" - depends on PPC_POWERNV && PPC_64K_PAGES - default y - help - This enables support for IBM Virtual Accelerator Switchboard (VAS). - - VAS allows accelerators in co-processors like NX-GZIP and NX-842 - to be accessible to kernel subsystems and user processes. - - VAS adapters are found in POWER9 based systems. - - If unsure, say N. - config SCOM_DEBUGFS bool "Expose SCOM controllers via debugfs" depends on DEBUG_FS diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile index be2546b96816..dc7b37c23b60 100644 --- a/arch/powerpc/platforms/powernv/Makefile +++ b/arch/powerpc/platforms/powernv/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o obj-$(CONFIG_OPAL_PRD) += opal-prd.o obj-$(CONFIG_PERF_EVENTS) += opal-imc.o obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o -obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o vas-api.o +obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o obj-$(CONFIG_OCXL_BASE) += ocxl.o obj-$(CONFIG_SCOM_DEBUGFS) += opal-xscom.o obj-$(CONFIG_PPC_SECURE_BOOT) += opal-secvar.o diff --git a/arch/powerpc/platforms/powernv/opal-call.c b/arch/powerpc/platforms/powernv/opal-call.c index 01401e3da7ca..f812c74c61e5 100644 --- a/arch/powerpc/platforms/powernv/opal-call.c +++ b/arch/powerpc/platforms/powernv/opal-call.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include #include @@ -100,6 +101,9 @@ static int64_t opal_call(int64_t a0, int64_t a1, int64_t a2, int64_t a3, bool mmu = (msr & (MSR_IR|MSR_DR)); int64_t ret; + /* OPAL call / firmware may use SRR and/or HSRR */ + srr_regs_clobbered(); + msr &= ~MSR_EE; if (unlikely(!mmu)) diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c index 303d7c775740..2835376e61a4 100644 --- a/arch/powerpc/platforms/powernv/opal.c +++ b/arch/powerpc/platforms/powernv/opal.c @@ -773,7 +773,7 @@ bool opal_mce_check_early_recovery(struct pt_regs *regs) * Setup regs->nip to rfi into fixup address. */ if (recover_addr) - regs->nip = recover_addr; + regs_set_return_ip(regs, recover_addr); out: return !!recover_addr; diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index b18468dc31ff..6bb3c52633fb 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -711,7 +711,7 @@ int pnv_pci_cfg_write(struct pci_dn *pdn, return PCIBIOS_SUCCESSFUL; } -#if CONFIG_EEH +#ifdef CONFIG_EEH static bool pnv_pci_cfg_check(struct pci_dn *pdn) { struct eeh_dev *edev = NULL; diff --git a/arch/powerpc/platforms/powernv/subcore.c b/arch/powerpc/platforms/powernv/subcore.c index 73207b53dc2b..7e98b00ea2e8 100644 --- a/arch/powerpc/platforms/powernv/subcore.c +++ b/arch/powerpc/platforms/powernv/subcore.c @@ -169,6 +169,16 @@ static void update_hid_in_slw(u64 hid0) } } +static inline void update_power8_hid0(unsigned long hid0) +{ + /* + * The HID0 update on Power8 should at the very least be + * preceded by a SYNC instruction followed by an ISYNC + * instruction + */ + asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); +} + static void unsplit_core(void) { u64 hid0, mask; diff --git a/arch/powerpc/platforms/powernv/vas-api.c b/arch/powerpc/platforms/powernv/vas-api.c deleted file mode 100644 index 98ed5d8c5441..000000000000 --- a/arch/powerpc/platforms/powernv/vas-api.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * VAS user space API for its accelerators (Only NX-GZIP is supported now) - * Copyright (C) 2019 Haren Myneni, IBM Corp - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "vas.h" - -/* - * The driver creates the device node that can be used as follows: - * For NX-GZIP - * - * fd = open("/dev/crypto/nx-gzip", O_RDWR); - * rc = ioctl(fd, VAS_TX_WIN_OPEN, &attr); - * paste_addr = mmap(NULL, PAGE_SIZE, prot, MAP_SHARED, fd, 0ULL). - * vas_copy(&crb, 0, 1); - * vas_paste(paste_addr, 0, 1); - * close(fd) or exit process to close window. - * - * where "vas_copy" and "vas_paste" are defined in copy-paste.h. - * copy/paste returns to the user space directly. So refer NX hardware - * documententation for exact copy/paste usage and completion / error - * conditions. - */ - -/* - * Wrapper object for the nx-gzip device - there is just one instance of - * this node for the whole system. - */ -static struct coproc_dev { - struct cdev cdev; - struct device *device; - char *name; - dev_t devt; - struct class *class; - enum vas_cop_type cop_type; -} coproc_device; - -struct coproc_instance { - struct coproc_dev *coproc; - struct vas_window *txwin; -}; - -static char *coproc_devnode(struct device *dev, umode_t *mode) -{ - return kasprintf(GFP_KERNEL, "crypto/%s", dev_name(dev)); -} - -static int coproc_open(struct inode *inode, struct file *fp) -{ - struct coproc_instance *cp_inst; - - cp_inst = kzalloc(sizeof(*cp_inst), GFP_KERNEL); - if (!cp_inst) - return -ENOMEM; - - cp_inst->coproc = container_of(inode->i_cdev, struct coproc_dev, - cdev); - fp->private_data = cp_inst; - - return 0; -} - -static int coproc_ioc_tx_win_open(struct file *fp, unsigned long arg) -{ - void __user *uptr = (void __user *)arg; - struct vas_tx_win_attr txattr = {}; - struct vas_tx_win_open_attr uattr; - struct coproc_instance *cp_inst; - struct vas_window *txwin; - int rc, vasid; - - cp_inst = fp->private_data; - - /* - * One window for file descriptor - */ - if (cp_inst->txwin) - return -EEXIST; - - rc = copy_from_user(&uattr, uptr, sizeof(uattr)); - if (rc) { - pr_err("%s(): copy_from_user() returns %d\n", __func__, rc); - return -EFAULT; - } - - if (uattr.version != 1) { - pr_err("Invalid version\n"); - return -EINVAL; - } - - vasid = uattr.vas_id; - - vas_init_tx_win_attr(&txattr, cp_inst->coproc->cop_type); - - txattr.lpid = mfspr(SPRN_LPID); - txattr.pidr = mfspr(SPRN_PID); - txattr.user_win = true; - txattr.rsvd_txbuf_count = false; - txattr.pswid = false; - - pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr, - mfspr(SPRN_PID)); - - txwin = vas_tx_win_open(vasid, cp_inst->coproc->cop_type, &txattr); - if (IS_ERR(txwin)) { - pr_err("%s() vas_tx_win_open() failed, %ld\n", __func__, - PTR_ERR(txwin)); - return PTR_ERR(txwin); - } - - cp_inst->txwin = txwin; - - return 0; -} - -static int coproc_release(struct inode *inode, struct file *fp) -{ - struct coproc_instance *cp_inst = fp->private_data; - - if (cp_inst->txwin) { - vas_win_close(cp_inst->txwin); - cp_inst->txwin = NULL; - } - - kfree(cp_inst); - fp->private_data = NULL; - - /* - * We don't know here if user has other receive windows - * open, so we can't really call clear_thread_tidr(). - * So, once the process calls set_thread_tidr(), the - * TIDR value sticks around until process exits, resulting - * in an extra copy in restore_sprs(). - */ - - return 0; -} - -static int coproc_mmap(struct file *fp, struct vm_area_struct *vma) -{ - struct coproc_instance *cp_inst = fp->private_data; - struct vas_window *txwin; - unsigned long pfn; - u64 paste_addr; - pgprot_t prot; - int rc; - - txwin = cp_inst->txwin; - - if ((vma->vm_end - vma->vm_start) > PAGE_SIZE) { - pr_debug("%s(): size 0x%zx, PAGE_SIZE 0x%zx\n", __func__, - (vma->vm_end - vma->vm_start), PAGE_SIZE); - return -EINVAL; - } - - /* Ensure instance has an open send window */ - if (!txwin) { - pr_err("%s(): No send window open?\n", __func__); - return -EINVAL; - } - - vas_win_paste_addr(txwin, &paste_addr, NULL); - pfn = paste_addr >> PAGE_SHIFT; - - /* flags, page_prot from cxl_mmap(), except we want cachable */ - vma->vm_flags |= VM_IO | VM_PFNMAP; - vma->vm_page_prot = pgprot_cached(vma->vm_page_prot); - - prot = __pgprot(pgprot_val(vma->vm_page_prot) | _PAGE_DIRTY); - - rc = remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, - vma->vm_end - vma->vm_start, prot); - - pr_devel("%s(): paste addr %llx at %lx, rc %d\n", __func__, - paste_addr, vma->vm_start, rc); - - return rc; -} - -static long coproc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) -{ - switch (cmd) { - case VAS_TX_WIN_OPEN: - return coproc_ioc_tx_win_open(fp, arg); - default: - return -EINVAL; - } -} - -static struct file_operations coproc_fops = { - .open = coproc_open, - .release = coproc_release, - .mmap = coproc_mmap, - .unlocked_ioctl = coproc_ioctl, -}; - -/* - * Supporting only nx-gzip coprocessor type now, but this API code - * extended to other coprocessor types later. - */ -int vas_register_coproc_api(struct module *mod, enum vas_cop_type cop_type, - const char *name) -{ - int rc = -EINVAL; - dev_t devno; - - rc = alloc_chrdev_region(&coproc_device.devt, 1, 1, name); - if (rc) { - pr_err("Unable to allocate coproc major number: %i\n", rc); - return rc; - } - - pr_devel("%s device allocated, dev [%i,%i]\n", name, - MAJOR(coproc_device.devt), MINOR(coproc_device.devt)); - - coproc_device.class = class_create(mod, name); - if (IS_ERR(coproc_device.class)) { - rc = PTR_ERR(coproc_device.class); - pr_err("Unable to create %s class %d\n", name, rc); - goto err_class; - } - coproc_device.class->devnode = coproc_devnode; - coproc_device.cop_type = cop_type; - - coproc_fops.owner = mod; - cdev_init(&coproc_device.cdev, &coproc_fops); - - devno = MKDEV(MAJOR(coproc_device.devt), 0); - rc = cdev_add(&coproc_device.cdev, devno, 1); - if (rc) { - pr_err("cdev_add() failed %d\n", rc); - goto err_cdev; - } - - coproc_device.device = device_create(coproc_device.class, NULL, - devno, NULL, name, MINOR(devno)); - if (IS_ERR(coproc_device.device)) { - rc = PTR_ERR(coproc_device.device); - pr_err("Unable to create coproc-%d %d\n", MINOR(devno), rc); - goto err; - } - - pr_devel("%s: Added dev [%d,%d]\n", __func__, MAJOR(devno), - MINOR(devno)); - - return 0; - -err: - cdev_del(&coproc_device.cdev); -err_cdev: - class_destroy(coproc_device.class); -err_class: - unregister_chrdev_region(coproc_device.devt, 1); - return rc; -} -EXPORT_SYMBOL_GPL(vas_register_coproc_api); - -void vas_unregister_coproc_api(void) -{ - dev_t devno; - - cdev_del(&coproc_device.cdev); - devno = MKDEV(MAJOR(coproc_device.devt), 0); - device_destroy(coproc_device.class, devno); - - class_destroy(coproc_device.class); - unregister_chrdev_region(coproc_device.devt, 1); -} -EXPORT_SYMBOL_GPL(vas_unregister_coproc_api); diff --git a/arch/powerpc/platforms/powernv/vas-debug.c b/arch/powerpc/platforms/powernv/vas-debug.c index 41fa90d2f4ab..3ce89a4b54be 100644 --- a/arch/powerpc/platforms/powernv/vas-debug.c +++ b/arch/powerpc/platforms/powernv/vas-debug.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "vas.h" static struct dentry *vas_debugfs; @@ -28,7 +29,7 @@ static char *cop_to_str(int cop) static int info_show(struct seq_file *s, void *private) { - struct vas_window *window = s->private; + struct pnv_vas_window *window = s->private; mutex_lock(&vas_mutex); @@ -36,9 +37,9 @@ static int info_show(struct seq_file *s, void *private) if (!window->hvwc_map) goto unlock; - seq_printf(s, "Type: %s, %s\n", cop_to_str(window->cop), + seq_printf(s, "Type: %s, %s\n", cop_to_str(window->vas_win.cop), window->tx_win ? "Send" : "Receive"); - seq_printf(s, "Pid : %d\n", vas_window_pid(window)); + seq_printf(s, "Pid : %d\n", vas_window_pid(&window->vas_win)); unlock: mutex_unlock(&vas_mutex); @@ -47,7 +48,7 @@ unlock: DEFINE_SHOW_ATTRIBUTE(info); -static inline void print_reg(struct seq_file *s, struct vas_window *win, +static inline void print_reg(struct seq_file *s, struct pnv_vas_window *win, char *name, u32 reg) { seq_printf(s, "0x%016llx %s\n", read_hvwc_reg(win, name, reg), name); @@ -55,7 +56,7 @@ static inline void print_reg(struct seq_file *s, struct vas_window *win, static int hvwc_show(struct seq_file *s, void *private) { - struct vas_window *window = s->private; + struct pnv_vas_window *window = s->private; mutex_lock(&vas_mutex); @@ -103,8 +104,10 @@ unlock: DEFINE_SHOW_ATTRIBUTE(hvwc); -void vas_window_free_dbgdir(struct vas_window *window) +void vas_window_free_dbgdir(struct pnv_vas_window *pnv_win) { + struct vas_window *window = &pnv_win->vas_win; + if (window->dbgdir) { debugfs_remove_recursive(window->dbgdir); kfree(window->dbgname); @@ -113,21 +116,21 @@ void vas_window_free_dbgdir(struct vas_window *window) } } -void vas_window_init_dbgdir(struct vas_window *window) +void vas_window_init_dbgdir(struct pnv_vas_window *window) { struct dentry *d; if (!window->vinst->dbgdir) return; - window->dbgname = kzalloc(16, GFP_KERNEL); - if (!window->dbgname) + window->vas_win.dbgname = kzalloc(16, GFP_KERNEL); + if (!window->vas_win.dbgname) return; - snprintf(window->dbgname, 16, "w%d", window->winid); + snprintf(window->vas_win.dbgname, 16, "w%d", window->vas_win.winid); - d = debugfs_create_dir(window->dbgname, window->vinst->dbgdir); - window->dbgdir = d; + d = debugfs_create_dir(window->vas_win.dbgname, window->vinst->dbgdir); + window->vas_win.dbgdir = d; debugfs_create_file("info", 0444, d, window, &info_fops); debugfs_create_file("hvwc", 0444, d, window, &hvwc_fops); diff --git a/arch/powerpc/platforms/powernv/vas-fault.c b/arch/powerpc/platforms/powernv/vas-fault.c index 3d21fce254b7..a7aabc18039e 100644 --- a/arch/powerpc/platforms/powernv/vas-fault.c +++ b/arch/powerpc/platforms/powernv/vas-fault.c @@ -26,150 +26,6 @@ */ #define VAS_FAULT_WIN_FIFO_SIZE (4 << 20) -static void dump_crb(struct coprocessor_request_block *crb) -{ - struct data_descriptor_entry *dde; - struct nx_fault_stamp *nx; - - dde = &crb->source; - pr_devel("SrcDDE: addr 0x%llx, len %d, count %d, idx %d, flags %d\n", - be64_to_cpu(dde->address), be32_to_cpu(dde->length), - dde->count, dde->index, dde->flags); - - dde = &crb->target; - pr_devel("TgtDDE: addr 0x%llx, len %d, count %d, idx %d, flags %d\n", - be64_to_cpu(dde->address), be32_to_cpu(dde->length), - dde->count, dde->index, dde->flags); - - nx = &crb->stamp.nx; - pr_devel("NX Stamp: PSWID 0x%x, FSA 0x%llx, flags 0x%x, FS 0x%x\n", - be32_to_cpu(nx->pswid), - be64_to_cpu(crb->stamp.nx.fault_storage_addr), - nx->flags, nx->fault_status); -} - -/* - * Update the CSB to indicate a translation error. - * - * User space will be polling on CSB after the request is issued. - * If NX can handle the request without any issues, it updates CSB. - * Whereas if NX encounters page fault, the kernel will handle the - * fault and update CSB with translation error. - * - * If we are unable to update the CSB means copy_to_user failed due to - * invalid csb_addr, send a signal to the process. - */ -static void update_csb(struct vas_window *window, - struct coprocessor_request_block *crb) -{ - struct coprocessor_status_block csb; - struct kernel_siginfo info; - struct task_struct *tsk; - void __user *csb_addr; - struct pid *pid; - int rc; - - /* - * NX user space windows can not be opened for task->mm=NULL - * and faults will not be generated for kernel requests. - */ - if (WARN_ON_ONCE(!window->mm || !window->user_win)) - return; - - csb_addr = (void __user *)be64_to_cpu(crb->csb_addr); - - memset(&csb, 0, sizeof(csb)); - csb.cc = CSB_CC_FAULT_ADDRESS; - csb.ce = CSB_CE_TERMINATION; - csb.cs = 0; - csb.count = 0; - - /* - * NX operates and returns in BE format as defined CRB struct. - * So saves fault_storage_addr in BE as NX pastes in FIFO and - * expects user space to convert to CPU format. - */ - csb.address = crb->stamp.nx.fault_storage_addr; - csb.flags = 0; - - pid = window->pid; - tsk = get_pid_task(pid, PIDTYPE_PID); - /* - * Process closes send window after all pending NX requests are - * completed. In multi-thread applications, a child thread can - * open a window and can exit without closing it. May be some - * requests are pending or this window can be used by other - * threads later. We should handle faults if NX encounters - * pages faults on these requests. Update CSB with translation - * error and fault address. If csb_addr passed by user space is - * invalid, send SEGV signal to pid saved in window. If the - * child thread is not running, send the signal to tgid. - * Parent thread (tgid) will close this window upon its exit. - * - * pid and mm references are taken when window is opened by - * process (pid). So tgid is used only when child thread opens - * a window and exits without closing it. - */ - if (!tsk) { - pid = window->tgid; - tsk = get_pid_task(pid, PIDTYPE_PID); - /* - * Parent thread (tgid) will be closing window when it - * exits. So should not get here. - */ - if (WARN_ON_ONCE(!tsk)) - return; - } - - /* Return if the task is exiting. */ - if (tsk->flags & PF_EXITING) { - put_task_struct(tsk); - return; - } - - kthread_use_mm(window->mm); - rc = copy_to_user(csb_addr, &csb, sizeof(csb)); - /* - * User space polls on csb.flags (first byte). So add barrier - * then copy first byte with csb flags update. - */ - if (!rc) { - csb.flags = CSB_V; - /* Make sure update to csb.flags is visible now */ - smp_mb(); - rc = copy_to_user(csb_addr, &csb, sizeof(u8)); - } - kthread_unuse_mm(window->mm); - put_task_struct(tsk); - - /* Success */ - if (!rc) - return; - - pr_debug("Invalid CSB address 0x%p signalling pid(%d)\n", - csb_addr, pid_vnr(pid)); - - clear_siginfo(&info); - info.si_signo = SIGSEGV; - info.si_errno = EFAULT; - info.si_code = SEGV_MAPERR; - info.si_addr = csb_addr; - - /* - * process will be polling on csb.flags after request is sent to - * NX. So generally CSB update should not fail except when an - * application passes invalid csb_addr. So an error message will - * be displayed and leave it to user space whether to ignore or - * handle this signal. - */ - rcu_read_lock(); - rc = kill_pid_info(SIGSEGV, &info, pid); - rcu_read_unlock(); - - pr_devel("%s(): pid %d kill_proc_info() rc %d\n", __func__, - pid_vnr(pid), rc); -} - static void dump_fifo(struct vas_instance *vinst, void *entry) { unsigned long *end = vinst->fault_fifo + vinst->fault_fifo_size; @@ -212,7 +68,7 @@ irqreturn_t vas_fault_thread_fn(int irq, void *data) struct vas_instance *vinst = data; struct coprocessor_request_block *crb, *entry; struct coprocessor_request_block buf; - struct vas_window *window; + struct pnv_vas_window *window; unsigned long flags; void *fifo; @@ -272,7 +128,7 @@ irqreturn_t vas_fault_thread_fn(int irq, void *data) vinst->vas_id, vinst->fault_fifo, fifo, vinst->fault_crbs); - dump_crb(crb); + vas_dump_crb(crb); window = vas_pswid_to_window(vinst, be32_to_cpu(crb->stamp.nx.pswid)); @@ -293,7 +149,14 @@ irqreturn_t vas_fault_thread_fn(int irq, void *data) WARN_ON_ONCE(1); } else { - update_csb(window, crb); + /* + * NX sees faults only with user space windows. + */ + if (window->user_win) + vas_update_csb(crb, &window->vas_win.task_ref); + else + WARN_ON_ONCE(!window->user_win); + /* * Return credit for send window after processing * fault CRB. @@ -336,6 +199,7 @@ irqreturn_t vas_fault_handler(int irq, void *dev_id) int vas_setup_fault_window(struct vas_instance *vinst) { struct vas_rx_win_attr attr; + struct vas_window *win; vinst->fault_fifo_size = VAS_FAULT_WIN_FIFO_SIZE; vinst->fault_fifo = kzalloc(vinst->fault_fifo_size, GFP_KERNEL); @@ -364,18 +228,17 @@ int vas_setup_fault_window(struct vas_instance *vinst) attr.lnotify_pid = mfspr(SPRN_PID); attr.lnotify_tid = mfspr(SPRN_PID); - vinst->fault_win = vas_rx_win_open(vinst->vas_id, VAS_COP_TYPE_FAULT, - &attr); - - if (IS_ERR(vinst->fault_win)) { - pr_err("VAS: Error %ld opening FaultWin\n", - PTR_ERR(vinst->fault_win)); + win = vas_rx_win_open(vinst->vas_id, VAS_COP_TYPE_FAULT, &attr); + if (IS_ERR(win)) { + pr_err("VAS: Error %ld opening FaultWin\n", PTR_ERR(win)); kfree(vinst->fault_fifo); - return PTR_ERR(vinst->fault_win); + return PTR_ERR(win); } + vinst->fault_win = container_of(win, struct pnv_vas_window, vas_win); + pr_devel("VAS: Created FaultWin %d, LPID/PID/TID [%d/%d/%d]\n", - vinst->fault_win->winid, attr.lnotify_lpid, + vinst->fault_win->vas_win.winid, attr.lnotify_lpid, attr.lnotify_pid, attr.lnotify_tid); return 0; diff --git a/arch/powerpc/platforms/powernv/vas-trace.h b/arch/powerpc/platforms/powernv/vas-trace.h index a449b9f0c12e..ca2e08f2ddc0 100644 --- a/arch/powerpc/platforms/powernv/vas-trace.h +++ b/arch/powerpc/platforms/powernv/vas-trace.h @@ -80,7 +80,7 @@ TRACE_EVENT( vas_tx_win_open, TRACE_EVENT( vas_paste_crb, TP_PROTO(struct task_struct *tsk, - struct vas_window *win), + struct pnv_vas_window *win), TP_ARGS(tsk, win), @@ -96,7 +96,7 @@ TRACE_EVENT( vas_paste_crb, TP_fast_assign( __entry->pid = tsk->pid; __entry->vasid = win->vinst->vas_id; - __entry->winid = win->winid; + __entry->winid = win->vas_win.winid; __entry->paste_kaddr = (unsigned long)win->paste_kaddr ), diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c index 5f5fe63a3d1c..0f8d39fbf2b2 100644 --- a/arch/powerpc/platforms/powernv/vas-window.c +++ b/arch/powerpc/platforms/powernv/vas-window.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "vas.h" #include "copy-paste.h" @@ -26,14 +27,14 @@ * Compute the paste address region for the window @window using the * ->paste_base_addr and ->paste_win_id_shift we got from device tree. */ -void vas_win_paste_addr(struct vas_window *window, u64 *addr, int *len) +void vas_win_paste_addr(struct pnv_vas_window *window, u64 *addr, int *len) { int winid; u64 base, shift; base = window->vinst->paste_base_addr; shift = window->vinst->paste_win_id_shift; - winid = window->winid; + winid = window->vas_win.winid; *addr = base + (winid << shift); if (len) @@ -42,23 +43,23 @@ void vas_win_paste_addr(struct vas_window *window, u64 *addr, int *len) pr_debug("Txwin #%d: Paste addr 0x%llx\n", winid, *addr); } -static inline void get_hvwc_mmio_bar(struct vas_window *window, +static inline void get_hvwc_mmio_bar(struct pnv_vas_window *window, u64 *start, int *len) { u64 pbaddr; pbaddr = window->vinst->hvwc_bar_start; - *start = pbaddr + window->winid * VAS_HVWC_SIZE; + *start = pbaddr + window->vas_win.winid * VAS_HVWC_SIZE; *len = VAS_HVWC_SIZE; } -static inline void get_uwc_mmio_bar(struct vas_window *window, +static inline void get_uwc_mmio_bar(struct pnv_vas_window *window, u64 *start, int *len) { u64 pbaddr; pbaddr = window->vinst->uwc_bar_start; - *start = pbaddr + window->winid * VAS_UWC_SIZE; + *start = pbaddr + window->vas_win.winid * VAS_UWC_SIZE; *len = VAS_UWC_SIZE; } @@ -67,7 +68,7 @@ static inline void get_uwc_mmio_bar(struct vas_window *window, * space. Unlike MMIO regions (map_mmio_region() below), paste region must * be mapped cache-able and is only applicable to send windows. */ -static void *map_paste_region(struct vas_window *txwin) +static void *map_paste_region(struct pnv_vas_window *txwin) { int len; void *map; @@ -75,7 +76,7 @@ static void *map_paste_region(struct vas_window *txwin) u64 start; name = kasprintf(GFP_KERNEL, "window-v%d-w%d", txwin->vinst->vas_id, - txwin->winid); + txwin->vas_win.winid); if (!name) goto free_name; @@ -132,7 +133,7 @@ static void unmap_region(void *addr, u64 start, int len) /* * Unmap the paste address region for a window. */ -static void unmap_paste_region(struct vas_window *window) +static void unmap_paste_region(struct pnv_vas_window *window) { int len; u64 busaddr_start; @@ -153,7 +154,7 @@ static void unmap_paste_region(struct vas_window *window) * path, just minimize the time we hold the mutex for now. We can add * a per-instance mutex later if necessary. */ -static void unmap_winctx_mmio_bars(struct vas_window *window) +static void unmap_winctx_mmio_bars(struct pnv_vas_window *window) { int len; void *uwc_map; @@ -186,7 +187,7 @@ static void unmap_winctx_mmio_bars(struct vas_window *window) * OS/User Window Context (UWC) MMIO Base Address Region for the given window. * Map these bus addresses and save the mapped kernel addresses in @window. */ -static int map_winctx_mmio_bars(struct vas_window *window) +static int map_winctx_mmio_bars(struct pnv_vas_window *window) { int len; u64 start; @@ -214,7 +215,7 @@ static int map_winctx_mmio_bars(struct vas_window *window) * registers are not sequential. And, we can only write to offsets * with valid registers. */ -static void reset_window_regs(struct vas_window *window) +static void reset_window_regs(struct pnv_vas_window *window) { write_hvwc_reg(window, VREG(LPID), 0ULL); write_hvwc_reg(window, VREG(PID), 0ULL); @@ -270,7 +271,7 @@ static void reset_window_regs(struct vas_window *window) * want to add fields to vas_winctx and move the initialization to * init_vas_winctx_regs(). */ -static void init_xlate_regs(struct vas_window *window, bool user_win) +static void init_xlate_regs(struct pnv_vas_window *window, bool user_win) { u64 lpcr, val; @@ -335,7 +336,7 @@ static void init_xlate_regs(struct vas_window *window, bool user_win) * * TODO: Reserved (aka dedicated) send buffers are not supported yet. */ -static void init_rsvd_tx_buf_count(struct vas_window *txwin, +static void init_rsvd_tx_buf_count(struct pnv_vas_window *txwin, struct vas_winctx *winctx) { write_hvwc_reg(txwin, VREG(TX_RSVD_BUF_COUNT), 0ULL); @@ -357,7 +358,7 @@ static void init_rsvd_tx_buf_count(struct vas_window *txwin, * as a one-time task? That could work for NX but what about other * receivers? Let the receivers tell us the rx-fifo buffers for now. */ -static void init_winctx_regs(struct vas_window *window, +static void init_winctx_regs(struct pnv_vas_window *window, struct vas_winctx *winctx) { u64 val; @@ -519,10 +520,10 @@ static int vas_assign_window_id(struct ida *ida) return winid; } -static void vas_window_free(struct vas_window *window) +static void vas_window_free(struct pnv_vas_window *window) { - int winid = window->winid; struct vas_instance *vinst = window->vinst; + int winid = window->vas_win.winid; unmap_winctx_mmio_bars(window); @@ -533,10 +534,10 @@ static void vas_window_free(struct vas_window *window) vas_release_window_id(&vinst->ida, winid); } -static struct vas_window *vas_window_alloc(struct vas_instance *vinst) +static struct pnv_vas_window *vas_window_alloc(struct vas_instance *vinst) { int winid; - struct vas_window *window; + struct pnv_vas_window *window; winid = vas_assign_window_id(&vinst->ida); if (winid < 0) @@ -547,7 +548,7 @@ static struct vas_window *vas_window_alloc(struct vas_instance *vinst) goto out_free; window->vinst = vinst; - window->winid = winid; + window->vas_win.winid = winid; if (map_winctx_mmio_bars(window)) goto out_free; @@ -562,7 +563,7 @@ out_free: return ERR_PTR(-ENOMEM); } -static void put_rx_win(struct vas_window *rxwin) +static void put_rx_win(struct pnv_vas_window *rxwin) { /* Better not be a send window! */ WARN_ON_ONCE(rxwin->tx_win); @@ -578,10 +579,11 @@ static void put_rx_win(struct vas_window *rxwin) * * NOTE: We access ->windows[] table and assume that vinst->mutex is held. */ -static struct vas_window *get_user_rxwin(struct vas_instance *vinst, u32 pswid) +static struct pnv_vas_window *get_user_rxwin(struct vas_instance *vinst, + u32 pswid) { int vasid, winid; - struct vas_window *rxwin; + struct pnv_vas_window *rxwin; decode_pswid(pswid, &vasid, &winid); @@ -590,7 +592,7 @@ static struct vas_window *get_user_rxwin(struct vas_instance *vinst, u32 pswid) rxwin = vinst->windows[winid]; - if (!rxwin || rxwin->tx_win || rxwin->cop != VAS_COP_TYPE_FTW) + if (!rxwin || rxwin->tx_win || rxwin->vas_win.cop != VAS_COP_TYPE_FTW) return ERR_PTR(-EINVAL); return rxwin; @@ -602,10 +604,10 @@ static struct vas_window *get_user_rxwin(struct vas_instance *vinst, u32 pswid) * * See also function header of set_vinst_win(). */ -static struct vas_window *get_vinst_rxwin(struct vas_instance *vinst, +static struct pnv_vas_window *get_vinst_rxwin(struct vas_instance *vinst, enum vas_cop_type cop, u32 pswid) { - struct vas_window *rxwin; + struct pnv_vas_window *rxwin; mutex_lock(&vinst->mutex); @@ -638,9 +640,9 @@ static struct vas_window *get_vinst_rxwin(struct vas_instance *vinst, * window, we also save the window in the ->rxwin[] table. */ static void set_vinst_win(struct vas_instance *vinst, - struct vas_window *window) + struct pnv_vas_window *window) { - int id = window->winid; + int id = window->vas_win.winid; mutex_lock(&vinst->mutex); @@ -649,8 +651,8 @@ static void set_vinst_win(struct vas_instance *vinst, * unless its a user (FTW) window. */ if (!window->user_win && !window->tx_win) { - WARN_ON_ONCE(vinst->rxwin[window->cop]); - vinst->rxwin[window->cop] = window; + WARN_ON_ONCE(vinst->rxwin[window->vas_win.cop]); + vinst->rxwin[window->vas_win.cop] = window; } WARN_ON_ONCE(vinst->windows[id] != NULL); @@ -663,16 +665,16 @@ static void set_vinst_win(struct vas_instance *vinst, * Clear this window from the table(s) of windows for this VAS instance. * See also function header of set_vinst_win(). */ -static void clear_vinst_win(struct vas_window *window) +static void clear_vinst_win(struct pnv_vas_window *window) { - int id = window->winid; + int id = window->vas_win.winid; struct vas_instance *vinst = window->vinst; mutex_lock(&vinst->mutex); if (!window->user_win && !window->tx_win) { - WARN_ON_ONCE(!vinst->rxwin[window->cop]); - vinst->rxwin[window->cop] = NULL; + WARN_ON_ONCE(!vinst->rxwin[window->vas_win.cop]); + vinst->rxwin[window->vas_win.cop] = NULL; } WARN_ON_ONCE(vinst->windows[id] != window); @@ -681,7 +683,7 @@ static void clear_vinst_win(struct vas_window *window) mutex_unlock(&vinst->mutex); } -static void init_winctx_for_rxwin(struct vas_window *rxwin, +static void init_winctx_for_rxwin(struct pnv_vas_window *rxwin, struct vas_rx_win_attr *rxattr, struct vas_winctx *winctx) { @@ -702,7 +704,7 @@ static void init_winctx_for_rxwin(struct vas_window *rxwin, winctx->rx_fifo = rxattr->rx_fifo; winctx->rx_fifo_size = rxattr->rx_fifo_size; - winctx->wcreds_max = rxwin->wcreds_max; + winctx->wcreds_max = rxwin->vas_win.wcreds_max; winctx->pin_win = rxattr->pin_win; winctx->nx_win = rxattr->nx_win; @@ -851,7 +853,7 @@ EXPORT_SYMBOL_GPL(vas_init_rx_win_attr); struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop, struct vas_rx_win_attr *rxattr) { - struct vas_window *rxwin; + struct pnv_vas_window *rxwin; struct vas_winctx winctx; struct vas_instance *vinst; @@ -870,21 +872,21 @@ struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop, rxwin = vas_window_alloc(vinst); if (IS_ERR(rxwin)) { pr_devel("Unable to allocate memory for Rx window\n"); - return rxwin; + return (struct vas_window *)rxwin; } rxwin->tx_win = false; rxwin->nx_win = rxattr->nx_win; rxwin->user_win = rxattr->user_win; - rxwin->cop = cop; - rxwin->wcreds_max = rxattr->wcreds_max; + rxwin->vas_win.cop = cop; + rxwin->vas_win.wcreds_max = rxattr->wcreds_max; init_winctx_for_rxwin(rxwin, rxattr, &winctx); init_winctx_regs(rxwin, &winctx); set_vinst_win(vinst, rxwin); - return rxwin; + return &rxwin->vas_win; } EXPORT_SYMBOL_GPL(vas_rx_win_open); @@ -905,7 +907,7 @@ void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr, enum vas_cop_type cop) } EXPORT_SYMBOL_GPL(vas_init_tx_win_attr); -static void init_winctx_for_txwin(struct vas_window *txwin, +static void init_winctx_for_txwin(struct pnv_vas_window *txwin, struct vas_tx_win_attr *txattr, struct vas_winctx *winctx) { @@ -926,7 +928,7 @@ static void init_winctx_for_txwin(struct vas_window *txwin, */ memset(winctx, 0, sizeof(struct vas_winctx)); - winctx->wcreds_max = txwin->wcreds_max; + winctx->wcreds_max = txwin->vas_win.wcreds_max; winctx->user_win = txattr->user_win; winctx->nx_win = txwin->rxwin->nx_win; @@ -946,13 +948,13 @@ static void init_winctx_for_txwin(struct vas_window *txwin, winctx->lpid = txattr->lpid; winctx->pidr = txattr->pidr; - winctx->rx_win_id = txwin->rxwin->winid; + winctx->rx_win_id = txwin->rxwin->vas_win.winid; /* * IRQ and fault window setup is successful. Set fault window * for the send window so that ready to handle faults. */ if (txwin->vinst->virq) - winctx->fault_win_id = txwin->vinst->fault_win->winid; + winctx->fault_win_id = txwin->vinst->fault_win->vas_win.winid; winctx->dma_type = VAS_DMA_TYPE_INJECT; winctx->tc_mode = txattr->tc_mode; @@ -962,7 +964,8 @@ static void init_winctx_for_txwin(struct vas_window *txwin, winctx->irq_port = txwin->vinst->irq_port; winctx->pswid = txattr->pswid ? txattr->pswid : - encode_pswid(txwin->vinst->vas_id, txwin->winid); + encode_pswid(txwin->vinst->vas_id, + txwin->vas_win.winid); } static bool tx_win_args_valid(enum vas_cop_type cop, @@ -993,8 +996,8 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop, struct vas_tx_win_attr *attr) { int rc; - struct vas_window *txwin; - struct vas_window *rxwin; + struct pnv_vas_window *txwin; + struct pnv_vas_window *rxwin; struct vas_winctx winctx; struct vas_instance *vinst; @@ -1020,7 +1023,7 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop, rxwin = get_vinst_rxwin(vinst, cop, attr->pswid); if (IS_ERR(rxwin)) { pr_devel("No RxWin for vasid %d, cop %d\n", vasid, cop); - return rxwin; + return (struct vas_window *)rxwin; } txwin = vas_window_alloc(vinst); @@ -1029,12 +1032,12 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop, goto put_rxwin; } - txwin->cop = cop; + txwin->vas_win.cop = cop; txwin->tx_win = 1; txwin->rxwin = rxwin; txwin->nx_win = txwin->rxwin->nx_win; txwin->user_win = attr->user_win; - txwin->wcreds_max = attr->wcreds_max ?: VAS_WCREDS_DEFAULT; + txwin->vas_win.wcreds_max = attr->wcreds_max ?: VAS_WCREDS_DEFAULT; init_winctx_for_txwin(txwin, attr, &winctx); @@ -1064,56 +1067,16 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop, rc = -ENODEV; goto free_window; } - - /* - * Window opened by a child thread may not be closed when - * it exits. So take reference to its pid and release it - * when the window is free by parent thread. - * Acquire a reference to the task's pid to make sure - * pid will not be re-used - needed only for multithread - * applications. - */ - txwin->pid = get_task_pid(current, PIDTYPE_PID); - /* - * Acquire a reference to the task's mm. - */ - txwin->mm = get_task_mm(current); - - if (!txwin->mm) { - put_pid(txwin->pid); - pr_err("VAS: pid(%d): mm_struct is not found\n", - current->pid); - rc = -EPERM; + rc = get_vas_user_win_ref(&txwin->vas_win.task_ref); + if (rc) goto free_window; - } - mmgrab(txwin->mm); - mmput(txwin->mm); - mm_context_add_vas_window(txwin->mm); - /* - * Process closes window during exit. In the case of - * multithread application, the child thread can open - * window and can exit without closing it. Expects parent - * thread to use and close the window. So do not need - * to take pid reference for parent thread. - */ - txwin->tgid = find_get_pid(task_tgid_vnr(current)); - /* - * Even a process that has no foreign real address mapping can - * use an unpaired COPY instruction (to no real effect). Issue - * CP_ABORT to clear any pending COPY and prevent a covert - * channel. - * - * __switch_to() will issue CP_ABORT on future context switches - * if process / thread has any open VAS window (Use - * current->mm->context.vas_windows). - */ - asm volatile(PPC_CP_ABORT); + vas_user_win_add_mm_context(&txwin->vas_win.task_ref); } set_vinst_win(vinst, txwin); - return txwin; + return &txwin->vas_win; free_window: vas_window_free(txwin); @@ -1132,12 +1095,14 @@ int vas_copy_crb(void *crb, int offset) EXPORT_SYMBOL_GPL(vas_copy_crb); #define RMA_LSMP_REPORT_ENABLE PPC_BIT(53) -int vas_paste_crb(struct vas_window *txwin, int offset, bool re) +int vas_paste_crb(struct vas_window *vwin, int offset, bool re) { + struct pnv_vas_window *txwin; int rc; void *addr; uint64_t val; + txwin = container_of(vwin, struct pnv_vas_window, vas_win); trace_vas_paste_crb(current, txwin); /* @@ -1167,7 +1132,7 @@ int vas_paste_crb(struct vas_window *txwin, int offset, bool re) else rc = -EINVAL; - pr_debug("Txwin #%d: Msg count %llu\n", txwin->winid, + pr_debug("Txwin #%d: Msg count %llu\n", txwin->vas_win.winid, read_hvwc_reg(txwin, VREG(LRFIFO_PUSH))); return rc; @@ -1187,7 +1152,7 @@ EXPORT_SYMBOL_GPL(vas_paste_crb); * user space. (NX-842 driver waits for CSB and Fast thread-wakeup * doesn't use credit checking). */ -static void poll_window_credits(struct vas_window *window) +static void poll_window_credits(struct pnv_vas_window *window) { u64 val; int creds, mode; @@ -1217,7 +1182,7 @@ retry: * and issue CRB Kill to stop all pending requests. Need only * if there is a bug in NX or fault handling in kernel. */ - if (creds < window->wcreds_max) { + if (creds < window->vas_win.wcreds_max) { val = 0; set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(msecs_to_jiffies(10)); @@ -1228,7 +1193,8 @@ retry: */ if (!(count % 1000)) pr_warn_ratelimited("VAS: pid %d stuck. Waiting for credits returned for Window(%d). creds %d, Retries %d\n", - vas_window_pid(window), window->winid, + vas_window_pid(&window->vas_win), + window->vas_win.winid, creds, count); goto retry; @@ -1240,7 +1206,7 @@ retry: * short time to queue a CRB, so window should not be busy for too long. * Trying 5ms intervals. */ -static void poll_window_busy_state(struct vas_window *window) +static void poll_window_busy_state(struct pnv_vas_window *window) { int busy; u64 val; @@ -1260,7 +1226,8 @@ retry: */ if (!(count % 1000)) pr_warn_ratelimited("VAS: pid %d stuck. Window (ID=%d) is in busy state. Retries %d\n", - vas_window_pid(window), window->winid, count); + vas_window_pid(&window->vas_win), + window->vas_win.winid, count); goto retry; } @@ -1282,7 +1249,7 @@ retry: * casting out becomes necessary we should consider offloading the * job to a worker thread, so the window close can proceed quickly. */ -static void poll_window_castout(struct vas_window *window) +static void poll_window_castout(struct pnv_vas_window *window) { /* stub for now */ } @@ -1291,7 +1258,7 @@ static void poll_window_castout(struct vas_window *window) * Unpin and close a window so no new requests are accepted and the * hardware can evict this window from cache if necessary. */ -static void unpin_close_window(struct vas_window *window) +static void unpin_close_window(struct pnv_vas_window *window) { u64 val; @@ -1313,11 +1280,15 @@ static void unpin_close_window(struct vas_window *window) * * Besides the hardware, kernel has some bookkeeping of course. */ -int vas_win_close(struct vas_window *window) +int vas_win_close(struct vas_window *vwin) { - if (!window) + struct pnv_vas_window *window; + + if (!vwin) return 0; + window = container_of(vwin, struct pnv_vas_window, vas_win); + if (!window->tx_win && atomic_read(&window->num_txwins) != 0) { pr_devel("Attempting to close an active Rx window!\n"); WARN_ON_ONCE(1); @@ -1339,12 +1310,8 @@ int vas_win_close(struct vas_window *window) /* if send window, drop reference to matching receive window */ if (window->tx_win) { if (window->user_win) { - /* Drop references to pid and mm */ - put_pid(window->pid); - if (window->mm) { - mm_context_remove_vas_window(window->mm); - mmdrop(window->mm); - } + put_vas_user_win_ref(&vwin->task_ref); + mm_context_remove_vas_window(vwin->task_ref.mm); } put_rx_win(window->rxwin); } @@ -1377,7 +1344,7 @@ EXPORT_SYMBOL_GPL(vas_win_close); * - The kernel with return credit on fault window after reading entry * from fault FIFO. */ -void vas_return_credit(struct vas_window *window, bool tx) +void vas_return_credit(struct pnv_vas_window *window, bool tx) { uint64_t val; @@ -1391,10 +1358,10 @@ void vas_return_credit(struct vas_window *window, bool tx) } } -struct vas_window *vas_pswid_to_window(struct vas_instance *vinst, +struct pnv_vas_window *vas_pswid_to_window(struct vas_instance *vinst, uint32_t pswid) { - struct vas_window *window; + struct pnv_vas_window *window; int winid; if (!pswid) { @@ -1431,13 +1398,74 @@ struct vas_window *vas_pswid_to_window(struct vas_instance *vinst, * by NX). */ if (!window->tx_win || !window->user_win || !window->nx_win || - window->cop == VAS_COP_TYPE_FAULT || - window->cop == VAS_COP_TYPE_FTW) { + window->vas_win.cop == VAS_COP_TYPE_FAULT || + window->vas_win.cop == VAS_COP_TYPE_FTW) { pr_err("PSWID decode: id %d, tx %d, user %d, nx %d, cop %d\n", winid, window->tx_win, window->user_win, - window->nx_win, window->cop); + window->nx_win, window->vas_win.cop); WARN_ON(1); } return window; } + +static struct vas_window *vas_user_win_open(int vas_id, u64 flags, + enum vas_cop_type cop_type) +{ + struct vas_tx_win_attr txattr = {}; + + vas_init_tx_win_attr(&txattr, cop_type); + + txattr.lpid = mfspr(SPRN_LPID); + txattr.pidr = mfspr(SPRN_PID); + txattr.user_win = true; + txattr.rsvd_txbuf_count = false; + txattr.pswid = false; + + pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr, + mfspr(SPRN_PID)); + + return vas_tx_win_open(vas_id, cop_type, &txattr); +} + +static u64 vas_user_win_paste_addr(struct vas_window *txwin) +{ + struct pnv_vas_window *win; + u64 paste_addr; + + win = container_of(txwin, struct pnv_vas_window, vas_win); + vas_win_paste_addr(win, &paste_addr, NULL); + + return paste_addr; +} + +static int vas_user_win_close(struct vas_window *txwin) +{ + vas_win_close(txwin); + + return 0; +} + +static const struct vas_user_win_ops vops = { + .open_win = vas_user_win_open, + .paste_addr = vas_user_win_paste_addr, + .close_win = vas_user_win_close, +}; + +/* + * Supporting only nx-gzip coprocessor type now, but this API code + * extended to other coprocessor types later. + */ +int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type, + const char *name) +{ + + return vas_register_coproc_api(mod, cop_type, name, &vops); +} +EXPORT_SYMBOL_GPL(vas_register_api_powernv); + +void vas_unregister_api_powernv(void) +{ + vas_unregister_coproc_api(); +} +EXPORT_SYMBOL_GPL(vas_unregister_api_powernv); diff --git a/arch/powerpc/platforms/powernv/vas.h b/arch/powerpc/platforms/powernv/vas.h index c7db3190baca..8bb08e395de0 100644 --- a/arch/powerpc/platforms/powernv/vas.h +++ b/arch/powerpc/platforms/powernv/vas.h @@ -334,11 +334,11 @@ struct vas_instance { int fifo_in_progress; /* To wake up thread or return IRQ_HANDLED */ spinlock_t fault_lock; /* Protects fifo_in_progress update */ void *fault_fifo; - struct vas_window *fault_win; /* Fault window */ + struct pnv_vas_window *fault_win; /* Fault window */ struct mutex mutex; - struct vas_window *rxwin[VAS_COP_TYPE_MAX]; - struct vas_window *windows[VAS_WINDOWS_PER_CHIP]; + struct pnv_vas_window *rxwin[VAS_COP_TYPE_MAX]; + struct pnv_vas_window *windows[VAS_WINDOWS_PER_CHIP]; char *name; char *dbgname; @@ -346,32 +346,24 @@ struct vas_instance { }; /* - * In-kernel state a VAS window. One per window. + * In-kernel state a VAS window on PowerNV. One per window. */ -struct vas_window { +struct pnv_vas_window { + struct vas_window vas_win; /* Fields common to send and receive windows */ struct vas_instance *vinst; - int winid; bool tx_win; /* True if send window */ bool nx_win; /* True if NX window */ bool user_win; /* True if user space window */ void *hvwc_map; /* HV window context */ void *uwc_map; /* OS/User window context */ - struct pid *pid; /* Linux process id of owner */ - struct pid *tgid; /* Thread group ID of owner */ - struct mm_struct *mm; /* Linux process mm_struct */ - int wcreds_max; /* Window credits */ - - char *dbgname; - struct dentry *dbgdir; /* Fields applicable only to send windows */ void *paste_kaddr; char *paste_addr_name; - struct vas_window *rxwin; + struct pnv_vas_window *rxwin; - /* Feilds applicable only to receive windows */ - enum vas_cop_type cop; + /* Fields applicable only to receive windows */ atomic_t num_txwins; }; @@ -430,32 +422,32 @@ extern struct mutex vas_mutex; extern struct vas_instance *find_vas_instance(int vasid); extern void vas_init_dbgdir(void); extern void vas_instance_init_dbgdir(struct vas_instance *vinst); -extern void vas_window_init_dbgdir(struct vas_window *win); -extern void vas_window_free_dbgdir(struct vas_window *win); +extern void vas_window_init_dbgdir(struct pnv_vas_window *win); +extern void vas_window_free_dbgdir(struct pnv_vas_window *win); extern int vas_setup_fault_window(struct vas_instance *vinst); extern irqreturn_t vas_fault_thread_fn(int irq, void *data); extern irqreturn_t vas_fault_handler(int irq, void *dev_id); -extern void vas_return_credit(struct vas_window *window, bool tx); -extern struct vas_window *vas_pswid_to_window(struct vas_instance *vinst, +extern void vas_return_credit(struct pnv_vas_window *window, bool tx); +extern struct pnv_vas_window *vas_pswid_to_window(struct vas_instance *vinst, uint32_t pswid); -extern void vas_win_paste_addr(struct vas_window *window, u64 *addr, - int *len); +extern void vas_win_paste_addr(struct pnv_vas_window *window, u64 *addr, + int *len); static inline int vas_window_pid(struct vas_window *window) { - return pid_vnr(window->pid); + return pid_vnr(window->task_ref.pid); } -static inline void vas_log_write(struct vas_window *win, char *name, +static inline void vas_log_write(struct pnv_vas_window *win, char *name, void *regptr, u64 val) { if (val) pr_debug("%swin #%d: %s reg %p, val 0x%016llx\n", - win->tx_win ? "Tx" : "Rx", win->winid, name, - regptr, val); + win->tx_win ? "Tx" : "Rx", win->vas_win.winid, + name, regptr, val); } -static inline void write_uwc_reg(struct vas_window *win, char *name, +static inline void write_uwc_reg(struct pnv_vas_window *win, char *name, s32 reg, u64 val) { void *regptr; @@ -466,7 +458,7 @@ static inline void write_uwc_reg(struct vas_window *win, char *name, out_be64(regptr, val); } -static inline void write_hvwc_reg(struct vas_window *win, char *name, +static inline void write_hvwc_reg(struct pnv_vas_window *win, char *name, s32 reg, u64 val) { void *regptr; @@ -477,7 +469,7 @@ static inline void write_hvwc_reg(struct vas_window *win, char *name, out_be64(regptr, val); } -static inline u64 read_hvwc_reg(struct vas_window *win, +static inline u64 read_hvwc_reg(struct pnv_vas_window *win, char *name __maybe_unused, s32 reg) { return in_be64(win->hvwc_map+reg); diff --git a/arch/powerpc/platforms/ps3/Kconfig b/arch/powerpc/platforms/ps3/Kconfig index 4d0535cc7946..a4048b8c8c50 100644 --- a/arch/powerpc/platforms/ps3/Kconfig +++ b/arch/powerpc/platforms/ps3/Kconfig @@ -86,6 +86,15 @@ config PS3_SYS_MANAGER This support is required for PS3 system control. In general, all users will say Y or M. +config PS3_VERBOSE_RESULT + bool "PS3 Verbose LV1 hypercall results" if PS3_ADVANCED + depends on PPC_PS3 + help + Enables more verbose log mesages for LV1 hypercall results. + + If in doubt, say N here and reduce the size of the kernel by a + small amount. + config PS3_REPOSITORY_WRITE bool "PS3 Repository write support" if PS3_ADVANCED depends on PPC_PS3 diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c index d094321964fb..a81eac35d900 100644 --- a/arch/powerpc/platforms/ps3/mm.c +++ b/arch/powerpc/platforms/ps3/mm.c @@ -6,6 +6,7 @@ * Copyright 2006 Sony Corp. */ +#include #include #include #include @@ -1118,6 +1119,7 @@ int ps3_dma_region_init(struct ps3_system_bus_device *dev, enum ps3_dma_region_type region_type, void *addr, unsigned long len) { unsigned long lpar_addr; + int result; lpar_addr = addr ? ps3_mm_phys_to_lpar(__pa(addr)) : 0; @@ -1129,6 +1131,16 @@ int ps3_dma_region_init(struct ps3_system_bus_device *dev, r->offset -= map.r1.offset; r->len = len ? len : ALIGN(map.total, 1 << r->page_size); + dev->core.dma_mask = &r->dma_mask; + + result = dma_set_mask_and_coherent(&dev->core, DMA_BIT_MASK(32)); + + if (result < 0) { + dev_err(&dev->core, "%s:%d: dma_set_mask_and_coherent failed: %d\n", + __func__, __LINE__, result); + return result; + } + switch (dev->dev_type) { case PS3_DEVICE_TYPE_SB: r->region_ops = (USE_DYNAMIC_DMA) diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c index e9ae5dd03593..3de9145c20bc 100644 --- a/arch/powerpc/platforms/ps3/setup.c +++ b/arch/powerpc/platforms/ps3/setup.c @@ -36,6 +36,7 @@ DEFINE_MUTEX(ps3_gpu_mutex); EXPORT_SYMBOL_GPL(ps3_gpu_mutex); static union ps3_firmware_version ps3_firmware_version; +static char ps3_firmware_version_str[16]; void ps3_get_firmware_version(union ps3_firmware_version *v) { @@ -182,6 +183,40 @@ static int ps3_set_dabr(unsigned long dabr, unsigned long dabrx) return lv1_set_dabr(dabr, dabrx) ? -1 : 0; } +static ssize_t ps3_fw_version_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s", ps3_firmware_version_str); +} + +static int __init ps3_setup_sysfs(void) +{ + static struct kobj_attribute attr = __ATTR(fw-version, S_IRUGO, + ps3_fw_version_show, NULL); + static struct kobject *kobj; + int result; + + kobj = kobject_create_and_add("ps3", firmware_kobj); + + if (!kobj) { + pr_warn("%s:%d: kobject_create_and_add failed.\n", __func__, + __LINE__); + return -ENOMEM; + } + + result = sysfs_create_file(kobj, &attr.attr); + + if (result) { + pr_warn("%s:%d: sysfs_create_file failed.\n", __func__, + __LINE__); + kobject_put(kobj); + return -ENOMEM; + } + + return 0; +} +core_initcall(ps3_setup_sysfs); + static void __init ps3_setup_arch(void) { u64 tmp; @@ -190,9 +225,11 @@ static void __init ps3_setup_arch(void) lv1_get_version_info(&ps3_firmware_version.raw, &tmp); - printk(KERN_INFO "PS3 firmware version %u.%u.%u\n", - ps3_firmware_version.major, ps3_firmware_version.minor, - ps3_firmware_version.rev); + snprintf(ps3_firmware_version_str, sizeof(ps3_firmware_version_str), + "%u.%u.%u", ps3_firmware_version.major, + ps3_firmware_version.minor, ps3_firmware_version.rev); + + printk(KERN_INFO "PS3 firmware version %s\n", ps3_firmware_version_str); ps3_spu_set_platform(); diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index b431f41c6cb5..1a5665875165 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -64,9 +64,10 @@ static int ps3_open_hv_device_sb(struct ps3_system_bus_device *dev) result = lv1_open_device(dev->bus_id, dev->dev_id, 0); if (result) { - pr_debug("%s:%d: lv1_open_device failed: %s\n", __func__, - __LINE__, ps3_result(result)); - result = -EPERM; + pr_warn("%s:%d: lv1_open_device dev=%u.%u(%s) failed: %s\n", + __func__, __LINE__, dev->match_id, dev->match_sub_id, + dev_name(&dev->core), ps3_result(result)); + result = -EPERM; } done: @@ -120,7 +121,7 @@ static int ps3_open_hv_device_gpu(struct ps3_system_bus_device *dev) result = lv1_gpu_open(0); if (result) { - pr_debug("%s:%d: lv1_gpu_open failed: %s\n", __func__, + pr_warn("%s:%d: lv1_gpu_open failed: %s\n", __func__, __LINE__, ps3_result(result)); result = -EPERM; } diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile index c8a2b0b05ac0..4cda0ef87be0 100644 --- a/arch/powerpc/platforms/pseries/Makefile +++ b/arch/powerpc/platforms/pseries/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_PPC_SVM) += svm.o obj-$(CONFIG_FA_DUMP) += rtas-fadump.o obj-$(CONFIG_SUSPEND) += suspend.o +obj-$(CONFIG_PPC_VAS) += vas.o diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c index 3ac70790ec7a..b1f01ac0c29e 100644 --- a/arch/powerpc/platforms/pseries/dlpar.c +++ b/arch/powerpc/platforms/pseries/dlpar.c @@ -289,8 +289,7 @@ int dlpar_acquire_drc(u32 drc_index) { int dr_status, rc; - rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status, - DR_ENTITY_SENSE, drc_index); + rc = rtas_get_sensor(DR_ENTITY_SENSE, drc_index, &dr_status); if (rc || dr_status != DR_ENTITY_UNUSABLE) return -1; @@ -311,8 +310,7 @@ int dlpar_release_drc(u32 drc_index) { int dr_status, rc; - rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status, - DR_ENTITY_SENSE, drc_index); + rc = rtas_get_sensor(DR_ENTITY_SENSE, drc_index, &dr_status); if (rc || dr_status != DR_ENTITY_PRESENT) return -1; @@ -333,8 +331,7 @@ int dlpar_unisolate_drc(u32 drc_index) { int dr_status, rc; - rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status, - DR_ENTITY_SENSE, drc_index); + rc = rtas_get_sensor(DR_ENTITY_SENSE, drc_index, &dr_status); if (rc || dr_status != DR_ENTITY_PRESENT) return -1; diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c index 8377f1f7c78e..377d852f5a9a 100644 --- a/arch/powerpc/platforms/pseries/hotplug-memory.c +++ b/arch/powerpc/platforms/pseries/hotplug-memory.c @@ -348,7 +348,8 @@ static int pseries_remove_mem_node(struct device_node *np) static bool lmb_is_removable(struct drmem_lmb *lmb) { - if (!(lmb->flags & DRCONF_MEM_ASSIGNED)) + if ((lmb->flags & DRCONF_MEM_RESERVED) || + !(lmb->flags & DRCONF_MEM_ASSIGNED)) return false; #ifdef CONFIG_FA_DUMP @@ -401,7 +402,7 @@ static int dlpar_remove_lmb(struct drmem_lmb *lmb) static int dlpar_memory_remove_by_count(u32 lmbs_to_remove) { struct drmem_lmb *lmb; - int lmbs_removed = 0; + int lmbs_reserved = 0; int lmbs_available = 0; int rc; @@ -435,12 +436,12 @@ static int dlpar_memory_remove_by_count(u32 lmbs_to_remove) */ drmem_mark_lmb_reserved(lmb); - lmbs_removed++; - if (lmbs_removed == lmbs_to_remove) + lmbs_reserved++; + if (lmbs_reserved == lmbs_to_remove) break; } - if (lmbs_removed != lmbs_to_remove) { + if (lmbs_reserved != lmbs_to_remove) { pr_err("Memory hot-remove failed, adding LMB's back\n"); for_each_drmem_lmb(lmb) { @@ -453,6 +454,10 @@ static int dlpar_memory_remove_by_count(u32 lmbs_to_remove) lmb->drc_index); drmem_remove_lmb_reservation(lmb); + + lmbs_reserved--; + if (lmbs_reserved == 0) + break; } rc = -EINVAL; @@ -466,6 +471,10 @@ static int dlpar_memory_remove_by_count(u32 lmbs_to_remove) lmb->base_addr); drmem_remove_lmb_reservation(lmb); + + lmbs_reserved--; + if (lmbs_reserved == 0) + break; } rc = 0; } @@ -508,7 +517,6 @@ static int dlpar_memory_remove_by_index(u32 drc_index) static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index) { struct drmem_lmb *lmb, *start_lmb, *end_lmb; - int lmbs_available = 0; int rc; pr_info("Attempting to hot-remove %u LMB(s) at %x\n", @@ -521,18 +529,29 @@ static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index) if (rc) return -EINVAL; - /* Validate that there are enough LMBs to satisfy the request */ + /* + * Validate that all LMBs in range are not reserved. Note that it + * is ok if they are !ASSIGNED since our goal here is to remove the + * LMB range, regardless of whether some LMBs were already removed + * by any other reason. + * + * This is a contrast to what is done in remove_by_count() where we + * check for both RESERVED and !ASSIGNED (via lmb_is_removable()), + * because we want to remove a fixed amount of LMBs in that function. + */ for_each_drmem_lmb_in_range(lmb, start_lmb, end_lmb) { - if (lmb->flags & DRCONF_MEM_RESERVED) - break; - - lmbs_available++; + if (lmb->flags & DRCONF_MEM_RESERVED) { + pr_err("Memory at %llx (drc index %x) is reserved\n", + lmb->base_addr, lmb->drc_index); + return -EINVAL; + } } - if (lmbs_available < lmbs_to_remove) - return -EINVAL; - for_each_drmem_lmb_in_range(lmb, start_lmb, end_lmb) { + /* + * dlpar_remove_lmb() will error out if the LMB is already + * !ASSIGNED, but this case is a no-op for us. + */ if (!(lmb->flags & DRCONF_MEM_ASSIGNED)) continue; @@ -551,6 +570,13 @@ static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index) if (!drmem_lmb_reserved(lmb)) continue; + /* + * Setting the isolation state of an UNISOLATED/CONFIGURED + * device to UNISOLATE is a no-op, but the hypervisor can + * use it as a hint that the LMB removal failed. + */ + dlpar_unisolate_drc(lmb->drc_index); + rc = dlpar_add_lmb(lmb); if (rc) pr_err("Failed to add LMB, drc index %x\n", @@ -585,10 +611,6 @@ static inline int pseries_remove_mem_node(struct device_node *np) { return 0; } -static inline int dlpar_memory_remove(struct pseries_hp_errorlog *hp_elog) -{ - return -EOPNOTSUPP; -} static int dlpar_remove_lmb(struct drmem_lmb *lmb) { return -EOPNOTSUPP; @@ -651,7 +673,7 @@ static int dlpar_memory_add_by_count(u32 lmbs_to_add) { struct drmem_lmb *lmb; int lmbs_available = 0; - int lmbs_added = 0; + int lmbs_reserved = 0; int rc; pr_info("Attempting to hot-add %d LMB(s)\n", lmbs_to_add); @@ -661,6 +683,9 @@ static int dlpar_memory_add_by_count(u32 lmbs_to_add) /* Validate that there are enough LMBs to satisfy the request */ for_each_drmem_lmb(lmb) { + if (lmb->flags & DRCONF_MEM_RESERVED) + continue; + if (!(lmb->flags & DRCONF_MEM_ASSIGNED)) lmbs_available++; @@ -689,13 +714,12 @@ static int dlpar_memory_add_by_count(u32 lmbs_to_add) * requested LMBs cannot be added. */ drmem_mark_lmb_reserved(lmb); - - lmbs_added++; - if (lmbs_added == lmbs_to_add) + lmbs_reserved++; + if (lmbs_reserved == lmbs_to_add) break; } - if (lmbs_added != lmbs_to_add) { + if (lmbs_reserved != lmbs_to_add) { pr_err("Memory hot-add failed, removing any added LMBs\n"); for_each_drmem_lmb(lmb) { @@ -710,6 +734,10 @@ static int dlpar_memory_add_by_count(u32 lmbs_to_add) dlpar_release_drc(lmb->drc_index); drmem_remove_lmb_reservation(lmb); + lmbs_reserved--; + + if (lmbs_reserved == 0) + break; } rc = -EINVAL; } else { @@ -720,6 +748,10 @@ static int dlpar_memory_add_by_count(u32 lmbs_to_add) pr_debug("Memory at %llx (drc index %x) was hot-added\n", lmb->base_addr, lmb->drc_index); drmem_remove_lmb_reservation(lmb); + lmbs_reserved--; + + if (lmbs_reserved == 0) + break; } rc = 0; } @@ -764,7 +796,6 @@ static int dlpar_memory_add_by_index(u32 drc_index) static int dlpar_memory_add_by_ic(u32 lmbs_to_add, u32 drc_index) { struct drmem_lmb *lmb, *start_lmb, *end_lmb; - int lmbs_available = 0; int rc; pr_info("Attempting to hot-add %u LMB(s) at index %x\n", @@ -779,15 +810,14 @@ static int dlpar_memory_add_by_ic(u32 lmbs_to_add, u32 drc_index) /* Validate that the LMBs in this range are not reserved */ for_each_drmem_lmb_in_range(lmb, start_lmb, end_lmb) { - if (lmb->flags & DRCONF_MEM_RESERVED) - break; - - lmbs_available++; + /* Fail immediately if the whole range can't be hot-added */ + if (lmb->flags & DRCONF_MEM_RESERVED) { + pr_err("Memory at %llx (drc index %x) is reserved\n", + lmb->base_addr, lmb->drc_index); + return -EINVAL; + } } - if (lmbs_available < lmbs_to_add) - return -EINVAL; - for_each_drmem_lmb_in_range(lmb, start_lmb, end_lmb) { if (lmb->flags & DRCONF_MEM_ASSIGNED) continue; diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S index 8a2b8d64265b..ab9fc6506861 100644 --- a/arch/powerpc/platforms/pseries/hvCall.S +++ b/arch/powerpc/platforms/pseries/hvCall.S @@ -108,6 +108,10 @@ _GLOBAL_TOC(plpar_hcall_norets_notrace) mfcr r0 stw r0,8(r1) HVSC /* invoke the hypervisor */ + + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 blr /* return r3 = status */ @@ -120,6 +124,9 @@ _GLOBAL_TOC(plpar_hcall_norets) HCALL_BRANCH(plpar_hcall_norets_trace) HVSC /* invoke the hypervisor */ + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 blr /* return r3 = status */ @@ -129,6 +136,10 @@ plpar_hcall_norets_trace: HCALL_INST_PRECALL(R4) HVSC HCALL_INST_POSTCALL_NORETS + + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 blr @@ -159,6 +170,9 @@ _GLOBAL_TOC(plpar_hcall) std r6, 16(r12) std r7, 24(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 @@ -188,6 +202,9 @@ plpar_hcall_trace: HCALL_INST_POSTCALL(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 @@ -223,6 +240,9 @@ _GLOBAL(plpar_hcall_raw) std r6, 16(r12) std r7, 24(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 @@ -262,6 +282,9 @@ _GLOBAL_TOC(plpar_hcall9) std r11,56(r12) std r0, 64(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 @@ -300,6 +323,9 @@ plpar_hcall9_trace: HCALL_INST_POSTCALL(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 @@ -339,6 +365,9 @@ _GLOBAL(plpar_hcall9_raw) std r11,56(r12) std r0, 64(r12) + li r4,0 + stb r4,PACASRR_VALID(r13) + lwz r0,8(r1) mtcrf 0xff,r0 diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c index ef26fe40efb0..f48e87ac89c9 100644 --- a/arch/powerpc/platforms/pseries/papr_scm.c +++ b/arch/powerpc/platforms/pseries/papr_scm.c @@ -18,6 +18,7 @@ #include #include #include +#include #define BIND_ANY_ADDR (~0ul) @@ -114,6 +115,9 @@ struct papr_scm_priv { /* Health information for the dimm */ u64 health_bitmap; + /* Holds the last known dirty shutdown counter value */ + u64 dirty_shutdown_counter; + /* length of the stat buffer as expected by phyp */ size_t stat_buffer_len; }; @@ -260,7 +264,7 @@ err_out: * Query the Dimm performance stats from PHYP and copy them (if returned) to * provided struct papr_scm_perf_stats instance 'stats' that can hold atleast * (num_stats + header) bytes. - * - If buff_stats == NULL the return value is the size in byes of the buffer + * - If buff_stats == NULL the return value is the size in bytes of the buffer * needed to hold all supported performance-statistics. * - If buff_stats != NULL and num_stats == 0 then we copy all known * performance-statistics to 'buff_stat' and expect to be large enough to @@ -310,6 +314,13 @@ static ssize_t drc_pmem_query_stats(struct papr_scm_priv *p, dev_err(&p->pdev->dev, "Unknown performance stats, Err:0x%016lX\n", ret[0]); return -ENOENT; + } else if (rc == H_AUTHORITY) { + dev_info(&p->pdev->dev, + "Permission denied while accessing performance stats"); + return -EPERM; + } else if (rc == H_UNSUPPORTED) { + dev_dbg(&p->pdev->dev, "Performance stats unsupported\n"); + return -EOPNOTSUPP; } else if (rc != H_SUCCESS) { dev_err(&p->pdev->dev, "Failed to query performance stats, Err:%lld\n", rc); @@ -596,6 +607,16 @@ free_stats: return rc; } +/* Add the dirty-shutdown-counter value to the pdsm */ +static int papr_pdsm_dsc(struct papr_scm_priv *p, + union nd_pdsm_payload *payload) +{ + payload->health.extension_flags |= PDSM_DIMM_DSC_VALID; + payload->health.dimm_dsc = p->dirty_shutdown_counter; + + return sizeof(struct nd_papr_pdsm_health); +} + /* Fetch the DIMM health info and populate it in provided package. */ static int papr_pdsm_health(struct papr_scm_priv *p, union nd_pdsm_payload *payload) @@ -639,6 +660,8 @@ static int papr_pdsm_health(struct papr_scm_priv *p, /* Populate the fuel gauge meter in the payload */ papr_pdsm_fuel_gauge(p, payload); + /* Populate the dirty-shutdown-counter field */ + papr_pdsm_dsc(p, payload); rc = sizeof(struct nd_papr_pdsm_health); @@ -900,15 +923,41 @@ static ssize_t flags_show(struct device *dev, } DEVICE_ATTR_RO(flags); +static ssize_t dirty_shutdown_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct nvdimm *dimm = to_nvdimm(dev); + struct papr_scm_priv *p = nvdimm_provider_data(dimm); + + return sysfs_emit(buf, "%llu\n", p->dirty_shutdown_counter); +} +DEVICE_ATTR_RO(dirty_shutdown); + +static umode_t papr_nd_attribute_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct nvdimm *nvdimm = to_nvdimm(dev); + struct papr_scm_priv *p = nvdimm_provider_data(nvdimm); + + /* For if perf-stats not available remove perf_stats sysfs */ + if (attr == &dev_attr_perf_stats.attr && p->stat_buffer_len == 0) + return 0; + + return attr->mode; +} + /* papr_scm specific dimm attributes */ static struct attribute *papr_nd_attributes[] = { &dev_attr_flags.attr, &dev_attr_perf_stats.attr, + &dev_attr_dirty_shutdown.attr, NULL, }; static struct attribute_group papr_nd_attribute_group = { .name = "papr", + .is_visible = papr_nd_attribute_visible, .attrs = papr_nd_attributes, }; @@ -924,7 +973,6 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p) struct nd_region_desc ndr_desc; unsigned long dimm_flags; int target_nid, online_nid; - ssize_t stat_size; p->bus_desc.ndctl = papr_scm_ndctl; p->bus_desc.module = THIS_MODULE; @@ -1009,16 +1057,6 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p) list_add_tail(&p->region_list, &papr_nd_regions); mutex_unlock(&papr_ndr_lock); - /* Try retriving the stat buffer and see if its supported */ - stat_size = drc_pmem_query_stats(p, NULL, 0); - if (stat_size > 0) { - p->stat_buffer_len = stat_size; - dev_dbg(&p->pdev->dev, "Max perf-stat size %lu-bytes\n", - p->stat_buffer_len); - } else { - dev_info(&p->pdev->dev, "Dimm performance stats unavailable\n"); - } - return 0; err: nvdimm_bus_unregister(p->bus); @@ -1094,8 +1132,10 @@ static int papr_scm_probe(struct platform_device *pdev) u32 drc_index, metadata_size; u64 blocks, block_size; struct papr_scm_priv *p; + u8 uuid_raw[UUID_SIZE]; const char *uuid_str; - u64 uuid[2]; + ssize_t stat_size; + uuid_t uuid; int rc; /* check we have all the required DT properties */ @@ -1137,17 +1177,28 @@ static int papr_scm_probe(struct platform_device *pdev) p->is_volatile = !of_property_read_bool(dn, "ibm,cache-flush-required"); p->hcall_flush_required = of_property_read_bool(dn, "ibm,hcall-flush-required"); + if (of_property_read_u64(dn, "ibm,persistence-failed-count", + &p->dirty_shutdown_counter)) + p->dirty_shutdown_counter = 0; + /* We just need to ensure that set cookies are unique across */ - uuid_parse(uuid_str, (uuid_t *) uuid); + uuid_parse(uuid_str, &uuid); + /* - * cookie1 and cookie2 are not really little endian - * we store a little endian representation of the - * uuid str so that we can compare this with the label - * area cookie irrespective of the endian config with which - * the kernel is built. + * The cookie1 and cookie2 are not really little endian. + * We store a raw buffer representation of the + * uuid string so that we can compare this with the label + * area cookie irrespective of the endian configuration + * with which the kernel is built. + * + * Historically we stored the cookie in the below format. + * for a uuid string 72511b67-0b3b-42fd-8d1d-5be3cae8bcaa + * cookie1 was 0xfd423b0b671b5172 + * cookie2 was 0xaabce8cae35b1d8d */ - p->nd_set.cookie1 = cpu_to_le64(uuid[0]); - p->nd_set.cookie2 = cpu_to_le64(uuid[1]); + export_uuid(uuid_raw, &uuid); + p->nd_set.cookie1 = get_unaligned_le64(&uuid_raw[0]); + p->nd_set.cookie2 = get_unaligned_le64(&uuid_raw[8]); /* might be zero */ p->metadata_size = metadata_size; @@ -1172,6 +1223,14 @@ static int papr_scm_probe(struct platform_device *pdev) p->res.name = pdev->name; p->res.flags = IORESOURCE_MEM; + /* Try retrieving the stat buffer and see if its supported */ + stat_size = drc_pmem_query_stats(p, NULL, 0); + if (stat_size > 0) { + p->stat_buffer_len = stat_size; + dev_dbg(&p->pdev->dev, "Max perf-stat size %lu-bytes\n", + p->stat_buffer_len); + } + rc = papr_scm_nvdimm_init(p); if (rc) goto err2; diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c index 9d4ef65da7f3..167f2e1b8d39 100644 --- a/arch/powerpc/platforms/pseries/ras.c +++ b/arch/powerpc/platforms/pseries/ras.c @@ -487,8 +487,8 @@ int pSeries_system_reset_exception(struct pt_regs *regs) if ((be64_to_cpu(regs->msr) & (MSR_LE|MSR_RI|MSR_DR|MSR_IR|MSR_ME|MSR_PR| MSR_ILE|MSR_HV|MSR_SF)) == (MSR_DR|MSR_SF)) { - regs->nip = be64_to_cpu((__be64)regs->nip); - regs->msr = 0; + regs_set_return_ip(regs, be64_to_cpu((__be64)regs->nip)); + regs_set_return_msr(regs, 0); } #endif @@ -593,8 +593,6 @@ static int mce_handle_err_virtmode(struct pt_regs *regs, mce_err.severity = MCE_SEV_SEVERE; else if (severity == RTAS_SEVERITY_ERROR) mce_err.severity = MCE_SEV_SEVERE; - else if (severity == RTAS_SEVERITY_FATAL) - mce_err.severity = MCE_SEV_FATAL; else mce_err.severity = MCE_SEV_FATAL; diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 754e493b7c05..631a0d57b6cd 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -549,6 +549,15 @@ static void init_cpu_char_feature_flags(struct h_cpu_char_result *result) if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); + if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY) + security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); + + if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS) + security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); + + if (result->behaviour & H_CPU_BEHAV_NO_STF_BARRIER) + security_ftr_clear(SEC_FTR_STF_BARRIER); + if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR)) security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); } diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index c70b4be9f0a5..096629f54576 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -211,7 +211,9 @@ static __init void pSeries_smp_probe(void) if (!cpu_has_feature(CPU_FTR_SMT)) return; - if (check_kvm_guest()) { + check_kvm_guest(); + + if (is_kvm_guest()) { /* * KVM emulates doorbells by disabling FSCR[MSGP] so msgsndp * faults to the hypervisor which then reads the instruction diff --git a/arch/powerpc/platforms/pseries/vas.c b/arch/powerpc/platforms/pseries/vas.c new file mode 100644 index 000000000000..b5c1cf1bc64d --- /dev/null +++ b/arch/powerpc/platforms/pseries/vas.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2020-21 IBM Corp. + */ + +#define pr_fmt(fmt) "vas: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vas.h" + +#define VAS_INVALID_WIN_ADDRESS 0xFFFFFFFFFFFFFFFFul +#define VAS_DEFAULT_DOMAIN_ID 0xFFFFFFFFFFFFFFFFul +/* The hypervisor allows one credit per window right now */ +#define DEF_WIN_CREDS 1 + +static struct vas_all_caps caps_all; +static bool copypaste_feat; + +static struct vas_caps vascaps[VAS_MAX_FEAT_TYPE]; +static DEFINE_MUTEX(vas_pseries_mutex); + +static long hcall_return_busy_check(long rc) +{ + /* Check if we are stalled for some time */ + if (H_IS_LONG_BUSY(rc)) { + msleep(get_longbusy_msecs(rc)); + rc = H_BUSY; + } else if (rc == H_BUSY) { + cond_resched(); + } + + return rc; +} + +/* + * Allocate VAS window hcall + */ +static int h_allocate_vas_window(struct pseries_vas_window *win, u64 *domain, + u8 wintype, u16 credits) +{ + long retbuf[PLPAR_HCALL9_BUFSIZE] = {0}; + long rc; + + do { + rc = plpar_hcall9(H_ALLOCATE_VAS_WINDOW, retbuf, wintype, + credits, domain[0], domain[1], domain[2], + domain[3], domain[4], domain[5]); + + rc = hcall_return_busy_check(rc); + } while (rc == H_BUSY); + + if (rc == H_SUCCESS) { + if (win->win_addr == VAS_INVALID_WIN_ADDRESS) { + pr_err("H_ALLOCATE_VAS_WINDOW: COPY/PASTE is not supported\n"); + return -ENOTSUPP; + } + win->vas_win.winid = retbuf[0]; + win->win_addr = retbuf[1]; + win->complete_irq = retbuf[2]; + win->fault_irq = retbuf[3]; + return 0; + } + + pr_err("H_ALLOCATE_VAS_WINDOW error: %ld, wintype: %u, credits: %u\n", + rc, wintype, credits); + + return -EIO; +} + +/* + * Deallocate VAS window hcall. + */ +static int h_deallocate_vas_window(u64 winid) +{ + long rc; + + do { + rc = plpar_hcall_norets(H_DEALLOCATE_VAS_WINDOW, winid); + + rc = hcall_return_busy_check(rc); + } while (rc == H_BUSY); + + if (rc == H_SUCCESS) + return 0; + + pr_err("H_DEALLOCATE_VAS_WINDOW error: %ld, winid: %llu\n", + rc, winid); + return -EIO; +} + +/* + * Modify VAS window. + * After the window is opened with allocate window hcall, configure it + * with flags and LPAR PID before using. + */ +static int h_modify_vas_window(struct pseries_vas_window *win) +{ + long rc; + u32 lpid = mfspr(SPRN_PID); + + /* + * AMR value is not supported in Linux VAS implementation. + * The hypervisor ignores it if 0 is passed. + */ + do { + rc = plpar_hcall_norets(H_MODIFY_VAS_WINDOW, + win->vas_win.winid, lpid, 0, + VAS_MOD_WIN_FLAGS, 0); + + rc = hcall_return_busy_check(rc); + } while (rc == H_BUSY); + + if (rc == H_SUCCESS) + return 0; + + pr_err("H_MODIFY_VAS_WINDOW error: %ld, winid %u lpid %u\n", + rc, win->vas_win.winid, lpid); + return -EIO; +} + +/* + * This hcall is used to determine the capabilities from the hypervisor. + * @hcall: H_QUERY_VAS_CAPABILITIES or H_QUERY_NX_CAPABILITIES + * @query_type: If 0 is passed, the hypervisor returns the overall + * capabilities which provides all feature(s) that are + * available. Then query the hypervisor to get the + * corresponding capabilities for the specific feature. + * Example: H_QUERY_VAS_CAPABILITIES provides VAS GZIP QoS + * and VAS GZIP Default capabilities. + * H_QUERY_NX_CAPABILITIES provides NX GZIP + * capabilities. + * @result: Return buffer to save capabilities. + */ +int h_query_vas_capabilities(const u64 hcall, u8 query_type, u64 result) +{ + long rc; + + rc = plpar_hcall_norets(hcall, query_type, result); + + if (rc == H_SUCCESS) + return 0; + + pr_err("HCALL(%llx) error %ld, query_type %u, result buffer 0x%llx\n", + hcall, rc, query_type, result); + return -EIO; +} +EXPORT_SYMBOL_GPL(h_query_vas_capabilities); + +/* + * hcall to get fault CRB from the hypervisor. + */ +static int h_get_nx_fault(u32 winid, u64 buffer) +{ + long rc; + + rc = plpar_hcall_norets(H_GET_NX_FAULT, winid, buffer); + + if (rc == H_SUCCESS) + return 0; + + pr_err("H_GET_NX_FAULT error: %ld, winid %u, buffer 0x%llx\n", + rc, winid, buffer); + return -EIO; + +} + +/* + * Handle the fault interrupt. + * When the fault interrupt is received for each window, query the + * hypervisor to get the fault CRB on the specific fault. Then + * process the CRB by updating CSB or send signal if the user space + * CSB is invalid. + * Note: The hypervisor forwards an interrupt for each fault request. + * So one fault CRB to process for each H_GET_NX_FAULT hcall. + */ +irqreturn_t pseries_vas_fault_thread_fn(int irq, void *data) +{ + struct pseries_vas_window *txwin = data; + struct coprocessor_request_block crb; + struct vas_user_win_ref *tsk_ref; + int rc; + + rc = h_get_nx_fault(txwin->vas_win.winid, (u64)virt_to_phys(&crb)); + if (!rc) { + tsk_ref = &txwin->vas_win.task_ref; + vas_dump_crb(&crb); + vas_update_csb(&crb, tsk_ref); + } + + return IRQ_HANDLED; +} + +/* + * Allocate window and setup IRQ mapping. + */ +static int allocate_setup_window(struct pseries_vas_window *txwin, + u64 *domain, u8 wintype) +{ + int rc; + + rc = h_allocate_vas_window(txwin, domain, wintype, DEF_WIN_CREDS); + if (rc) + return rc; + /* + * On PowerVM, the hypervisor setup and forwards the fault + * interrupt per window. So the IRQ setup and fault handling + * will be done for each open window separately. + */ + txwin->fault_virq = irq_create_mapping(NULL, txwin->fault_irq); + if (!txwin->fault_virq) { + pr_err("Failed irq mapping %d\n", txwin->fault_irq); + rc = -EINVAL; + goto out_win; + } + + txwin->name = kasprintf(GFP_KERNEL, "vas-win-%d", + txwin->vas_win.winid); + if (!txwin->name) { + rc = -ENOMEM; + goto out_irq; + } + + rc = request_threaded_irq(txwin->fault_virq, NULL, + pseries_vas_fault_thread_fn, IRQF_ONESHOT, + txwin->name, txwin); + if (rc) { + pr_err("VAS-Window[%d]: Request IRQ(%u) failed with %d\n", + txwin->vas_win.winid, txwin->fault_virq, rc); + goto out_free; + } + + txwin->vas_win.wcreds_max = DEF_WIN_CREDS; + + return 0; +out_free: + kfree(txwin->name); +out_irq: + irq_dispose_mapping(txwin->fault_virq); +out_win: + h_deallocate_vas_window(txwin->vas_win.winid); + return rc; +} + +static inline void free_irq_setup(struct pseries_vas_window *txwin) +{ + free_irq(txwin->fault_virq, txwin); + kfree(txwin->name); + irq_dispose_mapping(txwin->fault_virq); +} + +static struct vas_window *vas_allocate_window(int vas_id, u64 flags, + enum vas_cop_type cop_type) +{ + long domain[PLPAR_HCALL9_BUFSIZE] = {VAS_DEFAULT_DOMAIN_ID}; + struct vas_cop_feat_caps *cop_feat_caps; + struct vas_caps *caps; + struct pseries_vas_window *txwin; + int rc; + + txwin = kzalloc(sizeof(*txwin), GFP_KERNEL); + if (!txwin) + return ERR_PTR(-ENOMEM); + + /* + * A VAS window can have many credits which means that many + * requests can be issued simultaneously. But the hypervisor + * restricts one credit per window. + * The hypervisor introduces 2 different types of credits: + * Default credit type (Uses normal priority FIFO): + * A limited number of credits are assigned to partitions + * based on processor entitlement. But these credits may be + * over-committed on a system depends on whether the CPUs + * are in shared or dedicated modes - that is, more requests + * may be issued across the system than NX can service at + * once which can result in paste command failure (RMA_busy). + * Then the process has to resend requests or fall-back to + * SW compression. + * Quality of Service (QoS) credit type (Uses high priority FIFO): + * To avoid NX HW contention, the system admins can assign + * QoS credits for each LPAR so that this partition is + * guaranteed access to NX resources. These credits are + * assigned to partitions via the HMC. + * Refer PAPR for more information. + * + * Allocate window with QoS credits if user requested. Otherwise + * default credits are used. + */ + if (flags & VAS_TX_WIN_FLAG_QOS_CREDIT) + caps = &vascaps[VAS_GZIP_QOS_FEAT_TYPE]; + else + caps = &vascaps[VAS_GZIP_DEF_FEAT_TYPE]; + + cop_feat_caps = &caps->caps; + + if (atomic_inc_return(&cop_feat_caps->used_lpar_creds) > + atomic_read(&cop_feat_caps->target_lpar_creds)) { + pr_err("Credits are not available to allocate window\n"); + rc = -EINVAL; + goto out; + } + + if (vas_id == -1) { + /* + * The user space is requesting to allocate a window on + * a VAS instance where the process is executing. + * On PowerVM, domain values are passed to the hypervisor + * to select VAS instance. Useful if the process is + * affinity to NUMA node. + * The hypervisor selects VAS instance if + * VAS_DEFAULT_DOMAIN_ID (-1) is passed for domain values. + * The h_allocate_vas_window hcall is defined to take a + * domain values as specified by h_home_node_associativity, + * So no unpacking needs to be done. + */ + rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, domain, + VPHN_FLAG_VCPU, smp_processor_id()); + if (rc != H_SUCCESS) { + pr_err("H_HOME_NODE_ASSOCIATIVITY error: %d\n", rc); + goto out; + } + } + + /* + * Allocate / Deallocate window hcalls and setup / free IRQs + * have to be protected with mutex. + * Open VAS window: Allocate window hcall and setup IRQ + * Close VAS window: Deallocate window hcall and free IRQ + * The hypervisor waits until all NX requests are + * completed before closing the window. So expects OS + * to handle NX faults, means IRQ can be freed only + * after the deallocate window hcall is returned. + * So once the window is closed with deallocate hcall before + * the IRQ is freed, it can be assigned to new allocate + * hcall with the same fault IRQ by the hypervisor. It can + * result in setup IRQ fail for the new window since the + * same fault IRQ is not freed by the OS before. + */ + mutex_lock(&vas_pseries_mutex); + rc = allocate_setup_window(txwin, (u64 *)&domain[0], + cop_feat_caps->win_type); + mutex_unlock(&vas_pseries_mutex); + if (rc) + goto out; + + /* + * Modify window and it is ready to use. + */ + rc = h_modify_vas_window(txwin); + if (!rc) + rc = get_vas_user_win_ref(&txwin->vas_win.task_ref); + if (rc) + goto out_free; + + vas_user_win_add_mm_context(&txwin->vas_win.task_ref); + txwin->win_type = cop_feat_caps->win_type; + mutex_lock(&vas_pseries_mutex); + list_add(&txwin->win_list, &caps->list); + mutex_unlock(&vas_pseries_mutex); + + return &txwin->vas_win; + +out_free: + /* + * Window is not operational. Free IRQ before closing + * window so that do not have to hold mutex. + */ + free_irq_setup(txwin); + h_deallocate_vas_window(txwin->vas_win.winid); +out: + atomic_dec(&cop_feat_caps->used_lpar_creds); + kfree(txwin); + return ERR_PTR(rc); +} + +static u64 vas_paste_address(struct vas_window *vwin) +{ + struct pseries_vas_window *win; + + win = container_of(vwin, struct pseries_vas_window, vas_win); + return win->win_addr; +} + +static int deallocate_free_window(struct pseries_vas_window *win) +{ + int rc = 0; + + /* + * The hypervisor waits for all requests including faults + * are processed before closing the window - Means all + * credits have to be returned. In the case of fault + * request, a credit is returned after OS issues + * H_GET_NX_FAULT hcall. + * So free IRQ after executing H_DEALLOCATE_VAS_WINDOW + * hcall. + */ + rc = h_deallocate_vas_window(win->vas_win.winid); + if (!rc) + free_irq_setup(win); + + return rc; +} + +static int vas_deallocate_window(struct vas_window *vwin) +{ + struct pseries_vas_window *win; + struct vas_cop_feat_caps *caps; + int rc = 0; + + if (!vwin) + return -EINVAL; + + win = container_of(vwin, struct pseries_vas_window, vas_win); + + /* Should not happen */ + if (win->win_type >= VAS_MAX_FEAT_TYPE) { + pr_err("Window (%u): Invalid window type %u\n", + vwin->winid, win->win_type); + return -EINVAL; + } + + caps = &vascaps[win->win_type].caps; + mutex_lock(&vas_pseries_mutex); + rc = deallocate_free_window(win); + if (rc) { + mutex_unlock(&vas_pseries_mutex); + return rc; + } + + list_del(&win->win_list); + atomic_dec(&caps->used_lpar_creds); + mutex_unlock(&vas_pseries_mutex); + + put_vas_user_win_ref(&vwin->task_ref); + mm_context_remove_vas_window(vwin->task_ref.mm); + + kfree(win); + return 0; +} + +static const struct vas_user_win_ops vops_pseries = { + .open_win = vas_allocate_window, /* Open and configure window */ + .paste_addr = vas_paste_address, /* To do copy/paste */ + .close_win = vas_deallocate_window, /* Close window */ +}; + +/* + * Supporting only nx-gzip coprocessor type now, but this API code + * extended to other coprocessor types later. + */ +int vas_register_api_pseries(struct module *mod, enum vas_cop_type cop_type, + const char *name) +{ + int rc; + + if (!copypaste_feat) + return -ENOTSUPP; + + rc = vas_register_coproc_api(mod, cop_type, name, &vops_pseries); + + return rc; +} +EXPORT_SYMBOL_GPL(vas_register_api_pseries); + +void vas_unregister_api_pseries(void) +{ + vas_unregister_coproc_api(); +} +EXPORT_SYMBOL_GPL(vas_unregister_api_pseries); + +/* + * Get the specific capabilities based on the feature type. + * Right now supports GZIP default and GZIP QoS capabilities. + */ +static int get_vas_capabilities(u8 feat, enum vas_cop_feat_type type, + struct hv_vas_cop_feat_caps *hv_caps) +{ + struct vas_cop_feat_caps *caps; + struct vas_caps *vcaps; + int rc = 0; + + vcaps = &vascaps[type]; + memset(vcaps, 0, sizeof(*vcaps)); + INIT_LIST_HEAD(&vcaps->list); + + caps = &vcaps->caps; + + rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES, feat, + (u64)virt_to_phys(hv_caps)); + if (rc) + return rc; + + caps->user_mode = hv_caps->user_mode; + if (!(caps->user_mode & VAS_COPY_PASTE_USER_MODE)) { + pr_err("User space COPY/PASTE is not supported\n"); + return -ENOTSUPP; + } + + caps->descriptor = be64_to_cpu(hv_caps->descriptor); + caps->win_type = hv_caps->win_type; + if (caps->win_type >= VAS_MAX_FEAT_TYPE) { + pr_err("Unsupported window type %u\n", caps->win_type); + return -EINVAL; + } + caps->max_lpar_creds = be16_to_cpu(hv_caps->max_lpar_creds); + caps->max_win_creds = be16_to_cpu(hv_caps->max_win_creds); + atomic_set(&caps->target_lpar_creds, + be16_to_cpu(hv_caps->target_lpar_creds)); + if (feat == VAS_GZIP_DEF_FEAT) { + caps->def_lpar_creds = be16_to_cpu(hv_caps->def_lpar_creds); + + if (caps->max_win_creds < DEF_WIN_CREDS) { + pr_err("Window creds(%u) > max allowed window creds(%u)\n", + DEF_WIN_CREDS, caps->max_win_creds); + return -EINVAL; + } + } + + copypaste_feat = true; + + return 0; +} + +static int __init pseries_vas_init(void) +{ + struct hv_vas_cop_feat_caps *hv_cop_caps; + struct hv_vas_all_caps *hv_caps; + int rc; + + /* + * Linux supports user space COPY/PASTE only with Radix + */ + if (!radix_enabled()) { + pr_err("API is supported only with radix page tables\n"); + return -ENOTSUPP; + } + + hv_caps = kmalloc(sizeof(*hv_caps), GFP_KERNEL); + if (!hv_caps) + return -ENOMEM; + /* + * Get VAS overall capabilities by passing 0 to feature type. + */ + rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES, 0, + (u64)virt_to_phys(hv_caps)); + if (rc) + goto out; + + caps_all.descriptor = be64_to_cpu(hv_caps->descriptor); + caps_all.feat_type = be64_to_cpu(hv_caps->feat_type); + + hv_cop_caps = kmalloc(sizeof(*hv_cop_caps), GFP_KERNEL); + if (!hv_cop_caps) { + rc = -ENOMEM; + goto out; + } + /* + * QOS capabilities available + */ + if (caps_all.feat_type & VAS_GZIP_QOS_FEAT_BIT) { + rc = get_vas_capabilities(VAS_GZIP_QOS_FEAT, + VAS_GZIP_QOS_FEAT_TYPE, hv_cop_caps); + + if (rc) + goto out_cop; + } + /* + * Default capabilities available + */ + if (caps_all.feat_type & VAS_GZIP_DEF_FEAT_BIT) { + rc = get_vas_capabilities(VAS_GZIP_DEF_FEAT, + VAS_GZIP_DEF_FEAT_TYPE, hv_cop_caps); + if (rc) + goto out_cop; + } + + pr_info("GZIP feature is available\n"); + +out_cop: + kfree(hv_cop_caps); +out: + kfree(hv_caps); + return rc; +} +machine_device_initcall(pseries, pseries_vas_init); diff --git a/arch/powerpc/platforms/pseries/vas.h b/arch/powerpc/platforms/pseries/vas.h new file mode 100644 index 000000000000..4ecb3fcabd10 --- /dev/null +++ b/arch/powerpc/platforms/pseries/vas.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2020-21 IBM Corp. + */ + +#ifndef _VAS_H +#define _VAS_H +#include +#include +#include + +/* + * VAS window modify flags + */ +#define VAS_MOD_WIN_CLOSE PPC_BIT(0) +#define VAS_MOD_WIN_JOBS_KILL PPC_BIT(1) +#define VAS_MOD_WIN_DR PPC_BIT(3) +#define VAS_MOD_WIN_PR PPC_BIT(4) +#define VAS_MOD_WIN_SF PPC_BIT(5) +#define VAS_MOD_WIN_TA PPC_BIT(6) +#define VAS_MOD_WIN_FLAGS (VAS_MOD_WIN_JOBS_KILL | VAS_MOD_WIN_DR | \ + VAS_MOD_WIN_PR | VAS_MOD_WIN_SF) + +#define VAS_WIN_ACTIVE 0x0 +#define VAS_WIN_CLOSED 0x1 +#define VAS_WIN_INACTIVE 0x2 /* Inactive due to HW failure */ +/* Process of being modified, deallocated, or quiesced */ +#define VAS_WIN_MOD_IN_PROCESS 0x3 + +#define VAS_COPY_PASTE_USER_MODE 0x00000001 +#define VAS_COP_OP_USER_MODE 0x00000010 + +/* + * Co-processor feature - GZIP QoS windows or GZIP default windows + */ +enum vas_cop_feat_type { + VAS_GZIP_QOS_FEAT_TYPE, + VAS_GZIP_DEF_FEAT_TYPE, + VAS_MAX_FEAT_TYPE, +}; + +/* + * Use to get feature specific capabilities from the + * hypervisor. + */ +struct hv_vas_cop_feat_caps { + __be64 descriptor; + u8 win_type; /* Default or QoS type */ + u8 user_mode; + __be16 max_lpar_creds; + __be16 max_win_creds; + union { + __be16 reserved; + __be16 def_lpar_creds; /* Used for default capabilities */ + }; + __be16 target_lpar_creds; +} __packed __aligned(0x1000); + +/* + * Feature specific (QoS or default) capabilities. + */ +struct vas_cop_feat_caps { + u64 descriptor; + u8 win_type; /* Default or QoS type */ + u8 user_mode; /* User mode copy/paste or COP HCALL */ + u16 max_lpar_creds; /* Max credits available in LPAR */ + /* Max credits can be assigned per window */ + u16 max_win_creds; + union { + u16 reserved; /* Used for QoS credit type */ + u16 def_lpar_creds; /* Used for default credit type */ + }; + /* Total LPAR available credits. Can be different from max LPAR */ + /* credits due to DLPAR operation */ + atomic_t target_lpar_creds; + atomic_t used_lpar_creds; /* Used credits so far */ + u16 avail_lpar_creds; /* Remaining available credits */ +}; + +/* + * Feature (QoS or Default) specific to store capabilities and + * the list of open windows. + */ +struct vas_caps { + struct vas_cop_feat_caps caps; + struct list_head list; /* List of open windows */ +}; + +/* + * To get window information from the hypervisor. + */ +struct hv_vas_win_lpar { + __be16 version; + u8 win_type; + u8 status; + __be16 credits; /* No of credits assigned to this window */ + __be16 reserved; + __be32 pid; /* LPAR Process ID */ + __be32 tid; /* LPAR Thread ID */ + __be64 win_addr; /* Paste address */ + __be32 interrupt; /* Interrupt when NX request completes */ + __be32 fault; /* Interrupt when NX sees fault */ + /* Associativity Domain Identifiers as returned in */ + /* H_HOME_NODE_ASSOCIATIVITY */ + __be64 domain[6]; + __be64 win_util; /* Number of bytes processed */ +} __packed __aligned(0x1000); + +struct pseries_vas_window { + struct vas_window vas_win; + u64 win_addr; /* Physical paste address */ + u8 win_type; /* QoS or Default window */ + u32 complete_irq; /* Completion interrupt */ + u32 fault_irq; /* Fault interrupt */ + u64 domain[6]; /* Associativity domain Ids */ + /* this window is allocated */ + u64 util; + + /* List of windows opened which is used for LPM */ + struct list_head win_list; + u64 flags; + char *name; + int fault_virq; +}; +#endif /* _VAS_H */ diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 69af73765783..b8f76f3fd994 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1072,7 +1072,7 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs) ret = get_kernel_nofault(inst, (void *)regs->nip); if (!ret && mcheck_handle_load(regs, inst)) { - regs->nip += 4; + regs_add_return_ip(regs, 4); return 1; } } diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 07c164f7f8cf..5a95b8ea23d8 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -108,8 +108,8 @@ int fsl_rio_mcheck_exception(struct pt_regs *regs) __func__); out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); - regs->msr |= MSR_RI; - regs->nip = extable_fixup(entry); + regs_set_return_msr(regs, regs->msr | MSR_RI); + regs_set_return_ip(regs, extable_fixup(entry)); return 1; } } diff --git a/arch/powerpc/sysdev/xics/Kconfig b/arch/powerpc/sysdev/xics/Kconfig index 304614c920aa..063d9195891f 100644 --- a/arch/powerpc/sysdev/xics/Kconfig +++ b/arch/powerpc/sysdev/xics/Kconfig @@ -12,3 +12,6 @@ config PPC_ICP_HV config PPC_ICS_RTAS def_bool n + +config PPC_ICS_NATIVE + def_bool n diff --git a/arch/powerpc/sysdev/xics/Makefile b/arch/powerpc/sysdev/xics/Makefile index ba1e3117b1c0..747063927c6c 100644 --- a/arch/powerpc/sysdev/xics/Makefile +++ b/arch/powerpc/sysdev/xics/Makefile @@ -4,4 +4,5 @@ obj-y += xics-common.o obj-$(CONFIG_PPC_ICP_NATIVE) += icp-native.o obj-$(CONFIG_PPC_ICP_HV) += icp-hv.o obj-$(CONFIG_PPC_ICS_RTAS) += ics-rtas.o +obj-$(CONFIG_PPC_ICS_NATIVE) += ics-native.o obj-$(CONFIG_PPC_POWERNV) += ics-opal.o icp-opal.o diff --git a/arch/powerpc/sysdev/xics/ics-native.c b/arch/powerpc/sysdev/xics/ics-native.c new file mode 100644 index 000000000000..d450502f4053 --- /dev/null +++ b/arch/powerpc/sysdev/xics/ics-native.c @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ICS backend for OPAL managed interrupts. + * + * Copyright 2011 IBM Corp. + */ + +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +struct ics_native { + struct ics ics; + struct device_node *node; + void __iomem *base; + u32 ibase; + u32 icount; +}; +#define to_ics_native(_ics) container_of(_ics, struct ics_native, ics) + +static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec) +{ + return in->base + 0x800 + ((vec - in->ibase) << 2); +} + +static void ics_native_unmask_irq(struct irq_data *d) +{ + unsigned int vec = (unsigned int)irqd_to_hwirq(d); + struct ics *ics = irq_data_get_irq_chip_data(d); + struct ics_native *in = to_ics_native(ics); + unsigned int server; + + pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return; + + server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); + out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY); +} + +static unsigned int ics_native_startup(struct irq_data *d) +{ +#ifdef CONFIG_PCI_MSI + /* + * The generic MSI code returns with the interrupt disabled on the + * card, using the MSI mask bits. Firmware doesn't appear to unmask + * at that level, so we do it here by hand. + */ + if (irq_data_get_msi_desc(d)) + pci_msi_unmask_irq(d); +#endif + + /* unmask it */ + ics_native_unmask_irq(d); + return 0; +} + +static void ics_native_do_mask(struct ics_native *in, unsigned int vec) +{ + out_be32(ics_native_xive(in, vec), 0xff); +} + +static void ics_native_mask_irq(struct irq_data *d) +{ + unsigned int vec = (unsigned int)irqd_to_hwirq(d); + struct ics *ics = irq_data_get_irq_chip_data(d); + struct ics_native *in = to_ics_native(ics); + + pr_devel("ics-native: mask virq %d [hw 0x%x]\n", d->irq, vec); + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return; + ics_native_do_mask(in, vec); +} + +static int ics_native_set_affinity(struct irq_data *d, + const struct cpumask *cpumask, + bool force) +{ + unsigned int vec = (unsigned int)irqd_to_hwirq(d); + struct ics *ics = irq_data_get_irq_chip_data(d); + struct ics_native *in = to_ics_native(ics); + int server; + u32 xive; + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return -EINVAL; + + server = xics_get_irq_server(d->irq, cpumask, 1); + if (server == -1) { + pr_warn("%s: No online cpus in the mask %*pb for irq %d\n", + __func__, cpumask_pr_args(cpumask), d->irq); + return -1; + } + + xive = in_be32(ics_native_xive(in, vec)); + xive = (xive & 0xff) | (server << 8); + out_be32(ics_native_xive(in, vec), xive); + + return IRQ_SET_MASK_OK; +} + +static struct irq_chip ics_native_irq_chip = { + .name = "ICS", + .irq_startup = ics_native_startup, + .irq_mask = ics_native_mask_irq, + .irq_unmask = ics_native_unmask_irq, + .irq_eoi = NULL, /* Patched at init time */ + .irq_set_affinity = ics_native_set_affinity, + .irq_set_type = xics_set_irq_type, + .irq_retrigger = xics_retrigger, +}; + +static int ics_native_map(struct ics *ics, unsigned int virq) +{ + unsigned int vec = (unsigned int)virq_to_hw(virq); + struct ics_native *in = to_ics_native(ics); + + pr_devel("%s: vec=0x%x\n", __func__, vec); + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return -EINVAL; + + irq_set_chip_and_handler(virq, &ics_native_irq_chip, handle_fasteoi_irq); + irq_set_chip_data(virq, ics); + + return 0; +} + +static void ics_native_mask_unknown(struct ics *ics, unsigned long vec) +{ + struct ics_native *in = to_ics_native(ics); + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return; + + ics_native_do_mask(in, vec); +} + +static long ics_native_get_server(struct ics *ics, unsigned long vec) +{ + struct ics_native *in = to_ics_native(ics); + u32 xive; + + if (vec < in->ibase || vec >= (in->ibase + in->icount)) + return -EINVAL; + + xive = in_be32(ics_native_xive(in, vec)); + return (xive >> 8) & 0xfff; +} + +static int ics_native_host_match(struct ics *ics, struct device_node *node) +{ + struct ics_native *in = to_ics_native(ics); + + return in->node == node; +} + +static struct ics ics_native_template = { + .map = ics_native_map, + .mask_unknown = ics_native_mask_unknown, + .get_server = ics_native_get_server, + .host_match = ics_native_host_match, +}; + +static int __init ics_native_add_one(struct device_node *np) +{ + struct ics_native *ics; + u32 ranges[2]; + int rc, count; + + ics = kzalloc(sizeof(struct ics_native), GFP_KERNEL); + if (!ics) + return -ENOMEM; + ics->node = of_node_get(np); + memcpy(&ics->ics, &ics_native_template, sizeof(struct ics)); + + ics->base = of_iomap(np, 0); + if (!ics->base) { + pr_err("Failed to map %pOFP\n", np); + rc = -ENOMEM; + goto fail; + } + + count = of_property_count_u32_elems(np, "interrupt-ranges"); + if (count < 2 || count & 1) { + pr_err("Failed to read interrupt-ranges of %pOFP\n", np); + rc = -EINVAL; + goto fail; + } + if (count > 2) { + pr_warn("ICS %pOFP has %d ranges, only one supported\n", + np, count >> 1); + } + rc = of_property_read_u32_array(np, "interrupt-ranges", + ranges, 2); + if (rc) { + pr_err("Failed to read interrupt-ranges of %pOFP\n", np); + goto fail; + } + ics->ibase = ranges[0]; + ics->icount = ranges[1]; + + pr_info("ICS native initialized for sources %d..%d\n", + ics->ibase, ics->ibase + ics->icount - 1); + + /* Register ourselves */ + xics_register_ics(&ics->ics); + + return 0; +fail: + of_node_put(ics->node); + kfree(ics); + return rc; +} + +int __init ics_native_init(void) +{ + struct device_node *ics; + bool found_one = false; + + /* We need to patch our irq chip's EOI to point to the + * right ICP + */ + ics_native_irq_chip.irq_eoi = icp_ops->eoi; + + /* Find native ICS in the device-tree */ + for_each_compatible_node(ics, NULL, "openpower,xics-sources") { + if (ics_native_add_one(ics) == 0) + found_one = true; + } + + if (found_one) + pr_info("ICS native backend registered\n"); + + return found_one ? 0 : -ENODEV; +} diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c index fdf8db4444b6..b14c502e56a8 100644 --- a/arch/powerpc/sysdev/xics/xics-common.c +++ b/arch/powerpc/sysdev/xics/xics-common.c @@ -476,6 +476,8 @@ void __init xics_init(void) rc = ics_rtas_init(); if (rc < 0) rc = ics_opal_init(); + if (rc < 0) + rc = ics_native_init(); if (rc < 0) pr_warn("XICS: Cannot find a Source Controller !\n"); diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 84de2d7c2f40..da4d7f225a40 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -70,6 +70,9 @@ static cpumask_t cpus_in_xmon = CPU_MASK_NONE; static unsigned long xmon_taken = 1; static int xmon_owner; static int xmon_gate; +static int xmon_batch; +static unsigned long xmon_batch_start_cpu; +static cpumask_t xmon_batch_cpus = CPU_MASK_NONE; #else #define xmon_owner 0 #endif /* CONFIG_SMP */ @@ -100,7 +103,7 @@ static long *xmon_fault_jmp[NR_CPUS]; /* Breakpoint stuff */ struct bpt { unsigned long address; - struct ppc_inst *instr; + u32 *instr; atomic_t ref_count; int enabled; unsigned long pad; @@ -133,6 +136,12 @@ static void prdump(unsigned long, long); static int ppc_inst_dump(unsigned long, long, int); static void dump_log_buf(void); +#ifdef CONFIG_SMP +static int xmon_switch_cpu(unsigned long); +static int xmon_batch_next_cpu(void); +static int batch_cmds(struct pt_regs *); +#endif + #ifdef CONFIG_PPC_POWERNV static void dump_opal_msglog(void); #else @@ -216,7 +225,8 @@ Commands:\n\ #ifdef CONFIG_SMP "\ c print cpus stopped in xmon\n\ - c# try to switch to cpu number h (in hex)\n" + c# try to switch to cpu number h (in hex)\n\ + c# $ run command '$' (one of 'r','S' or 't') on all cpus in xmon\n" #endif "\ C checksum\n\ @@ -489,10 +499,10 @@ static void xmon_touch_watchdogs(void) touch_nmi_watchdog(); } -static int xmon_core(struct pt_regs *regs, int fromipi) +static int xmon_core(struct pt_regs *regs, volatile int fromipi) { - int cmd = 0; - struct bpt *bp; + volatile int cmd = 0; + struct bpt *volatile bp; long recurse_jmp[JMP_BUF_LEN]; bool locked_down; unsigned long offset; @@ -514,7 +524,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi) bp = in_breakpoint_table(regs->nip, &offset); if (bp != NULL) { - regs->nip = bp->address + offset; + regs_set_return_ip(regs, bp->address + offset); atomic_dec(&bp->ref_count); } @@ -644,7 +654,12 @@ static int xmon_core(struct pt_regs *regs, int fromipi) spin_cpu_relax(); touch_nmi_watchdog(); } else { - if (!locked_down) + cmd = 1; +#ifdef CONFIG_SMP + if (xmon_batch) + cmd = batch_cmds(regs); +#endif + if (!locked_down && cmd) cmd = cmds(regs); if (locked_down || cmd != 0) { /* exiting xmon */ @@ -702,7 +717,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi) if (regs->msr & MSR_DE) { bp = at_breakpoint(regs->nip); if (bp != NULL) { - regs->nip = (unsigned long) &bp->instr[0]; + regs_set_return_ip(regs, (unsigned long) &bp->instr[0]); atomic_inc(&bp->ref_count); } } @@ -712,7 +727,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi) if (bp != NULL) { int stepped = emulate_step(regs, ppc_inst_read(bp->instr)); if (stepped == 0) { - regs->nip = (unsigned long) &bp->instr[0]; + regs_set_return_ip(regs, (unsigned long) &bp->instr[0]); atomic_inc(&bp->ref_count); } else if (stepped < 0) { printf("Couldn't single-step %s instruction\n", @@ -766,7 +781,7 @@ static int xmon_bpt(struct pt_regs *regs) /* Are we at the trap at bp->instr[1] for some bp? */ bp = in_breakpoint_table(regs->nip, &offset); if (bp != NULL && (offset == 4 || offset == 8)) { - regs->nip = bp->address + offset; + regs_set_return_ip(regs, bp->address + offset); atomic_dec(&bp->ref_count); return 1; } @@ -836,7 +851,7 @@ static int xmon_fault_handler(struct pt_regs *regs) if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { bp = in_breakpoint_table(regs->nip, &offset); if (bp != NULL) { - regs->nip = bp->address + offset; + regs_set_return_ip(regs, bp->address + offset); atomic_dec(&bp->ref_count); } } @@ -857,7 +872,7 @@ static inline void force_enable_xmon(void) static struct bpt *at_breakpoint(unsigned long pc) { int i; - struct bpt *bp; + struct bpt *volatile bp; bp = bpts; for (i = 0; i < NBPTS; ++i, ++bp) @@ -946,11 +961,11 @@ static void insert_bpts(void) } patch_instruction(bp->instr, instr); - patch_instruction(ppc_inst_next(bp->instr, &instr), + patch_instruction(ppc_inst_next(bp->instr, bp->instr), ppc_inst(bpinstr)); if (bp->enabled & BP_CIABR) continue; - if (patch_instruction((struct ppc_inst *)bp->address, + if (patch_instruction((u32 *)bp->address, ppc_inst(bpinstr)) != 0) { printf("Couldn't write instruction at %lx, " "disabling breakpoint there\n", bp->address); @@ -992,7 +1007,7 @@ static void remove_bpts(void) if (mread_instr(bp->address, &instr) && ppc_inst_equal(instr, ppc_inst(bpinstr)) && patch_instruction( - (struct ppc_inst *)bp->address, ppc_inst_read(bp->instr)) != 0) + (u32 *)bp->address, ppc_inst_read(bp->instr)) != 0) printf("Couldn't remove breakpoint at %lx\n", bp->address); } @@ -1188,7 +1203,7 @@ cmds(struct pt_regs *excp) #ifdef CONFIG_BOOKE static int do_step(struct pt_regs *regs) { - regs->msr |= MSR_DE; + regs_set_return_msr(regs, regs->msr | MSR_DE); mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM); return 1; } @@ -1221,7 +1236,7 @@ static int do_step(struct pt_regs *regs) } } } - regs->msr |= MSR_SE; + regs_set_return_msr(regs, regs->msr | MSR_SE); return 1; } #endif @@ -1243,11 +1258,112 @@ static void bootcmds(void) } } +#ifdef CONFIG_SMP +static int xmon_switch_cpu(unsigned long cpu) +{ + int timeout; + + xmon_taken = 0; + mb(); + xmon_owner = cpu; + timeout = 10000000; + while (!xmon_taken) { + if (--timeout == 0) { + if (test_and_set_bit(0, &xmon_taken)) + break; + /* take control back */ + mb(); + xmon_owner = smp_processor_id(); + printf("cpu 0x%lx didn't take control\n", cpu); + return 0; + } + barrier(); + } + return 1; +} + +static int xmon_batch_next_cpu(void) +{ + unsigned long cpu; + + while (!cpumask_empty(&xmon_batch_cpus)) { + cpu = cpumask_next_wrap(smp_processor_id(), &xmon_batch_cpus, + xmon_batch_start_cpu, true); + if (cpu == nr_cpumask_bits) + break; + if (xmon_batch_start_cpu == -1) + xmon_batch_start_cpu = cpu; + if (xmon_switch_cpu(cpu)) + return 0; + cpumask_clear_cpu(cpu, &xmon_batch_cpus); + } + + xmon_batch = 0; + printf("%x:mon> \n", smp_processor_id()); + return 1; +} + +static int batch_cmds(struct pt_regs *excp) +{ + int cmd; + + /* simulate command entry */ + cmd = xmon_batch; + termch = '\n'; + + last_cmd = NULL; + xmon_regs = excp; + + printf("%x:", smp_processor_id()); + printf("mon> "); + printf("%c\n", (char)cmd); + + switch (cmd) { + case 'r': + prregs(excp); /* print regs */ + break; + case 'S': + super_regs(); + break; + case 't': + backtrace(excp); + break; + } + + cpumask_clear_cpu(smp_processor_id(), &xmon_batch_cpus); + + return xmon_batch_next_cpu(); +} + static int cpu_cmd(void) { -#ifdef CONFIG_SMP unsigned long cpu, first_cpu, last_cpu; - int timeout; + + cpu = skipbl(); + if (cpu == '#') { + xmon_batch = skipbl(); + if (xmon_batch) { + switch (xmon_batch) { + case 'r': + case 'S': + case 't': + cpumask_copy(&xmon_batch_cpus, &cpus_in_xmon); + if (cpumask_weight(&xmon_batch_cpus) <= 1) { + printf("There are no other cpus in xmon\n"); + break; + } + xmon_batch_start_cpu = -1; + if (!xmon_batch_next_cpu()) + return 1; + break; + default: + printf("c# only supports 'r', 'S' and 't' commands\n"); + } + xmon_batch = 0; + return 0; + } + } + termch = cpu; if (!scanhex(&cpu)) { /* print cpus waiting or in xmon */ @@ -1279,27 +1395,15 @@ static int cpu_cmd(void) #endif return 0; } - xmon_taken = 0; - mb(); - xmon_owner = cpu; - timeout = 10000000; - while (!xmon_taken) { - if (--timeout == 0) { - if (test_and_set_bit(0, &xmon_taken)) - break; - /* take control back */ - mb(); - xmon_owner = smp_processor_id(); - printf("cpu 0x%lx didn't take control\n", cpu); - return 0; - } - barrier(); - } - return 1; -#else - return 0; -#endif /* CONFIG_SMP */ + + return xmon_switch_cpu(cpu); } +#else +static int cpu_cmd(void) +{ + return 0; +} +#endif /* CONFIG_SMP */ static unsigned short fcstab[256] = { 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, @@ -2214,7 +2318,7 @@ mread_instr(unsigned long adrs, struct ppc_inst *instr) if (setjmp(bus_error_jmp) == 0) { catch_memory_errors = 1; sync(); - *instr = ppc_inst_read((struct ppc_inst *)adrs); + *instr = ppc_inst_read((u32 *)adrs); sync(); /* wait a little while to see if we get a machine check */ __delay(200); @@ -2975,7 +3079,7 @@ static void dump_log_buf(void) { struct kmsg_dump_iter iter; - unsigned char buf[128]; + static unsigned char buf[1024]; size_t len; if (setjmp(bus_error_jmp) != 0) { @@ -3005,7 +3109,7 @@ static void dump_opal_msglog(void) { unsigned char buf[128]; ssize_t res; - loff_t pos = 0; + volatile loff_t pos = 0; if (!firmware_has_feature(FW_FEATURE_OPAL)) { printf("Machine is not running OPAL firmware.\n"); @@ -3160,7 +3264,7 @@ memzcan(void) printf("%.8lx\n", a - mskip); } -static void show_task(struct task_struct *tsk) +static void show_task(struct task_struct *volatile tsk) { unsigned int p_state = READ_ONCE(tsk->__state); char state; @@ -3205,7 +3309,7 @@ static void format_pte(void *ptep, unsigned long pte) static void show_pte(unsigned long addr) { unsigned long tskv = 0; - struct task_struct *tsk = NULL; + struct task_struct *volatile tsk = NULL; struct mm_struct *mm; pgd_t *pgdp; p4d_t *p4dp; @@ -3300,7 +3404,7 @@ static void show_pte(unsigned long addr) static void show_tasks(void) { unsigned long tskv; - struct task_struct *tsk = NULL; + struct task_struct *volatile tsk = NULL; printf(" task_struct ->thread.ksp ->thread.regs PID PPID S P CMD\n"); @@ -3623,7 +3727,7 @@ static void xmon_print_symbol(unsigned long address, const char *mid, const char *after) { char *modname; - const char *name = NULL; + const char *volatile name = NULL; unsigned long offset, size; printf(REG, address); @@ -4055,7 +4159,7 @@ void xmon_register_spus(struct list_head *list) static void stop_spus(void) { struct spu *spu; - int i; + volatile int i; u64 tmp; for (i = 0; i < XMON_NUM_SPUS; i++) { @@ -4096,7 +4200,7 @@ static void stop_spus(void) static void restart_spus(void) { struct spu *spu; - int i; + volatile int i; for (i = 0; i < XMON_NUM_SPUS; i++) { if (!spu_info[i].spu) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 15f9490a7aad..469a70bd8da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -104,6 +104,7 @@ config RISCV select SYSCTL_EXCEPTION_TRACE select THREAD_INFO_IN_TASK select UACCESS_MEMCPY if !MMU + select ZONE_DMA32 if 64BIT config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT @@ -133,10 +134,6 @@ config MMU Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'. -config ZONE_DMA32 - bool - default y if 64BIT - config VA_BITS int default 32 if 32BIT diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h index 23b1544e0ca5..0af6933a7100 100644 --- a/arch/riscv/include/asm/pgalloc.h +++ b/arch/riscv/include/asm/pgalloc.h @@ -38,8 +38,6 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) } #endif /* __PAGETABLE_PMD_FOLDED */ -#define pmd_pgtable(pmd) pmd_page(pmd) - static inline pgd_t *pgd_alloc(struct mm_struct *mm) { pgd_t *pgd; diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 380cd3a7e548..62f3fe7368f3 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -536,8 +536,6 @@ void setup_bootmem(void); void paging_init(void); void misc_mem_init(void); -#define FIRST_USER_ADDRESS 0 - /* * ZERO_PAGE is a global shared page that is always zero, * used for zero-mapped memory areas, etc. diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index a49971647f81..07b2328f29e0 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -2,9 +2,6 @@ config MMU def_bool y -config ZONE_DMA - def_bool y - config CPU_BIG_ENDIAN def_bool y @@ -62,7 +59,7 @@ config S390 select ARCH_BINFMT_ELF_STATE select ARCH_ENABLE_MEMORY_HOTPLUG if SPARSEMEM select ARCH_ENABLE_MEMORY_HOTREMOVE - select ARCH_ENABLE_SPLIT_PMD_PTLOCK + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 select ARCH_HAS_DEBUG_VM_PGTABLE select ARCH_HAS_DEBUG_WX select ARCH_HAS_DEVMEM_IS_ALLOWED @@ -165,6 +162,7 @@ config S390 select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO + select HAVE_IOREMAP_PROT if PCI select HAVE_IRQ_EXIT_ON_IRQ_STACK select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_GZIP @@ -173,6 +171,7 @@ config S390 select HAVE_KERNEL_LZO select HAVE_KERNEL_UNCOMPRESSED select HAVE_KERNEL_XZ + select HAVE_KERNEL_ZSTD select HAVE_KPROBES select HAVE_KPROBES_ON_FTRACE select HAVE_KRETPROBES @@ -211,6 +210,7 @@ config S390 select THREAD_INFO_IN_TASK select TTY select VIRT_CPU_ACCOUNTING + select ZONE_DMA # Note: keep the above list sorted alphabetically config SCHED_OMIT_FRAME_POINTER @@ -769,7 +769,7 @@ config VFIO_CCW config VFIO_AP def_tristate n prompt "VFIO support for AP devices" - depends on S390_AP_IOMMU && VFIO_MDEV_DEVICE && KVM + depends on S390_AP_IOMMU && VFIO_MDEV && KVM depends on ZCRYPT help This driver grants access to Adjunct Processor (AP) devices @@ -854,7 +854,7 @@ config CMM_IUCV config APPLDATA_BASE def_bool n prompt "Linux - VM Monitor Stream, base infrastructure" - depends on PROC_FS + depends on PROC_SYSCTL help This provides a kernel interface for creating and updating z/VM APPLDATA monitor records. The monitor records are updated at certain time diff --git a/arch/s390/Makefile b/arch/s390/Makefile index e443ed9947bd..098abe3a56f3 100644 --- a/arch/s390/Makefile +++ b/arch/s390/Makefile @@ -28,6 +28,7 @@ KBUILD_CFLAGS_DECOMPRESSOR += -DDISABLE_BRANCH_PROFILING -D__NO_FORTIFY KBUILD_CFLAGS_DECOMPRESSOR += -fno-delete-null-pointer-checks -msoft-float -mbackchain KBUILD_CFLAGS_DECOMPRESSOR += -fno-asynchronous-unwind-tables KBUILD_CFLAGS_DECOMPRESSOR += -ffreestanding +KBUILD_CFLAGS_DECOMPRESSOR += -fno-stack-protector KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-disable-warning, address-of-packed-member) KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO),-g) KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO_DWARF4), $(call cc-option, -gdwarf-4,)) diff --git a/arch/s390/boot/als.c b/arch/s390/boot/als.c index ff6801d401c4..47c48fbfb563 100644 --- a/arch/s390/boot/als.c +++ b/arch/s390/boot/als.c @@ -68,7 +68,7 @@ void print_missing_facilities(void) first = 1; for (i = 0; i < ARRAY_SIZE(als); i++) { - val = ~S390_lowcore.stfle_fac_list[i] & als[i]; + val = ~stfle_fac_list[i] & als[i]; for (j = 0; j < BITS_PER_LONG; j++) { if (!(val & (1UL << (BITS_PER_LONG - 1 - j)))) continue; @@ -106,9 +106,9 @@ void verify_facilities(void) { int i; - __stfle(S390_lowcore.stfle_fac_list, ARRAY_SIZE(S390_lowcore.stfle_fac_list)); + __stfle(stfle_fac_list, ARRAY_SIZE(stfle_fac_list)); for (i = 0; i < ARRAY_SIZE(als); i++) { - if ((S390_lowcore.stfle_fac_list[i] & als[i]) != als[i]) + if ((stfle_fac_list[i] & als[i]) != als[i]) facility_mismatch(); } } diff --git a/arch/s390/boot/boot.h b/arch/s390/boot/boot.h index 8b50967f5804..ae04e1c93764 100644 --- a/arch/s390/boot/boot.h +++ b/arch/s390/boot/boot.h @@ -24,6 +24,7 @@ void __printf(1, 2) decompressor_printk(const char *fmt, ...); extern const char kernel_version[]; extern unsigned long memory_limit; +extern unsigned long vmalloc_size; extern int vmalloc_size_set; extern int kaslr_enabled; diff --git a/arch/s390/boot/compressed/Makefile b/arch/s390/boot/compressed/Makefile index de18dab518bb..660c799d875d 100644 --- a/arch/s390/boot/compressed/Makefile +++ b/arch/s390/boot/compressed/Makefile @@ -14,6 +14,7 @@ obj-y := $(if $(CONFIG_KERNEL_UNCOMPRESSED),,decompressor.o) info.o obj-all := $(obj-y) piggy.o syms.o targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4 +targets += vmlinux.bin.zst targets += info.bin syms.bin vmlinux.syms $(obj-all) KBUILD_AFLAGS := $(KBUILD_AFLAGS_DECOMPRESSOR) @@ -33,7 +34,7 @@ $(obj)/vmlinux.syms: $(obj)/vmlinux.lds $(objtree)/arch/s390/boot/startup.a $(OB quiet_cmd_dumpsyms = DUMPSYMS $< define cmd_dumpsyms - $(NM) -n -S --format=bsd "$<" | $(PERL) -ne '/(\w+)\s+(\w+)\s+[tT]\s+(\w+)/ and printf "%x %x %s\0",hex $$1,hex $$2,$$3' > "$@" + $(NM) -n -S --format=bsd "$<" | sed -nE 's/^0*([0-9a-fA-F]+) 0*([0-9a-fA-F]+) [tT] ([^ ]*)$$/\1 \2 \3/p' | tr '\n' '\0' > "$@" endef $(obj)/syms.bin: $(obj)/vmlinux.syms FORCE @@ -63,6 +64,7 @@ suffix-$(CONFIG_KERNEL_LZ4) := .lz4 suffix-$(CONFIG_KERNEL_LZMA) := .lzma suffix-$(CONFIG_KERNEL_LZO) := .lzo suffix-$(CONFIG_KERNEL_XZ) := .xz +suffix-$(CONFIG_KERNEL_ZSTD) := .zst $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) @@ -76,6 +78,8 @@ $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE $(call if_changed,lzo) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE $(call if_changed,xzkern) +$(obj)/vmlinux.bin.zst: $(vmlinux.bin.all-y) FORCE + $(call if_changed,zstd22) OBJCOPYFLAGS_piggy.o := -I binary -O elf64-s390 -B s390:64-bit --rename-section .data=.vmlinux.bin.compressed $(obj)/piggy.o: $(obj)/vmlinux.bin$(suffix-y) FORCE diff --git a/arch/s390/boot/compressed/decompressor.c b/arch/s390/boot/compressed/decompressor.c index 3061b11c4d27..37a4a8d33c6c 100644 --- a/arch/s390/boot/compressed/decompressor.c +++ b/arch/s390/boot/compressed/decompressor.c @@ -28,8 +28,10 @@ extern char _end[]; extern unsigned char _compressed_start[]; extern unsigned char _compressed_end[]; -#ifdef CONFIG_HAVE_KERNEL_BZIP2 +#ifdef CONFIG_KERNEL_BZIP2 #define BOOT_HEAP_SIZE 0x400000 +#elif CONFIG_KERNEL_ZSTD +#define BOOT_HEAP_SIZE 0x30000 #else #define BOOT_HEAP_SIZE 0x10000 #endif @@ -61,6 +63,10 @@ static unsigned long free_mem_end_ptr = (unsigned long) _end + BOOT_HEAP_SIZE; #include "../../../../lib/decompress_unxz.c" #endif +#ifdef CONFIG_KERNEL_ZSTD +#include "../../../../lib/decompress_unzstd.c" +#endif + #define decompress_offset ALIGN((unsigned long)_end + BOOT_HEAP_SIZE, PAGE_SIZE) unsigned long mem_safe_offset(void) diff --git a/arch/s390/boot/head.S b/arch/s390/boot/head.S index dacb7813f982..51693cfb65c2 100644 --- a/arch/s390/boot/head.S +++ b/arch/s390/boot/head.S @@ -401,6 +401,7 @@ SYM_CODE_END(startup_pgm_check_handler) # Must be keept in sync with struct parmarea in setup.h # .org PARMAREA +SYM_DATA_START(parmarea) .quad 0 # IPL_DEVICE .quad 0 # INITRD_START .quad 0 # INITRD_SIZE @@ -411,6 +412,8 @@ SYM_CODE_END(startup_pgm_check_handler) .org COMMAND_LINE .byte "root=/dev/ram0 ro" .byte 0 + .org PARMAREA+__PARMAREA_SIZE +SYM_DATA_END(parmarea) .org EARLY_SCCB_OFFSET .fill 4096 diff --git a/arch/s390/boot/ipl_parm.c b/arch/s390/boot/ipl_parm.c index d372a45fe10e..0f84c072625e 100644 --- a/arch/s390/boot/ipl_parm.c +++ b/arch/s390/boot/ipl_parm.c @@ -12,39 +12,44 @@ #include "boot.h" char __bootdata(early_command_line)[COMMAND_LINE_SIZE]; -struct ipl_parameter_block __bootdata_preserved(ipl_block); -int __bootdata_preserved(ipl_block_valid); -unsigned int __bootdata_preserved(zlib_dfltcc_support) = ZLIB_DFLTCC_FULL; - -unsigned long __bootdata(vmalloc_size) = VMALLOC_DEFAULT_SIZE; int __bootdata(noexec_disabled); +unsigned int __bootdata_preserved(zlib_dfltcc_support) = ZLIB_DFLTCC_FULL; +struct ipl_parameter_block __bootdata_preserved(ipl_block); +int __bootdata_preserved(ipl_block_valid); + +unsigned long vmalloc_size = VMALLOC_DEFAULT_SIZE; unsigned long memory_limit; int vmalloc_size_set; int kaslr_enabled; static inline int __diag308(unsigned long subcode, void *addr) { - register unsigned long _addr asm("0") = (unsigned long)addr; - register unsigned long _rc asm("1") = 0; unsigned long reg1, reg2; - psw_t old = S390_lowcore.program_new_psw; + union register_pair r1; + psw_t old; + r1.even = (unsigned long) addr; + r1.odd = 0; asm volatile( - " epsw %0,%1\n" - " st %0,%[psw_pgm]\n" - " st %1,%[psw_pgm]+4\n" - " larl %0,1f\n" - " stg %0,%[psw_pgm]+8\n" - " diag %[addr],%[subcode],0x308\n" - "1: nopr %%r7\n" - : "=&d" (reg1), "=&a" (reg2), - [psw_pgm] "=Q" (S390_lowcore.program_new_psw), - [addr] "+d" (_addr), "+d" (_rc) - : [subcode] "d" (subcode) + " mvc 0(16,%[psw_old]),0(%[psw_pgm])\n" + " epsw %[reg1],%[reg2]\n" + " st %[reg1],0(%[psw_pgm])\n" + " st %[reg2],4(%[psw_pgm])\n" + " larl %[reg1],1f\n" + " stg %[reg1],8(%[psw_pgm])\n" + " diag %[r1],%[subcode],0x308\n" + "1: mvc 0(16,%[psw_pgm]),0(%[psw_old])\n" + : [r1] "+&d" (r1.pair), + [reg1] "=&d" (reg1), + [reg2] "=&a" (reg2), + "+Q" (S390_lowcore.program_new_psw), + "=Q" (old) + : [subcode] "d" (subcode), + [psw_old] "a" (&old), + [psw_pgm] "a" (&S390_lowcore.program_new_psw) : "cc", "memory"); - S390_lowcore.program_new_psw = old; - return _rc; + return r1.odd; } void store_ipl_parmblock(void) @@ -165,12 +170,12 @@ static inline int has_ebcdic_char(const char *str) void setup_boot_command_line(void) { - COMMAND_LINE[ARCH_COMMAND_LINE_SIZE - 1] = 0; + parmarea.command_line[ARCH_COMMAND_LINE_SIZE - 1] = 0; /* convert arch command line to ascii if necessary */ - if (has_ebcdic_char(COMMAND_LINE)) - EBCASC(COMMAND_LINE, ARCH_COMMAND_LINE_SIZE); + if (has_ebcdic_char(parmarea.command_line)) + EBCASC(parmarea.command_line, ARCH_COMMAND_LINE_SIZE); /* copy arch command line */ - strcpy(early_command_line, strim(COMMAND_LINE)); + strcpy(early_command_line, strim(parmarea.command_line)); /* append IPL PARM data to the boot command line */ if (!is_prot_virt_guest() && ipl_block_valid) @@ -180,9 +185,9 @@ void setup_boot_command_line(void) static void modify_facility(unsigned long nr, bool clear) { if (clear) - __clear_facility(nr, S390_lowcore.stfle_fac_list); + __clear_facility(nr, stfle_fac_list); else - __set_facility(nr, S390_lowcore.stfle_fac_list); + __set_facility(nr, stfle_fac_list); } static void check_cleared_facilities(void) @@ -191,7 +196,7 @@ static void check_cleared_facilities(void) int i; for (i = 0; i < ARRAY_SIZE(als); i++) { - if ((S390_lowcore.stfle_fac_list[i] & als[i]) != als[i]) { + if ((stfle_fac_list[i] & als[i]) != als[i]) { sclp_early_printk("Warning: The Linux kernel requires facilities cleared via command line option\n"); print_missing_facilities(); break; diff --git a/arch/s390/boot/mem_detect.c b/arch/s390/boot/mem_detect.c index 40168e59abd3..4e17adbde495 100644 --- a/arch/s390/boot/mem_detect.c +++ b/arch/s390/boot/mem_detect.c @@ -64,30 +64,37 @@ void add_mem_detect_block(u64 start, u64 end) static int __diag260(unsigned long rx1, unsigned long rx2) { - register unsigned long _rx1 asm("2") = rx1; - register unsigned long _rx2 asm("3") = rx2; - register unsigned long _ry asm("4") = 0x10; /* storage configuration */ - int rc = -1; /* fail */ - unsigned long reg1, reg2; - psw_t old = S390_lowcore.program_new_psw; + unsigned long reg1, reg2, ry; + union register_pair rx; + psw_t old; + int rc; + rx.even = rx1; + rx.odd = rx2; + ry = 0x10; /* storage configuration */ + rc = -1; /* fail */ asm volatile( - " epsw %0,%1\n" - " st %0,%[psw_pgm]\n" - " st %1,%[psw_pgm]+4\n" - " larl %0,1f\n" - " stg %0,%[psw_pgm]+8\n" + " mvc 0(16,%[psw_old]),0(%[psw_pgm])\n" + " epsw %[reg1],%[reg2]\n" + " st %[reg1],0(%[psw_pgm])\n" + " st %[reg2],4(%[psw_pgm])\n" + " larl %[reg1],1f\n" + " stg %[reg1],8(%[psw_pgm])\n" " diag %[rx],%[ry],0x260\n" " ipm %[rc]\n" " srl %[rc],28\n" - "1:\n" - : "=&d" (reg1), "=&a" (reg2), - [psw_pgm] "=Q" (S390_lowcore.program_new_psw), - [rc] "+&d" (rc), [ry] "+d" (_ry) - : [rx] "d" (_rx1), "d" (_rx2) + "1: mvc 0(16,%[psw_pgm]),0(%[psw_old])\n" + : [reg1] "=&d" (reg1), + [reg2] "=&a" (reg2), + [rc] "+&d" (rc), + [ry] "+&d" (ry), + "+Q" (S390_lowcore.program_new_psw), + "=Q" (old) + : [rx] "d" (rx.pair), + [psw_old] "a" (&old), + [psw_pgm] "a" (&S390_lowcore.program_new_psw) : "cc", "memory"); - S390_lowcore.program_new_psw = old; - return rc == 0 ? _ry : -1; + return rc == 0 ? ry : -1; } static int diag260(void) @@ -111,24 +118,30 @@ static int diag260(void) static int tprot(unsigned long addr) { - unsigned long pgm_addr; + unsigned long reg1, reg2; int rc = -EFAULT; - psw_t old = S390_lowcore.program_new_psw; + psw_t old; - S390_lowcore.program_new_psw.mask = __extract_psw(); asm volatile( - " larl %[pgm_addr],1f\n" - " stg %[pgm_addr],%[psw_pgm_addr]\n" + " mvc 0(16,%[psw_old]),0(%[psw_pgm])\n" + " epsw %[reg1],%[reg2]\n" + " st %[reg1],0(%[psw_pgm])\n" + " st %[reg2],4(%[psw_pgm])\n" + " larl %[reg1],1f\n" + " stg %[reg1],8(%[psw_pgm])\n" " tprot 0(%[addr]),0\n" " ipm %[rc]\n" " srl %[rc],28\n" - "1:\n" - : [pgm_addr] "=&d"(pgm_addr), - [psw_pgm_addr] "=Q"(S390_lowcore.program_new_psw.addr), - [rc] "+&d"(rc) - : [addr] "a"(addr) + "1: mvc 0(16,%[psw_pgm]),0(%[psw_old])\n" + : [reg1] "=&d" (reg1), + [reg2] "=&a" (reg2), + [rc] "+&d" (rc), + "=Q" (S390_lowcore.program_new_psw.addr), + "=Q" (old) + : [psw_old] "a" (&old), + [psw_pgm] "a" (&S390_lowcore.program_new_psw), + [addr] "a" (addr) : "cc", "memory"); - S390_lowcore.program_new_psw = old; return rc; } diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 05f8eefa3dcf..bbe4df6c2f8b 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -15,8 +16,17 @@ extern char __boot_data_start[], __boot_data_end[]; extern char __boot_data_preserved_start[], __boot_data_preserved_end[]; unsigned long __bootdata_preserved(__kaslr_offset); +unsigned long __bootdata_preserved(VMALLOC_START); +unsigned long __bootdata_preserved(VMALLOC_END); +struct page *__bootdata_preserved(vmemmap); +unsigned long __bootdata_preserved(vmemmap_size); +unsigned long __bootdata_preserved(MODULES_VADDR); +unsigned long __bootdata_preserved(MODULES_END); unsigned long __bootdata(ident_map_size); +u64 __bootdata_preserved(stfle_fac_list[16]); +u64 __bootdata_preserved(alt_stfle_fac_list[16]); + /* * Some code and data needs to stay below 2 GB, even when the kernel would be * relocated above 2 GB, because it has to use 31 bit addresses. @@ -169,6 +179,86 @@ static void setup_ident_map_size(unsigned long max_physmem_end) #endif } +static void setup_kernel_memory_layout(void) +{ + bool vmalloc_size_verified = false; + unsigned long vmemmap_off; + unsigned long vspace_left; + unsigned long rte_size; + unsigned long pages; + unsigned long vmax; + + pages = ident_map_size / PAGE_SIZE; + /* vmemmap contains a multiple of PAGES_PER_SECTION struct pages */ + vmemmap_size = SECTION_ALIGN_UP(pages) * sizeof(struct page); + + /* choose kernel address space layout: 4 or 3 levels. */ + vmemmap_off = round_up(ident_map_size, _REGION3_SIZE); + if (IS_ENABLED(CONFIG_KASAN) || + vmalloc_size > _REGION2_SIZE || + vmemmap_off + vmemmap_size + vmalloc_size + MODULES_LEN > _REGION2_SIZE) + vmax = _REGION1_SIZE; + else + vmax = _REGION2_SIZE; + + /* keep vmemmap_off aligned to a top level region table entry */ + rte_size = vmax == _REGION1_SIZE ? _REGION2_SIZE : _REGION3_SIZE; + MODULES_END = vmax; + if (is_prot_virt_host()) { + /* + * forcing modules and vmalloc area under the ultravisor + * secure storage limit, so that any vmalloc allocation + * we do could be used to back secure guest storage. + */ + adjust_to_uv_max(&MODULES_END); + } + +#ifdef CONFIG_KASAN + if (MODULES_END < vmax) { + /* force vmalloc and modules below kasan shadow */ + MODULES_END = min(MODULES_END, KASAN_SHADOW_START); + } else { + /* + * leave vmalloc and modules above kasan shadow but make + * sure they don't overlap with it + */ + vmalloc_size = min(vmalloc_size, vmax - KASAN_SHADOW_END - MODULES_LEN); + vmalloc_size_verified = true; + vspace_left = KASAN_SHADOW_START; + } +#endif + MODULES_VADDR = MODULES_END - MODULES_LEN; + VMALLOC_END = MODULES_VADDR; + + if (vmalloc_size_verified) { + VMALLOC_START = VMALLOC_END - vmalloc_size; + } else { + vmemmap_off = round_up(ident_map_size, rte_size); + + if (vmemmap_off + vmemmap_size > VMALLOC_END || + vmalloc_size > VMALLOC_END - vmemmap_off - vmemmap_size) { + /* + * allow vmalloc area to occupy up to 1/2 of + * the rest virtual space left. + */ + vmalloc_size = min(vmalloc_size, VMALLOC_END / 2); + } + VMALLOC_START = VMALLOC_END - vmalloc_size; + vspace_left = VMALLOC_START; + } + + pages = vspace_left / (PAGE_SIZE + sizeof(struct page)); + pages = SECTION_ALIGN_UP(pages); + vmemmap_off = round_up(vspace_left - pages * sizeof(struct page), rte_size); + /* keep vmemmap left most starting from a fresh region table entry */ + vmemmap_off = min(vmemmap_off, round_up(ident_map_size, rte_size)); + /* take care that identity map is lower then vmemmap */ + ident_map_size = min(ident_map_size, vmemmap_off); + vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); + VMALLOC_START = max(vmemmap_off + vmemmap_size, VMALLOC_START); + vmemmap = (struct page *)vmemmap_off; +} + /* * This function clears the BSS section of the decompressed Linux kernel and NOT the decompressor's. */ @@ -208,6 +298,7 @@ void startup_kernel(void) parse_boot_command_line(); setup_ident_map_size(detect_memory()); setup_vmalloc_size(); + setup_kernel_memory_layout(); random_lma = __kaslr_offset = 0; if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_enabled) { diff --git a/arch/s390/boot/uv.c b/arch/s390/boot/uv.c index 87641dd65ccf..82b99b916243 100644 --- a/arch/s390/boot/uv.c +++ b/arch/s390/boot/uv.c @@ -44,3 +44,28 @@ void uv_query_info(void) prot_virt_guest = 1; #endif } + +#if IS_ENABLED(CONFIG_KVM) +static bool has_uv_sec_stor_limit(void) +{ + /* + * keep these conditions in line with setup_uv() + */ + if (!is_prot_virt_host()) + return false; + + if (is_prot_virt_guest()) + return false; + + if (!test_facility(158)) + return false; + + return !!uv_info.max_sec_stor_addr; +} + +void adjust_to_uv_max(unsigned long *vmax) +{ + if (has_uv_sec_stor_limit()) + *vmax = min_t(unsigned long, *vmax, uv_info.max_sec_stor_addr); +} +#endif diff --git a/arch/s390/hypfs/hypfs_sprp.c b/arch/s390/hypfs/hypfs_sprp.c index 7d9fb496d155..f5f7e78ddc0c 100644 --- a/arch/s390/hypfs/hypfs_sprp.c +++ b/arch/s390/hypfs/hypfs_sprp.c @@ -25,14 +25,13 @@ static inline unsigned long __hypfs_sprp_diag304(void *data, unsigned long cmd) { - register unsigned long _data asm("2") = (unsigned long) data; - register unsigned long _rc asm("3"); - register unsigned long _cmd asm("4") = cmd; + union register_pair r1 = { .even = (unsigned long)data, }; - asm volatile("diag %1,%2,0x304\n" - : "=d" (_rc) : "d" (_data), "d" (_cmd) : "memory"); - - return _rc; + asm volatile("diag %[r1],%[r3],0x304\n" + : [r1] "+&d" (r1.pair) + : [r3] "d" (cmd) + : "memory"); + return r1.odd; } static unsigned long hypfs_sprp_diag304(void *data, unsigned long cmd) diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index 68da67d2c4c9..fd149480b6e2 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -299,13 +299,13 @@ static inline unsigned char __flogr(unsigned long word) } return bit; } else { - register unsigned long bit asm("4") = word; - register unsigned long out asm("5"); + union register_pair rp; + rp.even = word; asm volatile( - " flogr %[bit],%[bit]\n" - : [bit] "+d" (bit), [out] "=d" (out) : : "cc"); - return bit; + " flogr %[rp],%[rp]\n" + : [rp] "+d" (rp.pair) : : "cc"); + return rp.even; } } diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h index ad3acb1e882b..20f169b6db4e 100644 --- a/arch/s390/include/asm/ccwgroup.h +++ b/arch/s390/include/asm/ccwgroup.h @@ -11,8 +11,7 @@ struct ccw_driver; * @count: number of attached slave devices * @dev: embedded device structure * @cdev: variable number of slave devices, allocated as needed - * @ungroup_work: work to be done when a ccwgroup notifier has action - * type %BUS_NOTIFY_UNBIND_DRIVER + * @ungroup_work: used to ungroup the ccwgroup device */ struct ccwgroup_device { enum { diff --git a/arch/s390/include/asm/checksum.h b/arch/s390/include/asm/checksum.h index a8c02cfbc712..cdd19d326345 100644 --- a/arch/s390/include/asm/checksum.h +++ b/arch/s390/include/asm/checksum.h @@ -29,13 +29,15 @@ */ static inline __wsum csum_partial(const void *buff, int len, __wsum sum) { - register unsigned long reg2 asm("2") = (unsigned long) buff; - register unsigned long reg3 asm("3") = (unsigned long) len; + union register_pair rp = { + .even = (unsigned long) buff, + .odd = (unsigned long) len, + }; asm volatile( - "0: cksm %0,%1\n" /* do checksum on longs */ + "0: cksm %[sum],%[rp]\n" " jo 0b\n" - : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); + : [sum] "+&d" (sum), [rp] "+&d" (rp.pair) : : "cc", "memory"); return sum; } diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h index ac02df906cae..f58c92f28701 100644 --- a/arch/s390/include/asm/cio.h +++ b/arch/s390/include/asm/cio.h @@ -9,6 +9,7 @@ #include #include #include +#include #define LPM_ANYPATH 0xff #define __MAX_CSSID 0 diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h index 1960a7295ae5..84c3f0d576c5 100644 --- a/arch/s390/include/asm/cmpxchg.h +++ b/arch/s390/include/asm/cmpxchg.h @@ -169,32 +169,36 @@ static __always_inline unsigned long __cmpxchg(unsigned long address, #define system_has_cmpxchg_double() 1 -#define __cmpxchg_double(p1, p2, o1, o2, n1, n2) \ -({ \ - register __typeof__(*(p1)) __old1 asm("2") = (o1); \ - register __typeof__(*(p2)) __old2 asm("3") = (o2); \ - register __typeof__(*(p1)) __new1 asm("4") = (n1); \ - register __typeof__(*(p2)) __new2 asm("5") = (n2); \ - int cc; \ - asm volatile( \ - " cdsg %[old],%[new],%[ptr]\n" \ - " ipm %[cc]\n" \ - " srl %[cc],28" \ - : [cc] "=d" (cc), [old] "+d" (__old1), "+d" (__old2) \ - : [new] "d" (__new1), "d" (__new2), \ - [ptr] "Q" (*(p1)), "Q" (*(p2)) \ - : "memory", "cc"); \ - !cc; \ -}) +static __always_inline int __cmpxchg_double(unsigned long p1, unsigned long p2, + unsigned long o1, unsigned long o2, + unsigned long n1, unsigned long n2) +{ + union register_pair old = { .even = o1, .odd = o2, }; + union register_pair new = { .even = n1, .odd = n2, }; + int cc; + + asm volatile( + " cdsg %[old],%[new],%[ptr]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [old] "+&d" (old.pair) + : [new] "d" (new.pair), + [ptr] "QS" (*(unsigned long *)p1), "Q" (*(unsigned long *)p2) + : "memory", "cc"); + return !cc; +} #define arch_cmpxchg_double(p1, p2, o1, o2, n1, n2) \ ({ \ - __typeof__(p1) __p1 = (p1); \ - __typeof__(p2) __p2 = (p2); \ + typeof(p1) __p1 = (p1); \ + typeof(p2) __p2 = (p2); \ + \ BUILD_BUG_ON(sizeof(*(p1)) != sizeof(long)); \ BUILD_BUG_ON(sizeof(*(p2)) != sizeof(long)); \ VM_BUG_ON((unsigned long)((__p1) + 1) != (unsigned long)(__p2));\ - __cmpxchg_double(__p1, __p2, o1, o2, n1, n2); \ + __cmpxchg_double((unsigned long)__p1, (unsigned long)__p2, \ + (unsigned long)(o1), (unsigned long)(o2), \ + (unsigned long)(n1), (unsigned long)(n2)); \ }) #endif /* __ASM_CMPXCHG_H */ diff --git a/arch/s390/include/asm/cpu_mcf.h b/arch/s390/include/asm/cpu_mcf.h index 3e4cbcb7c4cc..4dcefddb7751 100644 --- a/arch/s390/include/asm/cpu_mcf.h +++ b/arch/s390/include/asm/cpu_mcf.h @@ -92,9 +92,8 @@ struct cpu_cf_events { struct cpumf_ctr_info info; atomic_t ctr_set[CPUMF_CTR_SET_MAX]; atomic64_t alert; - u64 state, tx_state; + u64 state; unsigned int flags; - unsigned int txn_flags; }; DECLARE_PER_CPU(struct cpu_cf_events, cpu_cf_events); diff --git a/arch/s390/include/asm/facility.h b/arch/s390/include/asm/facility.h index 91b5d714d28f..e3aa354ab9f4 100644 --- a/arch/s390/include/asm/facility.h +++ b/arch/s390/include/asm/facility.h @@ -13,7 +13,10 @@ #include #include -#define MAX_FACILITY_BIT (sizeof(((struct lowcore *)0)->stfle_fac_list) * 8) +#define MAX_FACILITY_BIT (sizeof(stfle_fac_list) * 8) + +extern u64 stfle_fac_list[16]; +extern u64 alt_stfle_fac_list[16]; static inline void __set_facility(unsigned long nr, void *facilities) { @@ -56,18 +59,20 @@ static inline int test_facility(unsigned long nr) if (__test_facility(nr, &facilities_als)) return 1; } - return __test_facility(nr, &S390_lowcore.stfle_fac_list); + return __test_facility(nr, &stfle_fac_list); } static inline unsigned long __stfle_asm(u64 *stfle_fac_list, int size) { - register unsigned long reg0 asm("0") = size - 1; + unsigned long reg0 = size - 1; asm volatile( - ".insn s,0xb2b00000,0(%1)" /* stfle */ - : "+d" (reg0) - : "a" (stfle_fac_list) - : "memory", "cc"); + " lgr 0,%[reg0]\n" + " .insn s,0xb2b00000,%[list]\n" /* stfle */ + " lgr %[reg0],0\n" + : [reg0] "+&d" (reg0), [list] "+Q" (*stfle_fac_list) + : + : "memory", "cc", "0"); return reg0; } @@ -79,13 +84,15 @@ static inline unsigned long __stfle_asm(u64 *stfle_fac_list, int size) static inline void __stfle(u64 *stfle_fac_list, int size) { unsigned long nr; + u32 stfl_fac_list; asm volatile( " stfl 0(0)\n" : "=m" (S390_lowcore.stfl_fac_list)); + stfl_fac_list = S390_lowcore.stfl_fac_list; + memcpy(stfle_fac_list, &stfl_fac_list, 4); nr = 4; /* bytes stored by stfl */ - memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4); - if (S390_lowcore.stfl_fac_list & 0x01000000) { + if (stfl_fac_list & 0x01000000) { /* More facility bits available with stfle */ nr = __stfle_asm(stfle_fac_list, size); nr = min_t(unsigned long, (nr + 1) * 8, size * 8); diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h index 586df4c9e2f2..02427b205c11 100644 --- a/arch/s390/include/asm/irqflags.h +++ b/arch/s390/include/asm/irqflags.h @@ -32,45 +32,45 @@ }) /* set system mask. */ -static inline notrace void __arch_local_irq_ssm(unsigned long flags) +static __always_inline void __arch_local_irq_ssm(unsigned long flags) { asm volatile("ssm %0" : : "Q" (flags) : "memory"); } -static inline notrace unsigned long arch_local_save_flags(void) +static __always_inline unsigned long arch_local_save_flags(void) { return __arch_local_irq_stnsm(0xff); } -static inline notrace unsigned long arch_local_irq_save(void) +static __always_inline unsigned long arch_local_irq_save(void) { return __arch_local_irq_stnsm(0xfc); } -static inline notrace void arch_local_irq_disable(void) +static __always_inline void arch_local_irq_disable(void) { arch_local_irq_save(); } -static inline notrace void arch_local_irq_enable(void) +static __always_inline void arch_local_irq_enable(void) { __arch_local_irq_stosm(0x03); } /* This only restores external and I/O interrupt state */ -static inline notrace void arch_local_irq_restore(unsigned long flags) +static __always_inline void arch_local_irq_restore(unsigned long flags) { /* only disabled->disabled and disabled->enabled is valid */ if (flags & ARCH_IRQ_ENABLED) arch_local_irq_enable(); } -static inline notrace bool arch_irqs_disabled_flags(unsigned long flags) +static __always_inline bool arch_irqs_disabled_flags(unsigned long flags) { return !(flags & ARCH_IRQ_ENABLED); } -static inline notrace bool arch_irqs_disabled(void) +static __always_inline bool arch_irqs_disabled(void) { return arch_irqs_disabled_flags(arch_local_save_flags()); } diff --git a/arch/s390/include/asm/kasan.h b/arch/s390/include/asm/kasan.h index 76f351bd6645..2768d5db181f 100644 --- a/arch/s390/include/asm/kasan.h +++ b/arch/s390/include/asm/kasan.h @@ -16,7 +16,6 @@ extern void kasan_early_init(void); extern void kasan_copy_shadow_mapping(void); extern void kasan_free_early_identity(void); -extern unsigned long kasan_vmax; /* * Estimate kasan memory requirements, which it will reserve diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index 22bceeeba4bc..47bde5a20a41 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -17,15 +17,23 @@ #define LC_ORDER 1 #define LC_PAGES 2 +struct pgm_tdb { + u64 data[32]; +}; + struct lowcore { __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */ __u32 ipl_parmblock_ptr; /* 0x0014 */ __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */ __u32 ext_params; /* 0x0080 */ - __u16 ext_cpu_addr; /* 0x0084 */ - __u16 ext_int_code; /* 0x0086 */ - __u16 svc_ilc; /* 0x0088 */ - __u16 svc_code; /* 0x008a */ + union { + struct { + __u16 ext_cpu_addr; /* 0x0084 */ + __u16 ext_int_code; /* 0x0086 */ + }; + __u32 ext_int_code_addr; + }; + __u32 svc_int_code; /* 0x0088 */ __u16 pgm_ilc; /* 0x008c */ __u16 pgm_code; /* 0x008e */ __u32 data_exc_code; /* 0x0090 */ @@ -40,10 +48,15 @@ struct lowcore { __u8 pad_0x00a4[0x00a8-0x00a4]; /* 0x00a4 */ __u64 trans_exc_code; /* 0x00a8 */ __u64 monitor_code; /* 0x00b0 */ - __u16 subchannel_id; /* 0x00b8 */ - __u16 subchannel_nr; /* 0x00ba */ - __u32 io_int_parm; /* 0x00bc */ - __u32 io_int_word; /* 0x00c0 */ + union { + struct { + __u16 subchannel_id; /* 0x00b8 */ + __u16 subchannel_nr; /* 0x00ba */ + __u32 io_int_parm; /* 0x00bc */ + __u32 io_int_word; /* 0x00c0 */ + }; + struct tpi_info tpi_info; /* 0x00b8 */ + }; __u8 pad_0x00c4[0x00c8-0x00c4]; /* 0x00c4 */ __u32 stfl_fac_list; /* 0x00c8 */ __u8 pad_0x00cc[0x00e8-0x00cc]; /* 0x00cc */ @@ -154,12 +167,7 @@ struct lowcore { __u64 vmcore_info; /* 0x0e0c */ __u8 pad_0x0e14[0x0e18-0x0e14]; /* 0x0e14 */ __u64 os_info; /* 0x0e18 */ - __u8 pad_0x0e20[0x0f00-0x0e20]; /* 0x0e20 */ - - /* Extended facility list */ - __u64 stfle_fac_list[16]; /* 0x0f00 */ - __u64 alt_stfle_fac_list[16]; /* 0x0f80 */ - __u8 pad_0x1000[0x11b0-0x1000]; /* 0x1000 */ + __u8 pad_0x0e20[0x11b0-0x0e20]; /* 0x0e20 */ /* Pointer to the machine check extended save area */ __u64 mcesad; /* 0x11b0 */ @@ -185,7 +193,7 @@ struct lowcore { __u8 pad_0x1400[0x1800-0x1400]; /* 0x1400 */ /* Transaction abort diagnostic block */ - __u8 pgm_tdb[256]; /* 0x1800 */ + struct pgm_tdb pgm_tdb; /* 0x1800 */ __u8 pad_0x1900[0x2000-0x1900]; /* 0x1900 */ } __packed __aligned(8192); diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index e7cffc7b5c2f..c7937f369e62 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -70,8 +70,8 @@ static inline int init_new_context(struct task_struct *tsk, return 0; } -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) +static inline void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) { int cpu = smp_processor_id(); @@ -85,6 +85,17 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, if (prev != next) cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask); } +#define switch_mm_irqs_off switch_mm_irqs_off + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + unsigned long flags; + + local_irq_save(flags); + switch_mm_irqs_off(prev, next, tsk); + local_irq_restore(flags); +} #define finish_arch_post_lock_switch finish_arch_post_lock_switch static inline void finish_arch_post_lock_switch(void) diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 479dc76e0eca..3ba945c6b9dc 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -55,13 +55,16 @@ static inline void storage_key_init_range(unsigned long start, unsigned long end */ static inline void copy_page(void *to, void *from) { - register void *reg2 asm ("2") = to; - register unsigned long reg3 asm ("3") = 0x1000; - register void *reg4 asm ("4") = from; - register unsigned long reg5 asm ("5") = 0xb0001000; + union register_pair dst, src; + + dst.even = (unsigned long) to; + dst.odd = 0x1000; + src.even = (unsigned long) from; + src.odd = 0xb0001000; + asm volatile( - " mvcl 2,4" - : "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5) + " mvcl %[dst],%[src]" + : [dst] "+&d" (dst.pair), [src] "+&d" (src.pair) : : "memory", "cc"); } diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index 10b67f8aab99..5509b224c2ec 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -133,7 +133,8 @@ struct zpci_dev { u8 has_resources : 1; u8 is_physfn : 1; u8 util_str_avail : 1; - u8 reserved : 3; + u8 irqs_registered : 1; + u8 reserved : 2; unsigned int devfn; /* DEVFN part of the RID*/ struct mutex lock; @@ -271,9 +272,13 @@ struct zpci_dev *get_zdev_by_fid(u32); int zpci_dma_init(void); void zpci_dma_exit(void); +/* IRQ */ int __init zpci_irq_init(void); void __init zpci_irq_exit(void); +int zpci_set_irq(struct zpci_dev *zdev); +int zpci_clear_irq(struct zpci_dev *zdev); + /* FMB */ int zpci_fmb_enable_device(struct zpci_dev *); int zpci_fmb_disable_device(struct zpci_dev *); diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h index 918f0ba4f4d2..cb5fc0690435 100644 --- a/arch/s390/include/asm/percpu.h +++ b/arch/s390/include/asm/percpu.h @@ -164,19 +164,20 @@ #define this_cpu_xchg_4(pcp, nval) arch_this_cpu_xchg(pcp, nval) #define this_cpu_xchg_8(pcp, nval) arch_this_cpu_xchg(pcp, nval) -#define arch_this_cpu_cmpxchg_double(pcp1, pcp2, o1, o2, n1, n2) \ -({ \ - typeof(pcp1) o1__ = (o1), n1__ = (n1); \ - typeof(pcp2) o2__ = (o2), n2__ = (n2); \ - typeof(pcp1) *p1__; \ - typeof(pcp2) *p2__; \ - int ret__; \ - preempt_disable_notrace(); \ - p1__ = raw_cpu_ptr(&(pcp1)); \ - p2__ = raw_cpu_ptr(&(pcp2)); \ - ret__ = __cmpxchg_double(p1__, p2__, o1__, o2__, n1__, n2__); \ - preempt_enable_notrace(); \ - ret__; \ +#define arch_this_cpu_cmpxchg_double(pcp1, pcp2, o1, o2, n1, n2) \ +({ \ + typeof(pcp1) *p1__; \ + typeof(pcp2) *p2__; \ + int ret__; \ + \ + preempt_disable_notrace(); \ + p1__ = raw_cpu_ptr(&(pcp1)); \ + p2__ = raw_cpu_ptr(&(pcp2)); \ + ret__ = __cmpxchg_double((unsigned long)p1__, (unsigned long)p2__, \ + (unsigned long)(o1), (unsigned long)(o2), \ + (unsigned long)(n1), (unsigned long)(n2)); \ + preempt_enable_notrace(); \ + ret__; \ }) #define this_cpu_cmpxchg_double_8 arch_this_cpu_cmpxchg_double diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h index 6b187cd72251..f14a555eff74 100644 --- a/arch/s390/include/asm/pgalloc.h +++ b/arch/s390/include/asm/pgalloc.h @@ -134,9 +134,6 @@ static inline void pmd_populate(struct mm_struct *mm, #define pmd_populate_kernel(mm, pmd, pte) pmd_populate(mm, pmd, pte) -#define pmd_pgtable(pmd) \ - ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) - /* * page table entry allocation/free routines. */ diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index b38f7b781564..dcac7b2df72c 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -65,8 +66,6 @@ extern unsigned long zero_page_mask; /* TODO: s390 cannot support io_remap_pfn_range... */ -#define FIRST_USER_ADDRESS 0UL - #define pte_ERROR(e) \ printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) #define pmd_ERROR(e) \ @@ -86,16 +85,16 @@ extern unsigned long zero_page_mask; * happen without trampolines and in addition the placement within a * 2GB frame is branch prediction unit friendly. */ -extern unsigned long VMALLOC_START; -extern unsigned long VMALLOC_END; +extern unsigned long __bootdata_preserved(VMALLOC_START); +extern unsigned long __bootdata_preserved(VMALLOC_END); #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) -extern struct page *vmemmap; -extern unsigned long vmemmap_size; +extern struct page *__bootdata_preserved(vmemmap); +extern unsigned long __bootdata_preserved(vmemmap_size); #define VMEM_MAX_PHYS ((unsigned long) vmemmap) -extern unsigned long MODULES_VADDR; -extern unsigned long MODULES_END; +extern unsigned long __bootdata_preserved(MODULES_VADDR); +extern unsigned long __bootdata_preserved(MODULES_END); #define MODULES_VADDR MODULES_VADDR #define MODULES_END MODULES_END #define MODULES_LEN (1UL << 31) @@ -555,27 +554,25 @@ static inline int mm_uses_skeys(struct mm_struct *mm) static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) { - register unsigned long reg2 asm("2") = old; - register unsigned long reg3 asm("3") = new; + union register_pair r1 = { .even = old, .odd = new, }; unsigned long address = (unsigned long)ptr | 1; asm volatile( - " csp %0,%3" - : "+d" (reg2), "+m" (*ptr) - : "d" (reg3), "d" (address) + " csp %[r1],%[address]" + : [r1] "+&d" (r1.pair), "+m" (*ptr) + : [address] "d" (address) : "cc"); } static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) { - register unsigned long reg2 asm("2") = old; - register unsigned long reg3 asm("3") = new; + union register_pair r1 = { .even = old, .odd = new, }; unsigned long address = (unsigned long)ptr | 1; asm volatile( - " .insn rre,0xb98a0000,%0,%3" - : "+d" (reg2), "+m" (*ptr) - : "d" (reg3), "d" (address) + " .insn rre,0xb98a0000,%[r1],%[address]" + : [r1] "+&d" (r1.pair), "+m" (*ptr) + : [address] "d" (address) : "cc"); } @@ -589,14 +586,12 @@ static inline void crdte(unsigned long old, unsigned long new, unsigned long table, unsigned long dtt, unsigned long address, unsigned long asce) { - register unsigned long reg2 asm("2") = old; - register unsigned long reg3 asm("3") = new; - register unsigned long reg4 asm("4") = table | dtt; - register unsigned long reg5 asm("5") = address; + union register_pair r1 = { .even = old, .odd = new, }; + union register_pair r2 = { .even = table | dtt, .odd = address, }; - asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" - : "+d" (reg2) - : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) + asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" + : [r1] "+&d" (r1.pair) + : [r2] "d" (r2.pair), [asce] "a" (asce) : "memory", "cc"); } @@ -863,6 +858,25 @@ static inline int pte_unused(pte_t pte) return pte_val(pte) & _PAGE_UNUSED; } +/* + * Extract the pgprot value from the given pte while at the same time making it + * usable for kernel address space mappings where fault driven dirty and + * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID + * must not be set. + */ +static inline pgprot_t pte_pgprot(pte_t pte) +{ + unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; + + if (pte_write(pte)) + pte_flags |= pgprot_val(PAGE_KERNEL); + else + pte_flags |= pgprot_val(PAGE_KERNEL_RO); + pte_flags |= pte_val(pte) & mio_wb_bit_mask; + + return __pgprot(pte_flags); +} + /* * pgd/pmd/pte modification functions */ @@ -1711,4 +1725,7 @@ extern void s390_reset_cmma(struct mm_struct *mm); #define HAVE_ARCH_UNMAPPED_AREA #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN +#define pmd_pgtable(pmd) \ + ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) + #endif /* _S390_PAGE_H */ diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index 023a15dc25a3..ddc7858bbce4 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -129,7 +129,7 @@ struct thread_struct { struct runtime_instr_cb *ri_cb; struct gs_cb *gs_cb; /* Current guarded storage cb */ struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ - unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ + struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */ /* * Warning: 'fpu' is dynamically-sized. It *MUST* be at * the end. @@ -207,7 +207,7 @@ static __always_inline unsigned long current_stack_pointer(void) return sp; } -static __no_kasan_or_inline unsigned short stap(void) +static __always_inline unsigned short stap(void) { unsigned short cpu_address; @@ -246,7 +246,7 @@ static inline void __load_psw(psw_t psw) * Set PSW mask to specified value, while leaving the * PSW addr pointing to the next instruction. */ -static __no_kasan_or_inline void __load_psw_mask(unsigned long mask) +static __always_inline void __load_psw_mask(unsigned long mask) { unsigned long addr; psw_t psw; diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index f828be78937f..c7850d649373 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -9,6 +9,7 @@ #include #include +#include #define PIF_SYSCALL 0 /* inside a system call */ #define PIF_SYSCALL_RESTART 1 /* restart the current system call */ @@ -86,9 +87,14 @@ struct pt_regs }; }; unsigned long orig_gpr2; - unsigned int int_code; - unsigned int int_parm; - unsigned long int_parm_long; + union { + struct { + unsigned int int_code; + unsigned int int_parm; + unsigned long int_parm_long; + }; + struct tpi_info tpi_info; + }; unsigned long flags; unsigned long cr1; }; diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index 3e388fa208d4..a8b75da3c1b8 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -78,6 +78,8 @@ struct parmarea { char command_line[ARCH_COMMAND_LINE_SIZE]; /* 0x10480 */ }; +extern struct parmarea parmarea; + extern unsigned int zlib_dfltcc_support; #define ZLIB_DFLTCC_DISABLED 0 #define ZLIB_DFLTCC_FULL 1 @@ -87,7 +89,6 @@ extern unsigned int zlib_dfltcc_support; extern int noexec_disabled; extern unsigned long ident_map_size; -extern unsigned long vmalloc_size; /* The Write Back bit position in the physaddr is given by the SLPC PCI */ extern unsigned long mio_wb_bit_mask; diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h index 53ee795cd3d3..edee63da08e7 100644 --- a/arch/s390/include/asm/sigp.h +++ b/arch/s390/include/asm/sigp.h @@ -41,15 +41,17 @@ static inline int ____pcpu_sigp(u16 addr, u8 order, unsigned long parm, u32 *status) { - register unsigned long reg1 asm ("1") = parm; + union register_pair r1 = { .odd = parm, }; int cc; asm volatile( - " sigp %1,%2,0(%3)\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); - *status = reg1; + " sigp %[r1],%[addr],0(%[order])\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [r1] "+&d" (r1.pair) + : [addr] "d" (addr), [order] "a" (order) + : "cc"); + *status = r1.even; return cc; } diff --git a/arch/s390/include/asm/string.h b/arch/s390/include/asm/string.h index 4c0690fc5167..4fd66c5e8934 100644 --- a/arch/s390/include/asm/string.h +++ b/arch/s390/include/asm/string.h @@ -107,16 +107,18 @@ static inline void *memset64(uint64_t *s, uint64_t v, size_t count) #ifdef __HAVE_ARCH_MEMCHR static inline void *memchr(const void * s, int c, size_t n) { - register int r0 asm("0") = (char) c; const void *ret = s + n; asm volatile( - "0: srst %0,%1\n" + " lgr 0,%[c]\n" + "0: srst %[ret],%[s]\n" " jo 0b\n" " jl 1f\n" - " la %0,0\n" + " la %[ret],0\n" "1:" - : "+a" (ret), "+&a" (s) : "d" (r0) : "cc", "memory"); + : [ret] "+&a" (ret), [s] "+&a" (s) + : [c] "d" (c) + : "cc", "memory", "0"); return (void *) ret; } #endif @@ -124,13 +126,15 @@ static inline void *memchr(const void * s, int c, size_t n) #ifdef __HAVE_ARCH_MEMSCAN static inline void *memscan(void *s, int c, size_t n) { - register int r0 asm("0") = (char) c; const void *ret = s + n; asm volatile( - "0: srst %0,%1\n" + " lgr 0,%[c]\n" + "0: srst %[ret],%[s]\n" " jo 0b\n" - : "+a" (ret), "+&a" (s) : "d" (r0) : "cc", "memory"); + : [ret] "+&a" (ret), [s] "+&a" (s) + : [c] "d" (c) + : "cc", "memory", "0"); return (void *) ret; } #endif @@ -138,17 +142,18 @@ static inline void *memscan(void *s, int c, size_t n) #ifdef __HAVE_ARCH_STRCAT static inline char *strcat(char *dst, const char *src) { - register int r0 asm("0") = 0; - unsigned long dummy; + unsigned long dummy = 0; char *ret = dst; asm volatile( - "0: srst %0,%1\n" + " lghi 0,0\n" + "0: srst %[dummy],%[dst]\n" " jo 0b\n" - "1: mvst %0,%2\n" + "1: mvst %[dummy],%[src]\n" " jo 1b" - : "=&a" (dummy), "+a" (dst), "+a" (src) - : "d" (r0), "0" (0) : "cc", "memory" ); + : [dummy] "+&a" (dummy), [dst] "+&a" (dst), [src] "+&a" (src) + : + : "cc", "memory", "0"); return ret; } #endif @@ -156,14 +161,15 @@ static inline char *strcat(char *dst, const char *src) #ifdef __HAVE_ARCH_STRCPY static inline char *strcpy(char *dst, const char *src) { - register int r0 asm("0") = 0; char *ret = dst; asm volatile( - "0: mvst %0,%1\n" + " lghi 0,0\n" + "0: mvst %[dst],%[src]\n" " jo 0b" - : "+&a" (dst), "+&a" (src) : "d" (r0) - : "cc", "memory"); + : [dst] "+&a" (dst), [src] "+&a" (src) + : + : "cc", "memory", "0"); return ret; } #endif @@ -171,28 +177,33 @@ static inline char *strcpy(char *dst, const char *src) #if defined(__HAVE_ARCH_STRLEN) || (defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__)) static inline size_t __no_sanitize_prefix_strfunc(strlen)(const char *s) { - register unsigned long r0 asm("0") = 0; + unsigned long end = 0; const char *tmp = s; asm volatile( - "0: srst %0,%1\n" + " lghi 0,0\n" + "0: srst %[end],%[tmp]\n" " jo 0b" - : "+d" (r0), "+a" (tmp) : : "cc", "memory"); - return r0 - (unsigned long) s; + : [end] "+&a" (end), [tmp] "+&a" (tmp) + : + : "cc", "memory", "0"); + return end - (unsigned long)s; } #endif #ifdef __HAVE_ARCH_STRNLEN static inline size_t strnlen(const char * s, size_t n) { - register int r0 asm("0") = 0; const char *tmp = s; const char *end = s + n; asm volatile( - "0: srst %0,%1\n" + " lghi 0,0\n" + "0: srst %[end],%[tmp]\n" " jo 0b" - : "+a" (end), "+a" (tmp) : "d" (r0) : "cc", "memory"); + : [end] "+&a" (end), [tmp] "+&a" (tmp) + : + : "cc", "memory", "0"); return end - s; } #endif diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index f6326c6d2abe..50d9b04ecbd1 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -75,9 +75,12 @@ static inline void set_clock_comparator(__u64 time) static inline void set_tod_programmable_field(u16 val) { - register unsigned long reg0 asm("0") = val; - - asm volatile("sckpf" : : "d" (reg0)); + asm volatile( + " lgr 0,%[val]\n" + " sckpf\n" + : + : [val] "d" ((unsigned long)val) + : "0"); } void clock_comparator_work(void); @@ -138,16 +141,19 @@ struct ptff_qui { #define ptff(ptff_block, len, func) \ ({ \ struct addrtype { char _[len]; }; \ - register unsigned int reg0 asm("0") = func; \ - register unsigned long reg1 asm("1") = (unsigned long) (ptff_block);\ + unsigned int reg0 = func; \ + unsigned long reg1 = (unsigned long)(ptff_block); \ int rc; \ \ asm volatile( \ - " .word 0x0104\n" \ - " ipm %0\n" \ - " srl %0,28\n" \ - : "=d" (rc), "+m" (*(struct addrtype *) reg1) \ - : "d" (reg0), "d" (reg1) : "cc"); \ + " lgr 0,%[reg0]\n" \ + " lgr 1,%[reg1]\n" \ + " .insn e,0x0104\n" \ + " ipm %[rc]\n" \ + " srl %[rc],28\n" \ + : [rc] "=&d" (rc), "+m" (*(struct addrtype *)reg1) \ + : [reg0] "d" (reg0), [reg1] "d" (reg1) \ + : "cc", "0", "1"); \ rc; \ }) diff --git a/arch/s390/include/asm/tpi.h b/arch/s390/include/asm/tpi.h new file mode 100644 index 000000000000..1ac538b8cbf5 --- /dev/null +++ b/arch/s390/include/asm/tpi.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_S390_TPI_H +#define _ASM_S390_TPI_H + +#include +#include + +#ifndef __ASSEMBLY__ + +/* I/O-Interruption Code as stored by TEST PENDING INTERRUPTION (TPI). */ +struct tpi_info { + struct subchannel_id schid; + u32 intparm; + u32 adapter_IO:1; + u32 directed_irq:1; + u32 isc:3; + u32 :12; + u32 type:3; + u32 :12; +} __packed __aligned(4); + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_S390_TPI_H */ diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h new file mode 100644 index 000000000000..0b5d550a0478 --- /dev/null +++ b/arch/s390/include/asm/types.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_S390_TYPES_H +#define _ASM_S390_TYPES_H + +#include + +#ifndef __ASSEMBLY__ + +union register_pair { + unsigned __int128 pair; + struct { + unsigned long even; + unsigned long odd; + }; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_S390_TYPES_H */ diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h index 4756d2937e54..2316f2440881 100644 --- a/arch/s390/include/asm/uaccess.h +++ b/arch/s390/include/asm/uaccess.h @@ -49,52 +49,51 @@ int __get_user_bad(void) __attribute__((noreturn)); #ifdef CONFIG_HAVE_MARCH_Z10_FEATURES -#define __put_get_user_asm(to, from, size, spec) \ +#define __put_get_user_asm(to, from, size, insn) \ ({ \ - register unsigned long __reg0 asm("0") = spec; \ int __rc; \ \ asm volatile( \ - "0: mvcos %1,%3,%2\n" \ - "1: xr %0,%0\n" \ + insn " 0,%[spec]\n" \ + "0: mvcos %[_to],%[_from],%[_size]\n" \ + "1: xr %[rc],%[rc]\n" \ "2:\n" \ ".pushsection .fixup, \"ax\"\n" \ - "3: lhi %0,%5\n" \ + "3: lhi %[rc],%[retval]\n" \ " jg 2b\n" \ ".popsection\n" \ EX_TABLE(0b,3b) EX_TABLE(1b,3b) \ - : "=d" (__rc), "+Q" (*(to)) \ - : "d" (size), "Q" (*(from)), \ - "d" (__reg0), "K" (-EFAULT) \ - : "cc"); \ + : [rc] "=&d" (__rc), [_to] "+Q" (*(to)) \ + : [_size] "d" (size), [_from] "Q" (*(from)), \ + [retval] "K" (-EFAULT), [spec] "K" (0x81UL) \ + : "cc", "0"); \ __rc; \ }) static __always_inline int __put_user_fn(void *x, void __user *ptr, unsigned long size) { - unsigned long spec = 0x810000UL; int rc; switch (size) { case 1: rc = __put_get_user_asm((unsigned char __user *)ptr, (unsigned char *)x, - size, spec); + size, "llilh"); break; case 2: rc = __put_get_user_asm((unsigned short __user *)ptr, (unsigned short *)x, - size, spec); + size, "llilh"); break; case 4: rc = __put_get_user_asm((unsigned int __user *)ptr, (unsigned int *)x, - size, spec); + size, "llilh"); break; case 8: rc = __put_get_user_asm((unsigned long __user *)ptr, (unsigned long *)x, - size, spec); + size, "llilh"); break; default: __put_user_bad(); @@ -105,29 +104,28 @@ static __always_inline int __put_user_fn(void *x, void __user *ptr, unsigned lon static __always_inline int __get_user_fn(void *x, const void __user *ptr, unsigned long size) { - unsigned long spec = 0x81UL; int rc; switch (size) { case 1: rc = __put_get_user_asm((unsigned char *)x, (unsigned char __user *)ptr, - size, spec); + size, "lghi"); break; case 2: rc = __put_get_user_asm((unsigned short *)x, (unsigned short __user *)ptr, - size, spec); + size, "lghi"); break; case 4: rc = __put_get_user_asm((unsigned int *)x, (unsigned int __user *)ptr, - size, spec); + size, "lghi"); break; case 8: rc = __put_get_user_asm((unsigned long *)x, (unsigned long __user *)ptr, - size, spec); + size, "lghi"); break; default: __get_user_bad(); diff --git a/arch/s390/include/uapi/asm/schid.h b/arch/s390/include/uapi/asm/schid.h index 58fca6f48410..a3e1cf168553 100644 --- a/arch/s390/include/uapi/asm/schid.h +++ b/arch/s390/include/uapi/asm/schid.h @@ -4,6 +4,8 @@ #include +#ifndef __ASSEMBLY__ + struct subchannel_id { __u32 cssid : 8; __u32 : 4; @@ -13,5 +15,6 @@ struct subchannel_id { __u32 sch_no : 16; } __attribute__ ((packed, aligned(4))); +#endif /* __ASSEMBLY__ */ #endif /* _UAPIASM_SCHID_H */ diff --git a/arch/s390/kernel/alternative.c b/arch/s390/kernel/alternative.c index 8e1f2aee85ef..c22ea1c3ef84 100644 --- a/arch/s390/kernel/alternative.c +++ b/arch/s390/kernel/alternative.c @@ -76,8 +76,7 @@ static void __init_or_module __apply_alternatives(struct alt_instr *start, instr = (u8 *)&a->instr_offset + a->instr_offset; replacement = (u8 *)&a->repl_offset + a->repl_offset; - if (!__test_facility(a->facility, - S390_lowcore.alt_stfle_fac_list)) + if (!__test_facility(a->facility, alt_stfle_fac_list)) continue; if (unlikely(a->instrlen % 2 || a->replacementlen % 2)) { diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index 15e637728a4b..f53605a3dfcd 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -15,6 +15,7 @@ #include #include #include +#include #include int main(void) @@ -58,8 +59,6 @@ int main(void) OFFSET(__LC_EXT_PARAMS, lowcore, ext_params); OFFSET(__LC_EXT_CPU_ADDR, lowcore, ext_cpu_addr); OFFSET(__LC_EXT_INT_CODE, lowcore, ext_int_code); - OFFSET(__LC_SVC_ILC, lowcore, svc_ilc); - OFFSET(__LC_SVC_INT_CODE, lowcore, svc_code); OFFSET(__LC_PGM_ILC, lowcore, pgm_ilc); OFFSET(__LC_PGM_INT_CODE, lowcore, pgm_code); OFFSET(__LC_DATA_EXC_CODE, lowcore, data_exc_code); @@ -77,8 +76,6 @@ int main(void) OFFSET(__LC_SUBCHANNEL_NR, lowcore, subchannel_nr); OFFSET(__LC_IO_INT_PARM, lowcore, io_int_parm); OFFSET(__LC_IO_INT_WORD, lowcore, io_int_word); - OFFSET(__LC_STFL_FAC_LIST, lowcore, stfl_fac_list); - OFFSET(__LC_STFLE_FAC_LIST, lowcore, stfle_fac_list); OFFSET(__LC_MCCK_CODE, lowcore, mcck_interruption_code); OFFSET(__LC_EXT_DAMAGE_CODE, lowcore, external_damage_code); OFFSET(__LC_MCCK_FAIL_STOR_ADDR, lowcore, failing_storage_address); @@ -159,5 +156,7 @@ int main(void) OFFSET(__KEXEC_SHA_REGION_START, kexec_sha_region, start); OFFSET(__KEXEC_SHA_REGION_LEN, kexec_sha_region, len); DEFINE(__KEXEC_SHA_REGION_SIZE, sizeof(struct kexec_sha_region)); + /* sizeof kernel parameter area */ + DEFINE(__PARMAREA_SIZE, sizeof(struct parmarea)); return 0; } diff --git a/arch/s390/kernel/cpcmd.c b/arch/s390/kernel/cpcmd.c index 2da027359798..54efc279f54e 100644 --- a/arch/s390/kernel/cpcmd.c +++ b/arch/s390/kernel/cpcmd.c @@ -26,33 +26,35 @@ static char cpcmd_buf[241]; static int diag8_noresponse(int cmdlen) { - register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; - register unsigned long reg3 asm ("3") = cmdlen; - asm volatile( - " diag %1,%0,0x8\n" - : "+d" (reg3) : "d" (reg2) : "cc"); - return reg3; + " diag %[rx],%[ry],0x8\n" + : [ry] "+&d" (cmdlen) + : [rx] "d" ((addr_t) cpcmd_buf) + : "cc"); + return cmdlen; } static int diag8_response(int cmdlen, char *response, int *rlen) { - unsigned long _cmdlen = cmdlen | 0x40000000L; - unsigned long _rlen = *rlen; - register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; - register unsigned long reg3 asm ("3") = (addr_t) response; - register unsigned long reg4 asm ("4") = _cmdlen; - register unsigned long reg5 asm ("5") = _rlen; + union register_pair rx, ry; + int cc; + rx.even = (addr_t) cpcmd_buf; + rx.odd = (addr_t) response; + ry.even = cmdlen | 0x40000000L; + ry.odd = *rlen; asm volatile( - " diag %2,%0,0x8\n" - " brc 8,1f\n" - " agr %1,%4\n" - "1:\n" - : "+d" (reg4), "+d" (reg5) - : "d" (reg2), "d" (reg3), "d" (*rlen) : "cc"); - *rlen = reg5; - return reg4; + " diag %[rx],%[ry],0x8\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [ry] "+&d" (ry.pair) + : [rx] "d" (rx.pair) + : "cc"); + if (cc) + *rlen += ry.odd; + else + *rlen = ry.odd; + return ry.even; } /* diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c index bb958d32bd81..09b6c6402f9b 100644 --- a/arch/s390/kernel/debug.c +++ b/arch/s390/kernel/debug.c @@ -1418,7 +1418,7 @@ int debug_dflt_header_fn(debug_info_t *id, struct debug_view *view, else except_str = "-"; caller = (unsigned long) entry->caller; - rc += sprintf(out_buf, "%02i %011ld:%06lu %1u %1s %04u %pK ", + rc += sprintf(out_buf, "%02i %011ld:%06lu %1u %1s %04u %px ", area, sec, usec, level, except_str, entry->cpu, (void *)caller); return rc; diff --git a/arch/s390/kernel/diag.c b/arch/s390/kernel/diag.c index b8b0cd7b008f..a3f47464c3f1 100644 --- a/arch/s390/kernel/diag.c +++ b/arch/s390/kernel/diag.c @@ -141,16 +141,15 @@ EXPORT_SYMBOL(diag14); static inline int __diag204(unsigned long *subcode, unsigned long size, void *addr) { - register unsigned long _subcode asm("0") = *subcode; - register unsigned long _size asm("1") = size; + union register_pair rp = { .even = *subcode, .odd = size }; asm volatile( - " diag %2,%0,0x204\n" + " diag %[addr],%[rp],0x204\n" "0: nopr %%r7\n" EX_TABLE(0b,0b) - : "+d" (_subcode), "+d" (_size) : "d" (addr) : "memory"); - *subcode = _subcode; - return _size; + : [rp] "+&d" (rp.pair) : [addr] "d" (addr) : "memory"); + *subcode = rp.even; + return rp.odd; } int diag204(unsigned long subcode, unsigned long size, void *addr) diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c index a361d2e70025..c2cf79d353cf 100644 --- a/arch/s390/kernel/early.c +++ b/arch/s390/kernel/early.c @@ -180,11 +180,9 @@ static noinline __init void setup_lowcore_early(void) static noinline __init void setup_facility_list(void) { - memcpy(S390_lowcore.alt_stfle_fac_list, - S390_lowcore.stfle_fac_list, - sizeof(S390_lowcore.alt_stfle_fac_list)); + memcpy(alt_stfle_fac_list, stfle_fac_list, sizeof(alt_stfle_fac_list)); if (!IS_ENABLED(CONFIG_KERNEL_NOBP)) - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); } static __init void detect_diag9c(void) diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index e84f495e7eb2..3e8c6669373a 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -129,6 +129,27 @@ _LPP_OFFSET = __LC_LPP "jnz .+8; .long 0xb2e8d000", 82 .endm +#if IS_ENABLED(CONFIG_KVM) + /* + * The OUTSIDE macro jumps to the provided label in case the value + * in the provided register is outside of the provided range. The + * macro is useful for checking whether a PSW stored in a register + * pair points inside or outside of a block of instructions. + * @reg: register to check + * @start: start of the range + * @end: end of the range + * @outside_label: jump here if @reg is outside of [@start..@end) + */ + .macro OUTSIDE reg,start,end,outside_label + lgr %r14,\reg + larl %r13,\start + slgr %r14,%r13 + lghi %r13,\end - \start + clgr %r14,%r13 + jhe \outside_label + .endm +#endif + GEN_BR_THUNK %r14 GEN_BR_THUNK %r14,%r13 @@ -214,7 +235,7 @@ ENTRY(sie64a) # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable. # Other instructions between sie64a and .Lsie_done should not cause program # interrupts. So lets use 3 nops as a landing pad for all possible rewinds. -# See also .Lcleanup_sie_mcck/.Lcleanup_sie_int +# See also .Lcleanup_sie .Lrewind_pad6: nopr 7 .Lrewind_pad4: @@ -276,6 +297,7 @@ ENTRY(system_call) xgr %r10,%r10 xgr %r11,%r11 la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs + mvc __PT_R8(64,%r2),__LC_SAVE_AREA_SYNC lgr %r3,%r14 brasl %r14,__do_syscall lctlg %c1,%c1,__LC_USER_ASCE @@ -318,12 +340,7 @@ ENTRY(pgm_check_handler) .Lpgm_skip_asce: #if IS_ENABLED(CONFIG_KVM) # cleanup critical section for program checks in sie64a - lgr %r14,%r9 - larl %r13,.Lsie_gmap - slgr %r14,%r13 - lghi %r13,.Lsie_done - .Lsie_gmap - clgr %r14,%r13 - jhe 1f + OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce @@ -392,13 +409,8 @@ ENTRY(\name) tmhh %r8,0x0001 # interrupting from user ? jnz 1f #if IS_ENABLED(CONFIG_KVM) - lgr %r14,%r9 - larl %r13,.Lsie_gmap - slgr %r14,%r13 - lghi %r13,.Lsie_done - .Lsie_gmap - clgr %r14,%r13 - jhe 0f - brasl %r14,.Lcleanup_sie_int + OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f + brasl %r14,.Lcleanup_sie #endif 0: CHECK_STACK __LC_SAVE_AREA_ASYNC aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) @@ -541,13 +553,10 @@ ENTRY(mcck_int_handler) tmhh %r8,0x0001 # interrupting from user ? jnz .Lmcck_user #if IS_ENABLED(CONFIG_KVM) - lgr %r14,%r9 - larl %r13,.Lsie_gmap - slgr %r14,%r13 - lghi %r13,.Lsie_done - .Lsie_gmap - clgr %r14,%r13 - jhe .Lmcck_stack - brasl %r14,.Lcleanup_sie_mcck + OUTSIDE %r9,.Lsie_gmap,.Lsie_done,.Lmcck_stack + OUTSIDE %r9,.Lsie_entry,.Lsie_skip,5f + oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST +5: brasl %r14,.Lcleanup_sie #endif j .Lmcck_stack .Lmcck_user: @@ -649,21 +658,13 @@ ENDPROC(stack_overflow) #endif #if IS_ENABLED(CONFIG_KVM) -.Lcleanup_sie_mcck: - larl %r13,.Lsie_entry - slgr %r9,%r13 - lghi %r13,.Lsie_skip - .Lsie_entry - clgr %r9,%r13 - jhe .Lcleanup_sie_int - oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST -.Lcleanup_sie_int: +.Lcleanup_sie: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST) lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE lctlg %c1,%c1,__LC_KERNEL_ASCE larl %r9,sie_exit # skip forward to sie_exit BR_EX %r14,%r13 - #endif .section .rodata, "a" #define SYSCALL(esame,emu) .quad __s390x_ ## esame diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c index dba04fbc37a2..50e2c21e0ec9 100644 --- a/arch/s390/kernel/ipl.c +++ b/arch/s390/kernel/ipl.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -162,16 +163,18 @@ static bool reipl_ccw_clear; static inline int __diag308(unsigned long subcode, void *addr) { - register unsigned long _addr asm("0") = (unsigned long) addr; - register unsigned long _rc asm("1") = 0; + union register_pair r1; + r1.even = (unsigned long) addr; + r1.odd = 0; asm volatile( - " diag %0,%2,0x308\n" + " diag %[r1],%[subcode],0x308\n" "0: nopr %%r7\n" EX_TABLE(0b,0b) - : "+d" (_addr), "+d" (_rc) - : "d" (subcode) : "cc", "memory"); - return _rc; + : [r1] "+&d" (r1.pair) + : [subcode] "d" (subcode) + : "cc", "memory"); + return r1.odd; } int diag308(unsigned long subcode, void *addr) diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index 714269e10eec..c0df4060d28d 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -146,8 +146,8 @@ void noinstr do_io_irq(struct pt_regs *regs) account_idle_time_irq(); do { - memcpy(®s->int_code, &S390_lowcore.subchannel_id, 12); - if (S390_lowcore.io_int_word & BIT(31)) + regs->tpi_info = S390_lowcore.tpi_info; + if (S390_lowcore.tpi_info.adapter_IO) do_irq_async(regs, THIN_INTERRUPT); else do_irq_async(regs, IO_INTERRUPT); @@ -172,7 +172,7 @@ void noinstr do_ext_irq(struct pt_regs *regs) if (user_mode(regs)) update_timer_sys(); - memcpy(®s->int_code, &S390_lowcore.ext_cpu_addr, 4); + regs->int_code = S390_lowcore.ext_int_code_addr; regs->int_parm = S390_lowcore.ext_params; regs->int_parm_long = S390_lowcore.ext_params2; diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 74b0bd2c24d4..528bb31815c3 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -44,11 +44,6 @@ void *alloc_insn_page(void) return page; } -void free_insn_page(void *page) -{ - module_memfree(page); -} - static void *alloc_s390_insn_page(void) { if (xchg(&insn_page_in_use, 1) == 1) diff --git a/arch/s390/kernel/nospec-branch.c b/arch/s390/kernel/nospec-branch.c index 29e511f5bf06..250e4dbf653c 100644 --- a/arch/s390/kernel/nospec-branch.c +++ b/arch/s390/kernel/nospec-branch.c @@ -17,11 +17,11 @@ static int __init nobp_setup_early(char *str) * The user explicitely requested nobp=1, enable it and * disable the expoline support. */ - __set_facility(82, S390_lowcore.alt_stfle_fac_list); + __set_facility(82, alt_stfle_fac_list); if (IS_ENABLED(CONFIG_EXPOLINE)) nospec_disable = 1; } else { - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); } return 0; } @@ -29,7 +29,7 @@ early_param("nobp", nobp_setup_early); static int __init nospec_setup_early(char *str) { - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); return 0; } early_param("nospec", nospec_setup_early); @@ -40,7 +40,7 @@ static int __init nospec_report(void) pr_info("Spectre V2 mitigation: etokens\n"); if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) pr_info("Spectre V2 mitigation: execute trampolines\n"); - if (__test_facility(82, S390_lowcore.alt_stfle_fac_list)) + if (__test_facility(82, alt_stfle_fac_list)) pr_info("Spectre V2 mitigation: limited branch prediction\n"); return 0; } @@ -66,14 +66,14 @@ void __init nospec_auto_detect(void) */ if (__is_defined(CC_USING_EXPOLINE)) nospec_disable = 1; - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); } else if (__is_defined(CC_USING_EXPOLINE)) { /* * The kernel has been compiled with expolines. * Keep expolines enabled and disable nobp. */ nospec_disable = 0; - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); } /* * If the kernel has not been compiled with expolines the @@ -86,7 +86,7 @@ static int __init spectre_v2_setup_early(char *str) { if (str && !strncmp(str, "on", 2)) { nospec_disable = 0; - __clear_facility(82, S390_lowcore.alt_stfle_fac_list); + __clear_facility(82, alt_stfle_fac_list); } if (str && !strncmp(str, "off", 3)) nospec_disable = 1; @@ -99,6 +99,7 @@ early_param("spectre_v2", spectre_v2_setup_early); static void __init_or_module __nospec_revert(s32 *start, s32 *end) { enum { BRCL_EXPOLINE, BRASL_EXPOLINE } type; + static const u8 branch[] = { 0x47, 0x00, 0x07, 0x00 }; u8 *instr, *thunk, *br; u8 insnbuf[6]; s32 *epo; @@ -128,7 +129,7 @@ static void __init_or_module __nospec_revert(s32 *start, s32 *end) if ((br[0] & 0xbf) != 0x07 || (br[1] & 0xf0) != 0xf0) continue; - memcpy(insnbuf + 2, (char[]) { 0x47, 0x00, 0x07, 0x00 }, 4); + memcpy(insnbuf + 2, branch, sizeof(branch)); switch (type) { case BRCL_EXPOLINE: insnbuf[0] = br[0]; diff --git a/arch/s390/kernel/nospec-sysfs.c b/arch/s390/kernel/nospec-sysfs.c index 48f472bf9290..b4b5c8c21166 100644 --- a/arch/s390/kernel/nospec-sysfs.c +++ b/arch/s390/kernel/nospec-sysfs.c @@ -17,7 +17,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, return sprintf(buf, "Mitigation: etokens\n"); if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) return sprintf(buf, "Mitigation: execute trampolines\n"); - if (__test_facility(82, S390_lowcore.alt_stfle_fac_list)) + if (__test_facility(82, alt_stfle_fac_list)) return sprintf(buf, "Mitigation: limited branch prediction\n"); return sprintf(buf, "Vulnerable\n"); } diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 31a605bcbc6e..1b7a0525fbed 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -362,15 +362,9 @@ static void cpumf_pmu_start(struct perf_event *event, int flags) struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); struct hw_perf_event *hwc = &event->hw; - if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) + if (!(hwc->state & PERF_HES_STOPPED)) return; - if (WARN_ON_ONCE(hwc->config == -1)) - return; - - if (flags & PERF_EF_RELOAD) - WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); - hwc->state = 0; /* (Re-)enable and activate the counter set */ @@ -413,15 +407,6 @@ static int cpumf_pmu_add(struct perf_event *event, int flags) { struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - /* Check authorization for the counter set to which this - * counter belongs. - * For group events transaction, the authorization check is - * done in cpumf_pmu_commit_txn(). - */ - if (!(cpuhw->txn_flags & PERF_PMU_TXN_ADD)) - if (validate_ctr_auth(&event->hw)) - return -ENOENT; - ctr_set_enable(&cpuhw->state, event->hw.config_base); event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; @@ -449,78 +434,6 @@ static void cpumf_pmu_del(struct perf_event *event, int flags) ctr_set_disable(&cpuhw->state, event->hw.config_base); } -/* - * Start group events scheduling transaction. - * Set flags to perform a single test at commit time. - * - * We only support PERF_PMU_TXN_ADD transactions. Save the - * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD - * transactions. - */ -static void cpumf_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - - WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ - - cpuhw->txn_flags = txn_flags; - if (txn_flags & ~PERF_PMU_TXN_ADD) - return; - - perf_pmu_disable(pmu); - cpuhw->tx_state = cpuhw->state; -} - -/* - * Stop and cancel a group events scheduling tranctions. - * Assumes cpumf_pmu_del() is called for each successful added - * cpumf_pmu_add() during the transaction. - */ -static void cpumf_pmu_cancel_txn(struct pmu *pmu) -{ - unsigned int txn_flags; - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - - WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ - - txn_flags = cpuhw->txn_flags; - cpuhw->txn_flags = 0; - if (txn_flags & ~PERF_PMU_TXN_ADD) - return; - - WARN_ON(cpuhw->tx_state != cpuhw->state); - - perf_pmu_enable(pmu); -} - -/* - * Commit the group events scheduling transaction. On success, the - * transaction is closed. On error, the transaction is kept open - * until cpumf_pmu_cancel_txn() is called. - */ -static int cpumf_pmu_commit_txn(struct pmu *pmu) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - u64 state; - - WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ - - if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { - cpuhw->txn_flags = 0; - return 0; - } - - /* check if the updated state can be scheduled */ - state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); - state >>= CPUMF_LCCTL_ENABLE_SHIFT; - if ((state & cpuhw->info.auth_ctl) != state) - return -ENOENT; - - cpuhw->txn_flags = 0; - perf_pmu_enable(pmu); - return 0; -} - /* Performance monitoring unit for s390x */ static struct pmu cpumf_pmu = { .task_ctx_nr = perf_sw_context, @@ -533,9 +446,6 @@ static struct pmu cpumf_pmu = { .start = cpumf_pmu_start, .stop = cpumf_pmu_stop, .read = cpumf_pmu_read, - .start_txn = cpumf_pmu_start_txn, - .commit_txn = cpumf_pmu_commit_txn, - .cancel_txn = cpumf_pmu_cancel_txn, }; static int __init cpumf_pmu_init(void) diff --git a/arch/s390/kernel/perf_cpum_cf_common.c b/arch/s390/kernel/perf_cpum_cf_common.c index 6d53215c8484..2300fbaac556 100644 --- a/arch/s390/kernel/perf_cpum_cf_common.c +++ b/arch/s390/kernel/perf_cpum_cf_common.c @@ -30,7 +30,6 @@ DEFINE_PER_CPU(struct cpu_cf_events, cpu_cf_events) = { .alert = ATOMIC64_INIT(0), .state = 0, .flags = 0, - .txn_flags = 0, }; /* Indicator whether the CPU-Measurement Counter Facility Support is ready */ static bool cpum_cf_initalized; diff --git a/arch/s390/kernel/processor.c b/arch/s390/kernel/processor.c index c92d04f876cb..82df39b17bb5 100644 --- a/arch/s390/kernel/processor.c +++ b/arch/s390/kernel/processor.c @@ -103,11 +103,9 @@ EXPORT_SYMBOL(cpu_have_feature); static void show_facilities(struct seq_file *m) { unsigned int bit; - long *facilities; - facilities = (long *)&S390_lowcore.stfle_fac_list; seq_puts(m, "facilities :"); - for_each_set_bit_inv(bit, facilities, MAX_FACILITY_BIT) + for_each_set_bit_inv(bit, (long *)&stfle_fac_list, MAX_FACILITY_BIT) seq_printf(m, " %d", bit); seq_putc(m, '\n'); } diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 18b3416fd663..0ea3d02b378d 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -975,10 +975,12 @@ static int s390_tdb_get(struct task_struct *target, struct membuf to) { struct pt_regs *regs = task_pt_regs(target); + size_t size; if (!(regs->int_code & 0x200)) return -ENODATA; - return membuf_write(&to, target->thread.trap_tdb, 256); + size = sizeof(target->thread.trap_tdb.data); + return membuf_write(&to, target->thread.trap_tdb.data, size); } static int s390_tdb_set(struct task_struct *target, diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 5aab59ad5688..b58ee83f30e3 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -96,7 +96,6 @@ unsigned long int_hwcap = 0; int __bootdata(noexec_disabled); unsigned long __bootdata(ident_map_size); -unsigned long __bootdata(vmalloc_size); struct mem_detect_info __bootdata(mem_detect); struct exception_table_entry *__bootdata_preserved(__start_dma_ex_table); @@ -108,6 +107,9 @@ unsigned long __bootdata_preserved(__edma); unsigned long __bootdata_preserved(__kaslr_offset); unsigned int __bootdata_preserved(zlib_dfltcc_support); EXPORT_SYMBOL(zlib_dfltcc_support); +u64 __bootdata_preserved(stfle_fac_list[16]); +EXPORT_SYMBOL(stfle_fac_list); +u64 __bootdata_preserved(alt_stfle_fac_list[16]); unsigned long VMALLOC_START; EXPORT_SYMBOL(VMALLOC_START); @@ -165,7 +167,7 @@ static void __init set_preferred_console(void) else if (CONSOLE_IS_3270) add_preferred_console("tty3270", 0, NULL); else if (CONSOLE_IS_VT220) - add_preferred_console("ttyS", 1, NULL); + add_preferred_console("ttysclp", 0, NULL); else if (CONSOLE_IS_HVC) add_preferred_console("hvc", 0, NULL); } @@ -338,27 +340,6 @@ int __init arch_early_irq_init(void) return 0; } -static int __init stack_realloc(void) -{ - unsigned long old, new; - - old = S390_lowcore.async_stack - STACK_INIT_OFFSET; - new = stack_alloc(); - if (!new) - panic("Couldn't allocate async stack"); - WRITE_ONCE(S390_lowcore.async_stack, new + STACK_INIT_OFFSET); - free_pages(old, THREAD_SIZE_ORDER); - - old = S390_lowcore.mcck_stack - STACK_INIT_OFFSET; - new = stack_alloc(); - if (!new) - panic("Couldn't allocate machine check stack"); - WRITE_ONCE(S390_lowcore.mcck_stack, new + STACK_INIT_OFFSET); - memblock_free_late(old, THREAD_SIZE); - return 0; -} -early_initcall(stack_realloc); - void __init arch_call_rest_init(void) { unsigned long stack; @@ -413,11 +394,6 @@ static void __init setup_lowcore_dat_off(void) lc->lpp = LPP_MAGIC; lc->machine_flags = S390_lowcore.machine_flags; lc->preempt_count = S390_lowcore.preempt_count; - lc->stfl_fac_list = S390_lowcore.stfl_fac_list; - memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, - sizeof(lc->stfle_fac_list)); - memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list, - sizeof(lc->alt_stfle_fac_list)); nmi_alloc_boot_cpu(lc); lc->sys_enter_timer = S390_lowcore.sys_enter_timer; lc->exit_timer = S390_lowcore.exit_timer; @@ -568,53 +544,10 @@ static void __init setup_resources(void) #endif } -static void __init setup_ident_map_size(void) +static void __init setup_memory_end(void) { - unsigned long vmax, tmp; - - /* Choose kernel address space layout: 3 or 4 levels. */ - tmp = ident_map_size / PAGE_SIZE; - tmp = tmp * (sizeof(struct page) + PAGE_SIZE); - if (tmp + vmalloc_size + MODULES_LEN <= _REGION2_SIZE) - vmax = _REGION2_SIZE; /* 3-level kernel page table */ - else - vmax = _REGION1_SIZE; /* 4-level kernel page table */ - /* module area is at the end of the kernel address space. */ - MODULES_END = vmax; - if (is_prot_virt_host()) - adjust_to_uv_max(&MODULES_END); -#ifdef CONFIG_KASAN - vmax = _REGION1_SIZE; - MODULES_END = kasan_vmax; -#endif - MODULES_VADDR = MODULES_END - MODULES_LEN; - VMALLOC_END = MODULES_VADDR; - VMALLOC_START = VMALLOC_END - vmalloc_size; - - /* Split remaining virtual space between 1:1 mapping & vmemmap array */ - tmp = VMALLOC_START / (PAGE_SIZE + sizeof(struct page)); - /* vmemmap contains a multiple of PAGES_PER_SECTION struct pages */ - tmp = SECTION_ALIGN_UP(tmp); - tmp = VMALLOC_START - tmp * sizeof(struct page); - tmp &= ~((vmax >> 11) - 1); /* align to page table level */ - tmp = min(tmp, 1UL << MAX_PHYSMEM_BITS); - vmemmap = (struct page *) tmp; - - /* Take care that ident_map_size <= vmemmap */ - ident_map_size = min(ident_map_size, (unsigned long)vmemmap); -#ifdef CONFIG_KASAN - ident_map_size = min(ident_map_size, KASAN_SHADOW_START); -#endif - vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); -#ifdef CONFIG_KASAN - /* move vmemmap above kasan shadow only if stands in a way */ - if (KASAN_SHADOW_END > (unsigned long)vmemmap && - (unsigned long)vmemmap + vmemmap_size > KASAN_SHADOW_START) - vmemmap = max(vmemmap, (struct page *)KASAN_SHADOW_END); -#endif - max_pfn = max_low_pfn = PFN_DOWN(ident_map_size); memblock_remove(ident_map_size, ULONG_MAX); - + max_pfn = max_low_pfn = PFN_DOWN(ident_map_size); pr_notice("The maximum memory size is %luMB\n", ident_map_size >> 20); } @@ -652,30 +585,6 @@ static void __init reserve_above_ident_map(void) memblock_reserve(ident_map_size, ULONG_MAX); } -/* - * Make sure that oldmem, where the dump is stored, is protected - */ -static void __init reserve_oldmem(void) -{ -#ifdef CONFIG_CRASH_DUMP - if (OLDMEM_BASE) - /* Forget all memory above the running kdump system */ - memblock_reserve(OLDMEM_SIZE, (phys_addr_t)ULONG_MAX); -#endif -} - -/* - * Make sure that oldmem, where the dump is stored, is protected - */ -static void __init remove_oldmem(void) -{ -#ifdef CONFIG_CRASH_DUMP - if (OLDMEM_BASE) - /* Forget all memory above the running kdump system */ - memblock_remove(OLDMEM_SIZE, (phys_addr_t)ULONG_MAX); -#endif -} - /* * Reserve memory for kdump kernel to be loaded with kexec */ @@ -1141,7 +1050,6 @@ void __init setup_arch(char **cmdline_p) /* Do some memory reservations *before* memory is added to memblock */ reserve_above_ident_map(); - reserve_oldmem(); reserve_kernel(); reserve_initrd(); reserve_certificate_list(); @@ -1152,10 +1060,9 @@ void __init setup_arch(char **cmdline_p) memblock_add_mem_detect_info(); free_mem_detect_info(); - remove_oldmem(); setup_uv(); - setup_ident_map_size(); + setup_memory_end(); setup_memory(); dma_contiguous_reserve(ident_map_size); vmcp_cma_reserve(); diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 111909aeb8d2..ff42d3aa0f00 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -74,7 +74,6 @@ enum { static DEFINE_PER_CPU(struct cpu *, cpu_device); struct pcpu { - struct lowcore *lowcore; /* lowcore page(s) for the cpu */ unsigned long ec_mask; /* bit mask for ec_xxx functions */ unsigned long ec_clk; /* sigp timestamp for ec_xxx */ signed char state; /* physical cpu state */ @@ -194,20 +193,12 @@ static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) unsigned long async_stack, nodat_stack, mcck_stack; struct lowcore *lc; - if (pcpu != &pcpu_devices[0]) { - pcpu->lowcore = (struct lowcore *) - __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); - nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); - if (!pcpu->lowcore || !nodat_stack) - goto out; - } else { - nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET; - } + lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); + nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); async_stack = stack_alloc(); mcck_stack = stack_alloc(); - if (!async_stack || !mcck_stack) - goto out_stack; - lc = pcpu->lowcore; + if (!lc || !nodat_stack || !async_stack || !mcck_stack) + goto out; memcpy(lc, &S390_lowcore, 512); memset((char *) lc + 512, 0, sizeof(*lc) - 512); lc->async_stack = async_stack + STACK_INIT_OFFSET; @@ -220,45 +211,42 @@ static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); if (nmi_alloc_per_cpu(lc)) - goto out_stack; + goto out; lowcore_ptr[cpu] = lc; pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); return 0; -out_stack: +out: stack_free(mcck_stack); stack_free(async_stack); -out: - if (pcpu != &pcpu_devices[0]) { - free_pages(nodat_stack, THREAD_SIZE_ORDER); - free_pages((unsigned long) pcpu->lowcore, LC_ORDER); - } + free_pages(nodat_stack, THREAD_SIZE_ORDER); + free_pages((unsigned long) lc, LC_ORDER); return -ENOMEM; } static void pcpu_free_lowcore(struct pcpu *pcpu) { - unsigned long async_stack, nodat_stack, mcck_stack, lowcore; - - nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET; - async_stack = pcpu->lowcore->async_stack - STACK_INIT_OFFSET; - mcck_stack = pcpu->lowcore->mcck_stack - STACK_INIT_OFFSET; - lowcore = (unsigned long) pcpu->lowcore; + unsigned long async_stack, nodat_stack, mcck_stack; + struct lowcore *lc; + int cpu; + cpu = pcpu - pcpu_devices; + lc = lowcore_ptr[cpu]; + nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET; + async_stack = lc->async_stack - STACK_INIT_OFFSET; + mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); - lowcore_ptr[pcpu - pcpu_devices] = NULL; - nmi_free_per_cpu(pcpu->lowcore); + lowcore_ptr[cpu] = NULL; + nmi_free_per_cpu(lc); stack_free(async_stack); stack_free(mcck_stack); - if (pcpu == &pcpu_devices[0]) - return; free_pages(nodat_stack, THREAD_SIZE_ORDER); - free_pages(lowcore, LC_ORDER); + free_pages((unsigned long) lc, LC_ORDER); } static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) { - struct lowcore *lc = pcpu->lowcore; + struct lowcore *lc = lowcore_ptr[cpu]; cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); @@ -275,17 +263,16 @@ static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) lc->cregs_save_area[1] = lc->kernel_asce; lc->cregs_save_area[7] = lc->user_asce; save_access_regs((unsigned int *) lc->access_regs_save_area); - memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, - sizeof(lc->stfle_fac_list)); - memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list, - sizeof(lc->alt_stfle_fac_list)); arch_spin_lock_setup(cpu); } static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) { - struct lowcore *lc = pcpu->lowcore; + struct lowcore *lc; + int cpu; + cpu = pcpu - pcpu_devices; + lc = lowcore_ptr[cpu]; lc->kernel_stack = (unsigned long) task_stack_page(tsk) + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); lc->current_task = (unsigned long) tsk; @@ -301,8 +288,11 @@ static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) { - struct lowcore *lc = pcpu->lowcore; + struct lowcore *lc; + int cpu; + cpu = pcpu - pcpu_devices; + lc = lowcore_ptr[cpu]; lc->restart_stack = lc->nodat_stack; lc->restart_fn = (unsigned long) func; lc->restart_data = (unsigned long) data; @@ -387,7 +377,7 @@ void smp_call_online_cpu(void (*func)(void *), void *data) */ void smp_call_ipl_cpu(void (*func)(void *), void *data) { - struct lowcore *lc = pcpu_devices->lowcore; + struct lowcore *lc = lowcore_ptr[0]; if (pcpu_devices[0].address == stap()) lc = &S390_lowcore; @@ -600,18 +590,21 @@ EXPORT_SYMBOL(smp_ctl_clear_bit); int smp_store_status(int cpu) { - struct pcpu *pcpu = pcpu_devices + cpu; + struct lowcore *lc; + struct pcpu *pcpu; unsigned long pa; - pa = __pa(&pcpu->lowcore->floating_pt_save_area); + pcpu = pcpu_devices + cpu; + lc = lowcore_ptr[cpu]; + pa = __pa(&lc->floating_pt_save_area); if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, pa) != SIGP_CC_ORDER_CODE_ACCEPTED) return -EIO; if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) return 0; - pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK); + pa = __pa(lc->mcesad & MCESA_ORIGIN_MASK); if (MACHINE_HAS_GS) - pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK; + pa |= lc->mcesad & MCESA_LC_MASK; if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, pa) != SIGP_CC_ORDER_CODE_ACCEPTED) return -EIO; @@ -1011,7 +1004,6 @@ void __init smp_prepare_boot_cpu(void) WARN_ON(!cpu_present(0) || !cpu_online(0)); pcpu->state = CPU_STATE_CONFIGURED; - pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix(); S390_lowcore.percpu_offset = __per_cpu_offset[0]; smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); } @@ -1237,3 +1229,54 @@ out: return rc; } subsys_initcall(s390_smp_init); + +static __always_inline void set_new_lowcore(struct lowcore *lc) +{ + union register_pair dst, src; + u32 pfx; + + src.even = (unsigned long) &S390_lowcore; + src.odd = sizeof(S390_lowcore); + dst.even = (unsigned long) lc; + dst.odd = sizeof(*lc); + pfx = (unsigned long) lc; + + asm volatile( + " mvcl %[dst],%[src]\n" + " spx %[pfx]\n" + : [dst] "+&d" (dst.pair), [src] "+&d" (src.pair) + : [pfx] "Q" (pfx) + : "memory", "cc"); +} + +static int __init smp_reinit_ipl_cpu(void) +{ + unsigned long async_stack, nodat_stack, mcck_stack; + struct lowcore *lc, *lc_ipl; + unsigned long flags; + + lc_ipl = lowcore_ptr[0]; + lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); + nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); + async_stack = stack_alloc(); + mcck_stack = stack_alloc(); + if (!lc || !nodat_stack || !async_stack || !mcck_stack) + panic("Couldn't allocate memory"); + + local_irq_save(flags); + local_mcck_disable(); + set_new_lowcore(lc); + S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET; + S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET; + S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET; + lowcore_ptr[0] = lc; + local_mcck_enable(); + local_irq_restore(flags); + + free_pages(lc_ipl->async_stack - STACK_INIT_OFFSET, THREAD_SIZE_ORDER); + memblock_free_late(lc_ipl->mcck_stack - STACK_INIT_OFFSET, THREAD_SIZE); + memblock_free_late((unsigned long) lc_ipl, sizeof(*lc_ipl)); + + return 0; +} +early_initcall(smp_reinit_ipl_cpu); diff --git a/arch/s390/kernel/sthyi.c b/arch/s390/kernel/sthyi.c index 888cc2f166db..4d141e2c132e 100644 --- a/arch/s390/kernel/sthyi.c +++ b/arch/s390/kernel/sthyi.c @@ -395,19 +395,18 @@ out: static int sthyi(u64 vaddr, u64 *rc) { - register u64 code asm("0") = 0; - register u64 addr asm("2") = vaddr; - register u64 rcode asm("3"); + union register_pair r1 = { .even = 0, }; /* subcode */ + union register_pair r2 = { .even = vaddr, }; int cc; asm volatile( - ".insn rre,0xB2560000,%[code],%[addr]\n" + ".insn rre,0xB2560000,%[r1],%[r2]\n" "ipm %[cc]\n" "srl %[cc],28\n" - : [cc] "=d" (cc), "=d" (rcode) - : [code] "d" (code), [addr] "a" (addr) + : [cc] "=&d" (cc), [r2] "+&d" (r2.pair) + : [r1] "d" (r1.pair) : "memory", "cc"); - *rc = rcode; + *rc = r2.odd; return cc; } diff --git a/arch/s390/kernel/syscall.c b/arch/s390/kernel/syscall.c index 4e5cc7d2364e..76f7916cc30f 100644 --- a/arch/s390/kernel/syscall.c +++ b/arch/s390/kernel/syscall.c @@ -144,11 +144,8 @@ void noinstr __do_syscall(struct pt_regs *regs, int per_trap) { add_random_kstack_offset(); enter_from_user_mode(regs); - - memcpy(®s->gprs[8], S390_lowcore.save_area_sync, 8 * sizeof(unsigned long)); - memcpy(®s->int_code, &S390_lowcore.svc_ilc, sizeof(regs->int_code)); regs->psw = S390_lowcore.svc_old_psw; - + regs->int_code = S390_lowcore.svc_int_code; update_timer_sys(); local_irq_enable(); diff --git a/arch/s390/kernel/sysinfo.c b/arch/s390/kernel/sysinfo.c index 2ac3c9b56a13..ef3f2659876c 100644 --- a/arch/s390/kernel/sysinfo.c +++ b/arch/s390/kernel/sysinfo.c @@ -25,19 +25,22 @@ int topology_max_mnest; static inline int __stsi(void *sysinfo, int fc, int sel1, int sel2, int *lvl) { - register int r0 asm("0") = (fc << 28) | sel1; - register int r1 asm("1") = sel2; + int r0 = (fc << 28) | sel1; int rc = 0; asm volatile( - " stsi 0(%3)\n" + " lr 0,%[r0]\n" + " lr 1,%[r1]\n" + " stsi 0(%[sysinfo])\n" "0: jz 2f\n" - "1: lhi %1,%4\n" - "2:\n" + "1: lhi %[rc],%[retval]\n" + "2: lr %[r0],0\n" EX_TABLE(0b, 1b) - : "+d" (r0), "+d" (rc) - : "d" (r1), "a" (sysinfo), "K" (-EOPNOTSUPP) - : "cc", "memory"); + : [r0] "+d" (r0), [rc] "+d" (rc) + : [r1] "d" (sel2), + [sysinfo] "a" (sysinfo), + [retval] "K" (-EOPNOTSUPP) + : "cc", "0", "1", "memory"); *lvl = ((unsigned int) r0) >> 28; return rc; } diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c index 8dd23c703718..019c5748b607 100644 --- a/arch/s390/kernel/traps.c +++ b/arch/s390/kernel/traps.c @@ -36,7 +36,7 @@ static inline void __user *get_trap_ip(struct pt_regs *regs) unsigned long address; if (regs->int_code & 0x200) - address = *(unsigned long *)(current->thread.trap_tdb + 24); + address = current->thread.trap_tdb.data[3]; else address = regs->psw.addr; return (void __user *) (address - (regs->int_code >> 16)); @@ -318,7 +318,7 @@ void noinstr __do_pgm_check(struct pt_regs *regs) if (S390_lowcore.pgm_code & 0x0200) { /* transaction abort */ - memcpy(¤t->thread.trap_tdb, &S390_lowcore.pgm_tdb, 256); + current->thread.trap_tdb = S390_lowcore.pgm_tdb; } if (S390_lowcore.pgm_code & PGM_INT_CODE_PER) { diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index 370f664580af..6be2167943bb 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -52,7 +52,7 @@ void __init setup_uv(void) unsigned long uv_stor_base; /* - * keep these conditions in line with kasan init code has_uv_sec_stor_limit() + * keep these conditions in line with has_uv_sec_stor_limit() */ if (!is_prot_virt_host()) return; @@ -91,12 +91,6 @@ fail: prot_virt_host = 0; } -void adjust_to_uv_max(unsigned long *vmax) -{ - if (uv_info.max_sec_stor_addr) - *vmax = min_t(unsigned long, *vmax, uv_info.max_sec_stor_addr); -} - /* * Requests the Ultravisor to pin the page in the shared state. This will * cause an intercept when the guest attempts to unshare the pinned page. diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index f9fb1e1d960d..b655a7d82bf0 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -234,7 +234,7 @@ static unsigned long kvm_s390_fac_size(void) BUILD_BUG_ON(SIZE_INTERNAL > S390_ARCH_FAC_MASK_SIZE_U64); BUILD_BUG_ON(SIZE_INTERNAL > S390_ARCH_FAC_LIST_SIZE_U64); BUILD_BUG_ON(SIZE_INTERNAL * sizeof(unsigned long) > - sizeof(S390_lowcore.stfle_fac_list)); + sizeof(stfle_fac_list)); return SIZE_INTERNAL; } @@ -1482,8 +1482,8 @@ static int kvm_s390_get_machine(struct kvm *kvm, struct kvm_device_attr *attr) mach->ibc = sclp.ibc; memcpy(&mach->fac_mask, kvm->arch.model.fac_mask, S390_ARCH_FAC_LIST_SIZE_BYTE); - memcpy((unsigned long *)&mach->fac_list, S390_lowcore.stfle_fac_list, - sizeof(S390_lowcore.stfle_fac_list)); + memcpy((unsigned long *)&mach->fac_list, stfle_fac_list, + sizeof(stfle_fac_list)); VM_EVENT(kvm, 3, "GET: host ibc: 0x%4.4x, host cpuid: 0x%16.16llx", kvm->arch.model.ibc, kvm->arch.model.cpuid); @@ -2707,10 +2707,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm->arch.model.fac_list = kvm->arch.sie_page2->fac_list; for (i = 0; i < kvm_s390_fac_size(); i++) { - kvm->arch.model.fac_mask[i] = S390_lowcore.stfle_fac_list[i] & + kvm->arch.model.fac_mask[i] = stfle_fac_list[i] & (kvm_s390_fac_base[i] | kvm_s390_fac_ext[i]); - kvm->arch.model.fac_list[i] = S390_lowcore.stfle_fac_list[i] & + kvm->arch.model.fac_list[i] = stfle_fac_list[i] & kvm_s390_fac_base[i]; } kvm->arch.model.subfuncs = kvm_s390_available_subfunc; @@ -5079,7 +5079,7 @@ static int __init kvm_s390_init(void) for (i = 0; i < 16; i++) kvm_s390_fac_base[i] |= - S390_lowcore.stfle_fac_list[i] & nonhyp_mask(i); + stfle_fac_list[i] & nonhyp_mask(i); return kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); } diff --git a/arch/s390/lib/string.c b/arch/s390/lib/string.c index 93b3209b94a2..ec5b76bde4d8 100644 --- a/arch/s390/lib/string.c +++ b/arch/s390/lib/string.c @@ -18,23 +18,30 @@ */ static inline char *__strend(const char *s) { - register unsigned long r0 asm("0") = 0; + unsigned long e = 0; - asm volatile ("0: srst %0,%1\n" - " jo 0b" - : "+d" (r0), "+a" (s) : : "cc", "memory"); - return (char *) r0; + asm volatile( + " lghi 0,0\n" + "0: srst %[e],%[s]\n" + " jo 0b\n" + : [e] "+&a" (e), [s] "+&a" (s) + : + : "cc", "memory", "0"); + return (char *)e; } static inline char *__strnend(const char *s, size_t n) { - register unsigned long r0 asm("0") = 0; const char *p = s + n; - asm volatile ("0: srst %0,%1\n" - " jo 0b" - : "+d" (p), "+a" (s) : "d" (r0) : "cc", "memory"); - return (char *) p; + asm volatile( + " lghi 0,0\n" + "0: srst %[p],%[s]\n" + " jo 0b\n" + : [p] "+&d" (p), [s] "+&a" (s) + : + : "cc", "memory", "0"); + return (char *)p; } /** @@ -76,13 +83,15 @@ EXPORT_SYMBOL(strnlen); #ifdef __HAVE_ARCH_STRCPY char *strcpy(char *dest, const char *src) { - register int r0 asm("0") = 0; char *ret = dest; - asm volatile ("0: mvst %0,%1\n" - " jo 0b" - : "+&a" (dest), "+&a" (src) : "d" (r0) - : "cc", "memory" ); + asm volatile( + " lghi 0,0\n" + "0: mvst %[dest],%[src]\n" + " jo 0b\n" + : [dest] "+&a" (dest), [src] "+&a" (src) + : + : "cc", "memory", "0"); return ret; } EXPORT_SYMBOL(strcpy); @@ -144,16 +153,18 @@ EXPORT_SYMBOL(strncpy); #ifdef __HAVE_ARCH_STRCAT char *strcat(char *dest, const char *src) { - register int r0 asm("0") = 0; - unsigned long dummy; + unsigned long dummy = 0; char *ret = dest; - asm volatile ("0: srst %0,%1\n" - " jo 0b\n" - "1: mvst %0,%2\n" - " jo 1b" - : "=&a" (dummy), "+a" (dest), "+a" (src) - : "d" (r0), "0" (0UL) : "cc", "memory" ); + asm volatile( + " lghi 0,0\n" + "0: srst %[dummy],%[dest]\n" + " jo 0b\n" + "1: mvst %[dummy],%[src]\n" + " jo 1b\n" + : [dummy] "=&a" (dummy), [dest] "+&a" (dest), [src] "+&a" (src) + : + : "cc", "memory", "0"); return ret; } EXPORT_SYMBOL(strcat); @@ -221,18 +232,20 @@ EXPORT_SYMBOL(strncat); #ifdef __HAVE_ARCH_STRCMP int strcmp(const char *s1, const char *s2) { - register int r0 asm("0") = 0; int ret = 0; - asm volatile ("0: clst %2,%3\n" - " jo 0b\n" - " je 1f\n" - " ic %0,0(%2)\n" - " ic %1,0(%3)\n" - " sr %0,%1\n" - "1:" - : "+d" (ret), "+d" (r0), "+a" (s1), "+a" (s2) - : : "cc", "memory"); + asm volatile( + " lghi 0,0\n" + "0: clst %[s1],%[s2]\n" + " jo 0b\n" + " je 1f\n" + " ic %[ret],0(%[s1])\n" + " ic 0,0(%[s2])\n" + " sr %[ret],0\n" + "1:" + : [ret] "+&d" (ret), [s1] "+&a" (s1), [s2] "+&a" (s2) + : + : "cc", "memory", "0"); return ret; } EXPORT_SYMBOL(strcmp); @@ -261,18 +274,18 @@ EXPORT_SYMBOL(strrchr); static inline int clcle(const char *s1, unsigned long l1, const char *s2, unsigned long l2) { - register unsigned long r2 asm("2") = (unsigned long) s1; - register unsigned long r3 asm("3") = (unsigned long) l1; - register unsigned long r4 asm("4") = (unsigned long) s2; - register unsigned long r5 asm("5") = (unsigned long) l2; + union register_pair r1 = { .even = (unsigned long)s1, .odd = l1, }; + union register_pair r3 = { .even = (unsigned long)s2, .odd = l2, }; int cc; - asm volatile ("0: clcle %1,%3,0\n" - " jo 0b\n" - " ipm %0\n" - " srl %0,28" - : "=&d" (cc), "+a" (r2), "+a" (r3), - "+a" (r4), "+a" (r5) : : "cc", "memory"); + asm volatile( + "0: clcle %[r1],%[r3],0\n" + " jo 0b\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [r1] "+&d" (r1.pair), [r3] "+&d" (r3.pair) + : + : "cc", "memory"); return cc; } @@ -315,15 +328,18 @@ EXPORT_SYMBOL(strstr); #ifdef __HAVE_ARCH_MEMCHR void *memchr(const void *s, int c, size_t n) { - register int r0 asm("0") = (char) c; const void *ret = s + n; - asm volatile ("0: srst %0,%1\n" - " jo 0b\n" - " jl 1f\n" - " la %0,0\n" - "1:" - : "+a" (ret), "+&a" (s) : "d" (r0) : "cc", "memory"); + asm volatile( + " lgr 0,%[c]\n" + "0: srst %[ret],%[s]\n" + " jo 0b\n" + " jl 1f\n" + " la %[ret],0\n" + "1:" + : [ret] "+&a" (ret), [s] "+&a" (s) + : [c] "d" (c) + : "cc", "memory", "0"); return (void *) ret; } EXPORT_SYMBOL(memchr); @@ -360,13 +376,16 @@ EXPORT_SYMBOL(memcmp); #ifdef __HAVE_ARCH_MEMSCAN void *memscan(void *s, int c, size_t n) { - register int r0 asm("0") = (char) c; const void *ret = s + n; - asm volatile ("0: srst %0,%1\n" - " jo 0b\n" - : "+a" (ret), "+&a" (s) : "d" (r0) : "cc", "memory"); - return (void *) ret; + asm volatile( + " lgr 0,%[c]\n" + "0: srst %[ret],%[s]\n" + " jo 0b\n" + : [ret] "+&a" (ret), [s] "+&a" (s) + : [c] "d" (c) + : "cc", "memory", "0"); + return (void *)ret; } EXPORT_SYMBOL(memscan); #endif diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c index 2fece1fd210a..67606d932825 100644 --- a/arch/s390/lib/uaccess.c +++ b/arch/s390/lib/uaccess.c @@ -61,11 +61,11 @@ static inline int copy_with_mvcos(void) static inline unsigned long copy_from_user_mvcos(void *x, const void __user *ptr, unsigned long size) { - register unsigned long reg0 asm("0") = 0x81UL; unsigned long tmp1, tmp2; tmp1 = -4096UL; asm volatile( + " lghi 0,%[spec]\n" "0: .insn ss,0xc80000000000,0(%0,%2),0(%1),0\n" "6: jz 4f\n" "1: algr %0,%3\n" @@ -84,7 +84,8 @@ static inline unsigned long copy_from_user_mvcos(void *x, const void __user *ptr "5:\n" EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b) : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) - : "d" (reg0) : "cc", "memory"); + : [spec] "K" (0x81UL) + : "cc", "memory", "0"); return size; } @@ -133,11 +134,11 @@ EXPORT_SYMBOL(raw_copy_from_user); static inline unsigned long copy_to_user_mvcos(void __user *ptr, const void *x, unsigned long size) { - register unsigned long reg0 asm("0") = 0x810000UL; unsigned long tmp1, tmp2; tmp1 = -4096UL; asm volatile( + " llilh 0,%[spec]\n" "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n" "6: jz 4f\n" "1: algr %0,%3\n" @@ -156,7 +157,8 @@ static inline unsigned long copy_to_user_mvcos(void __user *ptr, const void *x, "5:\n" EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b) : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) - : "d" (reg0) : "cc", "memory"); + : [spec] "K" (0x81UL) + : "cc", "memory", "0"); return size; } @@ -205,12 +207,12 @@ EXPORT_SYMBOL(raw_copy_to_user); static inline unsigned long copy_in_user_mvcos(void __user *to, const void __user *from, unsigned long size) { - register unsigned long reg0 asm("0") = 0x810081UL; unsigned long tmp1, tmp2; tmp1 = -4096UL; /* FIXME: copy with reduced length. */ asm volatile( + " lgr 0,%[spec]\n" "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n" " jz 2f\n" "1: algr %0,%3\n" @@ -221,7 +223,8 @@ static inline unsigned long copy_in_user_mvcos(void __user *to, const void __use "3: \n" EX_TABLE(0b,3b) : "+a" (size), "+a" (to), "+a" (from), "+a" (tmp1), "=a" (tmp2) - : "d" (reg0) : "cc", "memory"); + : [spec] "d" (0x810081UL) + : "cc", "memory"); return size; } @@ -266,11 +269,11 @@ EXPORT_SYMBOL(raw_copy_in_user); static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size) { - register unsigned long reg0 asm("0") = 0x810000UL; unsigned long tmp1, tmp2; tmp1 = -4096UL; asm volatile( + " llilh 0,%[spec]\n" "0: .insn ss,0xc80000000000,0(%0,%1),0(%4),0\n" " jz 4f\n" "1: algr %0,%2\n" @@ -288,7 +291,8 @@ static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size "5:\n" EX_TABLE(0b,2b) EX_TABLE(3b,5b) : "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2) - : "a" (empty_zero_page), "d" (reg0) : "cc", "memory"); + : "a" (empty_zero_page), [spec] "K" (0x81UL) + : "cc", "memory", "0"); return size; } @@ -338,10 +342,10 @@ EXPORT_SYMBOL(__clear_user); static inline unsigned long strnlen_user_srst(const char __user *src, unsigned long size) { - register unsigned long reg0 asm("0") = 0; unsigned long tmp1, tmp2; asm volatile( + " lghi 0,0\n" " la %2,0(%1)\n" " la %3,0(%0,%1)\n" " slgr %0,%0\n" @@ -353,7 +357,8 @@ static inline unsigned long strnlen_user_srst(const char __user *src, "1: sacf 768\n" EX_TABLE(0b,1b) : "+a" (size), "+a" (src), "=a" (tmp1), "=a" (tmp2) - : "d" (reg0) : "cc", "memory"); + : + : "cc", "memory", "0"); return size; } diff --git a/arch/s390/lib/xor.c b/arch/s390/lib/xor.c index 29d9470dbceb..a963c3d8ad0d 100644 --- a/arch/s390/lib/xor.c +++ b/arch/s390/lib/xor.c @@ -91,9 +91,6 @@ static void xor_xc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, static void xor_xc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4, unsigned long *p5) { - /* Get around a gcc oddity */ - register unsigned long *reg7 asm ("7") = p5; - asm volatile( " larl 1,2f\n" " aghi %0,-1\n" @@ -122,7 +119,7 @@ static void xor_xc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, " xc 0(1,%1),0(%5)\n" "3:\n" : "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4), - "+a" (reg7) + "+a" (p5) : : "0", "1", "cc", "memory"); } diff --git a/arch/s390/mm/kasan_init.c b/arch/s390/mm/kasan_init.c index db4d303aaaa9..a0fdc6dc5f9d 100644 --- a/arch/s390/mm/kasan_init.c +++ b/arch/s390/mm/kasan_init.c @@ -13,7 +13,6 @@ #include #include -unsigned long kasan_vmax; static unsigned long segment_pos __initdata; static unsigned long segment_low __initdata; static unsigned long pgalloc_pos __initdata; @@ -251,28 +250,9 @@ static void __init kasan_early_detect_facilities(void) } } -static bool __init has_uv_sec_stor_limit(void) -{ - /* - * keep these conditions in line with setup_uv() - */ - if (!is_prot_virt_host()) - return false; - - if (is_prot_virt_guest()) - return false; - - if (!test_facility(158)) - return false; - - return !!uv_info.max_sec_stor_addr; -} - void __init kasan_early_init(void) { - unsigned long untracked_mem_end; unsigned long shadow_alloc_size; - unsigned long vmax_unlimited; unsigned long initrd_end; unsigned long memsize; unsigned long pgt_prot = pgprot_val(PAGE_KERNEL_RO); @@ -306,9 +286,6 @@ void __init kasan_early_init(void) BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_START, P4D_SIZE)); BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_END, P4D_SIZE)); crst_table_init((unsigned long *)early_pg_dir, _REGION2_ENTRY_EMPTY); - untracked_mem_end = kasan_vmax = vmax_unlimited = _REGION1_SIZE; - if (has_uv_sec_stor_limit()) - kasan_vmax = min(vmax_unlimited, uv_info.max_sec_stor_addr); /* init kasan zero shadow */ crst_table_init((unsigned long *)kasan_early_shadow_p4d, @@ -375,18 +352,18 @@ void __init kasan_early_init(void) */ /* populate kasan shadow (for identity mapping and zero page mapping) */ kasan_early_pgtable_populate(__sha(0), __sha(memsize), POPULATE_MAP); - if (IS_ENABLED(CONFIG_MODULES)) - untracked_mem_end = kasan_vmax - MODULES_LEN; if (IS_ENABLED(CONFIG_KASAN_VMALLOC)) { - untracked_mem_end = kasan_vmax - vmalloc_size - MODULES_LEN; /* shallowly populate kasan shadow for vmalloc and modules */ - kasan_early_pgtable_populate(__sha(untracked_mem_end), __sha(kasan_vmax), + kasan_early_pgtable_populate(__sha(VMALLOC_START), __sha(MODULES_END), POPULATE_SHALLOW); } /* populate kasan shadow for untracked memory */ - kasan_early_pgtable_populate(__sha(ident_map_size), __sha(untracked_mem_end), + kasan_early_pgtable_populate(__sha(ident_map_size), + IS_ENABLED(CONFIG_KASAN_VMALLOC) ? + __sha(VMALLOC_START) : + __sha(MODULES_VADDR), POPULATE_ZERO_SHADOW); - kasan_early_pgtable_populate(__sha(kasan_vmax), __sha(vmax_unlimited), + kasan_early_pgtable_populate(__sha(MODULES_END), __sha(_REGION1_SIZE), POPULATE_ZERO_SHADOW); /* memory allocated for identity mapping structs will be freed later */ pgalloc_freeable = pgalloc_pos; diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 1d17413b319a..1f1f906344ff 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -79,22 +79,21 @@ notrace void *s390_kernel_write(void *dst, const void *src, size_t size) static int __no_sanitize_address __memcpy_real(void *dest, void *src, size_t count) { - register unsigned long _dest asm("2") = (unsigned long) dest; - register unsigned long _len1 asm("3") = (unsigned long) count; - register unsigned long _src asm("4") = (unsigned long) src; - register unsigned long _len2 asm("5") = (unsigned long) count; + union register_pair _dst, _src; int rc = -EFAULT; + _dst.even = (unsigned long) dest; + _dst.odd = (unsigned long) count; + _src.even = (unsigned long) src; + _src.odd = (unsigned long) count; asm volatile ( - "0: mvcle %1,%2,0x0\n" + "0: mvcle %[dst],%[src],0\n" "1: jo 0b\n" - " lhi %0,0x0\n" + " lhi %[rc],0\n" "2:\n" EX_TABLE(1b,2b) - : "+d" (rc), "+d" (_dest), "+d" (_src), "+d" (_len1), - "+d" (_len2), "=m" (*((long *) dest)) - : "m" (*((long *) src)) - : "cc", "memory"); + : [rc] "+&d" (rc), [dst] "+&d" (_dst.pair), [src] "+&d" (_src.pair) + : : "cc", "memory"); return rc; } diff --git a/arch/s390/mm/page-states.c b/arch/s390/mm/page-states.c index 7f0e154a470a..68b153083a92 100644 --- a/arch/s390/mm/page-states.c +++ b/arch/s390/mm/page-states.c @@ -31,17 +31,17 @@ __setup("cmma=", cmma); static inline int cmma_test_essa(void) { - register unsigned long tmp asm("0") = 0; - register int rc asm("1"); + unsigned long tmp = 0; + int rc = -EOPNOTSUPP; /* test ESSA_GET_STATE */ asm volatile( - " .insn rrf,0xb9ab0000,%1,%1,%2,0\n" - "0: la %0,0\n" + " .insn rrf,0xb9ab0000,%[tmp],%[tmp],%[cmd],0\n" + "0: la %[rc],0\n" "1:\n" EX_TABLE(0b,1b) - : "=&d" (rc), "+&d" (tmp) - : "i" (ESSA_GET_STATE), "0" (-EOPNOTSUPP)); + : [rc] "+&d" (rc), [tmp] "+&d" (tmp) + : [cmd] "i" (ESSA_GET_STATE)); return rc; } diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 18205f851c24..eec3a9d7176e 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -691,7 +691,7 @@ static void ptep_zap_swap_entry(struct mm_struct *mm, swp_entry_t entry) if (!non_swap_entry(entry)) dec_mm_counter(mm, MM_SWAPENTS); else if (is_migration_entry(entry)) { - struct page *page = migration_entry_to_page(entry); + struct page *page = pfn_swap_entry_to_page(entry); dec_mm_counter(mm, mm_counter(page)); } diff --git a/arch/s390/pci/pci_insn.c b/arch/s390/pci/pci_insn.c index 02f9505c99a8..2e43996159f0 100644 --- a/arch/s390/pci/pci_insn.c +++ b/arch/s390/pci/pci_insn.c @@ -63,16 +63,15 @@ u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status) /* Refresh PCI Translations */ static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status) { - register u64 __addr asm("2") = addr; - register u64 __range asm("3") = range; + union register_pair addr_range = {.even = addr, .odd = range}; u8 cc; asm volatile ( - " .insn rre,0xb9d30000,%[fn],%[addr]\n" + " .insn rre,0xb9d30000,%[fn],%[addr_range]\n" " ipm %[cc]\n" " srl %[cc],28\n" : [cc] "=d" (cc), [fn] "+d" (fn) - : [addr] "d" (__addr), "d" (__range) + : [addr_range] "d" (addr_range.pair) : "cc"); *status = fn >> 24 & 0xff; return cc; @@ -113,21 +112,19 @@ int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib) /* PCI Load */ static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status) { - register u64 __req asm("2") = req; - register u64 __offset asm("3") = offset; + union register_pair req_off = {.even = req, .odd = offset}; int cc = -ENXIO; u64 __data; asm volatile ( - " .insn rre,0xb9d20000,%[data],%[req]\n" + " .insn rre,0xb9d20000,%[data],%[req_off]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) - : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req) - : "d" (__offset) - : "cc"); - *status = __req >> 24 & 0xff; + : [cc] "+d" (cc), [data] "=d" (__data), + [req_off] "+&d" (req_off.pair) :: "cc"); + *status = req_off.even >> 24 & 0xff; *data = __data; return cc; } @@ -173,21 +170,19 @@ static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr, static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status) { - register u64 addr asm("2") = ioaddr; - register u64 r3 asm("3") = len; + union register_pair ioaddr_len = {.even = ioaddr, .odd = len}; int cc = -ENXIO; u64 __data; asm volatile ( - " .insn rre,0xb9d60000,%[data],%[ioaddr]\n" + " .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) - : [cc] "+d" (cc), [data] "=d" (__data), "+d" (r3) - : [ioaddr] "d" (addr) - : "cc"); - *status = r3 >> 24 & 0xff; + : [cc] "+d" (cc), [data] "=d" (__data), + [ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc"); + *status = ioaddr_len.odd >> 24 & 0xff; *data = __data; return cc; } @@ -211,20 +206,19 @@ EXPORT_SYMBOL_GPL(zpci_load); /* PCI Store */ static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status) { - register u64 __req asm("2") = req; - register u64 __offset asm("3") = offset; + union register_pair req_off = {.even = req, .odd = offset}; int cc = -ENXIO; asm volatile ( - " .insn rre,0xb9d00000,%[data],%[req]\n" + " .insn rre,0xb9d00000,%[data],%[req_off]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) - : [cc] "+d" (cc), [req] "+d" (__req) - : "d" (__offset), [data] "d" (data) + : [cc] "+d" (cc), [req_off] "+&d" (req_off.pair) + : [data] "d" (data) : "cc"); - *status = __req >> 24 & 0xff; + *status = req_off.even >> 24 & 0xff; return cc; } @@ -257,20 +251,19 @@ static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data, static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status) { - register u64 addr asm("2") = ioaddr; - register u64 r3 asm("3") = len; + union register_pair ioaddr_len = {.even = ioaddr, .odd = len}; int cc = -ENXIO; asm volatile ( - " .insn rre,0xb9d40000,%[data],%[ioaddr]\n" + " .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) - : [cc] "+d" (cc), "+d" (r3) - : [data] "d" (data), [ioaddr] "d" (addr) - : "cc"); - *status = r3 >> 24 & 0xff; + : [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair) + : [data] "d" (data) + : "cc", "memory"); + *status = ioaddr_len.odd >> 24 & 0xff; return cc; } diff --git a/arch/s390/pci/pci_irq.c b/arch/s390/pci/pci_irq.c index 9dd5ad1b553d..9c7de9089939 100644 --- a/arch/s390/pci/pci_irq.c +++ b/arch/s390/pci/pci_irq.c @@ -35,7 +35,7 @@ static struct airq_iv *zpci_sbv; */ static struct airq_iv **zpci_ibv; -/* Modify PCI: Register adapter interruptions */ +/* Modify PCI: Register floating adapter interruptions */ static int zpci_set_airq(struct zpci_dev *zdev) { u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT); @@ -53,7 +53,7 @@ static int zpci_set_airq(struct zpci_dev *zdev) return zpci_mod_fc(req, &fib, &status) ? -EIO : 0; } -/* Modify PCI: Unregister adapter interruptions */ +/* Modify PCI: Unregister floating adapter interruptions */ static int zpci_clear_airq(struct zpci_dev *zdev) { u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT); @@ -98,6 +98,38 @@ static int zpci_clear_directed_irq(struct zpci_dev *zdev) return cc ? -EIO : 0; } +/* Register adapter interruptions */ +int zpci_set_irq(struct zpci_dev *zdev) +{ + int rc; + + if (irq_delivery == DIRECTED) + rc = zpci_set_directed_irq(zdev); + else + rc = zpci_set_airq(zdev); + + if (!rc) + zdev->irqs_registered = 1; + + return rc; +} + +/* Clear adapter interruptions */ +int zpci_clear_irq(struct zpci_dev *zdev) +{ + int rc; + + if (irq_delivery == DIRECTED) + rc = zpci_clear_directed_irq(zdev); + else + rc = zpci_clear_airq(zdev); + + if (!rc) + zdev->irqs_registered = 0; + + return rc; +} + static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest, bool force) { @@ -311,10 +343,7 @@ int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) zdev->msi_first_bit = bit; zdev->msi_nr_irqs = msi_vecs; - if (irq_delivery == DIRECTED) - rc = zpci_set_directed_irq(zdev); - else - rc = zpci_set_airq(zdev); + rc = zpci_set_irq(zdev); if (rc) return rc; @@ -328,10 +357,7 @@ void arch_teardown_msi_irqs(struct pci_dev *pdev) int rc; /* Disable interrupts */ - if (irq_delivery == DIRECTED) - rc = zpci_clear_directed_irq(zdev); - else - rc = zpci_clear_airq(zdev); + rc = zpci_clear_irq(zdev); if (rc) return; diff --git a/arch/s390/pci/pci_mmio.c b/arch/s390/pci/pci_mmio.c index 474617b88648..ae683aa623ac 100644 --- a/arch/s390/pci/pci_mmio.c +++ b/arch/s390/pci/pci_mmio.c @@ -49,8 +49,7 @@ static inline int __pcistg_mio_inuser( void __iomem *ioaddr, const void __user *src, u64 ulen, u8 *status) { - register u64 addr asm("2") = (u64 __force) ioaddr; - register u64 len asm("3") = ulen; + union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen}; int cc = -ENXIO; u64 val = 0; u64 cnt = ulen; @@ -68,7 +67,7 @@ static inline int __pcistg_mio_inuser( " aghi %[src],1\n" " ogr %[val],%[tmp]\n" " brctg %[cnt],0b\n" - "1: .insn rre,0xb9d40000,%[val],%[ioaddr]\n" + "1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n" "2: ipm %[cc]\n" " srl %[cc],28\n" "3: sacf 768\n" @@ -76,10 +75,9 @@ static inline int __pcistg_mio_inuser( : [src] "+a" (src), [cnt] "+d" (cnt), [val] "+d" (val), [tmp] "=d" (tmp), - [len] "+d" (len), [cc] "+d" (cc), - [ioaddr] "+a" (addr) + [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc", "memory"); - *status = len >> 24 & 0xff; + *status = ioaddr_len.odd >> 24 & 0xff; /* did we read everything from user memory? */ if (!cc && cnt != 0) @@ -195,8 +193,7 @@ static inline int __pcilg_mio_inuser( void __user *dst, const void __iomem *ioaddr, u64 ulen, u8 *status) { - register u64 addr asm("2") = (u64 __force) ioaddr; - register u64 len asm("3") = ulen; + union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen}; u64 cnt = ulen; int shift = ulen * 8; int cc = -ENXIO; @@ -209,7 +206,7 @@ static inline int __pcilg_mio_inuser( */ asm volatile ( " sacf 256\n" - "0: .insn rre,0xb9d60000,%[val],%[ioaddr]\n" + "0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n" "1: ipm %[cc]\n" " srl %[cc],28\n" " ltr %[cc],%[cc]\n" @@ -222,18 +219,17 @@ static inline int __pcilg_mio_inuser( "4: sacf 768\n" EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b) : - [cc] "+d" (cc), [val] "=d" (val), [len] "+d" (len), + [ioaddr_len] "+&d" (ioaddr_len.pair), + [cc] "+d" (cc), [val] "=d" (val), [dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp), [shift] "+d" (shift) - : - [ioaddr] "a" (addr) - : "cc", "memory"); + :: "cc", "memory"); /* did we write everything to the user space buffer? */ if (!cc && cnt != 0) cc = -EFAULT; - *status = len >> 24 & 0xff; + *status = ioaddr_len.odd >> 24 & 0xff; return cc; } diff --git a/arch/s390/purgatory/Makefile b/arch/s390/purgatory/Makefile index c57f8c40e992..21c4ebe29b9a 100644 --- a/arch/s390/purgatory/Makefile +++ b/arch/s390/purgatory/Makefile @@ -24,6 +24,7 @@ KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes KBUILD_CFLAGS += -Wno-pointer-sign -Wno-sign-compare KBUILD_CFLAGS += -fno-zero-initialized-in-bss -fno-builtin -ffreestanding KBUILD_CFLAGS += -c -MD -Os -m64 -msoft-float -fno-common +KBUILD_CFLAGS += -fno-stack-protector KBUILD_CFLAGS += $(CLANG_FLAGS) KBUILD_CFLAGS += $(call cc-option,-fno-PIE) KBUILD_AFLAGS := $(filter-out -DCC_USING_EXPOLINE,$(KBUILD_AFLAGS)) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 68129537e350..45a0549421cd 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -14,7 +14,6 @@ config SUPERH select ARCH_HIBERNATION_POSSIBLE if MMU select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_WANT_IPC_PARSE_VERSION - select CLKDEV_LOOKUP select CPU_NO_EFFICIENT_FFS select DMA_DECLARE_COHERENT select GENERIC_ATOMIC64 diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h index 0e6b0be25e33..a9e98233c4d4 100644 --- a/arch/sh/include/asm/pgalloc.h +++ b/arch/sh/include/asm/pgalloc.h @@ -30,7 +30,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } -#define pmd_pgtable(pmd) pmd_page(pmd) #define __pte_free_tlb(tlb,pte,addr) \ do { \ diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index 27751e9470df..d7ddb1ec86a0 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h @@ -59,8 +59,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val) /* Entries per level */ #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) -#define FIRST_USER_ADDRESS 0UL - #define PHYS_ADDR_MASK29 0x1fffffff #define PHYS_ADDR_MASK32 0xffffffff diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h deleted file mode 100644 index d311f00ed530..000000000000 --- a/arch/sh/include/asm/unaligned-sh4a.h +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_SH_UNALIGNED_SH4A_H -#define __ASM_SH_UNALIGNED_SH4A_H - -/* - * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. - * Support for 64-bit accesses are done through shifting and masking - * relative to the endianness. Unaligned stores are not supported by the - * instruction encoding, so these continue to use the packed - * struct. - * - * The same note as with the movli.l/movco.l pair applies here, as long - * as the load is guaranteed to be inlined, nothing else will hook in to - * r0 and we get the return value for free. - * - * NOTE: Due to the fact we require r0 encoding, care should be taken to - * avoid mixing these heavily with other r0 consumers, such as the atomic - * ops. Failure to adhere to this can result in the compiler running out - * of spill registers and blowing up when building at low optimization - * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. - */ -#include -#include -#include - -static inline u16 sh4a_get_unaligned_cpu16(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return p[0] | p[1] << 8; -#else - return p[0] << 8 | p[1]; -#endif -} - -static __always_inline u32 sh4a_get_unaligned_cpu32(const u8 *p) -{ - unsigned long unaligned; - - __asm__ __volatile__ ( - "movua.l @%1, %0\n\t" - : "=z" (unaligned) - : "r" (p) - ); - - return unaligned; -} - -/* - * Even though movua.l supports auto-increment on the read side, it can - * only store to r0 due to instruction encoding constraints, so just let - * the compiler sort it out on its own. - */ -static inline u64 sh4a_get_unaligned_cpu64(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return (u64)sh4a_get_unaligned_cpu32(p + 4) << 32 | - sh4a_get_unaligned_cpu32(p); -#else - return (u64)sh4a_get_unaligned_cpu32(p) << 32 | - sh4a_get_unaligned_cpu32(p + 4); -#endif -} - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpu(sh4a_get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpu(sh4a_get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpu(sh4a_get_unaligned_cpu64(p)); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpu(sh4a_get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpu(sh4a_get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpu(sh4a_get_unaligned_cpu64(p)); -} - -static inline void nonnative_put_le16(u16 val, u8 *p) -{ - *p++ = val; - *p++ = val >> 8; -} - -static inline void nonnative_put_le32(u32 val, u8 *p) -{ - nonnative_put_le16(val, p); - nonnative_put_le16(val >> 16, p + 2); -} - -static inline void nonnative_put_le64(u64 val, u8 *p) -{ - nonnative_put_le32(val, p); - nonnative_put_le32(val >> 32, p + 4); -} - -static inline void nonnative_put_be16(u16 val, u8 *p) -{ - *p++ = val >> 8; - *p++ = val; -} - -static inline void nonnative_put_be32(u32 val, u8 *p) -{ - nonnative_put_be16(val >> 16, p); - nonnative_put_be16(val, p + 2); -} - -static inline void nonnative_put_be64(u64 val, u8 *p) -{ - nonnative_put_be32(val >> 32, p); - nonnative_put_be32(val, p + 4); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - __put_unaligned_cpu16(val, p); -#else - nonnative_put_le16(val, p); -#endif -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - __put_unaligned_cpu32(val, p); -#else - nonnative_put_le32(val, p); -#endif -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - __put_unaligned_cpu64(val, p); -#else - nonnative_put_le64(val, p); -#endif -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ -#ifdef __BIG_ENDIAN - __put_unaligned_cpu16(val, p); -#else - nonnative_put_be16(val, p); -#endif -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ -#ifdef __BIG_ENDIAN - __put_unaligned_cpu32(val, p); -#else - nonnative_put_be32(val, p); -#endif -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ -#ifdef __BIG_ENDIAN - __put_unaligned_cpu64(val, p); -#else - nonnative_put_be64(val, p); -#endif -} - -/* - * While it's a bit non-obvious, even though the generic le/be wrappers - * use the __get/put_xxx prefixing, they actually wrap in to the - * non-prefixed get/put_xxx variants as provided above. - */ -#include - -#ifdef __LITTLE_ENDIAN -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#endif - -#endif /* __ASM_SH_UNALIGNED_SH4A_H */ diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h deleted file mode 100644 index 0c92e2c73af4..000000000000 --- a/arch/sh/include/asm/unaligned.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SH_UNALIGNED_H -#define _ASM_SH_UNALIGNED_H - -#ifdef CONFIG_CPU_SH4A -/* SH-4A can handle unaligned loads in a relatively neutered fashion. */ -#include -#else -/* Otherwise, SH can't handle unaligned accesses. */ -#include -#endif - -#endif /* _ASM_SH_UNALIGNED_H */ diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index c72f52c704cd..c5fa7932b550 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -59,6 +59,7 @@ config SPARC32 select CLZ_TAB select HAVE_UID16 select OLD_SIGACTION + select ZONE_DMA config SPARC64 def_bool 64BIT @@ -141,10 +142,6 @@ config HIGHMEM default y if SPARC32 select KMAP_LOCAL -config ZONE_DMA - bool - default y if SPARC32 - config GENERIC_ISA_DMA bool default y if SPARC32 diff --git a/arch/sparc/include/asm/pgalloc_32.h b/arch/sparc/include/asm/pgalloc_32.h index 9d353e6dc5a9..4f73e87b22a3 100644 --- a/arch/sparc/include/asm/pgalloc_32.h +++ b/arch/sparc/include/asm/pgalloc_32.h @@ -51,7 +51,6 @@ static inline void free_pmd_fast(pmd_t * pmd) #define __pmd_free_tlb(tlb, pmd, addr) pmd_free((tlb)->mm, pmd) #define pmd_populate(mm, pmd, pte) pmd_set(pmd, pte) -#define pmd_pgtable(pmd) (pgtable_t)__pmd_page(pmd) void pmd_set(pmd_t *pmdp, pte_t *ptep); #define pmd_populate_kernel pmd_populate diff --git a/arch/sparc/include/asm/pgalloc_64.h b/arch/sparc/include/asm/pgalloc_64.h index a8dafc550985..7b5561d17ab1 100644 --- a/arch/sparc/include/asm/pgalloc_64.h +++ b/arch/sparc/include/asm/pgalloc_64.h @@ -67,7 +67,6 @@ void pte_free(struct mm_struct *mm, pgtable_t ptepage); #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(MM, PMD, PTE) #define pmd_populate(MM, PMD, PTE) pmd_set(MM, PMD, PTE) -#define pmd_pgtable(PMD) ((pte_t *)pmd_page_vaddr(PMD)) void pgtable_free(void *table, bool is_page); diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h index a5cf79c149fe..ebaf374b55ab 100644 --- a/arch/sparc/include/asm/pgtable_32.h +++ b/arch/sparc/include/asm/pgtable_32.h @@ -48,7 +48,6 @@ unsigned long __init bootmem_init(unsigned long *pages_avail); #define PTRS_PER_PMD 64 #define PTRS_PER_PGD 256 #define USER_PTRS_PER_PGD PAGE_OFFSET / PGDIR_SIZE -#define FIRST_USER_ADDRESS 0UL #define PTE_SIZE (PTRS_PER_PTE*4) #define PAGE_NONE SRMMU_PAGE_NONE @@ -433,4 +432,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, /* We provide our own get_unmapped_area to cope with VA holes for userland */ #define HAVE_ARCH_UNMAPPED_AREA +#define pmd_pgtable(pmd) ((pgtable_t)__pmd_page(pmd)) + #endif /* !(_SPARC_PGTABLE_H) */ diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h index 550d3904de65..e0ee48ec3903 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h @@ -95,9 +95,6 @@ bool kern_addr_valid(unsigned long addr); #define PTRS_PER_PUD (1UL << PUD_BITS) #define PTRS_PER_PGD (1UL << PGDIR_BITS) -/* Kernel has a separate 44bit address space. */ -#define FIRST_USER_ADDRESS 0UL - #define pmd_ERROR(e) \ pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) @@ -377,8 +374,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t prot) #define pgprot_noncached pgprot_noncached #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) -extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, - struct page *page, int writable); +pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags); #define arch_make_huge_pte arch_make_huge_pte static inline unsigned long __pte_default_huge_mask(void) { @@ -1121,6 +1117,8 @@ extern unsigned long cmdline_memory_size; asmlinkage void do_sparc64_fault(struct pt_regs *regs); +#define pmd_pgtable(PMD) ((pte_t *)pmd_page_vaddr(PMD)) + #ifdef CONFIG_HUGETLB_PAGE #define pud_leaf_size pud_leaf_size diff --git a/arch/sparc/include/asm/unaligned.h b/arch/sparc/include/asm/unaligned.h deleted file mode 100644 index 7971d89d2f54..000000000000 --- a/arch/sparc/include/asm/unaligned.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SPARC_UNALIGNED_H -#define _ASM_SPARC_UNALIGNED_H - -#include -#include -#include -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* _ASM_SPARC_UNALIGNED_H */ diff --git a/arch/sparc/include/asm/vio.h b/arch/sparc/include/asm/vio.h index 059f0eb678e0..8a1a83bbb6d5 100644 --- a/arch/sparc/include/asm/vio.h +++ b/arch/sparc/include/asm/vio.h @@ -362,7 +362,7 @@ struct vio_driver { struct list_head node; const struct vio_device_id *id_table; int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); - int (*remove)(struct vio_dev *dev); + void (*remove)(struct vio_dev *dev); void (*shutdown)(struct vio_dev *dev); unsigned long driver_data; struct device_driver driver; diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index 522e5b51050c..4a5bdb0df779 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c @@ -1236,11 +1236,6 @@ out_err: return err; } -static int ds_remove(struct vio_dev *vdev) -{ - return 0; -} - static const struct vio_device_id ds_match[] = { { .type = "domain-services-port", @@ -1251,7 +1246,6 @@ static const struct vio_device_id ds_match[] = { static struct vio_driver ds_driver = { .id_table = ds_match, .probe = ds_probe, - .remove = ds_remove, .name = "ds", }; diff --git a/arch/sparc/kernel/sstate.c b/arch/sparc/kernel/sstate.c index ac8677c3841e..3bcc4ddc6911 100644 --- a/arch/sparc/kernel/sstate.c +++ b/arch/sparc/kernel/sstate.c @@ -6,6 +6,7 @@ #include #include +#include #include #include diff --git a/arch/sparc/kernel/vio.c b/arch/sparc/kernel/vio.c index 4f57056ed463..348a88691219 100644 --- a/arch/sparc/kernel/vio.c +++ b/arch/sparc/kernel/vio.c @@ -105,10 +105,10 @@ static int vio_device_remove(struct device *dev) * routines to do so at the moment. TBD */ - return drv->remove(vdev); + drv->remove(vdev); } - return 1; + return 0; } static ssize_t devspec_show(struct device *dev, diff --git a/arch/sparc/mm/hugetlbpage.c b/arch/sparc/mm/hugetlbpage.c index 04d8790f6c32..0f49fada2093 100644 --- a/arch/sparc/mm/hugetlbpage.c +++ b/arch/sparc/mm/hugetlbpage.c @@ -177,10 +177,8 @@ static pte_t hugepage_shift_to_tte(pte_t entry, unsigned int shift) return sun4u_hugepage_shift_to_tte(entry, shift); } -pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, - struct page *page, int writeable) +pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) { - unsigned int shift = huge_page_shift(hstate_vma(vma)); pte_t pte; pte = hugepage_shift_to_tte(entry, shift); @@ -188,7 +186,7 @@ pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, #ifdef CONFIG_SPARC64 /* If this vma has ADI enabled on it, turn on TTE.mcd */ - if (vma->vm_flags & VM_SPARC_ADI) + if (flags & VM_SPARC_ADI) return pte_mkmcd(pte); else return pte_mknotmcd(pte); diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 06e938d03f3b..1b23639e2fcd 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c index 1c70a31e7c5b..fbc623d2cc07 100644 --- a/arch/um/drivers/line.c +++ b/arch/um/drivers/line.c @@ -32,7 +32,7 @@ static irqreturn_t line_interrupt(int irq, void *data) * * Should be called while holding line->lock (this does not modify data). */ -static int write_room(struct line *line) +static unsigned int write_room(struct line *line) { int n; @@ -47,11 +47,11 @@ static int write_room(struct line *line) return n - 1; } -int line_write_room(struct tty_struct *tty) +unsigned int line_write_room(struct tty_struct *tty) { struct line *line = tty->driver_data; unsigned long flags; - int room; + unsigned int room; spin_lock_irqsave(&line->lock, flags); room = write_room(line); @@ -60,11 +60,11 @@ int line_write_room(struct tty_struct *tty) return room; } -int line_chars_in_buffer(struct tty_struct *tty) +unsigned int line_chars_in_buffer(struct tty_struct *tty) { struct line *line = tty->driver_data; unsigned long flags; - int ret; + unsigned int ret; spin_lock_irqsave(&line->lock, flags); /* write_room subtracts 1 for the needed NULL, so we readd it.*/ @@ -211,11 +211,6 @@ out_up: return ret; } -void line_set_termios(struct tty_struct *tty, struct ktermios * old) -{ - /* nothing */ -} - void line_throttle(struct tty_struct *tty) { struct line *line = tty->driver_data; diff --git a/arch/um/drivers/line.h b/arch/um/drivers/line.h index 01d21e76144f..bdb16b96e76f 100644 --- a/arch/um/drivers/line.h +++ b/arch/um/drivers/line.h @@ -66,11 +66,10 @@ extern int line_setup(char **conf, unsigned nlines, char **def, char *init, char *name); extern int line_write(struct tty_struct *tty, const unsigned char *buf, int len); -extern void line_set_termios(struct tty_struct *tty, struct ktermios * old); -extern int line_chars_in_buffer(struct tty_struct *tty); +extern unsigned int line_chars_in_buffer(struct tty_struct *tty); extern void line_flush_buffer(struct tty_struct *tty); extern void line_flush_chars(struct tty_struct *tty); -extern int line_write_room(struct tty_struct *tty); +extern unsigned int line_write_room(struct tty_struct *tty); extern void line_throttle(struct tty_struct *tty); extern void line_unthrottle(struct tty_struct *tty); diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index 6d00af25ec6b..6ead1e240457 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -140,7 +141,7 @@ void mconsole_proc(struct mc_request *req) mconsole_reply(req, "Proc not available", 1, 0); goto out; } - file = file_open_root(mnt->mnt_root, mnt, ptr, O_RDONLY, 0); + file = file_open_root_mnt(mnt, ptr, O_RDONLY, 0); if (IS_ERR(file)) { mconsole_reply(req, "Failed to open file", 1, 0); printk(KERN_ERR "open /proc/%s: %ld\n", ptr, PTR_ERR(file)); diff --git a/arch/um/drivers/ssl.c b/arch/um/drivers/ssl.c index 6476b28d7c5e..41eae2e8fb65 100644 --- a/arch/um/drivers/ssl.c +++ b/arch/um/drivers/ssl.c @@ -99,7 +99,6 @@ static const struct tty_operations ssl_ops = { .chars_in_buffer = line_chars_in_buffer, .flush_buffer = line_flush_buffer, .flush_chars = line_flush_chars, - .set_termios = line_set_termios, .throttle = line_throttle, .unthrottle = line_unthrottle, .install = ssl_install, diff --git a/arch/um/drivers/stdio_console.c b/arch/um/drivers/stdio_console.c index 37b127941e6f..e8b762f4d8c2 100644 --- a/arch/um/drivers/stdio_console.c +++ b/arch/um/drivers/stdio_console.c @@ -106,7 +106,6 @@ static const struct tty_operations console_ops = { .chars_in_buffer = line_chars_in_buffer, .flush_buffer = line_flush_buffer, .flush_chars = line_flush_chars, - .set_termios = line_set_termios, .throttle = line_throttle, .unthrottle = line_unthrottle, .hangup = line_hangup, diff --git a/arch/um/include/asm/pgalloc.h b/arch/um/include/asm/pgalloc.h index 2bbf28cf3aa9..8ec7cd46dd96 100644 --- a/arch/um/include/asm/pgalloc.h +++ b/arch/um/include/asm/pgalloc.h @@ -19,7 +19,6 @@ set_pmd(pmd, __pmd(_PAGE_TABLE + \ ((unsigned long long)page_to_pfn(pte) << \ (unsigned long long) PAGE_SHIFT))) -#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. diff --git a/arch/um/include/asm/pgtable-2level.h b/arch/um/include/asm/pgtable-2level.h index 32106d31e4ab..8256ecc5b919 100644 --- a/arch/um/include/asm/pgtable-2level.h +++ b/arch/um/include/asm/pgtable-2level.h @@ -23,7 +23,6 @@ #define PTRS_PER_PTE 1024 #define USER_PTRS_PER_PGD ((TASK_SIZE + (PGDIR_SIZE - 1)) / PGDIR_SIZE) #define PTRS_PER_PGD 1024 -#define FIRST_USER_ADDRESS 0UL #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), \ diff --git a/arch/um/include/asm/pgtable-3level.h b/arch/um/include/asm/pgtable-3level.h index 7e6a4180db9d..9289a86643a9 100644 --- a/arch/um/include/asm/pgtable-3level.h +++ b/arch/um/include/asm/pgtable-3level.h @@ -41,7 +41,6 @@ #endif #define USER_PTRS_PER_PGD ((TASK_SIZE + (PGDIR_SIZE - 1)) / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), \ diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c index 74e07e748a9b..9512253947d5 100644 --- a/arch/um/kernel/um_arch.c +++ b/arch/um/kernel/um_arch.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 867e7936dbc5..49270655e827 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -33,6 +33,7 @@ config X86_64 select NEED_DMA_MAP_STATE select SWIOTLB select ARCH_HAS_ELFCORE_COMPAT + select ZONE_DMA32 config FORCE_DYNAMIC_FTRACE def_bool y @@ -63,7 +64,7 @@ config X86 select ARCH_ENABLE_HUGEPAGE_MIGRATION if X86_64 && HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_MEMORY_HOTPLUG if X86_64 || (X86_32 && HIGHMEM) select ARCH_ENABLE_MEMORY_HOTREMOVE if MEMORY_HOTPLUG - select ARCH_ENABLE_SPLIT_PMD_PTLOCK if X86_64 || X86_PAE + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if (PGTABLE_LEVELS > 2) && (X86_64 || X86_PAE) select ARCH_ENABLE_THP_MIGRATION if X86_64 && TRANSPARENT_HUGEPAGE select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI select ARCH_HAS_CACHE_LINE_SIZE @@ -93,6 +94,7 @@ config X86 select ARCH_HAS_SYSCALL_WRAPPER select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_DEBUG_WX + select ARCH_HAS_ZONE_DMA_SET if EXPERT select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI select ARCH_MIGHT_HAVE_PC_PARPORT @@ -344,9 +346,6 @@ config ARCH_SUSPEND_POSSIBLE config ARCH_WANT_GENERAL_HUGETLB def_bool y -config ZONE_DMA32 - def_bool y if X86_64 - config AUDIT_ARCH def_bool y if X86_64 @@ -394,16 +393,6 @@ config CC_HAS_SANE_STACKPROTECTOR menu "Processor type and features" -config ZONE_DMA - bool "DMA memory allocation support" if EXPERT - default y - help - DMA memory allocation support allows devices with less than 32-bit - addressing to allocate within the first 16MB of address space. - Disable if no such devices will be used. - - If unsure, say Y. - config SMP bool "Symmetric multi-processing support" help diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index e63cf582201f..ab97b22ac04a 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -9,6 +9,7 @@ #include #include +#include #include #include diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h index 62ad61d6fefc..c7ec5bb88334 100644 --- a/arch/x86/include/asm/pgalloc.h +++ b/arch/x86/include/asm/pgalloc.h @@ -84,8 +84,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE)); } -#define pmd_pgtable(pmd) pmd_page(pmd) - #if CONFIG_PGTABLE_LEVELS > 2 extern void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd); diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index f24d7ef8fffa..40497a9020c6 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -7,8 +7,6 @@ #include -#define FIRST_USER_ADDRESS 0UL - #define _PAGE_BIT_PRESENT 0 /* is present */ #define _PAGE_BIT_RW 1 /* writeable */ #define _PAGE_BIT_USER 2 /* userspace addressable */ diff --git a/arch/x86/include/asm/unaligned.h b/arch/x86/include/asm/unaligned.h deleted file mode 100644 index 9c754a7447aa..000000000000 --- a/arch/x86/include/asm/unaligned.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_UNALIGNED_H -#define _ASM_X86_UNALIGNED_H - -/* - * The x86 can do unaligned accesses itself. - */ - -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_X86_UNALIGNED_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 0f66682ac02a..3e625c61f008 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_FUNCTION_TRACER) += ftrace_$(BITS).o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o obj-$(CONFIG_X86_TSC) += trace_clock.o +obj-$(CONFIG_TRACING) += trace.o obj-$(CONFIG_CRASH_CORE) += crash_core_$(BITS).o obj-$(CONFIG_KEXEC_CORE) += machine_kexec_$(BITS).o obj-$(CONFIG_KEXEC_CORE) += relocate_kernel_$(BITS).o crash.o diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 01ca94f42e4e..cc8f1773deca 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 6edd1e2ee8af..38837dad46e6 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -549,9 +549,11 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_CNL_IDS(&gen9_early_ops), INTEL_ICL_11_IDS(&gen11_early_ops), INTEL_EHL_IDS(&gen11_early_ops), + INTEL_JSL_IDS(&gen11_early_ops), INTEL_TGL_12_IDS(&gen11_early_ops), INTEL_RKL_IDS(&gen11_early_ops), INTEL_ADLS_IDS(&gen11_early_ops), + INTEL_ADLP_IDS(&gen11_early_ops), }; struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index c492ad3001ca..b6e046e4b289 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -422,12 +422,6 @@ void *alloc_insn_page(void) return page; } -/* Recover page to RW mode before releasing it */ -void free_insn_page(void *page) -{ - module_memfree(page); -} - /* Kprobe x86 instruction emulation - only regs->ip or IF flag modifiers */ static void kprobe_emulate_ifmodifiers(struct kprobe *p, struct pt_regs *regs) diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 85acd22f8022..9f1d9215a9fb 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/trace.c b/arch/x86/kernel/trace.c new file mode 100644 index 000000000000..6b73b6f92ad3 --- /dev/null +++ b/arch/x86/kernel/trace.c @@ -0,0 +1,234 @@ +#include +#include + +#if defined(CONFIG_OSNOISE_TRACER) && defined(CONFIG_X86_LOCAL_APIC) +/* + * trace_intel_irq_entry - record intel specific IRQ entry + */ +static void trace_intel_irq_entry(void *data, int vector) +{ + osnoise_trace_irq_entry(vector); +} + +/* + * trace_intel_irq_exit - record intel specific IRQ exit + */ +static void trace_intel_irq_exit(void *data, int vector) +{ + char *vector_desc = (char *) data; + + osnoise_trace_irq_exit(vector, vector_desc); +} + +/* + * register_intel_irq_tp - Register intel specific IRQ entry tracepoints + */ +int osnoise_arch_register(void) +{ + int ret; + + ret = register_trace_local_timer_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_err; + + ret = register_trace_local_timer_exit(trace_intel_irq_exit, "local_timer"); + if (ret) + goto out_timer_entry; + +#ifdef CONFIG_X86_THERMAL_VECTOR + ret = register_trace_thermal_apic_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_timer_exit; + + ret = register_trace_thermal_apic_exit(trace_intel_irq_exit, "thermal_apic"); + if (ret) + goto out_thermal_entry; +#endif /* CONFIG_X86_THERMAL_VECTOR */ + +#ifdef CONFIG_X86_MCE_AMD + ret = register_trace_deferred_error_apic_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_thermal_exit; + + ret = register_trace_deferred_error_apic_exit(trace_intel_irq_exit, "deferred_error"); + if (ret) + goto out_deferred_entry; +#endif + +#ifdef CONFIG_X86_MCE_THRESHOLD + ret = register_trace_threshold_apic_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_deferred_exit; + + ret = register_trace_threshold_apic_exit(trace_intel_irq_exit, "threshold_apic"); + if (ret) + goto out_threshold_entry; +#endif /* CONFIG_X86_MCE_THRESHOLD */ + +#ifdef CONFIG_SMP + ret = register_trace_call_function_single_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_threshold_exit; + + ret = register_trace_call_function_single_exit(trace_intel_irq_exit, + "call_function_single"); + if (ret) + goto out_call_function_single_entry; + + ret = register_trace_call_function_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_call_function_single_exit; + + ret = register_trace_call_function_exit(trace_intel_irq_exit, "call_function"); + if (ret) + goto out_call_function_entry; + + ret = register_trace_reschedule_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_call_function_exit; + + ret = register_trace_reschedule_exit(trace_intel_irq_exit, "reschedule"); + if (ret) + goto out_reschedule_entry; +#endif /* CONFIG_SMP */ + +#ifdef CONFIG_IRQ_WORK + ret = register_trace_irq_work_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_reschedule_exit; + + ret = register_trace_irq_work_exit(trace_intel_irq_exit, "irq_work"); + if (ret) + goto out_irq_work_entry; +#endif + + ret = register_trace_x86_platform_ipi_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_irq_work_exit; + + ret = register_trace_x86_platform_ipi_exit(trace_intel_irq_exit, "x86_platform_ipi"); + if (ret) + goto out_x86_ipi_entry; + + ret = register_trace_error_apic_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_x86_ipi_exit; + + ret = register_trace_error_apic_exit(trace_intel_irq_exit, "error_apic"); + if (ret) + goto out_error_apic_entry; + + ret = register_trace_spurious_apic_entry(trace_intel_irq_entry, NULL); + if (ret) + goto out_error_apic_exit; + + ret = register_trace_spurious_apic_exit(trace_intel_irq_exit, "spurious_apic"); + if (ret) + goto out_spurious_apic_entry; + + return 0; + +out_spurious_apic_entry: + unregister_trace_spurious_apic_entry(trace_intel_irq_entry, NULL); +out_error_apic_exit: + unregister_trace_error_apic_exit(trace_intel_irq_exit, "error_apic"); +out_error_apic_entry: + unregister_trace_error_apic_entry(trace_intel_irq_entry, NULL); +out_x86_ipi_exit: + unregister_trace_x86_platform_ipi_exit(trace_intel_irq_exit, "x86_platform_ipi"); +out_x86_ipi_entry: + unregister_trace_x86_platform_ipi_entry(trace_intel_irq_entry, NULL); +out_irq_work_exit: + +#ifdef CONFIG_IRQ_WORK + unregister_trace_irq_work_exit(trace_intel_irq_exit, "irq_work"); +out_irq_work_entry: + unregister_trace_irq_work_entry(trace_intel_irq_entry, NULL); +out_reschedule_exit: +#endif + +#ifdef CONFIG_SMP + unregister_trace_reschedule_exit(trace_intel_irq_exit, "reschedule"); +out_reschedule_entry: + unregister_trace_reschedule_entry(trace_intel_irq_entry, NULL); +out_call_function_exit: + unregister_trace_call_function_exit(trace_intel_irq_exit, "call_function"); +out_call_function_entry: + unregister_trace_call_function_entry(trace_intel_irq_entry, NULL); +out_call_function_single_exit: + unregister_trace_call_function_single_exit(trace_intel_irq_exit, "call_function_single"); +out_call_function_single_entry: + unregister_trace_call_function_single_entry(trace_intel_irq_entry, NULL); +out_threshold_exit: +#endif + +#ifdef CONFIG_X86_MCE_THRESHOLD + unregister_trace_threshold_apic_exit(trace_intel_irq_exit, "threshold_apic"); +out_threshold_entry: + unregister_trace_threshold_apic_entry(trace_intel_irq_entry, NULL); +out_deferred_exit: +#endif + +#ifdef CONFIG_X86_MCE_AMD + unregister_trace_deferred_error_apic_exit(trace_intel_irq_exit, "deferred_error"); +out_deferred_entry: + unregister_trace_deferred_error_apic_entry(trace_intel_irq_entry, NULL); +out_thermal_exit: +#endif /* CONFIG_X86_MCE_AMD */ + +#ifdef CONFIG_X86_THERMAL_VECTOR + unregister_trace_thermal_apic_exit(trace_intel_irq_exit, "thermal_apic"); +out_thermal_entry: + unregister_trace_thermal_apic_entry(trace_intel_irq_entry, NULL); +out_timer_exit: +#endif /* CONFIG_X86_THERMAL_VECTOR */ + + unregister_trace_local_timer_exit(trace_intel_irq_exit, "local_timer"); +out_timer_entry: + unregister_trace_local_timer_entry(trace_intel_irq_entry, NULL); +out_err: + return -EINVAL; +} + +void osnoise_arch_unregister(void) +{ + unregister_trace_spurious_apic_exit(trace_intel_irq_exit, "spurious_apic"); + unregister_trace_spurious_apic_entry(trace_intel_irq_entry, NULL); + unregister_trace_error_apic_exit(trace_intel_irq_exit, "error_apic"); + unregister_trace_error_apic_entry(trace_intel_irq_entry, NULL); + unregister_trace_x86_platform_ipi_exit(trace_intel_irq_exit, "x86_platform_ipi"); + unregister_trace_x86_platform_ipi_entry(trace_intel_irq_entry, NULL); + +#ifdef CONFIG_IRQ_WORK + unregister_trace_irq_work_exit(trace_intel_irq_exit, "irq_work"); + unregister_trace_irq_work_entry(trace_intel_irq_entry, NULL); +#endif + +#ifdef CONFIG_SMP + unregister_trace_reschedule_exit(trace_intel_irq_exit, "reschedule"); + unregister_trace_reschedule_entry(trace_intel_irq_entry, NULL); + unregister_trace_call_function_exit(trace_intel_irq_exit, "call_function"); + unregister_trace_call_function_entry(trace_intel_irq_entry, NULL); + unregister_trace_call_function_single_exit(trace_intel_irq_exit, "call_function_single"); + unregister_trace_call_function_single_entry(trace_intel_irq_entry, NULL); +#endif + +#ifdef CONFIG_X86_MCE_THRESHOLD + unregister_trace_threshold_apic_exit(trace_intel_irq_exit, "threshold_apic"); + unregister_trace_threshold_apic_entry(trace_intel_irq_entry, NULL); +#endif + +#ifdef CONFIG_X86_MCE_AMD + unregister_trace_deferred_error_apic_exit(trace_intel_irq_exit, "deferred_error"); + unregister_trace_deferred_error_apic_entry(trace_intel_irq_entry, NULL); +#endif + +#ifdef CONFIG_X86_THERMAL_VECTOR + unregister_trace_thermal_apic_exit(trace_intel_irq_exit, "thermal_apic"); + unregister_trace_thermal_apic_entry(trace_intel_irq_entry, NULL); +#endif /* CONFIG_X86_THERMAL_VECTOR */ + + unregister_trace_local_timer_exit(trace_intel_irq_exit, "local_timer"); + unregister_trace_local_timer_entry(trace_intel_irq_entry, NULL); +} +#endif /* CONFIG_OSNOISE_TRAECR && CONFIG_X86_LOCAL_APIC */ diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index e527d829e1ed..65ea58527176 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -1269,7 +1270,7 @@ static struct kcore_list kcore_vsyscall; static void __init register_page_bootmem_info(void) { -#ifdef CONFIG_NUMA +#if defined(CONFIG_NUMA) || defined(CONFIG_HUGETLB_PAGE_FREE_VMEMMAP) int i; for_each_online_node(i) @@ -1623,7 +1624,7 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, return err; } -#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HAVE_BOOTMEM_INFO_NODE) +#ifdef CONFIG_HAVE_BOOTMEM_INFO_NODE void register_page_bootmem_memmap(unsigned long section_nr, struct page *start_page, unsigned long nr_pages) { diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index d27cf69e811d..1303ff6ef7be 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -682,6 +682,7 @@ int p4d_clear_huge(p4d_t *p4d) } #endif +#if CONFIG_PGTABLE_LEVELS > 3 /** * pud_set_huge - setup kernel PUD mapping * @@ -720,6 +721,23 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) return 1; } +/** + * pud_clear_huge - clear kernel PUD mapping when it is set + * + * Returns 1 on success and 0 on failure (no PUD map is found). + */ +int pud_clear_huge(pud_t *pud) +{ + if (pud_large(*pud)) { + pud_clear(pud); + return 1; + } + + return 0; +} +#endif + +#if CONFIG_PGTABLE_LEVELS > 2 /** * pmd_set_huge - setup kernel PMD mapping * @@ -750,21 +768,6 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) return 1; } -/** - * pud_clear_huge - clear kernel PUD mapping when it is set - * - * Returns 1 on success and 0 on failure (no PUD map is found). - */ -int pud_clear_huge(pud_t *pud) -{ - if (pud_large(*pud)) { - pud_clear(pud); - return 1; - } - - return 0; -} - /** * pmd_clear_huge - clear kernel PMD mapping when it is set * @@ -779,6 +782,7 @@ int pmd_clear_huge(pmd_t *pmd) return 0; } +#endif #ifdef CONFIG_X86_64 /** diff --git a/arch/x86/purgatory/purgatory.c b/arch/x86/purgatory/purgatory.c index f03b64d9cb51..7558139920f8 100644 --- a/arch/x86/purgatory/purgatory.c +++ b/arch/x86/purgatory/purgatory.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include #include diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index aa9f50fccc5d..c79bd0af2e8c 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/include/asm/pgalloc.h b/arch/xtensa/include/asm/pgalloc.h index d3a22da4d2c9..eeb2de3a89e5 100644 --- a/arch/xtensa/include/asm/pgalloc.h +++ b/arch/xtensa/include/asm/pgalloc.h @@ -25,7 +25,6 @@ (pmd_val(*(pmdp)) = ((unsigned long)ptep)) #define pmd_populate(mm, pmdp, page) \ (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page))) -#define pmd_pgtable(pmd) pmd_page(pmd) static inline pgd_t* pgd_alloc(struct mm_struct *mm) @@ -63,7 +62,6 @@ static inline pgtable_t pte_alloc_one(struct mm_struct *mm) return page; } -#define pmd_pgtable(pmd) pmd_page(pmd) #endif /* CONFIG_MMU */ #endif /* _XTENSA_PGALLOC_H */ diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h index d7fc45c920c2..bd5aeb795567 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h @@ -59,7 +59,6 @@ #define PTRS_PER_PGD 1024 #define PGD_ORDER 0 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) #ifdef CONFIG_MMU diff --git a/arch/xtensa/include/asm/unaligned.h b/arch/xtensa/include/asm/unaligned.h deleted file mode 100644 index 8e7ed046bfed..000000000000 --- a/arch/xtensa/include/asm/unaligned.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Xtensa doesn't handle unaligned accesses efficiently. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ -#ifndef _ASM_XTENSA_UNALIGNED_H -#define _ASM_XTENSA_UNALIGNED_H - -#include - -#ifdef __LITTLE_ENDIAN -# include -# include -# include -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# include -# include -# include -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#endif - -#endif /* _ASM_XTENSA_UNALIGNED_H */ diff --git a/arch/xtensa/include/uapi/asm/mman.h b/arch/xtensa/include/uapi/asm/mman.h index e5e643752947..b3a22095371b 100644 --- a/arch/xtensa/include/uapi/asm/mman.h +++ b/arch/xtensa/include/uapi/asm/mman.h @@ -106,6 +106,9 @@ #define MADV_COLD 20 /* deactivate these pages */ #define MADV_PAGEOUT 21 /* reclaim these pages */ +#define MADV_POPULATE_READ 22 /* populate (prefault) page tables readable */ +#define MADV_POPULATE_WRITE 23 /* populate (prefault) page tables writable */ + /* compatibility flags */ #define MAP_FILE 0 diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c index a3dda25a4e45..21184488c277 100644 --- a/arch/xtensa/platforms/iss/console.c +++ b/arch/xtensa/platforms/iss/console.c @@ -100,18 +100,12 @@ static void rs_flush_chars(struct tty_struct *tty) { } -static int rs_write_room(struct tty_struct *tty) +static unsigned int rs_write_room(struct tty_struct *tty) { /* Let's say iss can always accept 2K characters.. */ return 2 * 1024; } -static int rs_chars_in_buffer(struct tty_struct *tty) -{ - /* the iss doesn't buffer characters */ - return 0; -} - static void rs_hangup(struct tty_struct *tty) { /* Stub, once again.. */ @@ -135,7 +129,6 @@ static const struct tty_operations serial_ops = { .put_char = rs_put_char, .flush_chars = rs_flush_chars, .write_room = rs_write_room, - .chars_in_buffer = rs_chars_in_buffer, .hangup = rs_hangup, .wait_until_sent = rs_wait_until_sent, .proc_show = rs_proc_show, diff --git a/arch/xtensa/platforms/iss/setup.c b/arch/xtensa/platforms/iss/setup.c index ed519aee0ec8..d3433e1bb94e 100644 --- a/arch/xtensa/platforms/iss/setup.c +++ b/arch/xtensa/platforms/iss/setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/block/Kconfig b/block/Kconfig index aabfb8588e9d..1f951a4b89d6 100644 --- a/block/Kconfig +++ b/block/Kconfig @@ -151,6 +151,15 @@ config BLK_CGROUP_IOLATENCY Note, this is an experimental interface and could be changed someday. +config BLK_CGROUP_FC_APPID + bool "Enable support to track FC I/O Traffic across cgroup applications" + depends on BLK_CGROUP && NVME_FC + help + Enabling this option enables the support to track FC I/O traffic across + cgroup applications. It enables the Fabric and the storage targets to + identify, monitor, and handle FC traffic based on VM tags by inserting + application specific identification into the FC frame. + config BLK_CGROUP_IOCOST bool "Enable support for cost model based cgroup IO controller" depends on BLK_CGROUP=y diff --git a/block/bsg-lib.c b/block/bsg-lib.c index 330fede77271..cf1811261722 100644 --- a/block/bsg-lib.c +++ b/block/bsg-lib.c @@ -84,7 +84,7 @@ static int bsg_transport_complete_rq(struct request *rq, struct sg_io_v4 *hdr) */ hdr->device_status = job->result & 0xff; hdr->transport_status = host_byte(job->result); - hdr->driver_status = driver_byte(job->result); + hdr->driver_status = 0; hdr->info = 0; if (hdr->device_status || hdr->transport_status || hdr->driver_status) hdr->info |= SG_INFO_CHECK; diff --git a/block/bsg.c b/block/bsg.c index bd10922d5cbb..33e3f82ed03a 100644 --- a/block/bsg.c +++ b/block/bsg.c @@ -96,7 +96,9 @@ static int bsg_scsi_complete_rq(struct request *rq, struct sg_io_v4 *hdr) */ hdr->device_status = sreq->result & 0xff; hdr->transport_status = host_byte(sreq->result); - hdr->driver_status = driver_byte(sreq->result); + hdr->driver_status = 0; + if (scsi_status_is_check_condition(sreq->result)) + hdr->driver_status = DRIVER_SENSE; hdr->info = 0; if (hdr->device_status || hdr->transport_status || hdr->driver_status) hdr->info |= SG_INFO_CHECK; diff --git a/block/partitions/ldm.c b/block/partitions/ldm.c index d333786b5c7e..cc86534c80ad 100644 --- a/block/partitions/ldm.c +++ b/block/partitions/ldm.c @@ -510,7 +510,7 @@ static bool ldm_validate_partition_table(struct parsed_partitions *state) p = (struct msdos_partition *)(data + 0x01BE); for (i = 0; i < 4; i++, p++) - if (SYS_IND (p) == LDM_PARTITION) { + if (p->sys_ind == LDM_PARTITION) { result = true; break; } diff --git a/block/partitions/ldm.h b/block/partitions/ldm.h index d8d6beaa72c4..8693704dcf5e 100644 --- a/block/partitions/ldm.h +++ b/block/partitions/ldm.h @@ -84,9 +84,6 @@ struct parsed_partitions; #define TOC_BITMAP1 "config" /* Names of the two defined */ #define TOC_BITMAP2 "log" /* bitmaps in the TOCBLOCK. */ -/* Borrowed from msdos.c */ -#define SYS_IND(p) (get_unaligned(&(p)->sys_ind)) - struct frag { /* VBLK Fragment handling */ struct list_head list; u32 group; diff --git a/block/partitions/msdos.c b/block/partitions/msdos.c index 63e4f6f8b6e9..f5102596a984 100644 --- a/block/partitions/msdos.c +++ b/block/partitions/msdos.c @@ -38,8 +38,6 @@ */ #include -#define SYS_IND(p) get_unaligned(&p->sys_ind) - static inline sector_t nr_sects(struct msdos_partition *p) { return (sector_t)get_unaligned_le32(&p->nr_sects); @@ -52,9 +50,9 @@ static inline sector_t start_sect(struct msdos_partition *p) static inline int is_extended_partition(struct msdos_partition *p) { - return (SYS_IND(p) == DOS_EXTENDED_PARTITION || - SYS_IND(p) == WIN98_EXTENDED_PARTITION || - SYS_IND(p) == LINUX_EXTENDED_PARTITION); + return (p->sys_ind == DOS_EXTENDED_PARTITION || + p->sys_ind == WIN98_EXTENDED_PARTITION || + p->sys_ind == LINUX_EXTENDED_PARTITION); } #define MSDOS_LABEL_MAGIC1 0x55 @@ -193,7 +191,7 @@ static void parse_extended(struct parsed_partitions *state, put_partition(state, state->next, next, size); set_info(state, state->next, disksig); - if (SYS_IND(p) == LINUX_RAID_PARTITION) + if (p->sys_ind == LINUX_RAID_PARTITION) state->parts[state->next].flags = ADDPART_FLAG_RAID; loopct = 0; if (++state->next == state->limit) @@ -546,7 +544,7 @@ static void parse_minix(struct parsed_partitions *state, * a secondary MBR describing its subpartitions, or * the normal boot sector. */ if (msdos_magic_present(data + 510) && - SYS_IND(p) == MINIX_PARTITION) { /* subpartition table present */ + p->sys_ind == MINIX_PARTITION) { /* subpartition table present */ char tmp[1 + BDEVNAME_SIZE + 10 + 9 + 1]; snprintf(tmp, sizeof(tmp), " %s%d: name, origin); @@ -555,7 +553,7 @@ static void parse_minix(struct parsed_partitions *state, if (state->next == state->limit) break; /* add each partition in use */ - if (SYS_IND(p) == MINIX_PARTITION) + if (p->sys_ind == MINIX_PARTITION) put_partition(state, state->next++, start_sect(p), nr_sects(p)); } @@ -643,7 +641,7 @@ int msdos_partition(struct parsed_partitions *state) p = (struct msdos_partition *) (data + 0x1be); for (slot = 1 ; slot <= 4 ; slot++, p++) { /* If this is an EFI GPT disk, msdos should ignore it. */ - if (SYS_IND(p) == EFI_PMBR_OSTYPE_EFI_GPT) { + if (p->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT) { put_dev_sector(sect); return 0; } @@ -685,11 +683,11 @@ int msdos_partition(struct parsed_partitions *state) } put_partition(state, slot, start, size); set_info(state, slot, disksig); - if (SYS_IND(p) == LINUX_RAID_PARTITION) + if (p->sys_ind == LINUX_RAID_PARTITION) state->parts[slot].flags = ADDPART_FLAG_RAID; - if (SYS_IND(p) == DM6_PARTITION) + if (p->sys_ind == DM6_PARTITION) strlcat(state->pp_buf, "[DM]", PAGE_SIZE); - if (SYS_IND(p) == EZD_PARTITION) + if (p->sys_ind == EZD_PARTITION) strlcat(state->pp_buf, "[EZD]", PAGE_SIZE); } @@ -698,7 +696,7 @@ int msdos_partition(struct parsed_partitions *state) /* second pass - output for each on a separate line */ p = (struct msdos_partition *) (0x1be + data); for (slot = 1 ; slot <= 4 ; slot++, p++) { - unsigned char id = SYS_IND(p); + unsigned char id = p->sys_ind; int n; if (!nr_sects(p)) diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c index 1b3fe99b83a6..fa6df11b8bdd 100644 --- a/block/scsi_ioctl.c +++ b/block/scsi_ioctl.c @@ -254,9 +254,11 @@ static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, */ hdr->status = req->result & 0xff; hdr->masked_status = status_byte(req->result); - hdr->msg_status = msg_byte(req->result); + hdr->msg_status = COMMAND_COMPLETE; hdr->host_status = host_byte(req->result); - hdr->driver_status = driver_byte(req->result); + hdr->driver_status = 0; + if (scsi_status_is_check_condition(hdr->status)) + hdr->driver_status = DRIVER_SENSE; hdr->info = 0; if (hdr->masked_status || hdr->host_status || hdr->driver_status) hdr->info |= SG_INFO_CHECK; @@ -484,9 +486,10 @@ int sg_scsi_ioctl(struct request_queue *q, struct gendisk *disk, fmode_t mode, break; } - if (bytes && blk_rq_map_kern(q, rq, buffer, bytes, GFP_NOIO)) { - err = DRIVER_ERROR << 24; - goto error; + if (bytes) { + err = blk_rq_map_kern(q, rq, buffer, bytes, GFP_NOIO); + if (err) + goto error; } blk_execute_rq(disk, rq, 0); diff --git a/drivers/accessibility/braille/braille_console.c b/drivers/accessibility/braille/braille_console.c index 359bead4b280..fdc6b593f500 100644 --- a/drivers/accessibility/braille/braille_console.c +++ b/drivers/accessibility/braille/braille_console.c @@ -225,6 +225,7 @@ static int keyboard_notifier_call(struct notifier_block *blk, case KBD_POST_KEYSYM: { unsigned char type = KTYP(param->value) - 0xf0; + if (type == KT_SPEC) { unsigned char val = KVAL(param->value); int on_off = -1; @@ -265,6 +266,7 @@ static int vt_notifier_call(struct notifier_block *blk, { struct vt_notifier_param *param = _param; struct vc_data *vc = param->vc; + switch (code) { case VT_ALLOCATE: break; @@ -273,6 +275,7 @@ static int vt_notifier_call(struct notifier_block *blk, case VT_WRITE: { unsigned char c = param->c; + if (vc->vc_num != fg_console) break; switch (c) { diff --git a/drivers/accessibility/speakup/i18n.c b/drivers/accessibility/speakup/i18n.c index 46bd50f3c3a4..bc7b47d1876f 100644 --- a/drivers/accessibility/speakup/i18n.c +++ b/drivers/accessibility/speakup/i18n.c @@ -90,6 +90,13 @@ static char *speakup_default_msgs[MSG_LAST_INDEX] = { [MSG_COLOR_YELLOW] = "yellow", [MSG_COLOR_WHITE] = "white", [MSG_COLOR_GREY] = "grey", + [MSG_COLOR_BRIGHTBLUE] "bright blue", + [MSG_COLOR_BRIGHTGREEN] "bright green", + [MSG_COLOR_BRIGHTCYAN] "bright cyan", + [MSG_COLOR_BRIGHTRED] "bright red", + [MSG_COLOR_BRIGHTMAGENTA] "bright magenta", + [MSG_COLOR_BRIGHTYELLOW] "bright yellow", + [MSG_COLOR_BRIGHTWHITE] "bright white", /* Names of key states. */ [MSG_STATE_DOUBLE] = "double", diff --git a/drivers/accessibility/speakup/i18n.h b/drivers/accessibility/speakup/i18n.h index 2a607d263234..51e3260995d9 100644 --- a/drivers/accessibility/speakup/i18n.h +++ b/drivers/accessibility/speakup/i18n.h @@ -99,7 +99,14 @@ enum msg_index_t { MSG_COLOR_YELLOW, MSG_COLOR_WHITE, MSG_COLOR_GREY, - MSG_COLORS_END = MSG_COLOR_GREY, + MSG_COLOR_BRIGHTBLUE, + MSG_COLOR_BRIGHTGREEN, + MSG_COLOR_BRIGHTCYAN, + MSG_COLOR_BRIGHTRED, + MSG_COLOR_BRIGHTMAGENTA, + MSG_COLOR_BRIGHTYELLOW, + MSG_COLOR_BRIGHTWHITE, + MSG_COLORS_END = MSG_COLOR_BRIGHTWHITE, MSG_STATES_START, MSG_STATE_DOUBLE = MSG_STATES_START, diff --git a/drivers/accessibility/speakup/main.c b/drivers/accessibility/speakup/main.c index 428fceaf9d50..d726537fa16c 100644 --- a/drivers/accessibility/speakup/main.c +++ b/drivers/accessibility/speakup/main.c @@ -389,10 +389,6 @@ static void say_attributes(struct vc_data *vc) int fg = spk_attr & 0x0f; int bg = spk_attr >> 4; - if (fg > 8) { - synth_printf("%s ", spk_msg_get(MSG_BRIGHT)); - fg -= 8; - } synth_printf("%s", spk_msg_get(MSG_COLORS_START + fg)); if (bg > 7) { synth_printf(" %s ", spk_msg_get(MSG_ON_BLINKING)); diff --git a/drivers/accessibility/speakup/spk_ttyio.c b/drivers/accessibility/speakup/spk_ttyio.c index 2e39fcf492d8..0d1f397cd896 100644 --- a/drivers/accessibility/speakup/spk_ttyio.c +++ b/drivers/accessibility/speakup/spk_ttyio.c @@ -72,7 +72,8 @@ static void spk_ttyio_ldisc_close(struct tty_struct *tty) } static int spk_ttyio_receive_buf2(struct tty_struct *tty, - const unsigned char *cp, char *fp, int count) + const unsigned char *cp, + const char *fp, int count) { struct spk_ldisc_data *ldisc_data = tty->disc_data; struct spk_synth *synth = ldisc_data->synth; @@ -104,6 +105,7 @@ static int spk_ttyio_receive_buf2(struct tty_struct *tty, static struct tty_ldisc_ops spk_ttyio_ldisc_ops = { .owner = THIS_MODULE, + .num = N_SPEAKUP, .name = "speakup_ldisc", .open = spk_ttyio_ldisc_open, .close = spk_ttyio_ldisc_close, @@ -211,14 +213,13 @@ static int spk_ttyio_initialise_ldisc(struct spk_synth *synth) void spk_ttyio_register_ldisc(void) { - if (tty_register_ldisc(N_SPEAKUP, &spk_ttyio_ldisc_ops)) + if (tty_register_ldisc(&spk_ttyio_ldisc_ops)) pr_warn("speakup: Error registering line discipline. Most synths won't work.\n"); } void spk_ttyio_unregister_ldisc(void) { - if (tty_unregister_ldisc(N_SPEAKUP)) - pr_warn("speakup: Couldn't unregister ldisc\n"); + tty_unregister_ldisc(&spk_ttyio_ldisc_ops); } static int spk_ttyio_out(struct spk_synth *in_synth, const char ch) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 3972de7b7565..fe0bb6277e4d 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -526,6 +526,9 @@ endif source "drivers/acpi/pmic/Kconfig" +config ACPI_VIOT + bool + endif # ACPI config X86_PM_TIMER diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index ceb1aed4b1fc..3018714e87d9 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -124,3 +124,5 @@ video-objs += acpi_video.o video_detect.o obj-y += dptf/ obj-$(CONFIG_ARM64) += arm64/ + +obj-$(CONFIG_ACPI_VIOT) += viot.o diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile index 6ff50f4ed947..66acbe77f46e 100644 --- a/drivers/acpi/arm64/Makefile +++ b/drivers/acpi/arm64/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_ACPI_IORT) += iort.o obj-$(CONFIG_ACPI_GTDT) += gtdt.o +obj-y += dma.o diff --git a/drivers/acpi/arm64/dma.c b/drivers/acpi/arm64/dma.c new file mode 100644 index 000000000000..f16739ad3cc0 --- /dev/null +++ b/drivers/acpi/arm64/dma.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include + +void acpi_arch_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size) +{ + int ret; + u64 end, mask; + u64 dmaaddr = 0, size = 0, offset = 0; + + /* + * If @dev is expected to be DMA-capable then the bus code that created + * it should have initialised its dma_mask pointer by this point. For + * now, we'll continue the legacy behaviour of coercing it to the + * coherent mask if not, but we'll no longer do so quietly. + */ + if (!dev->dma_mask) { + dev_warn(dev, "DMA mask not set\n"); + dev->dma_mask = &dev->coherent_dma_mask; + } + + if (dev->coherent_dma_mask) + size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1); + else + size = 1ULL << 32; + + ret = acpi_dma_get_range(dev, &dmaaddr, &offset, &size); + if (ret == -ENODEV) + ret = iort_dma_get_ranges(dev, &size); + if (!ret) { + /* + * Limit coherent and dma mask based on size retrieved from + * firmware. + */ + end = dmaaddr + size - 1; + mask = DMA_BIT_MASK(ilog2(end) + 1); + dev->bus_dma_limit = end; + dev->coherent_dma_mask = min(dev->coherent_dma_mask, mask); + *dev->dma_mask = min(*dev->dma_mask, mask); + } + + *dma_addr = dmaaddr; + *dma_size = size; + + ret = dma_direct_set_offset(dev, dmaaddr + offset, dmaaddr, size); + + dev_dbg(dev, "dma_offset(%#08llx)%s\n", offset, ret ? " failed!" : ""); +} diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index e34937e11186..3b23fb775ac4 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -806,23 +806,6 @@ static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) return NULL; } -static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - return (fwspec && fwspec->ops) ? fwspec->ops : NULL; -} - -static inline int iort_add_device_replay(struct device *dev) -{ - int err = 0; - - if (dev->bus && !device_iommu_mapped(dev)) - err = iommu_probe_device(dev); - - return err; -} - /** * iort_iommu_msi_get_resv_regions - Reserved region driver helper * @dev: Device from iommu_get_resv_regions() @@ -900,18 +883,6 @@ static inline bool iort_iommu_driver_enabled(u8 type) } } -static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops) -{ - int ret = iommu_fwspec_init(dev, fwnode, ops); - - if (!ret) - ret = iommu_fwspec_add_ids(dev, &streamid, 1); - - return ret; -} - static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) { struct acpi_iort_root_complex *pci_rc; @@ -946,7 +917,7 @@ static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, return iort_iommu_driver_enabled(node->type) ? -EPROBE_DEFER : -ENODEV; - return arm_smmu_iort_xlate(dev, streamid, iort_fwnode, ops); + return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode, ops); } struct iort_pci_alias_info { @@ -968,13 +939,15 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) static void iort_named_component_init(struct device *dev, struct acpi_iort_node *node) { - struct property_entry props[2] = {}; + struct property_entry props[3] = {}; struct acpi_iort_named_component *nc; nc = (struct acpi_iort_named_component *)node->node_data; props[0] = PROPERTY_ENTRY_U32("pasid-num-bits", FIELD_GET(ACPI_IORT_NC_PASID_BITS, nc->node_flags)); + if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) + props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall"); if (device_create_managed_software_node(dev, props, NULL)) dev_warn(dev, "Could not add device properties\n"); @@ -1020,24 +993,13 @@ static int iort_nc_iommu_map_id(struct device *dev, * @dev: device to configure * @id_in: optional input id const value pointer * - * Returns: iommu_ops pointer on configuration success - * NULL on configuration failure + * Returns: 0 on success, <0 on failure */ -const struct iommu_ops *iort_iommu_configure_id(struct device *dev, - const u32 *id_in) +int iort_iommu_configure_id(struct device *dev, const u32 *id_in) { struct acpi_iort_node *node; - const struct iommu_ops *ops; int err = -ENODEV; - /* - * If we already translated the fwspec there - * is nothing left to do, return the iommu_ops. - */ - ops = iort_fwspec_iommu_ops(dev); - if (ops) - return ops; - if (dev_is_pci(dev)) { struct iommu_fwspec *fwspec; struct pci_bus *bus = to_pci_dev(dev)->bus; @@ -1046,7 +1008,7 @@ const struct iommu_ops *iort_iommu_configure_id(struct device *dev, node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, iort_match_node_callback, &bus->dev); if (!node) - return NULL; + return -ENODEV; info.node = node; err = pci_for_each_dma_alias(to_pci_dev(dev), @@ -1059,7 +1021,7 @@ const struct iommu_ops *iort_iommu_configure_id(struct device *dev, node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, iort_match_node_callback, dev); if (!node) - return NULL; + return -ENODEV; err = id_in ? iort_nc_iommu_map_id(dev, node, id_in) : iort_nc_iommu_map(dev, node); @@ -1068,32 +1030,14 @@ const struct iommu_ops *iort_iommu_configure_id(struct device *dev, iort_named_component_init(dev, node); } - /* - * If we have reason to believe the IOMMU driver missed the initial - * add_device callback for dev, replay it to get things in order. - */ - if (!err) { - ops = iort_fwspec_iommu_ops(dev); - err = iort_add_device_replay(dev); - } - - /* Ignore all other errors apart from EPROBE_DEFER */ - if (err == -EPROBE_DEFER) { - ops = ERR_PTR(err); - } else if (err) { - dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); - ops = NULL; - } - - return ops; + return err; } #else int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) { return 0; } -const struct iommu_ops *iort_iommu_configure_id(struct device *dev, - const u32 *input_id) -{ return NULL; } +int iort_iommu_configure_id(struct device *dev, const u32 *input_id) +{ return -ENODEV; } #endif static int nc_dma_get_range(struct device *dev, u64 *size) @@ -1144,56 +1088,18 @@ static int rc_dma_get_range(struct device *dev, u64 *size) } /** - * iort_dma_setup() - Set-up device DMA parameters. + * iort_dma_get_ranges() - Look up DMA addressing limit for the device + * @dev: device to lookup + * @size: DMA range size result pointer * - * @dev: device to configure - * @dma_addr: device DMA address result pointer - * @dma_size: DMA range size result pointer + * Return: 0 on success, an error otherwise. */ -void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size) +int iort_dma_get_ranges(struct device *dev, u64 *size) { - u64 end, mask, dmaaddr = 0, size = 0, offset = 0; - int ret; - - /* - * If @dev is expected to be DMA-capable then the bus code that created - * it should have initialised its dma_mask pointer by this point. For - * now, we'll continue the legacy behaviour of coercing it to the - * coherent mask if not, but we'll no longer do so quietly. - */ - if (!dev->dma_mask) { - dev_warn(dev, "DMA mask not set\n"); - dev->dma_mask = &dev->coherent_dma_mask; - } - - if (dev->coherent_dma_mask) - size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1); + if (dev_is_pci(dev)) + return rc_dma_get_range(dev, size); else - size = 1ULL << 32; - - ret = acpi_dma_get_range(dev, &dmaaddr, &offset, &size); - if (ret == -ENODEV) - ret = dev_is_pci(dev) ? rc_dma_get_range(dev, &size) - : nc_dma_get_range(dev, &size); - - if (!ret) { - /* - * Limit coherent and dma mask based on size retrieved from - * firmware. - */ - end = dmaaddr + size - 1; - mask = DMA_BIT_MASK(ilog2(end) + 1); - dev->bus_dma_limit = end; - dev->coherent_dma_mask = min(dev->coherent_dma_mask, mask); - *dev->dma_mask = min(*dev->dma_mask, mask); - } - - *dma_addr = dmaaddr; - *dma_size = size; - - ret = dma_direct_set_offset(dev, dmaaddr + offset, dmaaddr, size); - - dev_dbg(dev, "dma_offset(%#08llx)%s\n", offset, ret ? " failed!" : ""); + return nc_dma_get_range(dev, size); } static void __init acpi_iort_register_irq(int hwirq, const char *name, diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 60fb6a843853..ee24246d88fd 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -27,6 +27,7 @@ #include #endif #include +#include #include #include #include @@ -1335,6 +1336,7 @@ static int __init acpi_init(void) acpi_wakeup_device_init(); acpi_debugger_init(); acpi_setup_sb_notify_handler(); + acpi_viot_init(); return 0; } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 0641bc20b097..b24513ec3fae 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -1526,6 +1528,78 @@ int acpi_dma_get_range(struct device *dev, u64 *dma_addr, u64 *offset, return ret >= 0 ? 0 : ret; } +#ifdef CONFIG_IOMMU_API +int acpi_iommu_fwspec_init(struct device *dev, u32 id, + struct fwnode_handle *fwnode, + const struct iommu_ops *ops) +{ + int ret = iommu_fwspec_init(dev, fwnode, ops); + + if (!ret) + ret = iommu_fwspec_add_ids(dev, &id, 1); + + return ret; +} + +static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + return fwspec ? fwspec->ops : NULL; +} + +static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, + const u32 *id_in) +{ + int err; + const struct iommu_ops *ops; + + /* + * If we already translated the fwspec there is nothing left to do, + * return the iommu_ops. + */ + ops = acpi_iommu_fwspec_ops(dev); + if (ops) + return ops; + + err = iort_iommu_configure_id(dev, id_in); + if (err && err != -EPROBE_DEFER) + err = viot_iommu_configure(dev); + + /* + * If we have reason to believe the IOMMU driver missed the initial + * iommu_probe_device() call for dev, replay it to get things in order. + */ + if (!err && dev->bus && !device_iommu_mapped(dev)) + err = iommu_probe_device(dev); + + /* Ignore all other errors apart from EPROBE_DEFER */ + if (err == -EPROBE_DEFER) { + return ERR_PTR(err); + } else if (err) { + dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); + return NULL; + } + return acpi_iommu_fwspec_ops(dev); +} + +#else /* !CONFIG_IOMMU_API */ + +int acpi_iommu_fwspec_init(struct device *dev, u32 id, + struct fwnode_handle *fwnode, + const struct iommu_ops *ops) +{ + return -ENODEV; +} + +static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev, + const u32 *id_in) +{ + return NULL; +} + +#endif /* !CONFIG_IOMMU_API */ + /** * acpi_dma_configure_id - Set-up DMA configuration for the device. * @dev: The pointer to the device @@ -1543,9 +1617,9 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, return 0; } - iort_dma_setup(dev, &dma_addr, &size); + acpi_arch_dma_setup(dev, &dma_addr, &size); - iommu = iort_iommu_configure_id(dev, input_id); + iommu = acpi_iommu_configure_id(dev, input_id); if (PTR_ERR(iommu) == -EPROBE_DEFER) return -EPROBE_DEFER; diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c new file mode 100644 index 000000000000..d2256326c73a --- /dev/null +++ b/drivers/acpi/viot.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Virtual I/O topology + * + * The Virtual I/O Translation Table (VIOT) describes the topology of + * para-virtual IOMMUs and the endpoints they manage. The OS uses it to + * initialize devices in the right order, preventing endpoints from issuing DMA + * before their IOMMU is ready. + * + * When binding a driver to a device, before calling the device driver's probe() + * method, the driver infrastructure calls dma_configure(). At that point the + * VIOT driver looks for an IOMMU associated to the device in the VIOT table. + * If an IOMMU exists and has been initialized, the VIOT driver initializes the + * device's IOMMU fwspec, allowing the DMA infrastructure to invoke the IOMMU + * ops when the device driver configures DMA mappings. If an IOMMU exists and + * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing + * the device until the IOMMU is available. + */ +#define pr_fmt(fmt) "ACPI: VIOT: " fmt + +#include +#include +#include +#include +#include +#include +#include + +struct viot_iommu { + /* Node offset within the table */ + unsigned int offset; + struct fwnode_handle *fwnode; + struct list_head list; +}; + +struct viot_endpoint { + union { + /* PCI range */ + struct { + u16 segment_start; + u16 segment_end; + u16 bdf_start; + u16 bdf_end; + }; + /* MMIO */ + u64 address; + }; + u32 endpoint_id; + struct viot_iommu *viommu; + struct list_head list; +}; + +static struct acpi_table_viot *viot; +static LIST_HEAD(viot_iommus); +static LIST_HEAD(viot_pci_ranges); +static LIST_HEAD(viot_mmio_endpoints); + +static int __init viot_check_bounds(const struct acpi_viot_header *hdr) +{ + struct acpi_viot_header *start, *end, *hdr_end; + + start = ACPI_ADD_PTR(struct acpi_viot_header, viot, + max_t(size_t, sizeof(*viot), viot->node_offset)); + end = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->header.length); + hdr_end = ACPI_ADD_PTR(struct acpi_viot_header, hdr, sizeof(*hdr)); + + if (hdr < start || hdr_end > end) { + pr_err(FW_BUG "Node pointer overflows\n"); + return -EOVERFLOW; + } + if (hdr->length < sizeof(*hdr)) { + pr_err(FW_BUG "Empty node\n"); + return -EINVAL; + } + return 0; +} + +static int __init viot_get_pci_iommu_fwnode(struct viot_iommu *viommu, + u16 segment, u16 bdf) +{ + struct pci_dev *pdev; + struct fwnode_handle *fwnode; + + pdev = pci_get_domain_bus_and_slot(segment, PCI_BUS_NUM(bdf), + bdf & 0xff); + if (!pdev) { + pr_err("Could not find PCI IOMMU\n"); + return -ENODEV; + } + + fwnode = pdev->dev.fwnode; + if (!fwnode) { + /* + * PCI devices aren't necessarily described by ACPI. Create a + * fwnode so the IOMMU subsystem can identify this device. + */ + fwnode = acpi_alloc_fwnode_static(); + if (!fwnode) { + pci_dev_put(pdev); + return -ENOMEM; + } + set_primary_fwnode(&pdev->dev, fwnode); + } + viommu->fwnode = pdev->dev.fwnode; + pci_dev_put(pdev); + return 0; +} + +static int __init viot_get_mmio_iommu_fwnode(struct viot_iommu *viommu, + u64 address) +{ + struct acpi_device *adev; + struct resource res = { + .start = address, + .end = address, + .flags = IORESOURCE_MEM, + }; + + adev = acpi_resource_consumer(&res); + if (!adev) { + pr_err("Could not find MMIO IOMMU\n"); + return -EINVAL; + } + viommu->fwnode = &adev->fwnode; + return 0; +} + +static struct viot_iommu * __init viot_get_iommu(unsigned int offset) +{ + int ret; + struct viot_iommu *viommu; + struct acpi_viot_header *hdr = ACPI_ADD_PTR(struct acpi_viot_header, + viot, offset); + union { + struct acpi_viot_virtio_iommu_pci pci; + struct acpi_viot_virtio_iommu_mmio mmio; + } *node = (void *)hdr; + + list_for_each_entry(viommu, &viot_iommus, list) + if (viommu->offset == offset) + return viommu; + + if (viot_check_bounds(hdr)) + return NULL; + + viommu = kzalloc(sizeof(*viommu), GFP_KERNEL); + if (!viommu) + return NULL; + + viommu->offset = offset; + switch (hdr->type) { + case ACPI_VIOT_NODE_VIRTIO_IOMMU_PCI: + if (hdr->length < sizeof(node->pci)) + goto err_free; + + ret = viot_get_pci_iommu_fwnode(viommu, node->pci.segment, + node->pci.bdf); + break; + case ACPI_VIOT_NODE_VIRTIO_IOMMU_MMIO: + if (hdr->length < sizeof(node->mmio)) + goto err_free; + + ret = viot_get_mmio_iommu_fwnode(viommu, + node->mmio.base_address); + break; + default: + ret = -EINVAL; + } + if (ret) + goto err_free; + + list_add(&viommu->list, &viot_iommus); + return viommu; + +err_free: + kfree(viommu); + return NULL; +} + +static int __init viot_parse_node(const struct acpi_viot_header *hdr) +{ + int ret = -EINVAL; + struct list_head *list; + struct viot_endpoint *ep; + union { + struct acpi_viot_mmio mmio; + struct acpi_viot_pci_range pci; + } *node = (void *)hdr; + + if (viot_check_bounds(hdr)) + return -EINVAL; + + if (hdr->type == ACPI_VIOT_NODE_VIRTIO_IOMMU_PCI || + hdr->type == ACPI_VIOT_NODE_VIRTIO_IOMMU_MMIO) + return 0; + + ep = kzalloc(sizeof(*ep), GFP_KERNEL); + if (!ep) + return -ENOMEM; + + switch (hdr->type) { + case ACPI_VIOT_NODE_PCI_RANGE: + if (hdr->length < sizeof(node->pci)) { + pr_err(FW_BUG "Invalid PCI node size\n"); + goto err_free; + } + + ep->segment_start = node->pci.segment_start; + ep->segment_end = node->pci.segment_end; + ep->bdf_start = node->pci.bdf_start; + ep->bdf_end = node->pci.bdf_end; + ep->endpoint_id = node->pci.endpoint_start; + ep->viommu = viot_get_iommu(node->pci.output_node); + list = &viot_pci_ranges; + break; + case ACPI_VIOT_NODE_MMIO: + if (hdr->length < sizeof(node->mmio)) { + pr_err(FW_BUG "Invalid MMIO node size\n"); + goto err_free; + } + + ep->address = node->mmio.base_address; + ep->endpoint_id = node->mmio.endpoint; + ep->viommu = viot_get_iommu(node->mmio.output_node); + list = &viot_mmio_endpoints; + break; + default: + pr_warn("Unsupported node %x\n", hdr->type); + ret = 0; + goto err_free; + } + + if (!ep->viommu) { + pr_warn("No IOMMU node found\n"); + /* + * A future version of the table may use the node for other + * purposes. Keep parsing. + */ + ret = 0; + goto err_free; + } + + list_add(&ep->list, list); + return 0; + +err_free: + kfree(ep); + return ret; +} + +/** + * acpi_viot_init - Parse the VIOT table + * + * Parse the VIOT table, prepare the list of endpoints to be used during DMA + * setup of devices. + */ +void __init acpi_viot_init(void) +{ + int i; + acpi_status status; + struct acpi_table_header *hdr; + struct acpi_viot_header *node; + + status = acpi_get_table(ACPI_SIG_VIOT, 0, &hdr); + if (ACPI_FAILURE(status)) { + if (status != AE_NOT_FOUND) { + const char *msg = acpi_format_exception(status); + + pr_err("Failed to get table, %s\n", msg); + } + return; + } + + viot = (void *)hdr; + + node = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->node_offset); + for (i = 0; i < viot->node_count; i++) { + if (viot_parse_node(node)) + return; + + node = ACPI_ADD_PTR(struct acpi_viot_header, node, + node->length); + } + + acpi_put_table(hdr); +} + +static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu, + u32 epid) +{ + const struct iommu_ops *ops; + + if (!viommu) + return -ENODEV; + + /* We're not translating ourself */ + if (viommu->fwnode == dev->fwnode) + return -EINVAL; + + ops = iommu_ops_from_fwnode(viommu->fwnode); + if (!ops) + return IS_ENABLED(CONFIG_VIRTIO_IOMMU) ? + -EPROBE_DEFER : -ENODEV; + + return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, ops); +} + +static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data) +{ + u32 epid; + struct viot_endpoint *ep; + u32 domain_nr = pci_domain_nr(pdev->bus); + + list_for_each_entry(ep, &viot_pci_ranges, list) { + if (domain_nr >= ep->segment_start && + domain_nr <= ep->segment_end && + dev_id >= ep->bdf_start && + dev_id <= ep->bdf_end) { + epid = ((domain_nr - ep->segment_start) << 16) + + dev_id - ep->bdf_start + ep->endpoint_id; + + /* + * If we found a PCI range managed by the viommu, we're + * the one that has to request ACS. + */ + pci_request_acs(); + + return viot_dev_iommu_init(&pdev->dev, ep->viommu, + epid); + } + } + return -ENODEV; +} + +static int viot_mmio_dev_iommu_init(struct platform_device *pdev) +{ + struct resource *mem; + struct viot_endpoint *ep; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) + return -ENODEV; + + list_for_each_entry(ep, &viot_mmio_endpoints, list) { + if (ep->address == mem->start) + return viot_dev_iommu_init(&pdev->dev, ep->viommu, + ep->endpoint_id); + } + return -ENODEV; +} + +/** + * viot_iommu_configure - Setup IOMMU ops for an endpoint described by VIOT + * @dev: the endpoint + * + * Return: 0 on success, <0 on failure + */ +int viot_iommu_configure(struct device *dev) +{ + if (dev_is_pci(dev)) + return pci_for_each_dma_alias(to_pci_dev(dev), + viot_pci_dev_iommu_init, NULL); + else if (dev_is_platform(dev)) + return viot_mmio_dev_iommu_init(to_platform_device(dev)); + return -ENODEV; +} diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index fd8b6febbf70..b9588c52815d 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -196,9 +196,7 @@ void ata_scsi_set_sense(struct ata_device *dev, struct scsi_cmnd *cmd, if (!cmd) return; - cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; - - scsi_build_sense_buffer(d_sense, cmd->sense_buffer, sk, asc, ascq); + scsi_build_sense(cmd, d_sense, sk, asc, ascq); } void ata_scsi_set_sense_information(struct ata_device *dev, @@ -409,13 +407,16 @@ int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg) cmd_result = scsi_execute(scsidev, scsi_cmd, data_dir, argbuf, argsize, sensebuf, &sshdr, (10*HZ), 5, 0, 0, NULL); - if (driver_byte(cmd_result) == DRIVER_SENSE) {/* sense data available */ + if (cmd_result < 0) { + rc = cmd_result; + goto error; + } + if (scsi_sense_valid(&sshdr)) {/* sense data available */ u8 *desc = sensebuf + 8; - cmd_result &= ~(0xFF<<24); /* DRIVER_SENSE is not an error */ /* If we set cc then ATA pass-through will cause a * check condition even if no error. Filter that. */ - if (cmd_result & SAM_STAT_CHECK_CONDITION) { + if (scsi_status_is_check_condition(cmd_result)) { if (sshdr.sense_key == RECOVERED_ERROR && sshdr.asc == 0 && sshdr.ascq == 0x1d) cmd_result &= ~SAM_STAT_CHECK_CONDITION; @@ -490,9 +491,12 @@ int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg) cmd_result = scsi_execute(scsidev, scsi_cmd, DMA_NONE, NULL, 0, sensebuf, &sshdr, (10*HZ), 5, 0, 0, NULL); - if (driver_byte(cmd_result) == DRIVER_SENSE) {/* sense data available */ + if (cmd_result < 0) { + rc = cmd_result; + goto error; + } + if (scsi_sense_valid(&sshdr)) {/* sense data available */ u8 *desc = sensebuf + 8; - cmd_result &= ~(0xFF<<24); /* DRIVER_SENSE is not an error */ /* If we set cc then ATA pass-through will cause a * check condition even if no error. Filter that. */ @@ -638,7 +642,7 @@ static struct ata_queued_cmd *ata_scsi_qc_new(struct ata_device *dev, if (cmd->request->rq_flags & RQF_QUIET) qc->flags |= ATA_QCFLAG_QUIET; } else { - cmd->result = (DID_OK << 16) | (QUEUE_FULL << 1); + cmd->result = (DID_OK << 16) | SAM_STAT_TASK_SET_FULL; cmd->scsi_done(cmd); } @@ -858,8 +862,6 @@ static void ata_gen_passthru_sense(struct ata_queued_cmd *qc) memset(sb, 0, SCSI_SENSE_BUFFERSIZE); - cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; - /* * Use ata_to_sense_error() to map status register bits * onto sense key, asc & ascq. @@ -874,8 +876,7 @@ static void ata_gen_passthru_sense(struct ata_queued_cmd *qc) * ATA PASS-THROUGH INFORMATION AVAILABLE * Always in descriptor format sense. */ - scsi_build_sense_buffer(1, cmd->sense_buffer, - RECOVERED_ERROR, 0, 0x1D); + scsi_build_sense(cmd, 1, RECOVERED_ERROR, 0, 0x1D); } if ((cmd->sense_buffer[0] & 0x7f) >= 0x72) { @@ -957,8 +958,6 @@ static void ata_gen_ata_sense(struct ata_queued_cmd *qc) memset(sb, 0, SCSI_SENSE_BUFFERSIZE); - cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; - if (ata_dev_disabled(dev)) { /* Device disabled after error recovery */ /* LOGICAL UNIT NOT READY, HARD RESET REQUIRED */ @@ -4196,7 +4195,6 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd) case REQUEST_SENSE: ata_scsi_set_sense(dev, cmd, 0, 0, 0); - cmd->result = (DRIVER_SENSE << 24); break; /* if we reach this, then writeback caching is disabled, diff --git a/drivers/base/Makefile b/drivers/base/Makefile index 8b93a7f291ec..ef8e44a7d288 100644 --- a/drivers/base/Makefile +++ b/drivers/base/Makefile @@ -30,3 +30,6 @@ obj-y += test/ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG +# define_trace.h needs to know how to find our header +CFLAGS_trace.o := -I$(src) +obj-$(CONFIG_TRACING) += trace.o diff --git a/drivers/base/attribute_container.c b/drivers/base/attribute_container.c index 9c00d203d61e..01ef796c2055 100644 --- a/drivers/base/attribute_container.c +++ b/drivers/base/attribute_container.c @@ -284,8 +284,8 @@ fail: * matching classdev or fail all of them. * * @dev: The generic device to run the trigger for - * @fn the function to execute for each classdev. - * @undo A function to undo the work previously done in case of error + * @fn: the function to execute for each classdev. + * @undo: A function to undo the work previously done in case of error * * This function is a safe version of * attribute_container_device_trigger. It stops on the first error and @@ -343,7 +343,7 @@ attribute_container_device_trigger_safe(struct device *dev, * attribute_container_device_trigger - execute a trigger for each matching classdev * * @dev: The generic device to run the trigger for - * @fn the function to execute for each classdev. + * @fn: the function to execute for each classdev. * * This function is for executing a trigger when you need to know both * the container and the classdev. If you only care about the diff --git a/drivers/base/base.h b/drivers/base/base.h index e5f9b7e656c3..404db83ee5ec 100644 --- a/drivers/base/base.h +++ b/drivers/base/base.h @@ -152,7 +152,6 @@ extern int driver_add_groups(struct device_driver *drv, const struct attribute_group **groups); extern void driver_remove_groups(struct device_driver *drv, const struct attribute_group **groups); -int device_driver_attach(struct device_driver *drv, struct device *dev); void device_driver_detach(struct device *dev); extern char *make_class_name(const char *name, struct kobject *kobj); diff --git a/drivers/base/bus.c b/drivers/base/bus.c index 36d0c654ea61..1f6b4bd61056 100644 --- a/drivers/base/bus.c +++ b/drivers/base/bus.c @@ -210,15 +210,11 @@ static ssize_t bind_store(struct device_driver *drv, const char *buf, int err = -ENODEV; dev = bus_find_device_by_name(bus, NULL, buf); - if (dev && dev->driver == NULL && driver_match_device(drv, dev)) { + if (dev && driver_match_device(drv, dev)) { err = device_driver_attach(drv, dev); - - if (err > 0) { + if (!err) { /* success */ err = count; - } else if (err == 0) { - /* driver didn't accept device */ - err = -ENODEV; } } put_device(dev); diff --git a/drivers/base/component.c b/drivers/base/component.c index 272ba42392f0..5e79299f6c3f 100644 --- a/drivers/base/component.c +++ b/drivers/base/component.c @@ -63,7 +63,7 @@ struct master { bool bound; const struct component_master_ops *ops; - struct device *dev; + struct device *parent; struct component_match *match; }; @@ -95,7 +95,7 @@ static int component_devices_show(struct seq_file *s, void *data) seq_printf(s, "%-40s %20s\n", "master name", "status"); seq_puts(s, "-------------------------------------------------------------\n"); seq_printf(s, "%-40s %20s\n\n", - dev_name(m->dev), m->bound ? "bound" : "not bound"); + dev_name(m->parent), m->bound ? "bound" : "not bound"); seq_printf(s, "%-40s %20s\n", "device name", "status"); seq_puts(s, "-------------------------------------------------------------\n"); @@ -124,13 +124,13 @@ core_initcall(component_debug_init); static void component_master_debugfs_add(struct master *m) { - debugfs_create_file(dev_name(m->dev), 0444, component_debugfs_dir, m, + debugfs_create_file(dev_name(m->parent), 0444, component_debugfs_dir, m, &component_devices_fops); } static void component_master_debugfs_del(struct master *m) { - debugfs_remove(debugfs_lookup(dev_name(m->dev), component_debugfs_dir)); + debugfs_remove(debugfs_lookup(dev_name(m->parent), component_debugfs_dir)); } #else @@ -143,13 +143,13 @@ static void component_master_debugfs_del(struct master *m) #endif -static struct master *__master_find(struct device *dev, +static struct master *__master_find(struct device *parent, const struct component_master_ops *ops) { struct master *m; list_for_each_entry(m, &masters, node) - if (m->dev == dev && (!ops || m->ops == ops)) + if (m->parent == parent && (!ops || m->ops == ops)) return m; return NULL; @@ -189,7 +189,7 @@ static int find_components(struct master *master) struct component_match_array *mc = &match->compare[i]; struct component *c; - dev_dbg(master->dev, "Looking for component %zu\n", i); + dev_dbg(master->parent, "Looking for component %zu\n", i); if (match->compare[i].component) continue; @@ -200,7 +200,7 @@ static int find_components(struct master *master) break; } - dev_dbg(master->dev, "found component %s, duplicate %u\n", dev_name(c->dev), !!c->master); + dev_dbg(master->parent, "found component %s, duplicate %u\n", dev_name(c->dev), !!c->master); /* Attach this component to the master */ match->compare[i].duplicate = !!c->master; @@ -233,28 +233,28 @@ static int try_to_bring_up_master(struct master *master, { int ret; - dev_dbg(master->dev, "trying to bring up master\n"); + dev_dbg(master->parent, "trying to bring up master\n"); if (find_components(master)) { - dev_dbg(master->dev, "master has incomplete components\n"); + dev_dbg(master->parent, "master has incomplete components\n"); return 0; } if (component && component->master != master) { - dev_dbg(master->dev, "master is not for this component (%s)\n", + dev_dbg(master->parent, "master is not for this component (%s)\n", dev_name(component->dev)); return 0; } - if (!devres_open_group(master->dev, NULL, GFP_KERNEL)) + if (!devres_open_group(master->parent, NULL, GFP_KERNEL)) return -ENOMEM; /* Found all components */ - ret = master->ops->bind(master->dev); + ret = master->ops->bind(master->parent); if (ret < 0) { - devres_release_group(master->dev, NULL); + devres_release_group(master->parent, NULL); if (ret != -EPROBE_DEFER) - dev_info(master->dev, "master bind failed: %d\n", ret); + dev_info(master->parent, "master bind failed: %d\n", ret); return ret; } @@ -281,34 +281,28 @@ static int try_to_bring_up_masters(struct component *component) static void take_down_master(struct master *master) { if (master->bound) { - master->ops->unbind(master->dev); - devres_release_group(master->dev, NULL); + master->ops->unbind(master->parent); + devres_release_group(master->parent, NULL); master->bound = false; } } -static void component_match_release(struct device *master, - struct component_match *match) +static void devm_component_match_release(struct device *parent, void *res) { + struct component_match *match = res; unsigned int i; for (i = 0; i < match->num; i++) { struct component_match_array *mc = &match->compare[i]; if (mc->release) - mc->release(master, mc->data); + mc->release(parent, mc->data); } kfree(match->compare); } -static void devm_component_match_release(struct device *dev, void *res) -{ - component_match_release(dev, res); -} - -static int component_match_realloc(struct device *dev, - struct component_match *match, size_t num) +static int component_match_realloc(struct component_match *match, size_t num) { struct component_match_array *new; @@ -359,7 +353,7 @@ static void __component_match_add(struct device *master, size_t new_size = match->alloc + 16; int ret; - ret = component_match_realloc(master, match, new_size); + ret = component_match_realloc(match, new_size); if (ret) { *matchptr = ERR_PTR(ret); return; @@ -451,7 +445,7 @@ static void free_master(struct master *master) /** * component_master_add_with_match - register an aggregate driver - * @dev: device with the aggregate driver + * @parent: parent device of the aggregate driver * @ops: callbacks for the aggregate driver * @match: component match list for the aggregate driver * @@ -461,7 +455,7 @@ static void free_master(struct master *master) * &component_master_ops.bind from @ops. Must be unregistered by calling * component_master_del(). */ -int component_master_add_with_match(struct device *dev, +int component_master_add_with_match(struct device *parent, const struct component_master_ops *ops, struct component_match *match) { @@ -469,7 +463,7 @@ int component_master_add_with_match(struct device *dev, int ret; /* Reallocate the match array for its true size */ - ret = component_match_realloc(dev, match, match->num); + ret = component_match_realloc(match, match->num); if (ret) return ret; @@ -477,7 +471,7 @@ int component_master_add_with_match(struct device *dev, if (!master) return -ENOMEM; - master->dev = dev; + master->parent = parent; master->ops = ops; master->match = match; @@ -499,20 +493,20 @@ EXPORT_SYMBOL_GPL(component_master_add_with_match); /** * component_master_del - unregister an aggregate driver - * @dev: device with the aggregate driver + * @parent: parent device of the aggregate driver * @ops: callbacks for the aggregate driver * * Unregisters an aggregate driver registered with * component_master_add_with_match(). If necessary the aggregate driver is first * disassembled by calling &component_master_ops.unbind from @ops. */ -void component_master_del(struct device *dev, +void component_master_del(struct device *parent, const struct component_master_ops *ops) { struct master *master; mutex_lock(&component_mutex); - master = __master_find(dev, ops); + master = __master_find(parent, ops); if (master) { take_down_master(master); free_master(master); @@ -527,7 +521,7 @@ static void component_unbind(struct component *component, WARN_ON(!component->bound); if (component->ops && component->ops->unbind) - component->ops->unbind(component->dev, master->dev, data); + component->ops->unbind(component->dev, master->parent, data); component->bound = false; /* Release all resources claimed in the binding of this component */ @@ -536,14 +530,14 @@ static void component_unbind(struct component *component, /** * component_unbind_all - unbind all components of an aggregate driver - * @master_dev: device with the aggregate driver + * @parent: parent device of the aggregate driver * @data: opaque pointer, passed to all components * - * Unbinds all components of the aggregate @dev by passing @data to their + * Unbinds all components of the aggregate device by passing @data to their * &component_ops.unbind functions. Should be called from * &component_master_ops.unbind. */ -void component_unbind_all(struct device *master_dev, void *data) +void component_unbind_all(struct device *parent, void *data) { struct master *master; struct component *c; @@ -551,7 +545,7 @@ void component_unbind_all(struct device *master_dev, void *data) WARN_ON(!mutex_is_locked(&component_mutex)); - master = __master_find(master_dev, NULL); + master = __master_find(parent, NULL); if (!master) return; @@ -574,7 +568,7 @@ static int component_bind(struct component *component, struct master *master, * This allows us to roll-back a failed component without * affecting anything else. */ - if (!devres_open_group(master->dev, NULL, GFP_KERNEL)) + if (!devres_open_group(master->parent, NULL, GFP_KERNEL)) return -ENOMEM; /* @@ -583,14 +577,14 @@ static int component_bind(struct component *component, struct master *master, * at the appropriate moment. */ if (!devres_open_group(component->dev, component, GFP_KERNEL)) { - devres_release_group(master->dev, NULL); + devres_release_group(master->parent, NULL); return -ENOMEM; } - dev_dbg(master->dev, "binding %s (ops %ps)\n", + dev_dbg(master->parent, "binding %s (ops %ps)\n", dev_name(component->dev), component->ops); - ret = component->ops->bind(component->dev, master->dev, data); + ret = component->ops->bind(component->dev, master->parent, data); if (!ret) { component->bound = true; @@ -601,16 +595,16 @@ static int component_bind(struct component *component, struct master *master, * can clean those resources up independently. */ devres_close_group(component->dev, NULL); - devres_remove_group(master->dev, NULL); + devres_remove_group(master->parent, NULL); - dev_info(master->dev, "bound %s (ops %ps)\n", + dev_info(master->parent, "bound %s (ops %ps)\n", dev_name(component->dev), component->ops); } else { devres_release_group(component->dev, NULL); - devres_release_group(master->dev, NULL); + devres_release_group(master->parent, NULL); if (ret != -EPROBE_DEFER) - dev_err(master->dev, "failed to bind %s (ops %ps): %d\n", + dev_err(master->parent, "failed to bind %s (ops %ps): %d\n", dev_name(component->dev), component->ops, ret); } @@ -619,14 +613,14 @@ static int component_bind(struct component *component, struct master *master, /** * component_bind_all - bind all components of an aggregate driver - * @master_dev: device with the aggregate driver + * @parent: parent device of the aggregate driver * @data: opaque pointer, passed to all components * * Binds all components of the aggregate @dev by passing @data to their * &component_ops.bind functions. Should be called from * &component_master_ops.bind. */ -int component_bind_all(struct device *master_dev, void *data) +int component_bind_all(struct device *parent, void *data) { struct master *master; struct component *c; @@ -635,7 +629,7 @@ int component_bind_all(struct device *master_dev, void *data) WARN_ON(!mutex_is_locked(&component_mutex)); - master = __master_find(master_dev, NULL); + master = __master_find(parent, NULL); if (!master) return -EINVAL; diff --git a/drivers/base/core.c b/drivers/base/core.c index 2a61003ea2c1..cadcade65825 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -2409,6 +2409,25 @@ static ssize_t online_store(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(online); +static ssize_t removable_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + const char *loc; + + switch (dev->removable) { + case DEVICE_REMOVABLE: + loc = "removable"; + break; + case DEVICE_FIXED: + loc = "fixed"; + break; + default: + loc = "unknown"; + } + return sysfs_emit(buf, "%s\n", loc); +} +static DEVICE_ATTR_RO(removable); + int device_add_groups(struct device *dev, const struct attribute_group **groups) { return sysfs_create_groups(&dev->kobj, groups); @@ -2586,8 +2605,16 @@ static int device_add_attrs(struct device *dev) goto err_remove_dev_online; } + if (dev_removable_is_valid(dev)) { + error = device_create_file(dev, &dev_attr_removable); + if (error) + goto err_remove_dev_waiting_for_supplier; + } + return 0; + err_remove_dev_waiting_for_supplier: + device_remove_file(dev, &dev_attr_waiting_for_supplier); err_remove_dev_online: device_remove_file(dev, &dev_attr_online); err_remove_dev_groups: @@ -2607,6 +2634,7 @@ static void device_remove_attrs(struct device *dev) struct class *class = dev->class; const struct device_type *type = dev->type; + device_remove_file(dev, &dev_attr_removable); device_remove_file(dev, &dev_attr_waiting_for_supplier); device_remove_file(dev, &dev_attr_online); device_remove_groups(dev, dev->groups); @@ -3442,7 +3470,7 @@ bool kill_device(struct device *dev) * to run while we are tearing out the bus/class/sysfs from * underneath the device. */ - lockdep_assert_held(&dev->mutex); + device_lock_assert(dev); if (dev->p->dead) return false; diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 2b9e41377a07..5ef14db97904 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -175,7 +175,7 @@ static struct attribute *crash_note_cpu_attrs[] = { NULL }; -static struct attribute_group crash_note_cpu_attr_group = { +static const struct attribute_group crash_note_cpu_attr_group = { .attrs = crash_note_cpu_attrs, }; #endif @@ -475,7 +475,7 @@ static struct attribute *cpu_root_attrs[] = { NULL }; -static struct attribute_group cpu_root_attr_group = { +static const struct attribute_group cpu_root_attr_group = { .attrs = cpu_root_attrs, }; diff --git a/drivers/base/dd.c b/drivers/base/dd.c index ecd7cf848daf..daeb9b5763ae 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -471,6 +471,8 @@ static void driver_sysfs_remove(struct device *dev) * (It is ok to call with no other effort from a driver's probe() method.) * * This function must be called with the device lock held. + * + * Callers should prefer to use device_driver_attach() instead. */ int device_bind_driver(struct device *dev) { @@ -491,15 +493,6 @@ EXPORT_SYMBOL_GPL(device_bind_driver); static atomic_t probe_count = ATOMIC_INIT(0); static DECLARE_WAIT_QUEUE_HEAD(probe_waitqueue); -static void driver_deferred_probe_add_trigger(struct device *dev, - int local_trigger_count) -{ - driver_deferred_probe_add(dev); - /* Did a trigger occur while probing? Need to re-trigger if yes */ - if (local_trigger_count != atomic_read(&deferred_trigger_count)) - driver_deferred_probe_trigger(); -} - static ssize_t state_synced_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -513,12 +506,43 @@ static ssize_t state_synced_show(struct device *dev, } static DEVICE_ATTR_RO(state_synced); + +static int call_driver_probe(struct device *dev, struct device_driver *drv) +{ + int ret = 0; + + if (dev->bus->probe) + ret = dev->bus->probe(dev); + else if (drv->probe) + ret = drv->probe(dev); + + switch (ret) { + case 0: + break; + case -EPROBE_DEFER: + /* Driver requested deferred probing */ + dev_dbg(dev, "Driver %s requests probe deferral\n", drv->name); + break; + case -ENODEV: + case -ENXIO: + pr_debug("%s: probe of %s rejects match %d\n", + drv->name, dev_name(dev), ret); + break; + default: + /* driver matched but the probe failed */ + pr_warn("%s: probe of %s failed with error %d\n", + drv->name, dev_name(dev), ret); + break; + } + + return ret; +} + static int really_probe(struct device *dev, struct device_driver *drv) { - int ret = -EPROBE_DEFER; - int local_trigger_count = atomic_read(&deferred_trigger_count); bool test_remove = IS_ENABLED(CONFIG_DEBUG_TEST_DRIVER_REMOVE) && !drv->suppress_bind_attrs; + int ret; if (defer_all_probes) { /* @@ -527,17 +551,13 @@ static int really_probe(struct device *dev, struct device_driver *drv) * wait_for_device_probe() right after that to avoid any races. */ dev_dbg(dev, "Driver %s force probe deferral\n", drv->name); - driver_deferred_probe_add(dev); - return ret; + return -EPROBE_DEFER; } ret = device_links_check_suppliers(dev); - if (ret == -EPROBE_DEFER) - driver_deferred_probe_add_trigger(dev, local_trigger_count); if (ret) return ret; - atomic_inc(&probe_count); pr_debug("bus: '%s': %s: probing driver %s with device %s\n", drv->bus->name, __func__, drv->name, dev_name(dev)); if (!list_empty(&dev->devres_head)) { @@ -572,14 +592,14 @@ re_probe: goto probe_failed; } - if (dev->bus->probe) { - ret = dev->bus->probe(dev); - if (ret) - goto probe_failed; - } else if (drv->probe) { - ret = drv->probe(dev); - if (ret) - goto probe_failed; + ret = call_driver_probe(dev, drv); + if (ret) { + /* + * Return probe errors as positive values so that the callers + * can distinguish them from other errors. + */ + ret = -ret; + goto probe_failed; } if (device_add_groups(dev, drv->dev_groups)) { @@ -621,7 +641,6 @@ re_probe: dev->pm_domain->sync(dev); driver_bound(dev); - ret = 1; pr_debug("bus: '%s': %s: bound device %s to driver %s\n", drv->bus->name, __func__, dev_name(dev), drv->name); goto done; @@ -650,31 +669,7 @@ pinctrl_bind_failed: dev->pm_domain->dismiss(dev); pm_runtime_reinit(dev); dev_pm_set_driver_flags(dev, 0); - - switch (ret) { - case -EPROBE_DEFER: - /* Driver requested deferred probing */ - dev_dbg(dev, "Driver %s requests probe deferral\n", drv->name); - driver_deferred_probe_add_trigger(dev, local_trigger_count); - break; - case -ENODEV: - case -ENXIO: - pr_debug("%s: probe of %s rejects match %d\n", - drv->name, dev_name(dev), ret); - break; - default: - /* driver matched but the probe failed */ - pr_warn("%s: probe of %s failed with error %d\n", - drv->name, dev_name(dev), ret); - } - /* - * Ignore errors returned by ->probe so that the next driver can try - * its luck. - */ - ret = 0; done: - atomic_dec(&probe_count); - wake_up_all(&probe_waitqueue); return ret; } @@ -728,25 +723,14 @@ void wait_for_device_probe(void) } EXPORT_SYMBOL_GPL(wait_for_device_probe); -/** - * driver_probe_device - attempt to bind device & driver together - * @drv: driver to bind a device to - * @dev: device to try to bind to the driver - * - * This function returns -ENODEV if the device is not registered, - * 1 if the device is bound successfully and 0 otherwise. - * - * This function must be called with @dev lock held. When called for a - * USB interface, @dev->parent lock must be held as well. - * - * If the device has a parent, runtime-resume the parent before driver probing. - */ -static int driver_probe_device(struct device_driver *drv, struct device *dev) +static int __driver_probe_device(struct device_driver *drv, struct device *dev) { int ret = 0; - if (!device_is_registered(dev)) + if (dev->p->dead || !device_is_registered(dev)) return -ENODEV; + if (dev->driver) + return -EBUSY; dev->can_match = true; pr_debug("bus: '%s': %s: matched device %s with driver %s\n", @@ -770,6 +754,42 @@ static int driver_probe_device(struct device_driver *drv, struct device *dev) return ret; } +/** + * driver_probe_device - attempt to bind device & driver together + * @drv: driver to bind a device to + * @dev: device to try to bind to the driver + * + * This function returns -ENODEV if the device is not registered, -EBUSY if it + * already has a driver, 0 if the device is bound successfully and a positive + * (inverted) error code for failures from the ->probe method. + * + * This function must be called with @dev lock held. When called for a + * USB interface, @dev->parent lock must be held as well. + * + * If the device has a parent, runtime-resume the parent before driver probing. + */ +static int driver_probe_device(struct device_driver *drv, struct device *dev) +{ + int trigger_count = atomic_read(&deferred_trigger_count); + int ret; + + atomic_inc(&probe_count); + ret = __driver_probe_device(drv, dev); + if (ret == -EPROBE_DEFER || ret == EPROBE_DEFER) { + driver_deferred_probe_add(dev); + + /* + * Did a trigger occur while probing? Need to re-trigger if yes + */ + if (trigger_count != atomic_read(&deferred_trigger_count) && + !defer_all_probes) + driver_deferred_probe_trigger(); + } + atomic_dec(&probe_count); + wake_up_all(&probe_waitqueue); + return ret; +} + static inline bool cmdline_requested_async_probing(const char *drv_name) { return parse_option_str(async_probe_drv_names, drv_name); @@ -867,7 +887,14 @@ static int __device_attach_driver(struct device_driver *drv, void *_data) if (data->check_async && async_allowed != data->want_async) return 0; - return driver_probe_device(drv, dev); + /* + * Ignore errors returned by ->probe so that the next driver can try + * its luck. + */ + ret = driver_probe_device(drv, dev); + if (ret < 0) + return ret; + return ret == 0; } static void __device_attach_async_helper(void *_dev, async_cookie_t cookie) @@ -1023,43 +1050,34 @@ static void __device_driver_unlock(struct device *dev, struct device *parent) * @dev: Device to attach it to * * Manually attach driver to a device. Will acquire both @dev lock and - * @dev->parent lock if needed. + * @dev->parent lock if needed. Returns 0 on success, -ERR on failure. */ int device_driver_attach(struct device_driver *drv, struct device *dev) { - int ret = 0; + int ret; __device_driver_lock(dev, dev->parent); - - /* - * If device has been removed or someone has already successfully - * bound a driver before us just skip the driver probe call. - */ - if (!dev->p->dead && !dev->driver) - ret = driver_probe_device(drv, dev); - + ret = __driver_probe_device(drv, dev); __device_driver_unlock(dev, dev->parent); + /* also return probe errors as normal negative errnos */ + if (ret > 0) + ret = -ret; + if (ret == -EPROBE_DEFER) + return -EAGAIN; return ret; } +EXPORT_SYMBOL_GPL(device_driver_attach); static void __driver_attach_async_helper(void *_dev, async_cookie_t cookie) { struct device *dev = _dev; struct device_driver *drv; - int ret = 0; + int ret; __device_driver_lock(dev, dev->parent); - drv = dev->p->async_driver; - - /* - * If device has been removed or someone has already successfully - * bound a driver before us just skip the driver probe call. - */ - if (!dev->p->dead && !dev->driver) - ret = driver_probe_device(drv, dev); - + ret = driver_probe_device(drv, dev); __device_driver_unlock(dev, dev->parent); dev_dbg(dev, "driver %s async attach completed: %d\n", drv->name, ret); @@ -1114,7 +1132,9 @@ static int __driver_attach(struct device *dev, void *data) return 0; } - device_driver_attach(drv, dev); + __device_driver_lock(dev, dev->parent); + driver_probe_device(drv, dev); + __device_driver_unlock(dev, dev->parent); return 0; } diff --git a/drivers/base/devcoredump.c b/drivers/base/devcoredump.c index 8eec0e0ddff7..f4d794d6bb85 100644 --- a/drivers/base/devcoredump.c +++ b/drivers/base/devcoredump.c @@ -3,10 +3,6 @@ * Copyright(c) 2014 Intel Mobile Communications GmbH * Copyright(c) 2015 Intel Deutschland GmbH * - * Contact Information: - * Intel Linux Wireless - * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 - * * Author: Johannes Berg */ #include diff --git a/drivers/base/devres.c b/drivers/base/devres.c index 8746f2212781..eaa9a5cd1db9 100644 --- a/drivers/base/devres.c +++ b/drivers/base/devres.c @@ -14,14 +14,13 @@ #include #include "base.h" +#include "trace.h" struct devres_node { struct list_head entry; dr_release_t release; -#ifdef CONFIG_DEBUG_DEVRES const char *name; size_t size; -#endif }; struct devres { @@ -43,10 +42,6 @@ struct devres_group { /* -- 8 pointers */ }; -#ifdef CONFIG_DEBUG_DEVRES -static int log_devres = 0; -module_param_named(log, log_devres, int, S_IRUGO | S_IWUSR); - static void set_node_dbginfo(struct devres_node *node, const char *name, size_t size) { @@ -54,7 +49,11 @@ static void set_node_dbginfo(struct devres_node *node, const char *name, node->size = size; } -static void devres_log(struct device *dev, struct devres_node *node, +#ifdef CONFIG_DEBUG_DEVRES +static int log_devres = 0; +module_param_named(log, log_devres, int, S_IRUGO | S_IWUSR); + +static void devres_dbg(struct device *dev, struct devres_node *node, const char *op) { if (unlikely(log_devres)) @@ -62,10 +61,16 @@ static void devres_log(struct device *dev, struct devres_node *node, op, node, node->name, node->size); } #else /* CONFIG_DEBUG_DEVRES */ -#define set_node_dbginfo(node, n, s) do {} while (0) -#define devres_log(dev, node, op) do {} while (0) +#define devres_dbg(dev, node, op) do {} while (0) #endif /* CONFIG_DEBUG_DEVRES */ +static void devres_log(struct device *dev, struct devres_node *node, + const char *op) +{ + trace_devres_log(dev, op, node, node->name, node->size); + devres_dbg(dev, node, op); +} + /* * Release functions for devres group. These callbacks are used only * for identification. @@ -134,9 +139,23 @@ static void replace_dr(struct device *dev, list_replace(&old->entry, &new->entry); } -#ifdef CONFIG_DEBUG_DEVRES -void * __devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid, - const char *name) +/** + * __devres_alloc_node - Allocate device resource data + * @release: Release function devres will be associated with + * @size: Allocation size + * @gfp: Allocation flags + * @nid: NUMA node + * @name: Name of the resource + * + * Allocate devres of @size bytes. The allocated area is zeroed, then + * associated with @release. The returned pointer can be passed to + * other devres_*() functions. + * + * RETURNS: + * Pointer to allocated devres on success, NULL on failure. + */ +void *__devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid, + const char *name) { struct devres *dr; @@ -147,32 +166,6 @@ void * __devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid return dr->data; } EXPORT_SYMBOL_GPL(__devres_alloc_node); -#else -/** - * devres_alloc_node - Allocate device resource data - * @release: Release function devres will be associated with - * @size: Allocation size - * @gfp: Allocation flags - * @nid: NUMA node - * - * Allocate devres of @size bytes. The allocated area is zeroed, then - * associated with @release. The returned pointer can be passed to - * other devres_*() functions. - * - * RETURNS: - * Pointer to allocated devres on success, NULL on failure. - */ -void * devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid) -{ - struct devres *dr; - - dr = alloc_dr(release, size, gfp | __GFP_ZERO, nid); - if (unlikely(!dr)) - return NULL; - return dr->data; -} -EXPORT_SYMBOL_GPL(devres_alloc_node); -#endif /** * devres_for_each_res - Resource iterator @@ -438,20 +431,16 @@ static int remove_nodes(struct device *dev, struct list_head *first, struct list_head *end, struct list_head *todo) { + struct devres_node *node, *n; int cnt = 0, nr_groups = 0; - struct list_head *cur; /* First pass - move normal devres entries to @todo and clear * devres_group colors. */ - cur = first; - while (cur != end) { - struct devres_node *node; + node = list_entry(first, struct devres_node, entry); + list_for_each_entry_safe_from(node, n, end, entry) { struct devres_group *grp; - node = list_entry(cur, struct devres_node, entry); - cur = cur->next; - grp = node_to_group(node); if (grp) { /* clear color of group markers in the first pass */ @@ -471,18 +460,14 @@ static int remove_nodes(struct device *dev, /* Second pass - Scan groups and color them. A group gets * color value of two iff the group is wholly contained in - * [cur, end). That is, for a closed group, both opening and - * closing markers should be in the range, while just the + * [current node, end). That is, for a closed group, both opening + * and closing markers should be in the range, while just the * opening marker is enough for an open group. */ - cur = first; - while (cur != end) { - struct devres_node *node; + node = list_entry(first, struct devres_node, entry); + list_for_each_entry_safe_from(node, n, end, entry) { struct devres_group *grp; - node = list_entry(cur, struct devres_node, entry); - cur = cur->next; - grp = node_to_group(node); BUG_ON(!grp || list_empty(&grp->node[0].entry)); @@ -492,7 +477,7 @@ static int remove_nodes(struct device *dev, BUG_ON(grp->color <= 0 || grp->color > 2); if (grp->color == 2) { - /* No need to update cur or end. The removed + /* No need to update current node or end. The removed * nodes are always before both. */ list_move_tail(&grp->node[0].entry, todo); @@ -503,28 +488,18 @@ static int remove_nodes(struct device *dev, return cnt; } -static int release_nodes(struct device *dev, struct list_head *first, - struct list_head *end, unsigned long flags) - __releases(&dev->devres_lock) +static void release_nodes(struct device *dev, struct list_head *todo) { - LIST_HEAD(todo); - int cnt; struct devres *dr, *tmp; - cnt = remove_nodes(dev, first, end, &todo); - - spin_unlock_irqrestore(&dev->devres_lock, flags); - /* Release. Note that both devres and devres_group are * handled as devres in the following loop. This is safe. */ - list_for_each_entry_safe_reverse(dr, tmp, &todo, node.entry) { + list_for_each_entry_safe_reverse(dr, tmp, todo, node.entry) { devres_log(dev, &dr->node, "REL"); dr->node.release(dev, dr->data); kfree(dr); } - - return cnt; } /** @@ -537,13 +512,23 @@ static int release_nodes(struct device *dev, struct list_head *first, int devres_release_all(struct device *dev) { unsigned long flags; + LIST_HEAD(todo); + int cnt; /* Looks like an uninitialized device structure */ if (WARN_ON(dev->devres_head.next == NULL)) return -ENODEV; + + /* Nothing to release if list is empty */ + if (list_empty(&dev->devres_head)) + return 0; + spin_lock_irqsave(&dev->devres_lock, flags); - return release_nodes(dev, dev->devres_head.next, &dev->devres_head, - flags); + cnt = remove_nodes(dev, dev->devres_head.next, &dev->devres_head, &todo); + spin_unlock_irqrestore(&dev->devres_lock, flags); + + release_nodes(dev, &todo); + return cnt; } /** @@ -679,6 +664,7 @@ int devres_release_group(struct device *dev, void *id) { struct devres_group *grp; unsigned long flags; + LIST_HEAD(todo); int cnt = 0; spin_lock_irqsave(&dev->devres_lock, flags); @@ -691,7 +677,10 @@ int devres_release_group(struct device *dev, void *id) if (!list_empty(&grp->node[1].entry)) end = grp->node[1].entry.next; - cnt = release_nodes(dev, first, end, flags); + cnt = remove_nodes(dev, first, end, &todo); + spin_unlock_irqrestore(&dev->devres_lock, flags); + + release_nodes(dev, &todo); } else { WARN_ON(1); spin_unlock_irqrestore(&dev->devres_lock, flags); diff --git a/drivers/base/firmware_loader/builtin/Makefile b/drivers/base/firmware_loader/builtin/Makefile index 5fa7ce3745a0..101754ad48d9 100644 --- a/drivers/base/firmware_loader/builtin/Makefile +++ b/drivers/base/firmware_loader/builtin/Makefile @@ -8,7 +8,6 @@ fwdir := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir)) obj-y := $(addsuffix .gen.o, $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE))) FWNAME = $(patsubst $(obj)/%.gen.S,%,$@) -comma := , FWSTR = $(subst $(comma),_,$(subst /,_,$(subst .,_,$(subst -,_,$(FWNAME))))) ASM_WORD = $(if $(CONFIG_64BIT),.quad,.long) ASM_ALIGN = $(if $(CONFIG_64BIT),3,2) diff --git a/drivers/base/memory.c b/drivers/base/memory.c index d5ffaab3cb61..aa31a21f33d7 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -596,7 +596,7 @@ static struct attribute *memory_memblk_attrs[] = { NULL }; -static struct attribute_group memory_memblk_attr_group = { +static const struct attribute_group memory_memblk_attr_group = { .attrs = memory_memblk_attrs, }; @@ -772,7 +772,7 @@ static struct attribute *memory_root_attrs[] = { NULL }; -static struct attribute_group memory_root_attr_group = { +static const struct attribute_group memory_root_attr_group = { .attrs = memory_root_attrs, }; diff --git a/drivers/base/node.c b/drivers/base/node.c index 9db297431b97..4a4ae868ad9f 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -233,7 +233,7 @@ static ssize_t name##_show(struct device *dev, \ return sysfs_emit(buf, fmt "\n", \ to_cache_info(dev)->cache_attrs.name); \ } \ -DEVICE_ATTR_RO(name); +static DEVICE_ATTR_RO(name); CACHE_ATTR(size, "%llu") CACHE_ATTR(line_size, "%u") @@ -1038,7 +1038,7 @@ static struct attribute *node_state_attrs[] = { NULL }; -static struct attribute_group memory_root_attr_group = { +static const struct attribute_group memory_root_attr_group = { .attrs = node_state_attrs, }; diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 9cd34def2237..8640578f45e9 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -124,26 +124,6 @@ void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); -/** - * devm_platform_ioremap_resource_wc - write-combined variant of - * devm_platform_ioremap_resource() - * - * @pdev: platform device to use both for memory resource lookup as well as - * resource management - * @index: resource index - * - * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code - * on failure. - */ -void __iomem *devm_platform_ioremap_resource_wc(struct platform_device *pdev, - unsigned int index) -{ - struct resource *res; - - res = platform_get_resource(pdev, IORESOURCE_MEM, index); - return devm_ioremap_resource_wc(&pdev->dev, res); -} - /** * devm_platform_ioremap_resource_byname - call devm_ioremap_resource for * a platform device, retrieve the @@ -1355,7 +1335,7 @@ static umode_t platform_dev_attrs_visible(struct kobject *kobj, struct attribute return a->mode; } -static struct attribute_group platform_dev_group = { +static const struct attribute_group platform_dev_group = { .attrs = platform_dev_attrs, .is_visible = platform_dev_attrs_visible, }; diff --git a/drivers/base/property.c b/drivers/base/property.c index 1f533b314efc..d0874f6c29bb 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -627,14 +627,15 @@ EXPORT_SYMBOL_GPL(fwnode_get_next_parent); */ struct device *fwnode_get_next_parent_dev(struct fwnode_handle *fwnode) { - struct device *dev = NULL; + struct device *dev; fwnode_handle_get(fwnode); do { fwnode = fwnode_get_next_parent(fwnode); - if (fwnode) - dev = get_dev_from_fwnode(fwnode); - } while (fwnode && !dev); + if (!fwnode) + return NULL; + dev = get_dev_from_fwnode(fwnode); + } while (!dev); fwnode_handle_put(fwnode); return dev; } @@ -742,10 +743,9 @@ fwnode_get_next_available_child_node(const struct fwnode_handle *fwnode, do { next_child = fwnode_get_next_child_node(fwnode, next_child); - - if (!next_child || fwnode_device_is_available(next_child)) - break; - } while (next_child); + if (!next_child) + return NULL; + } while (!fwnode_device_is_available(next_child)); return next_child; } diff --git a/drivers/base/test/property-entry-test.c b/drivers/base/test/property-entry-test.c index 1106fedcceed..6071d5bc128c 100644 --- a/drivers/base/test/property-entry-test.c +++ b/drivers/base/test/property-entry-test.c @@ -32,11 +32,11 @@ static void pe_test_uints(struct kunit *test) error = fwnode_property_read_u8(node, "prop-u8", &val_u8); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u8, 8); + KUNIT_EXPECT_EQ(test, val_u8, 8); error = fwnode_property_read_u8_array(node, "prop-u8", array_u8, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u8[0], 8); + KUNIT_EXPECT_EQ(test, array_u8[0], 8); error = fwnode_property_read_u8_array(node, "prop-u8", array_u8, 2); KUNIT_EXPECT_NE(test, error, 0); @@ -49,14 +49,14 @@ static void pe_test_uints(struct kunit *test) error = fwnode_property_read_u16(node, "prop-u16", &val_u16); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u16, 16); + KUNIT_EXPECT_EQ(test, val_u16, 16); error = fwnode_property_count_u16(node, "prop-u16"); KUNIT_EXPECT_EQ(test, error, 1); error = fwnode_property_read_u16_array(node, "prop-u16", array_u16, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u16[0], 16); + KUNIT_EXPECT_EQ(test, array_u16[0], 16); error = fwnode_property_read_u16_array(node, "prop-u16", array_u16, 2); KUNIT_EXPECT_NE(test, error, 0); @@ -69,14 +69,14 @@ static void pe_test_uints(struct kunit *test) error = fwnode_property_read_u32(node, "prop-u32", &val_u32); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u32, 32); + KUNIT_EXPECT_EQ(test, val_u32, 32); error = fwnode_property_count_u32(node, "prop-u32"); KUNIT_EXPECT_EQ(test, error, 1); error = fwnode_property_read_u32_array(node, "prop-u32", array_u32, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u32[0], 32); + KUNIT_EXPECT_EQ(test, array_u32[0], 32); error = fwnode_property_read_u32_array(node, "prop-u32", array_u32, 2); KUNIT_EXPECT_NE(test, error, 0); @@ -89,14 +89,14 @@ static void pe_test_uints(struct kunit *test) error = fwnode_property_read_u64(node, "prop-u64", &val_u64); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u64, 64); + KUNIT_EXPECT_EQ(test, val_u64, 64); error = fwnode_property_count_u64(node, "prop-u64"); KUNIT_EXPECT_EQ(test, error, 1); error = fwnode_property_read_u64_array(node, "prop-u64", array_u64, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u64[0], 64); + KUNIT_EXPECT_EQ(test, array_u64[0], 64); error = fwnode_property_read_u64_array(node, "prop-u64", array_u64, 2); KUNIT_EXPECT_NE(test, error, 0); @@ -140,19 +140,19 @@ static void pe_test_uint_arrays(struct kunit *test) error = fwnode_property_read_u8(node, "prop-u8", &val_u8); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u8, 8); + KUNIT_EXPECT_EQ(test, val_u8, 8); error = fwnode_property_count_u8(node, "prop-u8"); KUNIT_EXPECT_EQ(test, error, 10); error = fwnode_property_read_u8_array(node, "prop-u8", array_u8, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u8[0], 8); + KUNIT_EXPECT_EQ(test, array_u8[0], 8); error = fwnode_property_read_u8_array(node, "prop-u8", array_u8, 2); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u8[0], 8); - KUNIT_EXPECT_EQ(test, (int)array_u8[1], 9); + KUNIT_EXPECT_EQ(test, array_u8[0], 8); + KUNIT_EXPECT_EQ(test, array_u8[1], 9); error = fwnode_property_read_u8_array(node, "prop-u8", array_u8, 17); KUNIT_EXPECT_NE(test, error, 0); @@ -165,19 +165,19 @@ static void pe_test_uint_arrays(struct kunit *test) error = fwnode_property_read_u16(node, "prop-u16", &val_u16); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u16, 16); + KUNIT_EXPECT_EQ(test, val_u16, 16); error = fwnode_property_count_u16(node, "prop-u16"); KUNIT_EXPECT_EQ(test, error, 10); error = fwnode_property_read_u16_array(node, "prop-u16", array_u16, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u16[0], 16); + KUNIT_EXPECT_EQ(test, array_u16[0], 16); error = fwnode_property_read_u16_array(node, "prop-u16", array_u16, 2); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u16[0], 16); - KUNIT_EXPECT_EQ(test, (int)array_u16[1], 17); + KUNIT_EXPECT_EQ(test, array_u16[0], 16); + KUNIT_EXPECT_EQ(test, array_u16[1], 17); error = fwnode_property_read_u16_array(node, "prop-u16", array_u16, 17); KUNIT_EXPECT_NE(test, error, 0); @@ -190,19 +190,19 @@ static void pe_test_uint_arrays(struct kunit *test) error = fwnode_property_read_u32(node, "prop-u32", &val_u32); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u32, 32); + KUNIT_EXPECT_EQ(test, val_u32, 32); error = fwnode_property_count_u32(node, "prop-u32"); KUNIT_EXPECT_EQ(test, error, 10); error = fwnode_property_read_u32_array(node, "prop-u32", array_u32, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u32[0], 32); + KUNIT_EXPECT_EQ(test, array_u32[0], 32); error = fwnode_property_read_u32_array(node, "prop-u32", array_u32, 2); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u32[0], 32); - KUNIT_EXPECT_EQ(test, (int)array_u32[1], 33); + KUNIT_EXPECT_EQ(test, array_u32[0], 32); + KUNIT_EXPECT_EQ(test, array_u32[1], 33); error = fwnode_property_read_u32_array(node, "prop-u32", array_u32, 17); KUNIT_EXPECT_NE(test, error, 0); @@ -215,19 +215,19 @@ static void pe_test_uint_arrays(struct kunit *test) error = fwnode_property_read_u64(node, "prop-u64", &val_u64); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)val_u64, 64); + KUNIT_EXPECT_EQ(test, val_u64, 64); error = fwnode_property_count_u64(node, "prop-u64"); KUNIT_EXPECT_EQ(test, error, 10); error = fwnode_property_read_u64_array(node, "prop-u64", array_u64, 1); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u64[0], 64); + KUNIT_EXPECT_EQ(test, array_u64[0], 64); error = fwnode_property_read_u64_array(node, "prop-u64", array_u64, 2); KUNIT_EXPECT_EQ(test, error, 0); - KUNIT_EXPECT_EQ(test, (int)array_u64[0], 64); - KUNIT_EXPECT_EQ(test, (int)array_u64[1], 65); + KUNIT_EXPECT_EQ(test, array_u64[0], 64); + KUNIT_EXPECT_EQ(test, array_u64[1], 65); error = fwnode_property_read_u64_array(node, "prop-u64", array_u64, 17); KUNIT_EXPECT_NE(test, error, 0); @@ -358,13 +358,13 @@ static void pe_test_move_inline_u8(struct kunit *test) KUNIT_EXPECT_TRUE(test, copy[0].is_inline); data_ptr = (u8 *)©[0].value; - KUNIT_EXPECT_EQ(test, (int)data_ptr[0], 1); - KUNIT_EXPECT_EQ(test, (int)data_ptr[1], 2); + KUNIT_EXPECT_EQ(test, data_ptr[0], 1); + KUNIT_EXPECT_EQ(test, data_ptr[1], 2); KUNIT_EXPECT_FALSE(test, copy[1].is_inline); data_ptr = copy[1].pointer; - KUNIT_EXPECT_EQ(test, (int)data_ptr[0], 5); - KUNIT_EXPECT_EQ(test, (int)data_ptr[1], 6); + KUNIT_EXPECT_EQ(test, data_ptr[0], 5); + KUNIT_EXPECT_EQ(test, data_ptr[1], 6); property_entries_free(copy); } diff --git a/drivers/base/trace.c b/drivers/base/trace.c new file mode 100644 index 000000000000..b24b0a309c4a --- /dev/null +++ b/drivers/base/trace.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device core Trace Support + * Copyright (C) 2021, Intel Corporation + * + * Author: Andy Shevchenko + */ + +#define CREATE_TRACE_POINTS +#include "trace.h" diff --git a/drivers/base/trace.h b/drivers/base/trace.h new file mode 100644 index 000000000000..3192e18f877e --- /dev/null +++ b/drivers/base/trace.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device core Trace Support + * Copyright (C) 2021, Intel Corporation + * + * Author: Andy Shevchenko + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM dev + +#if !defined(__DEV_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define __DEV_TRACE_H + +#include +#include +#include + +DECLARE_EVENT_CLASS(devres, + TP_PROTO(struct device *dev, const char *op, void *node, const char *name, size_t size), + TP_ARGS(dev, op, node, name, size), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __field(struct device *, dev) + __field(const char *, op) + __field(void *, node) + __field(const char *, name) + __field(size_t, size) + ), + TP_fast_assign( + __assign_str(devname, dev_name(dev)); + __entry->op = op; + __entry->node = node; + __entry->name = name; + __entry->size = size; + ), + TP_printk("%s %3s %p %s (%zu bytes)", __get_str(devname), + __entry->op, __entry->node, __entry->name, __entry->size) +); + +DEFINE_EVENT(devres, devres_log, + TP_PROTO(struct device *dev, const char *op, void *node, const char *name, size_t size), + TP_ARGS(dev, op, node, name, size) +); + +#endif /* __DEV_TRACE_H */ + +/* this part has to be here */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace + +#include diff --git a/drivers/block/rnbd/rnbd-clt.c b/drivers/block/rnbd/rnbd-clt.c index f4fa45d24c0b..e9cc413495f0 100644 --- a/drivers/block/rnbd/rnbd-clt.c +++ b/drivers/block/rnbd/rnbd-clt.c @@ -92,7 +92,7 @@ static int rnbd_clt_set_dev_attr(struct rnbd_clt_dev *dev, dev->fua = !!(rsp->cache_policy & RNBD_FUA); dev->max_hw_sectors = sess->max_io_size / SECTOR_SIZE; - dev->max_segments = BMAX_SEGMENTS; + dev->max_segments = sess->max_segments; return 0; } @@ -1292,7 +1292,7 @@ find_and_get_or_create_sess(const char *sessname, sess->rtrs = rtrs_clt_open(&rtrs_ops, sessname, paths, path_cnt, port_nr, 0, /* Do not use pdu of rtrs */ - RECONNECT_DELAY, BMAX_SEGMENTS, + RECONNECT_DELAY, MAX_RECONNECTS, nr_poll_queues); if (IS_ERR(sess->rtrs)) { err = PTR_ERR(sess->rtrs); @@ -1306,6 +1306,7 @@ find_and_get_or_create_sess(const char *sessname, sess->max_io_size = attrs.max_io_size; sess->queue_depth = attrs.queue_depth; sess->nr_poll_queues = nr_poll_queues; + sess->max_segments = attrs.max_segments; err = setup_mq_tags(sess); if (err) diff --git a/drivers/block/rnbd/rnbd-clt.h b/drivers/block/rnbd/rnbd-clt.h index b5322c5aaac0..9ef8c4f306f2 100644 --- a/drivers/block/rnbd/rnbd-clt.h +++ b/drivers/block/rnbd/rnbd-clt.h @@ -20,10 +20,6 @@ #include "rnbd-proto.h" #include "rnbd-log.h" -/* Max. number of segments per IO request, Mellanox Connect X ~ Connect X5, - * choose minimial 30 for all, minus 1 for internal protocol, so 29. - */ -#define BMAX_SEGMENTS 29 /* time in seconds between reconnect tries, default to 30 s */ #define RECONNECT_DELAY 30 /* @@ -89,6 +85,7 @@ struct rnbd_clt_session { atomic_t busy; size_t queue_depth; u32 max_io_size; + u32 max_segments; struct blk_mq_tag_set tag_set; u32 nr_poll_queues; struct mutex lock; /* protects state and devs_list */ diff --git a/drivers/block/sunvdc.c b/drivers/block/sunvdc.c index c4631e684386..4d4bb810c2ae 100644 --- a/drivers/block/sunvdc.c +++ b/drivers/block/sunvdc.c @@ -1050,7 +1050,7 @@ err_out_release_mdesc: return err; } -static int vdc_port_remove(struct vio_dev *vdev) +static void vdc_port_remove(struct vio_dev *vdev) { struct vdc_port *port = dev_get_drvdata(&vdev->dev); @@ -1072,7 +1072,6 @@ static int vdc_port_remove(struct vio_dev *vdev) kfree(port); } - return 0; } static void vdc_requeue_inflight(struct vdc_port *port) diff --git a/drivers/block/zram/zram_drv.h b/drivers/block/zram/zram_drv.h index 74c411911b6e..80c3b43b4828 100644 --- a/drivers/block/zram/zram_drv.h +++ b/drivers/block/zram/zram_drv.h @@ -113,8 +113,8 @@ struct zram { * zram is claimed so open request will be failed */ bool claim; /* Protected by disk->open_mutex */ - struct file *backing_dev; #ifdef CONFIG_ZRAM_WRITEBACK + struct file *backing_dev; spinlock_t wb_limit_lock; bool wb_limit_enable; u64 bd_wb_limit; diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c index 71a4ca505e09..5ed2cfa7da1d 100644 --- a/drivers/bluetooth/hci_ldisc.c +++ b/drivers/bluetooth/hci_ldisc.c @@ -593,7 +593,7 @@ static void hci_uart_tty_wakeup(struct tty_struct *tty) * Return Value: None */ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, - char *flags, int count) + const char *flags, int count) { struct hci_uart *hu = tty->disc_data; @@ -821,6 +821,7 @@ static __poll_t hci_uart_tty_poll(struct tty_struct *tty, static struct tty_ldisc_ops hci_uart_ldisc = { .owner = THIS_MODULE, + .num = N_HCI, .name = "n_hci", .open = hci_uart_tty_open, .close = hci_uart_tty_close, @@ -840,7 +841,7 @@ static int __init hci_uart_init(void) BT_INFO("HCI UART driver ver %s", VERSION); /* Register the tty discipline */ - err = tty_register_ldisc(N_HCI, &hci_uart_ldisc); + err = tty_register_ldisc(&hci_uart_ldisc); if (err) { BT_ERR("HCI line discipline registration failed. (%d)", err); return err; @@ -882,8 +883,6 @@ static int __init hci_uart_init(void) static void __exit hci_uart_exit(void) { - int err; - #ifdef CONFIG_BT_HCIUART_H4 h4_deinit(); #endif @@ -915,10 +914,7 @@ static void __exit hci_uart_exit(void) mrvl_deinit(); #endif - /* Release tty registration of line discipline */ - err = tty_unregister_ldisc(N_HCI); - if (err) - BT_ERR("Can't unregister HCI line discipline (%d)", err); + tty_unregister_ldisc(&hci_uart_ldisc); } module_init(hci_uart_init); diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index 7355fa2cb439..6551286a60cc 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index e3e2ae41c22b..315e830b6ecd 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -350,7 +350,8 @@ int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, * dprc_scan_container - Scans a physical DPRC and synchronizes Linux bus state * * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object - * + * @alloc_interrupts: if true the function allocates the interrupt pool, + * otherwise the interrupt allocation is delayed * Scans the physical DPRC and synchronizes the state of the Linux * bus driver with the actual state of the MC by adding and removing * devices as appropriate. @@ -373,10 +374,11 @@ int dprc_scan_container(struct fsl_mc_device *mc_bus_dev, return error; } EXPORT_SYMBOL_GPL(dprc_scan_container); + /** * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 * - * @irq: IRQ number of the interrupt being handled + * @irq_num: IRQ number of the interrupt being handled * @arg: Pointer to device structure */ static irqreturn_t dprc_irq0_handler(int irq_num, void *arg) @@ -387,7 +389,7 @@ static irqreturn_t dprc_irq0_handler(int irq_num, void *arg) /** * dprc_irq0_handler_thread - Handler thread function for DPRC interrupt 0 * - * @irq: IRQ number of the interrupt being handled + * @irq_num: IRQ number of the interrupt being handled * @arg: Pointer to device structure */ static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c index 27b0a01bad9b..d129338b8bc0 100644 --- a/drivers/bus/fsl-mc/dprc.c +++ b/drivers/bus/fsl-mc/dprc.c @@ -334,7 +334,7 @@ int dprc_clear_irq_status(struct fsl_mc_io *mc_io, * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPRC object - * @attributes Returned container attributes + * @attr: Returned container attributes * * Return: '0' on Success; Error code otherwise. */ @@ -504,7 +504,7 @@ EXPORT_SYMBOL_GPL(dprc_set_obj_irq); * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPRC object - * @obj_type; Object type as returned in dprc_get_obj() + * @obj_type: Object type as returned in dprc_get_obj() * @obj_id: Unique object instance as returned in dprc_get_obj() * @region_index: The specific region to query * @region_desc: Returns the requested region descriptor diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index 2d7c764bb7dc..6c513556911e 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -254,7 +254,7 @@ EXPORT_SYMBOL_GPL(fsl_mc_resource_free); * @mc_dev: fsl-mc device which is used in conjunction with the * allocated object * @pool_type: pool type - * @new_mc_dev: pointer to area where the pointer to the allocated device + * @new_mc_adev: pointer to area where the pointer to the allocated device * is to be returned * * Allocatable objects are always used in conjunction with some functional @@ -409,7 +409,7 @@ cleanup_msi_irqs: } EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool); -/** +/* * Teardown the interrupt pool associated with an fsl-mc bus. * It frees the IRQs that were allocated to the pool, back to the GIC-ITS. */ @@ -436,7 +436,7 @@ void fsl_mc_cleanup_irq_pool(struct fsl_mc_device *mc_bus_dev) } EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool); -/** +/* * Allocate the IRQs required by a given fsl-mc device. */ int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev) @@ -578,7 +578,7 @@ void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type); } -/** +/* * fsl_mc_allocator_probe - callback invoked when an allocatable device is * being added to the system */ @@ -610,7 +610,7 @@ static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) return 0; } -/** +/* * fsl_mc_allocator_remove - callback invoked when an allocatable device is * being removed from the system */ diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 380ad1fdb745..09c8ab5e0959 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -24,7 +24,7 @@ #include "fsl-mc-private.h" -/** +/* * Default DMA mask for devices on a fsl-mc bus */ #define FSL_MC_DEFAULT_DMA_MASK (~0ULL) @@ -36,6 +36,7 @@ static struct fsl_mc_version mc_version; * @root_mc_bus_dev: fsl-mc device representing the root DPRC * @num_translation_ranges: number of entries in addr_translation_ranges * @translation_ranges: array of bus to system address translation ranges + * @fsl_mc_regs: base address of register bank */ struct fsl_mc { struct fsl_mc_device *root_mc_bus_dev; @@ -117,7 +118,7 @@ out: return found; } -/** +/* * fsl_mc_bus_uevent - callback invoked when a device is added */ static int fsl_mc_bus_uevent(struct device *dev, struct kobj_uevent_env *env) @@ -467,7 +468,7 @@ static void fsl_mc_driver_shutdown(struct device *dev) mc_drv->shutdown(mc_dev); } -/** +/* * __fsl_mc_driver_register - registers a child device driver with the * MC bus * @@ -503,7 +504,7 @@ int __fsl_mc_driver_register(struct fsl_mc_driver *mc_driver, } EXPORT_SYMBOL_GPL(__fsl_mc_driver_register); -/** +/* * fsl_mc_driver_unregister - unregisters a device driver from the * MC bus */ @@ -563,7 +564,7 @@ struct fsl_mc_version *fsl_mc_get_version(void) } EXPORT_SYMBOL_GPL(fsl_mc_get_version); -/** +/* * fsl_mc_get_root_dprc - function to traverse to the root dprc */ void fsl_mc_get_root_dprc(struct device *dev, @@ -732,7 +733,7 @@ error_cleanup_regions: return error; } -/** +/* * fsl_mc_is_root_dprc - function to check if a given device is a root dprc */ bool fsl_mc_is_root_dprc(struct device *dev) @@ -757,7 +758,7 @@ static void fsl_mc_device_release(struct device *dev) kfree(mc_dev); } -/** +/* * Add a newly discovered fsl-mc device to be visible in Linux */ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, @@ -1058,7 +1059,7 @@ static int get_mc_addr_translation_ranges(struct device *dev, return 0; } -/** +/* * fsl_mc_bus_probe - callback invoked when the root MC bus is being * added */ @@ -1182,7 +1183,7 @@ error_cleanup_mc_io: return error; } -/** +/* * fsl_mc_bus_remove - callback invoked when the root MC bus is being * removed */ diff --git a/drivers/bus/fsl-mc/fsl-mc-msi.c b/drivers/bus/fsl-mc/fsl-mc-msi.c index 8edadf05cbb7..cf974870ba55 100644 --- a/drivers/bus/fsl-mc/fsl-mc-msi.c +++ b/drivers/bus/fsl-mc/fsl-mc-msi.c @@ -148,7 +148,7 @@ static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) /** * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain - * @np: Optional device-tree node of the interrupt controller + * @fwnode: Optional firmware node of the interrupt controller * @info: MSI domain info * @parent: Parent irq domain * diff --git a/drivers/bus/fsl-mc/mc-io.c b/drivers/bus/fsl-mc/mc-io.c index 305015486b91..95b10a6cf307 100644 --- a/drivers/bus/fsl-mc/mc-io.c +++ b/drivers/bus/fsl-mc/mc-io.c @@ -50,12 +50,12 @@ static void fsl_mc_io_unset_dpmcp(struct fsl_mc_io *mc_io) } /** - * Creates an MC I/O object + * fsl_create_mc_io() - Creates an MC I/O object * * @dev: device to be associated with the MC I/O object * @mc_portal_phys_addr: physical address of the MC portal to use * @mc_portal_size: size in bytes of the MC portal - * @dpmcp-dev: Pointer to the DPMCP object associated with this MC I/O + * @dpmcp_dev: Pointer to the DPMCP object associated with this MC I/O * object or NULL if none. * @flags: flags for the new MC I/O object * @new_mc_io: Area to return pointer to newly created MC I/O object @@ -123,7 +123,7 @@ error_destroy_mc_io: } /** - * Destroys an MC I/O object + * fsl_destroy_mc_io() - Destroys an MC I/O object * * @mc_io: MC I/O object to destroy */ diff --git a/drivers/bus/fsl-mc/mc-sys.c b/drivers/bus/fsl-mc/mc-sys.c index b291b35e3884..f2052cd0a051 100644 --- a/drivers/bus/fsl-mc/mc-sys.c +++ b/drivers/bus/fsl-mc/mc-sys.c @@ -16,7 +16,7 @@ #include "fsl-mc-private.h" -/** +/* * Timeout in milliseconds to wait for the completion of an MC command */ #define MC_CMD_COMPLETION_TIMEOUT_MS 500 @@ -148,9 +148,10 @@ static inline enum mc_cmd_status mc_read_response(struct fsl_mc_command __iomem } /** - * Waits for the completion of an MC command doing preemptible polling. - * uslepp_range() is called between polling iterations. - * + * mc_polling_wait_preemptible() - Waits for the completion of an MC + * command doing preemptible polling. + * uslepp_range() is called between + * polling iterations. * @mc_io: MC I/O object to be used * @cmd: command buffer to receive MC response * @mc_status: MC command completion status @@ -194,9 +195,9 @@ static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io, } /** - * Waits for the completion of an MC command doing atomic polling. - * udelay() is called between polling iterations. - * + * mc_polling_wait_atomic() - Waits for the completion of an MC command + * doing atomic polling. udelay() is called + * between polling iterations. * @mc_io: MC I/O object to be used * @cmd: command buffer to receive MC response * @mc_status: MC command completion status @@ -234,8 +235,8 @@ static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io, } /** - * Sends a command to the MC device using the given MC I/O object - * + * mc_send_command() - Sends a command to the MC device using the given + * MC I/O object * @mc_io: MC I/O object to be used * @cmd: command to be sent * diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index e2e59a341fef..bbf6cd04861e 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -465,23 +465,15 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl) /* Trigger MHI RESET so that the device will not access host memory */ if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) { - u32 in_reset = -1; - unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms); - dev_dbg(dev, "Triggering MHI Reset in device\n"); mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); /* Wait for the reset bit to be cleared by the device */ - ret = wait_event_timeout(mhi_cntrl->state_event, - mhi_read_reg_field(mhi_cntrl, - mhi_cntrl->regs, - MHICTRL, - MHICTRL_RESET_MASK, - MHICTRL_RESET_SHIFT, - &in_reset) || - !in_reset, timeout); - if (!ret || in_reset) - dev_err(dev, "Device failed to exit MHI Reset state\n"); + ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, + MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0, + 25000); + if (ret) + dev_err(dev, "Device failed to clear MHI Reset\n"); /* * Device will clear BHI_INTVEC as a part of RESET processing, @@ -934,6 +926,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl) ret = wait_event_timeout(mhi_cntrl->state_event, mhi_cntrl->dev_state == MHI_STATE_M0 || + mhi_cntrl->dev_state == MHI_STATE_M2 || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), msecs_to_jiffies(mhi_cntrl->timeout_ms)); diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index b3357a8a2fdb..ca3bc40427f8 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -665,7 +665,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - return err; + goto err_disable_reporting; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -699,6 +699,8 @@ err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); +err_disable_reporting: + pci_disable_pcie_error_reporting(pdev); return err; } @@ -721,6 +723,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) pm_runtime_get_noresume(&pdev->dev); mhi_unregister_controller(mhi_cntrl); + pci_disable_pcie_error_reporting(pdev); } static void mhi_pci_shutdown(struct pci_dev *pdev) diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index b151e0fcdeb5..ea3ead00f30f 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -218,19 +218,6 @@ config XILINX_HWICAP If unsure, say N. -config R3964 - tristate "Siemens R3964 line discipline" - depends on TTY && BROKEN - help - This driver allows synchronous communication with devices using the - Siemens R3964 packet protocol. Unless you are dealing with special - hardware like PLCs, you are unlikely to need this. - - To compile this driver as a module, choose M here: the - module will be called n_r3964. - - If unsure, say N. - config APPLICOM tristate "Applicom intelligent fieldbus card support" depends on PCI @@ -357,27 +344,6 @@ config NVRAM To compile this driver as a module, choose M here: the module will be called nvram. -config RAW_DRIVER - tristate "RAW driver (/dev/raw/rawN)" - depends on BLOCK - help - The raw driver permits block devices to be bound to /dev/raw/rawN. - Once bound, I/O against /dev/raw/rawN uses efficient zero-copy I/O. - See the raw(8) manpage for more details. - - Applications should preferably open the device (eg /dev/hda1) - with the O_DIRECT flag. - -config MAX_RAW_DEVS - int "Maximum number of RAW devices to support (1-65536)" - depends on RAW_DRIVER - range 1 65536 - default "256" - help - The maximum number of RAW devices that are supported. - Default is 256. Increase this number in case you need lots of - raw devices. - config DEVPORT bool "/dev/port character device" depends on ISA || PCI diff --git a/drivers/char/Makefile b/drivers/char/Makefile index ffce287ef415..264eb398fdd4 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o obj-y += misc.o obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o obj-$(CONFIG_VIRTIO_CONSOLE) += virtio_console.o -obj-$(CONFIG_RAW_DRIVER) += raw.o obj-$(CONFIG_MSPEC) += mspec.o obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o obj-$(CONFIG_IBM_BSR) += bsr.o @@ -44,6 +43,6 @@ obj-$(CONFIG_TCG_TPM) += tpm/ obj-$(CONFIG_PS3_FLASH) += ps3flash.o -obj-$(CONFIG_XILLYBUS) += xillybus/ +obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c index 8b55085650ad..4e5431f01450 100644 --- a/drivers/char/hpet.c +++ b/drivers/char/hpet.c @@ -156,12 +156,12 @@ static irqreturn_t hpet_interrupt(int irq, void *data) * This has the effect of treating non-periodic like periodic. */ if ((devp->hd_flags & (HPET_IE | HPET_PERIODIC)) == HPET_IE) { - unsigned long m, t, mc, base, k; + unsigned long t, mc, base, k; struct hpet __iomem *hpet = devp->hd_hpet; struct hpets *hpetp = devp->hd_hpets; t = devp->hd_ireqfreq; - m = read_counter(&devp->hd_timer->hpet_compare); + read_counter(&devp->hd_timer->hpet_compare); mc = read_counter(&hpet->hpet_mc); /* The time for the next interrupt would logically be t + m, * however, if we are very unlucky and the interrupt is delayed diff --git a/drivers/char/hw_random/pseries-rng.c b/drivers/char/hw_random/pseries-rng.c index f4949b689bd5..62bdd5af1339 100644 --- a/drivers/char/hw_random/pseries-rng.c +++ b/drivers/char/hw_random/pseries-rng.c @@ -29,7 +29,7 @@ static int pseries_rng_read(struct hwrng *rng, void *data, size_t max, bool wait return 8; } -/** +/* * pseries_rng_get_desired_dma - Return desired DMA allocate for CMO operations * * This is a required function for a driver to operate in a CMO environment diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index 8a0e97b33cae..e96cb5c4f97a 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/drivers/char/mem.c b/drivers/char/mem.c index 15dc54fa1d47..1c596b5cdb27 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/char/pcmcia/cm4000_cs.c b/drivers/char/pcmcia/cm4000_cs.c index 89681f07bc78..8f1bce0b4fe5 100644 --- a/drivers/char/pcmcia/cm4000_cs.c +++ b/drivers/char/pcmcia/cm4000_cs.c @@ -544,6 +544,10 @@ static int set_protocol(struct cm4000_dev *dev, struct ptsreq *ptsreq) io_read_num_rec_bytes(iobase, &num_bytes_read); if (num_bytes_read >= 4) { DEBUGP(2, dev, "NumRecBytes = %i\n", num_bytes_read); + if (num_bytes_read > 4) { + rc = -EIO; + goto exit_setprotocol; + } break; } usleep_range(10000, 11000); @@ -1050,7 +1054,6 @@ static ssize_t cmm_write(struct file *filp, const char __user *buf, struct cm4000_dev *dev = filp->private_data; unsigned int iobase = dev->p_dev->resource[0]->start; unsigned short s; - unsigned char tmp; unsigned char infolen; unsigned char sendT0; unsigned short nsend; @@ -1148,7 +1151,7 @@ static ssize_t cmm_write(struct file *filp, const char __user *buf, set_cardparameter(dev); /* dummy read, reset flag procedure received */ - tmp = inb(REG_FLAGS1(iobase)); + inb(REG_FLAGS1(iobase)); dev->flags1 = 0x20 /* T_Active */ | (sendT0) diff --git a/drivers/char/pcmcia/cm4040_cs.c b/drivers/char/pcmcia/cm4040_cs.c index d5e43606339c..827711911da4 100644 --- a/drivers/char/pcmcia/cm4040_cs.c +++ b/drivers/char/pcmcia/cm4040_cs.c @@ -221,7 +221,6 @@ static ssize_t cm4040_read(struct file *filp, char __user *buf, unsigned long i; size_t min_bytes_to_read; int rc; - unsigned char uc; DEBUGP(2, dev, "-> cm4040_read(%s,%d)\n", current->comm, current->pid); @@ -308,7 +307,7 @@ static ssize_t cm4040_read(struct file *filp, char __user *buf, return -EIO; } - uc = xinb(iobase + REG_OFFSET_BULK_IN); + xinb(iobase + REG_OFFSET_BULK_IN); DEBUGP(2, dev, "<- cm4040_read (successfully)\n"); return min_bytes_to_read; diff --git a/drivers/char/pcmcia/scr24x_cs.c b/drivers/char/pcmcia/scr24x_cs.c index 47feb39af34c..1bdce08fae3d 100644 --- a/drivers/char/pcmcia/scr24x_cs.c +++ b/drivers/char/pcmcia/scr24x_cs.c @@ -265,7 +265,6 @@ static int scr24x_probe(struct pcmcia_device *link) cdev_init(&dev->c_dev, &scr24x_fops); dev->c_dev.owner = THIS_MODULE; - dev->c_dev.ops = &scr24x_fops; ret = cdev_add(&dev->c_dev, MKDEV(MAJOR(scr24x_devt), dev->devno), 1); if (ret < 0) goto err; diff --git a/drivers/char/pcmcia/synclink_cs.c b/drivers/char/pcmcia/synclink_cs.c index 3287a7627ed0..6eaefea0520e 100644 --- a/drivers/char/pcmcia/synclink_cs.c +++ b/drivers/char/pcmcia/synclink_cs.c @@ -985,7 +985,7 @@ static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty) else #endif { - if (tty && (tty->stopped || tty->hw_stopped)) { + if (tty && (tty->flow.stopped || tty->hw_stopped)) { tx_stop(info); return; } @@ -1005,7 +1005,7 @@ static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty) if (!info->tx_active) return; } else { - if (tty && (tty->stopped || tty->hw_stopped)) { + if (tty && (tty->flow.stopped || tty->hw_stopped)) { tx_stop(info); return; } @@ -1419,13 +1419,7 @@ static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty) /* byte size and parity */ - switch (cflag & CSIZE) { - case CS5: info->params.data_bits = 5; break; - case CS6: info->params.data_bits = 6; break; - case CS7: info->params.data_bits = 7; break; - case CS8: info->params.data_bits = 8; break; - default: info->params.data_bits = 7; break; - } + info->params.data_bits = tty_get_char_size(cflag); if (cflag & CSTOPB) info->params.stop_bits = 2; @@ -1525,7 +1519,7 @@ static void mgslpc_flush_chars(struct tty_struct *tty) if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars")) return; - if (info->tx_count <= 0 || tty->stopped || + if (info->tx_count <= 0 || tty->flow.stopped || tty->hw_stopped || !info->tx_buf) return; @@ -1594,7 +1588,7 @@ static int mgslpc_write(struct tty_struct * tty, ret += c; } start: - if (info->tx_count && !tty->stopped && !tty->hw_stopped) { + if (info->tx_count && !tty->flow.stopped && !tty->hw_stopped) { spin_lock_irqsave(&info->lock, flags); if (!info->tx_active) tx_start(info, tty); @@ -1609,7 +1603,7 @@ cleanup: /* Return the count of free bytes in transmit buffer */ -static int mgslpc_write_room(struct tty_struct *tty) +static unsigned int mgslpc_write_room(struct tty_struct *tty) { MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; int ret; @@ -1637,10 +1631,10 @@ static int mgslpc_write_room(struct tty_struct *tty) /* Return the count of bytes in transmit buffer */ -static int mgslpc_chars_in_buffer(struct tty_struct *tty) +static unsigned int mgslpc_chars_in_buffer(struct tty_struct *tty) { MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; - int rc; + unsigned int rc; if (debug_level >= DEBUG_LEVEL_INFO) printk("%s(%d):mgslpc_chars_in_buffer(%s)\n", @@ -1655,7 +1649,7 @@ static int mgslpc_chars_in_buffer(struct tty_struct *tty) rc = info->tx_count; if (debug_level >= DEBUG_LEVEL_INFO) - printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n", + printk("%s(%d):mgslpc_chars_in_buffer(%s)=%u\n", __FILE__, __LINE__, info->device_name, rc); return rc; diff --git a/drivers/char/raw.c b/drivers/char/raw.c deleted file mode 100644 index 5d52a1f4738c..000000000000 --- a/drivers/char/raw.c +++ /dev/null @@ -1,362 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/drivers/char/raw.c - * - * Front-end raw character devices. These can be bound to any block - * devices to provide genuine Unix raw character device semantics. - * - * We reserve minor number 0 for a control interface. ioctl()s on this - * device are used to bind the other minor numbers to block devices. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -struct raw_device_data { - dev_t binding; - struct block_device *bdev; - int inuse; -}; - -static struct class *raw_class; -static struct raw_device_data *raw_devices; -static DEFINE_MUTEX(raw_mutex); -static const struct file_operations raw_ctl_fops; /* forward declaration */ - -static int max_raw_minors = CONFIG_MAX_RAW_DEVS; - -module_param(max_raw_minors, int, 0); -MODULE_PARM_DESC(max_raw_minors, "Maximum number of raw devices (1-65536)"); - -/* - * Open/close code for raw IO. - * - * We just rewrite the i_mapping for the /dev/raw/rawN file descriptor to - * point at the blockdev's address_space and set the file handle to use - * O_DIRECT. - * - * Set the device's soft blocksize to the minimum possible. This gives the - * finest possible alignment and has no adverse impact on performance. - */ -static int raw_open(struct inode *inode, struct file *filp) -{ - const int minor = iminor(inode); - struct block_device *bdev; - int err; - - if (minor == 0) { /* It is the control device */ - filp->f_op = &raw_ctl_fops; - return 0; - } - - pr_warn_ratelimited( - "process %s (pid %d) is using the deprecated raw device\n" - "support will be removed in Linux 5.14.\n", - current->comm, current->pid); - - mutex_lock(&raw_mutex); - - /* - * All we need to do on open is check that the device is bound. - */ - err = -ENODEV; - if (!raw_devices[minor].binding) - goto out; - bdev = blkdev_get_by_dev(raw_devices[minor].binding, - filp->f_mode | FMODE_EXCL, raw_open); - if (IS_ERR(bdev)) { - err = PTR_ERR(bdev); - goto out; - } - err = set_blocksize(bdev, bdev_logical_block_size(bdev)); - if (err) - goto out1; - filp->f_flags |= O_DIRECT; - filp->f_mapping = bdev->bd_inode->i_mapping; - if (++raw_devices[minor].inuse == 1) - file_inode(filp)->i_mapping = - bdev->bd_inode->i_mapping; - filp->private_data = bdev; - raw_devices[minor].bdev = bdev; - mutex_unlock(&raw_mutex); - return 0; - -out1: - blkdev_put(bdev, filp->f_mode | FMODE_EXCL); -out: - mutex_unlock(&raw_mutex); - return err; -} - -/* - * When the final fd which refers to this character-special node is closed, we - * make its ->mapping point back at its own i_data. - */ -static int raw_release(struct inode *inode, struct file *filp) -{ - const int minor= iminor(inode); - struct block_device *bdev; - - mutex_lock(&raw_mutex); - bdev = raw_devices[minor].bdev; - if (--raw_devices[minor].inuse == 0) - /* Here inode->i_mapping == bdev->bd_inode->i_mapping */ - inode->i_mapping = &inode->i_data; - mutex_unlock(&raw_mutex); - - blkdev_put(bdev, filp->f_mode | FMODE_EXCL); - return 0; -} - -/* - * Forward ioctls to the underlying block device. - */ -static long -raw_ioctl(struct file *filp, unsigned int command, unsigned long arg) -{ - struct block_device *bdev = filp->private_data; - return blkdev_ioctl(bdev, 0, command, arg); -} - -static int bind_set(int number, u64 major, u64 minor) -{ - dev_t dev = MKDEV(major, minor); - dev_t raw = MKDEV(RAW_MAJOR, number); - struct raw_device_data *rawdev; - int err = 0; - - if (number <= 0 || number >= max_raw_minors) - return -EINVAL; - - if (MAJOR(dev) != major || MINOR(dev) != minor) - return -EINVAL; - - rawdev = &raw_devices[number]; - - /* - * This is like making block devices, so demand the - * same capability - */ - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - /* - * For now, we don't need to check that the underlying - * block device is present or not: we can do that when - * the raw device is opened. Just check that the - * major/minor numbers make sense. - */ - - if (MAJOR(dev) == 0 && dev != 0) - return -EINVAL; - - mutex_lock(&raw_mutex); - if (rawdev->inuse) { - mutex_unlock(&raw_mutex); - return -EBUSY; - } - if (rawdev->binding) - module_put(THIS_MODULE); - - rawdev->binding = dev; - if (!dev) { - /* unbind */ - device_destroy(raw_class, raw); - } else { - __module_get(THIS_MODULE); - device_destroy(raw_class, raw); - device_create(raw_class, NULL, raw, NULL, "raw%d", number); - } - mutex_unlock(&raw_mutex); - return err; -} - -static int bind_get(int number, dev_t *dev) -{ - if (number <= 0 || number >= max_raw_minors) - return -EINVAL; - *dev = raw_devices[number].binding; - return 0; -} - -/* - * Deal with ioctls against the raw-device control interface, to bind - * and unbind other raw devices. - */ -static long raw_ctl_ioctl(struct file *filp, unsigned int command, - unsigned long arg) -{ - struct raw_config_request rq; - dev_t dev; - int err; - - switch (command) { - case RAW_SETBIND: - if (copy_from_user(&rq, (void __user *) arg, sizeof(rq))) - return -EFAULT; - - return bind_set(rq.raw_minor, rq.block_major, rq.block_minor); - - case RAW_GETBIND: - if (copy_from_user(&rq, (void __user *) arg, sizeof(rq))) - return -EFAULT; - - err = bind_get(rq.raw_minor, &dev); - if (err) - return err; - - rq.block_major = MAJOR(dev); - rq.block_minor = MINOR(dev); - - if (copy_to_user((void __user *)arg, &rq, sizeof(rq))) - return -EFAULT; - - return 0; - } - - return -EINVAL; -} - -#ifdef CONFIG_COMPAT -struct raw32_config_request { - compat_int_t raw_minor; - compat_u64 block_major; - compat_u64 block_minor; -}; - -static long raw_ctl_compat_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct raw32_config_request __user *user_req = compat_ptr(arg); - struct raw32_config_request rq; - dev_t dev; - int err = 0; - - switch (cmd) { - case RAW_SETBIND: - if (copy_from_user(&rq, user_req, sizeof(rq))) - return -EFAULT; - - return bind_set(rq.raw_minor, rq.block_major, rq.block_minor); - - case RAW_GETBIND: - if (copy_from_user(&rq, user_req, sizeof(rq))) - return -EFAULT; - - err = bind_get(rq.raw_minor, &dev); - if (err) - return err; - - rq.block_major = MAJOR(dev); - rq.block_minor = MINOR(dev); - - if (copy_to_user(user_req, &rq, sizeof(rq))) - return -EFAULT; - - return 0; - } - - return -EINVAL; -} -#endif - -static const struct file_operations raw_fops = { - .read_iter = blkdev_read_iter, - .write_iter = blkdev_write_iter, - .fsync = blkdev_fsync, - .open = raw_open, - .release = raw_release, - .unlocked_ioctl = raw_ioctl, - .llseek = default_llseek, - .owner = THIS_MODULE, -}; - -static const struct file_operations raw_ctl_fops = { - .unlocked_ioctl = raw_ctl_ioctl, -#ifdef CONFIG_COMPAT - .compat_ioctl = raw_ctl_compat_ioctl, -#endif - .open = raw_open, - .owner = THIS_MODULE, - .llseek = noop_llseek, -}; - -static struct cdev raw_cdev; - -static char *raw_devnode(struct device *dev, umode_t *mode) -{ - return kasprintf(GFP_KERNEL, "raw/%s", dev_name(dev)); -} - -static int __init raw_init(void) -{ - dev_t dev = MKDEV(RAW_MAJOR, 0); - int ret; - - if (max_raw_minors < 1 || max_raw_minors > 65536) { - pr_warn("raw: invalid max_raw_minors (must be between 1 and 65536), using %d\n", - CONFIG_MAX_RAW_DEVS); - max_raw_minors = CONFIG_MAX_RAW_DEVS; - } - - raw_devices = vzalloc(array_size(max_raw_minors, - sizeof(struct raw_device_data))); - if (!raw_devices) { - printk(KERN_ERR "Not enough memory for raw device structures\n"); - ret = -ENOMEM; - goto error; - } - - ret = register_chrdev_region(dev, max_raw_minors, "raw"); - if (ret) - goto error; - - cdev_init(&raw_cdev, &raw_fops); - ret = cdev_add(&raw_cdev, dev, max_raw_minors); - if (ret) - goto error_region; - raw_class = class_create(THIS_MODULE, "raw"); - if (IS_ERR(raw_class)) { - printk(KERN_ERR "Error creating raw class.\n"); - cdev_del(&raw_cdev); - ret = PTR_ERR(raw_class); - goto error_region; - } - raw_class->devnode = raw_devnode; - device_create(raw_class, NULL, MKDEV(RAW_MAJOR, 0), NULL, "rawctl"); - - return 0; - -error_region: - unregister_chrdev_region(dev, max_raw_minors); -error: - vfree(raw_devices); - return ret; -} - -static void __exit raw_exit(void) -{ - device_destroy(raw_class, MKDEV(RAW_MAJOR, 0)); - class_destroy(raw_class); - cdev_del(&raw_cdev); - unregister_chrdev_region(MKDEV(RAW_MAJOR, 0), max_raw_minors); -} - -module_init(raw_init); -module_exit(raw_exit); -MODULE_LICENSE("GPL"); diff --git a/drivers/char/ttyprintk.c b/drivers/char/ttyprintk.c index 93f5d11c830b..230b2c9b3e3c 100644 --- a/drivers/char/ttyprintk.c +++ b/drivers/char/ttyprintk.c @@ -52,12 +52,7 @@ static void tpk_flush(void) static int tpk_printk(const unsigned char *buf, int count) { - int i = tpk_curr; - - if (buf == NULL) { - tpk_flush(); - return i; - } + int i; for (i = 0; i < count; i++) { if (tpk_curr >= TPK_STR_SIZE) { @@ -100,12 +95,6 @@ static int tpk_open(struct tty_struct *tty, struct file *filp) static void tpk_close(struct tty_struct *tty, struct file *filp) { struct ttyprintk_port *tpkp = tty->driver_data; - unsigned long flags; - - spin_lock_irqsave(&tpkp->spinlock, flags); - /* flush tpk_printk buffer */ - tpk_printk(NULL, 0); - spin_unlock_irqrestore(&tpkp->spinlock, flags); tty_port_close(&tpkp->port, tty, filp); } @@ -120,7 +109,6 @@ static int tpk_write(struct tty_struct *tty, unsigned long flags; int ret; - /* exclusive use of tpk_printk within this tty */ spin_lock_irqsave(&tpkp->spinlock, flags); ret = tpk_printk(buf, count); @@ -132,32 +120,11 @@ static int tpk_write(struct tty_struct *tty, /* * TTY operations write_room function. */ -static int tpk_write_room(struct tty_struct *tty) +static unsigned int tpk_write_room(struct tty_struct *tty) { return TPK_MAX_ROOM; } -/* - * TTY operations ioctl function. - */ -static int tpk_ioctl(struct tty_struct *tty, - unsigned int cmd, unsigned long arg) -{ - struct ttyprintk_port *tpkp = tty->driver_data; - - if (!tpkp) - return -EINVAL; - - switch (cmd) { - /* Stop TIOCCONS */ - case TIOCCONS: - return -EOPNOTSUPP; - default: - return -ENOIOCTLCMD; - } - return 0; -} - /* * TTY operations hangup function. */ @@ -168,16 +135,31 @@ static void tpk_hangup(struct tty_struct *tty) tty_port_hangup(&tpkp->port); } +/* + * TTY port operations shutdown function. + */ +static void tpk_port_shutdown(struct tty_port *tport) +{ + struct ttyprintk_port *tpkp = + container_of(tport, struct ttyprintk_port, port); + unsigned long flags; + + spin_lock_irqsave(&tpkp->spinlock, flags); + tpk_flush(); + spin_unlock_irqrestore(&tpkp->spinlock, flags); +} + static const struct tty_operations ttyprintk_ops = { .open = tpk_open, .close = tpk_close, .write = tpk_write, .write_room = tpk_write_room, - .ioctl = tpk_ioctl, .hangup = tpk_hangup, }; -static const struct tty_port_operations null_ops = { }; +static const struct tty_port_operations tpk_port_ops = { + .shutdown = tpk_port_shutdown, +}; static struct tty_driver *ttyprintk_driver; @@ -195,7 +177,7 @@ static int __init ttyprintk_init(void) return PTR_ERR(ttyprintk_driver); tty_port_init(&tpk_port.port); - tpk_port.port.ops = &null_ops; + tpk_port.port.ops = &tpk_port_ops; ttyprintk_driver->driver_name = "ttyprintk"; ttyprintk_driver->name = "ttyprintk"; diff --git a/drivers/char/xillybus/Kconfig b/drivers/char/xillybus/Kconfig index 130dbdce858f..a8036dad437e 100644 --- a/drivers/char/xillybus/Kconfig +++ b/drivers/char/xillybus/Kconfig @@ -3,10 +3,14 @@ # Xillybus devices # +config XILLYBUS_CLASS + tristate + config XILLYBUS tristate "Xillybus generic FPGA interface" depends on PCI || OF select CRC32 + select XILLYBUS_CLASS help Xillybus is a generic interface for peripherals designed on programmable logic (FPGA). The driver probes the hardware for @@ -21,7 +25,7 @@ config XILLYBUS_PCIE depends on PCI_MSI help Set to M if you want Xillybus to use PCI Express for communicating - with the FPGA. + with the FPGA. The module will be called xillybus_pcie. config XILLYBUS_OF tristate "Xillybus over Device Tree" @@ -29,6 +33,20 @@ config XILLYBUS_OF help Set to M if you want Xillybus to find its resources from the Open Firmware Flattened Device Tree. If the target is an embedded - system, say M. + system, say M. The module will be called xillybus_of. endif # if XILLYBUS + +# XILLYUSB doesn't depend on XILLYBUS + +config XILLYUSB + tristate "XillyUSB: Xillybus generic FPGA interface for USB" + depends on USB + select CRC32 + select XILLYBUS_CLASS + help + XillyUSB is the Xillybus variant which uses USB for communicating + with the FPGA. + + Set to M if you want Xillybus to use USB for communicating with + the FPGA. The module will be called xillyusb. diff --git a/drivers/char/xillybus/Makefile b/drivers/char/xillybus/Makefile index 099e9a3585fc..16f31d03209d 100644 --- a/drivers/char/xillybus/Makefile +++ b/drivers/char/xillybus/Makefile @@ -3,6 +3,8 @@ # Makefile for Xillybus driver # +obj-$(CONFIG_XILLYBUS_CLASS) += xillybus_class.o obj-$(CONFIG_XILLYBUS) += xillybus_core.o obj-$(CONFIG_XILLYBUS_PCIE) += xillybus_pcie.o obj-$(CONFIG_XILLYBUS_OF) += xillybus_of.o +obj-$(CONFIG_XILLYUSB) += xillyusb.o diff --git a/drivers/char/xillybus/xillybus.h b/drivers/char/xillybus/xillybus.h index 8e3ed4d1bb7f..c63ffc56637c 100644 --- a/drivers/char/xillybus/xillybus.h +++ b/drivers/char/xillybus/xillybus.h @@ -30,7 +30,8 @@ struct xilly_buffer { struct xilly_idt_handle { unsigned char *chandesc; - unsigned char *idt; + unsigned char *names; + int names_len; int entries; }; @@ -94,7 +95,6 @@ struct xilly_endpoint { struct device *dev; struct xilly_endpoint_hardware *ephw; - struct list_head ep_list; int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */ __iomem void *registers; int fatal_error; @@ -102,12 +102,6 @@ struct xilly_endpoint { struct mutex register_mutex; wait_queue_head_t ep_wait; - /* Channels and message handling */ - struct cdev cdev; - - int major; - int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */ - int num_channels; /* EXCLUDING message buffer */ struct xilly_channel **channels; int msg_counter; diff --git a/drivers/char/xillybus/xillybus_class.c b/drivers/char/xillybus/xillybus_class.c new file mode 100644 index 000000000000..5046486011c8 --- /dev/null +++ b/drivers/char/xillybus/xillybus_class.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021 Xillybus Ltd, http://xillybus.com + * + * Driver for the Xillybus class + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xillybus_class.h" + +MODULE_DESCRIPTION("Driver for Xillybus class"); +MODULE_AUTHOR("Eli Billauer, Xillybus Ltd."); +MODULE_ALIAS("xillybus_class"); +MODULE_LICENSE("GPL v2"); + +static DEFINE_MUTEX(unit_mutex); +static LIST_HEAD(unit_list); +static struct class *xillybus_class; + +#define UNITNAMELEN 16 + +struct xilly_unit { + struct list_head list_entry; + void *private_data; + + struct cdev *cdev; + char name[UNITNAMELEN]; + int major; + int lowest_minor; + int num_nodes; +}; + +int xillybus_init_chrdev(struct device *dev, + const struct file_operations *fops, + struct module *owner, + void *private_data, + unsigned char *idt, unsigned int len, + int num_nodes, + const char *prefix, bool enumerate) +{ + int rc; + dev_t mdev; + int i; + char devname[48]; + + struct device *device; + size_t namelen; + struct xilly_unit *unit, *u; + + unit = kzalloc(sizeof(*unit), GFP_KERNEL); + + if (!unit) + return -ENOMEM; + + mutex_lock(&unit_mutex); + + if (!enumerate) + snprintf(unit->name, UNITNAMELEN, "%s", prefix); + + for (i = 0; enumerate; i++) { + snprintf(unit->name, UNITNAMELEN, "%s_%02d", + prefix, i); + + enumerate = false; + list_for_each_entry(u, &unit_list, list_entry) + if (!strcmp(unit->name, u->name)) { + enumerate = true; + break; + } + } + + rc = alloc_chrdev_region(&mdev, 0, num_nodes, unit->name); + + if (rc) { + dev_warn(dev, "Failed to obtain major/minors"); + goto fail_obtain; + } + + unit->major = MAJOR(mdev); + unit->lowest_minor = MINOR(mdev); + unit->num_nodes = num_nodes; + unit->private_data = private_data; + + unit->cdev = cdev_alloc(); + if (!unit->cdev) { + rc = -ENOMEM; + goto unregister_chrdev; + } + unit->cdev->ops = fops; + unit->cdev->owner = owner; + + rc = cdev_add(unit->cdev, MKDEV(unit->major, unit->lowest_minor), + unit->num_nodes); + if (rc) { + dev_err(dev, "Failed to add cdev.\n"); + /* kobject_put() is normally done by cdev_del() */ + kobject_put(&unit->cdev->kobj); + goto unregister_chrdev; + } + + for (i = 0; i < num_nodes; i++) { + namelen = strnlen(idt, len); + + if (namelen == len) { + dev_err(dev, "IDT's list of names is too short. This is exceptionally weird, because its CRC is OK\n"); + rc = -ENODEV; + goto unroll_device_create; + } + + snprintf(devname, sizeof(devname), "%s_%s", + unit->name, idt); + + len -= namelen + 1; + idt += namelen + 1; + + device = device_create(xillybus_class, + NULL, + MKDEV(unit->major, + i + unit->lowest_minor), + NULL, + "%s", devname); + + if (IS_ERR(device)) { + dev_err(dev, "Failed to create %s device. Aborting.\n", + devname); + rc = -ENODEV; + goto unroll_device_create; + } + } + + if (len) { + dev_err(dev, "IDT's list of names is too long. This is exceptionally weird, because its CRC is OK\n"); + rc = -ENODEV; + goto unroll_device_create; + } + + list_add_tail(&unit->list_entry, &unit_list); + + dev_info(dev, "Created %d device files.\n", num_nodes); + + mutex_unlock(&unit_mutex); + + return 0; + +unroll_device_create: + for (i--; i >= 0; i--) + device_destroy(xillybus_class, MKDEV(unit->major, + i + unit->lowest_minor)); + + cdev_del(unit->cdev); + +unregister_chrdev: + unregister_chrdev_region(MKDEV(unit->major, unit->lowest_minor), + unit->num_nodes); + +fail_obtain: + mutex_unlock(&unit_mutex); + + kfree(unit); + + return rc; +} +EXPORT_SYMBOL(xillybus_init_chrdev); + +void xillybus_cleanup_chrdev(void *private_data, + struct device *dev) +{ + int minor; + struct xilly_unit *unit; + bool found = false; + + mutex_lock(&unit_mutex); + + list_for_each_entry(unit, &unit_list, list_entry) + if (unit->private_data == private_data) { + found = true; + break; + } + + if (!found) { + dev_err(dev, "Weird bug: Failed to find unit\n"); + mutex_unlock(&unit_mutex); + return; + } + + for (minor = unit->lowest_minor; + minor < (unit->lowest_minor + unit->num_nodes); + minor++) + device_destroy(xillybus_class, MKDEV(unit->major, minor)); + + cdev_del(unit->cdev); + + unregister_chrdev_region(MKDEV(unit->major, unit->lowest_minor), + unit->num_nodes); + + dev_info(dev, "Removed %d device files.\n", + unit->num_nodes); + + list_del(&unit->list_entry); + kfree(unit); + + mutex_unlock(&unit_mutex); +} +EXPORT_SYMBOL(xillybus_cleanup_chrdev); + +int xillybus_find_inode(struct inode *inode, + void **private_data, int *index) +{ + int minor = iminor(inode); + int major = imajor(inode); + struct xilly_unit *unit; + bool found = false; + + mutex_lock(&unit_mutex); + + list_for_each_entry(unit, &unit_list, list_entry) + if (unit->major == major && + minor >= unit->lowest_minor && + minor < (unit->lowest_minor + unit->num_nodes)) { + found = true; + break; + } + + mutex_unlock(&unit_mutex); + + if (!found) + return -ENODEV; + + *private_data = unit->private_data; + *index = minor - unit->lowest_minor; + + return 0; +} +EXPORT_SYMBOL(xillybus_find_inode); + +static int __init xillybus_class_init(void) +{ + xillybus_class = class_create(THIS_MODULE, "xillybus"); + + if (IS_ERR(xillybus_class)) { + pr_warn("Failed to register xillybus class\n"); + + return PTR_ERR(xillybus_class); + } + return 0; +} + +static void __exit xillybus_class_exit(void) +{ + class_destroy(xillybus_class); +} + +module_init(xillybus_class_init); +module_exit(xillybus_class_exit); diff --git a/drivers/char/xillybus/xillybus_class.h b/drivers/char/xillybus/xillybus_class.h new file mode 100644 index 000000000000..5dbfdfc95c65 --- /dev/null +++ b/drivers/char/xillybus/xillybus_class.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2021 Xillybus Ltd, http://www.xillybus.com + * + * Header file for the Xillybus class + */ + +#ifndef __XILLYBUS_CLASS_H +#define __XILLYBUS_CLASS_H + +#include +#include +#include +#include + +int xillybus_init_chrdev(struct device *dev, + const struct file_operations *fops, + struct module *owner, + void *private_data, + unsigned char *idt, unsigned int len, + int num_nodes, + const char *prefix, bool enumerate); + +void xillybus_cleanup_chrdev(void *private_data, + struct device *dev); + +int xillybus_find_inode(struct inode *inode, + void **private_data, int *index); + +#endif /* __XILLYBUS_CLASS_H */ diff --git a/drivers/char/xillybus/xillybus_core.c b/drivers/char/xillybus/xillybus_core.c index 57fa68834981..931d0bf4cec6 100644 --- a/drivers/char/xillybus/xillybus_core.c +++ b/drivers/char/xillybus/xillybus_core.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -30,10 +29,10 @@ #include #include #include "xillybus.h" +#include "xillybus_class.h" MODULE_DESCRIPTION("Xillybus core functions"); MODULE_AUTHOR("Eli Billauer, Xillybus Ltd."); -MODULE_VERSION("1.07"); MODULE_ALIAS("xillybus_core"); MODULE_LICENSE("GPL v2"); @@ -58,16 +57,6 @@ MODULE_LICENSE("GPL v2"); static const char xillyname[] = "xillybus"; -static struct class *xillybus_class; - -/* - * ep_list_lock is the last lock to be taken; No other lock requests are - * allowed while holding it. It merely protects list_of_endpoints, and not - * the endpoints listed in it. - */ - -static LIST_HEAD(list_of_endpoints); -static struct mutex ep_list_lock; static struct workqueue_struct *xillybus_wq; /* @@ -570,10 +559,8 @@ static int xilly_scan_idt(struct xilly_endpoint *endpoint, unsigned char *scan; int len; - scan = idt; - idt_handle->idt = idt; - - scan++; /* Skip version number */ + scan = idt + 1; + idt_handle->names = scan; while ((scan <= end_of_idt) && *scan) { while ((scan <= end_of_idt) && *scan++) @@ -581,6 +568,8 @@ static int xilly_scan_idt(struct xilly_endpoint *endpoint, count++; } + idt_handle->names_len = scan - idt_handle->names; + scan++; if (scan > end_of_idt) { @@ -1407,36 +1396,20 @@ static ssize_t xillybus_write(struct file *filp, const char __user *userbuf, static int xillybus_open(struct inode *inode, struct file *filp) { - int rc = 0; + int rc; unsigned long flags; - int minor = iminor(inode); - int major = imajor(inode); - struct xilly_endpoint *ep_iter, *endpoint = NULL; + struct xilly_endpoint *endpoint; struct xilly_channel *channel; + int index; - mutex_lock(&ep_list_lock); - - list_for_each_entry(ep_iter, &list_of_endpoints, ep_list) { - if ((ep_iter->major == major) && - (minor >= ep_iter->lowest_minor) && - (minor < (ep_iter->lowest_minor + - ep_iter->num_channels))) { - endpoint = ep_iter; - break; - } - } - mutex_unlock(&ep_list_lock); - - if (!endpoint) { - pr_err("xillybus: open() failed to find a device for major=%d and minor=%d\n", - major, minor); - return -ENODEV; - } + rc = xillybus_find_inode(inode, (void **)&endpoint, &index); + if (rc) + return rc; if (endpoint->fatal_error) return -EIO; - channel = endpoint->channels[1 + minor - endpoint->lowest_minor]; + channel = endpoint->channels[1 + index]; filp->private_data = channel; /* @@ -1799,95 +1772,6 @@ static const struct file_operations xillybus_fops = { .poll = xillybus_poll, }; -static int xillybus_init_chrdev(struct xilly_endpoint *endpoint, - const unsigned char *idt) -{ - int rc; - dev_t dev; - int devnum, i, minor, major; - char devname[48]; - struct device *device; - - rc = alloc_chrdev_region(&dev, 0, /* minor start */ - endpoint->num_channels, - xillyname); - if (rc) { - dev_warn(endpoint->dev, "Failed to obtain major/minors"); - return rc; - } - - endpoint->major = major = MAJOR(dev); - endpoint->lowest_minor = minor = MINOR(dev); - - cdev_init(&endpoint->cdev, &xillybus_fops); - endpoint->cdev.owner = endpoint->ephw->owner; - rc = cdev_add(&endpoint->cdev, MKDEV(major, minor), - endpoint->num_channels); - if (rc) { - dev_warn(endpoint->dev, "Failed to add cdev. Aborting.\n"); - goto unregister_chrdev; - } - - idt++; - - for (i = minor, devnum = 0; - devnum < endpoint->num_channels; - devnum++, i++) { - snprintf(devname, sizeof(devname)-1, "xillybus_%s", idt); - - devname[sizeof(devname)-1] = 0; /* Should never matter */ - - while (*idt++) - /* Skip to next */; - - device = device_create(xillybus_class, - NULL, - MKDEV(major, i), - NULL, - "%s", devname); - - if (IS_ERR(device)) { - dev_warn(endpoint->dev, - "Failed to create %s device. Aborting.\n", - devname); - rc = -ENODEV; - goto unroll_device_create; - } - } - - dev_info(endpoint->dev, "Created %d device files.\n", - endpoint->num_channels); - return 0; /* succeed */ - -unroll_device_create: - devnum--; i--; - for (; devnum >= 0; devnum--, i--) - device_destroy(xillybus_class, MKDEV(major, i)); - - cdev_del(&endpoint->cdev); -unregister_chrdev: - unregister_chrdev_region(MKDEV(major, minor), endpoint->num_channels); - - return rc; -} - -static void xillybus_cleanup_chrdev(struct xilly_endpoint *endpoint) -{ - int minor; - - for (minor = endpoint->lowest_minor; - minor < (endpoint->lowest_minor + endpoint->num_channels); - minor++) - device_destroy(xillybus_class, MKDEV(endpoint->major, minor)); - cdev_del(&endpoint->cdev); - unregister_chrdev_region(MKDEV(endpoint->major, - endpoint->lowest_minor), - endpoint->num_channels); - - dev_info(endpoint->dev, "Removed %d device files.\n", - endpoint->num_channels); -} - struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev, struct device *dev, struct xilly_endpoint_hardware @@ -2027,28 +1911,20 @@ int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint) if (rc) goto failed_idt; - /* - * endpoint is now completely configured. We put it on the list - * available to open() before registering the char device(s) - */ + rc = xillybus_init_chrdev(dev, &xillybus_fops, + endpoint->ephw->owner, endpoint, + idt_handle.names, + idt_handle.names_len, + endpoint->num_channels, + xillyname, false); - mutex_lock(&ep_list_lock); - list_add_tail(&endpoint->ep_list, &list_of_endpoints); - mutex_unlock(&ep_list_lock); - - rc = xillybus_init_chrdev(endpoint, idt_handle.idt); if (rc) - goto failed_chrdevs; + goto failed_idt; devres_release_group(dev, bootstrap_resources); return 0; -failed_chrdevs: - mutex_lock(&ep_list_lock); - list_del(&endpoint->ep_list); - mutex_unlock(&ep_list_lock); - failed_idt: xilly_quiesce(endpoint); flush_workqueue(xillybus_wq); @@ -2059,11 +1935,7 @@ EXPORT_SYMBOL(xillybus_endpoint_discovery); void xillybus_endpoint_remove(struct xilly_endpoint *endpoint) { - xillybus_cleanup_chrdev(endpoint); - - mutex_lock(&ep_list_lock); - list_del(&endpoint->ep_list); - mutex_unlock(&ep_list_lock); + xillybus_cleanup_chrdev(endpoint, endpoint->dev); xilly_quiesce(endpoint); @@ -2077,17 +1949,9 @@ EXPORT_SYMBOL(xillybus_endpoint_remove); static int __init xillybus_init(void) { - mutex_init(&ep_list_lock); - - xillybus_class = class_create(THIS_MODULE, xillyname); - if (IS_ERR(xillybus_class)) - return PTR_ERR(xillybus_class); - xillybus_wq = alloc_workqueue(xillyname, 0, 0); - if (!xillybus_wq) { - class_destroy(xillybus_class); + if (!xillybus_wq) return -ENOMEM; - } return 0; } @@ -2096,8 +1960,6 @@ static void __exit xillybus_exit(void) { /* flush_workqueue() was called for each endpoint released */ destroy_workqueue(xillybus_wq); - - class_destroy(xillybus_class); } module_init(xillybus_init); diff --git a/drivers/char/xillybus/xillybus_of.c b/drivers/char/xillybus/xillybus_of.c index 96b6de8a30e5..1a20b286fd1d 100644 --- a/drivers/char/xillybus/xillybus_of.c +++ b/drivers/char/xillybus/xillybus_of.c @@ -17,7 +17,6 @@ MODULE_DESCRIPTION("Xillybus driver for Open Firmware"); MODULE_AUTHOR("Eli Billauer, Xillybus Ltd."); -MODULE_VERSION("1.06"); MODULE_ALIAS("xillybus_of"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/char/xillybus/xillybus_pcie.c b/drivers/char/xillybus/xillybus_pcie.c index 18b0c392bc93..bdf1c366b4fc 100644 --- a/drivers/char/xillybus/xillybus_pcie.c +++ b/drivers/char/xillybus/xillybus_pcie.c @@ -14,7 +14,6 @@ MODULE_DESCRIPTION("Xillybus driver for PCIe"); MODULE_AUTHOR("Eli Billauer, Xillybus Ltd."); -MODULE_VERSION("1.06"); MODULE_ALIAS("xillybus_pcie"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/char/xillybus/xillyusb.c b/drivers/char/xillybus/xillyusb.c new file mode 100644 index 000000000000..e7f88f35c702 --- /dev/null +++ b/drivers/char/xillybus/xillyusb.c @@ -0,0 +1,2259 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Xillybus Ltd, http://xillybus.com + * + * Driver for the XillyUSB FPGA/host framework. + * + * This driver interfaces with a special IP core in an FPGA, setting up + * a pipe between a hardware FIFO in the programmable logic and a device + * file in the host. The number of such pipes and their attributes are + * set up on the logic. This driver detects these automatically and + * creates the device files accordingly. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xillybus_class.h" + +MODULE_DESCRIPTION("Driver for XillyUSB FPGA IP Core"); +MODULE_AUTHOR("Eli Billauer, Xillybus Ltd."); +MODULE_ALIAS("xillyusb"); +MODULE_LICENSE("GPL v2"); + +#define XILLY_RX_TIMEOUT (10 * HZ / 1000) +#define XILLY_RESPONSE_TIMEOUT (500 * HZ / 1000) + +#define BUF_SIZE_ORDER 4 +#define BUFNUM 8 +#define LOG2_IDT_FIFO_SIZE 16 +#define LOG2_INITIAL_FIFO_BUF_SIZE 16 + +#define MSG_EP_NUM 1 +#define IN_EP_NUM 1 + +static const char xillyname[] = "xillyusb"; + +static unsigned int fifo_buf_order; + +#define USB_VENDOR_ID_XILINX 0x03fd +#define USB_VENDOR_ID_ALTERA 0x09fb + +#define USB_PRODUCT_ID_XILLYUSB 0xebbe + +static const struct usb_device_id xillyusb_table[] = { + { USB_DEVICE(USB_VENDOR_ID_XILINX, USB_PRODUCT_ID_XILLYUSB) }, + { USB_DEVICE(USB_VENDOR_ID_ALTERA, USB_PRODUCT_ID_XILLYUSB) }, + { } +}; + +MODULE_DEVICE_TABLE(usb, xillyusb_table); + +struct xillyusb_dev; + +struct xillyfifo { + unsigned int bufsize; /* In bytes, always a power of 2 */ + unsigned int bufnum; + unsigned int size; /* Lazy: Equals bufsize * bufnum */ + unsigned int buf_order; + + int fill; /* Number of bytes in the FIFO */ + spinlock_t lock; + wait_queue_head_t waitq; + + unsigned int readpos; + unsigned int readbuf; + unsigned int writepos; + unsigned int writebuf; + char **mem; +}; + +struct xillyusb_channel; + +struct xillyusb_endpoint { + struct xillyusb_dev *xdev; + + struct mutex ep_mutex; /* serialize operations on endpoint */ + + struct list_head buffers; + struct list_head filled_buffers; + spinlock_t buffers_lock; /* protect these two lists */ + + unsigned int order; + unsigned int buffer_size; + + unsigned int fill_mask; + + int outstanding_urbs; + + struct usb_anchor anchor; + + struct xillyfifo fifo; + + struct work_struct workitem; + + bool shutting_down; + bool drained; + bool wake_on_drain; + + u8 ep_num; +}; + +struct xillyusb_channel { + struct xillyusb_dev *xdev; + + struct xillyfifo *in_fifo; + struct xillyusb_endpoint *out_ep; + struct mutex lock; /* protect @out_ep, @in_fifo, bit fields below */ + + struct mutex in_mutex; /* serialize fops on FPGA to host stream */ + struct mutex out_mutex; /* serialize fops on host to FPGA stream */ + wait_queue_head_t flushq; + + int chan_idx; + + u32 in_consumed_bytes; + u32 in_current_checkpoint; + u32 out_bytes; + + unsigned int in_log2_element_size; + unsigned int out_log2_element_size; + unsigned int in_log2_fifo_size; + unsigned int out_log2_fifo_size; + + unsigned int read_data_ok; /* EOF not arrived (yet) */ + unsigned int poll_used; + unsigned int flushing; + unsigned int flushed; + unsigned int canceled; + + /* Bit fields protected by @lock except for initialization */ + unsigned readable:1; + unsigned writable:1; + unsigned open_for_read:1; + unsigned open_for_write:1; + unsigned in_synchronous:1; + unsigned out_synchronous:1; + unsigned in_seekable:1; + unsigned out_seekable:1; +}; + +struct xillybuffer { + struct list_head entry; + struct xillyusb_endpoint *ep; + void *buf; + unsigned int len; +}; + +struct xillyusb_dev { + struct xillyusb_channel *channels; + + struct usb_device *udev; + struct device *dev; /* For dev_err() and such */ + struct kref kref; + struct workqueue_struct *workq; + + int error; + spinlock_t error_lock; /* protect @error */ + struct work_struct wakeup_workitem; + + int num_channels; + + struct xillyusb_endpoint *msg_ep; + struct xillyusb_endpoint *in_ep; + + struct mutex msg_mutex; /* serialize opcode transmission */ + int in_bytes_left; + int leftover_chan_num; + unsigned int in_counter; + struct mutex process_in_mutex; /* synchronize wakeup_all() */ +}; + +/* FPGA to host opcodes */ +enum { + OPCODE_DATA = 0, + OPCODE_QUIESCE_ACK = 1, + OPCODE_EOF = 2, + OPCODE_REACHED_CHECKPOINT = 3, + OPCODE_CANCELED_CHECKPOINT = 4, +}; + +/* Host to FPGA opcodes */ +enum { + OPCODE_QUIESCE = 0, + OPCODE_REQ_IDT = 1, + OPCODE_SET_CHECKPOINT = 2, + OPCODE_CLOSE = 3, + OPCODE_SET_PUSH = 4, + OPCODE_UPDATE_PUSH = 5, + OPCODE_CANCEL_CHECKPOINT = 6, + OPCODE_SET_ADDR = 7, +}; + +/* + * fifo_write() and fifo_read() are NOT reentrant (i.e. concurrent multiple + * calls to each on the same FIFO is not allowed) however it's OK to have + * threads calling each of the two functions once on the same FIFO, and + * at the same time. + */ + +static int fifo_write(struct xillyfifo *fifo, + const void *data, unsigned int len, + int (*copier)(void *, const void *, int)) +{ + unsigned int done = 0; + unsigned int todo = len; + unsigned int nmax; + unsigned int writepos = fifo->writepos; + unsigned int writebuf = fifo->writebuf; + unsigned long flags; + int rc; + + nmax = fifo->size - READ_ONCE(fifo->fill); + + while (1) { + unsigned int nrail = fifo->bufsize - writepos; + unsigned int n = min(todo, nmax); + + if (n == 0) { + spin_lock_irqsave(&fifo->lock, flags); + fifo->fill += done; + spin_unlock_irqrestore(&fifo->lock, flags); + + fifo->writepos = writepos; + fifo->writebuf = writebuf; + + return done; + } + + if (n > nrail) + n = nrail; + + rc = (*copier)(fifo->mem[writebuf] + writepos, data + done, n); + + if (rc) + return rc; + + done += n; + todo -= n; + + writepos += n; + nmax -= n; + + if (writepos == fifo->bufsize) { + writepos = 0; + writebuf++; + + if (writebuf == fifo->bufnum) + writebuf = 0; + } + } +} + +static int fifo_read(struct xillyfifo *fifo, + void *data, unsigned int len, + int (*copier)(void *, const void *, int)) +{ + unsigned int done = 0; + unsigned int todo = len; + unsigned int fill; + unsigned int readpos = fifo->readpos; + unsigned int readbuf = fifo->readbuf; + unsigned long flags; + int rc; + + /* + * The spinlock here is necessary, because otherwise fifo->fill + * could have been increased by fifo_write() after writing data + * to the buffer, but this data would potentially not have been + * visible on this thread at the time the updated fifo->fill was. + * That could lead to reading invalid data. + */ + + spin_lock_irqsave(&fifo->lock, flags); + fill = fifo->fill; + spin_unlock_irqrestore(&fifo->lock, flags); + + while (1) { + unsigned int nrail = fifo->bufsize - readpos; + unsigned int n = min(todo, fill); + + if (n == 0) { + spin_lock_irqsave(&fifo->lock, flags); + fifo->fill -= done; + spin_unlock_irqrestore(&fifo->lock, flags); + + fifo->readpos = readpos; + fifo->readbuf = readbuf; + + return done; + } + + if (n > nrail) + n = nrail; + + rc = (*copier)(data + done, fifo->mem[readbuf] + readpos, n); + + if (rc) + return rc; + + done += n; + todo -= n; + + readpos += n; + fill -= n; + + if (readpos == fifo->bufsize) { + readpos = 0; + readbuf++; + + if (readbuf == fifo->bufnum) + readbuf = 0; + } + } +} + +/* + * These three wrapper functions are used as the @copier argument to + * fifo_write() and fifo_read(), so that they can work directly with + * user memory as well. + */ + +static int xilly_copy_from_user(void *dst, const void *src, int n) +{ + if (copy_from_user(dst, (const void __user *)src, n)) + return -EFAULT; + + return 0; +} + +static int xilly_copy_to_user(void *dst, const void *src, int n) +{ + if (copy_to_user((void __user *)dst, src, n)) + return -EFAULT; + + return 0; +} + +static int xilly_memcpy(void *dst, const void *src, int n) +{ + memcpy(dst, src, n); + + return 0; +} + +static int fifo_init(struct xillyfifo *fifo, + unsigned int log2_size) +{ + unsigned int log2_bufnum; + unsigned int buf_order; + int i; + + unsigned int log2_fifo_buf_size; + +retry: + log2_fifo_buf_size = fifo_buf_order + PAGE_SHIFT; + + if (log2_size > log2_fifo_buf_size) { + log2_bufnum = log2_size - log2_fifo_buf_size; + buf_order = fifo_buf_order; + fifo->bufsize = 1 << log2_fifo_buf_size; + } else { + log2_bufnum = 0; + buf_order = (log2_size > PAGE_SHIFT) ? + log2_size - PAGE_SHIFT : 0; + fifo->bufsize = 1 << log2_size; + } + + fifo->bufnum = 1 << log2_bufnum; + fifo->size = fifo->bufnum * fifo->bufsize; + fifo->buf_order = buf_order; + + fifo->mem = kmalloc_array(fifo->bufnum, sizeof(void *), GFP_KERNEL); + + if (!fifo->mem) + return -ENOMEM; + + for (i = 0; i < fifo->bufnum; i++) { + fifo->mem[i] = (void *) + __get_free_pages(GFP_KERNEL, buf_order); + + if (!fifo->mem[i]) + goto memfail; + } + + fifo->fill = 0; + fifo->readpos = 0; + fifo->readbuf = 0; + fifo->writepos = 0; + fifo->writebuf = 0; + spin_lock_init(&fifo->lock); + init_waitqueue_head(&fifo->waitq); + return 0; + +memfail: + for (i--; i >= 0; i--) + free_pages((unsigned long)fifo->mem[i], buf_order); + + kfree(fifo->mem); + fifo->mem = NULL; + + if (fifo_buf_order) { + fifo_buf_order--; + goto retry; + } else { + return -ENOMEM; + } +} + +static void fifo_mem_release(struct xillyfifo *fifo) +{ + int i; + + if (!fifo->mem) + return; + + for (i = 0; i < fifo->bufnum; i++) + free_pages((unsigned long)fifo->mem[i], fifo->buf_order); + + kfree(fifo->mem); +} + +/* + * When endpoint_quiesce() returns, the endpoint has no URBs submitted, + * won't accept any new URB submissions, and its related work item doesn't + * and won't run anymore. + */ + +static void endpoint_quiesce(struct xillyusb_endpoint *ep) +{ + mutex_lock(&ep->ep_mutex); + ep->shutting_down = true; + mutex_unlock(&ep->ep_mutex); + + usb_kill_anchored_urbs(&ep->anchor); + cancel_work_sync(&ep->workitem); +} + +/* + * Note that endpoint_dealloc() also frees fifo memory (if allocated), even + * though endpoint_alloc doesn't allocate that memory. + */ + +static void endpoint_dealloc(struct xillyusb_endpoint *ep) +{ + struct list_head *this, *next; + + fifo_mem_release(&ep->fifo); + + /* Join @filled_buffers with @buffers to free these entries too */ + list_splice(&ep->filled_buffers, &ep->buffers); + + list_for_each_safe(this, next, &ep->buffers) { + struct xillybuffer *xb = + list_entry(this, struct xillybuffer, entry); + + free_pages((unsigned long)xb->buf, ep->order); + kfree(xb); + } + + kfree(ep); +} + +static struct xillyusb_endpoint +*endpoint_alloc(struct xillyusb_dev *xdev, + u8 ep_num, + void (*work)(struct work_struct *), + unsigned int order, + int bufnum) +{ + int i; + + struct xillyusb_endpoint *ep; + + ep = kzalloc(sizeof(*ep), GFP_KERNEL); + + if (!ep) + return NULL; + + INIT_LIST_HEAD(&ep->buffers); + INIT_LIST_HEAD(&ep->filled_buffers); + + spin_lock_init(&ep->buffers_lock); + mutex_init(&ep->ep_mutex); + + init_usb_anchor(&ep->anchor); + INIT_WORK(&ep->workitem, work); + + ep->order = order; + ep->buffer_size = 1 << (PAGE_SHIFT + order); + ep->outstanding_urbs = 0; + ep->drained = true; + ep->wake_on_drain = false; + ep->xdev = xdev; + ep->ep_num = ep_num; + ep->shutting_down = false; + + for (i = 0; i < bufnum; i++) { + struct xillybuffer *xb; + unsigned long addr; + + xb = kzalloc(sizeof(*xb), GFP_KERNEL); + + if (!xb) { + endpoint_dealloc(ep); + return NULL; + } + + addr = __get_free_pages(GFP_KERNEL, order); + + if (!addr) { + kfree(xb); + endpoint_dealloc(ep); + return NULL; + } + + xb->buf = (void *)addr; + xb->ep = ep; + list_add_tail(&xb->entry, &ep->buffers); + } + return ep; +} + +static void cleanup_dev(struct kref *kref) +{ + struct xillyusb_dev *xdev = + container_of(kref, struct xillyusb_dev, kref); + + if (xdev->in_ep) + endpoint_dealloc(xdev->in_ep); + + if (xdev->msg_ep) + endpoint_dealloc(xdev->msg_ep); + + if (xdev->workq) + destroy_workqueue(xdev->workq); + + kfree(xdev->channels); /* Argument may be NULL, and that's fine */ + kfree(xdev); +} + +/* + * @process_in_mutex is taken to ensure that bulk_in_work() won't call + * process_bulk_in() after wakeup_all()'s execution: The latter zeroes all + * @read_data_ok entries, which will make process_bulk_in() report false + * errors if executed. The mechanism relies on that xdev->error is assigned + * a non-zero value by report_io_error() prior to queueing wakeup_all(), + * which prevents bulk_in_work() from calling process_bulk_in(). + * + * The fact that wakeup_all() and bulk_in_work() are queued on the same + * workqueue makes their concurrent execution very unlikely, however the + * kernel's API doesn't seem to ensure this strictly. + */ + +static void wakeup_all(struct work_struct *work) +{ + int i; + struct xillyusb_dev *xdev = container_of(work, struct xillyusb_dev, + wakeup_workitem); + + mutex_lock(&xdev->process_in_mutex); + + for (i = 0; i < xdev->num_channels; i++) { + struct xillyusb_channel *chan = &xdev->channels[i]; + + mutex_lock(&chan->lock); + + if (chan->in_fifo) { + /* + * Fake an EOF: Even if such arrives, it won't be + * processed. + */ + chan->read_data_ok = 0; + wake_up_interruptible(&chan->in_fifo->waitq); + } + + if (chan->out_ep) + wake_up_interruptible(&chan->out_ep->fifo.waitq); + + mutex_unlock(&chan->lock); + + wake_up_interruptible(&chan->flushq); + } + + mutex_unlock(&xdev->process_in_mutex); + + wake_up_interruptible(&xdev->msg_ep->fifo.waitq); + + kref_put(&xdev->kref, cleanup_dev); +} + +static void report_io_error(struct xillyusb_dev *xdev, + int errcode) +{ + unsigned long flags; + bool do_once = false; + + spin_lock_irqsave(&xdev->error_lock, flags); + if (!xdev->error) { + xdev->error = errcode; + do_once = true; + } + spin_unlock_irqrestore(&xdev->error_lock, flags); + + if (do_once) { + kref_get(&xdev->kref); /* xdev is used by work item */ + queue_work(xdev->workq, &xdev->wakeup_workitem); + } +} + +/* + * safely_assign_in_fifo() changes the value of chan->in_fifo and ensures + * the previous pointer is never used after its return. + */ + +static void safely_assign_in_fifo(struct xillyusb_channel *chan, + struct xillyfifo *fifo) +{ + mutex_lock(&chan->lock); + chan->in_fifo = fifo; + mutex_unlock(&chan->lock); + + flush_work(&chan->xdev->in_ep->workitem); +} + +static void bulk_in_completer(struct urb *urb) +{ + struct xillybuffer *xb = urb->context; + struct xillyusb_endpoint *ep = xb->ep; + unsigned long flags; + + if (urb->status) { + if (!(urb->status == -ENOENT || + urb->status == -ECONNRESET || + urb->status == -ESHUTDOWN)) + report_io_error(ep->xdev, -EIO); + + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->buffers); + ep->outstanding_urbs--; + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + return; + } + + xb->len = urb->actual_length; + + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->filled_buffers); + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + if (!ep->shutting_down) + queue_work(ep->xdev->workq, &ep->workitem); +} + +static void bulk_out_completer(struct urb *urb) +{ + struct xillybuffer *xb = urb->context; + struct xillyusb_endpoint *ep = xb->ep; + unsigned long flags; + + if (urb->status && + (!(urb->status == -ENOENT || + urb->status == -ECONNRESET || + urb->status == -ESHUTDOWN))) + report_io_error(ep->xdev, -EIO); + + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->buffers); + ep->outstanding_urbs--; + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + if (!ep->shutting_down) + queue_work(ep->xdev->workq, &ep->workitem); +} + +static void try_queue_bulk_in(struct xillyusb_endpoint *ep) +{ + struct xillyusb_dev *xdev = ep->xdev; + struct xillybuffer *xb; + struct urb *urb; + + int rc; + unsigned long flags; + unsigned int bufsize = ep->buffer_size; + + mutex_lock(&ep->ep_mutex); + + if (ep->shutting_down || xdev->error) + goto done; + + while (1) { + spin_lock_irqsave(&ep->buffers_lock, flags); + + if (list_empty(&ep->buffers)) { + spin_unlock_irqrestore(&ep->buffers_lock, flags); + goto done; + } + + xb = list_first_entry(&ep->buffers, struct xillybuffer, entry); + list_del(&xb->entry); + ep->outstanding_urbs++; + + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + urb = usb_alloc_urb(0, GFP_KERNEL); + if (!urb) { + report_io_error(xdev, -ENOMEM); + goto relist; + } + + usb_fill_bulk_urb(urb, xdev->udev, + usb_rcvbulkpipe(xdev->udev, ep->ep_num), + xb->buf, bufsize, bulk_in_completer, xb); + + usb_anchor_urb(urb, &ep->anchor); + + rc = usb_submit_urb(urb, GFP_KERNEL); + + if (rc) { + report_io_error(xdev, (rc == -ENOMEM) ? -ENOMEM : + -EIO); + goto unanchor; + } + + usb_free_urb(urb); /* This just decrements reference count */ + } + +unanchor: + usb_unanchor_urb(urb); + usb_free_urb(urb); + +relist: + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->buffers); + ep->outstanding_urbs--; + spin_unlock_irqrestore(&ep->buffers_lock, flags); + +done: + mutex_unlock(&ep->ep_mutex); +} + +static void try_queue_bulk_out(struct xillyusb_endpoint *ep) +{ + struct xillyfifo *fifo = &ep->fifo; + struct xillyusb_dev *xdev = ep->xdev; + struct xillybuffer *xb; + struct urb *urb; + + int rc; + unsigned int fill; + unsigned long flags; + bool do_wake = false; + + mutex_lock(&ep->ep_mutex); + + if (ep->shutting_down || xdev->error) + goto done; + + fill = READ_ONCE(fifo->fill) & ep->fill_mask; + + while (1) { + int count; + unsigned int max_read; + + spin_lock_irqsave(&ep->buffers_lock, flags); + + /* + * Race conditions might have the FIFO filled while the + * endpoint is marked as drained here. That doesn't matter, + * because the sole purpose of @drained is to ensure that + * certain data has been sent on the USB channel before + * shutting it down. Hence knowing that the FIFO appears + * to be empty with no outstanding URBs at some moment + * is good enough. + */ + + if (!fill) { + ep->drained = !ep->outstanding_urbs; + if (ep->drained && ep->wake_on_drain) + do_wake = true; + + spin_unlock_irqrestore(&ep->buffers_lock, flags); + goto done; + } + + ep->drained = false; + + if ((fill < ep->buffer_size && ep->outstanding_urbs) || + list_empty(&ep->buffers)) { + spin_unlock_irqrestore(&ep->buffers_lock, flags); + goto done; + } + + xb = list_first_entry(&ep->buffers, struct xillybuffer, entry); + list_del(&xb->entry); + ep->outstanding_urbs++; + + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + max_read = min(fill, ep->buffer_size); + + count = fifo_read(&ep->fifo, xb->buf, max_read, xilly_memcpy); + + /* + * xilly_memcpy always returns 0 => fifo_read can't fail => + * count > 0 + */ + + urb = usb_alloc_urb(0, GFP_KERNEL); + if (!urb) { + report_io_error(xdev, -ENOMEM); + goto relist; + } + + usb_fill_bulk_urb(urb, xdev->udev, + usb_sndbulkpipe(xdev->udev, ep->ep_num), + xb->buf, count, bulk_out_completer, xb); + + usb_anchor_urb(urb, &ep->anchor); + + rc = usb_submit_urb(urb, GFP_KERNEL); + + if (rc) { + report_io_error(xdev, (rc == -ENOMEM) ? -ENOMEM : + -EIO); + goto unanchor; + } + + usb_free_urb(urb); /* This just decrements reference count */ + + fill -= count; + do_wake = true; + } + +unanchor: + usb_unanchor_urb(urb); + usb_free_urb(urb); + +relist: + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->buffers); + ep->outstanding_urbs--; + spin_unlock_irqrestore(&ep->buffers_lock, flags); + +done: + mutex_unlock(&ep->ep_mutex); + + if (do_wake) + wake_up_interruptible(&fifo->waitq); +} + +static void bulk_out_work(struct work_struct *work) +{ + struct xillyusb_endpoint *ep = container_of(work, + struct xillyusb_endpoint, + workitem); + try_queue_bulk_out(ep); +} + +static int process_in_opcode(struct xillyusb_dev *xdev, + int opcode, + int chan_num) +{ + struct xillyusb_channel *chan; + struct device *dev = xdev->dev; + int chan_idx = chan_num >> 1; + + if (chan_idx >= xdev->num_channels) { + dev_err(dev, "Received illegal channel ID %d from FPGA\n", + chan_num); + return -EIO; + } + + chan = &xdev->channels[chan_idx]; + + switch (opcode) { + case OPCODE_EOF: + if (!chan->read_data_ok) { + dev_err(dev, "Received unexpected EOF for channel %d\n", + chan_num); + return -EIO; + } + + /* + * A write memory barrier ensures that the FIFO's fill level + * is visible before read_data_ok turns zero, so the data in + * the FIFO isn't missed by the consumer. + */ + smp_wmb(); + WRITE_ONCE(chan->read_data_ok, 0); + wake_up_interruptible(&chan->in_fifo->waitq); + break; + + case OPCODE_REACHED_CHECKPOINT: + chan->flushing = 0; + wake_up_interruptible(&chan->flushq); + break; + + case OPCODE_CANCELED_CHECKPOINT: + chan->canceled = 1; + wake_up_interruptible(&chan->flushq); + break; + + default: + dev_err(dev, "Received illegal opcode %d from FPGA\n", + opcode); + return -EIO; + } + + return 0; +} + +static int process_bulk_in(struct xillybuffer *xb) +{ + struct xillyusb_endpoint *ep = xb->ep; + struct xillyusb_dev *xdev = ep->xdev; + struct device *dev = xdev->dev; + int dws = xb->len >> 2; + __le32 *p = xb->buf; + u32 ctrlword; + struct xillyusb_channel *chan; + struct xillyfifo *fifo; + int chan_num = 0, opcode; + int chan_idx; + int bytes, count, dwconsume; + int in_bytes_left = 0; + int rc; + + if ((dws << 2) != xb->len) { + dev_err(dev, "Received BULK IN transfer with %d bytes, not a multiple of 4\n", + xb->len); + return -EIO; + } + + if (xdev->in_bytes_left) { + bytes = min(xdev->in_bytes_left, dws << 2); + in_bytes_left = xdev->in_bytes_left - bytes; + chan_num = xdev->leftover_chan_num; + goto resume_leftovers; + } + + while (dws) { + ctrlword = le32_to_cpu(*p++); + dws--; + + chan_num = ctrlword & 0xfff; + count = (ctrlword >> 12) & 0x3ff; + opcode = (ctrlword >> 24) & 0xf; + + if (opcode != OPCODE_DATA) { + unsigned int in_counter = xdev->in_counter++ & 0x3ff; + + if (count != in_counter) { + dev_err(dev, "Expected opcode counter %d, got %d\n", + in_counter, count); + return -EIO; + } + + rc = process_in_opcode(xdev, opcode, chan_num); + + if (rc) + return rc; + + continue; + } + + bytes = min(count + 1, dws << 2); + in_bytes_left = count + 1 - bytes; + +resume_leftovers: + chan_idx = chan_num >> 1; + + if (!(chan_num & 1) || chan_idx >= xdev->num_channels || + !xdev->channels[chan_idx].read_data_ok) { + dev_err(dev, "Received illegal channel ID %d from FPGA\n", + chan_num); + return -EIO; + } + chan = &xdev->channels[chan_idx]; + + fifo = chan->in_fifo; + + if (unlikely(!fifo)) + return -EIO; /* We got really unexpected data */ + + if (bytes != fifo_write(fifo, p, bytes, xilly_memcpy)) { + dev_err(dev, "Misbehaving FPGA overflowed an upstream FIFO!\n"); + return -EIO; + } + + wake_up_interruptible(&fifo->waitq); + + dwconsume = (bytes + 3) >> 2; + dws -= dwconsume; + p += dwconsume; + } + + xdev->in_bytes_left = in_bytes_left; + xdev->leftover_chan_num = chan_num; + return 0; +} + +static void bulk_in_work(struct work_struct *work) +{ + struct xillyusb_endpoint *ep = + container_of(work, struct xillyusb_endpoint, workitem); + struct xillyusb_dev *xdev = ep->xdev; + unsigned long flags; + struct xillybuffer *xb; + bool consumed = false; + int rc = 0; + + mutex_lock(&xdev->process_in_mutex); + + spin_lock_irqsave(&ep->buffers_lock, flags); + + while (1) { + if (rc || list_empty(&ep->filled_buffers)) { + spin_unlock_irqrestore(&ep->buffers_lock, flags); + mutex_unlock(&xdev->process_in_mutex); + + if (rc) + report_io_error(xdev, rc); + else if (consumed) + try_queue_bulk_in(ep); + + return; + } + + xb = list_first_entry(&ep->filled_buffers, struct xillybuffer, + entry); + list_del(&xb->entry); + + spin_unlock_irqrestore(&ep->buffers_lock, flags); + + consumed = true; + + if (!xdev->error) + rc = process_bulk_in(xb); + + spin_lock_irqsave(&ep->buffers_lock, flags); + list_add_tail(&xb->entry, &ep->buffers); + ep->outstanding_urbs--; + } +} + +static int xillyusb_send_opcode(struct xillyusb_dev *xdev, + int chan_num, char opcode, u32 data) +{ + struct xillyusb_endpoint *ep = xdev->msg_ep; + struct xillyfifo *fifo = &ep->fifo; + __le32 msg[2]; + + int rc = 0; + + msg[0] = cpu_to_le32((chan_num & 0xfff) | + ((opcode & 0xf) << 24)); + msg[1] = cpu_to_le32(data); + + mutex_lock(&xdev->msg_mutex); + + /* + * The wait queue is woken with the interruptible variant, so the + * wait function matches, however returning because of an interrupt + * will mess things up considerably, in particular when the caller is + * the release method. And the xdev->error part prevents being stuck + * forever in the event of a bizarre hardware bug: Pull the USB plug. + */ + + while (wait_event_interruptible(fifo->waitq, + fifo->fill <= (fifo->size - 8) || + xdev->error)) + ; /* Empty loop */ + + if (xdev->error) { + rc = xdev->error; + goto unlock_done; + } + + fifo_write(fifo, (void *)msg, 8, xilly_memcpy); + + try_queue_bulk_out(ep); + +unlock_done: + mutex_unlock(&xdev->msg_mutex); + + return rc; +} + +/* + * Note that flush_downstream() merely waits for the data to arrive to + * the application logic at the FPGA -- unlike PCIe Xillybus' counterpart, + * it does nothing to make it happen (and neither is it necessary). + * + * This function is not reentrant for the same @chan, but this is covered + * by the fact that for any given @chan, it's called either by the open, + * write, llseek and flush fops methods, which can't run in parallel (and the + * write + flush and llseek method handlers are protected with out_mutex). + * + * chan->flushed is there to avoid multiple flushes at the same position, + * in particular as a result of programs that close the file descriptor + * e.g. after a dup2() for redirection. + */ + +static int flush_downstream(struct xillyusb_channel *chan, + long timeout, + bool interruptible) +{ + struct xillyusb_dev *xdev = chan->xdev; + int chan_num = chan->chan_idx << 1; + long deadline, left_to_sleep; + int rc; + + if (chan->flushed) + return 0; + + deadline = jiffies + 1 + timeout; + + if (chan->flushing) { + long cancel_deadline = jiffies + 1 + XILLY_RESPONSE_TIMEOUT; + + chan->canceled = 0; + rc = xillyusb_send_opcode(xdev, chan_num, + OPCODE_CANCEL_CHECKPOINT, 0); + + if (rc) + return rc; /* Only real error, never -EINTR */ + + /* Ignoring interrupts. Cancellation must be handled */ + while (!chan->canceled) { + left_to_sleep = cancel_deadline - ((long)jiffies); + + if (left_to_sleep <= 0) { + report_io_error(xdev, -EIO); + return -EIO; + } + + rc = wait_event_interruptible_timeout(chan->flushq, + chan->canceled || + xdev->error, + left_to_sleep); + + if (xdev->error) + return xdev->error; + } + } + + chan->flushing = 1; + + /* + * The checkpoint is given in terms of data elements, not bytes. As + * a result, if less than an element's worth of data is stored in the + * FIFO, it's not flushed, including the flush before closing, which + * means that such data is lost. This is consistent with PCIe Xillybus. + */ + + rc = xillyusb_send_opcode(xdev, chan_num, + OPCODE_SET_CHECKPOINT, + chan->out_bytes >> + chan->out_log2_element_size); + + if (rc) + return rc; /* Only real error, never -EINTR */ + + if (!timeout) { + while (chan->flushing) { + rc = wait_event_interruptible(chan->flushq, + !chan->flushing || + xdev->error); + if (xdev->error) + return xdev->error; + + if (interruptible && rc) + return -EINTR; + } + + goto done; + } + + while (chan->flushing) { + left_to_sleep = deadline - ((long)jiffies); + + if (left_to_sleep <= 0) + return -ETIMEDOUT; + + rc = wait_event_interruptible_timeout(chan->flushq, + !chan->flushing || + xdev->error, + left_to_sleep); + + if (xdev->error) + return xdev->error; + + if (interruptible && rc < 0) + return -EINTR; + } + +done: + chan->flushed = 1; + return 0; +} + +/* request_read_anything(): Ask the FPGA for any little amount of data */ +static int request_read_anything(struct xillyusb_channel *chan, + char opcode) +{ + struct xillyusb_dev *xdev = chan->xdev; + unsigned int sh = chan->in_log2_element_size; + int chan_num = (chan->chan_idx << 1) | 1; + u32 mercy = chan->in_consumed_bytes + (2 << sh) - 1; + + return xillyusb_send_opcode(xdev, chan_num, opcode, mercy >> sh); +} + +static int xillyusb_open(struct inode *inode, struct file *filp) +{ + struct xillyusb_dev *xdev; + struct xillyusb_channel *chan; + struct xillyfifo *in_fifo = NULL; + struct xillyusb_endpoint *out_ep = NULL; + int rc; + int index; + + rc = xillybus_find_inode(inode, (void **)&xdev, &index); + if (rc) + return rc; + + chan = &xdev->channels[index]; + filp->private_data = chan; + + mutex_lock(&chan->lock); + + rc = -ENODEV; + + if (xdev->error) + goto unmutex_fail; + + if (((filp->f_mode & FMODE_READ) && !chan->readable) || + ((filp->f_mode & FMODE_WRITE) && !chan->writable)) + goto unmutex_fail; + + if ((filp->f_flags & O_NONBLOCK) && (filp->f_mode & FMODE_READ) && + chan->in_synchronous) { + dev_err(xdev->dev, + "open() failed: O_NONBLOCK not allowed for read on this device\n"); + goto unmutex_fail; + } + + if ((filp->f_flags & O_NONBLOCK) && (filp->f_mode & FMODE_WRITE) && + chan->out_synchronous) { + dev_err(xdev->dev, + "open() failed: O_NONBLOCK not allowed for write on this device\n"); + goto unmutex_fail; + } + + rc = -EBUSY; + + if (((filp->f_mode & FMODE_READ) && chan->open_for_read) || + ((filp->f_mode & FMODE_WRITE) && chan->open_for_write)) + goto unmutex_fail; + + kref_get(&xdev->kref); + + if (filp->f_mode & FMODE_READ) + chan->open_for_read = 1; + + if (filp->f_mode & FMODE_WRITE) + chan->open_for_write = 1; + + mutex_unlock(&chan->lock); + + if (filp->f_mode & FMODE_WRITE) { + out_ep = endpoint_alloc(xdev, + (chan->chan_idx + 2) | USB_DIR_OUT, + bulk_out_work, BUF_SIZE_ORDER, BUFNUM); + + if (!out_ep) { + rc = -ENOMEM; + goto unopen; + } + + rc = fifo_init(&out_ep->fifo, chan->out_log2_fifo_size); + + if (rc) + goto late_unopen; + + out_ep->fill_mask = -(1 << chan->out_log2_element_size); + chan->out_bytes = 0; + chan->flushed = 0; + + /* + * Sending a flush request to a previously closed stream + * effectively opens it, and also waits until the command is + * confirmed by the FPGA. The latter is necessary because the + * data is sent through a separate BULK OUT endpoint, and the + * xHCI controller is free to reorder transmissions. + * + * This can't go wrong unless there's a serious hardware error + * (or the computer is stuck for 500 ms?) + */ + rc = flush_downstream(chan, XILLY_RESPONSE_TIMEOUT, false); + + if (rc == -ETIMEDOUT) { + rc = -EIO; + report_io_error(xdev, rc); + } + + if (rc) + goto late_unopen; + } + + if (filp->f_mode & FMODE_READ) { + in_fifo = kzalloc(sizeof(*in_fifo), GFP_KERNEL); + + if (!in_fifo) { + rc = -ENOMEM; + goto late_unopen; + } + + rc = fifo_init(in_fifo, chan->in_log2_fifo_size); + + if (rc) { + kfree(in_fifo); + goto late_unopen; + } + } + + mutex_lock(&chan->lock); + if (in_fifo) { + chan->in_fifo = in_fifo; + chan->read_data_ok = 1; + } + if (out_ep) + chan->out_ep = out_ep; + mutex_unlock(&chan->lock); + + if (in_fifo) { + u32 in_checkpoint = 0; + + if (!chan->in_synchronous) + in_checkpoint = in_fifo->size >> + chan->in_log2_element_size; + + chan->in_consumed_bytes = 0; + chan->poll_used = 0; + chan->in_current_checkpoint = in_checkpoint; + rc = xillyusb_send_opcode(xdev, (chan->chan_idx << 1) | 1, + OPCODE_SET_CHECKPOINT, + in_checkpoint); + + if (rc) /* Failure guarantees that opcode wasn't sent */ + goto unfifo; + + /* + * In non-blocking mode, request the FPGA to send any data it + * has right away. Otherwise, the first read() will always + * return -EAGAIN, which is OK strictly speaking, but ugly. + * Checking and unrolling if this fails isn't worth the + * effort -- the error is propagated to the first read() + * anyhow. + */ + if (filp->f_flags & O_NONBLOCK) + request_read_anything(chan, OPCODE_SET_PUSH); + } + + return 0; + +unfifo: + chan->read_data_ok = 0; + safely_assign_in_fifo(chan, NULL); + fifo_mem_release(in_fifo); + kfree(in_fifo); + + if (out_ep) { + mutex_lock(&chan->lock); + chan->out_ep = NULL; + mutex_unlock(&chan->lock); + } + +late_unopen: + if (out_ep) + endpoint_dealloc(out_ep); + +unopen: + mutex_lock(&chan->lock); + + if (filp->f_mode & FMODE_READ) + chan->open_for_read = 0; + + if (filp->f_mode & FMODE_WRITE) + chan->open_for_write = 0; + + mutex_unlock(&chan->lock); + + kref_put(&xdev->kref, cleanup_dev); + + return rc; + +unmutex_fail: + mutex_unlock(&chan->lock); + return rc; +} + +static ssize_t xillyusb_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *f_pos) +{ + struct xillyusb_channel *chan = filp->private_data; + struct xillyusb_dev *xdev = chan->xdev; + struct xillyfifo *fifo = chan->in_fifo; + int chan_num = (chan->chan_idx << 1) | 1; + + long deadline, left_to_sleep; + int bytes_done = 0; + bool sent_set_push = false; + int rc; + + deadline = jiffies + 1 + XILLY_RX_TIMEOUT; + + rc = mutex_lock_interruptible(&chan->in_mutex); + + if (rc) + return rc; + + while (1) { + u32 fifo_checkpoint_bytes, complete_checkpoint_bytes; + u32 complete_checkpoint, fifo_checkpoint; + u32 checkpoint; + s32 diff, leap; + unsigned int sh = chan->in_log2_element_size; + bool checkpoint_for_complete; + + rc = fifo_read(fifo, (__force void *)userbuf + bytes_done, + count - bytes_done, xilly_copy_to_user); + + if (rc < 0) + break; + + bytes_done += rc; + chan->in_consumed_bytes += rc; + + left_to_sleep = deadline - ((long)jiffies); + + /* + * Some 32-bit arithmetic that may wrap. Note that + * complete_checkpoint is rounded up to the closest element + * boundary, because the read() can't be completed otherwise. + * fifo_checkpoint_bytes is rounded down, because it protects + * in_fifo from overflowing. + */ + + fifo_checkpoint_bytes = chan->in_consumed_bytes + fifo->size; + complete_checkpoint_bytes = + chan->in_consumed_bytes + count - bytes_done; + + fifo_checkpoint = fifo_checkpoint_bytes >> sh; + complete_checkpoint = + (complete_checkpoint_bytes + (1 << sh) - 1) >> sh; + + diff = (fifo_checkpoint - complete_checkpoint) << sh; + + if (chan->in_synchronous && diff >= 0) { + checkpoint = complete_checkpoint; + checkpoint_for_complete = true; + } else { + checkpoint = fifo_checkpoint; + checkpoint_for_complete = false; + } + + leap = (checkpoint - chan->in_current_checkpoint) << sh; + + /* + * To prevent flooding of OPCODE_SET_CHECKPOINT commands as + * data is consumed, it's issued only if it moves the + * checkpoint by at least an 8th of the FIFO's size, or if + * it's necessary to complete the number of bytes requested by + * the read() call. + * + * chan->read_data_ok is checked to spare an unnecessary + * submission after receiving EOF, however it's harmless if + * such slips away. + */ + + if (chan->read_data_ok && + (leap > (fifo->size >> 3) || + (checkpoint_for_complete && leap > 0))) { + chan->in_current_checkpoint = checkpoint; + rc = xillyusb_send_opcode(xdev, chan_num, + OPCODE_SET_CHECKPOINT, + checkpoint); + + if (rc) + break; + } + + if (bytes_done == count || + (left_to_sleep <= 0 && bytes_done)) + break; + + /* + * Reaching here means that the FIFO was empty when + * fifo_read() returned, but not necessarily right now. Error + * and EOF are checked and reported only now, so that no data + * that managed its way to the FIFO is lost. + */ + + if (!READ_ONCE(chan->read_data_ok)) { /* FPGA has sent EOF */ + /* Has data slipped into the FIFO since fifo_read()? */ + smp_rmb(); + if (READ_ONCE(fifo->fill)) + continue; + + rc = 0; + break; + } + + if (xdev->error) { + rc = xdev->error; + break; + } + + if (filp->f_flags & O_NONBLOCK) { + rc = -EAGAIN; + break; + } + + if (!sent_set_push) { + rc = xillyusb_send_opcode(xdev, chan_num, + OPCODE_SET_PUSH, + complete_checkpoint); + + if (rc) + break; + + sent_set_push = true; + } + + if (left_to_sleep > 0) { + /* + * Note that when xdev->error is set (e.g. when the + * device is unplugged), read_data_ok turns zero and + * fifo->waitq is awaken. + * Therefore no special attention to xdev->error. + */ + + rc = wait_event_interruptible_timeout + (fifo->waitq, + fifo->fill || !chan->read_data_ok, + left_to_sleep); + } else { /* bytes_done == 0 */ + /* Tell FPGA to send anything it has */ + rc = request_read_anything(chan, OPCODE_UPDATE_PUSH); + + if (rc) + break; + + rc = wait_event_interruptible + (fifo->waitq, + fifo->fill || !chan->read_data_ok); + } + + if (rc < 0) { + rc = -EINTR; + break; + } + } + + if (((filp->f_flags & O_NONBLOCK) || chan->poll_used) && + !READ_ONCE(fifo->fill)) + request_read_anything(chan, OPCODE_SET_PUSH); + + mutex_unlock(&chan->in_mutex); + + if (bytes_done) + return bytes_done; + + return rc; +} + +static int xillyusb_flush(struct file *filp, fl_owner_t id) +{ + struct xillyusb_channel *chan = filp->private_data; + int rc; + + if (!(filp->f_mode & FMODE_WRITE)) + return 0; + + rc = mutex_lock_interruptible(&chan->out_mutex); + + if (rc) + return rc; + + /* + * One second's timeout on flushing. Interrupts are ignored, because if + * the user pressed CTRL-C, that interrupt will still be in flight by + * the time we reach here, and the opportunity to flush is lost. + */ + rc = flush_downstream(chan, HZ, false); + + mutex_unlock(&chan->out_mutex); + + if (rc == -ETIMEDOUT) { + /* The things you do to use dev_warn() and not pr_warn() */ + struct xillyusb_dev *xdev = chan->xdev; + + mutex_lock(&chan->lock); + if (!xdev->error) + dev_warn(xdev->dev, + "Timed out while flushing. Output data may be lost.\n"); + mutex_unlock(&chan->lock); + } + + return rc; +} + +static ssize_t xillyusb_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *f_pos) +{ + struct xillyusb_channel *chan = filp->private_data; + struct xillyusb_dev *xdev = chan->xdev; + struct xillyfifo *fifo = &chan->out_ep->fifo; + int rc; + + rc = mutex_lock_interruptible(&chan->out_mutex); + + if (rc) + return rc; + + while (1) { + if (xdev->error) { + rc = xdev->error; + break; + } + + if (count == 0) + break; + + rc = fifo_write(fifo, (__force void *)userbuf, count, + xilly_copy_from_user); + + if (rc != 0) + break; + + if (filp->f_flags & O_NONBLOCK) { + rc = -EAGAIN; + break; + } + + if (wait_event_interruptible + (fifo->waitq, + fifo->fill != fifo->size || xdev->error)) { + rc = -EINTR; + break; + } + } + + if (rc < 0) + goto done; + + chan->out_bytes += rc; + + if (rc) { + try_queue_bulk_out(chan->out_ep); + chan->flushed = 0; + } + + if (chan->out_synchronous) { + int flush_rc = flush_downstream(chan, 0, true); + + if (flush_rc && !rc) + rc = flush_rc; + } + +done: + mutex_unlock(&chan->out_mutex); + + return rc; +} + +static int xillyusb_release(struct inode *inode, struct file *filp) +{ + struct xillyusb_channel *chan = filp->private_data; + struct xillyusb_dev *xdev = chan->xdev; + int rc_read = 0, rc_write = 0; + + if (filp->f_mode & FMODE_READ) { + struct xillyfifo *in_fifo = chan->in_fifo; + + rc_read = xillyusb_send_opcode(xdev, (chan->chan_idx << 1) | 1, + OPCODE_CLOSE, 0); + /* + * If rc_read is nonzero, xdev->error indicates a global + * device error. The error is reported later, so that + * resources are freed. + * + * Looping on wait_event_interruptible() kinda breaks the idea + * of being interruptible, and this should have been + * wait_event(). Only it's being waken with + * wake_up_interruptible() for the sake of other uses. If + * there's a global device error, chan->read_data_ok is + * deasserted and the wait queue is awaken, so this is covered. + */ + + while (wait_event_interruptible(in_fifo->waitq, + !chan->read_data_ok)) + ; /* Empty loop */ + + safely_assign_in_fifo(chan, NULL); + fifo_mem_release(in_fifo); + kfree(in_fifo); + + mutex_lock(&chan->lock); + chan->open_for_read = 0; + mutex_unlock(&chan->lock); + } + + if (filp->f_mode & FMODE_WRITE) { + struct xillyusb_endpoint *ep = chan->out_ep; + /* + * chan->flushing isn't zeroed. If the pre-release flush timed + * out, a cancel request will be sent before the next + * OPCODE_SET_CHECKPOINT (i.e. when the file is opened again). + * This is despite that the FPGA forgets about the checkpoint + * request as the file closes. Still, in an exceptional race + * condition, the FPGA could send an OPCODE_REACHED_CHECKPOINT + * just before closing that would reach the host after the + * file has re-opened. + */ + + mutex_lock(&chan->lock); + chan->out_ep = NULL; + mutex_unlock(&chan->lock); + + endpoint_quiesce(ep); + endpoint_dealloc(ep); + + /* See comments on rc_read above */ + rc_write = xillyusb_send_opcode(xdev, chan->chan_idx << 1, + OPCODE_CLOSE, 0); + + mutex_lock(&chan->lock); + chan->open_for_write = 0; + mutex_unlock(&chan->lock); + } + + kref_put(&xdev->kref, cleanup_dev); + + return rc_read ? rc_read : rc_write; +} + +/* + * Xillybus' API allows device nodes to be seekable, giving the user + * application access to a RAM array on the FPGA (or logic emulating it). + */ + +static loff_t xillyusb_llseek(struct file *filp, loff_t offset, int whence) +{ + struct xillyusb_channel *chan = filp->private_data; + struct xillyusb_dev *xdev = chan->xdev; + loff_t pos = filp->f_pos; + int rc = 0; + unsigned int log2_element_size = chan->readable ? + chan->in_log2_element_size : chan->out_log2_element_size; + + /* + * Take both mutexes not allowing interrupts, since it seems like + * common applications don't expect an -EINTR here. Besides, multiple + * access to a single file descriptor on seekable devices is a mess + * anyhow. + */ + + mutex_lock(&chan->out_mutex); + mutex_lock(&chan->in_mutex); + + switch (whence) { + case SEEK_SET: + pos = offset; + break; + case SEEK_CUR: + pos += offset; + break; + case SEEK_END: + pos = offset; /* Going to the end => to the beginning */ + break; + default: + rc = -EINVAL; + goto end; + } + + /* In any case, we must finish on an element boundary */ + if (pos & ((1 << log2_element_size) - 1)) { + rc = -EINVAL; + goto end; + } + + rc = xillyusb_send_opcode(xdev, chan->chan_idx << 1, + OPCODE_SET_ADDR, + pos >> log2_element_size); + + if (rc) + goto end; + + if (chan->writable) { + chan->flushed = 0; + rc = flush_downstream(chan, HZ, false); + } + +end: + mutex_unlock(&chan->out_mutex); + mutex_unlock(&chan->in_mutex); + + if (rc) /* Return error after releasing mutexes */ + return rc; + + filp->f_pos = pos; + + return pos; +} + +static __poll_t xillyusb_poll(struct file *filp, poll_table *wait) +{ + struct xillyusb_channel *chan = filp->private_data; + __poll_t mask = 0; + + if (chan->in_fifo) + poll_wait(filp, &chan->in_fifo->waitq, wait); + + if (chan->out_ep) + poll_wait(filp, &chan->out_ep->fifo.waitq, wait); + + /* + * If this is the first time poll() is called, and the file is + * readable, set the relevant flag. Also tell the FPGA to send all it + * has, to kickstart the mechanism that ensures there's always some + * data in in_fifo unless the stream is dry end-to-end. Note that the + * first poll() may not return a EPOLLIN, even if there's data on the + * FPGA. Rather, the data will arrive soon, and trigger the relevant + * wait queue. + */ + + if (!chan->poll_used && chan->in_fifo) { + chan->poll_used = 1; + request_read_anything(chan, OPCODE_SET_PUSH); + } + + /* + * poll() won't play ball regarding read() channels which + * are synchronous. Allowing that will create situations where data has + * been delivered at the FPGA, and users expecting select() to wake up, + * which it may not. So make it never work. + */ + + if (chan->in_fifo && !chan->in_synchronous && + (READ_ONCE(chan->in_fifo->fill) || !chan->read_data_ok)) + mask |= EPOLLIN | EPOLLRDNORM; + + if (chan->out_ep && + (READ_ONCE(chan->out_ep->fifo.fill) != chan->out_ep->fifo.size)) + mask |= EPOLLOUT | EPOLLWRNORM; + + if (chan->xdev->error) + mask |= EPOLLERR; + + return mask; +} + +static const struct file_operations xillyusb_fops = { + .owner = THIS_MODULE, + .read = xillyusb_read, + .write = xillyusb_write, + .open = xillyusb_open, + .flush = xillyusb_flush, + .release = xillyusb_release, + .llseek = xillyusb_llseek, + .poll = xillyusb_poll, +}; + +static int xillyusb_setup_base_eps(struct xillyusb_dev *xdev) +{ + xdev->msg_ep = endpoint_alloc(xdev, MSG_EP_NUM | USB_DIR_OUT, + bulk_out_work, 1, 2); + if (!xdev->msg_ep) + return -ENOMEM; + + if (fifo_init(&xdev->msg_ep->fifo, 13)) /* 8 kiB */ + goto dealloc; + + xdev->msg_ep->fill_mask = -8; /* 8 bytes granularity */ + + xdev->in_ep = endpoint_alloc(xdev, IN_EP_NUM | USB_DIR_IN, + bulk_in_work, BUF_SIZE_ORDER, BUFNUM); + if (!xdev->in_ep) + goto dealloc; + + try_queue_bulk_in(xdev->in_ep); + + return 0; + +dealloc: + endpoint_dealloc(xdev->msg_ep); /* Also frees FIFO mem if allocated */ + return -ENOMEM; +} + +static int setup_channels(struct xillyusb_dev *xdev, + __le16 *chandesc, + int num_channels) +{ + struct xillyusb_channel *chan; + int i; + + chan = kcalloc(num_channels, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + xdev->channels = chan; + + for (i = 0; i < num_channels; i++, chan++) { + unsigned int in_desc = le16_to_cpu(*chandesc++); + unsigned int out_desc = le16_to_cpu(*chandesc++); + + chan->xdev = xdev; + mutex_init(&chan->in_mutex); + mutex_init(&chan->out_mutex); + mutex_init(&chan->lock); + init_waitqueue_head(&chan->flushq); + + chan->chan_idx = i; + + if (in_desc & 0x80) { /* Entry is valid */ + chan->readable = 1; + chan->in_synchronous = !!(in_desc & 0x40); + chan->in_seekable = !!(in_desc & 0x20); + chan->in_log2_element_size = in_desc & 0x0f; + chan->in_log2_fifo_size = ((in_desc >> 8) & 0x1f) + 16; + } + + /* + * A downstream channel should never exist above index 13, + * as it would request a nonexistent BULK endpoint > 15. + * In the peculiar case that it does, it's ignored silently. + */ + + if ((out_desc & 0x80) && i < 14) { /* Entry is valid */ + chan->writable = 1; + chan->out_synchronous = !!(out_desc & 0x40); + chan->out_seekable = !!(out_desc & 0x20); + chan->out_log2_element_size = out_desc & 0x0f; + chan->out_log2_fifo_size = + ((out_desc >> 8) & 0x1f) + 16; + } + } + + return 0; +} + +static int xillyusb_discovery(struct usb_interface *interface) +{ + int rc; + struct xillyusb_dev *xdev = usb_get_intfdata(interface); + __le16 bogus_chandesc[2]; + struct xillyfifo idt_fifo; + struct xillyusb_channel *chan; + unsigned int idt_len, names_offset; + unsigned char *idt; + int num_channels; + + rc = xillyusb_send_opcode(xdev, ~0, OPCODE_QUIESCE, 0); + + if (rc) { + dev_err(&interface->dev, "Failed to send quiesce request. Aborting.\n"); + return rc; + } + + /* Phase I: Set up one fake upstream channel and obtain IDT */ + + /* Set up a fake IDT with one async IN stream */ + bogus_chandesc[0] = cpu_to_le16(0x80); + bogus_chandesc[1] = cpu_to_le16(0); + + rc = setup_channels(xdev, bogus_chandesc, 1); + + if (rc) + return rc; + + rc = fifo_init(&idt_fifo, LOG2_IDT_FIFO_SIZE); + + if (rc) + return rc; + + chan = xdev->channels; + + chan->in_fifo = &idt_fifo; + chan->read_data_ok = 1; + + xdev->num_channels = 1; + + rc = xillyusb_send_opcode(xdev, ~0, OPCODE_REQ_IDT, 0); + + if (rc) { + dev_err(&interface->dev, "Failed to send IDT request. Aborting.\n"); + goto unfifo; + } + + rc = wait_event_interruptible_timeout(idt_fifo.waitq, + !chan->read_data_ok, + XILLY_RESPONSE_TIMEOUT); + + if (xdev->error) { + rc = xdev->error; + goto unfifo; + } + + if (rc < 0) { + rc = -EINTR; /* Interrupt on probe method? Interesting. */ + goto unfifo; + } + + if (chan->read_data_ok) { + rc = -ETIMEDOUT; + dev_err(&interface->dev, "No response from FPGA. Aborting.\n"); + goto unfifo; + } + + idt_len = READ_ONCE(idt_fifo.fill); + idt = kmalloc(idt_len, GFP_KERNEL); + + if (!idt) { + rc = -ENOMEM; + goto unfifo; + } + + fifo_read(&idt_fifo, idt, idt_len, xilly_memcpy); + + if (crc32_le(~0, idt, idt_len) != 0) { + dev_err(&interface->dev, "IDT failed CRC check. Aborting.\n"); + rc = -ENODEV; + goto unidt; + } + + if (*idt > 0x90) { + dev_err(&interface->dev, "No support for IDT version 0x%02x. Maybe the xillyusb driver needs an upgrade. Aborting.\n", + (int)*idt); + rc = -ENODEV; + goto unidt; + } + + /* Phase II: Set up the streams as defined in IDT */ + + num_channels = le16_to_cpu(*((__le16 *)(idt + 1))); + names_offset = 3 + num_channels * 4; + idt_len -= 4; /* Exclude CRC */ + + if (idt_len < names_offset) { + dev_err(&interface->dev, "IDT too short. This is exceptionally weird, because its CRC is OK\n"); + rc = -ENODEV; + goto unidt; + } + + rc = setup_channels(xdev, (void *)idt + 3, num_channels); + + if (rc) + goto unidt; + + /* + * Except for wildly misbehaving hardware, or if it was disconnected + * just after responding with the IDT, there is no reason for any + * work item to be running now. To be sure that xdev->channels + * is updated on anything that might run in parallel, flush the + * workqueue, which rarely does anything. + */ + flush_workqueue(xdev->workq); + + xdev->num_channels = num_channels; + + fifo_mem_release(&idt_fifo); + kfree(chan); + + rc = xillybus_init_chrdev(&interface->dev, &xillyusb_fops, + THIS_MODULE, xdev, + idt + names_offset, + idt_len - names_offset, + num_channels, + xillyname, true); + + kfree(idt); + + return rc; + +unidt: + kfree(idt); + +unfifo: + safely_assign_in_fifo(chan, NULL); + fifo_mem_release(&idt_fifo); + + return rc; +} + +static int xillyusb_probe(struct usb_interface *interface, + const struct usb_device_id *id) +{ + struct xillyusb_dev *xdev; + int rc; + + xdev = kzalloc(sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return -ENOMEM; + + kref_init(&xdev->kref); + mutex_init(&xdev->process_in_mutex); + mutex_init(&xdev->msg_mutex); + + xdev->udev = usb_get_dev(interface_to_usbdev(interface)); + xdev->dev = &interface->dev; + xdev->error = 0; + spin_lock_init(&xdev->error_lock); + xdev->in_counter = 0; + xdev->in_bytes_left = 0; + xdev->workq = alloc_workqueue(xillyname, WQ_HIGHPRI, 0); + + if (!xdev->workq) { + dev_err(&interface->dev, "Failed to allocate work queue\n"); + rc = -ENOMEM; + goto fail; + } + + INIT_WORK(&xdev->wakeup_workitem, wakeup_all); + + usb_set_intfdata(interface, xdev); + + rc = xillyusb_setup_base_eps(xdev); + if (rc) + goto fail; + + rc = xillyusb_discovery(interface); + if (rc) + goto latefail; + + return 0; + +latefail: + endpoint_quiesce(xdev->in_ep); + endpoint_quiesce(xdev->msg_ep); + +fail: + usb_set_intfdata(interface, NULL); + kref_put(&xdev->kref, cleanup_dev); + return rc; +} + +static void xillyusb_disconnect(struct usb_interface *interface) +{ + struct xillyusb_dev *xdev = usb_get_intfdata(interface); + struct xillyusb_endpoint *msg_ep = xdev->msg_ep; + struct xillyfifo *fifo = &msg_ep->fifo; + int rc; + int i; + + xillybus_cleanup_chrdev(xdev, &interface->dev); + + /* + * Try to send OPCODE_QUIESCE, which will fail silently if the device + * was disconnected, but makes sense on module unload. + */ + + msg_ep->wake_on_drain = true; + xillyusb_send_opcode(xdev, ~0, OPCODE_QUIESCE, 0); + + /* + * If the device has been disconnected, sending the opcode causes + * a global device error with xdev->error, if such error didn't + * occur earlier. Hence timing out means that the USB link is fine, + * but somehow the message wasn't sent. Should never happen. + */ + + rc = wait_event_interruptible_timeout(fifo->waitq, + msg_ep->drained || xdev->error, + XILLY_RESPONSE_TIMEOUT); + + if (!rc) + dev_err(&interface->dev, + "Weird timeout condition on sending quiesce request.\n"); + + report_io_error(xdev, -ENODEV); /* Discourage further activity */ + + /* + * This device driver is declared with soft_unbind set, or else + * sending OPCODE_QUIESCE above would always fail. The price is + * that the USB framework didn't kill outstanding URBs, so it has + * to be done explicitly before returning from this call. + */ + + for (i = 0; i < xdev->num_channels; i++) { + struct xillyusb_channel *chan = &xdev->channels[i]; + + /* + * Lock taken to prevent chan->out_ep from changing. It also + * ensures xillyusb_open() and xillyusb_flush() don't access + * xdev->dev after being nullified below. + */ + mutex_lock(&chan->lock); + if (chan->out_ep) + endpoint_quiesce(chan->out_ep); + mutex_unlock(&chan->lock); + } + + endpoint_quiesce(xdev->in_ep); + endpoint_quiesce(xdev->msg_ep); + + usb_set_intfdata(interface, NULL); + + xdev->dev = NULL; + + kref_put(&xdev->kref, cleanup_dev); +} + +static struct usb_driver xillyusb_driver = { + .name = xillyname, + .id_table = xillyusb_table, + .probe = xillyusb_probe, + .disconnect = xillyusb_disconnect, + .soft_unbind = 1, +}; + +static int __init xillyusb_init(void) +{ + int rc = 0; + + if (LOG2_INITIAL_FIFO_BUF_SIZE > PAGE_SHIFT) + fifo_buf_order = LOG2_INITIAL_FIFO_BUF_SIZE - PAGE_SHIFT; + else + fifo_buf_order = 0; + + rc = usb_register(&xillyusb_driver); + + return rc; +} + +static void __exit xillyusb_exit(void) +{ + usb_deregister(&xillyusb_driver); +} + +module_init(xillyusb_init); +module_exit(xillyusb_exit); diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index e80918be8e9c..e873f9ea2e65 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -6,10 +6,6 @@ config HAVE_CLK The calls support software clock gating and thus are a key power management tool on many systems. -config CLKDEV_LOOKUP - bool - select HAVE_CLK - config HAVE_CLK_PREPARE bool @@ -26,7 +22,7 @@ menuconfig COMMON_CLK bool "Common Clock Framework" depends on !HAVE_LEGACY_CLK select HAVE_CLK_PREPARE - select CLKDEV_LOOKUP + select HAVE_CLK select SRCU select RATIONAL help @@ -55,6 +51,14 @@ config CLK_HSDK This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs control. +config LMK04832 + tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner" + depends on SPI + select REGMAP_SPI + help + Say yes here to build support for Texas Instruments' LMK04832 Ultra + Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs + config COMMON_CLK_MAX77686 tristate "Clock driver for Maxim 77620/77686/77802 MFD" depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST @@ -335,6 +339,16 @@ config COMMON_CLK_STM32MP157 help Support for stm32mp157 SoC family clocks +config COMMON_CLK_STM32MP157_SCMI + bool "stm32mp157 Clock driver with Trusted Firmware" + depends on COMMON_CLK_STM32MP157 + select COMMON_CLK_SCMI + select ARM_SCMI_PROTOCOL + default y + help + Support for stm32mp157 SoC family clocks with Trusted Firmware using + SCMI protocol. + config COMMON_CLK_STM32F def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) help @@ -358,10 +372,10 @@ config COMMON_CLK_MMP2_AUDIO config COMMON_CLK_BD718XX tristate "Clock driver for 32K clk gates on ROHM PMICs" - depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828 + depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828 help - This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and - ROHM BD70528 PMICs clock gates. + This driver supports ROHM BD71837, BD71847, BD71850, BD71815 + and BD71828 PMICs clock gates. config COMMON_CLK_FIXED_MMIO bool "Clock driver for Memory Mapped Fixed values" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5f06879d7fe9..2b91d34c582b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # common clock types -obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o -obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o +obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o @@ -37,6 +36,7 @@ obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o +obj-$(CONFIG_LMK04832) += clk-lmk04832.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 61bb224f6330..57d06e183dff 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" }; @@ -127,8 +128,7 @@ static struct clk_factor_table sd_factor_table[] = { { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 }, { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 }, { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 }, - { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 }, - { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 }, + { 24, 1, 25 }, /* bit8: /128 */ { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 }, @@ -137,19 +137,20 @@ static struct clk_factor_table sd_factor_table[] = { { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 }, { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, - { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 }, - { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 }, + { 280, 1, 25 * 128 }, { 0, 0, 0 }, }; -static struct clk_factor_table bisp_factor_table[] = { - { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, - { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, +static struct clk_factor_table de_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, + { 8, 1, 12 }, { 0, 0, 0 }, }; -static struct clk_factor_table ahb_factor_table[] = { - { 1, 1, 2 }, { 2, 1, 3 }, +static struct clk_factor_table hde_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, { 0, 0, 0 }, }; @@ -158,6 +159,13 @@ static struct clk_div_table rmii_ref_div_table[] = { { 0, 0 }, }; +static struct clk_div_table std12rate_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, + { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, + { 0, 0 }, +}; + static struct clk_div_table i2s_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, @@ -174,7 +182,6 @@ static struct clk_div_table nand_div_table[] = { /* mux clock */ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); -static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); /* gate clocks */ static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); @@ -187,45 +194,60 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ -static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0); -static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); +static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ -static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); -static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); -static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); +static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); +static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 4, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), + 0); + +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 8, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL), + CLK_SET_RATE_PARENT); + +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk", + { 0 }, + 1, 1, 0); + static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), - OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), - OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 0); -static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, +static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p, OWL_MUX_HW(CMU_BISPCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), + OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), 0); -static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), + 0); -static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), + 0); static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), @@ -302,10 +324,14 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); +static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), + 1, 20, 0); + static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, @@ -317,31 +343,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, @@ -436,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = { &apb_clk.common, &dmac_clk.common, &gpio_clk.common, + &nic_clk.common, + ðernet_clk.common, }; static struct clk_hw_onecell_data s500_hw_clks = { @@ -495,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = { [CLK_APB] = &apb_clk.common.hw, [CLK_DMAC] = &dmac_clk.common.hw, [CLK_GPIO] = &gpio_clk.common.hw, + [CLK_NIC] = &nic_clk.common.hw, + [CLK_ETHERNET] = ðernet_clk.common.hw, }, .num = CLK_NR_CLKS, }; diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index 776ead319ae9..09ca82356399 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -23,8 +23,12 @@ #include #include +#include #include #include +#include +#include + #include /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */ @@ -198,7 +202,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c, } /** - * wrpll_configure() - compute PLL configuration for a target rate + * wrpll_configure_for_rate() - compute PLL configuration for a target rate * @c: ptr to a struct wrpll_cfg record to write into * @target_rate: target PLL output clock rate (post-Q-divider) * @parent_rate: PLL input refclk rate (pre-R-divider) diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c index d9e70e506d18..ac40b669d60b 100644 --- a/drivers/clk/clk-bd718x7.c +++ b/drivers/clk/clk-bd718x7.c @@ -15,15 +15,13 @@ /* clk control registers */ /* BD71815 */ #define BD71815_REG_OUT32K 0x1d -/* BD70528 */ -#define BD70528_REG_OUT32K 0x2c /* BD71828 */ #define BD71828_REG_OUT32K 0x4B /* BD71837 and BD71847 */ #define BD718XX_REG_OUT32K 0x2E /* - * BD71837, BD71847, BD70528 and BD71828 all use bit [0] to clk output control + * BD71837, BD71847, and BD71828 all use bit [0] to clk output control */ #define CLK_OUT_EN_MASK BIT(0) @@ -116,10 +114,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) c->reg = BD71828_REG_OUT32K; c->mask = CLK_OUT_EN_MASK; break; - case ROHM_CHIP_TYPE_BD70528: - c->reg = BD70528_REG_OUT32K; - c->mask = CLK_OUT_EN_MASK; - break; case ROHM_CHIP_TYPE_BD71815: c->reg = BD71815_REG_OUT32K; c->mask = CLK_OUT_EN_MASK; @@ -150,7 +144,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) static const struct platform_device_id bd718x7_clk_id[] = { { "bd71837-clk", ROHM_CHIP_TYPE_BD71837 }, { "bd71847-clk", ROHM_CHIP_TYPE_BD71847 }, - { "bd70528-clk", ROHM_CHIP_TYPE_BD70528 }, { "bd71828-clk", ROHM_CHIP_TYPE_BD71828 }, { "bd71815-clk", ROHM_CHIP_TYPE_BD71815 }, { }, @@ -168,6 +161,6 @@ static struct platform_driver bd71837_clk = { module_platform_driver(bd71837_clk); MODULE_AUTHOR("Matti Vaittinen "); -MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD70528 chip clk driver"); +MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:bd718xx-clk"); diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c new file mode 100644 index 000000000000..c1095e733220 --- /dev/null +++ b/drivers/clk/clk-lmk04832.c @@ -0,0 +1,1599 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner + * Pin compatible with the LMK0482x family + * + * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf + * + * Copyright (c) 2020, Xiphos Systems Corp. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* 0x000 - 0x00d System Functions */ +#define LMK04832_REG_RST3W 0x000 +#define LMK04832_BIT_RESET BIT(7) +#define LMK04832_BIT_SPI_3WIRE_DIS BIT(4) +#define LMK04832_REG_POWERDOWN 0x002 +#define LMK04832_REG_ID_DEV_TYPE 0x003 +#define LMK04832_REG_ID_PROD_MSB 0x004 +#define LMK04832_REG_ID_PROD_LSB 0x005 +#define LMK04832_REG_ID_MASKREV 0x006 +#define LMK04832_REG_ID_VNDR_MSB 0x00c +#define LMK04832_REG_ID_VNDR_LSB 0x00d + +/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */ +#define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8) +#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0) +#define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8) +#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0) +#define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8) +#define LMK04832_BIT_CLKOUTX_Y_PD BIT(7) +#define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4) +#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2) +#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0) +#define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8) +#define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5) +#define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8) +#define LMK04832_BIT_DCLKX_Y_PD BIT(4) +#define LMK04832_BIT_DCLKX_Y_DCC BIT(2) +#define LMK04832_BIT_DCLKX_Y_HS BIT(0) +#define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8) +#define LMK04832_BIT_SCLK_PD BIT(4) +#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2) +#define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8) +#define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8) +#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0) +#define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8) +#define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f) +#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00 +#define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01 +#define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02 +#define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03 +#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04 +#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05 +#define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06 +#define LMK04832_VAL_CLKOUT_FMT_CML16 0x07 +#define LMK04832_VAL_CLKOUT_FMT_CML24 0x08 +#define LMK04832_VAL_CLKOUT_FMT_CML32 0x09 +#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a +#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b +#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c +#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d +#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e +#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f + +/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */ +#define LMK04832_REG_VCO_OSCOUT 0x138 +#define LMK04832_BIT_VCO_MUX GENMASK(6, 5) +#define LMK04832_VAL_VCO_MUX_VCO0 0x00 +#define LMK04832_VAL_VCO_MUX_VCO1 0x01 +#define LMK04832_VAL_VCO_MUX_EXT 0x02 +#define LMK04832_REG_SYSREF_OUT 0x139 +#define LMK04832_BIT_SYSREF_REQ_EN BIT(6) +#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0) +#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00 +#define LMK04832_VAL_SYSREF_MUX_RECLK 0x01 +#define LMK04832_VAL_SYSREF_MUX_PULSER 0x02 +#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03 +#define LMK04832_REG_SYSREF_DIV_MSB 0x13a +#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0) +#define LMK04832_REG_SYSREF_DIV_LSB 0x13b +#define LMK04832_REG_SYSREF_DDLY_MSB 0x13c +#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0) +#define LMK04832_REG_SYSREF_DDLY_LSB 0x13d +#define LMK04832_REG_SYSREF_PULSE_CNT 0x13e +#define LMK04832_REG_FB_CTRL 0x13f +#define LMK04832_BIT_PLL2_RCLK_MUX BIT(7) +#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00 +#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01 +#define LMK04832_BIT_PLL2_NCLK_MUX BIT(5) +#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00 +#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01 +#define LMK04832_BIT_FB_MUX_EN BIT(0) +#define LMK04832_REG_MAIN_PD 0x140 +#define LMK04832_BIT_PLL1_PD BIT(7) +#define LMK04832_BIT_VCO_LDO_PD BIT(6) +#define LMK04832_BIT_VCO_PD BIT(5) +#define LMK04832_BIT_OSCIN_PD BIT(4) +#define LMK04832_BIT_SYSREF_GBL_PD BIT(3) +#define LMK04832_BIT_SYSREF_PD BIT(2) +#define LMK04832_BIT_SYSREF_DDLY_PD BIT(1) +#define LMK04832_BIT_SYSREF_PLSR_PD BIT(0) +#define LMK04832_REG_SYNC 0x143 +#define LMK04832_BIT_SYNC_CLR BIT(7) +#define LMK04832_BIT_SYNC_1SHOT_EN BIT(6) +#define LMK04832_BIT_SYNC_POL BIT(5) +#define LMK04832_BIT_SYNC_EN BIT(4) +#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0) +#define LMK04832_VAL_SYNC_MODE_OFF 0x00 +#define LMK04832_VAL_SYNC_MODE_ON 0x01 +#define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02 +#define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03 +#define LMK04832_REG_SYNC_DIS 0x144 + +/* 0x146 - 0x14a CLKin Control */ +#define LMK04832_REG_CLKIN_SEL0 0x148 +#define LMK04832_REG_CLKIN_SEL1 0x149 +#define LMK04832_REG_CLKIN_RST 0x14a +#define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6) +#define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3) +#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06 +#define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0) +#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03 + +/* 0x14b - 0x152 Holdover */ + +/* 0x153 - 0x15f PLL1 Configuration */ + +/* 0x160 - 0x16e PLL2 Configuration */ +#define LMK04832_REG_PLL2_R_MSB 0x160 +#define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0) +#define LMK04832_REG_PLL2_R_LSB 0x161 +#define LMK04832_REG_PLL2_MISC 0x162 +#define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5) +#define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0) +#define LMK04832_REG_PLL2_N_CAL_0 0x163 +#define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0) +#define LMK04832_REG_PLL2_N_CAL_1 0x164 +#define LMK04832_REG_PLL2_N_CAL_2 0x165 +#define LMK04832_REG_PLL2_N_0 0x166 +#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0) +#define LMK04832_REG_PLL2_N_1 0x167 +#define LMK04832_REG_PLL2_N_2 0x168 +#define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a +#define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b +#define LMK04832_REG_PLL2_LD 0x16e +#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3) +#define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02 +#define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0) +#define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03 + +/* 0x16F - 0x555 Misc Registers */ +#define LMK04832_REG_PLL2_PD 0x173 +#define LMK04832_BIT_PLL2_PRE_PD BIT(6) +#define LMK04832_BIT_PLL2_PD BIT(5) +#define LMK04832_REG_PLL1R_RST 0x177 +#define LMK04832_REG_CLR_PLL_LOST 0x182 +#define LMK04832_REG_RB_PLL_LD 0x183 +#define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184 +#define LMK04832_REG_RB_DAC_VAL_LSB 0x185 +#define LMK04832_REG_RB_HOLDOVER 0x188 +#define LMK04832_REG_SPI_LOCK 0x555 + +enum lmk04832_device_types { + LMK04832, +}; + +/** + * lmk04832_device_info - Holds static device information that is specific to + * the chip revision + * + * pid: Product Identifier + * maskrev: IC version identifier + * num_channels: Number of available output channels (clkout count) + * vco0_range: {min, max} of the VCO0 operating range (in MHz) + * vco1_range: {min, max} of the VCO1 operating range (in MHz) + */ +struct lmk04832_device_info { + u16 pid; + u8 maskrev; + size_t num_channels; + unsigned int vco0_range[2]; + unsigned int vco1_range[2]; +}; + +static const struct lmk04832_device_info lmk04832_device_info[] = { + [LMK04832] = { + .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */ + .maskrev = 0x70, + .num_channels = 14, + .vco0_range = { 2440, 2580 }, + .vco1_range = { 2945, 3255 }, + }, +}; + +enum lmk04832_rdbk_type { + RDBK_CLKIN_SEL0, + RDBK_CLKIN_SEL1, + RDBK_RESET, +}; + +struct lmk_dclk { + struct lmk04832 *lmk; + struct clk_hw hw; + u8 id; +}; + +struct lmk_clkout { + struct lmk04832 *lmk; + struct clk_hw hw; + bool sysref; + u32 format; + u8 id; +}; + +/** + * struct lmk04832 - The LMK04832 device structure + * + * @dev: reference to a struct device, linked to the spi_device + * @regmap: struct regmap instance use to access the chip + * @sync_mode: operational mode for SYNC signal + * @sysref_mux: select SYSREF source + * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous + * mode. + * @sysref_ddly: SYSREF digital delay value + * @oscin: PLL2 input clock + * @vco: reference to the internal VCO clock + * @sclk: reference to the internal sysref clock (SCLK) + * @vco_rate: user provided VCO rate + * @reset_gpio: reference to the reset GPIO + * @dclk: list of internal device clock references. + * Each pair of clkout clocks share a single device clock (DCLKX_Y) + * @clkout: list of output clock references + * @clk_data: holds clkout related data like clk_hw* and number of clocks + */ +struct lmk04832 { + struct device *dev; + struct regmap *regmap; + + unsigned int sync_mode; + unsigned int sysref_mux; + unsigned int sysref_pulse_cnt; + unsigned int sysref_ddly; + + struct clk *oscin; + struct clk_hw vco; + struct clk_hw sclk; + unsigned int vco_rate; + + struct gpio_desc *reset_gpio; + + struct lmk_dclk *dclk; + struct lmk_clkout *clkout; + struct clk_hw_onecell_data *clk_data; +}; + +static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg) +{ + switch (reg) { + case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV: + fallthrough; + case LMK04832_REG_ID_VNDR_MSB: + fallthrough; + case LMK04832_REG_ID_VNDR_LSB: + fallthrough; + case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: + fallthrough; + case LMK04832_REG_PLL2_LD: + fallthrough; + case LMK04832_REG_PLL2_PD: + fallthrough; + case LMK04832_REG_PLL1R_RST: + fallthrough; + case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: + fallthrough; + case LMK04832_REG_RB_HOLDOVER: + fallthrough; + case LMK04832_REG_SPI_LOCK: + return true; + default: + return false; + }; +}; + +static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg) +{ + switch (reg) { + case LMK04832_REG_RST3W: + fallthrough; + case LMK04832_REG_POWERDOWN: + return true; + case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV: + fallthrough; + case LMK04832_REG_ID_VNDR_MSB: + fallthrough; + case LMK04832_REG_ID_VNDR_LSB: + return false; + case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: + fallthrough; + case LMK04832_REG_PLL2_LD: + fallthrough; + case LMK04832_REG_PLL2_PD: + fallthrough; + case LMK04832_REG_PLL1R_RST: + fallthrough; + case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: + fallthrough; + case LMK04832_REG_RB_HOLDOVER: + fallthrough; + case LMK04832_REG_SPI_LOCK: + return true; + default: + return false; + }; +}; + +static const struct regmap_config regmap_config = { + .name = "lmk04832", + .reg_bits = 16, + .val_bits = 8, + .use_single_read = 1, + .use_single_write = 1, + .read_flag_mask = 0x80, + .write_flag_mask = 0x00, + .readable_reg = lmk04832_regmap_rd_regs, + .writeable_reg = lmk04832_regmap_wr_regs, + .cache_type = REGCACHE_NONE, + .max_register = LMK04832_REG_SPI_LOCK, +}; + +static int lmk04832_vco_is_enabled(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + unsigned int tmp; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); + if (ret) + return ret; + + return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) | + FIELD_GET(LMK04832_BIT_VCO_PD, tmp) | + FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp)); +} + +static int lmk04832_vco_prepare(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + int ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, + LMK04832_BIT_PLL2_PRE_PD | + LMK04832_BIT_PLL2_PD, + 0x00); + if (ret) + return ret; + + return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_VCO_LDO_PD | + LMK04832_BIT_VCO_PD | + LMK04832_BIT_OSCIN_PD, 0x00); +} + +static void lmk04832_vco_unprepare(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + + regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, + LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD, + 0xff); + + /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */ + regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff); +} + +static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7}; + unsigned int pll2_n, p, pll2_r; + unsigned int pll2_misc; + unsigned long vco_rate; + u8 tmp[3]; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); + if (ret) + return ret; + + p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc); + + ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); + if (ret) + return ret; + + pll2_n = FIELD_PREP(0x030000, tmp[0]) | + FIELD_PREP(0x00ff00, tmp[1]) | + FIELD_PREP(0x0000ff, tmp[2]); + + ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); + if (ret) + return ret; + + pll2_r = FIELD_PREP(0x0f00, tmp[0]) | + FIELD_PREP(0x00ff, tmp[1]); + + vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN, + pll2_misc)) * pll2_n * pll2_p[p] / pll2_r; + + return vco_rate; +}; + +/** + * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges + * + * @lmk: Reference to the lmk device + * @rate: Desired output rate for the VCO + * + * The LMK04832 has 2 internal VCO, each with independent operating ranges. + * Use the device_info structure to determine which VCO to use based on rate. + * + * Returns VCO_MUX value or negative errno. + */ +static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate) +{ + struct spi_device *spi = to_spi_device(lmk->dev); + const struct lmk04832_device_info *info; + unsigned long mhz = rate / 1000000; + + info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; + + if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) + return LMK04832_VAL_VCO_MUX_VCO0; + + if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) + return LMK04832_VAL_VCO_MUX_VCO1; + + dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); + return -ERANGE; +} + +/** + * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency + * + * @prate: parent rate to the PLL2, usually OSCin + * @rate: Desired output rate for the VCO + * @n: reference to PLL2_N + * @p: reference to PLL2_P + * @r: reference to PLL2_R + * + * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is + * recommended in the datasheet because a higher phase detector frequencies + * makes the design of wider loop bandwidth filters possible. + * + * the VCO rate can be calculated using the following expression: + * + * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R + * + * Returns vco rate or negative errno. + */ +static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate, + unsigned int *n, unsigned int *p, + unsigned int *r) +{ + unsigned int pll2_n, pll2_p, pll2_r; + unsigned long num, div; + + /* Set PLL2_P to a fixed value to simplify optimizations */ + pll2_p = 2; + + div = gcd(rate, prate); + + num = DIV_ROUND_CLOSEST(rate, div); + pll2_r = DIV_ROUND_CLOSEST(prate, div); + + if (num > 4) { + pll2_n = num >> 2; + } else { + pll2_r = pll2_r << 2; + pll2_n = num; + } + + if (pll2_n < 1 || pll2_n > 0x03ffff) + return -EINVAL; + if (pll2_r < 1 || pll2_r > 0xfff) + return -EINVAL; + + *n = pll2_n; + *p = pll2_p; + *r = pll2_r; + + return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r); +} + +static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + unsigned int n, p, r; + long vco_rate; + int ret; + + ret = lmk04832_check_vco_ranges(lmk, rate); + if (ret < 0) + return ret; + + vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r); + if (vco_rate < 0) { + dev_err(lmk->dev, "PLL2 parmeters out of range\n"); + return vco_rate; + } + + if (rate != vco_rate) + return -EINVAL; + + return vco_rate; +}; + +static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); + unsigned int n, p, r; + long vco_rate; + int vco_mux; + int ret; + + vco_mux = lmk04832_check_vco_ranges(lmk, rate); + if (vco_mux < 0) + return vco_mux; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, + LMK04832_BIT_VCO_MUX, + FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux)); + if (ret) + return ret; + + vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r); + if (vco_rate < 0) { + dev_err(lmk->dev, "failed to determine PLL2 parmeters\n"); + return vco_rate; + } + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, + LMK04832_BIT_PLL2_R_MSB, + FIELD_GET(0x000700, r)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, + FIELD_GET(0x0000ff, r)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, + LMK04832_BIT_PLL2_MISC_P, + FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p)); + if (ret) + return ret; + + /* + * PLL2_N registers must be programmed after other PLL2 dividers are + * programed to ensure proper VCO frequency calibration + */ + ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, + FIELD_GET(0x030000, n)); + if (ret) + return ret; + ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, + FIELD_GET(0x00ff00, n)); + if (ret) + return ret; + + return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, + FIELD_GET(0x0000ff, n)); +}; + +static const struct clk_ops lmk04832_vco_ops = { + .is_enabled = lmk04832_vco_is_enabled, + .prepare = lmk04832_vco_prepare, + .unprepare = lmk04832_vco_unprepare, + .recalc_rate = lmk04832_vco_recalc_rate, + .round_rate = lmk04832_vco_round_rate, + .set_rate = lmk04832_vco_set_rate, +}; + +/* + * lmk04832_register_vco - Initialize the internal VCO and clock distribution + * path in PLL2 single loop mode. + */ +static int lmk04832_register_vco(struct lmk04832 *lmk) +{ + const char *parent_names[1]; + struct clk_init_data init; + int ret; + + init.name = "lmk-vco"; + parent_names[0] = __clk_get_name(lmk->oscin); + init.parent_names = parent_names; + + init.ops = &lmk04832_vco_ops; + init.num_parents = 1; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, + LMK04832_BIT_VCO_MUX, + FIELD_PREP(LMK04832_BIT_VCO_MUX, + LMK04832_VAL_VCO_MUX_VCO1)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, + LMK04832_BIT_PLL2_RCLK_MUX | + LMK04832_BIT_PLL2_NCLK_MUX, + FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX, + LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)| + FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX, + LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, + LMK04832_BIT_PLL2_MISC_REF_2X_EN, + LMK04832_BIT_PLL2_MISC_REF_2X_EN); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, + FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX, + LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) | + FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE, + LMK04832_VAL_PLL2_LD_TYPE_OUT_PP)); + if (ret) + return ret; + + lmk->vco.init = &init; + return devm_clk_hw_register(lmk->dev, &lmk->vco); +} + +static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id) +{ + int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; + unsigned int sclkx_y_ddly = 10; + unsigned int dclkx_y_ddly; + unsigned int dclkx_y_div; + unsigned int sysref_ddly; + unsigned int dclkx_y_hs; + unsigned int lsb, msb; + int ret; + + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL2(id), + LMK04832_BIT_DCLKX_Y_DDLY_PD, + FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0)); + if (ret) + return ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); + if (ret) + return ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); + if (ret) + return ret; + + sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); + if (ret) + return ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); + if (ret) + return ret; + + dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); + if (ret) + return ret; + + dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb); + + dclkx_y_ddly = sysref_ddly + 1 - + dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - + dclkx_y_hs + sclkx_y_ddly; + + if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) { + dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", + dclkx_y_ddly); + return -EINVAL; + } + + ret = regmap_write(lmk->regmap, + LMK04832_REG_SCLKX_Y_DDLY(id), + FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), + FIELD_GET(0x00ff, dclkx_y_ddly)); + if (ret) + return ret; + + dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " + "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n", + id, sysref_ddly, dclkx_y_ddly, + dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7], + dclkx_y_hs, sclkx_y_ddly); + + return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), + LMK04832_BIT_DCLKX_Y_DDLY_MSB, + FIELD_GET(0x0300, dclkx_y_ddly)); +} + +/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk + * and dclk + * + * @lmk: Reference to the lmk device + * + * The synchronization sequence: + * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31 + * (8.3.3.1 How to enable SYSREF) + * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972 + * + * Returns 0 or negative errno. + */ +static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk) +{ + int ret; + int i; + + /* 1. (optional) mute all sysref_outputs during synchronization */ + /* 2. Enable and write device clock digital delay to applicable clocks */ + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_SYSREF_DDLY_PD, + FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0)); + if (ret) + return ret; + + for (i = 0; i < lmk->clk_data->num; i += 2) { + ret = lmk04832_clkout_set_ddly(lmk, i); + if (ret) + return ret; + } + + /* + * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC, + * and clear SYSREF_REQ_EN (see 6.) + */ + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, + LMK04832_BIT_SYSREF_REQ_EN | + LMK04832_BIT_SYSREF_MUX, + FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) | + FIELD_PREP(LMK04832_BIT_SYSREF_MUX, + LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_MODE, + FIELD_PREP(LMK04832_BIT_SYNC_MODE, + LMK04832_VAL_SYNC_MODE_ON)); + if (ret) + return ret; + + /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */ + ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); + if (ret) + return ret; + + /* + * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock + * distribution path cycles (VCO cycles), then back to 0. In + * PLL2-only use case, this will be complete in less than one SPI + * transaction. If SYSREF local digital delay is not used, this step + * can be skipped. + */ + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_CLR, + FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_CLR, + FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00)); + if (ret) + return ret; + + /* + * 6. Toggle SYNC_POL state between inverted and not inverted. + * If you use an external signal on the SYNC pin instead of toggling + * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX + * does not shift into continuous SYSREF mode. + */ + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_POL, + FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_POL, + FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00)); + if (ret) + return ret; + + /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */ + ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); + if (ret) + return ret; + + /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */ + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, + LMK04832_BIT_SYSREF_MUX, + FIELD_PREP(LMK04832_BIT_SYSREF_MUX, + lmk->sysref_mux)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, + LMK04832_BIT_SYNC_MODE, + FIELD_PREP(LMK04832_BIT_SYNC_MODE, + lmk->sync_mode)); + if (ret) + return ret; + + /* + * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs + * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state, + * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional + * option. + */ + + /* + * 10. (optional) To reduce power consumption, after the synchronization + * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the + * digital delay counters (which are only used immediately after the + * SYNC pulse to delay the output by some number of VCO counts). + */ + + return ret; +} + +static int lmk04832_sclk_is_enabled(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + unsigned int tmp; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); + if (ret) + return ret; + + return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp); +} + +static int lmk04832_sclk_prepare(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + + return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_SYSREF_PD, 0x00); +} + +static void lmk04832_sclk_unprepare(struct clk_hw *hw) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + + regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD); +} + +static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + unsigned int sysref_div; + u8 tmp[2]; + int ret; + + ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); + if (ret) + return ret; + + sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 | + tmp[1]; + + return DIV_ROUND_CLOSEST(prate, sysref_div); +} + +static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + unsigned long sclk_rate; + unsigned int sysref_div; + + sysref_div = DIV_ROUND_CLOSEST(*prate, rate); + sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div); + + if (sysref_div < 0x07 || sysref_div > 0x1fff) { + dev_err(lmk->dev, "SYSREF divider out of range\n"); + return -EINVAL; + } + + if (rate != sclk_rate) + return -EINVAL; + + return sclk_rate; +} + +static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); + unsigned int sysref_div; + int ret; + + sysref_div = DIV_ROUND_CLOSEST(prate, rate); + + if (sysref_div < 0x07 || sysref_div > 0x1fff) { + dev_err(lmk->dev, "SYSREF divider out of range\n"); + return -EINVAL; + } + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, + FIELD_GET(0x1f00, sysref_div)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, + FIELD_GET(0x00ff, sysref_div)); + if (ret) + return ret; + + ret = lmk04832_sclk_sync_sequence(lmk); + if (ret) + dev_err(lmk->dev, "SYNC sequence failed\n"); + + return ret; +} + +static const struct clk_ops lmk04832_sclk_ops = { + .is_enabled = lmk04832_sclk_is_enabled, + .prepare = lmk04832_sclk_prepare, + .unprepare = lmk04832_sclk_unprepare, + .recalc_rate = lmk04832_sclk_recalc_rate, + .round_rate = lmk04832_sclk_round_rate, + .set_rate = lmk04832_sclk_set_rate, +}; + +static int lmk04832_register_sclk(struct lmk04832 *lmk) +{ + const char *parent_names[1]; + struct clk_init_data init; + int ret; + + init.name = "lmk-sclk"; + parent_names[0] = clk_hw_get_name(&lmk->vco); + init.parent_names = parent_names; + + init.ops = &lmk04832_sclk_ops; + init.flags = CLK_SET_RATE_PARENT; + init.num_parents = 1; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, + LMK04832_BIT_SYSREF_MUX, + FIELD_PREP(LMK04832_BIT_SYSREF_MUX, + lmk->sysref_mux)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, + FIELD_GET(0x00ff, lmk->sysref_ddly)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, + FIELD_GET(0x1f00, lmk->sysref_ddly)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, + ilog2(lmk->sysref_pulse_cnt)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, + LMK04832_BIT_SYSREF_DDLY_PD | + LMK04832_BIT_SYSREF_PLSR_PD, + FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) | + FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, + FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) | + FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) | + FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); + if (ret) + return ret; + + lmk->sclk.init = &init; + return devm_clk_hw_register(lmk->dev, &lmk->sclk); +} + +static int lmk04832_dclk_is_enabled(struct clk_hw *hw) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + unsigned int tmp; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), + &tmp); + if (ret) + return ret; + + return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp); +} + +static int lmk04832_dclk_prepare(struct clk_hw *hw) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + + return regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL3(dclk->id), + LMK04832_BIT_DCLKX_Y_PD, 0x00); +} + +static void lmk04832_dclk_unprepare(struct clk_hw *hw) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + + regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL3(dclk->id), + LMK04832_BIT_DCLKX_Y_PD, 0xff); +} + +static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + unsigned int dclk_div; + unsigned int lsb, msb; + unsigned long rate; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), + &lsb); + if (ret) + return ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), + &msb); + if (ret) + return ret; + + dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; + rate = DIV_ROUND_CLOSEST(prate, dclk_div); + + return rate; +}; + +static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + unsigned long dclk_rate; + unsigned int dclk_div; + + dclk_div = DIV_ROUND_CLOSEST(*prate, rate); + dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div); + + if (dclk_div < 1 || dclk_div > 0x3ff) { + dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); + return -EINVAL; + } + + if (rate != dclk_rate) + return -EINVAL; + + return dclk_rate; +}; + +static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); + struct lmk04832 *lmk = dclk->lmk; + unsigned int dclk_div; + int ret; + + dclk_div = DIV_ROUND_CLOSEST(prate, rate); + + if (dclk_div > 0x3ff) { + dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); + return -EINVAL; + } + + /* Enable Duty Cycle Corretion */ + if (dclk_div == 1) { + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL3(dclk->id), + LMK04832_BIT_DCLKX_Y_DCC, + FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1)); + if (ret) + return ret; + } + + /* + * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC + * procedure requires to first program Divide-by-4 and then back to + * Divide-by-2 or Divide-by-3 before doing SYNC. + */ + if (dclk_div == 2 || dclk_div == 3) { + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL2(dclk->id), + LMK04832_BIT_DCLK_DIV_MSB, 0x00); + if (ret) + return ret; + + ret = regmap_write(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); + if (ret) + return ret; + } + + ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), + FIELD_GET(0x0ff, dclk_div)); + if (ret) + return ret; + + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL2(dclk->id), + LMK04832_BIT_DCLK_DIV_MSB, + FIELD_GET(0x300, dclk_div)); + if (ret) + return ret; + + ret = lmk04832_sclk_sync_sequence(lmk); + if (ret) + dev_err(lmk->dev, "SYNC sequence failed\n"); + + return ret; +}; + +static const struct clk_ops lmk04832_dclk_ops = { + .is_enabled = lmk04832_dclk_is_enabled, + .prepare = lmk04832_dclk_prepare, + .unprepare = lmk04832_dclk_unprepare, + .recalc_rate = lmk04832_dclk_recalc_rate, + .round_rate = lmk04832_dclk_round_rate, + .set_rate = lmk04832_dclk_set_rate, +}; + +static int lmk04832_clkout_is_enabled(struct clk_hw *hw) +{ + struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); + struct lmk04832 *lmk = clkout->lmk; + unsigned int clkoutx_y_pd; + unsigned int sclkx_y_pd; + unsigned int tmp; + u32 enabled; + int ret; + u8 fmt; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), + &clkoutx_y_pd); + if (ret) + return ret; + + enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd); + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), + &tmp); + if (ret) + return ret; + + if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { + ret = regmap_read(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL4(clkout->id), + &sclkx_y_pd); + if (ret) + return ret; + + enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd); + } + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), + &tmp); + if (ret) + return ret; + + if (clkout->id % 2) + fmt = FIELD_GET(0xf0, tmp); + else + fmt = FIELD_GET(0x0f, tmp); + + return enabled && !fmt; +} + +static int lmk04832_clkout_prepare(struct clk_hw *hw) +{ + struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); + struct lmk04832 *lmk = clkout->lmk; + unsigned int tmp; + int ret; + + if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) + dev_err(lmk->dev, "prepared %s but format is powerdown\n", + clk_hw_get_name(hw)); + + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL2(clkout->id), + LMK04832_BIT_CLKOUTX_Y_PD, 0x00); + if (ret) + return ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), + &tmp); + if (ret) + return ret; + + if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { + ret = regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_CTRL4(clkout->id), + LMK04832_BIT_SCLK_PD, 0x00); + if (ret) + return ret; + } + + return regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_FMT(clkout->id), + LMK04832_BIT_CLKOUT_FMT(clkout->id), + clkout->format << 4 * (clkout->id % 2)); +} + +static void lmk04832_clkout_unprepare(struct clk_hw *hw) +{ + struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); + struct lmk04832 *lmk = clkout->lmk; + + regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), + LMK04832_BIT_CLKOUT_FMT(clkout->id), + 0x00); +} + +static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index) +{ + struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); + struct lmk04832 *lmk = clkout->lmk; + + return regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), + LMK04832_BIT_CLKOUT_SRC_MUX, + FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, + index)); +} + +static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw) +{ + struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); + struct lmk04832 *lmk = clkout->lmk; + unsigned int tmp; + int ret; + + ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), + &tmp); + if (ret) + return ret; + + return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp); +} + +static const struct clk_ops lmk04832_clkout_ops = { + .is_enabled = lmk04832_clkout_is_enabled, + .prepare = lmk04832_clkout_prepare, + .unprepare = lmk04832_clkout_unprepare, + .set_parent = lmk04832_clkout_set_parent, + .get_parent = lmk04832_clkout_get_parent, +}; + +static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num) +{ + char name[] = "lmk-clkoutXX"; + char dclk_name[] = "lmk-dclkXX_YY"; + const char *parent_names[2]; + struct clk_init_data init; + int dclk_num = num / 2; + int ret; + + if (num % 2 == 0) { + sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); + init.name = dclk_name; + parent_names[0] = clk_hw_get_name(&lmk->vco); + init.ops = &lmk04832_dclk_ops; + init.flags = CLK_SET_RATE_PARENT; + init.num_parents = 1; + + lmk->dclk[dclk_num].id = num; + lmk->dclk[dclk_num].lmk = lmk; + lmk->dclk[dclk_num].hw.init = &init; + + ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); + if (ret) + return ret; + } else { + sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); + } + + if (of_property_read_string_index(lmk->dev->of_node, + "clock-output-names", + num, &init.name)) { + sprintf(name, "lmk-clkout%02d", num); + init.name = name; + } + + parent_names[0] = dclk_name; + parent_names[1] = clk_hw_get_name(&lmk->sclk); + init.parent_names = parent_names; + init.ops = &lmk04832_clkout_ops; + init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; + init.num_parents = ARRAY_SIZE(parent_names); + + lmk->clkout[num].id = num; + lmk->clkout[num].lmk = lmk; + lmk->clkout[num].hw.init = &init; + lmk->clk_data->hws[num] = &lmk->clkout[num].hw; + + /* Set initial parent */ + regmap_update_bits(lmk->regmap, + LMK04832_REG_CLKOUT_SRC_MUX(num), + LMK04832_BIT_CLKOUT_SRC_MUX, + FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, + lmk->clkout[num].sysref)); + + return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); +} + +static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) +{ + int reg; + int ret; + + dev_info(lmk->dev, "setting up 4-wire mode\n"); + ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, + LMK04832_BIT_SPI_3WIRE_DIS); + if (ret) + return ret; + + switch (rdbk_pin) { + case RDBK_CLKIN_SEL0: + reg = LMK04832_REG_CLKIN_SEL0; + break; + case RDBK_CLKIN_SEL1: + reg = LMK04832_REG_CLKIN_SEL1; + break; + case RDBK_RESET: + reg = LMK04832_REG_CLKIN_RST; + break; + default: + return -EINVAL; + } + + return regmap_write(lmk->regmap, reg, + FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX, + LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) | + FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE, + LMK04832_VAL_CLKIN_SEL_TYPE_OUT)); +} + +static int lmk04832_probe(struct spi_device *spi) +{ + const struct lmk04832_device_info *info; + int rdbk_pin = RDBK_CLKIN_SEL1; + struct device_node *child; + struct lmk04832 *lmk; + u8 tmp[3]; + int ret; + int i; + + info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; + + lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); + if (!lmk) + return -ENOMEM; + + lmk->dev = &spi->dev; + + lmk->oscin = devm_clk_get(lmk->dev, "oscin"); + if (IS_ERR(lmk->oscin)) { + dev_err(lmk->dev, "failed to get oscin clock\n"); + return PTR_ERR(lmk->oscin); + } + + ret = clk_prepare_enable(lmk->oscin); + if (ret) + return ret; + + lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", + GPIOD_OUT_LOW); + + lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, + sizeof(struct lmk_dclk), GFP_KERNEL); + if (IS_ERR(lmk->dclk)) { + ret = PTR_ERR(lmk->dclk); + goto err_disable_oscin; + } + + lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, + sizeof(*lmk->clkout), GFP_KERNEL); + if (IS_ERR(lmk->clkout)) { + ret = PTR_ERR(lmk->clkout); + goto err_disable_oscin; + } + + lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, + info->num_channels), + GFP_KERNEL); + if (IS_ERR(lmk->clk_data)) { + ret = PTR_ERR(lmk->clk_data); + goto err_disable_oscin; + } + + device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); + + lmk->sysref_ddly = 8; + device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); + + lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; + device_property_read_u32(lmk->dev, "ti,sysref-mux", + &lmk->sysref_mux); + + lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; + device_property_read_u32(lmk->dev, "ti,sync-mode", + &lmk->sync_mode); + + lmk->sysref_pulse_cnt = 4; + device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", + &lmk->sysref_pulse_cnt); + + for_each_child_of_node(lmk->dev->of_node, child) { + int reg; + + ret = of_property_read_u32(child, "reg", ®); + if (ret) { + dev_err(lmk->dev, "missing reg property in child: %s\n", + child->full_name); + of_node_put(child); + goto err_disable_oscin; + } + + of_property_read_u32(child, "ti,clkout-fmt", + &lmk->clkout[reg].format); + + if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 + && reg != 8 && reg != 10) + dev_err(lmk->dev, "invalid format for clkout%02d\n", + reg); + + lmk->clkout[reg].sysref = + of_property_read_bool(child, "ti,clkout-sysref"); + } + + lmk->regmap = devm_regmap_init_spi(spi, ®map_config); + if (IS_ERR(lmk->regmap)) { + dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", + + __func__, PTR_ERR(lmk->regmap)); + ret = PTR_ERR(lmk->regmap); + goto err_disable_oscin; + } + + regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); + + if (!(spi->mode & SPI_3WIRE)) { + device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", + &rdbk_pin); + ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin); + if (ret) + goto err_disable_oscin; + } + + regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); + if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { + dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", + tmp[0] << 8 | tmp[1], tmp[2]); + ret = -EINVAL; + goto err_disable_oscin; + } + + ret = lmk04832_register_vco(lmk); + if (ret) { + dev_err(lmk->dev, "failed to init device clock path\n"); + goto err_disable_oscin; + } + + if (lmk->vco_rate) { + dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); + ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); + if (ret) { + dev_err(lmk->dev, "failed to set VCO rate\n"); + goto err_disable_vco; + } + } + + ret = lmk04832_register_sclk(lmk); + if (ret) { + dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); + goto err_disable_vco; + } + + for (i = 0; i < info->num_channels; i++) { + ret = lmk04832_register_clkout(lmk, i); + if (ret) { + dev_err(lmk->dev, "failed to register clk %d\n", i); + goto err_disable_vco; + } + } + + lmk->clk_data->num = info->num_channels; + ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get, + lmk->clk_data); + if (ret) { + dev_err(lmk->dev, "failed to add provider (%d)\n", ret); + goto err_disable_vco; + } + + spi_set_drvdata(spi, lmk); + + return 0; + +err_disable_vco: + clk_disable_unprepare(lmk->vco.clk); + +err_disable_oscin: + clk_disable_unprepare(lmk->oscin); + + return ret; +} + +static int lmk04832_remove(struct spi_device *spi) +{ + struct lmk04832 *lmk = spi_get_drvdata(spi); + + clk_disable_unprepare(lmk->oscin); + of_clk_del_provider(spi->dev.of_node); + + return 0; +} +static const struct spi_device_id lmk04832_id[] = { + { "lmk04832", LMK04832 }, + {} +}; +MODULE_DEVICE_TABLE(spi, lmk04832_id); + +static const struct of_device_id lmk04832_of_id[] = { + { .compatible = "ti,lmk04832" }, + {} +}; +MODULE_DEVICE_TABLE(of, lmk04832_of_id); + +static struct spi_driver lmk04832_driver = { + .driver = { + .name = "lmk04832", + .of_match_table = lmk04832_of_id, + }, + .probe = lmk04832_probe, + .remove = lmk04832_remove, + .id_table = lmk04832_id, +}; +module_spi_driver(lmk04832_driver); + +MODULE_AUTHOR("Liam Beguin "); +MODULE_DESCRIPTION("Texas Instruments LMK04832"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index e0446e66fa64..57ae183982d8 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -59,6 +60,7 @@ struct clk_si5341_synth { struct clk_si5341_output { struct clk_hw hw; struct clk_si5341 *data; + struct regulator *vddo_reg; u8 index; }; #define to_clk_si5341_output(_hw) \ @@ -78,12 +80,15 @@ struct clk_si5341 { u8 num_outputs; u8 num_synth; u16 chip_id; + bool xaxb_ext_clk; + bool iovdd_33; }; #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) struct clk_si5341_output_config { u8 out_format_drv_bits; u8 out_cm_ampl_bits; + u8 vdd_sel_bits; bool synth_master; bool always_on; }; @@ -92,12 +97,23 @@ struct clk_si5341_output_config { #define SI5341_PN_BASE 0x0002 #define SI5341_DEVICE_REV 0x0005 #define SI5341_STATUS 0x000C +#define SI5341_LOS 0x000D +#define SI5341_STATUS_STICKY 0x0011 +#define SI5341_LOS_STICKY 0x0012 #define SI5341_SOFT_RST 0x001C #define SI5341_IN_SEL 0x0021 +#define SI5341_DEVICE_READY 0x00FE #define SI5341_XAXB_CFG 0x090E +#define SI5341_IO_VDD_SEL 0x0943 #define SI5341_IN_EN 0x0949 #define SI5341_INX_TO_PFD_EN 0x094A +/* Status bits */ +#define SI5341_STATUS_SYSINCAL BIT(0) +#define SI5341_STATUS_LOSXAXB BIT(1) +#define SI5341_STATUS_LOSREF BIT(2) +#define SI5341_STATUS_LOL BIT(3) + /* Input selection */ #define SI5341_IN_SEL_MASK 0x06 #define SI5341_IN_SEL_SHIFT 1 @@ -126,6 +142,8 @@ struct clk_si5341_output_config { #define SI5341_OUT_R_REG(output) \ ((output)->data->reg_rdiv_offset[(output)->index]) +#define SI5341_OUT_MUX_VDD_SEL_MASK 0x38 + /* Synthesize N divider */ #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) @@ -335,11 +353,12 @@ static const struct si5341_reg_default si5341_reg_defaults[] = { { 0x0804, 0x00 }, /* Not in datasheet */ { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ - { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */ { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ { 0x0A02, 0x00 }, /* Not in datasheet */ { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ + { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */ + { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */ }; /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ @@ -512,9 +531,11 @@ static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) if (err < 0) return err; - /* Power up XTAL oscillator and buffer */ + /* Power up XTAL oscillator and buffer, select clock mode */ err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, - SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB); + SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN, + SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ? + SI5341_XAXB_CFG_EXTCLK_EN : 0)); if (err < 0) return err; } @@ -623,6 +644,9 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); if (err < 0) return err; + /* Check for bogus/uninitialized settings */ + if (!n_num || !n_den) + return 0; /* * n_num and n_den are shifted left as much as possible, so to prevent @@ -806,6 +830,9 @@ static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate, { unsigned long r; + if (!rate) + return 0; + r = *parent_rate >> 1; /* If rate is an even divisor, no changes to parent required */ @@ -834,11 +861,16 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_si5341_output *output = to_clk_si5341_output(hw); - /* Frequency divider is (r_div + 1) * 2 */ - u32 r_div = (parent_rate / rate) >> 1; + u32 r_div; int err; u8 r[3]; + if (!rate) + return -EINVAL; + + /* Frequency divider is (r_div + 1) * 2 */ + r_div = (parent_rate / rate) >> 1; + if (r_div <= 1) r_div = 0; else if (r_div >= BIT(24)) @@ -1083,7 +1115,7 @@ static const struct si5341_reg_default si5341_preamble[] = { { 0x0B25, 0x00 }, { 0x0502, 0x01 }, { 0x0505, 0x03 }, - { 0x0957, 0x1F }, + { 0x0957, 0x17 }, { 0x0B4E, 0x1A }, }; @@ -1129,6 +1161,11 @@ static int si5341_finalize_defaults(struct clk_si5341 *data) int res; u32 revision; + res = regmap_write(data->regmap, SI5341_IO_VDD_SEL, + data->iovdd_33 ? 1 : 0); + if (res < 0) + return res; + res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); if (res < 0) return res; @@ -1189,6 +1226,32 @@ static const struct regmap_range_cfg si5341_regmap_ranges[] = { }, }; +static int si5341_wait_device_ready(struct i2c_client *client) +{ + int count; + + /* Datasheet warns: Any attempt to read or write any register other + * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the + * NVM programming and may corrupt the register contents, as they are + * read from NVM. Note that this includes accesses to the PAGE register. + * Also: DEVICE_READY is available on every register page, so no page + * change is needed to read it. + * Do this outside regmap to avoid automatic PAGE register access. + * May take up to 300ms to complete. + */ + for (count = 0; count < 15; ++count) { + s32 result = i2c_smbus_read_byte_data(client, + SI5341_DEVICE_READY); + if (result < 0) + return result; + if (result == 0x0F) + return 0; + msleep(20); + } + dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); + return -EIO; +} + static const struct regmap_config si5341_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -1199,11 +1262,11 @@ static const struct regmap_config si5341_regmap_config = { .volatile_table = &si5341_regmap_volatile, }; -static int si5341_dt_parse_dt(struct i2c_client *client, - struct clk_si5341_output_config *config) +static int si5341_dt_parse_dt(struct clk_si5341 *data, + struct clk_si5341_output_config *config) { struct device_node *child; - struct device_node *np = client->dev.of_node; + struct device_node *np = data->i2c_client->dev.of_node; u32 num; u32 val; @@ -1212,13 +1275,13 @@ static int si5341_dt_parse_dt(struct i2c_client *client, for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { - dev_err(&client->dev, "missing reg property of %s\n", + dev_err(&data->i2c_client->dev, "missing reg property of %s\n", child->name); goto put_child; } if (num >= SI5341_MAX_NUM_OUTPUTS) { - dev_err(&client->dev, "invalid clkout %d\n", num); + dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num); goto put_child; } @@ -1237,7 +1300,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client, config[num].out_format_drv_bits |= 0xc0; break; default: - dev_err(&client->dev, + dev_err(&data->i2c_client->dev, "invalid silabs,format %u for %u\n", val, num); goto put_child; @@ -1250,7 +1313,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client, if (!of_property_read_u32(child, "silabs,common-mode", &val)) { if (val > 0xf) { - dev_err(&client->dev, + dev_err(&data->i2c_client->dev, "invalid silabs,common-mode %u\n", val); goto put_child; @@ -1261,7 +1324,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client, if (!of_property_read_u32(child, "silabs,amplitude", &val)) { if (val > 0xf) { - dev_err(&client->dev, + dev_err(&data->i2c_client->dev, "invalid silabs,amplitude %u\n", val); goto put_child; @@ -1278,6 +1341,34 @@ static int si5341_dt_parse_dt(struct i2c_client *client, config[num].always_on = of_property_read_bool(child, "always-on"); + + config[num].vdd_sel_bits = 0x08; + if (data->clk[num].vddo_reg) { + int vdd = regulator_get_voltage(data->clk[num].vddo_reg); + + switch (vdd) { + case 3300000: + config[num].vdd_sel_bits |= 0 << 4; + break; + case 1800000: + config[num].vdd_sel_bits |= 1 << 4; + break; + case 2500000: + config[num].vdd_sel_bits |= 2 << 4; + break; + default: + dev_err(&data->i2c_client->dev, + "unsupported vddo voltage %d for %s\n", + vdd, child->name); + goto put_child; + } + } else { + /* chip seems to default to 2.5V when not set */ + dev_warn(&data->i2c_client->dev, + "no regulator set, defaulting vdd_sel to 2.5V for %s\n", + child->name); + config[num].vdd_sel_bits |= 2 << 4; + } } return 0; @@ -1366,6 +1457,94 @@ static int si5341_clk_select_active_input(struct clk_si5341 *data) return res; } +static ssize_t input_present_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct clk_si5341 *data = dev_get_drvdata(dev); + u32 status; + int res = regmap_read(data->regmap, SI5341_STATUS, &status); + + if (res < 0) + return res; + res = !(status & SI5341_STATUS_LOSREF); + return snprintf(buf, PAGE_SIZE, "%d\n", res); +} +static DEVICE_ATTR_RO(input_present); + +static ssize_t input_present_sticky_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct clk_si5341 *data = dev_get_drvdata(dev); + u32 status; + int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); + + if (res < 0) + return res; + res = !(status & SI5341_STATUS_LOSREF); + return snprintf(buf, PAGE_SIZE, "%d\n", res); +} +static DEVICE_ATTR_RO(input_present_sticky); + +static ssize_t pll_locked_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct clk_si5341 *data = dev_get_drvdata(dev); + u32 status; + int res = regmap_read(data->regmap, SI5341_STATUS, &status); + + if (res < 0) + return res; + res = !(status & SI5341_STATUS_LOL); + return snprintf(buf, PAGE_SIZE, "%d\n", res); +} +static DEVICE_ATTR_RO(pll_locked); + +static ssize_t pll_locked_sticky_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct clk_si5341 *data = dev_get_drvdata(dev); + u32 status; + int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); + + if (res < 0) + return res; + res = !(status & SI5341_STATUS_LOL); + return snprintf(buf, PAGE_SIZE, "%d\n", res); +} +static DEVICE_ATTR_RO(pll_locked_sticky); + +static ssize_t clear_sticky_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct clk_si5341 *data = dev_get_drvdata(dev); + long val; + + if (kstrtol(buf, 10, &val)) + return -EINVAL; + if (val) { + int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); + + if (res < 0) + return res; + } + return count; +} +static DEVICE_ATTR_WO(clear_sticky); + +static const struct attribute *si5341_attributes[] = { + &dev_attr_input_present.attr, + &dev_attr_input_present_sticky.attr, + &dev_attr_pll_locked.attr, + &dev_attr_pll_locked_sticky.attr, + &dev_attr_clear_sticky.attr, + NULL +}; + static int si5341_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -1378,6 +1557,7 @@ static int si5341_probe(struct i2c_client *client, unsigned int i; struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; bool initialization_required; + u32 status; data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -1385,6 +1565,11 @@ static int si5341_probe(struct i2c_client *client, data->i2c_client = client; + /* Must be done before otherwise touching hardware */ + err = si5341_wait_device_ready(client); + if (err) + return err; + for (i = 0; i < SI5341_NUM_INPUTS; ++i) { input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); if (IS_ERR(input)) { @@ -1397,9 +1582,33 @@ static int si5341_probe(struct i2c_client *client, } } - err = si5341_dt_parse_dt(client, config); + for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { + char reg_name[10]; + + snprintf(reg_name, sizeof(reg_name), "vddo%d", i); + data->clk[i].vddo_reg = devm_regulator_get_optional( + &client->dev, reg_name); + if (IS_ERR(data->clk[i].vddo_reg)) { + err = PTR_ERR(data->clk[i].vddo_reg); + data->clk[i].vddo_reg = NULL; + if (err == -ENODEV) + continue; + goto cleanup; + } else { + err = regulator_enable(data->clk[i].vddo_reg); + if (err) { + dev_err(&client->dev, + "failed to enable %s regulator: %d\n", + reg_name, err); + data->clk[i].vddo_reg = NULL; + goto cleanup; + } + } + } + + err = si5341_dt_parse_dt(data, config); if (err) - return err; + goto cleanup; if (of_property_read_string(client->dev.of_node, "clock-output-names", &init.name)) @@ -1407,34 +1616,40 @@ static int si5341_probe(struct i2c_client *client, root_clock_name = init.name; data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); - if (IS_ERR(data->regmap)) - return PTR_ERR(data->regmap); + if (IS_ERR(data->regmap)) { + err = PTR_ERR(data->regmap); + goto cleanup; + } i2c_set_clientdata(client, data); err = si5341_probe_chip_id(data); if (err < 0) - return err; + goto cleanup; if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { initialization_required = true; } else { err = si5341_is_programmed_already(data); if (err < 0) - return err; + goto cleanup; initialization_required = !err; } + data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node, + "silabs,xaxb-ext-clk"); + data->iovdd_33 = of_property_read_bool(client->dev.of_node, + "silabs,iovdd-33"); if (initialization_required) { /* Populate the regmap cache in preparation for "cache only" */ err = si5341_read_settings(data); if (err < 0) - return err; + goto cleanup; err = si5341_send_preamble(data); if (err < 0) - return err; + goto cleanup; /* * We intend to send all 'final' register values in a single @@ -1447,19 +1662,19 @@ static int si5341_probe(struct i2c_client *client, err = si5341_write_multiple(data, si5341_reg_defaults, ARRAY_SIZE(si5341_reg_defaults)); if (err < 0) - return err; + goto cleanup; } /* Input must be up and running at this point */ err = si5341_clk_select_active_input(data); if (err < 0) - return err; + goto cleanup; if (initialization_required) { /* PLL configuration is required */ err = si5341_initialize_pll(data); if (err < 0) - return err; + goto cleanup; } /* Register the PLL */ @@ -1472,7 +1687,7 @@ static int si5341_probe(struct i2c_client *client, err = devm_clk_hw_register(&client->dev, &data->hw); if (err) { dev_err(&client->dev, "clock registration failed\n"); - return err; + goto cleanup; } init.num_parents = 1; @@ -1509,13 +1724,17 @@ static int si5341_probe(struct i2c_client *client, regmap_write(data->regmap, SI5341_OUT_CM(&data->clk[i]), config[i].out_cm_ampl_bits); + regmap_update_bits(data->regmap, + SI5341_OUT_MUX_SEL(&data->clk[i]), + SI5341_OUT_MUX_VDD_SEL_MASK, + config[i].vdd_sel_bits); } err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); kfree(init.name); /* clock framework made a copy of the name */ if (err) { dev_err(&client->dev, "output %u registration failed\n", i); - return err; + goto cleanup; } if (config[i].always_on) clk_prepare(data->clk[i].hw.clk); @@ -1525,7 +1744,7 @@ static int si5341_probe(struct i2c_client *client, data); if (err) { dev_err(&client->dev, "unable to add clk provider\n"); - return err; + goto cleanup; } if (initialization_required) { @@ -1533,11 +1752,33 @@ static int si5341_probe(struct i2c_client *client, regcache_cache_only(data->regmap, false); err = regcache_sync(data->regmap); if (err < 0) - return err; + goto cleanup; err = si5341_finalize_defaults(data); if (err < 0) - return err; + goto cleanup; + } + + /* wait for device to report input clock present and PLL lock */ + err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status, + !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)), + 10000, 250000); + if (err) { + dev_err(&client->dev, "Error waiting for input clock or PLL lock\n"); + goto cleanup; + } + + /* clear sticky alarm bits from initialization */ + err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); + if (err) { + dev_err(&client->dev, "unable to clear sticky status\n"); + goto cleanup; + } + + err = sysfs_create_files(&client->dev.kobj, si5341_attributes); + if (err) { + dev_err(&client->dev, "unable to create sysfs files\n"); + goto cleanup; } /* Free the names, clk framework makes copies */ @@ -1545,6 +1786,28 @@ static int si5341_probe(struct i2c_client *client, devm_kfree(&client->dev, (void *)synth_clock_names[i]); return 0; + +cleanup: + for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { + if (data->clk[i].vddo_reg) + regulator_disable(data->clk[i].vddo_reg); + } + return err; +} + +static int si5341_remove(struct i2c_client *client) +{ + struct clk_si5341 *data = i2c_get_clientdata(client); + int i; + + sysfs_remove_files(&client->dev.kobj, si5341_attributes); + + for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { + if (data->clk[i].vddo_reg) + regulator_disable(data->clk[i].vddo_reg); + } + + return 0; } static const struct i2c_device_id si5341_id[] = { @@ -1573,6 +1836,7 @@ static struct i2c_driver si5341_driver = { .of_match_table = clk_si5341_of_match, }, .probe = si5341_probe, + .remove = si5341_remove, .id_table = si5341_id, }; module_i2c_driver(si5341_driver); diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a875649df8b8..6adc625e79cb 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -10,8 +10,11 @@ #include #include #include +#include #include #include +#include +#include #include #include @@ -245,7 +248,7 @@ static const char * const dsi_src[] = { }; static const char * const rtc_src[] = { - "off", "ck_lse", "ck_lsi", "ck_hse_rtc" + "off", "ck_lse", "ck_lsi", "ck_hse" }; static const char * const mco1_src[] = { @@ -469,7 +472,7 @@ static const struct clk_ops mp1_gate_clk_ops = { .is_enabled = clk_gate_is_enabled, }; -static struct clk_hw *_get_stm32_mux(void __iomem *base, +static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base, const struct stm32_mux_cfg *cfg, spinlock_t *lock) { @@ -478,7 +481,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base, struct clk_hw *mux_hw; if (cfg->mmux) { - mmux = kzalloc(sizeof(*mmux), GFP_KERNEL); + mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL); if (!mmux) return ERR_PTR(-ENOMEM); @@ -493,7 +496,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base, cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; } else { - mux = kzalloc(sizeof(*mux), GFP_KERNEL); + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) return ERR_PTR(-ENOMEM); @@ -509,13 +512,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base, return mux_hw; } -static struct clk_hw *_get_stm32_div(void __iomem *base, +static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base, const struct stm32_div_cfg *cfg, spinlock_t *lock) { struct clk_divider *div; - div = kzalloc(sizeof(*div), GFP_KERNEL); + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); @@ -530,16 +533,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base, return &div->hw; } -static struct clk_hw * -_get_stm32_gate(void __iomem *base, - const struct stm32_gate_cfg *cfg, spinlock_t *lock) +static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base, + const struct stm32_gate_cfg *cfg, + spinlock_t *lock) { struct stm32_clk_mgate *mgate; struct clk_gate *gate; struct clk_hw *gate_hw; if (cfg->mgate) { - mgate = kzalloc(sizeof(*mgate), GFP_KERNEL); + mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL); if (!mgate) return ERR_PTR(-ENOMEM); @@ -554,7 +557,7 @@ _get_stm32_gate(void __iomem *base, gate_hw = &mgate->gate.hw; } else { - gate = kzalloc(sizeof(*gate), GFP_KERNEL); + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); if (!gate) return ERR_PTR(-ENOMEM); @@ -592,7 +595,7 @@ clk_stm32_register_gate_ops(struct device *dev, if (cfg->ops) init.ops = cfg->ops; - hw = _get_stm32_gate(base, cfg, lock); + hw = _get_stm32_gate(dev, base, cfg, lock); if (IS_ERR(hw)) return ERR_PTR(-ENOMEM); @@ -623,7 +626,7 @@ clk_stm32_register_composite(struct device *dev, gate_ops = NULL; if (cfg->mux) { - mux_hw = _get_stm32_mux(base, cfg->mux, lock); + mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock); if (!IS_ERR(mux_hw)) { mux_ops = &clk_mux_ops; @@ -634,7 +637,7 @@ clk_stm32_register_composite(struct device *dev, } if (cfg->div) { - div_hw = _get_stm32_div(base, cfg->div, lock); + div_hw = _get_stm32_div(dev, base, cfg->div, lock); if (!IS_ERR(div_hw)) { div_ops = &clk_divider_ops; @@ -645,7 +648,7 @@ clk_stm32_register_composite(struct device *dev, } if (cfg->gate) { - gate_hw = _get_stm32_gate(base, cfg->gate, lock); + gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock); if (!IS_ERR(gate_hw)) { gate_ops = &clk_gate_ops; @@ -731,6 +734,7 @@ struct stm32_pll_obj { spinlock_t *lock; void __iomem *reg; struct clk_hw hw; + struct clk_mux mux; }; #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw) @@ -745,6 +749,8 @@ struct stm32_pll_obj { #define FRAC_MASK 0x1FFF #define FRAC_SHIFT 3 #define FRACLE BIT(16) +#define PLL_MUX_SHIFT 0 +#define PLL_MUX_MASK 3 static int __pll_is_enabled(struct clk_hw *hw) { @@ -856,16 +862,29 @@ static int pll_is_enabled(struct clk_hw *hw) return ret; } +static u8 pll_get_parent(struct clk_hw *hw) +{ + struct stm32_pll_obj *clk_elem = to_pll(hw); + struct clk_hw *mux_hw = &clk_elem->mux.hw; + + __clk_hw_set_clk(mux_hw, hw); + + return clk_mux_ops.get_parent(mux_hw); +} + static const struct clk_ops pll_ops = { .enable = pll_enable, .disable = pll_disable, .recalc_rate = pll_recalc_rate, .is_enabled = pll_is_enabled, + .get_parent = pll_get_parent, }; static struct clk_hw *clk_register_pll(struct device *dev, const char *name, - const char *parent_name, + const char * const *parent_names, + int num_parents, void __iomem *reg, + void __iomem *mux_reg, unsigned long flags, spinlock_t *lock) { @@ -874,15 +893,22 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name, struct clk_hw *hw; int err; - element = kzalloc(sizeof(*element), GFP_KERNEL); + element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL); if (!element) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &pll_ops; init.flags = flags; - init.parent_names = &parent_name; - init.num_parents = 1; + init.parent_names = parent_names; + init.num_parents = num_parents; + + element->mux.lock = lock; + element->mux.reg = mux_reg; + element->mux.shift = PLL_MUX_SHIFT; + element->mux.mask = PLL_MUX_MASK; + element->mux.flags = CLK_MUX_READ_ONLY; + element->mux.reg = mux_reg; element->hw.init = &init; element->reg = reg; @@ -891,10 +917,8 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name, hw = &element->hw; err = clk_hw_register(dev, hw); - if (err) { - kfree(element); + if (err) return ERR_PTR(err); - } return hw; } @@ -1005,7 +1029,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, struct clk_hw *hw; int err; - tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL); + tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL); if (!tim_ker) return ERR_PTR(-ENOMEM); @@ -1023,16 +1047,56 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, hw = &tim_ker->hw; err = clk_hw_register(dev, hw); - if (err) { - kfree(tim_ker); + if (err) return ERR_PTR(err); - } return hw; } +/* The divider of RTC clock concerns only ck_hse clock */ +#define HSE_RTC 3 + +static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC)) + return clk_divider_ops.recalc_rate(hw, parent_rate); + + return parent_rate; +} + +static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC)) + return clk_divider_ops.set_rate(hw, rate, parent_rate); + + return parent_rate; +} + +static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + unsigned long best_parent_rate = req->best_parent_rate; + + if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) { + req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate); + req->best_parent_rate = best_parent_rate; + } else { + req->rate = best_parent_rate; + } + + return 0; +} + +static const struct clk_ops rtc_div_clk_ops = { + .recalc_rate = clk_divider_rtc_recalc_rate, + .set_rate = clk_divider_rtc_set_rate, + .determine_rate = clk_divider_rtc_determine_rate +}; + struct stm32_pll_cfg { u32 offset; + u32 muxoff; }; static struct clk_hw *_clk_register_pll(struct device *dev, @@ -1042,8 +1106,11 @@ static struct clk_hw *_clk_register_pll(struct device *dev, { struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; - return clk_register_pll(dev, cfg->name, cfg->parent_name, - base + stm_pll_cfg->offset, cfg->flags, lock); + return clk_register_pll(dev, cfg->name, cfg->parent_names, + cfg->num_parents, + base + stm_pll_cfg->offset, + base + stm_pll_cfg->muxoff, + cfg->flags, lock); } struct stm32_cktim_cfg { @@ -1153,14 +1220,16 @@ _clk_stm32_register_composite(struct device *dev, .func = _clk_hw_register_mux,\ } -#define PLL(_id, _name, _parent, _flags, _offset)\ +#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ {\ .id = _id,\ .name = _name,\ - .parent_name = _parent,\ - .flags = _flags,\ + .parent_names = _parents,\ + .num_parents = ARRAY_SIZE(_parents),\ + .flags = CLK_IGNORE_UNUSED | (_flags),\ .cfg = &(struct stm32_pll_cfg) {\ - .offset = _offset,\ + .offset = _offset_p,\ + .muxoff = _offset_mux,\ },\ .func = _clk_register_pll,\ } @@ -1243,6 +1312,10 @@ _clk_stm32_register_composite(struct device *dev, _STM32_DIV(_div_offset, _div_shift, _div_width,\ _div_flags, _div_table, NULL)\ +#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\ + _STM32_DIV(_div_offset, _div_shift, _div_width,\ + _div_flags, _div_table, &rtc_div_clk_ops) + #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ .mux = &(struct stm32_mux_cfg) {\ &(struct mux_cfg) {\ @@ -1657,36 +1730,26 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = { }; static const struct clock_config stm32mp1_clock_cfg[] = { - /* Oscillator divider */ - DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO, - RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY), - /* External / Internal Oscillators */ GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0), /* ck_csi is used by IO compensation and should be critical */ GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL, RCC_OCENSETR, 4, 0), - GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0), + COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0, + _GATE_MP1(RCC_OCENSETR, 0, 0), + _NO_MUX, + _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO | + CLK_DIVIDER_READ_ONLY, NULL)), GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0), GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0), FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2), - /* ref clock pll */ - MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR, - 0, 2, CLK_MUX_READ_ONLY), - - MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR, - 0, 2, CLK_MUX_READ_ONLY), - - MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR, - 0, 2, CLK_MUX_READ_ONLY), - /* PLLs */ - PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR), - PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR), - PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR), - PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR), + PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR), + PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR), + PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR), + PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR), /* ODF */ COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0, @@ -1965,13 +2028,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), /* RTC clock */ - DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0), - - COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE | - CLK_SET_RATE_PARENT, + COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE, _GATE(RCC_BDCR, 20, 0), _MUX(RCC_BDCR, 16, 2, 0), - _NO_DIV), + _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)), /* MCO clocks */ COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE | @@ -1996,16 +2056,76 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)), }; -struct stm32_clock_match_data { +static const u32 stm32mp1_clock_secured[] = { + CK_HSE, + CK_HSI, + CK_CSI, + CK_LSI, + CK_LSE, + PLL1, + PLL2, + PLL1_P, + PLL2_P, + PLL2_Q, + PLL2_R, + CK_MPU, + CK_AXI, + SPI6, + I2C4, + I2C6, + USART1, + RTCAPB, + TZC1, + TZC2, + TZPC, + IWDG1, + BSEC, + STGEN, + GPIOZ, + CRYP1, + HASH1, + RNG1, + BKPSRAM, + RNG1_K, + STGEN_K, + SPI6_K, + I2C4_K, + I2C6_K, + USART1_K, + RTC, +}; + +static bool stm32_check_security(const struct clock_config *cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++) + if (cfg->id == stm32mp1_clock_secured[i]) + return true; + return false; +} + +struct stm32_rcc_match_data { const struct clock_config *cfg; unsigned int num; unsigned int maxbinding; + u32 clear_offset; + bool (*check_security)(const struct clock_config *cfg); }; -static struct stm32_clock_match_data stm32mp1_data = { +static struct stm32_rcc_match_data stm32mp1_data = { .cfg = stm32mp1_clock_cfg, .num = ARRAY_SIZE(stm32mp1_clock_cfg), .maxbinding = STM32MP1_LAST_CLK, + .clear_offset = RCC_CLR, +}; + +static struct stm32_rcc_match_data stm32mp1_data_secure = { + .cfg = stm32mp1_clock_cfg, + .num = ARRAY_SIZE(stm32mp1_clock_cfg), + .maxbinding = STM32MP1_LAST_CLK, + .clear_offset = RCC_CLR, + .check_security = &stm32_check_security }; static const struct of_device_id stm32mp1_match_data[] = { @@ -2013,8 +2133,13 @@ static const struct of_device_id stm32mp1_match_data[] = { .compatible = "st,stm32mp1-rcc", .data = &stm32mp1_data, }, + { + .compatible = "st,stm32mp1-rcc-secure", + .data = &stm32mp1_data_secure, + }, { } }; +MODULE_DEVICE_TABLE(of, stm32mp1_match_data); static int stm32_register_hw_clk(struct device *dev, struct clk_hw_onecell_data *clk_data, @@ -2040,28 +2165,126 @@ static int stm32_register_hw_clk(struct device *dev, return 0; } -static int stm32_rcc_init(struct device_node *np, - void __iomem *base, - const struct of_device_id *match_data) -{ - struct clk_hw_onecell_data *clk_data; - struct clk_hw **hws; - const struct of_device_id *match; - const struct stm32_clock_match_data *data; - int err, n, max_binding; +#define STM32_RESET_ID_MASK GENMASK(15, 0) - match = of_match_node(match_data, np); - if (!match) { - pr_err("%s: match data not found\n", __func__); - return -ENODEV; +struct stm32_reset_data { + /* reset lock */ + spinlock_t lock; + struct reset_controller_dev rcdev; + void __iomem *membase; + u32 clear_offset; +}; + +static inline struct stm32_reset_data * +to_stm32_reset_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct stm32_reset_data, rcdev); +} + +static int stm32_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct stm32_reset_data *data = to_stm32_reset_data(rcdev); + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + + if (data->clear_offset) { + void __iomem *addr; + + addr = data->membase + (bank * reg_width); + if (!assert) + addr += data->clear_offset; + + writel(BIT(offset), addr); + + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase + (bank * reg_width)); + + if (assert) + reg |= BIT(offset); + else + reg &= ~BIT(offset); + + writel(reg, data->membase + (bank * reg_width)); + + spin_unlock_irqrestore(&data->lock, flags); } + return 0; +} + +static int stm32_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return stm32_reset_update(rcdev, id, true); +} + +static int stm32_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return stm32_reset_update(rcdev, id, false); +} + +static int stm32_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct stm32_reset_data *data = to_stm32_reset_data(rcdev); + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + u32 reg; + + reg = readl(data->membase + (bank * reg_width)); + + return !!(reg & BIT(offset)); +} + +static const struct reset_control_ops stm32_reset_ops = { + .assert = stm32_reset_assert, + .deassert = stm32_reset_deassert, + .status = stm32_reset_status, +}; + +static int stm32_rcc_reset_init(struct device *dev, void __iomem *base, + const struct of_device_id *match) +{ + const struct stm32_rcc_match_data *data = match->data; + struct stm32_reset_data *reset_data = NULL; + data = match->data; + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reset_data->membase = base; + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.ops = &stm32_reset_ops; + reset_data->rcdev.of_node = dev_of_node(dev); + reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK; + reset_data->clear_offset = data->clear_offset; + + return reset_controller_register(&reset_data->rcdev); +} + +static int stm32_rcc_clock_init(struct device *dev, void __iomem *base, + const struct of_device_id *match) +{ + const struct stm32_rcc_match_data *data = match->data; + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + int err, n, max_binding; + max_binding = data->maxbinding; - clk_data = kzalloc(struct_size(clk_data, hws, max_binding), - GFP_KERNEL); + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), + GFP_KERNEL); if (!clk_data) return -ENOMEM; @@ -2073,36 +2296,139 @@ static int stm32_rcc_init(struct device_node *np, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { - err = stm32_register_hw_clk(NULL, clk_data, base, &rlock, + if (data->check_security && data->check_security(&data->cfg[n])) + continue; + + err = stm32_register_hw_clk(dev, clk_data, base, &rlock, &data->cfg[n]); if (err) { - pr_err("%s: can't register %s\n", __func__, - data->cfg[n].name); - - kfree(clk_data); + dev_err(dev, "Can't register clk %s: %d\n", + data->cfg[n].name, err); return err; } } - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); + return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data); } -static void stm32mp1_rcc_init(struct device_node *np) +static int stm32_rcc_init(struct device *dev, void __iomem *base, + const struct of_device_id *match_data) +{ + const struct of_device_id *match; + int err; + + match = of_match_node(match_data, dev_of_node(dev)); + if (!match) { + dev_err(dev, "match data not found\n"); + return -ENODEV; + } + + /* RCC Reset Configuration */ + err = stm32_rcc_reset_init(dev, base, match); + if (err) { + pr_err("stm32mp1 reset failed to initialize\n"); + return err; + } + + /* RCC Clock Configuration */ + err = stm32_rcc_clock_init(dev, base, match); + if (err) { + pr_err("stm32mp1 clock failed to initialize\n"); + return err; + } + + return 0; +} + +static int stm32mp1_rcc_init(struct device *dev) { void __iomem *base; + int ret; - base = of_iomap(np, 0); + base = of_iomap(dev_of_node(dev), 0); if (!base) { - pr_err("%pOFn: unable to map resource", np); - of_node_put(np); - return; + pr_err("%pOFn: unable to map resource", dev_of_node(dev)); + ret = -ENOMEM; + goto out; } - if (stm32_rcc_init(np, base, stm32mp1_match_data)) { - iounmap(base); - of_node_put(np); + ret = stm32_rcc_init(dev, base, stm32mp1_match_data); + +out: + if (ret) { + if (base) + iounmap(base); + + of_node_put(dev_of_node(dev)); } + + return ret; } -CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init); +static int get_clock_deps(struct device *dev) +{ + static const char * const clock_deps_name[] = { + "hsi", "hse", "csi", "lsi", "lse", + }; + size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name); + struct clk **clk_deps; + int i; + + clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL); + if (!clk_deps) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) { + struct clk *clk = of_clk_get_by_name(dev_of_node(dev), + clock_deps_name[i]); + + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) + return PTR_ERR(clk); + } else { + /* Device gets a reference count on the clock */ + clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk)); + clk_put(clk); + } + } + + return 0; +} + +static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret = get_clock_deps(dev); + + if (!ret) + ret = stm32mp1_rcc_init(dev); + + return ret; +} + +static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *child, *np = dev_of_node(dev); + + for_each_available_child_of_node(np, child) + of_clk_del_provider(child); + + return 0; +} + +static struct platform_driver stm32mp1_rcc_clocks_driver = { + .driver = { + .name = "stm32mp1_rcc", + .of_match_table = stm32mp1_match_data, + }, + .probe = stm32mp1_rcc_clocks_probe, + .remove = stm32mp1_rcc_clocks_remove, +}; + +static int __init stm32mp1_clocks_init(void) +{ + return platform_driver_register(&stm32mp1_rcc_clocks_driver); +} +core_initcall(stm32mp1_clocks_init); diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 344cd6c61188..3c737742c2a9 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -69,7 +69,10 @@ #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) #define VC5_RC_CONTROL0 0x1e #define VC5_RC_CONTROL1 0x1f -/* Register 0x20 is factory reserved */ + +/* These registers are named "Unused Factory Reserved Registers" */ +#define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10)) +#define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync bit */ /* Output divider control for divider 1,2,3,4 */ #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) @@ -87,7 +90,6 @@ #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) -/* Registers 0x30, 0x40, 0x50 are factory reserved */ /* Clock control register for clock 1,2 */ #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) @@ -140,6 +142,8 @@ #define VC5_HAS_INTERNAL_XTAL BIT(0) /* chip has PFD requency doubler */ #define VC5_HAS_PFD_FREQ_DBL BIT(1) +/* chip has bits to disable FOD sync */ +#define VC5_HAS_BYPASS_SYNC_BIT BIT(2) /* Supported IDT VC5 models. */ enum vc5_model { @@ -581,6 +585,23 @@ static int vc5_clk_out_prepare(struct clk_hw *hw) unsigned int src; int ret; + /* + * When enabling a FOD, all currently enabled FODs are briefly + * stopped in order to synchronize all of them. This causes a clock + * disruption to any unrelated chips that might be already using + * other clock outputs. Bypass the sync feature to avoid the issue, + * which is possible on the VersaClock 6E family via reserved + * registers. + */ + if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { + ret = regmap_update_bits(vc5->regmap, + VC5_RESERVED_X0(hwdata->num), + VC5_RESERVED_X0_BYPASS_SYNC, + VC5_RESERVED_X0_BYPASS_SYNC); + if (ret) + return ret; + } + /* * If the input mux is disabled, enable it first and * select source from matching FOD. @@ -1166,7 +1187,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = { .model = IDT_VC6_5P49V6965, .clk_fod_cnt = 4, .clk_out_cnt = 5, - .flags = 0, + .flags = VC5_HAS_BYPASS_SYNC_BIT, }; static const struct i2c_device_id vc5_id[] = { diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c index 0f2e3fcf0f19..67f601a41023 100644 --- a/drivers/clk/clkdev.c +++ b/drivers/clk/clkdev.c @@ -190,34 +190,6 @@ vclkdev_create(struct clk_hw *hw, const char *con_id, const char *dev_fmt, return cl; } -struct clk_lookup * __ref -clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(__clk_get_hw(clk), con_id, dev_fmt, ap); - va_end(ap); - - return cl; -} -EXPORT_SYMBOL(clkdev_alloc); - -struct clk_lookup * -clkdev_hw_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(hw, con_id, dev_fmt, ap); - va_end(ap); - - return cl; -} -EXPORT_SYMBOL(clkdev_hw_alloc); - /** * clkdev_create - allocate and add a clkdev lookup structure * @clk: struct clk to associate with all clk_lookups diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index 6a9e93a0bb95..5ecc37aaa118 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -15,6 +15,13 @@ config COMMON_CLK_HI3519 help Build the clock driver for hi3519. +config COMMON_CLK_HI3559A + bool "Hi3559A Clock Driver" + depends on ARCH_HISI || COMPILE_TEST + default ARCH_HISI + help + Build the clock driver for hi3559a. + config COMMON_CLK_HI3660 bool "Hi3660 Clock Driver" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index b2441b99f3d5..2978e56cb876 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o +obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c new file mode 100644 index 000000000000..b1f19c43b558 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Hisilicon Hi3559A clock driver + * + * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. + * + * Author: Dongjiu Geng + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "crg.h" +#include "reset.h" + +#define CRG_BASE_ADDR 0x18020000 +#define PLL_MASK_WIDTH 24 + +struct hi3559av100_pll_clock { + u32 id; + const char *name; + const char *parent_name; + const u32 ctrl_reg1; + const u8 frac_shift; + const u8 frac_width; + const u8 postdiv1_shift; + const u8 postdiv1_width; + const u8 postdiv2_shift; + const u8 postdiv2_width; + const u32 ctrl_reg2; + const u8 fbdiv_shift; + const u8 fbdiv_width; + const u8 refdiv_shift; + const u8 refdiv_width; +}; + +struct hi3559av100_clk_pll { + struct clk_hw hw; + u32 id; + void __iomem *ctrl_reg1; + u8 frac_shift; + u8 frac_width; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + void __iomem *ctrl_reg2; + u8 fbdiv_shift; + u8 fbdiv_width; + u8 refdiv_shift; + u8 refdiv_width; +}; + +/* soc clk config */ +static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = { + { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, }, + { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, }, + { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, }, + { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, }, + { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, }, + { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, }, + { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, }, + { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, }, + { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, }, + { HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, }, + { HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, }, + { HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, }, + { HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, }, + { HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, }, + { HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, }, + { HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, }, + { HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, }, + { HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, }, + { HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, }, + { HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, }, + { HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, }, + { HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, }, + { HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, }, + { HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, }, + { HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, }, + { HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, }, + { HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, }, + { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, }, + { HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, }, + { HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, }, + { HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, }, + { HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, }, + { HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, }, + { HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, }, + { HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, }, +}; + + +static const char *fmc_mux_p[] __initconst = { + "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m" +}; + +static const char *mmc_mux_p[] __initconst = { + "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k" +}; + +static const char *sysapb_mux_p[] __initconst = { + "24m", "50m", +}; + +static const char *sysbus_mux_p[] __initconst = { + "24m", "300m" +}; + +static const char *uart_mux_p[] __initconst = { "50m", "24m", "3m" }; + +static const char *a73_clksel_mux_p[] __initconst = { + "24m", "apll", "1000m" +}; + +static const u32 fmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; +static const u32 mmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; +static const u32 sysapb_mux_table[] = { 0, 1 }; +static const u32 sysbus_mux_table[] = { 0, 1 }; +static const u32 uart_mux_table[] = { 0, 1, 2 }; +static const u32 a73_clksel_mux_table[] = { 0, 1, 2 }; + +static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = { + { + HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, + }, + { + HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, + }, + { + HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, + }, + + { + HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, + }, + + { + HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table, + }, + + { + HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p), + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table + }, + + { + HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p), + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table + }, + + { + HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table + }, + + { + HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p), + CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table + }, +}; + +static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = { + { + HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux", + CLK_SET_RATE_PARENT, 0x170, 1, 0, + }, + { + HI3559AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux", + CLK_SET_RATE_PARENT, 0x1a8, 28, 0, + }, + { + HI3559AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux", + CLK_SET_RATE_PARENT, 0x1ec, 28, 0, + }, + { + HI3559AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux", + CLK_SET_RATE_PARENT, 0x214, 28, 0, + }, + { + HI3559AV100_MMC3_CLK, "clk_mmc3", "mmc3_mux", + CLK_SET_RATE_PARENT, 0x23c, 28, 0, + }, + { + HI3559AV100_UART0_CLK, "clk_uart0", "uart_mux", + CLK_SET_RATE_PARENT, 0x198, 23, 0, + }, + { + HI3559AV100_UART1_CLK, "clk_uart1", "uart_mux", + CLK_SET_RATE_PARENT, 0x198, 24, 0, + }, + { + HI3559AV100_UART2_CLK, "clk_uart2", "uart_mux", + CLK_SET_RATE_PARENT, 0x198, 25, 0, + }, + { + HI3559AV100_UART3_CLK, "clk_uart3", "uart_mux", + CLK_SET_RATE_PARENT, 0x198, 26, 0, + }, + { + HI3559AV100_UART4_CLK, "clk_uart4", "uart_mux", + CLK_SET_RATE_PARENT, 0x198, 27, 0, + }, + { + HI3559AV100_ETH_CLK, "clk_eth", NULL, + CLK_SET_RATE_PARENT, 0x0174, 1, 0, + }, + { + HI3559AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL, + CLK_SET_RATE_PARENT, 0x0174, 5, 0, + }, + { + HI3559AV100_ETH1_CLK, "clk_eth1", NULL, + CLK_SET_RATE_PARENT, 0x0174, 3, 0, + }, + { + HI3559AV100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL, + CLK_SET_RATE_PARENT, 0x0174, 7, 0, + }, + { + HI3559AV100_I2C0_CLK, "clk_i2c0", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 16, 0, + }, + { + HI3559AV100_I2C1_CLK, "clk_i2c1", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 17, 0, + }, + { + HI3559AV100_I2C2_CLK, "clk_i2c2", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 18, 0, + }, + { + HI3559AV100_I2C3_CLK, "clk_i2c3", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 19, 0, + }, + { + HI3559AV100_I2C4_CLK, "clk_i2c4", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 20, 0, + }, + { + HI3559AV100_I2C5_CLK, "clk_i2c5", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 21, 0, + }, + { + HI3559AV100_I2C6_CLK, "clk_i2c6", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 22, 0, + }, + { + HI3559AV100_I2C7_CLK, "clk_i2c7", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 23, 0, + }, + { + HI3559AV100_I2C8_CLK, "clk_i2c8", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 24, 0, + }, + { + HI3559AV100_I2C9_CLK, "clk_i2c9", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 25, 0, + }, + { + HI3559AV100_I2C10_CLK, "clk_i2c10", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 26, 0, + }, + { + HI3559AV100_I2C11_CLK, "clk_i2c11", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 27, 0, + }, + { + HI3559AV100_SPI0_CLK, "clk_spi0", "100m", + CLK_SET_RATE_PARENT, 0x0198, 16, 0, + }, + { + HI3559AV100_SPI1_CLK, "clk_spi1", "100m", + CLK_SET_RATE_PARENT, 0x0198, 17, 0, + }, + { + HI3559AV100_SPI2_CLK, "clk_spi2", "100m", + CLK_SET_RATE_PARENT, 0x0198, 18, 0, + }, + { + HI3559AV100_SPI3_CLK, "clk_spi3", "100m", + CLK_SET_RATE_PARENT, 0x0198, 19, 0, + }, + { + HI3559AV100_SPI4_CLK, "clk_spi4", "100m", + CLK_SET_RATE_PARENT, 0x0198, 20, 0, + }, + { + HI3559AV100_SPI5_CLK, "clk_spi5", "100m", + CLK_SET_RATE_PARENT, 0x0198, 21, 0, + }, + { + HI3559AV100_SPI6_CLK, "clk_spi6", "100m", + CLK_SET_RATE_PARENT, 0x0198, 22, 0, + }, + { + HI3559AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL, + CLK_SET_RATE_PARENT, 0x16c, 6, 0, + }, + { + HI3559AV100_EDMAC_CLK, "clk_edmac", NULL, + CLK_SET_RATE_PARENT, 0x16c, 5, 0, + }, + { + HI3559AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL, + CLK_SET_RATE_PARENT, 0x16c, 9, 0, + }, + { + HI3559AV100_EDMAC1_CLK, "clk_edmac1", NULL, + CLK_SET_RATE_PARENT, 0x16c, 8, 0, + }, + { + HI3559AV100_VDMAC_CLK, "clk_vdmac", NULL, + CLK_SET_RATE_PARENT, 0x14c, 5, 0, + }, +}; + +static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = { + { + HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3, + 0x4, 0, 12, 12, 6 + }, + { + HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3, + 0x24, 0, 12, 12, 6 + }, +}; + +#define to_pll_clk(_hw) container_of(_hw, struct hi3559av100_clk_pll, hw) +static void hi3559av100_calc_pll(u32 *frac_val, u32 *postdiv1_val, + u32 *postdiv2_val, + u32 *fbdiv_val, u32 *refdiv_val, u64 rate) +{ + u64 rem; + + *postdiv1_val = 2; + *postdiv2_val = 1; + + rate = rate * ((*postdiv1_val) * (*postdiv2_val)); + + *frac_val = 0; + rem = do_div(rate, 1000000); + rem = do_div(rate, PLL_MASK_WIDTH); + *fbdiv_val = rate; + *refdiv_val = 1; + rem = rem * (1 << PLL_MASK_WIDTH); + do_div(rem, PLL_MASK_WIDTH); + *frac_val = rem; +} + +static int clk_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct hi3559av100_clk_pll *clk = to_pll_clk(hw); + u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val; + u32 val; + + postdiv1_val = postdiv2_val = 0; + + hi3559av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val, + &fbdiv_val, &refdiv_val, (u64)rate); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift); + + val |= frac_val << clk->frac_shift; + val |= postdiv1_val << clk->postdiv1_shift; + val |= postdiv2_val << clk->postdiv2_shift; + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); + + val |= fbdiv_val << clk->fbdiv_shift; + val |= refdiv_val << clk->refdiv_shift; + writel_relaxed(val, clk->ctrl_reg2); + + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct hi3559av100_clk_pll *clk = to_pll_clk(hw); + u64 frac_val, fbdiv_val, refdiv_val; + u32 postdiv1_val, postdiv2_val; + u32 val; + u64 tmp, rate; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->frac_shift; + val &= ((1 << clk->frac_width) - 1); + frac_val = val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->postdiv1_shift; + val &= ((1 << clk->postdiv1_width) - 1); + postdiv1_val = val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->postdiv2_shift; + val &= ((1 << clk->postdiv2_width) - 1); + postdiv2_val = val; + + val = readl_relaxed(clk->ctrl_reg2); + val = val >> clk->fbdiv_shift; + val &= ((1 << clk->fbdiv_width) - 1); + fbdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg2); + val = val >> clk->refdiv_shift; + val &= ((1 << clk->refdiv_width) - 1); + refdiv_val = val; + + /* rate = 24000000 * (fbdiv + frac / (1<<24) ) / refdiv */ + rate = 0; + tmp = 24000000 * fbdiv_val + (24000000 * frac_val) / (1 << 24); + rate += tmp; + do_div(rate, refdiv_val); + do_div(rate, postdiv1_val * postdiv2_val); + + return rate; +} + +static const struct clk_ops hisi_clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .recalc_rate = clk_pll_recalc_rate, +}; + +static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, + int nums, struct hisi_clock_data *data, struct device *dev) +{ + void __iomem *base = data->base; + struct hi3559av100_clk_pll *p_clk = NULL; + struct clk *clk = NULL; + struct clk_init_data init; + int i; + + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + + if (!p_clk) + return; + + for (i = 0; i < nums; i++) { + init.name = clks[i].name; + init.flags = 0; + init.parent_names = + (clks[i].parent_name ? &clks[i].parent_name : NULL); + init.num_parents = (clks[i].parent_name ? 1 : 0); + init.ops = &hisi_clk_pll_ops; + + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1; + p_clk->frac_shift = clks[i].frac_shift; + p_clk->frac_width = clks[i].frac_width; + p_clk->postdiv1_shift = clks[i].postdiv1_shift; + p_clk->postdiv1_width = clks[i].postdiv1_width; + p_clk->postdiv2_shift = clks[i].postdiv2_shift; + p_clk->postdiv2_width = clks[i].postdiv2_width; + + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2; + p_clk->fbdiv_shift = clks[i].fbdiv_shift; + p_clk->fbdiv_width = clks[i].fbdiv_width; + p_clk->refdiv_shift = clks[i].refdiv_shift; + p_clk->refdiv_width = clks[i].refdiv_width; + p_clk->hw.init = &init; + + clk = clk_register(NULL, &p_clk->hw); + if (IS_ERR(clk)) { + devm_kfree(dev, p_clk); + dev_err(dev, "%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + + data->clk_data.clks[clks[i].id] = clk; + p_clk++; + } +} + +static __init struct hisi_clock_data *hi3559av100_clk_register( + struct platform_device *pdev) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data = hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg, + ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); + if (ret) + return ERR_PTR(ret); + + hisi_clk_register_pll(hi3559av100_pll_clks, + ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); + + ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg, + ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); + if (ret) + goto unregister_fixed_rate; + + ret = hisi_clk_register_gate(hi3559av100_gate_clks, + ARRAY_SIZE(hi3559av100_gate_clks), clk_data); + if (ret) + goto unregister_mux; + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(hi3559av100_gate_clks, + ARRAY_SIZE(hi3559av100_gate_clks), clk_data); +unregister_mux: + hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, + ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, + ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); + return ERR_PTR(ret); +} + +static __init void hi3559av100_clk_unregister(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(hi3559av100_gate_clks, + ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data); + hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, + ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data); + hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, + ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data); +} + +static const struct hisi_crg_funcs hi3559av100_crg_funcs = { + .register_clks = hi3559av100_clk_register, + .unregister_clks = hi3559av100_clk_unregister, +}; + +static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] + __initdata = { + { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, }, + { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, }, + { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, }, + { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, }, + { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, }, + { HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, }, +}; + +/* shub mux clk */ +static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3}; +static const char *shub_source_clk_mux_p[] __initconst = { + "clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL" +}; + +static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3}; +static const char *shub_uart_source_clk_mux_p[] __initconst = { + "clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M" +}; + +static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = { + { + HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p, + ARRAY_SIZE(shub_source_clk_mux_p), + 0, 0x0, 0, 2, 0, shub_source_clk_mux_table, + }, + + { + HI3559AV100_SHUB_UART_SOURCE_CLK, "shub_uart_source_clk", + shub_uart_source_clk_mux_p, ARRAY_SIZE(shub_uart_source_clk_mux_p), + 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table, + }, +}; + + +/* shub div clk */ +static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}}; +static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}}; + +static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = { + { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, + CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table, + }, + { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2, + CLK_DIVIDER_ALLOW_ZERO, shub_uart_div_clk_table, + }, +}; + +/* shub gate clk */ +static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = { + { + HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk", + 0, 0x20, 1, 0, + }, + { + HI3559AV100_SHUB_SPI1_CLK, "clk_shub_spi1", "clk_spi_clk", + 0, 0x20, 5, 0, + }, + { + HI3559AV100_SHUB_SPI2_CLK, "clk_shub_spi2", "clk_spi_clk", + 0, 0x20, 9, 0, + }, + + { + HI3559AV100_SHUB_UART0_CLK, "clk_shub_uart0", "shub_uart_source_clk", + 0, 0x1c, 1, 0, + }, + { + HI3559AV100_SHUB_UART1_CLK, "clk_shub_uart1", "shub_uart_source_clk", + 0, 0x1c, 5, 0, + }, + { + HI3559AV100_SHUB_UART2_CLK, "clk_shub_uart2", "shub_uart_source_clk", + 0, 0x1c, 9, 0, + }, + { + HI3559AV100_SHUB_UART3_CLK, "clk_shub_uart3", "shub_uart_source_clk", + 0, 0x1c, 13, 0, + }, + { + HI3559AV100_SHUB_UART4_CLK, "clk_shub_uart4", "shub_uart_source_clk", + 0, 0x1c, 17, 0, + }, + { + HI3559AV100_SHUB_UART5_CLK, "clk_shub_uart5", "shub_uart_source_clk", + 0, 0x1c, 21, 0, + }, + { + HI3559AV100_SHUB_UART6_CLK, "clk_shub_uart6", "shub_uart_source_clk", + 0, 0x1c, 25, 0, + }, + + { + HI3559AV100_SHUB_EDMAC_CLK, "clk_shub_dmac", "shub_clk", + 0, 0x24, 4, 0, + }, +}; + +static int hi3559av100_shub_default_clk_set(void) +{ + void __iomem *crg_base; + unsigned int val; + + crg_base = ioremap(CRG_BASE_ADDR, SZ_4K); + + /* SSP: 192M/2 */ + val = readl_relaxed(crg_base + 0x20); + val |= (0x2 << 24); + writel_relaxed(val, crg_base + 0x20); + + /* UART: 192M/8 */ + val = readl_relaxed(crg_base + 0x1C); + val |= (0x1 << 28); + writel_relaxed(val, crg_base + 0x1C); + + iounmap(crg_base); + crg_base = NULL; + + return 0; +} + +static __init struct hisi_clock_data *hi3559av100_shub_clk_register( + struct platform_device *pdev) +{ + struct hisi_clock_data *clk_data = NULL; + int ret; + + hi3559av100_shub_default_clk_set(); + + clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks, + ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks, + ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); + if (ret) + goto unregister_fixed_rate; + + ret = hisi_clk_register_divider(hi3559av100_shub_div_clks, + ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); + if (ret) + goto unregister_mux; + + ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks, + ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); + if (ret) + goto unregister_factor; + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, + ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); +unregister_factor: + hisi_clk_unregister_divider(hi3559av100_shub_div_clks, + ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); +unregister_mux: + hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, + ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, + ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); + return ERR_PTR(ret); +} + +static __init void hi3559av100_shub_clk_unregister(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, + ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data); + hisi_clk_unregister_divider(hi3559av100_shub_div_clks, + ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data); + hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, + ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data); + hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, + ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data); +} + +static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = { + .register_clks = hi3559av100_shub_clk_register, + .unregister_clks = hi3559av100_shub_clk_unregister, +}; + +static const struct of_device_id hi3559av100_crg_match_table[] = { + { + .compatible = "hisilicon,hi3559av100-clock", + .data = &hi3559av100_crg_funcs + }, + { + .compatible = "hisilicon,hi3559av100-shub-clock", + .data = &hi3559av100_shub_crg_funcs + }, + { } +}; +MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table); + +static int hi3559av100_crg_probe(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg; + + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); + if (!crg) + return -ENOMEM; + + crg->funcs = of_device_get_match_data(&pdev->dev); + if (!crg->funcs) + return -ENOENT; + + crg->rstc = hisi_reset_init(pdev); + if (!crg->rstc) + return -ENOMEM; + + crg->clk_data = crg->funcs->register_clks(pdev); + if (IS_ERR(crg->clk_data)) { + hisi_reset_exit(crg->rstc); + return PTR_ERR(crg->clk_data); + } + + platform_set_drvdata(pdev, crg); + return 0; +} + +static int hi3559av100_crg_remove(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + hisi_reset_exit(crg->rstc); + crg->funcs->unregister_clks(pdev); + return 0; +} + +static struct platform_driver hi3559av100_crg_driver = { + .probe = hi3559av100_crg_probe, + .remove = hi3559av100_crg_remove, + .driver = { + .name = "hi3559av100-clock", + .of_match_table = hi3559av100_crg_match_table, + }, +}; + +static int __init hi3559av100_crg_init(void) +{ + return platform_driver_register(&hi3559av100_crg_driver); +} +core_initcall(hi3559av100_crg_init); + +static void __exit hi3559av100_crg_exit(void) +{ + platform_driver_unregister(&hi3559av100_crg_driver); +} +module_exit(hi3559av100_crg_exit); + + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver"); diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93599..9361fba7cd4c 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -162,7 +162,7 @@ int hisi_clk_register_mux(const struct hisi_mux_clock *clks, clks[i].num_parents, clks[i].flags, base + clks[i].offset, clks[i].shift, mask, clks[i].mux_flags, - clks[i].table, &hisi_clk_lock); + (u32 *)clks[i].table, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 61cbd90d1213..7a9b42e1b027 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -50,7 +50,7 @@ struct hisi_mux_clock { u8 shift; u8 width; u8 mux_flags; - u32 *table; + const u32 *table; const char *alias; }; diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index dd6a737d060b..c24a2acbfa56 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o -clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o +clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \ + clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o obj-$(CONFIG_CLK_IMX1) += clk-imx1.o diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index e39c9c907c38..12837304545d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); - hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1); hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index b08019e1faf9..c491bc9c61ce 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); /* SYS PLL1 fixed output */ - hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9); - hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11); - hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13); - hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15); - hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17); - hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19); - hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21); - hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23); - hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25); - - hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20); - hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10); - hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8); - hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6); - hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5); - hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4); - hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3); - hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2); - hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1); + hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20); + hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10); + hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8); + hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6); + hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5); + hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4); + hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3); + hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2); + hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1); /* SYS PLL2 fixed output */ - hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9); - hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11); - hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13); - hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15); - hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17); - hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19); - hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21); - hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23); - hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25); - - hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20); - hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10); - hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8); - hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6); - hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5); - hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4); - hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3); - hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2); - hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1); + hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20); + hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10); + hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8); + hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6); + hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5); + hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4); + hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3); + hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2); + hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1); hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3); hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3); diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c new file mode 100644 index 000000000000..87e0b6ac027e --- /dev/null +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + * Dong Aisheng + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static const u32 imx8qm_clk_scu_rsrc_table[] = { + IMX_SC_R_A53, + IMX_SC_R_A72, + IMX_SC_R_DC_0_VIDEO0, + IMX_SC_R_DC_0_VIDEO1, + IMX_SC_R_DC_0, + IMX_SC_R_DC_0_PLL_0, + IMX_SC_R_DC_0_PLL_1, + IMX_SC_R_DC_1_VIDEO0, + IMX_SC_R_DC_1_VIDEO1, + IMX_SC_R_DC_1, + IMX_SC_R_DC_1_PLL_0, + IMX_SC_R_DC_1_PLL_1, + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_UART_4, + IMX_SC_R_EMVSIM_0, + IMX_SC_R_EMVSIM_1, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_I2C_4, + IMX_SC_R_ADC_0, + IMX_SC_R_ADC_1, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_GPU_0_PID0, + IMX_SC_R_GPU_1_PID0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_2, + IMX_SC_R_NAND, + IMX_SC_R_LVDS_0, + IMX_SC_R_LVDS_0_PWM_0, + IMX_SC_R_LVDS_0_I2C_0, + IMX_SC_R_LVDS_0_I2C_1, + IMX_SC_R_LVDS_1, + IMX_SC_R_LVDS_1_PWM_0, + IMX_SC_R_LVDS_1_I2C_0, + IMX_SC_R_LVDS_1_I2C_1, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_M4_1_I2C, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_VPU_UART, + IMX_SC_R_VPUCORE, + IMX_SC_R_MIPI_0, + IMX_SC_R_MIPI_0_PWM_0, + IMX_SC_R_MIPI_0_I2C_0, + IMX_SC_R_MIPI_0_I2C_1, + IMX_SC_R_MIPI_1, + IMX_SC_R_MIPI_1_PWM_0, + IMX_SC_R_MIPI_1_I2C_0, + IMX_SC_R_MIPI_1_I2C_1, + IMX_SC_R_CSI_0, + IMX_SC_R_CSI_0_PWM_0, + IMX_SC_R_CSI_0_I2C_0, + IMX_SC_R_CSI_1, + IMX_SC_R_CSI_1_PWM_0, + IMX_SC_R_CSI_1_I2C_0, + IMX_SC_R_HDMI, + IMX_SC_R_HDMI_I2S, + IMX_SC_R_HDMI_I2C_0, + IMX_SC_R_HDMI_PLL_0, + IMX_SC_R_HDMI_RX, + IMX_SC_R_HDMI_RX_BYPASS, + IMX_SC_R_HDMI_RX_I2C_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_HDMI_RX_PWM_0, + IMX_SC_R_HDMI_PLL_1, + IMX_SC_R_VPU, +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = { + .rsrc = imx8qm_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8qxp-rsrc.c b/drivers/clk/imx/clk-imx8qxp-rsrc.c new file mode 100644 index 000000000000..df09f2a7996d --- /dev/null +++ b/drivers/clk/imx/clk-imx8qxp-rsrc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + * Dong Aisheng + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static const u32 imx8qxp_clk_scu_rsrc_table[] = { + IMX_SC_R_DC_0_VIDEO0, + IMX_SC_R_DC_0_VIDEO1, + IMX_SC_R_DC_0, + IMX_SC_R_DC_0_PLL_0, + IMX_SC_R_DC_0_PLL_1, + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_ADC_0, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_GPU_0_PID0, + IMX_SC_R_LCD_0, + IMX_SC_R_LCD_0_PWM_0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_2, + IMX_SC_R_NAND, + IMX_SC_R_LVDS_0, + IMX_SC_R_LVDS_1, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_ELCDIF_PLL, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_PI_0, + IMX_SC_R_PI_0_PLL, + IMX_SC_R_MIPI_0, + IMX_SC_R_MIPI_0_PWM_0, + IMX_SC_R_MIPI_0_I2C_0, + IMX_SC_R_MIPI_0_I2C_1, + IMX_SC_R_MIPI_1, + IMX_SC_R_MIPI_1_PWM_0, + IMX_SC_R_MIPI_1_I2C_0, + IMX_SC_R_MIPI_1_I2C_1, + IMX_SC_R_CSI_0, + IMX_SC_R_CSI_0_PWM_0, + IMX_SC_R_CSI_0_I2C_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_A35, + IMX_SC_R_VPU_DEC_0, + IMX_SC_R_VPU_ENC_0, +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = { + .rsrc = imx8qxp_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index fbf1170c09ed..c53a688d8ccc 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * Dong Aisheng */ @@ -9,12 +9,12 @@ #include #include #include +#include #include #include #include "clk-scu.h" -#include #include static const char *dc0_sels[] = { @@ -25,159 +25,278 @@ static const char *dc0_sels[] = { "dc0_bypass0_clk", }; +static const char * const dc1_sels[] = { + "clk_dummy", + "clk_dummy", + "dc1_pll0_clk", + "dc1_pll1_clk", + "dc1_bypass0_clk", +}; + +static const char * const enet0_rgmii_txc_sels[] = { + "enet0_ref_div", + "clk_dummy", +}; + +static const char * const enet1_rgmii_txc_sels[] = { + "enet1_ref_div", + "clk_dummy", +}; + +static const char * const hdmi_sels[] = { + "clk_dummy", + "hdmi_dig_pll_clk", + "clk_dummy", + "clk_dummy", + "hdmi_av_pll_clk", +}; + +static const char * const hdmi_rx_sels[] = { + "clk_dummy", + "hdmi_rx_dig_pll_clk", + "clk_dummy", + "clk_dummy", + "hdmi_rx_bypass_clk", +}; + +static const char * const lcd_pxl_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "lcd_pxl_bypass_div_clk", +}; + +static const char * const mipi_sels[] = { + "clk_dummy", + "clk_dummy", + "mipi_pll_div2_clk", + "clk_dummy", + "clk_dummy", +}; + +static const char * const lcd_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "elcdif_pll", +}; + +static const char * const pi_pll0_sels[] = { + "clk_dummy", + "pi_dpll_clk", + "clk_dummy", + "clk_dummy", + "clk_dummy", +}; + static int imx8qxp_clk_probe(struct platform_device *pdev) { struct device_node *ccm_node = pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - struct clk_hw **clks; - u32 clk_cells; - int ret, i; + const struct imx_clk_scu_rsrc_table *rsrc_table; + int ret; - ret = imx_clk_scu_init(ccm_node); + rsrc_table = of_device_get_match_data(&pdev->dev); + ret = imx_clk_scu_init(ccm_node, rsrc_table); if (ret) return ret; - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, - IMX_SCU_CLK_END), GFP_KERNEL); - if (!clk_data) - return -ENOMEM; - - if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells)) - return -EINVAL; - - clk_data->num = IMX_SCU_CLK_END; - clks = clk_data->hws; - - /* Fixed clocks */ - clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0); - clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000); - clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333); - clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666); - clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333); - clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000); - clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000); - clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000); - clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000); - clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000); - clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000); - clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000); - clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000); - clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333); - clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000); - clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000); - /* ARM core */ - clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells); + imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU); /* LSIO SS */ - clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells); + imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER); - /* ADMA SS */ - clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells); + /* DMA SS */ + imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c4_clk", IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); + + /* Audio SS */ + imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1); /* Connectivity */ - clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells); - clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells); - clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells); - clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells); - clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells); - clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells); - clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells); + imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER); + imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV); + imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); + imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true); + imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); + imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); + imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); + imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true); + imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); + imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER); + imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); /* Display controller SS */ - clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells); - clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells); - clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells); - clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells); - clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells); - clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells); + imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); + + imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); /* MIPI-LVDS SS */ - clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells); - clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells); - clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells); - clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells); - clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); - clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); + imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); + + imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); + imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER); /* MIPI CSI SS */ - clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells); - clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC); + imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC); + imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER); + + /* Parallel Interface SS */ + imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("pi_per_div_clk", pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER); /* GPU SS */ - clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells); + imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC); - for (i = 0; i < clk_data->num; i++) { - if (IS_ERR(clks[i])) - pr_warn("i.MX clk %u: register failed with %ld\n", - i, PTR_ERR(clks[i])); - } + imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC); - if (clk_cells == 2) { - ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks); - if (ret) - imx_clk_scu_unregister(); - } else { - /* - * legacy binding code path doesn't unregister here because - * it will be removed later. - */ - ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data); - } + /* CM40 SS */ + imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER); + imx_clk_scu("cm40_lpuart_div", IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER); + + /* CM41 SS */ + imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER); + + /* HDMI TX SS */ + imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4); + imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0); + + /* HDMI RX SS */ + imx_clk_scu("hdmi_rx_i2s_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("hdmi_rx_spdif_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("hdmi_rx_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_i2c0_clk", IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_pwm_clk", IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_spdif_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("hdmi_rx_hd_ref_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1); + imx_clk_scu2("hdmi_rx_hd_core_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("hdmi_rx_pxl_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("hdmi_rx_i2s_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4); + + ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks); + if (ret) + imx_clk_scu_unregister(); return ret; } static const struct of_device_id imx8qxp_match[] = { { .compatible = "fsl,scu-clk", }, - { .compatible = "fsl,imx8qxp-clk", }, + { .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, }, + { .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, }, { /* sentinel */ } }; diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index f89b4da10e80..083da31dc3ea 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * Dong Aisheng */ #include #include +#include #include #include #include @@ -22,6 +23,7 @@ static struct imx_sc_ipc *ccm_ipc_handle; static struct device_node *pd_np; static struct platform_driver imx_clk_scu_driver; +static const struct imx_clk_scu_rsrc_table *rsrc_table; struct imx_scu_clk_node { const char *name; @@ -48,10 +50,28 @@ struct clk_scu { u8 clk_type; /* for state save&restore */ + struct clk_hw *parent; + u8 parent_index; bool is_enabled; u32 rate; }; +/* + * struct clk_gpr_scu - Description of one SCU GPR clock + * @hw: the common clk_hw + * @rsrc_id: resource ID of this SCU clock + * @gpr_id: GPR ID index to control the divider + */ +struct clk_gpr_scu { + struct clk_hw hw; + u16 rsrc_id; + u8 gpr_id; + u8 flags; + bool gate_invert; +}; + +#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw) + /* * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol * @hdr: SCU protocol header @@ -151,7 +171,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw) return container_of(hw, struct clk_scu, hw); } -int imx_clk_scu_init(struct device_node *np) +static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p) +{ + return *(u32 *)rsrc - *(u32 *)rsrc_p; +} + +static bool imx_scu_clk_is_valid(u32 rsrc_id) +{ + void *p; + + if (!rsrc_table) + return true; + + p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num, + sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp); + + return p != NULL; +} + +int imx_clk_scu_init(struct device_node *np, + const struct imx_clk_scu_rsrc_table *data) { u32 clk_cells; int ret, i; @@ -170,6 +209,8 @@ int imx_clk_scu_init(struct device_node *np) pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd"); if (!pd_np) return -EINVAL; + + rsrc_table = data; } return platform_driver_register(&imx_clk_scu_driver); @@ -234,8 +275,10 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, struct arm_smccc_res res; unsigned long cluster_id; - if (clk->rsrc_id == IMX_SC_R_A35) + if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) cluster_id = 0; + else if (clk->rsrc_id == IMX_SC_R_A72) + cluster_id = 1; else return -EINVAL; @@ -296,6 +339,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw) return 0; } + clk->parent_index = msg.data.resp.parent; + return msg.data.resp.parent; } @@ -304,6 +349,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) struct clk_scu *clk = to_clk_scu(hw); struct imx_sc_msg_set_clock_parent msg; struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; hdr->ver = IMX_SC_RPC_VERSION; hdr->svc = IMX_SC_RPC_SVC_PM; @@ -314,7 +360,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) msg.clk = clk->clk_type; msg.parent = index; - return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + if (ret) { + pr_err("%s: failed to set clock parent %d\n", + clk_hw_get_name(hw), ret); + return ret; + } + + clk->parent_index = index; + + return 0; } static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, @@ -386,6 +441,12 @@ static const struct clk_ops clk_scu_cpu_ops = { .unprepare = clk_scu_unprepare, }; +static const struct clk_ops clk_scu_pi_ops = { + .recalc_rate = clk_scu_recalc_rate, + .round_rate = clk_scu_round_rate, + .set_rate = clk_scu_set_rate, +}; + struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) @@ -404,8 +465,10 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, init.name = name; init.ops = &clk_scu_ops; - if (rsrc_id == IMX_SC_R_A35) + if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72) init.ops = &clk_scu_cpu_ops; + else if (rsrc_id == IMX_SC_R_PI_0_PLL) + init.ops = &clk_scu_pi_ops; else init.ops = &clk_scu_ops; init.parent_names = parents; @@ -458,15 +521,19 @@ static int imx_clk_scu_probe(struct platform_device *pdev) struct clk_hw *hw; int ret; - pm_runtime_set_suspended(dev); - pm_runtime_set_autosuspend_delay(dev, 50); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(dev); + if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || + (clk->rsrc == IMX_SC_R_A72))) { + pm_runtime_set_suspended(dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); - if (ret) { - pm_runtime_disable(dev); - return ret; + ret = pm_runtime_get_sync(dev); + if (ret) { + pm_genpd_remove_device(dev); + pm_runtime_disable(dev); + return ret; + } } hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents, @@ -479,8 +546,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev) clk->hw = hw; list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]); - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); + if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || + (clk->rsrc == IMX_SC_R_A72))) { + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + } dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc, clk->clk_type); @@ -491,10 +561,28 @@ static int imx_clk_scu_probe(struct platform_device *pdev) static int __maybe_unused imx_clk_scu_suspend(struct device *dev) { struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; - clk->rate = clk_hw_get_rate(&clk->hw); + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + + clk->parent = clk_hw_get_parent(&clk->hw); + + /* DC SS needs to handle bypass clock using non-cached clock rate */ + if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1) + clk->rate = clk_scu_recalc_rate(&clk->hw, 0); + else + clk->rate = clk_hw_get_rate(&clk->hw); clk->is_enabled = clk_hw_is_enabled(&clk->hw); + if (clk->parent) + dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), + clk->parent_index); + if (clk->rate) dev_dbg(dev, "save rate %d\n", clk->rate); @@ -507,15 +595,27 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) static int __maybe_unused imx_clk_scu_resume(struct device *dev) { struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; int ret = 0; + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + + if (clk->parent) { + ret = clk_scu_set_parent(&clk->hw, clk->parent_index); + dev_dbg(dev, "restore parent %s idx %u %s\n", + clk_hw_get_name(clk->parent), + clk->parent_index, !ret ? "success" : "failed"); + } + if (clk->rate) { ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); dev_dbg(dev, "restore rate %d %s\n", clk->rate, !ret ? "success" : "failed"); } - if (clk->is_enabled) { + if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) { ret = clk_scu_prepare(&clk->hw); dev_dbg(dev, "restore enabled state %s\n", !ret ? "success" : "failed"); @@ -567,6 +667,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name, struct platform_device *pdev; int ret; + if (!imx_scu_clk_is_valid(rsrc_id)) + return ERR_PTR(-EINVAL); + pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE); if (!pdev) { pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n", @@ -605,3 +708,176 @@ void imx_clk_scu_unregister(void) } } } + +static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + unsigned long rate = 0; + u32 val; + int err; + + err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + + rate = val ? parent_rate / 2 : parent_rate; + + return err ? 0 : rate; +} + +static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + if (rate < *prate) + rate = *prate / 2; + else + rate = *prate; + + return rate; +} + +static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + uint32_t val; + int err; + + val = (rate < parent_rate) ? 1 : 0; + err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, val); + + return err ? -EINVAL : 0; +} + +static const struct clk_ops clk_gpr_div_scu_ops = { + .recalc_rate = clk_gpr_div_scu_recalc_rate, + .round_rate = clk_gpr_div_scu_round_rate, + .set_rate = clk_gpr_div_scu_set_rate, +}; + +static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + u32 val = 0; + + imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + + return (u8)val; +} + +static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + + return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, index); +} + +static const struct clk_ops clk_gpr_mux_scu_ops = { + .get_parent = clk_gpr_mux_scu_get_parent, + .set_parent = clk_gpr_mux_scu_set_parent, +}; + +static int clk_gpr_gate_scu_prepare(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + + return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, !clk->gate_invert); +} + +static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + int ret; + + ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, clk->gate_invert); + if (ret) + pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), + ret); +} + +static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw) +{ + struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); + int ret; + u32 val; + + ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id, + clk->gpr_id, &val); + if (ret) + return ret; + + return clk->gate_invert ? !val : val; +} + +static const struct clk_ops clk_gpr_gate_scu_ops = { + .prepare = clk_gpr_gate_scu_prepare, + .unprepare = clk_gpr_gate_scu_unprepare, + .is_prepared = clk_gpr_gate_scu_is_prepared, +}; + +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, + int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, + bool invert) +{ + struct imx_scu_clk_node *clk_node; + struct clk_gpr_scu *clk; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST) + return ERR_PTR(-EINVAL); + + clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL); + if (!clk_node) + return ERR_PTR(-ENOMEM); + + if (!imx_scu_clk_is_valid(rsrc_id)) + return ERR_PTR(-EINVAL); + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) { + kfree(clk_node); + return ERR_PTR(-ENOMEM); + } + + clk->rsrc_id = rsrc_id; + clk->gpr_id = gpr_id; + clk->flags = flags; + clk->gate_invert = invert; + + if (flags & IMX_SCU_GPR_CLK_GATE) + init.ops = &clk_gpr_gate_scu_ops; + + if (flags & IMX_SCU_GPR_CLK_DIV) + init.ops = &clk_gpr_div_scu_ops; + + if (flags & IMX_SCU_GPR_CLK_MUX) + init.ops = &clk_gpr_mux_scu_ops; + + init.flags = 0; + init.name = name; + init.parent_names = parent_name; + init.num_parents = num_parents; + + clk->hw.init = &init; + + hw = &clk->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(clk); + kfree(clk_node); + hw = ERR_PTR(ret); + } else { + clk_node->hw = hw; + clk_node->clk_type = gpr_id; + list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]); + } + + return hw; +} diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h index e8352164923e..22156e93b85d 100644 --- a/drivers/clk/imx/clk-scu.h +++ b/drivers/clk/imx/clk-scu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * Dong Aisheng */ @@ -10,10 +10,22 @@ #include #include +#define IMX_SCU_GPR_CLK_GATE BIT(0) +#define IMX_SCU_GPR_CLK_DIV BIT(1) +#define IMX_SCU_GPR_CLK_MUX BIT(2) + +struct imx_clk_scu_rsrc_table { + const u32 *rsrc; + u8 num; +}; + extern struct list_head imx_scu_clks[]; extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm; -int imx_clk_scu_init(struct device_node *np); +int imx_clk_scu_init(struct device_node *np, + const struct imx_clk_scu_rsrc_table *data); struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *imx_clk_scu_alloc_dev(const char *name, @@ -31,23 +43,20 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name, void __iomem *reg, u8 bit_idx, bool hw_gate); void imx_clk_lpcg_scu_unregister(struct clk_hw *hw); +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, + int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags, + bool invert); + static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, - u8 clk_type, u8 clk_cells) + u8 clk_type) { - if (clk_cells == 2) - return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); - else - return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type); + return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); } static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents, - int num_parents, u32 rsrc_id, u8 clk_type, - u8 clk_cells) + int num_parents, u32 rsrc_id, u8 clk_type) { - if (clk_cells == 2) - return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); - else - return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type); + return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); } static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name, @@ -65,4 +74,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg, bit_idx, hw_gate); } + +static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name, + u32 rsrc_id, u8 gpr_id, bool invert) +{ + return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, + IMX_SCU_GPR_CLK_GATE, invert); +} + +static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name, + u32 rsrc_id, u8 gpr_id) +{ + return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id, + IMX_SCU_GPR_CLK_DIV, 0); +} + +static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names, + int num_parents, u32 rsrc_id, u8 gpr_id) +{ + return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id, + gpr_id, IMX_SCU_GPR_CLK_MUX, 0); +} #endif diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 580b0cf69ed5..898f1bc478c9 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -25,6 +25,16 @@ config INGENIC_CGU_JZ4725B If building for a JZ4725B SoC, you want to say Y here. +config INGENIC_CGU_JZ4760 + bool "Ingenic JZ4760 CGU driver" + default MACH_JZ4760 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4760 + and compatible SoCs. + + If building for a JZ4760 SoC, you want to say Y here. + config INGENIC_CGU_JZ4770 bool "Ingenic JZ4770 CGU driver" default MACH_JZ4770 diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index aaa4bffe03c6..9edfaf4610b9 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index c8e9cb6c8e39..266c7595d330 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - ctl = readl(cgu->base + pll_info->bypass_reg); + if (pll_info->bypass_bit >= 0) { + ctl = readl(cgu->base + pll_info->bypass_reg); - bypass = !pll_info->no_bypass_bit && - !!(ctl & BIT(pll_info->bypass_bit)); + bypass = !!(ctl & BIT(pll_info->bypass_bit)); - if (bypass) - return parent_rate; + if (bypass) + return parent_rate; + } for (od = 0; od < pll_info->od_max; od++) { if (pll_info->od_encoding[od] == od_enc) @@ -118,28 +119,42 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n * od); } -static unsigned long -ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, - unsigned long rate, unsigned long parent_rate, - unsigned *pm, unsigned *pn, unsigned *pod) +static void +ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) { - const struct ingenic_cgu_pll_info *pll_info; - unsigned m, n, od; - - pll_info = &clk_info->pll; - od = 1; + unsigned int m, n, od = 1; /* * The frequency after the input divider must be between 10 and 50 MHz. * The highest divider yields the best resolution. */ n = parent_rate / (10 * MHZ); - n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); - n = max_t(unsigned, n, pll_info->n_offset); + n = min_t(unsigned int, n, 1 << pll_info->n_bits); + n = max_t(unsigned int, n, pll_info->n_offset); m = (rate / MHZ) * od * n / (parent_rate / MHZ); - m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); - m = max_t(unsigned, m, pll_info->m_offset); + m = min_t(unsigned int, m, 1 << pll_info->m_bits); + m = max_t(unsigned int, m, pll_info->m_offset); + + *pm = m; + *pn = n; + *pod = od; +} + +static unsigned long +ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; + unsigned int m, n, od; + + if (pll_info->calc_m_n_od) + (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); + else + ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od); if (pm) *pm = m; @@ -225,11 +240,13 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->bypass_reg); + if (pll_info->bypass_bit >= 0) { + ctl = readl(cgu->base + pll_info->bypass_reg); - ctl &= ~BIT(pll_info->bypass_bit); + ctl &= ~BIT(pll_info->bypass_bit); - writel(ctl, cgu->base + pll_info->bypass_reg); + writel(ctl, cgu->base + pll_info->bypass_reg); + } ctl = readl(cgu->base + pll_info->reg); @@ -369,18 +386,23 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long rate = parent_rate; u32 div_reg, div; + u8 parent; if (clk_info->type & CGU_CLK_DIV) { - div_reg = readl(cgu->base + clk_info->div.reg); - div = (div_reg >> clk_info->div.shift) & - GENMASK(clk_info->div.bits - 1, 0); + parent = ingenic_clk_get_parent(hw); - if (clk_info->div.div_table) - div = clk_info->div.div_table[div]; - else - div = (div + 1) * clk_info->div.div; + if (!(clk_info->div.bypass_mask & BIT(parent))) { + div_reg = readl(cgu->base + clk_info->div.reg); + div = (div_reg >> clk_info->div.shift) & + GENMASK(clk_info->div.bits - 1, 0); - rate /= div; + if (clk_info->div.div_table) + div = clk_info->div.div_table[div]; + else + div = (div + 1) * clk_info->div.div; + + rate /= div; + } } else if (clk_info->type & CGU_CLK_FIXDIV) { rate /= clk_info->fixdiv.div; } @@ -410,10 +432,16 @@ ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, } static unsigned -ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info, +ingenic_clk_calc_div(struct clk_hw *hw, + const struct ingenic_cgu_clk_info *clk_info, unsigned long parent_rate, unsigned long req_rate) { unsigned int div, hw_div; + u8 parent; + + parent = ingenic_clk_get_parent(hw); + if (clk_info->div.bypass_mask & BIT(parent)) + return 1; /* calculate the divide */ div = DIV_ROUND_UP(parent_rate, req_rate); @@ -448,7 +476,7 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned int div = 1; if (clk_info->type & CGU_CLK_DIV) - div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate); + div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); else if (clk_info->type & CGU_CLK_FIXDIV) div = clk_info->fixdiv.div; else if (clk_hw_can_set_rate_parent(hw)) @@ -480,7 +508,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, int ret = 0; if (clk_info->type & CGU_CLK_DIV) { - div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate); + div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); rate = DIV_ROUND_UP(parent_rate, div); if (rate != req_rate) diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 2c75ef4a36f5..bfc2b9c38a41 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -39,10 +39,10 @@ * their encoded values in the PLL control register, or -1 for * unsupported values * @bypass_reg: the offset of the bypass control register within the CGU - * @bypass_bit: the index of the bypass bit in the PLL control register + * @bypass_bit: the index of the bypass bit in the PLL control register, or + * -1 if there is no bypass bit * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register - * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { unsigned reg; @@ -52,10 +52,12 @@ struct ingenic_cgu_pll_info { u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; unsigned bypass_reg; - u8 bypass_bit; + s8 bypass_bit; u8 enable_bit; u8 stable_bit; - bool no_bypass_bit; + void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *m, unsigned int *n, unsigned int *od); }; /** @@ -84,6 +86,7 @@ struct ingenic_cgu_mux_info { * isn't one * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one + * @bypass_mask: mask of parent clocks for which the divider does not apply * @div_table: optional table to map the value read from the register to the * actual divider value */ @@ -95,6 +98,7 @@ struct ingenic_cgu_div_info { s8 ce_bit; s8 busy_bit; s8 stop_bit; + u8 bypass_mask; const u8 *div_table; }; diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 8c38e72d14a7..5154b0cf8ad6 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -80,7 +80,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "pll half", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4725b_cgu_pll_half_div_table, }, }, @@ -89,7 +89,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "cclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, @@ -98,7 +98,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "hclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, @@ -107,7 +107,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "pclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, @@ -116,7 +116,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "mclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, @@ -125,7 +125,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "ipu", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR, 13 }, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index c0ac9196a581..cd878f08aca3 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -95,7 +95,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "pll half", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4740_cgu_pll_half_div_table, }, }, @@ -104,7 +104,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "cclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, @@ -113,7 +113,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "hclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, @@ -122,7 +122,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "pclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, @@ -131,7 +131,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "mclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, @@ -140,7 +140,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, .div = { - CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, + CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR, 10 }, diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c new file mode 100644 index 000000000000..14483797a4db --- /dev/null +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * JZ4760 SoC CGU driver + * Copyright 2018, Paul Cercueil + */ + +#include +#include +#include +#include +#include + +#include + +#include + +#include "cgu.h" +#include "pm.h" + +#define MHZ (1000 * 1000) + +/* + * CPM registers offset address definition + */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR0 0x10 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_CPPCR1 0x30 +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBCDR 0x50 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_UHCCDR 0x6c +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_GPSCDR 0x80 +#define CGU_REG_PCMCDR 0x84 +#define CGU_REG_GPUCDR 0x88 + +static const s8 pll_od_encoding[8] = { + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, +}; + +static const u8 jz4760_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4760_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static void +jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2; + + /* The frequency after the N divider must be between 1 and 50 MHz. */ + n = parent_rate / (1 * MHZ); + + /* The N divider must be >= 2. */ + n = clamp_val(n, 2, 1 << pll_info->n_bits); + + for (;; n >>= 1) { + od = (unsigned int)-1; + + do { + m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ); + } while ((m > m_max || m & 1) && (od < 4)); + + if (od < 4 && m >= 4 && m <= m_max) + break; + } + + *pm = m; + *pn = n; + *pod = 1 << od; +} + +static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { + + /* External clocks */ + + [JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + /* PLLs */ + + [JZ4760_CLK_PLL0] = { + "pll0", CGU_CLK_PLL, + .parents = { JZ4760_CLK_EXT }, + .pll = { + .reg = CGU_REG_CPPCR0, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 8, + .m_offset = 0, + .n_shift = 18, + .n_bits = 4, + .n_offset = 0, + .od_shift = 16, + .od_bits = 2, + .od_max = 8, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR0, + .bypass_bit = 9, + .enable_bit = 8, + .stable_bit = 10, + .calc_m_n_od = jz4760_cgu_calc_m_n_od, + }, + }, + + [JZ4760_CLK_PLL1] = { + /* TODO: PLL1 can depend on PLL0 */ + "pll1", CGU_CLK_PLL, + .parents = { JZ4760_CLK_EXT }, + .pll = { + .reg = CGU_REG_CPPCR1, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 8, + .m_offset = 0, + .n_shift = 18, + .n_bits = 4, + .n_offset = 0, + .od_shift = 16, + .od_bits = 2, + .od_max = 8, + .od_encoding = pll_od_encoding, + .bypass_bit = -1, + .enable_bit = 7, + .stable_bit = 6, + .calc_m_n_od = jz4760_cgu_calc_m_n_od, + }, + }, + + /* Main clocks */ + + [JZ4760_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + [JZ4760_CLK_HCLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + [JZ4760_CLK_SCLK] = { + "sclk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + [JZ4760_CLK_H2CLK] = { + "h2clk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + [JZ4760_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + [JZ4760_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0, }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4760_cgu_cpccr_div_table, + }, + }, + + /* Divided clocks */ + + [JZ4760_CLK_PLL0_HALF] = { + "pll0_half", CGU_CLK_DIV, + .parents = { JZ4760_CLK_PLL0 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0, + jz4760_cgu_pll_half_div_table, + }, + }, + + /* Those divided clocks can connect to PLL0 or PLL1 */ + + [JZ4760_CLK_UHC] = { + "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .mux = { CGU_REG_UHCCDR, 31, 1 }, + .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 24 }, + }, + [JZ4760_CLK_GPU] = { + "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .mux = { CGU_REG_GPUCDR, 31, 1 }, + .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR1, 9 }, + }, + [JZ4760_CLK_LPCLK_DIV] = { + "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .mux = { CGU_REG_LPCDR, 29, 1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + }, + [JZ4760_CLK_TVE] = { + "tve", CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR0, 27 }, + }, + [JZ4760_CLK_LPCLK] = { + "lpclk", CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, }, + .mux = { CGU_REG_LPCDR, 30, 1 }, + .gate = { CGU_REG_CLKGR0, 28 }, + }, + [JZ4760_CLK_GPS] = { + "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .mux = { CGU_REG_GPSCDR, 31, 1 }, + .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 22 }, + }, + + /* Those divided clocks can connect to EXT, PLL0 or PLL1 */ + + [JZ4760_CLK_PCM] = { + "pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_EXT, -1, + JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, + .mux = { CGU_REG_PCMCDR, 30, 2 }, + .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, + .gate = { CGU_REG_CLKGR1, 8 }, + }, + [JZ4760_CLK_I2S] = { + "i2s", CGU_CLK_DIV | CGU_CLK_MUX, + .parents = { JZ4760_CLK_EXT, -1, + JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, + .mux = { CGU_REG_I2SCDR, 30, 2 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, + }, + [JZ4760_CLK_OTG] = { + "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4760_CLK_EXT, -1, + JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, + .mux = { CGU_REG_USBCDR, 30, 2 }, + .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 2 }, + }, + + /* Those divided clocks can connect to EXT or PLL0 */ + [JZ4760_CLK_MMC_MUX] = { + "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, + .mux = { CGU_REG_MSCCDR, 31, 1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) }, + }, + [JZ4760_CLK_SSI_MUX] = { + "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, + .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, + .mux = { CGU_REG_SSICDR, 31, 1 }, + .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) }, + }, + + /* These divided clock can connect to PLL0 only */ + [JZ4760_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4760_CLK_PLL0_HALF }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 26 }, + }, + + /* Gate-only clocks */ + + [JZ4760_CLK_SSI0] = { + "ssi0", CGU_CLK_GATE, + .parents = { JZ4760_CLK_SSI_MUX, }, + .gate = { CGU_REG_CLKGR0, 4 }, + }, + [JZ4760_CLK_SSI1] = { + "ssi1", CGU_CLK_GATE, + .parents = { JZ4760_CLK_SSI_MUX, }, + .gate = { CGU_REG_CLKGR0, 19 }, + }, + [JZ4760_CLK_SSI2] = { + "ssi2", CGU_CLK_GATE, + .parents = { JZ4760_CLK_SSI_MUX, }, + .gate = { CGU_REG_CLKGR0, 20 }, + }, + [JZ4760_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4760_CLK_H2CLK, }, + .gate = { CGU_REG_CLKGR0, 21 }, + }, + [JZ4760_CLK_I2C0] = { + "i2c0", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 5 }, + }, + [JZ4760_CLK_I2C1] = { + "i2c1", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 6 }, + }, + [JZ4760_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 15 }, + }, + [JZ4760_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 16 }, + }, + [JZ4760_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 17 }, + }, + [JZ4760_CLK_UART3] = { + "uart3", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 18 }, + }, + [JZ4760_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4760_CLK_HCLK, }, + .gate = { CGU_REG_CLKGR0, 29 }, + }, + [JZ4760_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 14 }, + }, + [JZ4760_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4760_CLK_EXT, }, + .gate = { CGU_REG_CLKGR0, 8 }, + }, + [JZ4760_CLK_VPU] = { + "vpu", CGU_CLK_GATE, + .parents = { JZ4760_CLK_HCLK, }, + .gate = { CGU_REG_LCR, 30, false, 150 }, + }, + [JZ4760_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4760_CLK_MMC_MUX, }, + .gate = { CGU_REG_CLKGR0, 3 }, + }, + [JZ4760_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4760_CLK_MMC_MUX, }, + .gate = { CGU_REG_CLKGR0, 11 }, + }, + [JZ4760_CLK_MMC2] = { + "mmc2", CGU_CLK_GATE, + .parents = { JZ4760_CLK_MMC_MUX, }, + .gate = { CGU_REG_CLKGR0, 12 }, + }, + [JZ4760_CLK_UHC_PHY] = { + "uhc_phy", CGU_CLK_GATE, + .parents = { JZ4760_CLK_UHC, }, + .gate = { CGU_REG_OPCR, 5 }, + }, + [JZ4760_CLK_OTG_PHY] = { + "usb_phy", CGU_CLK_GATE, + .parents = { JZ4760_CLK_OTG }, + .gate = { CGU_REG_OPCR, 7, true, 50 }, + }, + + /* Custom clocks */ + [JZ4760_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4760_CLK_EXT }, + .fixdiv = { 512 }, + }, + [JZ4760_CLK_RTC] = { + "rtc", CGU_CLK_MUX, + .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, }, + .mux = { CGU_REG_OPCR, 2, 1}, + }, +}; + +static void __init jz4760_cgu_init(struct device_node *np) +{ + struct ingenic_cgu *cgu; + int retval; + + cgu = ingenic_cgu_new(jz4760_cgu_clocks, + ARRAY_SIZE(jz4760_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} + +/* We only probe via devicetree, no need for a platform driver */ +CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init); + +/* JZ4760B has some small differences, but we don't implement them. */ +CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init); diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 9ea4490ecb7f..2321742b3471 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, - .bypass_reg = CGU_REG_CPPCR1, - .no_bypass_bit = true, + .bypass_bit = -1, .enable_bit = 7, .stable_bit = 6, }, @@ -152,7 +151,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "cclk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, @@ -160,7 +159,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "h0clk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, @@ -168,7 +167,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR1, 7 }, @@ -177,7 +176,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "h2clk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, @@ -185,7 +184,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "c1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle @@ -194,7 +193,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "pclk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { - CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c index 9382dc3aa27e..77acfbeb4830 100644 --- a/drivers/clk/ingenic/tcu.c +++ b/drivers/clk/ingenic/tcu.c @@ -326,6 +326,7 @@ static const struct ingenic_soc_info x1000_soc_info = { static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = { { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, }, { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, }, + { .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, }, { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, }, { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, }, { /* sentinel */ } @@ -477,5 +478,6 @@ static void __init ingenic_tcu_init(struct device_node *np) CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init); +CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init); diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c index 5b3d36462174..aae1a4076281 100644 --- a/drivers/clk/keystone/syscon-clk.c +++ b/drivers/clk/keystone/syscon-clk.c @@ -149,11 +149,28 @@ static const struct ti_syscon_gate_clk_data am654_clk_data[] = { { /* Sentinel */ }, }; +static const struct ti_syscon_gate_clk_data am64_clk_data[] = { + TI_SYSCON_CLK_GATE("epwm_tbclk0", 0x0, 0), + TI_SYSCON_CLK_GATE("epwm_tbclk1", 0x0, 1), + TI_SYSCON_CLK_GATE("epwm_tbclk2", 0x0, 2), + TI_SYSCON_CLK_GATE("epwm_tbclk3", 0x0, 3), + TI_SYSCON_CLK_GATE("epwm_tbclk4", 0x0, 4), + TI_SYSCON_CLK_GATE("epwm_tbclk5", 0x0, 5), + TI_SYSCON_CLK_GATE("epwm_tbclk6", 0x0, 6), + TI_SYSCON_CLK_GATE("epwm_tbclk7", 0x0, 7), + TI_SYSCON_CLK_GATE("epwm_tbclk8", 0x0, 8), + { /* Sentinel */ }, +}; + static const struct of_device_id ti_syscon_gate_clk_ids[] = { { .compatible = "ti,am654-ehrpwm-tbclk", .data = &am654_clk_data, }, + { + .compatible = "ti,am64-epwm-tbclk", + .data = &am64_clk_data, + }, { } }; MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids); diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 7c8d02164443..bfe36bd41339 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -1665,8 +1665,7 @@ static int devm_clk_get_enable(struct device *dev, char *id) clk = devm_clk_get(dev, id); if (IS_ERR(clk)) { ret = PTR_ERR(clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get %s", id); + dev_err_probe(dev, ret, "failed to get %s", id); return ret; } @@ -1811,7 +1810,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) ret = device_reset(dev); if (ret) { - dev_err(dev, "failed to reset device\n"); + dev_err_probe(dev, ret, "failed to reset device\n"); return ret; } diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 49f27fe53213..9e55617bc3b4 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -242,8 +242,8 @@ static int meson_clk_get_pll_settings(unsigned long rate, return best ? 0 : -EINVAL; } -static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int meson_clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); @@ -251,22 +251,26 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long round; int ret; - ret = meson_clk_get_pll_settings(rate, *parent_rate, &m, &n, pll); + ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate, + &m, &n, pll); if (ret) - return meson_clk_pll_recalc_rate(hw, *parent_rate); + return ret; - round = __pll_params_to_rate(*parent_rate, m, n, 0, pll); + round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll); - if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round) - return round; + if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) { + req->rate = round; + return 0; + } /* * The rate provided by the setting is not an exact match, let's * try to improve the result using the fractional parameter */ - frac = __pll_params_with_frac(rate, *parent_rate, m, n, pll); + frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll); + req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll); - return __pll_params_to_rate(*parent_rate, m, n, frac, pll); + return 0; } static int meson_clk_pll_wait_lock(struct clk_hw *hw) @@ -419,7 +423,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, */ const struct clk_ops meson_clk_pcie_pll_ops = { .recalc_rate = meson_clk_pll_recalc_rate, - .round_rate = meson_clk_pll_round_rate, + .determine_rate = meson_clk_pll_determine_rate, .is_enabled = meson_clk_pll_is_enabled, .enable = meson_clk_pcie_pll_enable, .disable = meson_clk_pll_disable @@ -429,7 +433,7 @@ EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops); const struct clk_ops meson_clk_pll_ops = { .init = meson_clk_pll_init, .recalc_rate = meson_clk_pll_recalc_rate, - .round_rate = meson_clk_pll_round_rate, + .determine_rate = meson_clk_pll_determine_rate, .set_rate = meson_clk_pll_set_rate, .is_enabled = meson_clk_pll_is_enabled, .enable = meson_clk_pll_enable, diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index b080359b4645..310accf94830 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { }; static const struct pll_mult_range g12a_gp0_pll_mult_range = { - .min = 55, + .min = 125, .max = 255, }; @@ -4723,6 +4723,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, + [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, + [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, + [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, + [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, + [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, + [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45646b867cdb..62e00e15495c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -210,6 +210,13 @@ config MSM_LCC_8960 Say Y if you want to use audio devices such as i2s, pcm, SLIMBus, etc. +config MDM_GCC_9607 + tristate "MDM9607 Global Clock Controller" + help + Support for the global clock controller on mdm9607 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, SD/eMMC, etc. + config MDM_GCC_9615 tristate "MDM9615 Global Clock Controller" help @@ -483,6 +490,13 @@ config SDX_GCC_55 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_CAMCC_8250 + tristate "SM8250 Camera Clock Controller" + select SM_GCC_8250 + help + Support for the camera clock controller on SM8250 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_8250 tristate "SM8150 and SM8250 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 @@ -492,6 +506,13 @@ config SM_DISPCC_8250 Say Y if you want to support display devices and functionality such as splash screen. +config SM_GCC_6125 + tristate "SM6125 Global Clock Controller" + help + Support for the global clock controller on SM6125 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS, PCIe etc. + config SM_GCC_8150 tristate "SM8150 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c8291312e723..c2a1cafb31bc 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o +obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o @@ -73,7 +74,9 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o +obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o +obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o diff --git a/drivers/clk/qcom/apcs-sdx55.c b/drivers/clk/qcom/apcs-sdx55.c index d0edabebf9c2..e599f862ec44 100644 --- a/drivers/clk/qcom/apcs-sdx55.c +++ b/drivers/clk/qcom/apcs-sdx55.c @@ -57,7 +57,7 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) regmap = dev_get_regmap(parent, NULL); if (!regmap) { - dev_err_probe(dev, -ENODEV, "Failed to get parent regmap\n"); + dev_err(dev, "Failed to get parent regmap\n"); return -ENODEV; } @@ -80,19 +80,15 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) a7cc->parent_map = apcs_mux_clk_parent_map; a7cc->pclk = devm_clk_get(parent, "pll"); - if (IS_ERR(a7cc->pclk)) { - ret = PTR_ERR(a7cc->pclk); - if (ret != -EPROBE_DEFER) - dev_err_probe(dev, ret, "Failed to get PLL clk\n"); - return ret; - } + if (IS_ERR(a7cc->pclk)) + return dev_err_probe(dev, PTR_ERR(a7cc->pclk), + "Failed to get PLL clk\n"); a7cc->clk_nb.notifier_call = a7cc_notifier_cb; ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb); - if (ret) { - dev_err_probe(dev, ret, "Failed to register clock notifier\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clock notifier\n"); ret = devm_clk_register_regmap(dev, &a7cc->clkr); if (ret) { diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c new file mode 100644 index 000000000000..439eaafdcc86 --- /dev/null +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -0,0 +1,2456 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EARLY, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_SLEEP_CLK, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct pll_vco zonda_vco[] = { + { 595200000UL, 3600000000UL, 0 }, +}; + +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699c, + .user_ctl_val = 0x00003100, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x3, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 12, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x1f, + .alpha = 0x4000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699c, + .user_ctl_val = 0x00000100, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 8, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x4b, + .alpha = 0x0, + .config_ctl_val = 0x08200920, + .config_ctl_hi_val = 0x05002015, + .config_ctl_hi1_val = 0x00000000, + .user_ctl_val = 0x00000100, + .user_ctl_hi_val = 0x00000000, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .vco_table = zonda_vco, + .num_vco = ARRAY_SIZE(zonda_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_zonda_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { + .offset = 0x2000, + .post_div_shift = 8, + .post_div_table = post_div_table_cam_cc_pll2_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main), + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll2_out_main", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_zonda_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x24, + .alpha = 0x7555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699c, + .user_ctl_val = 0x00000100, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 8, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x24, + .alpha = 0x7555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699c, + .user_ctl_val = 0x00000100, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 8, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll2_out_main.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EARLY, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .fw_name = "bi_tcxo" }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x7010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { + .cmd_rcgr = 0xc0f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_camnoc_axi_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0xc0bc, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0xc0d8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0xa068, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x6000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x6020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x6040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x6060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x6080, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x60a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x703c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fd_core_clk_src = { + .cmd_rcgr = 0xc098, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fd_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_fd_core_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0xc074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fd_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0xa010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div cam_cc_sbi_div_clk_src = { + .reg = 0x9010, + .shift = 0, + .width = 3, + .clkr.hw.init = &(struct clk_init_data) { + .name = "cam_cc_sbi_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { + .cmd_rcgr = 0xa040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0xb010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { + .cmd_rcgr = 0xb040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0xc000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0xc01c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_0_clk_src = { + .cmd_rcgr = 0x8010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_ipe_0_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0xc048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6), + F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x5000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x5038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x5054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x5070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x50a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_sbi_csid_clk_src = { + .cmd_rcgr = 0x901c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32768, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0xc170, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x7058, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0xc154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x7070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7070, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_areg_clk = { + .halt_reg = 0x7054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_bps_areg_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_axi_clk = { + .halt_reg = 0x7038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_bps_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x7028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_clk = { + .halt_reg = 0xc114, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_camnoc_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0xc11c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc11c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_xo_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0xc0d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0xc0f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_1_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0xc150, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xc150, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0xc0f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0f4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x6018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x6038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x6058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x6078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x6098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi4phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x60b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x60b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csi5phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi5phytimer_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x601c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x601c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x603c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x603c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x605c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x605c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x607c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x607c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x609c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x609c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x60bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x60bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_csiphy5_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_fd_core_clk = { + .halt_reg = 0xc0b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_fd_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_fd_core_uar_clk = { + .halt_reg = 0xc0b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_fd_core_uar_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_gdsc_clk = { + .halt_reg = 0xc16c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc16c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_gdsc_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_xo_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0xc094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0xc08c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc08c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_ahb_clk = { + .halt_reg = 0xa088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_areg_clk = { + .halt_reg = 0xa030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_areg_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_axi_clk = { + .halt_reg = 0xa084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0xa028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { + .halt_reg = 0xa080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_csid_clk = { + .halt_reg = 0xa058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_csid_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_dsp_clk = { + .halt_reg = 0xa03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_0_dsp_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_ahb_clk = { + .halt_reg = 0xb068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_areg_clk = { + .halt_reg = 0xb030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_areg_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_axi_clk = { + .halt_reg = 0xb064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0xb028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { + .halt_reg = 0xb060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_csid_clk = { + .halt_reg = 0xb058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_csid_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_dsp_clk = { + .halt_reg = 0xb03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_1_dsp_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0xc040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_axi_clk = { + .halt_reg = 0xc044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0xc018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0xc03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0xc034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_ahb_clk = { + .halt_reg = 0x8040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ipe_0_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_areg_clk = { + .halt_reg = 0x803c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x803c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ipe_0_areg_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_axi_clk = { + .halt_reg = 0x8038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ipe_0_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_clk = { + .halt_reg = 0x8028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_ipe_0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0xc060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x5018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x5034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x5050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x506c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x5088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk4_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x50a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk5_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x50c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50c0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk6_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_ahb_clk = { + .halt_reg = 0x9040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_axi_clk = { + .halt_reg = 0x903c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x903c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_camnoc_axi_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_clk = { + .halt_reg = 0x9014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_sbi_div_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_cphy_rx_clk = { + .halt_reg = 0x9038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_csid_clk = { + .halt_reg = 0x9034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_csid_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_sbi_csid_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_ife_0_clk = { + .halt_reg = 0x9044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_ife_0_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_ife_1_clk = { + .halt_reg = 0x9048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sbi_ife_1_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sleep_clk = { + .halt_reg = 0xc188, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc188, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_sleep_clk", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_sleep_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc bps_gdsc = { + .gdscr = 0x7004, + .pd = { + .name = "bps_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ipe_0_gdsc = { + .gdscr = 0x8004, + .pd = { + .name = "ipe_0_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc sbi_gdsc = { + .gdscr = 0x9004, + .pd = { + .name = "sbi_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ife_0_gdsc = { + .gdscr = 0xa004, + .pd = { + .name = "ife_0_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ife_1_gdsc = { + .gdscr = 0xb004, + .pd = { + .name = "ife_1_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc titan_top_gdsc = { + .gdscr = 0xc144, + .pd = { + .name = "titan_top_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct clk_regmap *cam_cc_sm8250_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, + [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, + [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, + [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, + [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, + [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr, + [CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr, + [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, + [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, + [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, + [CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr, + [CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr, + [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, + [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, + [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, + [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, + [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, + [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, + [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, + [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr, + [CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr, + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, + [CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr, + [CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr, + [CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr, + [CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr, + [CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr, + [CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr, + [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_sm8250_gdscs[] = { + [BPS_GDSC] = &bps_gdsc, + [IPE_0_GDSC] = &ipe_0_gdsc, + [SBI_GDSC] = &sbi_gdsc, + [IFE_0_GDSC] = &ife_0_gdsc, + [IFE_1_GDSC] = &ife_1_gdsc, + [TITAN_TOP_GDSC] = &titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_sm8250_resets[] = { + [CAM_CC_BPS_BCR] = { 0x7000 }, + [CAM_CC_ICP_BCR] = { 0xc070 }, + [CAM_CC_IFE_0_BCR] = { 0xa000 }, + [CAM_CC_IFE_1_BCR] = { 0xb000 }, + [CAM_CC_IPE_0_BCR] = { 0x8000 }, + [CAM_CC_SBI_BCR] = { 0x9000 }, +}; + +static const struct regmap_config cam_cc_sm8250_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe004, + .fast_io = true, +}; + +static const struct qcom_cc_desc cam_cc_sm8250_desc = { + .config = &cam_cc_sm8250_regmap_config, + .clks = cam_cc_sm8250_clocks, + .num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks), + .resets = cam_cc_sm8250_resets, + .num_resets = ARRAY_SIZE(cam_cc_sm8250_resets), + .gdscs = cam_cc_sm8250_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs), +}; + +static const struct of_device_id cam_cc_sm8250_match_table[] = { + { .compatible = "qcom,sm8250-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table); + +static int cam_cc_sm8250_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + + return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap); +} + +static struct platform_driver cam_cc_sm8250_driver = { + .probe = cam_cc_sm8250_probe, + .driver = { + .name = "cam_cc-sm8250", + .of_match_table = cam_cc_sm8250_match_table, + }, +}; + +static int __init cam_cc_sm8250_init(void) +{ + return platform_driver_register(&cam_cc_sm8250_driver); +} +subsys_initcall(cam_cc_sm8250_init); + +static void __exit cam_cc_sm8250_exit(void) +{ + platform_driver_unregister(&cam_cc_sm8250_driver); +} +module_exit(cam_cc_sm8250_exit); + +MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index c6eb99169ddc..eaedcceb766f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x1c, [PLL_OFF_STATUS] = 0x2c, }, + [CLK_ALPHA_PLL_TYPE_ZONDA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL_U1] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_TEST_CTL_U1] = 0x24, + [PLL_OFF_OPMODE] = 0x28, + [PLL_OFF_STATUS] = 0x38, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) +/* ZONDA PLL specific */ +#define ZONDA_PLL_OUT_MASK 0xf +#define ZONDA_STAY_IN_CFA BIT(16) +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29) + #define pll_alpha_width(p) \ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) @@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_enable_lock(pll) \ wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") +#define wait_for_zonda_pll_freq_lock(pll) \ + wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") + #define wait_for_pll_disable(pll) \ wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") @@ -1234,7 +1255,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw) return ret; /* Setup PLL for calibration frequency */ - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), cal_l); + regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); /* Bringup the PLL at calibration frequency */ ret = clk_alpha_pll_enable(hw); @@ -1777,3 +1798,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, }; EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); + +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); + + /* Disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + + /* Set operation mode to OFF */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + /* Place the PLL in STANDBY mode */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); +} +EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); + +static int clk_zonda_pll_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + int ret; + + regmap_read(regmap, PLL_MODE(pll), &val); + + /* If in FSM mode, just vote for it */ + if (val & PLL_VOTE_FSM_ENA) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_active(pll); + } + + /* Get the PLL out of bypass mode */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); + + /* + * H/W requires a 1us delay between disabling the bypass and + * de-asserting the reset. + */ + udelay(1); + + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + + /* Set operation mode to RUN */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); + + regmap_read(regmap, PLL_TEST_CTL(pll), &val); + + /* If cfa mode then poll for freq lock */ + if (val & ZONDA_STAY_IN_CFA) + ret = wait_for_zonda_pll_freq_lock(pll); + else + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); + + /* Enable the global PLL outputs */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); + + return 0; +} + +static void clk_zonda_pll_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + + regmap_read(regmap, PLL_MODE(pll), &val); + + /* If in FSM mode, just unvote it */ + if (val & PLL_VOTE_FSM_ENA) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + + /* Disable the PLL outputs */ + regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); + + /* Put the PLL in bypass and reset */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); + + /* Place the PLL mode in OFF state */ + regmap_write(regmap, PLL_OPMODE(pll), 0x0); +} + +static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long rrate; + u32 test_ctl_val; + u32 l, alpha_width = pll_alpha_width(pll); + u64 a; + int ret; + + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); + + ret = alpha_pll_check_rate_margin(hw, rrate, rate); + if (ret < 0) + return ret; + + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + + /* Wait before polling for the frequency latch */ + udelay(5); + + /* Read stay in cfa mode */ + regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); + + /* If cfa mode then poll for freq lock */ + if (test_ctl_val & ZONDA_STAY_IN_CFA) + ret = wait_for_zonda_pll_freq_lock(pll); + else + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Wait for PLL output to stabilize */ + udelay(100); + return 0; +} + +const struct clk_ops clk_alpha_pll_zonda_ops = { + .enable = clk_zonda_pll_enable, + .disable = clk_zonda_pll_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = clk_zonda_pll_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6943e933be0f..55e4fa47912f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -16,6 +16,7 @@ enum { CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_AGERA, + CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_zonda_ops; +#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, #define clk_lucid_pll_configure(pll, regmap, config) \ clk_trion_pll_configure(pll, regmap, config) +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 05ff3b0d233e..e1b1b426fae4 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -357,6 +357,83 @@ static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, return __clk_rcg2_set_rate(hw, rate, FLOOR); } +static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + u32 notn_m, n, m, d, not2d, mask; + + if (!rcg->mnd_width) { + /* 50 % duty-cycle for Non-MND RCGs */ + duty->num = 1; + duty->den = 2; + return 0; + } + + regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d); + regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); + regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); + + if (!not2d && !m && !notn_m) { + /* 50 % duty-cycle always */ + duty->num = 1; + duty->den = 2; + return 0; + } + + mask = BIT(rcg->mnd_width) - 1; + + d = ~(not2d) & mask; + d = DIV_ROUND_CLOSEST(d, 2); + + n = (~(notn_m) + m) & mask; + + duty->num = d; + duty->den = n; + + return 0; +} + +static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + u32 notn_m, n, m, d, not2d, mask, duty_per; + int ret; + + /* Duty-cycle cannot be modified for non-MND RCGs */ + if (!rcg->mnd_width) + return -EINVAL; + + mask = BIT(rcg->mnd_width) - 1; + + regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); + regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); + + n = (~(notn_m) + m) & mask; + + duty_per = (duty->num * 100) / duty->den; + + /* Calculate 2d value */ + d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100); + + /* Check bit widths of 2d. If D is too big reduce duty cycle. */ + if (d > mask) + d = mask; + + if ((d / 2) > (n - m)) + d = (n - m) * 2; + else if ((d / 2) < (m / 2)) + d = m; + + not2d = ~d & mask; + + ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask, + not2d); + if (ret) + return ret; + + return update_config(rcg); +} + const struct clk_ops clk_rcg2_ops = { .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, @@ -365,6 +442,8 @@ const struct clk_ops clk_rcg2_ops = { .determine_rate = clk_rcg2_determine_rate, .set_rate = clk_rcg2_set_rate, .set_rate_and_parent = clk_rcg2_set_rate_and_parent, + .get_duty_cycle = clk_rcg2_get_duty_cycle, + .set_duty_cycle = clk_rcg2_set_duty_cycle, }; EXPORT_SYMBOL_GPL(clk_rcg2_ops); @@ -376,6 +455,8 @@ const struct clk_ops clk_rcg2_floor_ops = { .determine_rate = clk_rcg2_determine_floor_rate, .set_rate = clk_rcg2_set_floor_rate, .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent, + .get_duty_cycle = clk_rcg2_get_duty_cycle, + .set_duty_cycle = clk_rcg2_set_duty_cycle, }; EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 0e1dfa89489e..800b2fef1887 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -39,7 +39,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_name, \ - .parent_names = (const char *[]){ "xo_board" }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -54,7 +57,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ - .parent_names = (const char *[]){ "xo_board" }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } @@ -73,7 +79,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_name, \ - .parent_names = (const char *[]){ "xo_board" }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -89,7 +98,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_active, \ - .parent_names = (const char *[]){ "xo_board" }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } @@ -406,7 +418,6 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .unprepare = clk_smd_rpm_unprepare, }; -/* msm8916 */ DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); @@ -452,48 +463,35 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { .num_clks = ARRAY_SIZE(msm8916_clks), }; -/* msm8936 */ -DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5); static struct clk_smd_rpm *msm8936_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8936_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8936_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8936_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8936_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8936_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8936_bimc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8936_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8936_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8936_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8936_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8936_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8936_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8936_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8936_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8936_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8936_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8936_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8936_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8936_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8936_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8936_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8936_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8936_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8936_rf_clk2_a_pin, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { @@ -501,15 +499,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { .num_clks = ARRAY_SIZE(msm8936_clks), }; -/* msm8974 */ -DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4); @@ -525,22 +518,22 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6); static struct clk_smd_rpm *msm8974_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_CXO_D0] = &msm8974_cxo_d0, [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a, [RPM_SMD_CXO_D1] = &msm8974_cxo_d1, @@ -574,46 +567,33 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .num_clks = ARRAY_SIZE(msm8974_clks), }; - -/* msm8976 */ -DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2); static struct clk_smd_rpm *msm8976_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8976_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8976_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a, - [RPM_SMD_RF_CLK2] = &msm8976_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin, + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk, - [RPM_SMD_DIV_CLK2] = &msm8976_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, }; @@ -623,78 +603,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { .num_clks = ARRAY_SIZE(msm8976_clks), }; -/* msm8992 */ -DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13); -DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8); -DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, - QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5); DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); static struct clk_smd_rpm *msm8992_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk, - [RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src, - [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk, - [RPM_SMD_BB_CLK1] = &msm8992_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2] = &msm8992_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a, - [RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin, - [RPM_SMD_DIV_CLK1] = &msm8992_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8992_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a, + [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, + [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, + [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, - [RPM_SMD_IPA_CLK] = &msm8992_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8992_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8992_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, @@ -706,83 +663,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { .num_clks = ARRAY_SIZE(msm8992_clks), }; -/* msm8994 */ -DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13); -DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8); -DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, - QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5); - -DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); static struct clk_smd_rpm *msm8994_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk, - [RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src, - [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk, - [RPM_SMD_BB_CLK1] = &msm8994_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2] = &msm8994_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a, - [RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin, - [RPM_SMD_DIV_CLK1] = &msm8994_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8994_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8994_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a, - [RPM_SMD_IPA_CLK] = &msm8994_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk, - [RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8994_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8994_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin, - [RPM_SMD_CE1_CLK] = &msm8994_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk, - [RPM_SMD_CE2_CLK] = &msm8994_ce2_clk, - [RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, + [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, + [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, + [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk, [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk, }; @@ -792,79 +721,58 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { .num_clks = ARRAY_SIZE(msm8994_clks), }; -/* msm8996 */ -DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); -DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); static struct clk_smd_rpm *msm8996_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_IPA_CLK] = &msm8996_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &msm8996_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8996_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8996_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8996_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8996_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a, - [RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk, - [RPM_SMD_DIV_CLK1] = &msm8996_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8996_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8996_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, + [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { @@ -872,43 +780,29 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; -/* QCS404 */ -DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); - -DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); - -DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); - DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); -DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); static struct clk_smd_rpm *qcs404_clks[] = { - [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk, - [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, - [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk, - [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a, - [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { @@ -916,63 +810,47 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; -/* msm8998 */ -DEFINE_CLK_SMD_RPM(msm8998, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb); -DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3); -DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, - QCOM_SMD_RPM_MMAXI_CLK, 0); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6); static struct clk_smd_rpm *msm8998_clks[] = { - [RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8998_bimc_a_clk, - [RPM_SMD_PCNOC_CLK] = &msm8998_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8998_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk, - [RPM_SMD_CE1_CLK] = &msm8998_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk, - [RPM_SMD_DIV_CLK1] = &msm8998_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a, - [RPM_SMD_IPA_CLK] = &msm8998_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, - [RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk, [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk, [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8998_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a, - [RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, @@ -984,72 +862,48 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .num_clks = ARRAY_SIZE(msm8998_clks), }; -/* sdm660 */ DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, - QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, - QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, - QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11); -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, - ln_bb_clk1_pin_a, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, - ln_bb_clk2_pin_a, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, - ln_bb_clk3_pin_a, 3); static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk, - [RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk, - [RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk, - [RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk, - [RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk, - [RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk, - [RPM_SMD_IPA_CLK] = &sdm660_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &sdm660_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &sdm660_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a, - [RPM_SMD_DIV_CLK1] = &sdm660_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a, - [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1, - [RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a, + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk, + [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, + [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1, + [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, - [RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin, - [RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a, - [RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, }; @@ -1060,6 +914,7 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { }; static const struct of_device_id rpm_smd_clk_match_table[] = { + { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..601c7c0ba483 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -26,6 +26,8 @@ enum { P_DISP_CC_PLL1_OUT_MAIN, P_DP_PHY_PLL_LINK_CLK, P_DP_PHY_PLL_VCO_DIV_CLK, + P_EDP_PHY_PLL_LINK_CLK, + P_EDP_PHY_PLL_VCO_DIV_CLK, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_DSI1_PHY_PLL_OUT_BYTECLK, @@ -134,6 +136,18 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { { .hw = &disp_cc_pll1.clkr.hw }, }; +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_EDP_PHY_PLL_LINK_CLK, 1 }, + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "edp_phy_pll_link_clk" }, + { .fw_name = "edp_phy_pll_vco_div_clk" }, +}; + static const struct parent_map disp_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_DISP_CC_PLL0_OUT_MAIN, 1 }, @@ -158,6 +172,18 @@ static const struct clk_parent_data disp_cc_parent_data_6[] = { { .fw_name = "dsi1_phy_pll_out_dsiclk" }, }; +static const struct parent_map disp_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, + /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ +}; + +static const struct clk_parent_data disp_cc_parent_data_7[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll1.clkr.hw }, + /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ +}; + static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), @@ -261,7 +287,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { .name = "disp_cc_mdss_dp_link1_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -275,7 +301,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -318,6 +344,153 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { }, }; +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { + .cmd_rcgr = 0x228c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { + .cmd_rcgr = 0x22a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_7, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_gtc_clk_src", + .parent_data = disp_cc_parent_data_7, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { + .cmd_rcgr = 0x2270, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { + .cmd_rcgr = 0x2258, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .ops = &clk_dp_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_aux_clk = { + .halt_reg = 0x2078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_gtc_clk = { + .halt_reg = 0x207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x207c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_gtc_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_clk = { + .halt_reg = 0x2070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2070, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { + .halt_reg = 0x2074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_pixel_clk = { + .halt_reg = 0x206c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x206c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .cmd_rcgr = 0x2148, .mnd_width = 0, @@ -987,6 +1160,15 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = { [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, @@ -1037,6 +1219,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = { }; static const struct of_device_id disp_cc_sm8250_match_table[] = { + { .compatible = "qcom,sc8180x-dispcc" }, { .compatible = "qcom,sm8150-dispcc" }, { .compatible = "qcom,sm8250-dispcc" }, { } @@ -1053,7 +1236,8 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* note: trion == lucid, except for the prepare() op */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || + of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c new file mode 100644 index 000000000000..4c9078e99bb3 --- /dev/null +++ b/drivers/clk/qcom/gcc-mdm9607.c @@ -0,0 +1,1632 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-alpha-pll.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "reset.h" +#include "gdsc.h" + +enum { + P_XO, + P_BIMC, + P_GPLL0, + P_GPLL1, + P_GPLL2, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0_early = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gpll0_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data) + { + .name = "gpll0", + .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, +}; + +static struct clk_pll gpll1 = { + .l_reg = 0x20004, + .m_reg = 0x20008, + .n_reg = 0x2000c, + .config_reg = 0x20010, + .mode_reg = 0x20000, + .status_reg = 0x2001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll1_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_vote", + .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL1, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll1_vote.hw }, + { .fw_name = "sleep_clk" }, +}; + +static struct clk_alpha_pll gpll2_early = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(3), /* Yeah, apparently it's not 2 */ + .hw.init = &(struct clk_init_data) + { + .name = "gpll2_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll2 = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data) + { + .name = "gpll2", + .parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL2, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL1, 2 }, + { P_GPLL2, 3 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll1_vote.hw }, + { .hw = &gpll2.clkr.hw }, +}; + +static const struct freq_tbl ftbl_apss_ahb_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 apss_ahb_clk_src = { + .cmd_rcgr = 0x46000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_apss_ahb_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_ahb_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_pll bimc_pll = { + .l_reg = 0x23004, + .m_reg = 0x23008, + .n_reg = 0x2300c, + .config_reg = 0x23010, + .mode_reg = 0x23000, + .status_reg = 0x2301c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_pll", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap bimc_pll_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "bimc_pll_vote", + .parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_bimc_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_BIMC, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_bimc[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &bimc_pll_vote.hw }, +}; + +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 pcnoc_bfdcd_clk_src = { + .cmd_rcgr = 0x27000, + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcnoc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_bimc, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), + .ops = &clk_rcg2_ops, + .flags = CLK_IS_CRITICAL, + }, +}; + +static struct clk_rcg2 system_noc_bfdcd_clk_src = { + .cmd_rcgr = 0x26004, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_bimc, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x200c, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x2024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x3000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x3014, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x4000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x4024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x5000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x5024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { + .cmd_rcgr = 0x6000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { + .cmd_rcgr = 0x6024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { + .cmd_rcgr = 0x7000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { + .cmd_rcgr = 0x7024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { + F(3686400, P_GPLL0, 1, 72, 15625), + F(7372800, P_GPLL0, 1, 144, 15625), + F(14745600, P_GPLL0, 1, 288, 15625), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 1, 3, 100), + F(25000000, P_GPLL0, 16, 1, 2), + F(32000000, P_GPLL0, 1, 1, 25), + F(40000000, P_GPLL0, 1, 1, 20), + F(46400000, P_GPLL0, 1, 29, 500), + F(48000000, P_GPLL0, 1, 3, 50), + F(51200000, P_GPLL0, 1, 8, 125), + F(56000000, P_GPLL0, 1, 7, 100), + F(58982400, P_GPLL0, 1, 1152, 15625), + F(60000000, P_GPLL0, 1, 3, 40), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x2044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x3034, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart3_apps_clk_src = { + .cmd_rcgr = 0x4044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart3_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart4_apps_clk_src = { + .cmd_rcgr = 0x5044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart4_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart5_apps_clk_src = { + .cmd_rcgr = 0x6044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart5_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart6_apps_clk_src = { + .cmd_rcgr = 0x6044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart6_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_crypto_clk[] = { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 crypto_clk_src = { + .cmd_rcgr = 0x16004, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_crypto_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "crypto_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x8004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll1_sleep_map, + .freq_tbl = ftbl_gcc_gp1_3_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_data = gcc_xo_gpll0_gpll1_sleep, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x09004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll1_sleep_map, + .freq_tbl = ftbl_gcc_gp1_3_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_data = gcc_xo_gpll0_gpll1_sleep, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x0a004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll1_sleep_map, + .freq_tbl = ftbl_gcc_gp1_3_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_data = gcc_xo_gpll0_gpll1_sleep, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { + F(64000000, P_GPLL0, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src = { + .cmd_rcgr = 0x44010, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_pdm2_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 10, 1, 4), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(177770000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x42004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_sdcc_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_floor_ops, + }, +}; + +static struct clk_rcg2 sdcc2_apps_clk_src = { + .cmd_rcgr = 0x43004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_sdcc_apps_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { + F(155000000, P_GPLL2, 6, 0, 0), + F(310000000, P_GPLL2, 3, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + { } +}; + +static struct clk_rcg2 apss_tcu_clk_src = { + .cmd_rcgr = 0x1207c, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll1_gpll2_map, + .freq_tbl = ftbl_gcc_apss_tcu_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_tcu_clk_src", + .parent_data = gcc_xo_gpll0_gpll1_gpll2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(57140000, P_GPLL0, 14, 0, 0), + F(69565000, P_GPLL0, 11.5, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(177778000, P_GPLL0, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hs_system_clk_src = { + .cmd_rcgr = 0x41010, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_gcc_usb_hs_system_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb_hs_system_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb_hsic_clk_src[] = { + F(480000000, P_GPLL2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hsic_clk_src = { + .cmd_rcgr = 0x3d018, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_map, + .freq_tbl = ftbl_usb_hsic_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb_hsic_clk_src", + .parent_data = gcc_xo_gpll0_gpll2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = { + F(9600000, P_XO, 2, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hsic_io_cal_clk_src = { + .cmd_rcgr = 0x3d030, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_usb_hsic_io_cal_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb_hsic_io_cal_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(57140000, P_GPLL0, 14, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(177778000, P_GPLL0, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hsic_system_clk_src = { + .cmd_rcgr = 0x3d000, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .freq_tbl = ftbl_usb_hsic_system_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb_hsic_system_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x1008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_sleep_clk = { + .halt_reg = 0x1004, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_sleep_clk", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x2008, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x2004, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x3010, + .clkr = { + .enable_reg = 0x3010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x300c, + .clkr = { + .enable_reg = 0x300c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x4020, + .clkr = { + .enable_reg = 0x4020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x401c, + .clkr = { + .enable_reg = 0x401c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x5020, + .clkr = { + .enable_reg = 0x5020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x501c, + .clkr = { + .enable_reg = 0x501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { + .halt_reg = 0x6020, + .clkr = { + .enable_reg = 0x6020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { + .halt_reg = 0x601c, + .clkr = { + .enable_reg = 0x601c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { + .halt_reg = 0x7020, + .clkr = { + .enable_reg = 0x7020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { + .halt_reg = 0x701c, + .clkr = { + .enable_reg = 0x701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x203c, + .clkr = { + .enable_reg = 0x203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x302c, + .clkr = { + .enable_reg = 0x302c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart3_apps_clk = { + .halt_reg = 0x403c, + .clkr = { + .enable_reg = 0x403c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart3_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart4_apps_clk = { + .halt_reg = 0x503c, + .clkr = { + .enable_reg = 0x503c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart4_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart5_apps_clk = { + .halt_reg = 0x603c, + .clkr = { + .enable_reg = 0x603c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart5_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart6_apps_clk = { + .halt_reg = 0x703c, + .clkr = { + .enable_reg = 0x703c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart6_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x1300c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1601c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x08000, + .clkr = { + .enable_reg = 0x08000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x09000, + .clkr = { + .enable_reg = 0x09000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x0a000, + .clkr = { + .enable_reg = 0x0a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk = { + .halt_reg = 0x49000, + .clkr = { + .enable_reg = 0x49000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x4400c, + .clkr = { + .enable_reg = 0x4400c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x44004, + .clkr = { + .enable_reg = 0x44004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x13004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x4201c, + .clkr = { + .enable_reg = 0x4201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x42018, + .clkr = { + .enable_reg = 0x42018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x4301c, + .clkr = { + .enable_reg = 0x4301c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x43018, + .clkr = { + .enable_reg = 0x43018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 bimc_ddr_clk_src = { + .cmd_rcgr = 0x32004, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_ddr_clk_src", + .parent_data = gcc_xo_gpll0_bimc, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x49004, + .clkr = { + .enable_reg = 0x49004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_tcu_clk = { + .halt_reg = 0x12018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4500c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_tcu_clk", + .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_smmu_cfg_clk = { + .halt_reg = 0x12038, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4500c, + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_smmu_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk = { + .halt_reg = 0x29084, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qdss_dap_clk", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2a_phy_sleep_clk = { + .halt_reg = 0x4102c, + .clkr = { + .enable_reg = 0x4102c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb2a_phy_sleep_clk", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = { + .halt_reg = 0x41030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x41030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_hs_phy_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_ahb_clk = { + .halt_reg = 0x41008, + .clkr = { + .enable_reg = 0x41008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_hs_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_system_clk = { + .halt_reg = 0x41004, + .clkr = { + .enable_reg = 0x41004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_hs_system_clk", + .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_ahb_clk = { + .halt_reg = 0x4601c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_axi_clk = { + .halt_reg = 0x4601c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x45004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_mdm9607_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL0_EARLY] = &gpll0_early.clkr, + [GPLL1] = &gpll1.clkr, + [GPLL1_VOTE] = &gpll1_vote, + [GPLL2] = &gpll2.clkr, + [GPLL2_EARLY] = &gpll2_early.clkr, + [BIMC_PLL] = &bimc_pll.clkr, + [BIMC_PLL_VOTE] = &bimc_pll_vote, + [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, + [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, + [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, + [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, + [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, + [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, + [GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, + [GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, + [GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, +}; + +static const struct qcom_reset_map gcc_mdm9607_resets[] = { + [USB_HS_HSIC_BCR] = { 0x3d05c }, + [GCC_MSS_RESTART] = { 0x3e000 }, + [USB_HS_BCR] = { 0x41000 }, + [USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, + [QUSB2_PHY_BCR] = { 0x4103c }, +}; + +static const struct regmap_config gcc_mdm9607_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x80000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_mdm9607_desc = { + .config = &gcc_mdm9607_regmap_config, + .clks = gcc_mdm9607_clocks, + .num_clks = ARRAY_SIZE(gcc_mdm9607_clocks), + .resets = gcc_mdm9607_resets, + .num_resets = ARRAY_SIZE(gcc_mdm9607_resets), +}; + +static const struct of_device_id gcc_mdm9607_match_table[] = { + { .compatible = "qcom,gcc-mdm9607" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table); + +static int gcc_mdm9607_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_mdm9607_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Vote for GPLL0 to turn on. Needed by acpuclock. */ + regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap); +} + +static struct platform_driver gcc_mdm9607_driver = { + .probe = gcc_mdm9607_probe, + .driver = { + .name = "gcc-mdm9607", + .of_match_table = gcc_mdm9607_match_table, + }, +}; + +static int __init gcc_mdm9607_init(void) +{ + return platform_driver_register(&gcc_mdm9607_driver); +} +core_initcall(gcc_mdm9607_init); + +static void __exit gcc_mdm9607_exit(void) +{ + platform_driver_unregister(&gcc_mdm9607_driver); +} +module_exit(gcc_mdm9607_exit); + +MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 740d3c44c04b..bf305fa9e522 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -719,6 +719,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = { + F(50000000, P_GPLL0, 12, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_ce1_clk[] = { F(50000000, P_GPLL0, 12, 0, 0), F(75000000, P_GPLL0, 8, 0, 0), @@ -761,6 +767,11 @@ static struct clk_rcg2 ce2_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_gp_clk[] = { F(4800000, P_XO, 4, 0, 0), F(6000000, P_GPLL0, 10, 1, 10), @@ -1955,6 +1966,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", + .parent_names = (const char *[]){ + "system_noc_clk_src", + }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1993,6 +2008,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x0cc8, + .clkr = { + .enable_reg = 0x0cc8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_prng_ahb_clk = { .halt_reg = 0x0d04, .halt_check = BRANCH_HALT_VOTED, @@ -2430,6 +2459,121 @@ static struct gdsc usb_hs_hsic_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; +static struct clk_regmap *gcc_msm8226_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL0_VOTE] = &gpll0_vote, + [GPLL1] = &gpll1.clkr, + [GPLL1_VOTE] = &gpll1_vote, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, + [CE1_CLK_SRC] = &ce1_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, + [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, + [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, + [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, + [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, + [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, + [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, + [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, + [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, +}; + +static const struct qcom_reset_map gcc_msm8226_resets[] = { + [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, + [GCC_USB_HS_BCR] = { 0x0480 }, + [GCC_USB2A_PHY_BCR] = { 0x04a8 }, +}; + +static struct gdsc *gcc_msm8226_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, +}; + +static const struct regmap_config gcc_msm8226_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a80, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_msm8226_desc = { + .config = &gcc_msm8226_regmap_config, + .clks = gcc_msm8226_clocks, + .num_clks = ARRAY_SIZE(gcc_msm8226_clocks), + .resets = gcc_msm8226_resets, + .num_resets = ARRAY_SIZE(gcc_msm8226_resets), + .gdscs = gcc_msm8226_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs), +}; + static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -2682,13 +2826,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { }; static const struct of_device_id gcc_msm8974_match_table[] = { - { .compatible = "qcom,gcc-msm8974" }, - { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, - { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, + { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc }, + { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc }, { } }; MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); +static void msm8226_clock_override(void) +{ + ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226; + gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; +} + static void msm8974_pro_clock_override(void) { sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; @@ -2708,16 +2861,18 @@ static int gcc_msm8974_probe(struct platform_device *pdev) { int ret; struct device *dev = &pdev->dev; - bool pro; const struct of_device_id *id; id = of_match_device(gcc_msm8974_match_table, dev); if (!id) return -ENODEV; - pro = !!(id->data); - if (pro) - msm8974_pro_clock_override(); + if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) { + if (id->data == &gcc_msm8226_desc) + msm8226_clock_override(); + else + msm8974_pro_clock_override(); + } ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); if (ret) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index ef734db316df..6cefcdc86990 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -716,6 +716,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23), F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c new file mode 100644 index 000000000000..543cfab7561f --- /dev/null +++ b/drivers/clk/qcom/gcc-sm6125.c @@ -0,0 +1,4190 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_AUX2, + P_GPLL0_OUT_EARLY, + P_GPLL3_OUT_EARLY, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_EARLY, + P_GPLL6_OUT_MAIN, + P_GPLL7_OUT_MAIN, + P_GPLL8_OUT_EARLY, + P_GPLL8_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0_out_early = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_aux2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_aux2", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor gpll0_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll3_out_early = { + .offset = 0x3000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gpll3_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x4000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll5_out_main = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll5_out_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll6_out_early = { + .offset = 0x6000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll6_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll6_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll7_out_early = { + .offset = 0x7000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll7_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll7_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll7_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll7_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll8_out_early = { + .offset = 0x8000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gpll8_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll8_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll8_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll8_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll9_out_early = { + .offset = 0x9000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gpll9_out_early", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll9_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll9_out_main", + .parent_hws = (const struct clk_hw*[]){ + &gpll9_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll0_out_aux2.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL6_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll0_out_aux2.hw }, + { .hw = &gpll6_out_main.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll0_out_aux2.hw }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL5_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll5_out_main.clkr.hw }, + { .hw = &gpll4_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll9_out_main.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll4_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll9_out_main.hw }, + { .hw = &gpll6_out_early.clkr.hw }, + { .hw = &gpll8_out_main.hw }, + { .hw = &gpll4_out_main.clkr.hw }, + { .hw = &gpll3_out_early.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll8_out_main.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL3_OUT_EARLY, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll9_out_main.hw }, + { .hw = &gpll6_out_early.clkr.hw }, + { .hw = &gpll8_out_main.hw }, + { .hw = &gpll3_out_early.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_11[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll8_out_early.clkr.hw }, + { .hw = &gpll4_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_12[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_EARLY, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll6_out_early.clkr.hw }, + { .hw = &gpll8_out_early.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_13[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL7_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0_out_early.clkr.hw }, + { .hw = &gpll0_out_aux2.hw }, + { .hw = &gpll7_out_main.hw }, + { .hw = &gpll4_out_main.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_14[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_14[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "sleep_clk" }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0), + F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ahb_clk_src = { + .cmd_rcgr = 0x56088, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_9, + .freq_tbl = ftbl_gcc_camss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ahb_clk_src", + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { + F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0), + F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cci_clk_src = { + .cmd_rcgr = 0x52004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = { + F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0), + F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0), + F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cpp_clk_src = { + .cmd_rcgr = 0x560c8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_10, + .freq_tbl = ftbl_gcc_camss_cpp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_clk_src", + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0), + F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0_clk_src = { + .cmd_rcgr = 0x55030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { + .cmd_rcgr = 0x53004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1_clk_src = { + .cmd_rcgr = 0x5506c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { + .cmd_rcgr = 0x53024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi2_clk_src = { + .cmd_rcgr = 0x550a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { + .cmd_rcgr = 0x53044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_csi3_clk_src = { + .cmd_rcgr = 0x550e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), + F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csiphy_clk_src = { + .cmd_rcgr = 0x55000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_11, + .freq_tbl = ftbl_gcc_camss_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy_clk_src", + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = { + F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_gp0_clk_src = { + .cmd_rcgr = 0x50000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp0_clk_src", + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_gp1_clk_src = { + .cmd_rcgr = 0x5001c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp1_clk_src", + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = { + F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0), + F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), + F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0), + F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), + F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_jpeg_clk_src = { + .cmd_rcgr = 0x52028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_12, + .freq_tbl = ftbl_gcc_camss_jpeg_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_clk_src", + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), + F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), + { } +}; + +static struct clk_rcg2 gcc_camss_mclk0_clk_src = { + .cmd_rcgr = 0x51000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk1_clk_src = { + .cmd_rcgr = 0x5101c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk2_clk_src = { + .cmd_rcgr = 0x51038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk3_clk_src = { + .cmd_rcgr = 0x51054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = { + F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0), + F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0), + F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_vfe0_clk_src = { + .cmd_rcgr = 0x54010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_clk_src", + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_camss_vfe1_clk_src = { + .cmd_rcgr = 0x54048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_clk_src", + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x4d004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x4e004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x4f004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x20010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), + F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), + F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), + F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), + F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), + F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), + F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x1f148, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x1f278, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x1f3a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x1f4d8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x1f608, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x1f738, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { + .name = "gcc_qupv3_wrap1_s0_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { + .cmd_rcgr = 0x39148, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { + .name = "gcc_qupv3_wrap1_s1_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { + .cmd_rcgr = 0x39278, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { + .name = "gcc_qupv3_wrap1_s2_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { + .cmd_rcgr = 0x393a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { + .name = "gcc_qupv3_wrap1_s3_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { + .cmd_rcgr = 0x394d8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { + .name = "gcc_qupv3_wrap1_s4_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { + .cmd_rcgr = 0x39608, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { + .name = "gcc_qupv3_wrap1_s5_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { + .cmd_rcgr = 0x39738, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), + F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x38028, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x38010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(202000000, P_GPLL7_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1e00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_13, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_13, + .num_parents = ARRAY_SIZE(gcc_parent_data_13), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x45020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x45048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x4507c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x45060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0x1a01c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0), + F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0x1a060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_14, + .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_data = gcc_parent_data_14, + .num_parents = ARRAY_SIZE(gcc_parent_data_14), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_vs_ctrl_clk_src = { + .cmd_rcgr = 0x42030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0), + F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_vsensor_clk_src = { + .cmd_rcgr = 0x42018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_vsensor_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_vsensor_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ahb2phy_csi_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_csi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy_usb_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_usb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apc_vs_clk = { + .halt_reg = 0x4204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apc_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_axi_clk = { + .halt_reg = 0x71154, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x71154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x23004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_xo_clk = { + .halt_reg = 0x17028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_ahb_clk = { + .halt_reg = 0x52020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_clk = { + .halt_reg = 0x5201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_cci_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid0_clk = { + .halt_reg = 0x5504c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5504c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid1_clk = { + .halt_reg = 0x55088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid2_clk = { + .halt_reg = 0x550c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550c0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid3_clk = { + .halt_reg = 0x550fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550fc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_ahb_clk = { + .halt_reg = 0x560e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_axi_clk = { + .halt_reg = 0x560f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560f4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_clk = { + .halt_reg = 0x560e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560e0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_cpp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x560f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_vbif_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_ahb_clk = { + .halt_reg = 0x55050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_clk = { + .halt_reg = 0x55048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk = { + .halt_reg = 0x5301c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5301c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0pix_clk = { + .halt_reg = 0x55060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0pix_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0rdi_clk = { + .halt_reg = 0x55058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0rdi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_ahb_clk = { + .halt_reg = 0x5508c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5508c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_clk = { + .halt_reg = 0x55084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk = { + .halt_reg = 0x5303c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5303c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1pix_clk = { + .halt_reg = 0x5509c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5509c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1pix_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1rdi_clk = { + .halt_reg = 0x55094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1rdi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_ahb_clk = { + .halt_reg = 0x550c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550c4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_clk = { + .halt_reg = 0x550bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2phytimer_clk = { + .halt_reg = 0x5305c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5305c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2pix_clk = { + .halt_reg = 0x550d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2pix_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2rdi_clk = { + .halt_reg = 0x550cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2rdi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3_ahb_clk = { + .halt_reg = 0x55100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3_clk = { + .halt_reg = 0x550f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550f8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3pix_clk = { + .halt_reg = 0x55110, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3pix_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3rdi_clk = { + .halt_reg = 0x55108, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3rdi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csi3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe0_clk = { + .halt_reg = 0x54074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi_vfe0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe1_clk = { + .halt_reg = 0x54080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi_vfe1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy0_clk = { + .halt_reg = 0x55018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy1_clk = { + .halt_reg = 0x5501c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy2_clk = { + .halt_reg = 0x55020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_csiphy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp0_clk = { + .halt_reg = 0x50018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_gp0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp1_clk = { + .halt_reg = 0x50034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ispif_ahb_clk = { + .halt_reg = 0x540a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x540a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ispif_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_ahb_clk = { + .halt_reg = 0x52048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_axi_clk = { + .halt_reg = 0x5204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_clk = { + .halt_reg = 0x52040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk = { + .halt_reg = 0x51018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk = { + .halt_reg = 0x51034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk = { + .halt_reg = 0x51050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk3_clk = { + .halt_reg = 0x5106c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_micro_ahb_clk = { + .halt_reg = 0x560b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_micro_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_throttle_nrt_axi_clk = { + .halt_reg = 0x560a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_throttle_nrt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_throttle_rt_axi_clk = { + .halt_reg = 0x560a8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_throttle_rt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk = { + .halt_reg = 0x560a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560a0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_top_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_ahb_clk = { + .halt_reg = 0x54034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_clk = { + .halt_reg = 0x54028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_stream_clk = { + .halt_reg = 0x54030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_stream_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_ahb_clk = { + .halt_reg = 0x5406c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5406c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_clk = { + .halt_reg = 0x54060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_stream_clk = { + .halt_reg = 0x54068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_stream_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_vfe1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_tsctr_clk = { + .halt_reg = 0x5409c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5409c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x5408c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5408c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_vbif_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_camss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_vbif_axi_clk = { + .halt_reg = 0x54090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_vbif_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_ahb_clk = { + .halt_reg = 0x2700c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_axi_clk = { + .halt_reg = 0x27008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk = { + .halt_reg = 0x2b004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_gnoc_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_ahb_clk = { + .halt_reg = 0x1700c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1700c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0x17020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_throttle_core_clk = { + .halt_reg = 0x17064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_xo_clk = { + .halt_reg = 0x1702c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1702c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x4d000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x4e000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4e000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x4f000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x36004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x36004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x36004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_early.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_aux2.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x3600c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x3600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x36018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_core_clk = { + .halt_reg = 0x36048, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(31), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_xo_clk = { + .halt_reg = 0x36044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_throttle_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_vs_clk = { + .halt_reg = 0x42048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x2000c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2000c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x20004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x20004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x20004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x20008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x21004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x21004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0x17014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0x17060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0x17018, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { + .halt_reg = 0x36040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0x17010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x1f014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x1f00c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1f144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1f274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1f3a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1f4d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x1f604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x1f734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { + .halt_reg = 0x39014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk = { + .halt_reg = 0x3900c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk = { + .halt_reg = 0x39144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk = { + .halt_reg = 0x39274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(23), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk = { + .halt_reg = 0x393a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(24), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk = { + .halt_reg = 0x394d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk = { + .halt_reg = 0x39604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk = { + .halt_reg = 0x39734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { + .halt_reg = 0x39004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { + .halt_reg = 0x39008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x39008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x38008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x3800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x1e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x1e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = { + .halt_reg = 0x1050c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1050c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_compute_sf_axi_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { + .halt_reg = 0x2b06c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_cpuss_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { + .halt_reg = 0x45098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x45098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_mem_clkref_clk = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_mem_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x45014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk = { + .halt_reg = 0x45010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x45044, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x45078, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45078, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x4501c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x4501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x45018, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x45018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x45040, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0x1a010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0x1a018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0x1a014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk = { + .halt_reg = 0x80278, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80278, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0x1a054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1a058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vdda_vs_clk = { + .halt_reg = 0x4200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vdda_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vddcx_vs_clk = { + .halt_reg = 0x42004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vddcx_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vddmx_vs_clk = { + .halt_reg = 0x42008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vddmx_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk = { + .halt_reg = 0x1701c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_throttle_core_clk = { + .halt_reg = 0x17068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(28), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_xo_clk = { + .halt_reg = 0x17024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vs_ctrl_ahb_clk = { + .halt_reg = 0x42014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x42014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x42014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vs_ctrl_clk = { + .halt_reg = 0x42010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vs_ctrl_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_vs_clk = { + .halt_reg = 0x42050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_vs_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_vsensor_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0x1a004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_phy_gdsc = { + .gdscr = 0x45004, + .pd = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_vfe0_gdsc = { + .gdscr = 0x54004, + .pd = { + .name = "camss_vfe0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_vfe1_gdsc = { + .gdscr = 0x5403c, + .pd = { + .name = "camss_vfe1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_top_gdsc = { + .gdscr = 0x5607c, + .pd = { + .name = "camss_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc cam_cpp_gdsc = { + .gdscr = 0x560bc, + .pd = { + .name = "cam_cpp_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { + .gdscr = 0x7d060, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { + .gdscr = 0x80074, + .pd = { + .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { + .gdscr = 0x80084, + .pd = { + .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + + +static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { + .gdscr = 0x80094, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc *gcc_sm6125_gdscs[] = { + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, + [UFS_PHY_GDSC] = &ufs_phy_gdsc, + [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc, + [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc, + [CAMSS_TOP_GDSC] = &camss_top_gdsc, + [CAM_CPP_GDSC] = &cam_cpp_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, +}; + +static struct clk_hw *gcc_sm6125_hws[] = { + [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw, + [GPLL0_OUT_MAIN] = &gpll0_out_main.hw, + [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, + [GPLL7_OUT_MAIN] = &gpll7_out_main.hw, + [GPLL8_OUT_MAIN] = &gpll8_out_main.hw, + [GPLL9_OUT_MAIN] = &gpll9_out_main.hw, +}; + +static struct clk_regmap *gcc_sm6125_clocks[] = { + [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, + [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, + [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, + [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, + [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, + [GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr, + [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, + [GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr, + [GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr, + [GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr, + [GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr, + [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr, + [GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, + [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, + [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, + [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr, + [GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr, + [GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr, + [GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr, + [GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr, + [GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr, + [GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr, + [GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr, + [GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr, + [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr, + [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr, + [GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr, + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, + [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr, + [GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, + [GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr, + [GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr, + [GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr, + [GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr, + [GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr, + [GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr, + [GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, + [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, + [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, + [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, + [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr, + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, + [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, + [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, + [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, + [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, + [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, + [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, + [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, + [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, + [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, + [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, + [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, + [GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr, + [GPLL0_OUT_EARLY] = &gpll0_out_early.clkr, + [GPLL3_OUT_EARLY] = &gpll3_out_early.clkr, + [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, + [GPLL5_OUT_MAIN] = &gpll5_out_main.clkr, + [GPLL6_OUT_EARLY] = &gpll6_out_early.clkr, + [GPLL7_OUT_EARLY] = &gpll7_out_early.clkr, + [GPLL8_OUT_EARLY] = &gpll8_out_early.clkr, + [GPLL9_OUT_EARLY] = &gpll9_out_early.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, +}; + +static const struct qcom_reset_map gcc_sm6125_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, +}; + +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), +}; + +static const struct regmap_config gcc_sm6125_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc7000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_sm6125_desc = { + .config = &gcc_sm6125_regmap_config, + .clks = gcc_sm6125_clocks, + .num_clks = ARRAY_SIZE(gcc_sm6125_clocks), + .clk_hws = gcc_sm6125_hws, + .num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws), + .resets = gcc_sm6125_resets, + .num_resets = ARRAY_SIZE(gcc_sm6125_resets), + .gdscs = gcc_sm6125_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs), +}; + +static const struct of_device_id gcc_sm6125_match_table[] = { + { .compatible = "qcom,gcc-sm6125" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table); + +static int gcc_sm6125_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gcc_sm6125_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Disable the GPLL0 active input to video block via + * MISC registers. + */ + regmap_update_bits(regmap, 0x80258, 0x1, 0x1); + + /* + * Enable DUAL_EDGE mode for MCLK RCGs + * This is requierd to enable MND divider mode + */ + regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); + regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); + regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000); + regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000); + + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap); +} + +static struct platform_driver gcc_sm6125_driver = { + .probe = gcc_sm6125_probe, + .driver = { + .name = "gcc-sm6125", + .of_match_table = gcc_sm6125_match_table, + }, +}; + +static int __init gcc_sm6125_init(void) +{ + return platform_driver_register(&gcc_sm6125_driver); +} +subsys_initcall(gcc_sm6125_init); + +static void __exit gcc_sm6125_exit(void) +{ + platform_driver_unregister(&gcc_sm6125_driver); +} +module_exit(gcc_sm6125_exit); + +MODULE_DESCRIPTION("QTI GCC SM6125 Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 607e64a17d72..7b450650bcae 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -32,6 +32,7 @@ config CLK_RENESAS select CLK_R8A77995 if ARCH_R8A77995 select CLK_R8A779A0 if ARCH_R8A779A0 select CLK_R9A06G032 if ARCH_R9A06G032 + select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -156,6 +157,10 @@ config CLK_R9A06G032 help This is a driver for R9A06G032 clocks +config CLK_R9A07G044 + bool "RZ/G2L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP @@ -182,6 +187,10 @@ config CLK_RCAR_USB2_CLOCK_SEL help This is a driver for R-Car USB2 clock selector +config CLK_RZG2L + bool "Renesas RZ/G2L family clock support" if COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index ef0d2bba92bf..5c6c5c721d98 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family @@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o +obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o # Generic obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 8fb68e703a6b..3abd6e5400ad 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -28,8 +28,7 @@ * @hw: handle between common and hardware-specific interfaces * @reg: IO-remapped register * @div: divisor value (1-64) - * @src_shift: Shift to access the register bits to select the parent clock - * @src_width: Number of register bits to select the parent clock (may be 0) + * @src_mask: Bitmask covering the register bits to select the parent clock * @nb: Notifier block to save/restore clock state for system resume * @parents: Array to map from valid parent clocks indices to hardware indices */ @@ -37,8 +36,7 @@ struct div6_clock { struct clk_hw hw; void __iomem *reg; unsigned int div; - u32 src_shift; - u32 src_width; + u32 src_mask; struct notifier_block nb; u8 parents[]; }; @@ -99,15 +97,52 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate, rate = 1; div = DIV_ROUND_CLOSEST(parent_rate, rate); - return clamp_t(unsigned int, div, 1, 64); + return clamp(div, 1U, 64U); } -static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_div6_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); + unsigned long prate, calc_rate, diff, best_rate, best_prate; + unsigned int num_parents = clk_hw_get_num_parents(hw); + struct clk_hw *parent, *best_parent = NULL; + unsigned int i, min_div, max_div, div; + unsigned long min_diff = ULONG_MAX; - return *parent_rate / div; + for (i = 0; i < num_parents; i++) { + parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; + + prate = clk_hw_get_rate(parent); + if (!prate) + continue; + + min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL); + max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64; + if (max_div < min_div) + continue; + + div = cpg_div6_clock_calc_div(req->rate, prate); + div = clamp(div, min_div, max_div); + calc_rate = prate / div; + diff = calc_rate > req->rate ? calc_rate - req->rate + : req->rate - calc_rate; + if (diff < min_diff) { + best_rate = calc_rate; + best_parent = parent; + best_prate = prate; + min_diff = diff; + } + } + + if (!best_parent) + return -EINVAL; + + req->best_parent_rate = best_prate; + req->best_parent_hw = best_parent; + req->rate = best_rate; + return 0; } static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, @@ -133,11 +168,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) unsigned int i; u8 hw_index; - if (clock->src_width == 0) + if (clock->src_mask == 0) return 0; - hw_index = (readl(clock->reg) >> clock->src_shift) & - (BIT(clock->src_width) - 1); + hw_index = (readl(clock->reg) & clock->src_mask) >> + __ffs(clock->src_mask); for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; @@ -151,18 +186,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) { struct div6_clock *clock = to_div6_clock(hw); - u8 hw_index; - u32 mask; + u32 src; if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; - mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); - hw_index = clock->parents[index]; - - writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), - clock->reg); - + src = clock->parents[index] << __ffs(clock->src_mask); + writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); return 0; } @@ -173,7 +203,7 @@ static const struct clk_ops cpg_div6_clock_ops = { .get_parent = cpg_div6_clock_get_parent, .set_parent = cpg_div6_clock_set_parent, .recalc_rate = cpg_div6_clock_recalc_rate, - .round_rate = cpg_div6_clock_round_rate, + .determine_rate = cpg_div6_clock_determine_rate, .set_rate = cpg_div6_clock_set_rate, }; @@ -236,17 +266,15 @@ struct clk * __init cpg_div6_register(const char *name, switch (num_parents) { case 1: /* fixed parent clock */ - clock->src_shift = clock->src_width = 0; + clock->src_mask = 0; break; case 4: /* clock with EXSRC bits 6-7 */ - clock->src_shift = 6; - clock->src_width = 2; + clock->src_mask = GENMASK(7, 6); break; case 8: /* VCLK with EXSRC bits 12-14 */ - clock->src_shift = 12; - clock->src_width = 3; + clock->src_mask = GENMASK(14, 12); break; default: pr_err("%s: invalid number of parents for DIV6 clock %s\n", diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 9cfd00cf4e69..81c0bc1e78af 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), /* Core Clock Outputs */ + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1), DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 867c565cb58f..acaf5a93f1d3 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -180,6 +180,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), + DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1), DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 71b11443f6fc..c99942f0e4d4 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, return div; } -static long -r9a06g032_div_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *prate) +static int +r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); - u32 div = DIV_ROUND_UP(*prate, rate); + u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate); pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__, - hw->clk, rate, *prate, div); + hw->clk, req->rate, req->best_parent_rate, div); pr_devel(" min %d (%ld) max %d (%ld)\n", - clk->min, DIV_ROUND_UP(*prate, clk->min), - clk->max, DIV_ROUND_UP(*prate, clk->max)); + clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min), + clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max)); - div = r9a06g032_div_clamp_div(clk, rate, *prate); + div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate); /* * this is a hack. Currently the serial driver asks for a clock rate * that is 16 times the baud rate -- and that is wildly outside the @@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw, if (clk->index == R9A06G032_DIV_UART || clk->index == R9A06G032_DIV_P2_PG) { pr_devel("%s div uart hack!\n", __func__); - return clk_get_rate(hw->clk); + req->rate = clk_get_rate(hw->clk); + return 0; } + req->rate = DIV_ROUND_UP(req->best_parent_rate, div); pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk, - *prate, div, DIV_ROUND_UP(*prate, div)); - return DIV_ROUND_UP(*prate, div); + req->best_parent_rate, div, req->rate); + return 0; } static int @@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw, static const struct clk_ops r9a06g032_clk_div_ops = { .recalc_rate = r9a06g032_div_recalc_rate, - .round_rate = r9a06g032_div_round_rate, + .determine_rate = r9a06g032_div_determine_rate, .set_rate = r9a06g032_div_set_rate, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c new file mode 100644 index 000000000000..50b5269586a4 --- /dev/null +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L CPG driver + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "renesas-rzg2l-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A07G044_OSCCLK, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV16, + CLK_PLL2_DIV20, + CLK_PLL3, + CLK_PLL3_DIV2, + CLK_PLL3_DIV4, + CLK_PLL3_DIV8, + CLK_PLL4, + CLK_PLL5, + CLK_PLL5_DIV2, + CLK_PLL6, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_3b[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {4, 32}, +}; + +static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), + + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), + DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), + + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), + + /* Core output clk */ + DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, + dtable_3b, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, + DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), +}; + +static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { + DEF_MOD("gic", R9A07G044_CLK_GIC600, + R9A07G044_CLK_P1, + 0x514, BIT(0), (BIT(0) | BIT(1))), + DEF_MOD("ia55", R9A07G044_CLK_IA55, + R9A07G044_CLK_P1, + 0x518, (BIT(0) | BIT(1)), BIT(0)), + DEF_MOD("scif0", R9A07G044_CLK_SCIF0, + R9A07G044_CLK_P0, + 0x584, BIT(0), BIT(0)), + DEF_MOD("scif1", R9A07G044_CLK_SCIF1, + R9A07G044_CLK_P0, + 0x584, BIT(1), BIT(1)), + DEF_MOD("scif2", R9A07G044_CLK_SCIF2, + R9A07G044_CLK_P0, + 0x584, BIT(2), BIT(2)), + DEF_MOD("scif3", R9A07G044_CLK_SCIF3, + R9A07G044_CLK_P0, + 0x584, BIT(3), BIT(3)), + DEF_MOD("scif4", R9A07G044_CLK_SCIF4, + R9A07G044_CLK_P0, + 0x584, BIT(4), BIT(4)), + DEF_MOD("sci0", R9A07G044_CLK_SCI0, + R9A07G044_CLK_P0, + 0x588, BIT(0), BIT(0)), +}; + +static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A07G044_CLK_GIC600, +}; + +const struct rzg2l_cpg_info r9a07g044_cpg_info = { + /* Core Clocks */ + .core_clks = r9a07g044_core_clks, + .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a07g044_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a07g044_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), + .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1, +}; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index caa0f9414e45..558191c99b48 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -26,19 +26,135 @@ #include "rcar-cpg-lib.h" #include "rcar-gen3-cpg.h" -#define CPG_PLL0CR 0x00d8 +#define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */ + +#define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */ + +#define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */ #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 +#define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */ + #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ +/* PLL Clocks */ +struct cpg_pll_clk { + struct clk_hw hw; + void __iomem *pllcr_reg; + void __iomem *pllecr_reg; + unsigned int fixed_mult; + u32 pllecr_pllst_mask; +}; + +#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw) + +static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; + u32 val; + + val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; + mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; + + return parent_rate * mult * pll_clk->fixed_mult; +} + +static int cpg_pll_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int min_mult, max_mult, mult; + unsigned long prate; + + prate = req->best_parent_rate * pll_clk->fixed_mult; + min_mult = max(div64_ul(req->min_rate, prate), 1ULL); + max_mult = min(div64_ul(req->max_rate, prate), 128ULL); + if (max_mult < min_mult) + return -EINVAL; + + mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); + mult = clamp(mult, min_mult, max_mult); + + req->rate = prate * mult; + return 0; +} + +static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult, i; + u32 val; + + mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); + mult = clamp(mult, 1U, 128U); + + val = readl(pll_clk->pllcr_reg); + val &= ~CPG_PLLnCR_STC_MASK; + val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); + writel(val, pll_clk->pllcr_reg); + + for (i = 1000; i; i--) { + if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask) + return 0; + + cpu_relax(); + } + + return -ETIMEDOUT; +} + +static const struct clk_ops cpg_pll_clk_ops = { + .recalc_rate = cpg_pll_clk_recalc_rate, + .determine_rate = cpg_pll_clk_determine_rate, + .set_rate = cpg_pll_clk_set_rate, +}; + +static struct clk * __init cpg_pll_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + unsigned int mult, + unsigned int offset, + unsigned int index) + +{ + struct cpg_pll_clk *pll_clk; + struct clk_init_data init = {}; + struct clk *clk; + + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &cpg_pll_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll_clk->hw.init = &init; + pll_clk->pllcr_reg = base + offset; + pll_clk->pllecr_reg = base + CPG_PLLECR; + pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */ + pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); + + clk = clk_register(NULL, &pll_clk->hw); + if (IS_ERR(clk)) + kfree(pll_clk); + + return clk; +} + /* * Z Clock & Z2 Clock * * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled - * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 + * rate - rate is adjustable. + * clk->rate = (parent->rate * mult / 32 ) / fixed_div * parent - fixed parent. No clk_set_parent support */ #define CPG_FRQCRB 0x00000004 @@ -49,8 +165,9 @@ struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; void __iomem *kick_reg; - unsigned long mask; + unsigned long max_rate; /* Maximum rate for normal mode */ unsigned int fixed_div; + u32 mask; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -74,7 +191,18 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw, { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int min_mult, max_mult, mult; - unsigned long prate; + unsigned long rate, prate; + + rate = min(req->rate, req->max_rate); + if (rate <= zclk->max_rate) { + /* Set parent rate to initial value for normal modes */ + prate = zclk->max_rate; + } else { + /* Set increased parent rate for boost modes */ + prate = rate; + } + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), + prate * zclk->fixed_div); prate = req->best_parent_rate / zclk->fixed_div; min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); @@ -82,10 +210,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw, if (max_mult < min_mult) return -EINVAL; - mult = div64_ul(req->rate * 32ULL, prate); + mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); mult = clamp(mult, min_mult, max_mult); - req->rate = div_u64((u64)prate * mult, 32); + req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); return 0; } @@ -103,8 +231,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - cpg_reg_modify(zclk->reg, zclk->mask, - ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); + cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for @@ -117,7 +244,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, * * Using experimental measurements, it seems that no more than * ~10 iterations are needed, independently of the CPU rate. - * Since this value might be dependent of external xtal rate, pll1 + * Since this value might be dependent on external xtal rate, pll1 * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ @@ -153,7 +280,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, init.name = name; init.ops = &cpg_z_clk_ops; - init.flags = 0; + init.flags = CLK_SET_RATE_PARENT; init.parent_names = &parent_name; init.num_parents = 1; @@ -164,9 +291,13 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); - if (IS_ERR(clk)) + if (IS_ERR(clk)) { kfree(zclk); + return clk; + } + zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / + zclk->fixed_div; return clk; } @@ -314,16 +445,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_PLL0: /* - * PLL0 is a configurable multiplier clock. Register it as a - * fixed factor clock for now as there's no generic multiplier - * clock implementation and we currently have no need to change - * the multiplier value. + * PLL0 is implemented as a custom clock, to change the + * multiplier when cpufreq changes between normal and boost + * modes. */ - value = readl(base + CPG_PLL0CR); - mult = (((value >> 24) & 0x7f) + 1) * 2; - if (cpg_quirks & PLL_ERRATA) - mult *= 2; - break; + mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; + return cpg_pll_clk_register(core->name, __clk_get_name(parent), + base, mult, CPG_PLL0CR, 0); case CLK_TYPE_GEN3_PLL1: mult = cpg_pll_config->pll1_mult; @@ -332,16 +460,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_PLL2: /* - * PLL2 is a configurable multiplier clock. Register it as a - * fixed factor clock for now as there's no generic multiplier - * clock implementation and we currently have no need to change - * the multiplier value. + * PLL2 is implemented as a custom clock, to change the + * multiplier when cpufreq changes between normal and boost + * modes. */ - value = readl(base + CPG_PLL2CR); - mult = (((value >> 24) & 0x7f) + 1) * 2; - if (cpg_quirks & PLL_ERRATA) - mult *= 2; - break; + mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; + return cpg_pll_clk_register(core->name, __clk_get_name(parent), + base, mult, CPG_PLL2CR, 2); case CLK_TYPE_GEN3_PLL3: mult = cpg_pll_config->pll3_mult; diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c index 34a85dc95beb..9fb79bd79435 100644 --- a/drivers/clk/renesas/rcar-usb2-clock-sel.c +++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c @@ -128,10 +128,8 @@ static int rcar_usb2_clock_sel_resume(struct device *dev) static int rcar_usb2_clock_sel_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct usb2_clock_sel_priv *priv = platform_get_drvdata(pdev); of_clk_del_provider(dev->of_node); - clk_hw_unregister(&priv->hw); pm_runtime_put(dev); pm_runtime_disable(dev); @@ -164,9 +162,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) if (IS_ERR(priv->rsts)) return PTR_ERR(priv->rsts); - pm_runtime_enable(dev); - pm_runtime_get_sync(dev); - clk = devm_clk_get(dev, "usb_extal"); if (!IS_ERR(clk) && !clk_prepare_enable(clk)) { priv->extal = !!clk_get_rate(clk); @@ -183,6 +178,8 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) return -ENOENT; } + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); platform_set_drvdata(pdev, priv); dev_set_drvdata(dev, priv); @@ -190,11 +187,20 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) init.ops = &usb2_clock_sel_clock_ops; priv->hw.init = &init; - clk = clk_register(NULL, &priv->hw); - if (IS_ERR(clk)) - return PTR_ERR(clk); + ret = devm_clk_hw_register(NULL, &priv->hw); + if (ret) + goto pm_put; - return of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw); + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw); + if (ret) + goto pm_put; + + return 0; + +pm_put: + pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; } static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = { diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index fc531d35b269..21f762aa2131 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -100,13 +100,9 @@ static const u16 srcr_for_v3u[] = { 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, }; -/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) (smstpcr[i] - 0x20) - -/* Modem Module Stop Control Register offsets (r8a73a4) */ -#define MMSTPCR(i) (smstpcr[i] + 0x20) - -/* Software Reset Clearing Register offsets */ +/* + * Software Reset Clearing Register offsets + */ static const u16 srstclr[] = { 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c new file mode 100644 index 000000000000..5009b9e48b13 --- /dev/null +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on renesas-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2013 Ideas On Board SPRL + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "renesas-rzg2l-cpg.h" + +#ifdef DEBUG +#define WARN_DEBUG(x) WARN_ON(x) +#else +#define WARN_DEBUG(x) do { } while (0) +#endif + +#define DIV_RSMASK(v, s, m) ((v >> s) & m) +#define GET_SHIFT(val) ((val >> 12) & 0xff) +#define GET_WIDTH(val) ((val >> 8) & 0xf) + +#define KDIV(val) DIV_RSMASK(val, 16, 0xffff) +#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff) +#define PDIV(val) DIV_RSMASK(val, 0, 0x3f) +#define SDIV(val) DIV_RSMASK(val, 0, 0x7) + +#define CLK_ON_R(reg) (reg) +#define CLK_MON_R(reg) (0x680 - 0x500 + (reg)) +#define CLK_RST_R(reg) (0x800 - 0x500 + (reg)) +#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg)) + +#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff) +#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) +#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff) + +/** + * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data + * + * @rcdev: Reset controller entity + * @dev: CPG device + * @base: CPG register block base address + * @rmw_lock: protects register accesses + * @clks: Array containing all Core and Module Clocks + * @num_core_clks: Number of Core Clocks in clks[] + * @num_mod_clks: Number of Module Clocks in clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @notifiers: Notifier chain to save/restore clock state for system resume + * @info: Pointer to platform data + */ +struct rzg2l_cpg_priv { + struct reset_controller_dev rcdev; + struct device *dev; + void __iomem *base; + spinlock_t rmw_lock; + + struct clk **clks; + unsigned int num_core_clks; + unsigned int num_mod_clks; + unsigned int last_dt_core_clk; + + struct raw_notifier_head notifiers; + const struct rzg2l_cpg_info *info; +}; + +static void rzg2l_cpg_del_clk_provider(void *data) +{ + of_clk_del_provider(data); +} + +static struct clk * __init +rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, + struct clk **clks, + void __iomem *base, + struct rzg2l_cpg_priv *priv) +{ + struct device *dev = priv->dev; + const struct clk *parent; + const char *parent_name; + struct clk_hw *clk_hw; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + if (core->dtable) + clk_hw = clk_hw_register_divider_table(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, + core->dtable, + &priv->rmw_lock); + else + clk_hw = clk_hw_register_divider(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, &priv->rmw_lock); + + if (IS_ERR(clk_hw)) + return NULL; + + return clk_hw->clk; +} + +struct pll_clk { + struct clk_hw hw; + unsigned int conf; + unsigned int type; + void __iomem *base; + struct rzg2l_cpg_priv *priv; +}; + +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzg2l_cpg_priv *priv = pll_clk->priv; + unsigned int val1, val2; + unsigned int mult = 1; + unsigned int div = 1; + + if (pll_clk->type != CLK_TYPE_SAM_PLL) + return parent_rate; + + val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); + val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); + mult = MDIV(val1) + KDIV(val1) / 65536; + div = PDIV(val1) * (1 << SDIV(val2)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); +} + +static const struct clk_ops rzg2l_cpg_pll_ops = { + .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate, +}; + +static struct clk * __init +rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, + struct clk **clks, + void __iomem *base, + struct rzg2l_cpg_priv *priv) +{ + struct device *dev = priv->dev; + const struct clk *parent; + struct clk_init_data init; + const char *parent_name; + struct pll_clk *pll_clk; + struct clk *clk; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) { + clk = ERR_PTR(-ENOMEM); + return NULL; + } + + parent_name = __clk_get_name(parent); + init.name = core->name; + init.ops = &rzg2l_cpg_pll_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll_clk->hw.init = &init; + pll_clk->conf = core->conf; + pll_clk->base = base; + pll_clk->priv = priv; + pll_clk->type = core->type; + + clk = clk_register(NULL, &pll_clk->hw); + if (IS_ERR(clk)) + kfree(pll_clk); + + return clk; +} + +static struct clk +*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int clkidx = clkspec->args[1]; + struct rzg2l_cpg_priv *priv = data; + struct device *dev = priv->dev; + const char *type; + struct clk *clk; + + switch (clkspec->args[0]) { + case CPG_CORE: + type = "core"; + if (clkidx > priv->last_dt_core_clk) { + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[clkidx]; + break; + + case CPG_MOD: + type = "module"; + if (clkidx > priv->num_mod_clks) { + dev_err(dev, "Invalid %s clock index %u\n", type, + clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[priv->num_core_clks + clkidx]; + break; + + default: + dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); + return ERR_PTR(-EINVAL); + } + + if (IS_ERR(clk)) + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, + PTR_ERR(clk)); + else + dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", + clkspec->args[0], clkspec->args[1], clk, + clk_get_rate(clk)); + return clk; +} + +static void __init +rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, + const struct rzg2l_cpg_info *info, + struct rzg2l_cpg_priv *priv) +{ + struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent; + struct device *dev = priv->dev; + unsigned int id = core->id, div = core->div; + const char *parent_name; + + WARN_DEBUG(id >= priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + if (!core->name) { + /* Skip NULLified clock */ + return; + } + + switch (core->type) { + case CLK_TYPE_IN: + clk = of_clk_get_by_name(priv->dev->of_node, core->name); + break; + case CLK_TYPE_FF: + WARN_DEBUG(core->parent >= priv->num_core_clks); + parent = priv->clks[core->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + parent_name = __clk_get_name(parent); + clk = clk_register_fixed_factor(NULL, core->name, + parent_name, CLK_SET_RATE_PARENT, + core->mult, div); + break; + case CLK_TYPE_SAM_PLL: + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, + priv->base, priv); + break; + case CLK_TYPE_DIV: + clk = rzg2l_cpg_div_clk_register(core, priv->clks, + priv->base, priv); + break; + default: + goto fail; + }; + + if (IS_ERR_OR_NULL(clk)) + goto fail; + + dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); + priv->clks[id] = clk; + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", + core->name, PTR_ERR(clk)); +} + +/** + * struct mstp_clock - MSTP gating clock + * + * @hw: handle between common and hardware-specific interfaces + * @off: register offset + * @onoff: ON/MON bits + * @reset: reset bits + * @priv: CPG/MSTP private data + */ +struct mstp_clock { + struct clk_hw hw; + u16 off; + u8 onoff; + u8 reset; + struct rzg2l_cpg_priv *priv; +}; + +#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) + +static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mstp_clock *clock = to_mod_clock(hw); + struct rzg2l_cpg_priv *priv = clock->priv; + unsigned int reg = clock->off; + struct device *dev = priv->dev; + unsigned long flags; + unsigned int i; + u32 value; + + if (!clock->off) { + dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk); + return 0; + } + + dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, + enable ? "ON" : "OFF"); + spin_lock_irqsave(&priv->rmw_lock, flags); + + if (enable) + value = (clock->onoff << 16) | clock->onoff; + else + value = clock->onoff << 16; + writel(value, priv->base + CLK_ON_R(reg)); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (!enable) + return 0; + + for (i = 1000; i > 0; --i) { + if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff)) + break; + cpu_relax(); + } + + if (!i) { + dev_err(dev, "Failed to enable CLK_ON %p\n", + priv->base + CLK_ON_R(reg)); + return -ETIMEDOUT; + } + + return 0; +} + +static int rzg2l_mod_clock_enable(struct clk_hw *hw) +{ + return rzg2l_mod_clock_endisable(hw, true); +} + +static void rzg2l_mod_clock_disable(struct clk_hw *hw) +{ + rzg2l_mod_clock_endisable(hw, false); +} + +static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) +{ + struct mstp_clock *clock = to_mod_clock(hw); + struct rzg2l_cpg_priv *priv = clock->priv; + u32 value; + + if (!clock->off) { + dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk); + return 1; + } + + value = readl(priv->base + CLK_MON_R(clock->off)); + + return !(value & clock->onoff); +} + +static const struct clk_ops rzg2l_mod_clock_ops = { + .enable = rzg2l_mod_clock_enable, + .disable = rzg2l_mod_clock_disable, + .is_enabled = rzg2l_mod_clock_is_enabled, +}; + +static void __init +rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, + const struct rzg2l_cpg_info *info, + struct rzg2l_cpg_priv *priv) +{ + struct mstp_clock *clock = NULL; + struct device *dev = priv->dev; + unsigned int id = mod->id; + struct clk_init_data init; + struct clk *parent, *clk; + const char *parent_name; + unsigned int i; + + WARN_DEBUG(id < priv->num_core_clks); + WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + if (!mod->name) { + /* Skip NULLified clock */ + return; + } + + parent = priv->clks[mod->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); + if (!clock) { + clk = ERR_PTR(-ENOMEM); + goto fail; + } + + init.name = mod->name; + init.ops = &rzg2l_mod_clock_ops; + init.flags = CLK_SET_RATE_PARENT; + for (i = 0; i < info->num_crit_mod_clks; i++) + if (id == info->crit_mod_clks[i]) { + dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n", + mod->name); + init.flags |= CLK_IS_CRITICAL; + break; + } + + parent_name = __clk_get_name(parent); + init.parent_names = &parent_name; + init.num_parents = 1; + + clock->off = mod->off; + clock->onoff = mod->onoff; + clock->reset = mod->reset; + clock->priv = priv; + clock->hw.init = &init; + + clk = clk_register(NULL, &clock->hw); + if (IS_ERR(clk)) + goto fail; + + dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); + priv->clks[id] = clk; + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", + mod->name, PTR_ERR(clk)); + kfree(clock); +} + +#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev) + +static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 dis = info->mod_clks[id].reset; + u32 we = dis << 16; + + dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + /* Reset module */ + writel(we, priv->base + CLK_RST_R(reg)); + + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + + /* Release module from reset state */ + writel(we | dis, priv->base + CLK_RST_R(reg)); + + return 0; +} + +static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 value = info->mod_clks[id].reset << 16; + + dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); + return 0; +} + +static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 dis = info->mod_clks[id].reset; + u32 value = (dis << 16) | dis; + + dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); + return 0; +} + +static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 bitmask = info->mod_clks[id].reset; + + return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); +} + +static const struct reset_control_ops rzg2l_cpg_reset_ops = { + .reset = rzg2l_cpg_reset, + .assert = rzg2l_cpg_assert, + .deassert = rzg2l_cpg_deassert, + .status = rzg2l_cpg_status, +}; + +static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int id = reset_spec->args[0]; + + if (id >= rcdev->nr_resets) { + dev_err(rcdev->dev, "Invalid reset index %u\n", id); + return -EINVAL; + } + + return id; +} + +static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) +{ + priv->rcdev.ops = &rzg2l_cpg_reset_ops; + priv->rcdev.of_node = priv->dev->of_node; + priv->rcdev.dev = priv->dev; + priv->rcdev.of_reset_n_cells = 1; + priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate; + priv->rcdev.nr_resets = priv->num_mod_clks; + + return devm_reset_controller_register(priv->dev, &priv->rcdev); +} + +static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec) +{ + if (clkspec->args_count != 2) + return false; + + switch (clkspec->args[0]) { + case CPG_MOD: + return true; + + default: + return false; + } +} + +static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + struct device_node *np = dev->of_node; + struct of_phandle_args clkspec; + struct clk *clk; + int error; + int i = 0; + + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, + &clkspec)) { + if (rzg2l_cpg_is_pm_clk(&clkspec)) + goto found; + + of_node_put(clkspec.np); + i++; + } + + return 0; + +found: + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + + if (IS_ERR(clk)) + return PTR_ERR(clk); + + error = pm_clk_create(dev); + if (error) + goto fail_put; + + error = pm_clk_add_clk(dev, clk); + if (error) + goto fail_destroy; + + return 0; + +fail_destroy: + pm_clk_destroy(dev); +fail_put: + clk_put(clk); + return error; +} + +static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + if (!pm_clk_no_clocks(dev)) + pm_clk_destroy(dev); +} + +static int __init rzg2l_cpg_add_clk_domain(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct generic_pm_domain *genpd; + + genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = np->name; + genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | + GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev = rzg2l_cpg_attach_dev; + genpd->detach_dev = rzg2l_cpg_detach_dev; + pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + + of_genpd_add_provider_simple(np, genpd); + return 0; +} + +static int __init rzg2l_cpg_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct rzg2l_cpg_info *info; + struct rzg2l_cpg_priv *priv; + unsigned int nclks, i; + struct clk **clks; + int error; + + info = of_device_get_match_data(dev); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->info = info; + spin_lock_init(&priv->rmw_lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + nclks = info->num_total_core_clks + info->num_hw_mod_clks; + clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->clks = clks; + priv->num_core_clks = info->num_total_core_clks; + priv->num_mod_clks = info->num_hw_mod_clks; + priv->last_dt_core_clk = info->last_dt_core_clk; + + for (i = 0; i < nclks; i++) + clks[i] = ERR_PTR(-ENOENT); + + for (i = 0; i < info->num_core_clks; i++) + rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv); + + for (i = 0; i < info->num_mod_clks; i++) + rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv); + + error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv); + if (error) + return error; + + error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np); + if (error) + return error; + + error = rzg2l_cpg_add_clk_domain(dev); + if (error) + return error; + + error = rzg2l_cpg_reset_controller_register(priv); + if (error) + return error; + + return 0; +} + +static const struct of_device_id rzg2l_cpg_match[] = { +#ifdef CONFIG_CLK_R9A07G044 + { + .compatible = "renesas,r9a07g044-cpg", + .data = &r9a07g044_cpg_info, + }, +#endif + { /* sentinel */ } +}; + +static struct platform_driver rzg2l_cpg_driver = { + .driver = { + .name = "rzg2l-cpg", + .of_match_table = rzg2l_cpg_match, + }, +}; + +static int __init rzg2l_cpg_init(void) +{ + return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe); +} + +subsys_initcall(rzg2l_cpg_init); + +MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h new file mode 100644 index 000000000000..3948bdd8afc9 --- /dev/null +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __RENESAS_RZG2L_CPG_H__ +#define __RENESAS_RZG2L_CPG_H__ + +#define CPG_PL2_DDIV (0x204) +#define CPG_PL3A_DDIV (0x208) + +/* n = 0/1/2 for PLL1/4/6 */ +#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) +#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) + +#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) + +#define DDIV_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) +#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) + +/** + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + const char *name; + unsigned int id; + unsigned int parent; + unsigned int div; + unsigned int mult; + unsigned int type; + unsigned int conf; + const struct clk_div_table *dtable; + const char * const *parent_names; + int flag; + int num_parents; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_SAM_PLL, + + /* Clock with divider */ + CLK_TYPE_DIV, +}; + +#define DEF_TYPE(_name, _id, _type...) \ + { .name = _name, .id = _id, .type = _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent = _parent) +#define DEF_SAMPLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _mult, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) +#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ + .parent = _parent, .dtable = _dtable, .flag = _flag) + +/** + * struct rzg2l_mod_clk - Module Clocks definitions + * + * @name: handle between common and hardware-specific interfaces + * @id: clock index in array containing all Core and Module Clocks + * @parent: id of parent clock + * @off: register offset + * @onoff: ON/MON bits + * @reset: reset bits + */ +struct rzg2l_mod_clk { + const char *name; + unsigned int id; + unsigned int parent; + u16 off; + u8 onoff; + u8 reset; +}; + +#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \ + [_id] = { \ + .name = _name, \ + .id = MOD_CLK_BASE + _id, \ + .parent = (_parent), \ + .off = (_off), \ + .onoff = (_onoff), \ + .reset = (_reset) \ + } + +/** + * struct rzg2l_cpg_info - SoC-specific CPG Description + * + * @core_clks: Array of Core Clock definitions + * @num_core_clks: Number of entries in core_clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @num_total_core_clks: Total number of Core Clocks (exported + internal) + * + * @mod_clks: Array of Module Clock definitions + * @num_mod_clks: Number of entries in mod_clks[] + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware + * + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that + * should not be disabled without a knowledgeable driver + * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + */ +struct rzg2l_cpg_info { + /* Core Clocks */ + const struct cpg_core_clk *core_clks; + unsigned int num_core_clks; + unsigned int last_dt_core_clk; + unsigned int num_total_core_clks; + + /* Module Clocks */ + const struct rzg2l_mod_clk *mod_clks; + unsigned int num_mod_clks; + unsigned int num_hw_mod_clks; + + /* Critical Module Clocks that should not be disabled */ + const unsigned int *crit_mod_clks; + unsigned int num_crit_mod_clks; +}; + +extern const struct rzg2l_cpg_info r9a07g044_cpg_info; + +#endif diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 91d56ad45817..614845cc5b4a 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -259,7 +259,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKGATE_CON(1), 13, GFLAGS, &rk3036_uart2_fracmux), - COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, + COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0, RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 946ea2f45bf3..75ca855e720d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 10, GFLAGS), - COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 11, GFLAGS), - COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 12, GFLAGS), - COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 13, GFLAGS), COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 11, GFLAGS), + COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 12, GFLAGS), + COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 13, GFLAGS), + COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, RK3568_CLKGATE_CON(35), 14, GFLAGS), COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 571cee7bbfdc..7aa45cc70287 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -271,17 +271,24 @@ struct rockchip_clk_provider { struct rockchip_pll_rate_table { unsigned long rate; - unsigned int nr; - unsigned int nf; - unsigned int no; - unsigned int nb; - /* for RK3036/RK3399 */ - unsigned int fbdiv; - unsigned int postdiv1; - unsigned int refdiv; - unsigned int postdiv2; - unsigned int dsmpd; - unsigned int frac; + union { + struct { + /* for RK3066 */ + unsigned int nr; + unsigned int nf; + unsigned int no; + unsigned int nb; + }; + struct { + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; + }; + }; }; /** diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 0d79ba31a793..80a288c59e56 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -564,7 +564,7 @@ static int __prci_register_clocks(struct device *dev, struct __prci_data *pd, } /** - * sifive_prci_init() - initialize prci data and check parent count + * sifive_prci_probe() - initialize prci data and check parent count * @pdev: platform device pointer for the prci * * Return: 0 upon success or a negative error code upon failure. diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 92a6d740a799..1cb21ea79c64 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -177,6 +177,8 @@ static const struct clk_parent_data emac_mux[] = { .name = "emaca_free_clk", }, { .fw_name = "emacb_free_clk", .name = "emacb_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, }; static const struct clk_parent_data noc_mux[] = { @@ -186,6 +188,41 @@ static const struct clk_parent_data noc_mux[] = { .name = "boot_clk", }, }; +static const struct clk_parent_data sdmmc_mux[] = { + { .fw_name = "sdmmc_free_clk", + .name = "sdmmc_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data s2f_user1_mux[] = { + { .fw_name = "s2f_user1_free_clk", + .name = "s2f_user1_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data psi_mux[] = { + { .fw_name = "psi_ref_free_clk", + .name = "psi_ref_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data gpio_db_mux[] = { + { .fw_name = "gpio_db_free_clk", + .name = "gpio_db_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emac_ptp_mux[] = { + { .fw_name = "emac_ptp_free_clk", + .name = "emac_ptp_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + /* clocks in AO (always on) controller */ static const struct stratix10_pll_clock agilex_pll_clks[] = { { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, @@ -222,11 +259,9 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), 0, 0x3C, 0, 0, 0}, { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), - 0, 0x40, 0, 0, 1}, - { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, - 0, 4, 0, 0}, - { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), - 0, 0, 0, 0x30, 1}, + 0, 0x40, 0, 0, 0}, + { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0, 4, 0x30, 1}, { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0}, { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), @@ -236,7 +271,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3}, { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, - ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4}, + ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0}, { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, @@ -252,24 +287,24 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 0, 0, 0, 0, 0, 0, 4}, { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24, 0, 0, 0, 0, 0, 0, 2}, - { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24, - 1, 0x44, 0, 2, 0, 0, 0}, - { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24, - 2, 0x44, 8, 2, 0, 0, 0}, + { AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, + 1, 0x44, 0, 2, 0x30, 1, 0}, + { AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, + 2, 0x44, 8, 2, 0x30, 1, 0}, /* * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them * being the SP timers, thus cannot get gated. */ - { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24, - 3, 0x44, 16, 2, 0, 0, 0}, - { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24, - 4, 0x44, 24, 2, 0, 0, 0}, - { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24, - 4, 0x44, 26, 2, 0, 0, 0}, + { AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24, + 3, 0x44, 16, 2, 0x30, 1, 0}, + { AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, + 4, 0x44, 24, 2, 0x30, 1, 0}, + { AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, + 4, 0x44, 26, 2, 0x30, 1, 0}, { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4, 0x44, 28, 1, 0, 0, 0}, - { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24, - 5, 0, 0, 0, 0, 0, 0}, + { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, + 5, 0, 0, 0, 0x30, 1, 0}, { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24, 6, 0, 0, 0, 0, 0, 0}, { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, @@ -278,16 +313,16 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 1, 0, 0, 0, 0x94, 27, 0}, { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0}, - { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C, - 3, 0, 0, 0, 0, 0, 0}, - { AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C, - 4, 0x98, 0, 16, 0, 0, 0}, - { AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C, - 5, 0, 0, 0, 0, 0, 4}, - { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C, - 6, 0, 0, 0, 0, 0, 0}, - { AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C, - 7, 0, 0, 0, 0, 0, 0}, + { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, + 3, 0, 0, 0, 0x88, 2, 0}, + { AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C, + 4, 0x98, 0, 16, 0x88, 3, 0}, + { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C, + 5, 0, 0, 0, 0x88, 4, 4}, + { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, + 6, 0, 0, 0, 0x88, 5, 0}, + { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C, + 7, 0, 0, 0, 0x88, 6, 0}, { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 8, 0, 0, 0, 0, 0, 0}, { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, @@ -366,7 +401,7 @@ static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int i; for (i = 0; i < nums; i++) { - hw_clk = s10_register_gate(&clks[i], base); + hw_clk = agilex_register_gate(&clks[i], base); if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c index b84f2627551e..32567795765f 100644 --- a/drivers/clk/socfpga/clk-gate-s10.c +++ b/drivers/clk/socfpga/clk-gate-s10.c @@ -11,6 +11,13 @@ #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk" #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) +#define SOCFPGA_EMAC0_CLK "emac0_clk" +#define SOCFPGA_EMAC1_CLK "emac1_clk" +#define SOCFPGA_EMAC2_CLK "emac2_clk" +#define AGILEX_BYPASS_OFFSET 0xC +#define STRATIX10_BYPASS_OFFSET 0x2C +#define BOOTCLK_BYPASS 2 + static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { @@ -44,14 +51,61 @@ static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk, static u8 socfpga_gate_get_parent(struct clk_hw *hwclk) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - u32 mask; + u32 mask, second_bypass; u8 parent = 0; + const char *name = clk_hw_get_name(hwclk); if (socfpgaclk->bypass_reg) { mask = (0x1 << socfpgaclk->bypass_shift); parent = ((readl(socfpgaclk->bypass_reg) & mask) >> socfpgaclk->bypass_shift); } + + if (streq(name, SOCFPGA_EMAC0_CLK) || + streq(name, SOCFPGA_EMAC1_CLK) || + streq(name, SOCFPGA_EMAC2_CLK)) { + second_bypass = readl(socfpgaclk->bypass_reg - + STRATIX10_BYPASS_OFFSET); + /* EMACA bypass to bootclk @0xB0 offset */ + if (second_bypass & 0x1) + if (parent == 0) /* only applicable if parent is maca */ + parent = BOOTCLK_BYPASS; + + if (second_bypass & 0x2) + if (parent == 1) /* only applicable if parent is macb */ + parent = BOOTCLK_BYPASS; + } + return parent; +} + +static u8 socfpga_agilex_gate_get_parent(struct clk_hw *hwclk) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); + u32 mask, second_bypass; + u8 parent = 0; + const char *name = clk_hw_get_name(hwclk); + + if (socfpgaclk->bypass_reg) { + mask = (0x1 << socfpgaclk->bypass_shift); + parent = ((readl(socfpgaclk->bypass_reg) & mask) >> + socfpgaclk->bypass_shift); + } + + if (streq(name, SOCFPGA_EMAC0_CLK) || + streq(name, SOCFPGA_EMAC1_CLK) || + streq(name, SOCFPGA_EMAC2_CLK)) { + second_bypass = readl(socfpgaclk->bypass_reg - + AGILEX_BYPASS_OFFSET); + /* EMACA bypass to bootclk @0x88 offset */ + if (second_bypass & 0x1) + if (parent == 0) /* only applicable if parent is maca */ + parent = BOOTCLK_BYPASS; + + if (second_bypass & 0x2) + if (parent == 1) /* only applicable if parent is macb */ + parent = BOOTCLK_BYPASS; + } + return parent; } @@ -60,6 +114,11 @@ static struct clk_ops gateclk_ops = { .get_parent = socfpga_gate_get_parent, }; +static const struct clk_ops agilex_gateclk_ops = { + .recalc_rate = socfpga_gate_clk_recalc_rate, + .get_parent = socfpga_agilex_gate_get_parent, +}; + static const struct clk_ops dbgclk_ops = { .recalc_rate = socfpga_dbg_clk_recalc_rate, .get_parent = socfpga_gate_get_parent, @@ -122,3 +181,61 @@ struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void _ } return hw_clk; } + +struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) +{ + struct clk_hw *hw_clk; + struct socfpga_gate_clk *socfpga_clk; + struct clk_init_data init; + const char *parent_name = clks->parent_name; + int ret; + + socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); + if (!socfpga_clk) + return NULL; + + socfpga_clk->hw.reg = regbase + clks->gate_reg; + socfpga_clk->hw.bit_idx = clks->gate_idx; + + gateclk_ops.enable = clk_gate_ops.enable; + gateclk_ops.disable = clk_gate_ops.disable; + + socfpga_clk->fixed_div = clks->fixed_div; + + if (clks->div_reg) + socfpga_clk->div_reg = regbase + clks->div_reg; + else + socfpga_clk->div_reg = NULL; + + socfpga_clk->width = clks->div_width; + socfpga_clk->shift = clks->div_offset; + + if (clks->bypass_reg) + socfpga_clk->bypass_reg = regbase + clks->bypass_reg; + else + socfpga_clk->bypass_reg = NULL; + socfpga_clk->bypass_shift = clks->bypass_shift; + + if (streq(clks->name, "cs_pdbg_clk")) + init.ops = &dbgclk_ops; + else + init.ops = &agilex_gateclk_ops; + + init.name = clks->name; + init.flags = clks->flags; + + init.num_parents = clks->num_parents; + init.parent_names = parent_name ? &parent_name : NULL; + if (init.parent_names == NULL) + init.parent_data = clks->parent_data; + socfpga_clk->hw.hw.init = &init; + + hw_clk = &socfpga_clk->hw.hw; + + ret = clk_hw_register(NULL, &socfpga_clk->hw.hw); + if (ret) { + kfree(socfpga_clk); + return ERR_PTR(ret); + } + return hw_clk; +} diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index e5a5fef76df7..cbabde2b476b 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -64,16 +64,21 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk) { struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); u32 clk_src, mask; - u8 parent; + u8 parent = 0; + /* handle the bypass first */ if (socfpgaclk->bypass_reg) { mask = (0x1 << socfpgaclk->bypass_shift); parent = ((readl(socfpgaclk->bypass_reg) & mask) >> socfpgaclk->bypass_shift); - } else { + if (parent) + return parent; + } + + if (socfpgaclk->hw.reg) { clk_src = readl(socfpgaclk->hw.reg); parent = (clk_src >> CLK_MGR_FREE_SHIFT) & - CLK_MGR_FREE_MASK; + CLK_MGR_FREE_MASK; } return parent; } diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index dcb573d44034..127cc849c5ee 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -80,7 +80,6 @@ static __init struct clk_hw *__socfpga_pll_init(struct device_node *node, const char *parent_name[SOCFPGA_MAX_PARENTS]; struct clk_init_data init; struct device_node *clkmgr_np; - int rc; int err; of_property_read_u32(node, "reg", ®); @@ -114,7 +113,7 @@ static __init struct clk_hw *__socfpga_pll_init(struct device_node *node, kfree(pll_clk); return ERR_PTR(err); } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); + of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); return hw_clk; } diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index f0bd77138ecb..b532d51faaee 100644 --- a/drivers/clk/socfpga/clk-s10.c +++ b/drivers/clk/socfpga/clk-s10.c @@ -144,6 +144,41 @@ static const struct clk_parent_data mpu_free_mux[] = { .name = "f2s-free-clk", }, }; +static const struct clk_parent_data sdmmc_mux[] = { + { .fw_name = "sdmmc_free_clk", + .name = "sdmmc_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data s2f_user1_mux[] = { + { .fw_name = "s2f_user1_free_clk", + .name = "s2f_user1_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data psi_mux[] = { + { .fw_name = "psi_ref_free_clk", + .name = "psi_ref_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data gpio_db_mux[] = { + { .fw_name = "gpio_db_free_clk", + .name = "gpio_db_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emac_ptp_mux[] = { + { .fw_name = "emac_ptp_free_clk", + .name = "emac_ptp_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + /* clocks in AO (always on) controller */ static const struct stratix10_pll_clock s10_pll_clks[] = { { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, @@ -167,7 +202,7 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = { { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), 0, 0x48, 0, 0, 0}, { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), - 0, 0x4C, 0, 0, 0}, + 0, 0x4C, 0, 0x3C, 1}, { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0, 0x50, 0, 0, 0}, { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0, @@ -200,10 +235,8 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = { 0, 0xD4, 0, 0, 0}, { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0, 0xD8, 0, 0, 0}, - { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, - 0, 4, 0, 0}, - { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), - 0, 0, 0, 0x3C, 1}, + { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0, 4, 0x3C, 1}, { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), 0, 0, 2, 0xB0, 0}, { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), @@ -227,20 +260,20 @@ static const struct stratix10_gate_clock s10_gate_clks[] = { 0, 0, 0, 0, 0, 0, 4}, { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30, 0, 0, 0, 0, 0, 0, 2}, - { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30, - 1, 0x70, 0, 2, 0, 0, 0}, - { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30, - 2, 0x70, 8, 2, 0, 0, 0}, - { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30, - 3, 0x70, 16, 2, 0, 0, 0}, - { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30, - 4, 0x70, 24, 2, 0, 0, 0}, - { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30, - 4, 0x70, 26, 2, 0, 0, 0}, + { STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, + 1, 0x70, 0, 2, 0x3C, 1, 0}, + { STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, + 2, 0x70, 8, 2, 0x3C, 1, 0}, + { STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30, + 3, 0x70, 16, 2, 0x3C, 1, 0}, + { STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, + 4, 0x70, 24, 2, 0x3C, 1, 0}, + { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, + 4, 0x70, 26, 2, 0x3C, 1, 0}, { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30, 4, 0x70, 28, 1, 0, 0, 0}, - { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30, - 5, 0, 0, 0, 0, 0, 0}, + { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, + 5, 0, 0, 0, 0x3C, 1, 0}, { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30, 6, 0, 0, 0, 0, 0, 0}, { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, @@ -249,16 +282,16 @@ static const struct stratix10_gate_clock s10_gate_clks[] = { 1, 0, 0, 0, 0xDC, 27, 0}, { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 2, 0, 0, 0, 0xDC, 28, 0}, - { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4, - 3, 0, 0, 0, 0, 0, 0}, - { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4, - 4, 0xE0, 0, 16, 0, 0, 0}, - { STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4, - 5, 0, 0, 0, 0, 0, 4}, - { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4, - 6, 0, 0, 0, 0, 0, 0}, - { STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4, - 7, 0, 0, 0, 0, 0, 0}, + { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0xA4, + 3, 0, 0, 0, 0xB0, 2, 0}, + { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0xA4, + 4, 0xE0, 0, 16, 0xB0, 3, 0}, + { STRATIX10_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0xA4, + 5, 0, 0, 0, 0xB0, 4, 4}, + { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0xA4, + 6, 0, 0, 0, 0xB0, 5, 0}, + { STRATIX10_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0xA4, + 7, 0, 0, 0, 0xB0, 6, 0}, { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 8, 0, 0, 0, 0, 0, 0}, { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h index 61eaf3a41fbb..75234e0783e1 100644 --- a/drivers/clk/socfpga/stratix10-clk.h +++ b/drivers/clk/socfpga/stratix10-clk.h @@ -85,4 +85,6 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c void __iomem *reg); struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *reg); +struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, + void __iomem *reg); #endif /* __STRATIX10_CLK_H */ diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c index 55873d4b7603..7ae4f656191e 100644 --- a/drivers/clk/st/clk-flexgen.c +++ b/drivers/clk/st/clk-flexgen.c @@ -16,9 +16,16 @@ #include #include +struct clkgen_clk_out { + const char *name; + unsigned long flags; +}; + struct clkgen_data { unsigned long flags; bool mode; + const struct clkgen_clk_out *outputs; + const unsigned int outputs_nb; }; struct flexgen { @@ -295,6 +302,290 @@ static const struct clkgen_data clkgen_video = { .mode = 1, }; +static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = { + /* This clk needs to be on so that memory interface is accessible */ + { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL }, +}; + +static const struct clkgen_data clkgen_stih407_a0 = { + .outputs = clkgen_stih407_a0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = { + /* Those clks need to be on so that memory interface is accessible */ + { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL }, + { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL }, +}; + +static const struct clkgen_data clkgen_stih410_a0 = { + .outputs = clkgen_stih410_a0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = { + { .name = "clk-icn-gpu", }, + { .name = "clk-fdma", }, + { .name = "clk-nand", }, + { .name = "clk-hva", }, + { .name = "clk-proc-stfe", }, + { .name = "clk-proc-tp", }, + { .name = "clk-rx-icn-dmu", }, + { .name = "clk-rx-icn-hva", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, + { .name = "clk-mmc-0", }, + { .name = "clk-mmc-1", }, + { .name = "clk-jpegdec", }, + /* This clk needs to be on to keep A9 running */ + { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL }, + { .name = "clk-ic-bdisp-0", }, + { .name = "clk-ic-bdisp-1", }, + { .name = "clk-pp-dmu", }, + { .name = "clk-vid-dmu", }, + { .name = "clk-dss-lpc", }, + { .name = "clk-st231-aud-0", }, + { .name = "clk-st231-gp-1", }, + { .name = "clk-st231-dmu", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, + { .name = "clk-tx-icn-disp-1", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, + { .name = "clk-stfe-frc2", }, + { .name = "clk-eth-phy", }, + { .name = "clk-eth-ref-phyclk", }, + { .name = "clk-flash-promip", }, + { .name = "clk-main-disp", }, + { .name = "clk-aux-disp", }, + { .name = "clk-compo-dvp", }, +}; + +static const struct clkgen_data clkgen_stih407_c0 = { + .outputs = clkgen_stih407_c0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = { + { .name = "clk-icn-gpu", }, + { .name = "clk-fdma", }, + { .name = "clk-nand", }, + { .name = "clk-hva", }, + { .name = "clk-proc-stfe", }, + { .name = "clk-proc-tp", }, + { .name = "clk-rx-icn-dmu", }, + { .name = "clk-rx-icn-hva", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, + { .name = "clk-mmc-0", }, + { .name = "clk-mmc-1", }, + { .name = "clk-jpegdec", }, + /* This clk needs to be on to keep A9 running */ + { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL }, + { .name = "clk-ic-bdisp-0", }, + { .name = "clk-ic-bdisp-1", }, + { .name = "clk-pp-dmu", }, + { .name = "clk-vid-dmu", }, + { .name = "clk-dss-lpc", }, + { .name = "clk-st231-aud-0", }, + { .name = "clk-st231-gp-1", }, + { .name = "clk-st231-dmu", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, + { .name = "clk-tx-icn-disp-1", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, + { .name = "clk-stfe-frc2", }, + { .name = "clk-eth-phy", }, + { .name = "clk-eth-ref-phyclk", }, + { .name = "clk-flash-promip", }, + { .name = "clk-main-disp", }, + { .name = "clk-aux-disp", }, + { .name = "clk-compo-dvp", }, + { .name = "clk-tx-icn-hades", }, + { .name = "clk-rx-icn-hades", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL }, + { .name = "clk-pp-hades", }, + { .name = "clk-clust-hades", }, + { .name = "clk-hwpe-hades", }, + { .name = "clk-fc-hades", }, +}; + +static const struct clkgen_data clkgen_stih410_c0 = { + .outputs = clkgen_stih410_c0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih410_c0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih418_c0_clk_out[] = { + { .name = "clk-icn-gpu", }, + { .name = "clk-fdma", }, + { .name = "clk-nand", }, + { .name = "clk-hva", }, + { .name = "clk-proc-stfe", }, + { .name = "clk-tp", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-rx-icn-dmu", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-rx-icn-hva", .flags = CLK_IS_CRITICAL }, + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, + { .name = "clk-mmc-0", }, + { .name = "clk-mmc-1", }, + { .name = "clk-jpegdec", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-reg", .flags = CLK_IS_CRITICAL }, + { .name = "clk-proc-bdisp-0", }, + { .name = "clk-proc-bdisp-1", }, + { .name = "clk-pp-dmu", }, + { .name = "clk-vid-dmu", }, + { .name = "clk-dss-lpc", }, + { .name = "clk-st231-aud-0", }, + { .name = "clk-st231-gp-1", }, + { .name = "clk-st231-dmu", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-tx-icn-1", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, + { .name = "clk-stfe-frc2", }, + { .name = "clk-eth-phyref", }, + { .name = "clk-eth-ref-phyclk", }, + { .name = "clk-flash-promip", }, + { .name = "clk-main-disp", }, + { .name = "clk-aux-disp", }, + { .name = "clk-compo-dvp", }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-tx-icn-hades", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-rx-icn-hades", .flags = CLK_IS_CRITICAL }, + /* This clk needs to be on to keep bus interconnect alive */ + { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL }, + { .name = "clk-pp-hevc", }, + { .name = "clk-clust-hevc", }, + { .name = "clk-hwpe-hevc", }, + { .name = "clk-fc-hevc", }, + { .name = "clk-proc-mixer", }, + { .name = "clk-proc-sc", }, + { .name = "clk-avsp-hevc", }, +}; + +static const struct clkgen_data clkgen_stih418_c0 = { + .outputs = clkgen_stih418_c0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih418_c0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih407_d0_clk_out[] = { + { .name = "clk-pcm-0", }, + { .name = "clk-pcm-1", }, + { .name = "clk-pcm-2", }, + { .name = "clk-spdiff", }, +}; + +static const struct clkgen_data clkgen_stih407_d0 = { + .flags = CLK_SET_RATE_PARENT, + .outputs = clkgen_stih407_d0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih410_d0_clk_out[] = { + { .name = "clk-pcm-0", }, + { .name = "clk-pcm-1", }, + { .name = "clk-pcm-2", }, + { .name = "clk-spdiff", }, + { .name = "clk-pcmr10-master", }, + { .name = "clk-usb2-phy", }, +}; + +static const struct clkgen_data clkgen_stih410_d0 = { + .flags = CLK_SET_RATE_PARENT, + .outputs = clkgen_stih410_d0_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih410_d0_clk_out), +}; + +static const struct clkgen_clk_out clkgen_stih407_d2_clk_out[] = { + { .name = "clk-pix-main-disp", }, + { .name = "clk-pix-pip", }, + { .name = "clk-pix-gdp1", }, + { .name = "clk-pix-gdp2", }, + { .name = "clk-pix-gdp3", }, + { .name = "clk-pix-gdp4", }, + { .name = "clk-pix-aux-disp", }, + { .name = "clk-denc", }, + { .name = "clk-pix-hddac", }, + { .name = "clk-hddac", }, + { .name = "clk-sddac", }, + { .name = "clk-pix-dvo", }, + { .name = "clk-dvo", }, + { .name = "clk-pix-hdmi", }, + { .name = "clk-tmds-hdmi", }, + { .name = "clk-ref-hdmiphy", }, +}; + +static const struct clkgen_data clkgen_stih407_d2 = { + .outputs = clkgen_stih407_d2_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d2_clk_out), + .flags = CLK_SET_RATE_PARENT, + .mode = 1, +}; + +static const struct clkgen_clk_out clkgen_stih418_d2_clk_out[] = { + { .name = "clk-pix-main-disp", }, + { .name = "", }, + { .name = "", }, + { .name = "", }, + { .name = "", }, + { .name = "clk-tmds-hdmi-div2", }, + { .name = "clk-pix-aux-disp", }, + { .name = "clk-denc", }, + { .name = "clk-pix-hddac", }, + { .name = "clk-hddac", }, + { .name = "clk-sddac", }, + { .name = "clk-pix-dvo", }, + { .name = "clk-dvo", }, + { .name = "clk-pix-hdmi", }, + { .name = "clk-tmds-hdmi", }, + { .name = "clk-ref-hdmiphy", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "", }, { .name = "", }, { .name = "", }, + { .name = "clk-vp9", }, +}; + +static const struct clkgen_data clkgen_stih418_d2 = { + .outputs = clkgen_stih418_d2_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih418_d2_clk_out), + .flags = CLK_SET_RATE_PARENT, + .mode = 1, +}; + +static const struct clkgen_clk_out clkgen_stih407_d3_clk_out[] = { + { .name = "clk-stfe-frc1", }, + { .name = "clk-tsout-0", }, + { .name = "clk-tsout-1", }, + { .name = "clk-mchi", }, + { .name = "clk-vsens-compo", }, + { .name = "clk-frc1-remote", }, + { .name = "clk-lpc-0", }, + { .name = "clk-lpc-1", }, +}; + +static const struct clkgen_data clkgen_stih407_d3 = { + .outputs = clkgen_stih407_d3_clk_out, + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d3_clk_out), +}; + static const struct of_device_id flexgen_of_match[] = { { .compatible = "st,flexgen-audio", @@ -304,6 +595,46 @@ static const struct of_device_id flexgen_of_match[] = { .compatible = "st,flexgen-video", .data = &clkgen_video, }, + { + .compatible = "st,flexgen-stih407-a0", + .data = &clkgen_stih407_a0, + }, + { + .compatible = "st,flexgen-stih410-a0", + .data = &clkgen_stih410_a0, + }, + { + .compatible = "st,flexgen-stih407-c0", + .data = &clkgen_stih407_c0, + }, + { + .compatible = "st,flexgen-stih410-c0", + .data = &clkgen_stih410_c0, + }, + { + .compatible = "st,flexgen-stih418-c0", + .data = &clkgen_stih418_c0, + }, + { + .compatible = "st,flexgen-stih407-d0", + .data = &clkgen_stih407_d0, + }, + { + .compatible = "st,flexgen-stih410-d0", + .data = &clkgen_stih410_d0, + }, + { + .compatible = "st,flexgen-stih407-d2", + .data = &clkgen_stih407_d2, + }, + { + .compatible = "st,flexgen-stih418-d2", + .data = &clkgen_stih418_d2, + }, + { + .compatible = "st,flexgen-stih407-d3", + .data = &clkgen_stih407_d3, + }, {} }; @@ -320,6 +651,7 @@ static void __init st_of_flexgen_setup(struct device_node *np) unsigned long flex_flags = 0; int ret; bool clk_mode = 0; + const char *clk_name; pnode = of_get_parent(np); if (!pnode) @@ -347,13 +679,17 @@ static void __init st_of_flexgen_setup(struct device_node *np) if (!clk_data) goto err; - ret = of_property_count_strings(np, "clock-output-names"); - if (ret <= 0) { - pr_err("%s: Failed to get number of output clocks (%d)", - __func__, clk_data->clk_num); - goto err; - } - clk_data->clk_num = ret; + /* First try to get output information from the compatible data */ + if (!data || !data->outputs_nb || !data->outputs) { + ret = of_property_count_strings(np, "clock-output-names"); + if (ret <= 0) { + pr_err("%s: Failed to get number of output clocks (%d)", + __func__, clk_data->clk_num); + goto err; + } + clk_data->clk_num = ret; + } else + clk_data->clk_num = data->outputs_nb; clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), GFP_KERNEL); @@ -368,16 +704,19 @@ static void __init st_of_flexgen_setup(struct device_node *np) for (i = 0; i < clk_data->clk_num; i++) { struct clk *clk; - const char *clk_name; - if (of_property_read_string_index(np, "clock-output-names", - i, &clk_name)) { - break; + if (!data || !data->outputs_nb || !data->outputs) { + if (of_property_read_string_index(np, + "clock-output-names", + i, &clk_name)) + break; + flex_flags &= ~CLK_IS_CRITICAL; + of_clk_detect_critical(np, i, &flex_flags); + } else { + clk_name = data->outputs[i].name; + flex_flags = data->flags | data->outputs[i].flags; } - flex_flags &= ~CLK_IS_CRITICAL; - of_clk_detect_critical(np, i, &flex_flags); - /* * If we read an empty clock name then the output is unused */ diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index dd6062e043e0..164285d6be97 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -66,6 +66,16 @@ struct clkgen_quadfs_data { unsigned long *); }; +struct clkgen_clk_out { + const char *name; + unsigned long flags; +}; + +struct clkgen_quadfs_data_clks { + struct clkgen_quadfs_data *data; + const struct clkgen_clk_out *outputs; +}; + static const struct clk_ops st_quadfs_pll_c32_ops; static int clk_fs660c32_dig_get_params(unsigned long input, @@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = { .get_rate = clk_fs660c32_dig_get_rate, }; +static const struct clkgen_clk_out st_fs660c32_C_clks[] = { + { .name = "clk-s-c0-fs0-ch0", }, + { .name = "clk-s-c0-fs0-ch1", }, + { .name = "clk-s-c0-fs0-ch2", }, + { .name = "clk-s-c0-fs0-ch3", }, +}; + +static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = { + .data = (struct clkgen_quadfs_data *)&st_fs660c32_C, + .outputs = st_fs660c32_C_clks, +}; + static const struct clkgen_quadfs_data st_fs660c32_D = { .nrst_present = true, .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0), @@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = { .get_params = clk_fs660c32_dig_get_params, .get_rate = clk_fs660c32_dig_get_rate,}; +static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = { + .data = (struct clkgen_quadfs_data *)&st_fs660c32_D, +}; + +static const struct clkgen_clk_out st_fs660c32_D0_clks[] = { + { .name = "clk-s-d0-fs0-ch0", }, + { .name = "clk-s-d0-fs0-ch1", }, + { .name = "clk-s-d0-fs0-ch2", }, + { .name = "clk-s-d0-fs0-ch3", }, +}; + +static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = { + .data = (struct clkgen_quadfs_data *)&st_fs660c32_D, + .outputs = st_fs660c32_D0_clks, +}; + +static const struct clkgen_clk_out st_fs660c32_D2_clks[] = { + { .name = "clk-s-d2-fs0-ch0", }, + { .name = "clk-s-d2-fs0-ch1", }, + { .name = "clk-s-d2-fs0-ch2", }, + { .name = "clk-s-d2-fs0-ch3", }, +}; + +static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = { + .data = (struct clkgen_quadfs_data *)&st_fs660c32_D, + .outputs = st_fs660c32_D2_clks, +}; + +static const struct clkgen_clk_out st_fs660c32_D3_clks[] = { + { .name = "clk-s-d3-fs0-ch0", }, + { .name = "clk-s-d3-fs0-ch1", }, + { .name = "clk-s-d3-fs0-ch2", }, + { .name = "clk-s-d3-fs0-ch3", }, +}; + +static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = { + .data = (struct clkgen_quadfs_data *)&st_fs660c32_D, + .outputs = st_fs660c32_D3_clks, +}; + /** * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor * @@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth( static void __init st_of_create_quadfs_fsynths( struct device_node *np, const char *pll_name, - struct clkgen_quadfs_data *quadfs, void __iomem *reg, + struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg, spinlock_t *lock) { struct clk_onecell_data *clk_data; @@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths( const char *clk_name; unsigned long flags = 0; - if (of_property_read_string_index(np, "clock-output-names", - fschan, &clk_name)) { - break; + if (quadfs->outputs) { + clk_name = quadfs->outputs[fschan].name; + flags = quadfs->outputs[fschan].flags; + } else { + if (of_property_read_string_index(np, + "clock-output-names", + fschan, &clk_name)) + break; + of_clk_detect_critical(np, fschan, &flags); } /* @@ -892,10 +960,8 @@ static void __init st_of_create_quadfs_fsynths( if (*clk_name == '\0') continue; - of_clk_detect_critical(np, fschan, &flags); - clk = st_clk_register_quadfs_fsynth(clk_name, pll_name, - quadfs, reg, fschan, + quadfs->data, reg, fschan, flags, lock); /* @@ -915,7 +981,7 @@ static void __init st_of_create_quadfs_fsynths( } static void __init st_of_quadfs_setup(struct device_node *np, - struct clkgen_quadfs_data *data) + struct clkgen_quadfs_data_clks *datac) { struct clk *clk; const char *pll_name, *clk_parent_name; @@ -940,7 +1006,7 @@ static void __init st_of_quadfs_setup(struct device_node *np, spin_lock_init(lock); - clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, data, + clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, datac->data, reg, lock); if (IS_ERR(clk)) goto err_exit; @@ -950,7 +1016,7 @@ static void __init st_of_quadfs_setup(struct device_node *np, __clk_get_name(clk_get_parent(clk)), (unsigned int)clk_get_rate(clk)); - st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock); + st_of_create_quadfs_fsynths(np, pll_name, datac, reg, lock); err_exit: kfree(pll_name); /* No longer need local copy of the PLL name */ @@ -958,12 +1024,35 @@ err_exit: static void __init st_of_quadfs660C_setup(struct device_node *np) { - st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_C); + st_of_quadfs_setup(np, + (struct clkgen_quadfs_data_clks *) &st_fs660c32_C_data); } CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup); static void __init st_of_quadfs660D_setup(struct device_node *np) { - st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_D); + st_of_quadfs_setup(np, + (struct clkgen_quadfs_data_clks *) &st_fs660c32_D_data); } CLK_OF_DECLARE(quadfs660D, "st,quadfs", st_of_quadfs660D_setup); + +static void __init st_of_quadfs660D0_setup(struct device_node *np) +{ + st_of_quadfs_setup(np, + (struct clkgen_quadfs_data_clks *) &st_fs660c32_D0_data); +} +CLK_OF_DECLARE(quadfs660D0, "st,quadfs-d0", st_of_quadfs660D0_setup); + +static void __init st_of_quadfs660D2_setup(struct device_node *np) +{ + st_of_quadfs_setup(np, + (struct clkgen_quadfs_data_clks *) &st_fs660c32_D2_data); +} +CLK_OF_DECLARE(quadfs660D2, "st,quadfs-d2", st_of_quadfs660D2_setup); + +static void __init st_of_quadfs660D3_setup(struct device_node *np) +{ + st_of_quadfs_setup(np, + (struct clkgen_quadfs_data_clks *) &st_fs660c32_D3_data); +} +CLK_OF_DECLARE(quadfs660D3, "st,quadfs-d3", st_of_quadfs660D3_setup); diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 119c5b33080c..b36e4d803636 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -57,6 +57,17 @@ struct clkgen_pll_data { const struct clk_ops *ops; }; +struct clkgen_clk_out { + const char *name; + unsigned long flags; +}; + +struct clkgen_pll_data_clks { + struct clkgen_pll_data *data; + const struct clkgen_clk_out *outputs; +}; + + static const struct clk_ops stm_pll3200c32_ops; static const struct clk_ops stm_pll3200c32_a9_ops; static const struct clk_ops stm_pll4600c28_ops; @@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = { .ops = &stm_pll3200c32_ops, }; +static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, +}; + +static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = { + { .name = "clk-s-a0-pll-odf-0", }, +}; + +static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, + .outputs = st_pll3200c32_ax_0_clks, +}; + +static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = { + { .name = "clk-s-c0-pll0-odf-0", }, +}; + +static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, + .outputs = st_pll3200c32_cx_0_clks, +}; + static const struct clkgen_pll_data st_pll3200c32_cx_1 = { /* 407 C0 PLL1 */ .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), @@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = { .ops = &stm_pll3200c32_ops, }; +static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1, +}; + +static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = { + { .name = "clk-s-c0-pll1-odf-0", }, +}; + +static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1, + .outputs = st_pll3200c32_cx_1_clks, +}; + static const struct clkgen_pll_data st_pll3200c32_407_a9 = { /* 407 A9 */ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), @@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 = { .ops = &stm_pll3200c32_a9_ops, }; +static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = { + { .name = "clockgen-a9-pll-odf", }, +}; + +static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = { + .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9, + .outputs = st_pll3200c32_407_a9_clks, +}; + static struct clkgen_pll_data st_pll4600c28_418_a9 = { /* 418 A9 */ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), @@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = { .ops = &stm_pll4600c28_ops, }; +static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = { + { .name = "clockgen-a9-pll-odf", }, +}; + +static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = { + .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9, + .outputs = st_pll4600c28_418_a9_clks, +}; + /** * DOC: Clock Generated by PLL, rate set and enabled by bootloader * @@ -146,7 +210,6 @@ struct clkgen_pll { u32 ndiv; u32 idf; - u32 odf; u32 cp; }; @@ -685,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, static void __init clkgen_c32_pll_setup(struct device_node *np, - struct clkgen_pll_data *data) + struct clkgen_pll_data_clks *datac) { struct clk *clk; const char *parent_name, *pll_name; @@ -705,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np, of_clk_detect_critical(np, 0, &pll_flags); - clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags, - np->name, data->lock); + clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags, + np->name, datac->data->lock); if (IS_ERR(clk)) return; pll_name = __clk_get_name(clk); - num_odfs = data->num_odfs; + num_odfs = datac->data->num_odfs; clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); if (!clk_data) @@ -730,14 +793,21 @@ static void __init clkgen_c32_pll_setup(struct device_node *np, const char *clk_name; unsigned long odf_flags = 0; - if (of_property_read_string_index(np, "clock-output-names", - odf, &clk_name)) - return; + if (datac->outputs) { + clk_name = datac->outputs[odf].name; + odf_flags = datac->outputs[odf].flags; + } else { + if (of_property_read_string_index(np, + "clock-output-names", + odf, &clk_name)) + return; - of_clk_detect_critical(np, odf, &odf_flags); + of_clk_detect_critical(np, odf, &odf_flags); + } - clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags, - odf, &clkgena_c32_odf_lock, clk_name); + clk = clkgen_odf_register(pll_name, pll_base, datac->data, + odf_flags, odf, &clkgena_c32_odf_lock, + clk_name); if (IS_ERR(clk)) goto err; @@ -755,27 +825,48 @@ err: static void __init clkgen_c32_pll0_setup(struct device_node *np) { clkgen_c32_pll_setup(np, - (struct clkgen_pll_data *) &st_pll3200c32_cx_0); + (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_0_legacy_data); } CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup); +static void __init clkgen_c32_pll0_a0_setup(struct device_node *np) +{ + clkgen_c32_pll_setup(np, + (struct clkgen_pll_data_clks *) &st_pll3200c32_a0_data); +} +CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup); + +static void __init clkgen_c32_pll0_c0_setup(struct device_node *np) +{ + clkgen_c32_pll_setup(np, + (struct clkgen_pll_data_clks *) &st_pll3200c32_c0_data); +} +CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup); + static void __init clkgen_c32_pll1_setup(struct device_node *np) { clkgen_c32_pll_setup(np, - (struct clkgen_pll_data *) &st_pll3200c32_cx_1); + (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_1_legacy_data); } CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup); +static void __init clkgen_c32_pll1_c0_setup(struct device_node *np) +{ + clkgen_c32_pll_setup(np, + (struct clkgen_pll_data_clks *) &st_pll3200c32_c1_data); +} +CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup); + static void __init clkgen_c32_plla9_setup(struct device_node *np) { clkgen_c32_pll_setup(np, - (struct clkgen_pll_data *) &st_pll3200c32_407_a9); + (struct clkgen_pll_data_clks *) &st_pll3200c32_407_a9_data); } CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup); static void __init clkgen_c28_plla9_setup(struct device_node *np) { clkgen_c32_pll_setup(np, - (struct clkgen_pll_data *) &st_pll4600c28_418_a9); + (struct clkgen_pll_data_clks *) &st_pll4600c28_418_a9_data); } CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index a774942cb153..f49724a22540 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -817,10 +817,10 @@ static void __init sun8i_v3_v3s_ccu_init(struct device_node *node, return; } - /* Force the PLL-Audio-1x divider to 4 */ + /* Force the PLL-Audio-1x divider to 1 */ val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); - writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); + writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG); sunxi_ccu_probe(node, reg, ccu_desc); } diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 4b31beefc9fc..2091fc9b0ca9 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -48,36 +48,45 @@ static int clk_periph_is_enabled(struct clk_hw *hw) return state; } -static int clk_periph_enable(struct clk_hw *hw) +static void clk_periph_enable_locked(struct clk_hw *hw) { struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); - unsigned long flags = 0; - - spin_lock_irqsave(&periph_ref_lock, flags); - - gate->enable_refcnt[gate->clk_num]++; - if (gate->enable_refcnt[gate->clk_num] > 1) { - spin_unlock_irqrestore(&periph_ref_lock, flags); - return 0; - } write_enb_set(periph_clk_to_bit(gate), gate); udelay(2); - if (!(gate->flags & TEGRA_PERIPH_NO_RESET) && - !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) { - if (read_rst(gate) & periph_clk_to_bit(gate)) { - udelay(5); /* reset propogation delay */ - write_rst_clr(periph_clk_to_bit(gate), gate); - } - } - if (gate->flags & TEGRA_PERIPH_WAR_1005168) { writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); udelay(1); writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); } +} + +static void clk_periph_disable_locked(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + /* + * If peripheral is in the APB bus then read the APB bus to + * flush the write operation in apb bus. This will avoid the + * peripheral access after disabling clock + */ + if (gate->flags & TEGRA_PERIPH_ON_APB) + tegra_read_chipid(); + + write_enb_clr(periph_clk_to_bit(gate), gate); +} + +static int clk_periph_enable(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + unsigned long flags = 0; + + spin_lock_irqsave(&periph_ref_lock, flags); + + if (!gate->enable_refcnt[gate->clk_num]++) + clk_periph_enable_locked(hw); spin_unlock_irqrestore(&periph_ref_lock, flags); @@ -91,21 +100,28 @@ static void clk_periph_disable(struct clk_hw *hw) spin_lock_irqsave(&periph_ref_lock, flags); - gate->enable_refcnt[gate->clk_num]--; - if (gate->enable_refcnt[gate->clk_num] > 0) { - spin_unlock_irqrestore(&periph_ref_lock, flags); - return; - } + WARN_ON(!gate->enable_refcnt[gate->clk_num]); + + if (--gate->enable_refcnt[gate->clk_num] == 0) + clk_periph_disable_locked(hw); + + spin_unlock_irqrestore(&periph_ref_lock, flags); +} + +static void clk_periph_disable_unused(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + unsigned long flags = 0; + + spin_lock_irqsave(&periph_ref_lock, flags); /* - * If peripheral is in the APB bus then read the APB bus to - * flush the write operation in apb bus. This will avoid the - * peripheral access after disabling clock + * Some clocks are duplicated and some of them are marked as critical, + * like fuse and fuse_burn for example, thus the enable_refcnt will + * be non-zero here if the "unused" duplicate is disabled by CCF. */ - if (gate->flags & TEGRA_PERIPH_ON_APB) - tegra_read_chipid(); - - write_enb_clr(periph_clk_to_bit(gate), gate); + if (!gate->enable_refcnt[gate->clk_num]) + clk_periph_disable_locked(hw); spin_unlock_irqrestore(&periph_ref_lock, flags); } @@ -114,6 +130,7 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, }; struct clk *tegra_clk_register_periph_gate(const char *name, @@ -148,9 +165,6 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; - if (read_enb(gate) & periph_clk_to_bit(gate)) - enable_refcnt[clk_num]++; - /* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 67620c7ecd9e..79ca3aa072b7 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -100,6 +100,15 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static void clk_periph_disable_unused(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + + gate_ops->disable_unused(gate_hw); +} + static void clk_periph_restore_context(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); @@ -126,6 +135,7 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, }; @@ -135,6 +145,7 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, }; diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 0193cebe8c5a..eaa079c177c3 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -558,6 +558,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, u32 p_div = 0; int ret; + if (!rate) + return -EINVAL; + switch (parent_rate) { case 12000000: case 26000000: @@ -1131,7 +1134,8 @@ static int clk_pllu_enable(struct clk_hw *hw) if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) @@ -1748,15 +1752,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return -EINVAL; } - if (clk_pll_is_enabled(hw)) - return 0; - input_rate = clk_hw_get_rate(__clk_get_hw(osc)); if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 60cc34f90cb9..292d6269daf1 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -712,9 +712,9 @@ static struct tegra_periph_init_data periph_clks[] = { MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), - MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), - MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), - MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), + MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, TEGRA_PERIPH_NO_RESET, tegra_clk_extern1), + MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, TEGRA_PERIPH_NO_RESET, tegra_clk_extern2), + MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, TEGRA_PERIPH_NO_RESET, tegra_clk_extern3), MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8), MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index a03119c30456..68d7bcd5fc8a 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,8 @@ #define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) + static struct tegra_clk_super_mux *cclk_super; static bool cclk_on_pllx; @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - if (cclk_super_get_parent(hw) == PLLX_INDEX) - return parent_rate; + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + u32 val = readl_relaxed(super->reg); + unsigned int div2; - return tegra_clk_super_ops.recalc_rate(hw, parent_rate); + /* check whether thermal throttling is active */ + if (val & TSENSOR_SLOWDOWN) + div2 = 1; + else + div2 = 0; + + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate >> div2; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate) >> div2; } static int cclk_super_determine_rate(struct clk_hw *hw, diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 2ac2679d696d..5e339ad0a97c 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -537,7 +537,7 @@ static void get_alignment_from_dt(struct device *dev, static int get_alignment_from_regulator(struct device *dev, struct rail_alignment *align) { - struct regulator *reg = devm_regulator_get(dev, "vdd-cpu"); + struct regulator *reg = regulator_get(dev, "vdd-cpu"); if (IS_ERR(reg)) return PTR_ERR(reg); @@ -545,7 +545,7 @@ static int get_alignment_from_regulator(struct device *dev, align->offset_uv = regulator_list_voltage(reg, 0); align->step_uv = regulator_get_linear_step(reg); - devm_regulator_put(reg); + regulator_put(reg); return 0; } diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index bdf6f4a51617..74c1d894cca8 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -249,8 +249,10 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; err = tegra->prepare_timing_change(emc, timing->rate); - if (err) + if (err) { + clk_disable_unprepare(timing->parent); return err; + } spin_lock_irqsave(tegra->lock, flags); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3efc651b42e3..3664593a5ba4 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 16dbf83d2f62..64121bc66d85 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -930,7 +930,7 @@ static void __init tegra30_super_clk_init(void) /* CCLKG */ clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), - CLK_SET_RATE_PARENT, + CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, clk_base + CCLKG_BURST_POLICY, 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; @@ -1006,7 +1006,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0), TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1), TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2), - TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2), + TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2), TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE), TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI), TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM), @@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c3e36b5dcc75..0c3ba0ccce1a 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -553,9 +553,6 @@ struct tegra_clk_periph_regs { * Flags: * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed * for this module. - * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module - * after clock enable and driver for the module is responsible for - * doing reset. * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the * bus to flush the write operation in apb bus. This flag indicates * that this peripheral is in apb bus. @@ -577,7 +574,6 @@ struct tegra_clk_periph_gate { #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 #define TEGRA_PERIPH_NO_RESET BIT(0) -#define TEGRA_PERIPH_MANUAL_RESET BIT(1) #define TEGRA_PERIPH_ON_APB BIT(2) #define TEGRA_PERIPH_WAR_1005168 BIT(3) #define TEGRA_PERIPH_NO_DIV BIT(4) diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c index bb2f2836dab2..b341cd990be7 100644 --- a/drivers/clk/ti/adpll.c +++ b/drivers/clk/ti/adpll.c @@ -896,11 +896,8 @@ static int ti_adpll_probe(struct platform_device *pdev) d->pa = res->start; d->iobase = devm_ioremap_resource(dev, res); - if (IS_ERR(d->iobase)) { - dev_err(dev, "could not get IO base: %li\n", - PTR_ERR(d->iobase)); + if (IS_ERR(d->iobase)) return PTR_ERR(d->iobase); - } err = ti_adpll_init_registers(d); if (err) diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index d6f1ac5b53e1..e9f9aee936ae 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -290,7 +290,9 @@ static void __init of_ti_dpll_setup(struct device_node *node, struct clk_init_data *init = NULL; const char **parent_names = NULL; struct dpll_data *dd = NULL; + int ssc_clk_index; u8 dpll_mode = 0; + u32 min_div; dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); @@ -345,6 +347,27 @@ static void __init of_ti_dpll_setup(struct device_node *node, if (dd->autoidle_mask) { if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) goto cleanup; + + ssc_clk_index = 4; + } else { + ssc_clk_index = 3; + } + + if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask && + dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) { + if (ti_clk_get_reg_addr(node, ssc_clk_index++, + &dd->ssc_deltam_reg)) + goto cleanup; + + if (ti_clk_get_reg_addr(node, ssc_clk_index++, + &dd->ssc_modfreq_reg)) + goto cleanup; + + of_property_read_u32(node, "ti,ssc-modfreq-hz", + &dd->ssc_modfreq); + of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam); + dd->ssc_downspread = + of_property_read_bool(node, "ti,ssc-downspread"); } if (of_property_read_bool(node, "ti,low-power-stop")) @@ -356,6 +379,10 @@ static void __init of_ti_dpll_setup(struct device_node *node, if (of_property_read_bool(node, "ti,lock")) dpll_mode |= 1 << DPLL_LOCKED; + if (!of_property_read_u32(node, "ti,min-div", &min_div) && + min_div > dd->min_divider) + dd->min_divider = min_div; + if (dpll_mode) dd->modes = dpll_mode; @@ -585,8 +612,14 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) const struct dpll_data dd = { .idlest_mask = 0x1, .enable_mask = 0x7, + .ssc_enable_mask = 0x1 << 12, + .ssc_downspread_mask = 0x1 << 14, .mult_mask = 0x7ff << 8, .div1_mask = 0x7f, + .ssc_deltam_int_mask = 0x3 << 18, + .ssc_deltam_frac_mask = 0x3ffff, + .ssc_modfreq_mant_mask = 0x7f, + .ssc_modfreq_exp_mask = 0x7 << 8, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, @@ -645,8 +678,14 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) const struct dpll_data dd = { .idlest_mask = 0x1, .enable_mask = 0x7, + .ssc_enable_mask = 0x1 << 12, + .ssc_downspread_mask = 0x1 << 14, .mult_mask = 0x7ff << 8, .div1_mask = 0x7f, + .ssc_deltam_int_mask = 0x3 << 18, + .ssc_deltam_frac_mask = 0x3ffff, + .ssc_modfreq_mant_mask = 0x7f, + .ssc_modfreq_exp_mask = 0x7 << 8, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 6097b099a5df..e32b3515f9e7 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -292,7 +292,89 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) } /** - * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers + * @clk: struct clk * of DPLL to set + * + * Enable the DPLL spread spectrum clocking if frequency modulation and + * frequency spreading have been set, otherwise disable it. + */ +static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) +{ + struct dpll_data *dd = clk->dpll_data; + unsigned long ref_rate; + u32 v, ctrl, mod_freq_divider, exponent, mantissa; + u32 deltam_step, deltam_ceil; + + ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); + + if (dd->ssc_modfreq && dd->ssc_deltam) { + ctrl |= dd->ssc_enable_mask; + + if (dd->ssc_downspread) + ctrl |= dd->ssc_downspread_mask; + else + ctrl &= ~dd->ssc_downspread_mask; + + ref_rate = clk_hw_get_rate(dd->clk_ref); + mod_freq_divider = + (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq); + if (dd->ssc_modfreq > (ref_rate / 70)) + pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n", + __clk_get_name(clk->hw.clk), ref_rate / 70); + + exponent = 0; + mantissa = mod_freq_divider; + while ((mantissa > 127) && (exponent < 7)) { + exponent++; + mantissa /= 2; + } + if (mantissa > 127) + mantissa = 127; + + v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg); + v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask); + v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask); + v |= exponent << __ffs(dd->ssc_modfreq_exp_mask); + ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg); + + deltam_step = dd->last_rounded_m * dd->ssc_deltam; + deltam_step /= 10; + if (dd->ssc_downspread) + deltam_step /= 2; + + deltam_step <<= __ffs(dd->ssc_deltam_int_mask); + deltam_step /= 100; + deltam_step /= mod_freq_divider; + if (deltam_step > 0xFFFFF) + deltam_step = 0xFFFFF; + + deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >> + __ffs(dd->ssc_deltam_int_mask); + if (deltam_step & dd->ssc_deltam_frac_mask) + deltam_ceil++; + + if ((dd->ssc_downspread && + ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 || + dd->last_rounded_m > 2045)) || + ((dd->last_rounded_m - deltam_ceil) < 20 || + (dd->last_rounded_m + deltam_ceil) > 2045)) + pr_warn("clock: SSC multiplier of DPLL %s is out of range\n", + __clk_get_name(clk->hw.clk)); + + v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); + v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask); + v |= deltam_step << __ffs(dd->ssc_deltam_int_mask | + dd->ssc_deltam_frac_mask); + ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg); + } else { + ctrl &= ~dd->ssc_enable_mask; + } + + ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); +} + +/** + * omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set * @freqsel: FREQSEL value to set * @@ -390,6 +472,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) ti_clk_ll_ops->clk_writel(v, &dd->control_reg); } + if (dd->ssc_enable_mask) + omap3_noncore_dpll_ssc_program(clk); + /* We let the clock framework set the other output dividers later */ /* REVISIT: Set ramp-up delay? */ diff --git a/drivers/clk/versatile/Kconfig b/drivers/clk/versatile/Kconfig index 792315d893db..481de5657d85 100644 --- a/drivers/clk/versatile/Kconfig +++ b/drivers/clk/versatile/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only menu "Clock driver for ARM Reference designs" + depends on HAS_IOMEM config ICST bool "Clock driver for ARM Reference designs ICST" diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c index 10c9b889324f..695feaa82da5 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, init.name = name; init.ops = &zynqmp_clk_gate_ops; - init.flags = nodes->flag; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names = parents; init.num_parents = 1; diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 06194149be83..157d4a960bf4 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -38,7 +38,7 @@ struct zynqmp_clk_mux { * zynqmp_clk_mux_get_parent() - Get parent of clock * @hw: handle between common and hardware-specific interfaces * - * Return: Parent index + * Return: Parent index on success or number of parents in case of error */ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) { @@ -50,9 +50,15 @@ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) ret = zynqmp_pm_clock_getparent(clk_id, &val); - if (ret) + if (ret) { pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", __func__, clk_name, ret); + /* + * clk_core_get_parent_by_index() takes num_parents as incorrect + * index which is exactly what I want to return here + */ + return clk_hw_get_num_parents(hw); + } return val; } @@ -90,6 +96,27 @@ static const struct clk_ops zynqmp_clk_mux_ro_ops = { .get_parent = zynqmp_clk_mux_get_parent, }; +static inline unsigned long zynqmp_clk_map_mux_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) + ccf_flag |= CLK_MUX_INDEX_ONE; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) + ccf_flag |= CLK_MUX_INDEX_BIT; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) + ccf_flag |= CLK_MUX_HIWORD_MASK; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_READ_ONLY) + ccf_flag |= CLK_MUX_READ_ONLY; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) + ccf_flag |= CLK_MUX_ROUND_CLOSEST; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) + ccf_flag |= CLK_MUX_BIG_ENDIAN; + + return ccf_flag; +} + /** * zynqmp_clk_register_mux() - Register a mux table with the clock * framework @@ -120,10 +147,12 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, init.ops = &zynqmp_clk_mux_ro_ops; else init.ops = &zynqmp_clk_mux_ops; - init.flags = nodes->flag; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names = parents; init.num_parents = num_parents; - mux->flags = nodes->type_flag; + mux->flags = zynqmp_clk_map_mux_ccf_flags(nodes->type_flag); mux->hw.init = &init; mux->clk_id = clk_id; diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index 5beeb41b29fa..84fa80a969a9 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -10,6 +10,37 @@ #include +/* Common Flags */ +/* must be gated across rate change */ +#define ZYNQMP_CLK_SET_RATE_GATE BIT(0) +/* must be gated across re-parent */ +#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1) +/* propagate rate change up one level */ +#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2) +/* do not gate even if unused */ +#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3) +/* don't re-parent on rate change */ +#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7) +/* do not gate, ever */ +#define ZYNQMP_CLK_IS_CRITICAL BIT(11) + +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + +/* Type Flags for mux clock */ +#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0) +#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1) +#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2) +#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) +#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5) + enum topology_type { TYPE_INVALID, TYPE_MUX, @@ -33,6 +64,8 @@ struct clock_topology { u8 custom_type_flag; }; +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag); + struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index db8d0d7161ce..871184e406e1 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -271,6 +271,26 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, return ret; } +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) + ccf_flag |= CLK_SET_RATE_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) + ccf_flag |= CLK_SET_PARENT_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) + ccf_flag |= CLK_SET_RATE_PARENT; + if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) + ccf_flag |= CLK_IGNORE_UNUSED; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) + ccf_flag |= CLK_SET_RATE_NO_REPARENT; + if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) + ccf_flag |= CLK_IS_CRITICAL; + + return ccf_flag; +} + /** * zynqmp_clk_register_fixed_factor() - Register fixed factor with the * clock framework @@ -292,6 +312,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, struct zynqmp_pm_query_data qdata = {0}; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; + unsigned long flag; qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; qdata.arg1 = clk_id; @@ -303,9 +324,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, mult = ret_payload[1]; div = ret_payload[2]; + flag = zynqmp_clk_map_common_ccf_flags(nodes->flag); + hw = clk_hw_register_fixed_factor(NULL, name, parents[0], - nodes->flag, mult, + flag, mult, div); return hw; diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e9bf7958b821..cb49281f9cf9 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -256,6 +256,11 @@ static const struct clk_ops zynqmp_clk_divider_ops = { .set_rate = zynqmp_clk_divider_set_rate, }; +static const struct clk_ops zynqmp_clk_divider_ro_ops = { + .recalc_rate = zynqmp_clk_divider_recalc_rate, + .round_rate = zynqmp_clk_divider_round_rate, +}; + /** * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. * @clk_id: Id of clock @@ -284,6 +289,29 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) return ret_payload[1]; } +static inline unsigned long zynqmp_clk_map_divider_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) + ccf_flag |= CLK_DIVIDER_ONE_BASED; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_POWER_OF_TWO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) + ccf_flag |= CLK_DIVIDER_ALLOW_ZERO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_HIWORD_MASK; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) + ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) + ccf_flag |= CLK_DIVIDER_READ_ONLY; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) + ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO; + + return ccf_flag; +} + /** * zynqmp_clk_register_divider() - Register a divider clock * @name: Name of this clock @@ -311,16 +339,20 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, return ERR_PTR(-ENOMEM); init.name = name; - init.ops = &zynqmp_clk_divider_ops; - /* CLK_FRAC is not defined in the common clk framework */ - init.flags = nodes->flag & ~CLK_FRAC; + if (nodes->type_flag & CLK_DIVIDER_READ_ONLY) + init.ops = &zynqmp_clk_divider_ro_ops; + else + init.ops = &zynqmp_clk_divider_ops; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names = parents; init.num_parents = 1; /* struct clk_divider assignments */ div->is_frac = !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); - div->flags = nodes->type_flag; + div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag); div->hw.init = &init; div->clk_id = clk_id; div->div_type = nodes->type; diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index abe6afbf3407..036e4ff64a2f 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -31,8 +31,9 @@ struct zynqmp_pll { #define PS_PLL_VCO_MAX 3000000000UL enum pll_mode { - PLL_MODE_INT, - PLL_MODE_FRAC, + PLL_MODE_INT = 0, + PLL_MODE_FRAC = 1, + PLL_MODE_ERROR = 2, }; #define FRAC_OFFSET 0x8 @@ -54,9 +55,11 @@ static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) int ret; ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); - if (ret) + if (ret) { pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); + return PLL_MODE_ERROR; + } return ret_payload[1]; } @@ -126,7 +129,7 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, * @hw: Handle between common and hardware-specific interfaces * @parent_rate: Clock frequency of parent clock * - * Return: Current clock frequency + * Return: Current clock frequency or 0 in case of error */ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -138,14 +141,21 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long rate, frac; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; + enum pll_mode mode; ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); - if (ret) + if (ret) { pr_warn_once("%s() get divider failed for %s, ret = %d\n", __func__, clk_name, ret); + return 0ul; + } + + mode = zynqmp_pll_get_mode(hw); + if (mode == PLL_MODE_ERROR) + return 0ul; rate = parent_rate * fbdiv; - if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { + if (mode == PLL_MODE_FRAC) { zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); data = ret_payload[1]; frac = (parent_rate * data) / FRAC_DIV; @@ -312,7 +322,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, init.name = name; init.ops = &zynqmp_pll_ops; - init.flags = nodes->flag; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names = parents; init.num_parents = 1; @@ -331,8 +343,6 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, } clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX); - if (ret < 0) - pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret); return hw; } diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 22ebb985c18d..25dd789e3ada 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -374,7 +374,7 @@ config ARM_GT_INITIAL_PRESCALER_VAL config ARM_TIMER_SP804 bool "Support for Dual Timer SP804 module" if COMPILE_TEST - depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP + depends on GENERIC_SCHED_CLOCK && HAVE_CLK select CLKSRC_MMIO select TIMER_OF if OF @@ -584,12 +584,12 @@ config H8300_TPU config CLKSRC_IMX_GPT bool "Clocksource using i.MX GPT" if COMPILE_TEST - depends on (ARM || ARM64) && CLKDEV_LOOKUP + depends on (ARM || ARM64) && HAVE_CLK select CLKSRC_MMIO config CLKSRC_IMX_TPM bool "Clocksource using i.MX TPM" if COMPILE_TEST - depends on (ARM || ARM64) && CLKDEV_LOOKUP + depends on (ARM || ARM64) && HAVE_CLK select CLKSRC_MMIO select TIMER_OF help diff --git a/drivers/comedi/drivers/comedi_8254.c b/drivers/comedi/drivers/comedi_8254.c index d1d509e9add9..4bf5daa9e885 100644 --- a/drivers/comedi/drivers/comedi_8254.c +++ b/drivers/comedi/drivers/comedi_8254.c @@ -555,6 +555,7 @@ static int comedi_8254_insn_config(struct comedi_device *dev, /** * comedi_8254_subdevice_init - initialize a comedi_subdevice for the 8254 timer * @s: comedi_subdevice struct + * @i8254: comedi_8254 struct */ void comedi_8254_subdevice_init(struct comedi_subdevice *s, struct comedi_8254 *i8254) @@ -607,7 +608,7 @@ static struct comedi_8254 *__i8254_init(unsigned long iobase, /** * comedi_8254_init - allocate and initialize the 8254 device for pio access - * @mmio: port I/O base address + * @iobase: port I/O base address * @osc_base: base time of the counter in ns * OPTIONAL - only used by comedi_8254_cascade_ns_to_timer() * @iosize: I/O register size diff --git a/drivers/comedi/drivers/comedi_isadma.c b/drivers/comedi/drivers/comedi_isadma.c index c729094298c2..479b58e209ba 100644 --- a/drivers/comedi/drivers/comedi_isadma.c +++ b/drivers/comedi/drivers/comedi_isadma.c @@ -143,7 +143,7 @@ EXPORT_SYMBOL_GPL(comedi_isadma_set_mode); * comedi_isadma_alloc - allocate and initialize the ISA DMA * @dev: comedi_device struct * @n_desc: the number of cookies to allocate - * @dma_chan: DMA channel for the first cookie + * @dma_chan1: DMA channel for the first cookie * @dma_chan2: DMA channel for the second cookie * @maxsize: the size of the buffer to allocate for each cookie * @dma_dir: the DMA direction diff --git a/drivers/comedi/drivers/jr3_pci.c b/drivers/comedi/drivers/jr3_pci.c index 7a02c4fa3cda..f963080dd61f 100644 --- a/drivers/comedi/drivers/jr3_pci.c +++ b/drivers/comedi/drivers/jr3_pci.c @@ -186,19 +186,6 @@ static void set_full_scales(struct jr3_sensor __iomem *sensor, set_s16(&sensor->command_word0, 0x0a00); } -static struct six_axis_t get_min_full_scales(struct jr3_sensor __iomem *sensor) -{ - struct six_axis_t result; - - result.fx = get_s16(&sensor->min_full_scale.fx); - result.fy = get_s16(&sensor->min_full_scale.fy); - result.fz = get_s16(&sensor->min_full_scale.fz); - result.mx = get_s16(&sensor->min_full_scale.mx); - result.my = get_s16(&sensor->min_full_scale.my); - result.mz = get_s16(&sensor->min_full_scale.mz); - return result; -} - static struct six_axis_t get_max_full_scales(struct jr3_sensor __iomem *sensor) { struct six_axis_t result; @@ -504,10 +491,8 @@ jr3_pci_poll_subdevice(struct comedi_subdevice *s) result = poll_delay_min_max(20, 100); } else { /* Set full scale */ - struct six_axis_t min_full_scale; struct six_axis_t max_full_scale; - min_full_scale = get_min_full_scales(sensor); max_full_scale = get_max_full_scales(sensor); set_full_scales(sensor, max_full_scale); diff --git a/drivers/comedi/drivers/ni_routes.c b/drivers/comedi/drivers/ni_routes.c index c426a9286f15..f0f8cd424b30 100644 --- a/drivers/comedi/drivers/ni_routes.c +++ b/drivers/comedi/drivers/ni_routes.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routes.c * Route information for NI boards. @@ -246,7 +245,7 @@ unsigned int ni_get_valid_routes(const struct ni_route_tables *tables, } EXPORT_SYMBOL_GPL(ni_get_valid_routes); -/** +/* * List of NI global signal names that, as destinations, are only routeable * indirectly through the *_arg elements of the comedi_cmd structure. */ @@ -388,7 +387,7 @@ ni_find_route_set(const int destination, } EXPORT_SYMBOL_GPL(ni_find_route_set); -/** +/* * ni_route_set_has_source() - Determines whether the given source is in * included given route_set. * @@ -507,7 +506,7 @@ s8 ni_route_to_register(const int src, const int dest, } EXPORT_SYMBOL_GPL(ni_route_to_register); -/** +/* * ni_find_route_source() - Finds the signal source corresponding to a signal * route (src-->dest) of the specified routing register * value and the specified route destination on the diff --git a/drivers/comedi/drivers/ni_routes.h b/drivers/comedi/drivers/ni_routes.h index b7680fd2afe1..036982315584 100644 --- a/drivers/comedi/drivers/ni_routes.h +++ b/drivers/comedi/drivers/ni_routes.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routes.h * Route information for NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes.c b/drivers/comedi/drivers/ni_routing/ni_device_routes.c index 7b6a74dfe48b..58654c2b12d6 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes.h b/drivers/comedi/drivers/ni_routing/ni_device_routes.h index b9f1c47d19e1..09e4e172c659 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes.h +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/all.h b/drivers/comedi/drivers/ni_routing/ni_device_routes/all.h index 78b24138acb7..001dbb88a874 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/all.h +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/all.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/all.h * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6070e.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6070e.c index f1126a0cb285..7d3064c92643 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6070e.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6070e.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6070e.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6220.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6220.c index 74a59222963f..e2c462edb8ec 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6220.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6220.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6220.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6221.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6221.c index 44dcbabf2a99..9e02ec0a66ad 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6221.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6221.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6221.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6229.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6229.c index fa5794e4e2b3..33f7fff61f74 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6229.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6229.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6229.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6251.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6251.c index 645fd1cd2de4..dde676b73624 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6251.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6251.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6251.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6254.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6254.c index 056a240cd3a2..167a2da97c14 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6254.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6254.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6254.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6259.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6259.c index e0b5fa78c3bc..ba990f98590c 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6259.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6259.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6259.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6534.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6534.c index a2472ed288cf..f8d2a91b6c0a 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6534.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6534.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6534.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6602.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6602.c index 91de9dac2d6a..2eee91f590eb 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6602.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6602.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6602.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6713.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6713.c index d378b36d2084..c07ef3584a4b 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6713.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6713.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6713.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6723.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6723.c index e0cc57ab06e7..c37373f8f0e1 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6723.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6723.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6723.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6733.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6733.c index f6e1e17ab854..f252fbe19638 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6733.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pci-6733.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pci-6733.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6030e.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6030e.c index 9978d632117f..4ccba4fdf3bc 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6030e.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6030e.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxi-6030e.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6224.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6224.c index 1b89e27d7aa5..84fdfa2ef9a7 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6224.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6224.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxi-6224.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c index 10dfc34bc87c..2b99ce0f87a4 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6251.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6251.c index 25db4b7363de..1c5164c46306 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6251.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6251.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxi-6251.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6733.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6733.c index 27da4433fc4a..a3402b1ca6e8 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6733.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxi-6733.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxi-6733.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6251.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6251.c index 8354fe971d59..defcc4cfe1e4 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6251.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6251.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxie-6251.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6535.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6535.c index 2ebb679e0129..d2013b9e6767 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6535.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6535.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxie-6535.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c index d88504314d7f..89aff39a4fc2 100644 --- a/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c +++ b/drivers/comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values.c b/drivers/comedi/drivers/ni_routing/ni_route_values.c index 5901762734ed..54a740b39819 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values.c +++ b/drivers/comedi/drivers/ni_routing/ni_route_values.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values.c * Route information for NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values.h b/drivers/comedi/drivers/ni_routing/ni_route_values.h index 80e0145fb82b..6e358efa6f7f 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values.h +++ b/drivers/comedi/drivers/ni_routing/ni_route_values.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values.h * Route information for NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values/all.h b/drivers/comedi/drivers/ni_routing/ni_route_values/all.h index 7227461500b5..30761e55f746 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values/all.h +++ b/drivers/comedi/drivers/ni_routing/ni_route_values/all.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values/all.h * List of valid routes for specific NI boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_660x.c b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_660x.c index f1c7e6646261..aace60e49507 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_660x.c +++ b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_660x.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values/ni_660x.c * Route information for NI_660X boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_eseries.c b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_eseries.c index d1ab3c9ce585..7a52f024cdbd 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_eseries.c +++ b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_eseries.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values/ni_eseries.c * Route information for NI_ESERIES boards. diff --git a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_mseries.c b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_mseries.c index c59d8afe0ae9..d1ddd13b33b5 100644 --- a/drivers/comedi/drivers/ni_routing/ni_route_values/ni_mseries.c +++ b/drivers/comedi/drivers/ni_routing/ni_route_values/ni_mseries.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/ni_route_values/ni_mseries.c * Route information for NI_MSERIES boards. diff --git a/drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c b/drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c index dedb6f2fc678..d55521b5bdcb 100644 --- a/drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c +++ b/drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ #include #include diff --git a/drivers/comedi/drivers/ni_routing/tools/convert_csv_to_c.py b/drivers/comedi/drivers/ni_routing/tools/convert_csv_to_c.py index 532eb6372a5a..90378fb50580 100755 --- a/drivers/comedi/drivers/ni_routing/tools/convert_csv_to_c.py +++ b/drivers/comedi/drivers/ni_routing/tools/convert_csv_to_c.py @@ -1,6 +1,5 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0+ -# vim: ts=2:sw=2:et:tw=80:nowrap # This is simply to aide in creating the entries in the order of the value of # the device-global NI signal/terminal constants defined in comedi.h @@ -123,7 +122,6 @@ class DeviceRoutes(CSVCollection): output_file_top = """\ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * List of valid routes for specific NI boards. @@ -155,7 +153,6 @@ class DeviceRoutes(CSVCollection): extern_header = """\ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * List of valid routes for specific NI boards. @@ -193,7 +190,6 @@ class DeviceRoutes(CSVCollection): single_output_file_top = """\ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * List of valid routes for specific NI boards. @@ -299,7 +295,6 @@ class RouteValues(CSVCollection): output_file_top = """\ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * Route information for NI boards. @@ -337,7 +332,6 @@ class RouteValues(CSVCollection): extern_header = """\ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * List of valid routes for specific NI boards. @@ -375,7 +369,6 @@ class RouteValues(CSVCollection): single_output_file_top = """\ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/ni_routing/{filename} * Route information for {sheet} boards. diff --git a/drivers/comedi/drivers/ni_routing/tools/convert_py_to_csv.py b/drivers/comedi/drivers/ni_routing/tools/convert_py_to_csv.py index b3e6472bac22..a273b33edb8f 100755 --- a/drivers/comedi/drivers/ni_routing/tools/convert_py_to_csv.py +++ b/drivers/comedi/drivers/ni_routing/tools/convert_py_to_csv.py @@ -1,6 +1,5 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0+ -# vim: ts=2:sw=2:et:tw=80:nowrap from os import path import os, csv diff --git a/drivers/comedi/drivers/ni_routing/tools/csv_collection.py b/drivers/comedi/drivers/ni_routing/tools/csv_collection.py index 12617329a928..db977ecb4307 100644 --- a/drivers/comedi/drivers/ni_routing/tools/csv_collection.py +++ b/drivers/comedi/drivers/ni_routing/tools/csv_collection.py @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -# vim: ts=2:sw=2:et:tw=80:nowrap import os, csv, glob diff --git a/drivers/comedi/drivers/ni_routing/tools/make_blank_csv.py b/drivers/comedi/drivers/ni_routing/tools/make_blank_csv.py index 89c90a0ba24d..c00eaf803299 100755 --- a/drivers/comedi/drivers/ni_routing/tools/make_blank_csv.py +++ b/drivers/comedi/drivers/ni_routing/tools/make_blank_csv.py @@ -1,6 +1,5 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0+ -# vim: ts=2:sw=2:et:tw=80:nowrap from os import path import os, csv diff --git a/drivers/comedi/drivers/ni_routing/tools/ni_names.py b/drivers/comedi/drivers/ni_routing/tools/ni_names.py index 5f9b825968b1..d4df5f29e3e5 100644 --- a/drivers/comedi/drivers/ni_routing/tools/ni_names.py +++ b/drivers/comedi/drivers/ni_routing/tools/ni_names.py @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -# vim: ts=2:sw=2:et:tw=80:nowrap """ This file helps to extract string names of NI signals as included in comedi.h between NI_NAMES_BASE and NI_NAMES_BASE+NI_NUM_NAMES. diff --git a/drivers/comedi/drivers/ni_tio.c b/drivers/comedi/drivers/ni_tio.c index f6154addaa95..da6826d77e60 100644 --- a/drivers/comedi/drivers/ni_tio.c +++ b/drivers/comedi/drivers/ni_tio.c @@ -1501,7 +1501,7 @@ int ni_tio_insn_config(struct comedi_device *dev, } EXPORT_SYMBOL_GPL(ni_tio_insn_config); -/** +/* * Retrieves the register value of the current source of the output selector for * the given destination. * @@ -1541,10 +1541,10 @@ int ni_tio_get_routing(struct ni_gpct_device *counter_dev, unsigned int dest) EXPORT_SYMBOL_GPL(ni_tio_get_routing); /** - * Sets the register value of the selector MUX for the given destination. - * @counter_dev:Pointer to general counter device. - * @destination:Device-global identifier of route destination. - * @register_value: + * ni_tio_set_routing() - Sets the register value of the selector MUX for the given destination. + * @counter_dev: Pointer to general counter device. + * @dest: Device-global identifier of route destination. + * @reg: * The first several bits of this value should store the desired * value to write to the register. All other bits are for * transmitting information that modify the mode of the particular @@ -1580,7 +1580,7 @@ int ni_tio_set_routing(struct ni_gpct_device *counter_dev, unsigned int dest, } EXPORT_SYMBOL_GPL(ni_tio_set_routing); -/** +/* * Sets the given destination MUX to its default value or disable it. * * Return: 0 if successful; -EINVAL if terminal is unknown. diff --git a/drivers/comedi/drivers/tests/comedi_example_test.c b/drivers/comedi/drivers/tests/comedi_example_test.c index e5aaaeab7bdd..81d074bcdea5 100644 --- a/drivers/comedi/drivers/tests/comedi_example_test.c +++ b/drivers/comedi/drivers/tests/comedi_example_test.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/tests/comedi_example_test.c * Example set of unit tests. diff --git a/drivers/comedi/drivers/tests/ni_routes_test.c b/drivers/comedi/drivers/tests/ni_routes_test.c index 32073850d545..652362486ff6 100644 --- a/drivers/comedi/drivers/tests/ni_routes_test.c +++ b/drivers/comedi/drivers/tests/ni_routes_test.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/tests/ni_routes_test.c * Unit tests for NI routes (ni_routes.c module). diff --git a/drivers/comedi/drivers/tests/unittest.h b/drivers/comedi/drivers/tests/unittest.h index 2da3beea2479..b0b34e058aad 100644 --- a/drivers/comedi/drivers/tests/unittest.h +++ b/drivers/comedi/drivers/tests/unittest.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* vim: set ts=8 sw=8 noet tw=80 nowrap: */ /* * comedi/drivers/tests/unittest.h * Simple framework for unittests for comedi drivers. diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index 9691f8612be8..09a9a77cce06 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -21,7 +21,7 @@ static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)]; static unsigned int num_quad8; -module_param_array(base, uint, &num_quad8, 0); +module_param_hw_array(base, uint, ioport, &num_quad8, 0); MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); #define QUAD8_NUM_COUNTERS 8 @@ -193,7 +193,7 @@ enum quad8_count_function { QUAD8_COUNT_FUNCTION_QUADRATURE_X4 }; -static enum counter_count_function quad8_count_functions_list[] = { +static const enum counter_count_function quad8_count_functions_list[] = { [QUAD8_COUNT_FUNCTION_PULSE_DIRECTION] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION, [QUAD8_COUNT_FUNCTION_QUADRATURE_X1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A, [QUAD8_COUNT_FUNCTION_QUADRATURE_X2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A, @@ -305,12 +305,12 @@ enum quad8_synapse_action { QUAD8_SYNAPSE_ACTION_BOTH_EDGES }; -static enum counter_synapse_action quad8_index_actions_list[] = { +static const enum counter_synapse_action quad8_index_actions_list[] = { [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE }; -static enum counter_synapse_action quad8_synapse_actions_list[] = { +static const enum counter_synapse_action quad8_synapse_actions_list[] = { [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE, [QUAD8_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE, @@ -632,8 +632,8 @@ static ssize_t quad8_count_preset_read(struct counter_device *counter, return sprintf(buf, "%u\n", priv->preset[count->id]); } -static void quad8_preset_register_set(struct quad8 *priv, int id, - unsigned int preset) +static void quad8_preset_register_set(struct quad8 *const priv, const int id, + const unsigned int preset) { const unsigned int base_offset = priv->base + 2 * id; int i; @@ -1082,7 +1082,6 @@ static int quad8_probe(struct device *dev, unsigned int id) /* Enable all counters */ outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); - /* Register Counter device */ return devm_counter_register(dev, &priv->counter); } diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 5328705aa09c..d5d2540b30c2 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -91,4 +91,14 @@ config MICROCHIP_TCB_CAPTURE To compile this driver as a module, choose M here: the module will be called microchip-tcb-capture. +config INTEL_QEP + tristate "Intel Quadrature Encoder Peripheral driver" + depends on PCI + help + Select this option to enable the Intel Quadrature Encoder Peripheral + driver. + + To compile this driver as a module, choose M here: the module + will be called intel-qep. + endif # COUNTER diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index cb646ed2f039..19742e6f5e3e 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o obj-$(CONFIG_TI_EQEP) += ti-eqep.o obj-$(CONFIG_FTM_QUADDEC) += ftm-quaddec.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) += microchip-tcb-capture.o +obj-$(CONFIG_INTEL_QEP) += intel-qep.o diff --git a/drivers/counter/ftm-quaddec.c b/drivers/counter/ftm-quaddec.c index c2b3fdfd8b77..9371532406ca 100644 --- a/drivers/counter/ftm-quaddec.c +++ b/drivers/counter/ftm-quaddec.c @@ -162,7 +162,7 @@ enum ftm_quaddec_synapse_action { FTM_QUADDEC_SYNAPSE_ACTION_BOTH_EDGES, }; -static enum counter_synapse_action ftm_quaddec_synapse_actions[] = { +static const enum counter_synapse_action ftm_quaddec_synapse_actions[] = { [FTM_QUADDEC_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES }; diff --git a/drivers/counter/intel-qep.c b/drivers/counter/intel-qep.c new file mode 100644 index 000000000000..8d7ae28fbd67 --- /dev/null +++ b/drivers/counter/intel-qep.c @@ -0,0 +1,544 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Quadrature Encoder Peripheral driver + * + * Copyright (C) 2019-2021 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ +#include +#include +#include +#include +#include +#include +#include + +#define INTEL_QEPCON 0x00 +#define INTEL_QEPFLT 0x04 +#define INTEL_QEPCOUNT 0x08 +#define INTEL_QEPMAX 0x0c +#define INTEL_QEPWDT 0x10 +#define INTEL_QEPCAPDIV 0x14 +#define INTEL_QEPCNTR 0x18 +#define INTEL_QEPCAPBUF 0x1c +#define INTEL_QEPINT_STAT 0x20 +#define INTEL_QEPINT_MASK 0x24 + +/* QEPCON */ +#define INTEL_QEPCON_EN BIT(0) +#define INTEL_QEPCON_FLT_EN BIT(1) +#define INTEL_QEPCON_EDGE_A BIT(2) +#define INTEL_QEPCON_EDGE_B BIT(3) +#define INTEL_QEPCON_EDGE_INDX BIT(4) +#define INTEL_QEPCON_SWPAB BIT(5) +#define INTEL_QEPCON_OP_MODE BIT(6) +#define INTEL_QEPCON_PH_ERR BIT(7) +#define INTEL_QEPCON_COUNT_RST_MODE BIT(8) +#define INTEL_QEPCON_INDX_GATING_MASK GENMASK(10, 9) +#define INTEL_QEPCON_INDX_GATING(n) (((n) & 3) << 9) +#define INTEL_QEPCON_INDX_PAL_PBL INTEL_QEPCON_INDX_GATING(0) +#define INTEL_QEPCON_INDX_PAL_PBH INTEL_QEPCON_INDX_GATING(1) +#define INTEL_QEPCON_INDX_PAH_PBL INTEL_QEPCON_INDX_GATING(2) +#define INTEL_QEPCON_INDX_PAH_PBH INTEL_QEPCON_INDX_GATING(3) +#define INTEL_QEPCON_CAP_MODE BIT(11) +#define INTEL_QEPCON_FIFO_THRE_MASK GENMASK(14, 12) +#define INTEL_QEPCON_FIFO_THRE(n) ((((n) - 1) & 7) << 12) +#define INTEL_QEPCON_FIFO_EMPTY BIT(15) + +/* QEPFLT */ +#define INTEL_QEPFLT_MAX_COUNT(n) ((n) & 0x1fffff) + +/* QEPINT */ +#define INTEL_QEPINT_FIFOCRIT BIT(5) +#define INTEL_QEPINT_FIFOENTRY BIT(4) +#define INTEL_QEPINT_QEPDIR BIT(3) +#define INTEL_QEPINT_QEPRST_UP BIT(2) +#define INTEL_QEPINT_QEPRST_DOWN BIT(1) +#define INTEL_QEPINT_WDT BIT(0) + +#define INTEL_QEPINT_MASK_ALL GENMASK(5, 0) + +#define INTEL_QEP_CLK_PERIOD_NS 10 + +#define INTEL_QEP_COUNTER_EXT_RW(_name) \ +{ \ + .name = #_name, \ + .read = _name##_read, \ + .write = _name##_write, \ +} + +struct intel_qep { + struct counter_device counter; + struct mutex lock; + struct device *dev; + void __iomem *regs; + bool enabled; + /* Context save registers */ + u32 qepcon; + u32 qepflt; + u32 qepmax; +}; + +static inline u32 intel_qep_readl(struct intel_qep *qep, u32 offset) +{ + return readl(qep->regs + offset); +} + +static inline void intel_qep_writel(struct intel_qep *qep, + u32 offset, u32 value) +{ + writel(value, qep->regs + offset); +} + +static void intel_qep_init(struct intel_qep *qep) +{ + u32 reg; + + reg = intel_qep_readl(qep, INTEL_QEPCON); + reg &= ~INTEL_QEPCON_EN; + intel_qep_writel(qep, INTEL_QEPCON, reg); + qep->enabled = false; + /* + * Make sure peripheral is disabled by flushing the write with + * a dummy read + */ + reg = intel_qep_readl(qep, INTEL_QEPCON); + + reg &= ~(INTEL_QEPCON_OP_MODE | INTEL_QEPCON_FLT_EN); + reg |= INTEL_QEPCON_EDGE_A | INTEL_QEPCON_EDGE_B | + INTEL_QEPCON_EDGE_INDX | INTEL_QEPCON_COUNT_RST_MODE; + intel_qep_writel(qep, INTEL_QEPCON, reg); + intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL); +} + +static int intel_qep_count_read(struct counter_device *counter, + struct counter_count *count, + unsigned long *val) +{ + struct intel_qep *const qep = counter->priv; + + pm_runtime_get_sync(qep->dev); + *val = intel_qep_readl(qep, INTEL_QEPCOUNT); + pm_runtime_put(qep->dev); + + return 0; +} + +static const enum counter_count_function intel_qep_count_functions[] = { + COUNTER_COUNT_FUNCTION_QUADRATURE_X4, +}; + +static int intel_qep_function_get(struct counter_device *counter, + struct counter_count *count, + size_t *function) +{ + *function = 0; + + return 0; +} + +static const enum counter_synapse_action intel_qep_synapse_actions[] = { + COUNTER_SYNAPSE_ACTION_BOTH_EDGES, +}; + +static int intel_qep_action_get(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + size_t *action) +{ + *action = 0; + return 0; +} + +static const struct counter_ops intel_qep_counter_ops = { + .count_read = intel_qep_count_read, + .function_get = intel_qep_function_get, + .action_get = intel_qep_action_get, +}; + +#define INTEL_QEP_SIGNAL(_id, _name) { \ + .id = (_id), \ + .name = (_name), \ +} + +static struct counter_signal intel_qep_signals[] = { + INTEL_QEP_SIGNAL(0, "Phase A"), + INTEL_QEP_SIGNAL(1, "Phase B"), + INTEL_QEP_SIGNAL(2, "Index"), +}; + +#define INTEL_QEP_SYNAPSE(_signal_id) { \ + .actions_list = intel_qep_synapse_actions, \ + .num_actions = ARRAY_SIZE(intel_qep_synapse_actions), \ + .signal = &intel_qep_signals[(_signal_id)], \ +} + +static struct counter_synapse intel_qep_count_synapses[] = { + INTEL_QEP_SYNAPSE(0), + INTEL_QEP_SYNAPSE(1), + INTEL_QEP_SYNAPSE(2), +}; + +static ssize_t ceiling_read(struct counter_device *counter, + struct counter_count *count, + void *priv, char *buf) +{ + struct intel_qep *qep = counter->priv; + u32 reg; + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPMAX); + pm_runtime_put(qep->dev); + + return sysfs_emit(buf, "%u\n", reg); +} + +static ssize_t ceiling_write(struct counter_device *counter, + struct counter_count *count, + void *priv, const char *buf, size_t len) +{ + struct intel_qep *qep = counter->priv; + u32 max; + int ret; + + ret = kstrtou32(buf, 0, &max); + if (ret < 0) + return ret; + + mutex_lock(&qep->lock); + if (qep->enabled) { + ret = -EBUSY; + goto out; + } + + pm_runtime_get_sync(qep->dev); + intel_qep_writel(qep, INTEL_QEPMAX, max); + pm_runtime_put(qep->dev); + ret = len; + +out: + mutex_unlock(&qep->lock); + return ret; +} + +static ssize_t enable_read(struct counter_device *counter, + struct counter_count *count, + void *priv, char *buf) +{ + struct intel_qep *qep = counter->priv; + + return sysfs_emit(buf, "%u\n", qep->enabled); +} + +static ssize_t enable_write(struct counter_device *counter, + struct counter_count *count, + void *priv, const char *buf, size_t len) +{ + struct intel_qep *qep = counter->priv; + u32 reg; + bool val, changed; + int ret; + + ret = kstrtobool(buf, &val); + if (ret) + return ret; + + mutex_lock(&qep->lock); + changed = val ^ qep->enabled; + if (!changed) + goto out; + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPCON); + if (val) { + /* Enable peripheral and keep runtime PM always on */ + reg |= INTEL_QEPCON_EN; + pm_runtime_get_noresume(qep->dev); + } else { + /* Let runtime PM be idle and disable peripheral */ + pm_runtime_put_noidle(qep->dev); + reg &= ~INTEL_QEPCON_EN; + } + intel_qep_writel(qep, INTEL_QEPCON, reg); + pm_runtime_put(qep->dev); + qep->enabled = val; + +out: + mutex_unlock(&qep->lock); + return len; +} + +static ssize_t spike_filter_ns_read(struct counter_device *counter, + struct counter_count *count, + void *priv, char *buf) +{ + struct intel_qep *qep = counter->priv; + u32 reg; + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPCON); + if (!(reg & INTEL_QEPCON_FLT_EN)) { + pm_runtime_put(qep->dev); + return sysfs_emit(buf, "0\n"); + } + reg = INTEL_QEPFLT_MAX_COUNT(intel_qep_readl(qep, INTEL_QEPFLT)); + pm_runtime_put(qep->dev); + + return sysfs_emit(buf, "%u\n", (reg + 2) * INTEL_QEP_CLK_PERIOD_NS); +} + +static ssize_t spike_filter_ns_write(struct counter_device *counter, + struct counter_count *count, + void *priv, const char *buf, size_t len) +{ + struct intel_qep *qep = counter->priv; + u32 reg, length; + bool enable; + int ret; + + ret = kstrtou32(buf, 0, &length); + if (ret < 0) + return ret; + + /* + * Spike filter length is (MAX_COUNT + 2) clock periods. + * Disable filter when userspace writes 0, enable for valid + * nanoseconds values and error out otherwise. + */ + length /= INTEL_QEP_CLK_PERIOD_NS; + if (length == 0) { + enable = false; + length = 0; + } else if (length >= 2) { + enable = true; + length -= 2; + } else { + return -EINVAL; + } + + if (length > INTEL_QEPFLT_MAX_COUNT(length)) + return -EINVAL; + + mutex_lock(&qep->lock); + if (qep->enabled) { + ret = -EBUSY; + goto out; + } + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPCON); + if (enable) + reg |= INTEL_QEPCON_FLT_EN; + else + reg &= ~INTEL_QEPCON_FLT_EN; + intel_qep_writel(qep, INTEL_QEPFLT, length); + intel_qep_writel(qep, INTEL_QEPCON, reg); + pm_runtime_put(qep->dev); + ret = len; + +out: + mutex_unlock(&qep->lock); + return ret; +} + +static ssize_t preset_enable_read(struct counter_device *counter, + struct counter_count *count, + void *priv, char *buf) +{ + struct intel_qep *qep = counter->priv; + u32 reg; + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPCON); + pm_runtime_put(qep->dev); + return sysfs_emit(buf, "%u\n", !(reg & INTEL_QEPCON_COUNT_RST_MODE)); +} + +static ssize_t preset_enable_write(struct counter_device *counter, + struct counter_count *count, + void *priv, const char *buf, size_t len) +{ + struct intel_qep *qep = counter->priv; + u32 reg; + bool val; + int ret; + + ret = kstrtobool(buf, &val); + if (ret) + return ret; + + mutex_lock(&qep->lock); + if (qep->enabled) { + ret = -EBUSY; + goto out; + } + + pm_runtime_get_sync(qep->dev); + reg = intel_qep_readl(qep, INTEL_QEPCON); + if (val) + reg &= ~INTEL_QEPCON_COUNT_RST_MODE; + else + reg |= INTEL_QEPCON_COUNT_RST_MODE; + + intel_qep_writel(qep, INTEL_QEPCON, reg); + pm_runtime_put(qep->dev); + ret = len; + +out: + mutex_unlock(&qep->lock); + + return ret; +} + +static const struct counter_count_ext intel_qep_count_ext[] = { + INTEL_QEP_COUNTER_EXT_RW(ceiling), + INTEL_QEP_COUNTER_EXT_RW(enable), + INTEL_QEP_COUNTER_EXT_RW(spike_filter_ns), + INTEL_QEP_COUNTER_EXT_RW(preset_enable) +}; + +static struct counter_count intel_qep_counter_count[] = { + { + .id = 0, + .name = "Channel 1 Count", + .functions_list = intel_qep_count_functions, + .num_functions = ARRAY_SIZE(intel_qep_count_functions), + .synapses = intel_qep_count_synapses, + .num_synapses = ARRAY_SIZE(intel_qep_count_synapses), + .ext = intel_qep_count_ext, + .num_ext = ARRAY_SIZE(intel_qep_count_ext), + }, +}; + +static int intel_qep_probe(struct pci_dev *pci, const struct pci_device_id *id) +{ + struct intel_qep *qep; + struct device *dev = &pci->dev; + void __iomem *regs; + int ret; + + qep = devm_kzalloc(dev, sizeof(*qep), GFP_KERNEL); + if (!qep) + return -ENOMEM; + + ret = pcim_enable_device(pci); + if (ret) + return ret; + + pci_set_master(pci); + + ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) + return ret; + + regs = pcim_iomap_table(pci)[0]; + if (!regs) + return -ENOMEM; + + qep->dev = dev; + qep->regs = regs; + mutex_init(&qep->lock); + + intel_qep_init(qep); + pci_set_drvdata(pci, qep); + + qep->counter.name = pci_name(pci); + qep->counter.parent = dev; + qep->counter.ops = &intel_qep_counter_ops; + qep->counter.counts = intel_qep_counter_count; + qep->counter.num_counts = ARRAY_SIZE(intel_qep_counter_count); + qep->counter.signals = intel_qep_signals; + qep->counter.num_signals = ARRAY_SIZE(intel_qep_signals); + qep->counter.priv = qep; + qep->enabled = false; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return devm_counter_register(&pci->dev, &qep->counter); +} + +static void intel_qep_remove(struct pci_dev *pci) +{ + struct intel_qep *qep = pci_get_drvdata(pci); + struct device *dev = &pci->dev; + + pm_runtime_forbid(dev); + if (!qep->enabled) + pm_runtime_get(dev); + + intel_qep_writel(qep, INTEL_QEPCON, 0); +} + +static int __maybe_unused intel_qep_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct intel_qep *qep = pci_get_drvdata(pdev); + + qep->qepcon = intel_qep_readl(qep, INTEL_QEPCON); + qep->qepflt = intel_qep_readl(qep, INTEL_QEPFLT); + qep->qepmax = intel_qep_readl(qep, INTEL_QEPMAX); + + return 0; +} + +static int __maybe_unused intel_qep_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct intel_qep *qep = pci_get_drvdata(pdev); + + /* + * Make sure peripheral is disabled when restoring registers and + * control register bits that are writable only when the peripheral + * is disabled + */ + intel_qep_writel(qep, INTEL_QEPCON, 0); + intel_qep_readl(qep, INTEL_QEPCON); + + intel_qep_writel(qep, INTEL_QEPFLT, qep->qepflt); + intel_qep_writel(qep, INTEL_QEPMAX, qep->qepmax); + intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL); + + /* Restore all other control register bits except enable status */ + intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon & ~INTEL_QEPCON_EN); + intel_qep_readl(qep, INTEL_QEPCON); + + /* Restore enable status */ + intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon); + + return 0; +} + +static UNIVERSAL_DEV_PM_OPS(intel_qep_pm_ops, + intel_qep_suspend, intel_qep_resume, NULL); + +static const struct pci_device_id intel_qep_id_table[] = { + /* EHL */ + { PCI_VDEVICE(INTEL, 0x4bc3), }, + { PCI_VDEVICE(INTEL, 0x4b81), }, + { PCI_VDEVICE(INTEL, 0x4b82), }, + { PCI_VDEVICE(INTEL, 0x4b83), }, + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, intel_qep_id_table); + +static struct pci_driver intel_qep_driver = { + .name = "intel-qep", + .id_table = intel_qep_id_table, + .probe = intel_qep_probe, + .remove = intel_qep_remove, + .driver = { + .pm = &intel_qep_pm_ops, + } +}; + +module_pci_driver(intel_qep_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel Quadrature Encoder Peripheral driver"); diff --git a/drivers/counter/interrupt-cnt.c b/drivers/counter/interrupt-cnt.c index a99ee7996977..5df7cd13d4c7 100644 --- a/drivers/counter/interrupt-cnt.c +++ b/drivers/counter/interrupt-cnt.c @@ -77,7 +77,7 @@ static const struct counter_count_ext interrupt_cnt_ext[] = { }, }; -static enum counter_synapse_action interrupt_cnt_synapse_actionss[] = { +static const enum counter_synapse_action interrupt_cnt_synapse_actions[] = { COUNTER_SYNAPSE_ACTION_RISING_EDGE, }; @@ -112,7 +112,7 @@ static int interrupt_cnt_write(struct counter_device *counter, return 0; } -static enum counter_count_function interrupt_cnt_functions[] = { +static const enum counter_count_function interrupt_cnt_functions[] = { COUNTER_COUNT_FUNCTION_INCREASE, }; @@ -194,8 +194,8 @@ static int interrupt_cnt_probe(struct platform_device *pdev) priv->counter.signals = &priv->signals; priv->counter.num_signals = 1; - priv->synapses.actions_list = interrupt_cnt_synapse_actionss; - priv->synapses.num_actions = ARRAY_SIZE(interrupt_cnt_synapse_actionss); + priv->synapses.actions_list = interrupt_cnt_synapse_actions; + priv->synapses.num_actions = ARRAY_SIZE(interrupt_cnt_synapse_actions); priv->synapses.signal = &priv->signals; priv->cnts.name = "Channel 0 Count"; diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index 710acc0a3704..51b8af80f98b 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -37,7 +37,7 @@ enum mchp_tc_count_function { MCHP_TC_FUNCTION_QUADRATURE, }; -static enum counter_count_function mchp_tc_count_functions[] = { +static const enum counter_count_function mchp_tc_count_functions[] = { [MCHP_TC_FUNCTION_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE, [MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4, }; @@ -49,7 +49,7 @@ enum mchp_tc_synapse_action { MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE }; -static enum counter_synapse_action mchp_tc_synapse_actions[] = { +static const enum counter_synapse_action mchp_tc_synapse_actions[] = { [MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, [MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE, [MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE, diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c index 937439635d53..c19d998df5ba 100644 --- a/drivers/counter/stm32-lptimer-cnt.c +++ b/drivers/counter/stm32-lptimer-cnt.c @@ -134,7 +134,7 @@ enum stm32_lptim_cnt_function { STM32_LPTIM_ENCODER_BOTH_EDGE, }; -static enum counter_count_function stm32_lptim_cnt_functions[] = { +static const enum counter_count_function stm32_lptim_cnt_functions[] = { [STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE, [STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4, }; @@ -146,7 +146,7 @@ enum stm32_lptim_synapse_action { STM32_LPTIM_SYNAPSE_ACTION_NONE, }; -static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = { +static const enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = { /* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */ [STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE, [STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE, diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 75bc401fdd18..603b30ada839 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -50,7 +50,7 @@ enum stm32_count_function { STM32_COUNT_ENCODER_MODE_3, }; -static enum counter_count_function stm32_count_functions[] = { +static const enum counter_count_function stm32_count_functions[] = { [STM32_COUNT_SLAVE_MODE_DISABLED] = COUNTER_COUNT_FUNCTION_INCREASE, [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A, [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B, @@ -267,7 +267,7 @@ enum stm32_synapse_action { STM32_SYNAPSE_ACTION_BOTH_EDGES }; -static enum counter_synapse_action stm32_synapse_actions[] = { +static const enum counter_synapse_action stm32_synapse_actions[] = { [STM32_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, [STM32_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES }; diff --git a/drivers/crypto/nx/Kconfig b/drivers/crypto/nx/Kconfig index 23e3d0160e67..2a35e0e785bd 100644 --- a/drivers/crypto/nx/Kconfig +++ b/drivers/crypto/nx/Kconfig @@ -29,6 +29,7 @@ if CRYPTO_DEV_NX_COMPRESS config CRYPTO_DEV_NX_COMPRESS_PSERIES tristate "Compression acceleration support on pSeries platform" depends on PPC_PSERIES && IBMVIO + depends on PPC_VAS default y help Support for PowerPC Nest (NX) compression acceleration. This diff --git a/drivers/crypto/nx/Makefile b/drivers/crypto/nx/Makefile index bc89a20e5d9d..d00181a26dd6 100644 --- a/drivers/crypto/nx/Makefile +++ b/drivers/crypto/nx/Makefile @@ -14,5 +14,5 @@ nx-crypto-objs := nx.o \ obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES) += nx-compress-pseries.o nx-compress.o obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV) += nx-compress-powernv.o nx-compress.o nx-compress-objs := nx-842.o -nx-compress-pseries-objs := nx-842-pseries.o +nx-compress-pseries-objs := nx-common-pseries.o nx-compress-powernv-objs := nx-common-powernv.o diff --git a/drivers/crypto/nx/nx-common-powernv.c b/drivers/crypto/nx/nx-common-powernv.c index 655361ba9107..32a036ada5d0 100644 --- a/drivers/crypto/nx/nx-common-powernv.c +++ b/drivers/crypto/nx/nx-common-powernv.c @@ -1092,8 +1092,8 @@ static __init int nx_compress_powernv_init(void) * normal FIFO priority is assigned for userspace. * 842 compression is supported only in kernel. */ - ret = vas_register_coproc_api(THIS_MODULE, VAS_COP_TYPE_GZIP, - "nx-gzip"); + ret = vas_register_api_powernv(THIS_MODULE, VAS_COP_TYPE_GZIP, + "nx-gzip"); /* * GZIP is not supported in kernel right now. @@ -1129,7 +1129,7 @@ static void __exit nx_compress_powernv_exit(void) * use. So delete this API use for GZIP engine. */ if (!nx842_ct) - vas_unregister_coproc_api(); + vas_unregister_api_powernv(); crypto_unregister_alg(&nx842_powernv_alg); diff --git a/drivers/crypto/nx/nx-842-pseries.c b/drivers/crypto/nx/nx-common-pseries.c similarity index 90% rename from drivers/crypto/nx/nx-842-pseries.c rename to drivers/crypto/nx/nx-common-pseries.c index 1491cbfbc071..4e304f6081e4 100644 --- a/drivers/crypto/nx/nx-842-pseries.c +++ b/drivers/crypto/nx/nx-common-pseries.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include "nx-842.h" #include "nx_csbcpb.h" /* struct nx_csbcpb */ @@ -19,6 +21,29 @@ MODULE_DESCRIPTION("842 H/W Compression driver for IBM Power processors"); MODULE_ALIAS_CRYPTO("842"); MODULE_ALIAS_CRYPTO("842-nx"); +/* + * Coprocessor type specific capabilities from the hypervisor. + */ +struct hv_nx_cop_caps { + __be64 descriptor; + __be64 req_max_processed_len; /* Max bytes in one GZIP request */ + __be64 min_compress_len; /* Min compression size in bytes */ + __be64 min_decompress_len; /* Min decompression size in bytes */ +} __packed __aligned(0x1000); + +/* + * Coprocessor type specific capabilities. + */ +struct nx_cop_caps { + u64 descriptor; + u64 req_max_processed_len; /* Max bytes in one GZIP request */ + u64 min_compress_len; /* Min compression in bytes */ + u64 min_decompress_len; /* Min decompression in bytes */ +}; + +static u64 caps_feat; +static struct nx_cop_caps nx_cop_caps; + static struct nx842_constraints nx842_pseries_constraints = { .alignment = DDE_BUFFER_ALIGN, .multiple = DDE_BUFFER_LAST_MULT, @@ -942,6 +967,36 @@ static struct attribute_group nx842_attribute_group = { .attrs = nx842_sysfs_entries, }; +#define nxcop_caps_read(_name) \ +static ssize_t nxcop_##_name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + return sprintf(buf, "%lld\n", nx_cop_caps._name); \ +} + +#define NXCT_ATTR_RO(_name) \ + nxcop_caps_read(_name); \ + static struct device_attribute dev_attr_##_name = __ATTR(_name, \ + 0444, \ + nxcop_##_name##_show, \ + NULL); + +NXCT_ATTR_RO(req_max_processed_len); +NXCT_ATTR_RO(min_compress_len); +NXCT_ATTR_RO(min_decompress_len); + +static struct attribute *nxcop_caps_sysfs_entries[] = { + &dev_attr_req_max_processed_len.attr, + &dev_attr_min_compress_len.attr, + &dev_attr_min_decompress_len.attr, + NULL, +}; + +static struct attribute_group nxcop_caps_attr_group = { + .name = "nx_gzip_caps", + .attrs = nxcop_caps_sysfs_entries, +}; + static struct nx842_driver nx842_pseries_driver = { .name = KBUILD_MODNAME, .owner = THIS_MODULE, @@ -1031,6 +1086,16 @@ static int nx842_probe(struct vio_dev *viodev, goto error; } + if (caps_feat) { + if (sysfs_create_group(&viodev->dev.kobj, + &nxcop_caps_attr_group)) { + dev_err(&viodev->dev, + "Could not create sysfs NX capability entries\n"); + ret = -1; + goto error; + } + } + return 0; error_unlock: @@ -1050,6 +1115,9 @@ static void nx842_remove(struct vio_dev *viodev) pr_info("Removing IBM Power 842 compression device\n"); sysfs_remove_group(&viodev->dev.kobj, &nx842_attribute_group); + if (caps_feat) + sysfs_remove_group(&viodev->dev.kobj, &nxcop_caps_attr_group); + crypto_unregister_alg(&nx842_pseries_alg); spin_lock_irqsave(&devdata_mutex, flags); @@ -1065,6 +1133,64 @@ static void nx842_remove(struct vio_dev *viodev) kfree(old_devdata); } +/* + * Get NX capabilities from the hypervisor. + * Only NXGZIP capabilities are provided by the hypersvisor right + * now and these values are available to user space with sysfs. + */ +static void __init nxcop_get_capabilities(void) +{ + struct hv_vas_all_caps *hv_caps; + struct hv_nx_cop_caps *hv_nxc; + int rc; + + hv_caps = kmalloc(sizeof(*hv_caps), GFP_KERNEL); + if (!hv_caps) + return; + /* + * Get NX overall capabilities with feature type=0 + */ + rc = h_query_vas_capabilities(H_QUERY_NX_CAPABILITIES, 0, + (u64)virt_to_phys(hv_caps)); + if (rc) + goto out; + + caps_feat = be64_to_cpu(hv_caps->feat_type); + /* + * NX-GZIP feature available + */ + if (caps_feat & VAS_NX_GZIP_FEAT_BIT) { + hv_nxc = kmalloc(sizeof(*hv_nxc), GFP_KERNEL); + if (!hv_nxc) + goto out; + /* + * Get capabilities for NX-GZIP feature + */ + rc = h_query_vas_capabilities(H_QUERY_NX_CAPABILITIES, + VAS_NX_GZIP_FEAT, + (u64)virt_to_phys(hv_nxc)); + } else { + pr_err("NX-GZIP feature is not available\n"); + rc = -EINVAL; + } + + if (!rc) { + nx_cop_caps.descriptor = be64_to_cpu(hv_nxc->descriptor); + nx_cop_caps.req_max_processed_len = + be64_to_cpu(hv_nxc->req_max_processed_len); + nx_cop_caps.min_compress_len = + be64_to_cpu(hv_nxc->min_compress_len); + nx_cop_caps.min_decompress_len = + be64_to_cpu(hv_nxc->min_decompress_len); + } else { + caps_feat = 0; + } + + kfree(hv_nxc); +out: + kfree(hv_caps); +} + static const struct vio_device_id nx842_vio_driver_ids[] = { {"ibm,compression-v1", "ibm,compression"}, {"", ""}, @@ -1093,6 +1219,10 @@ static int __init nx842_pseries_init(void) return -ENOMEM; RCU_INIT_POINTER(devdata, new_devdata); + /* + * Get NX capabilities from the hypervisor. + */ + nxcop_get_capabilities(); ret = vio_register_driver(&nx842_vio_driver); if (ret) { @@ -1102,6 +1232,12 @@ static int __init nx842_pseries_init(void) return ret; } + ret = vas_register_api_pseries(THIS_MODULE, VAS_COP_TYPE_GZIP, + "nx-gzip"); + + if (ret) + pr_err("NX-GZIP is not supported. Returned=%d\n", ret); + return 0; } @@ -1112,6 +1248,8 @@ static void __exit nx842_pseries_exit(void) struct nx842_devdata *old_devdata; unsigned long flags; + vas_unregister_api_pseries(); + crypto_unregister_alg(&nx842_pseries_alg); spin_lock_irqsave(&devdata_mutex, flags); diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 97dc4d751651..e6de221cc568 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -15,21 +15,17 @@ if CXL_BUS config CXL_MEM tristate "CXL.mem: Memory Devices" + default CXL_BUS help The CXL.mem protocol allows a device to act as a provider of "System RAM" and/or "Persistent Memory" that is fully coherent as if the memory was attached to the typical CPU memory controller. - Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as - a module) that will attach to CXL.mem devices for - configuration, provisioning, and health monitoring. This - driver is required for dynamic provisioning of CXL.mem - attached memory which is a prerequisite for persistent memory - support. Typically volatile memory is mapped by platform - firmware and included in the platform memory map, but in some - cases the OS is responsible for mapping that memory. See - Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification. + Say 'y/m' to enable a driver that will attach to CXL.mem devices for + configuration and management primarily via the mailbox interface. See + Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more + details. If unsure say 'm'. @@ -50,4 +46,33 @@ config CXL_MEM_RAW_COMMANDS potential impact to memory currently in use by the kernel. If developing CXL hardware or the driver say Y, otherwise say N. + +config CXL_ACPI + tristate "CXL ACPI: Platform Support" + depends on ACPI + default CXL_BUS + help + Enable support for host managed device memory (HDM) resources + published by a platform's ACPI CXL memory layout description. See + Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 + specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) + (https://www.computeexpresslink.org/spec-landing). The CXL core + consumes these resource to publish the root of a cxl_port decode + hierarchy to map regions that represent System RAM, or Persistent + Memory regions to be managed by LIBNVDIMM. + + If unsure say 'm'. + +config CXL_PMEM + tristate "CXL PMEM: Persistent Memory Support" + depends on LIBNVDIMM + default CXL_BUS + help + In addition to typical memory resources a platform may also advertise + support for persistent memory attached via CXL. This support is + managed via a bridge driver from CXL to the LIBNVDIMM system + subsystem. Say 'y/m' to enable support for enumerating and + provisioning the persistent memory capacity of CXL memory expanders. + + If unsure say 'm'. endif diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index a314a1891f4d..32954059b37b 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,7 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_CXL_BUS) += cxl_bus.o -obj-$(CONFIG_CXL_MEM) += cxl_mem.o +obj-$(CONFIG_CXL_BUS) += cxl_core.o +obj-$(CONFIG_CXL_MEM) += cxl_pci.o +obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o +obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL -cxl_bus-y := bus.o -cxl_mem-y := mem.o +cxl_core-y := core.o +cxl_pci-y := pci.o +cxl_acpi-y := acpi.o +cxl_pmem-y := pmem.o diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c new file mode 100644 index 000000000000..8ae89273f58e --- /dev/null +++ b/drivers/cxl/acpi.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2021 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include "cxl.h" + +static struct acpi_table_header *acpi_cedt; + +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) + +static unsigned long cfmws_to_decoder_flags(int restrictions) +{ + unsigned long flags = 0; + + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) + flags |= CXL_DECODER_F_TYPE2; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) + flags |= CXL_DECODER_F_TYPE3; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) + flags |= CXL_DECODER_F_RAM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) + flags |= CXL_DECODER_F_PMEM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) + flags |= CXL_DECODER_F_LOCK; + + return flags; +} + +static int cxl_acpi_cfmws_verify(struct device *dev, + struct acpi_cedt_cfmws *cfmws) +{ + int expected_len; + + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); + return -EINVAL; + } + + expected_len = struct_size((cfmws), interleave_targets, + CFMWS_INTERLEAVE_WAYS(cfmws)); + + if (cfmws->header.length < expected_len) { + dev_err(dev, "CFMWS length %d less than expected %d\n", + cfmws->header.length, expected_len); + return -EINVAL; + } + + if (cfmws->header.length > expected_len) + dev_dbg(dev, "CFMWS length %d greater than expected %d\n", + cfmws->header.length, expected_len); + + return 0; +} + +static void cxl_add_cfmws_decoders(struct device *dev, + struct cxl_port *root_port) +{ + struct acpi_cedt_cfmws *cfmws; + struct cxl_decoder *cxld; + acpi_size len, cur = 0; + void *cedt_subtable; + unsigned long flags; + int rc; + + len = acpi_cedt->length - sizeof(*acpi_cedt); + cedt_subtable = acpi_cedt + 1; + + while (cur < len) { + struct acpi_cedt_header *c = cedt_subtable + cur; + + if (c->type != ACPI_CEDT_TYPE_CFMWS) { + cur += c->length; + continue; + } + + cfmws = cedt_subtable + cur; + + if (cfmws->header.length < sizeof(*cfmws)) { + dev_warn_once(dev, + "CFMWS entry skipped:invalid length:%u\n", + cfmws->header.length); + cur += c->length; + continue; + } + + rc = cxl_acpi_cfmws_verify(dev, cfmws); + if (rc) { + dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + cur += c->length; + continue; + } + + flags = cfmws_to_decoder_flags(cfmws->restrictions); + cxld = devm_cxl_add_decoder(dev, root_port, + CFMWS_INTERLEAVE_WAYS(cfmws), + cfmws->base_hpa, cfmws->window_size, + CFMWS_INTERLEAVE_WAYS(cfmws), + CFMWS_INTERLEAVE_GRANULARITY(cfmws), + CXL_DECODER_EXPANDER, + flags); + + if (IS_ERR(cxld)) { + dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + } else { + dev_dbg(dev, "add: %s range %#llx-%#llx\n", + dev_name(&cxld->dev), cfmws->base_hpa, + cfmws->base_hpa + cfmws->window_size - 1); + } + cur += c->length; + } +} + +static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) +{ + struct acpi_cedt_chbs *chbs, *chbs_match = NULL; + acpi_size len, cur = 0; + void *cedt_subtable; + + len = acpi_cedt->length - sizeof(*acpi_cedt); + cedt_subtable = acpi_cedt + 1; + + while (cur < len) { + struct acpi_cedt_header *c = cedt_subtable + cur; + + if (c->type != ACPI_CEDT_TYPE_CHBS) { + cur += c->length; + continue; + } + + chbs = cedt_subtable + cur; + + if (chbs->header.length < sizeof(*chbs)) { + dev_warn_once(dev, + "CHBS entry skipped: invalid length:%u\n", + chbs->header.length); + cur += c->length; + continue; + } + + if (chbs->uid != uid) { + cur += c->length; + continue; + } + + if (chbs_match) { + dev_warn_once(dev, + "CHBS entry skipped: duplicate UID:%u\n", + uid); + cur += c->length; + continue; + } + + chbs_match = chbs; + cur += c->length; + } + + return chbs_match ? chbs_match : ERR_PTR(-ENODEV); +} + +static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs) +{ + return IS_ERR(chbs) ? CXL_RESOURCE_NONE : chbs->base; +} + +struct cxl_walk_context { + struct device *dev; + struct pci_bus *root; + struct cxl_port *port; + int error; + int count; +}; + +static int match_add_root_ports(struct pci_dev *pdev, void *data) +{ + struct cxl_walk_context *ctx = data; + struct pci_bus *root_bus = ctx->root; + struct cxl_port *port = ctx->port; + int type = pci_pcie_type(pdev); + struct device *dev = ctx->dev; + u32 lnkcap, port_num; + int rc; + + if (pdev->bus != root_bus) + return 0; + if (!pci_is_pcie(pdev)) + return 0; + if (type != PCI_EXP_TYPE_ROOT_PORT) + return 0; + if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, + &lnkcap) != PCIBIOS_SUCCESSFUL) + return 0; + + /* TODO walk DVSEC to find component register base */ + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); + rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE); + if (rc) { + ctx->error = rc; + return rc; + } + ctx->count++; + + dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev)); + + return 0; +} + +static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev) +{ + struct cxl_dport *dport; + + device_lock(&port->dev); + list_for_each_entry(dport, &port->dports, list) + if (dport->dport == dev) { + device_unlock(&port->dev); + return dport; + } + + device_unlock(&port->dev); + return NULL; +} + +static struct acpi_device *to_cxl_host_bridge(struct device *dev) +{ + struct acpi_device *adev = to_acpi_device(dev); + + if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0) + return adev; + return NULL; +} + +/* + * A host bridge is a dport to a CFMWS decode and it is a uport to the + * dport (PCIe Root Ports) in the host bridge. + */ +static int add_host_bridge_uport(struct device *match, void *arg) +{ + struct acpi_device *bridge = to_cxl_host_bridge(match); + struct cxl_port *root_port = arg; + struct device *host = root_port->dev.parent; + struct acpi_pci_root *pci_root; + struct cxl_walk_context ctx; + struct cxl_decoder *cxld; + struct cxl_dport *dport; + struct cxl_port *port; + + if (!bridge) + return 0; + + pci_root = acpi_pci_find_root(bridge->handle); + if (!pci_root) + return -ENXIO; + + dport = find_dport_by_dev(root_port, match); + if (!dport) { + dev_dbg(host, "host bridge expected and not found\n"); + return -ENODEV; + } + + port = devm_cxl_add_port(host, match, dport->component_reg_phys, + root_port); + if (IS_ERR(port)) + return PTR_ERR(port); + dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev)); + + ctx = (struct cxl_walk_context){ + .dev = host, + .root = pci_root->bus, + .port = port, + }; + pci_walk_bus(pci_root->bus, match_add_root_ports, &ctx); + + if (ctx.count == 0) + return -ENODEV; + if (ctx.error) + return ctx.error; + + /* TODO: Scan CHBCR for HDM Decoder resources */ + + /* + * In the single-port host-bridge case there are no HDM decoders + * in the CHBCR and a 1:1 passthrough decode is implied. + */ + if (ctx.count == 1) { + cxld = devm_cxl_add_passthrough_decoder(host, port); + if (IS_ERR(cxld)) + return PTR_ERR(cxld); + + dev_dbg(host, "add: %s\n", dev_name(&cxld->dev)); + } + + return 0; +} + +static int add_host_bridge_dport(struct device *match, void *arg) +{ + int rc; + acpi_status status; + unsigned long long uid; + struct acpi_cedt_chbs *chbs; + struct cxl_port *root_port = arg; + struct device *host = root_port->dev.parent; + struct acpi_device *bridge = to_cxl_host_bridge(match); + + if (!bridge) + return 0; + + status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL, + &uid); + if (status != AE_OK) { + dev_err(host, "unable to retrieve _UID of %s\n", + dev_name(match)); + return -ENODEV; + } + + chbs = cxl_acpi_match_chbs(host, uid); + if (IS_ERR(chbs)) + dev_dbg(host, "No CHBS found for Host Bridge: %s\n", + dev_name(match)); + + rc = cxl_add_dport(root_port, match, uid, get_chbcr(chbs)); + if (rc) { + dev_err(host, "failed to add downstream port: %s\n", + dev_name(match)); + return rc; + } + dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match)); + return 0; +} + +static int add_root_nvdimm_bridge(struct device *match, void *data) +{ + struct cxl_decoder *cxld; + struct cxl_port *root_port = data; + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *host = root_port->dev.parent; + + if (!is_root_decoder(match)) + return 0; + + cxld = to_cxl_decoder(match); + if (!(cxld->flags & CXL_DECODER_F_PMEM)) + return 0; + + cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port); + if (IS_ERR(cxl_nvb)) { + dev_dbg(host, "failed to register pmem\n"); + return PTR_ERR(cxl_nvb); + } + dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev), + dev_name(&cxl_nvb->dev)); + return 1; +} + +static int cxl_acpi_probe(struct platform_device *pdev) +{ + int rc; + acpi_status status; + struct cxl_port *root_port; + struct device *host = &pdev->dev; + struct acpi_device *adev = ACPI_COMPANION(host); + + root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); + if (IS_ERR(root_port)) + return PTR_ERR(root_port); + dev_dbg(host, "add: %s\n", dev_name(&root_port->dev)); + + status = acpi_get_table(ACPI_SIG_CEDT, 0, &acpi_cedt); + if (ACPI_FAILURE(status)) + return -ENXIO; + + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, + add_host_bridge_dport); + if (rc) + goto out; + + cxl_add_cfmws_decoders(host, root_port); + + /* + * Root level scanned with host-bridge as dports, now scan host-bridges + * for their role as CXL uports to their CXL-capable PCIe Root Ports. + */ + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, + add_host_bridge_uport); + if (rc) + goto out; + + if (IS_ENABLED(CONFIG_CXL_PMEM)) + rc = device_for_each_child(&root_port->dev, root_port, + add_root_nvdimm_bridge); + +out: + acpi_put_table(acpi_cedt); + if (rc < 0) + return rc; + return 0; +} + +static const struct acpi_device_id cxl_acpi_ids[] = { + { "ACPI0017", 0 }, + { "", 0 }, +}; +MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids); + +static struct platform_driver cxl_acpi_driver = { + .probe = cxl_acpi_probe, + .driver = { + .name = KBUILD_MODNAME, + .acpi_match_table = cxl_acpi_ids, + }, +}; + +module_platform_driver(cxl_acpi_driver); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(CXL); diff --git a/drivers/cxl/bus.c b/drivers/cxl/bus.c deleted file mode 100644 index 58f74796d525..000000000000 --- a/drivers/cxl/bus.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ -#include -#include - -/** - * DOC: cxl bus - * - * The CXL bus provides namespace for control devices and a rendezvous - * point for cross-device interleave coordination. - */ -struct bus_type cxl_bus_type = { - .name = "cxl", -}; -EXPORT_SYMBOL_GPL(cxl_bus_type); - -static __init int cxl_bus_init(void) -{ - return bus_register(&cxl_bus_type); -} - -static void cxl_bus_exit(void) -{ - bus_unregister(&cxl_bus_type); -} - -module_init(cxl_bus_init); -module_exit(cxl_bus_exit); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c new file mode 100644 index 000000000000..a2e4d54fc7bc --- /dev/null +++ b/drivers/cxl/core.c @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include "cxl.h" +#include "mem.h" + +/** + * DOC: cxl core + * + * The CXL core provides a sysfs hierarchy for control devices and a rendezvous + * point for cross-device interleave coordination through cxl ports. + */ + +static DEFINE_IDA(cxl_port_ida); + +static ssize_t devtype_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "%s\n", dev->type->name); +} +static DEVICE_ATTR_RO(devtype); + +static struct attribute *cxl_base_attributes[] = { + &dev_attr_devtype.attr, + NULL, +}; + +static struct attribute_group cxl_base_attribute_group = { + .attrs = cxl_base_attributes, +}; + +static ssize_t start_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cxl_decoder *cxld = to_cxl_decoder(dev); + + return sysfs_emit(buf, "%#llx\n", cxld->range.start); +} +static DEVICE_ATTR_RO(start); + +static ssize_t size_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cxl_decoder *cxld = to_cxl_decoder(dev); + + return sysfs_emit(buf, "%#llx\n", range_len(&cxld->range)); +} +static DEVICE_ATTR_RO(size); + +#define CXL_DECODER_FLAG_ATTR(name, flag) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct cxl_decoder *cxld = to_cxl_decoder(dev); \ + \ + return sysfs_emit(buf, "%s\n", \ + (cxld->flags & (flag)) ? "1" : "0"); \ +} \ +static DEVICE_ATTR_RO(name) + +CXL_DECODER_FLAG_ATTR(cap_pmem, CXL_DECODER_F_PMEM); +CXL_DECODER_FLAG_ATTR(cap_ram, CXL_DECODER_F_RAM); +CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_TYPE2); +CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_TYPE3); +CXL_DECODER_FLAG_ATTR(locked, CXL_DECODER_F_LOCK); + +static ssize_t target_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_decoder *cxld = to_cxl_decoder(dev); + + switch (cxld->target_type) { + case CXL_DECODER_ACCELERATOR: + return sysfs_emit(buf, "accelerator\n"); + case CXL_DECODER_EXPANDER: + return sysfs_emit(buf, "expander\n"); + } + return -ENXIO; +} +static DEVICE_ATTR_RO(target_type); + +static ssize_t target_list_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_decoder *cxld = to_cxl_decoder(dev); + ssize_t offset = 0; + int i, rc = 0; + + device_lock(dev); + for (i = 0; i < cxld->interleave_ways; i++) { + struct cxl_dport *dport = cxld->target[i]; + struct cxl_dport *next = NULL; + + if (!dport) + break; + + if (i + 1 < cxld->interleave_ways) + next = cxld->target[i + 1]; + rc = sysfs_emit_at(buf, offset, "%d%s", dport->port_id, + next ? "," : ""); + if (rc < 0) + break; + offset += rc; + } + device_unlock(dev); + + if (rc < 0) + return rc; + + rc = sysfs_emit_at(buf, offset, "\n"); + if (rc < 0) + return rc; + + return offset + rc; +} +static DEVICE_ATTR_RO(target_list); + +static struct attribute *cxl_decoder_base_attrs[] = { + &dev_attr_start.attr, + &dev_attr_size.attr, + &dev_attr_locked.attr, + &dev_attr_target_list.attr, + NULL, +}; + +static struct attribute_group cxl_decoder_base_attribute_group = { + .attrs = cxl_decoder_base_attrs, +}; + +static struct attribute *cxl_decoder_root_attrs[] = { + &dev_attr_cap_pmem.attr, + &dev_attr_cap_ram.attr, + &dev_attr_cap_type2.attr, + &dev_attr_cap_type3.attr, + NULL, +}; + +static struct attribute_group cxl_decoder_root_attribute_group = { + .attrs = cxl_decoder_root_attrs, +}; + +static const struct attribute_group *cxl_decoder_root_attribute_groups[] = { + &cxl_decoder_root_attribute_group, + &cxl_decoder_base_attribute_group, + &cxl_base_attribute_group, + NULL, +}; + +static struct attribute *cxl_decoder_switch_attrs[] = { + &dev_attr_target_type.attr, + NULL, +}; + +static struct attribute_group cxl_decoder_switch_attribute_group = { + .attrs = cxl_decoder_switch_attrs, +}; + +static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = { + &cxl_decoder_switch_attribute_group, + &cxl_decoder_base_attribute_group, + &cxl_base_attribute_group, + NULL, +}; + +static void cxl_decoder_release(struct device *dev) +{ + struct cxl_decoder *cxld = to_cxl_decoder(dev); + struct cxl_port *port = to_cxl_port(dev->parent); + + ida_free(&port->decoder_ida, cxld->id); + kfree(cxld); +} + +static const struct device_type cxl_decoder_switch_type = { + .name = "cxl_decoder_switch", + .release = cxl_decoder_release, + .groups = cxl_decoder_switch_attribute_groups, +}; + +static const struct device_type cxl_decoder_root_type = { + .name = "cxl_decoder_root", + .release = cxl_decoder_release, + .groups = cxl_decoder_root_attribute_groups, +}; + +bool is_root_decoder(struct device *dev) +{ + return dev->type == &cxl_decoder_root_type; +} +EXPORT_SYMBOL_GPL(is_root_decoder); + +struct cxl_decoder *to_cxl_decoder(struct device *dev) +{ + if (dev_WARN_ONCE(dev, dev->type->release != cxl_decoder_release, + "not a cxl_decoder device\n")) + return NULL; + return container_of(dev, struct cxl_decoder, dev); +} +EXPORT_SYMBOL_GPL(to_cxl_decoder); + +static void cxl_dport_release(struct cxl_dport *dport) +{ + list_del(&dport->list); + put_device(dport->dport); + kfree(dport); +} + +static void cxl_port_release(struct device *dev) +{ + struct cxl_port *port = to_cxl_port(dev); + struct cxl_dport *dport, *_d; + + device_lock(dev); + list_for_each_entry_safe(dport, _d, &port->dports, list) + cxl_dport_release(dport); + device_unlock(dev); + ida_free(&cxl_port_ida, port->id); + kfree(port); +} + +static const struct attribute_group *cxl_port_attribute_groups[] = { + &cxl_base_attribute_group, + NULL, +}; + +static const struct device_type cxl_port_type = { + .name = "cxl_port", + .release = cxl_port_release, + .groups = cxl_port_attribute_groups, +}; + +struct cxl_port *to_cxl_port(struct device *dev) +{ + if (dev_WARN_ONCE(dev, dev->type != &cxl_port_type, + "not a cxl_port device\n")) + return NULL; + return container_of(dev, struct cxl_port, dev); +} + +static void unregister_port(void *_port) +{ + struct cxl_port *port = _port; + struct cxl_dport *dport; + + device_lock(&port->dev); + list_for_each_entry(dport, &port->dports, list) { + char link_name[CXL_TARGET_STRLEN]; + + if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", + dport->port_id) >= CXL_TARGET_STRLEN) + continue; + sysfs_remove_link(&port->dev.kobj, link_name); + } + device_unlock(&port->dev); + device_unregister(&port->dev); +} + +static void cxl_unlink_uport(void *_port) +{ + struct cxl_port *port = _port; + + sysfs_remove_link(&port->dev.kobj, "uport"); +} + +static int devm_cxl_link_uport(struct device *host, struct cxl_port *port) +{ + int rc; + + rc = sysfs_create_link(&port->dev.kobj, &port->uport->kobj, "uport"); + if (rc) + return rc; + return devm_add_action_or_reset(host, cxl_unlink_uport, port); +} + +static struct cxl_port *cxl_port_alloc(struct device *uport, + resource_size_t component_reg_phys, + struct cxl_port *parent_port) +{ + struct cxl_port *port; + struct device *dev; + int rc; + + port = kzalloc(sizeof(*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENOMEM); + + rc = ida_alloc(&cxl_port_ida, GFP_KERNEL); + if (rc < 0) + goto err; + port->id = rc; + + /* + * The top-level cxl_port "cxl_root" does not have a cxl_port as + * its parent and it does not have any corresponding component + * registers as its decode is described by a fixed platform + * description. + */ + dev = &port->dev; + if (parent_port) + dev->parent = &parent_port->dev; + else + dev->parent = uport; + + port->uport = uport; + port->component_reg_phys = component_reg_phys; + ida_init(&port->decoder_ida); + INIT_LIST_HEAD(&port->dports); + + device_initialize(dev); + device_set_pm_not_required(dev); + dev->bus = &cxl_bus_type; + dev->type = &cxl_port_type; + + return port; + +err: + kfree(port); + return ERR_PTR(rc); +} + +/** + * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy + * @host: host device for devm operations + * @uport: "physical" device implementing this upstream port + * @component_reg_phys: (optional) for configurable cxl_port instances + * @parent_port: next hop up in the CXL memory decode hierarchy + */ +struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, + resource_size_t component_reg_phys, + struct cxl_port *parent_port) +{ + struct cxl_port *port; + struct device *dev; + int rc; + + port = cxl_port_alloc(uport, component_reg_phys, parent_port); + if (IS_ERR(port)) + return port; + + dev = &port->dev; + if (parent_port) + rc = dev_set_name(dev, "port%d", port->id); + else + rc = dev_set_name(dev, "root%d", port->id); + if (rc) + goto err; + + rc = device_add(dev); + if (rc) + goto err; + + rc = devm_add_action_or_reset(host, unregister_port, port); + if (rc) + return ERR_PTR(rc); + + rc = devm_cxl_link_uport(host, port); + if (rc) + return ERR_PTR(rc); + + return port; + +err: + put_device(dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_GPL(devm_cxl_add_port); + +static struct cxl_dport *find_dport(struct cxl_port *port, int id) +{ + struct cxl_dport *dport; + + device_lock_assert(&port->dev); + list_for_each_entry (dport, &port->dports, list) + if (dport->port_id == id) + return dport; + return NULL; +} + +static int add_dport(struct cxl_port *port, struct cxl_dport *new) +{ + struct cxl_dport *dup; + + device_lock(&port->dev); + dup = find_dport(port, new->port_id); + if (dup) + dev_err(&port->dev, + "unable to add dport%d-%s non-unique port id (%s)\n", + new->port_id, dev_name(new->dport), + dev_name(dup->dport)); + else + list_add_tail(&new->list, &port->dports); + device_unlock(&port->dev); + + return dup ? -EEXIST : 0; +} + +/** + * cxl_add_dport - append downstream port data to a cxl_port + * @port: the cxl_port that references this dport + * @dport_dev: firmware or PCI device representing the dport + * @port_id: identifier for this dport in a decoder's target list + * @component_reg_phys: optional location of CXL component registers + * + * Note that all allocations and links are undone by cxl_port deletion + * and release. + */ +int cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id, + resource_size_t component_reg_phys) +{ + char link_name[CXL_TARGET_STRLEN]; + struct cxl_dport *dport; + int rc; + + if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", port_id) >= + CXL_TARGET_STRLEN) + return -EINVAL; + + dport = kzalloc(sizeof(*dport), GFP_KERNEL); + if (!dport) + return -ENOMEM; + + INIT_LIST_HEAD(&dport->list); + dport->dport = get_device(dport_dev); + dport->port_id = port_id; + dport->component_reg_phys = component_reg_phys; + dport->port = port; + + rc = add_dport(port, dport); + if (rc) + goto err; + + rc = sysfs_create_link(&port->dev.kobj, &dport_dev->kobj, link_name); + if (rc) + goto err; + + return 0; +err: + cxl_dport_release(dport); + return rc; +} +EXPORT_SYMBOL_GPL(cxl_add_dport); + +static struct cxl_decoder * +cxl_decoder_alloc(struct cxl_port *port, int nr_targets, resource_size_t base, + resource_size_t len, int interleave_ways, + int interleave_granularity, enum cxl_decoder_type type, + unsigned long flags) +{ + struct cxl_decoder *cxld; + struct device *dev; + int rc = 0; + + if (interleave_ways < 1) + return ERR_PTR(-EINVAL); + + device_lock(&port->dev); + if (list_empty(&port->dports)) + rc = -EINVAL; + device_unlock(&port->dev); + if (rc) + return ERR_PTR(rc); + + cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL); + if (!cxld) + return ERR_PTR(-ENOMEM); + + rc = ida_alloc(&port->decoder_ida, GFP_KERNEL); + if (rc < 0) + goto err; + + *cxld = (struct cxl_decoder) { + .id = rc, + .range = { + .start = base, + .end = base + len - 1, + }, + .flags = flags, + .interleave_ways = interleave_ways, + .interleave_granularity = interleave_granularity, + .target_type = type, + }; + + /* handle implied target_list */ + if (interleave_ways == 1) + cxld->target[0] = + list_first_entry(&port->dports, struct cxl_dport, list); + dev = &cxld->dev; + device_initialize(dev); + device_set_pm_not_required(dev); + dev->parent = &port->dev; + dev->bus = &cxl_bus_type; + + /* root ports do not have a cxl_port_type parent */ + if (port->dev.parent->type == &cxl_port_type) + dev->type = &cxl_decoder_switch_type; + else + dev->type = &cxl_decoder_root_type; + + return cxld; +err: + kfree(cxld); + return ERR_PTR(rc); +} + +static void unregister_dev(void *dev) +{ + device_unregister(dev); +} + +struct cxl_decoder * +devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets, + resource_size_t base, resource_size_t len, + int interleave_ways, int interleave_granularity, + enum cxl_decoder_type type, unsigned long flags) +{ + struct cxl_decoder *cxld; + struct device *dev; + int rc; + + cxld = cxl_decoder_alloc(port, nr_targets, base, len, interleave_ways, + interleave_granularity, type, flags); + if (IS_ERR(cxld)) + return cxld; + + dev = &cxld->dev; + rc = dev_set_name(dev, "decoder%d.%d", port->id, cxld->id); + if (rc) + goto err; + + rc = device_add(dev); + if (rc) + goto err; + + rc = devm_add_action_or_reset(host, unregister_dev, dev); + if (rc) + return ERR_PTR(rc); + return cxld; + +err: + put_device(dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_GPL(devm_cxl_add_decoder); + +/** + * cxl_probe_component_regs() - Detect CXL Component register blocks + * @dev: Host device of the @base mapping + * @base: Mapping containing the HDM Decoder Capability Header + * @map: Map object describing the register block information found + * + * See CXL 2.0 8.2.4 Component Register Layout and Definition + * See CXL 2.0 8.2.5.5 CXL Device Register Interface + * + * Probe for component register information and return it in map object. + */ +void cxl_probe_component_regs(struct device *dev, void __iomem *base, + struct cxl_component_reg_map *map) +{ + int cap, cap_count; + u64 cap_array; + + *map = (struct cxl_component_reg_map) { 0 }; + + /* + * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in + * CXL 2.0 8.2.4 Table 141. + */ + base += CXL_CM_OFFSET; + + cap_array = readq(base + CXL_CM_CAP_HDR_OFFSET); + + if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) { + dev_err(dev, + "Couldn't locate the CXL.cache and CXL.mem capability array header./n"); + return; + } + + /* It's assumed that future versions will be backward compatible */ + cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array); + + for (cap = 1; cap <= cap_count; cap++) { + void __iomem *register_block; + u32 hdr; + int decoder_cnt; + u16 cap_id, offset; + u32 length; + + hdr = readl(base + cap * 0x4); + + cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr); + offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr); + register_block = base + offset; + + switch (cap_id) { + case CXL_CM_CAP_CAP_ID_HDM: + dev_dbg(dev, "found HDM decoder capability (0x%x)\n", + offset); + + hdr = readl(register_block); + + decoder_cnt = cxl_hdm_decoder_count(hdr); + length = 0x20 * decoder_cnt + 0x10; + + map->hdm_decoder.valid = true; + map->hdm_decoder.offset = CXL_CM_OFFSET + offset; + map->hdm_decoder.size = length; + break; + default: + dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, + offset); + break; + } + } +} +EXPORT_SYMBOL_GPL(cxl_probe_component_regs); + +static void cxl_nvdimm_bridge_release(struct device *dev) +{ + struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev); + + kfree(cxl_nvb); +} + +static const struct attribute_group *cxl_nvdimm_bridge_attribute_groups[] = { + &cxl_base_attribute_group, + NULL, +}; + +static const struct device_type cxl_nvdimm_bridge_type = { + .name = "cxl_nvdimm_bridge", + .release = cxl_nvdimm_bridge_release, + .groups = cxl_nvdimm_bridge_attribute_groups, +}; + +struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev) +{ + if (dev_WARN_ONCE(dev, dev->type != &cxl_nvdimm_bridge_type, + "not a cxl_nvdimm_bridge device\n")) + return NULL; + return container_of(dev, struct cxl_nvdimm_bridge, dev); +} +EXPORT_SYMBOL_GPL(to_cxl_nvdimm_bridge); + +static struct cxl_nvdimm_bridge * +cxl_nvdimm_bridge_alloc(struct cxl_port *port) +{ + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + + cxl_nvb = kzalloc(sizeof(*cxl_nvb), GFP_KERNEL); + if (!cxl_nvb) + return ERR_PTR(-ENOMEM); + + dev = &cxl_nvb->dev; + cxl_nvb->port = port; + cxl_nvb->state = CXL_NVB_NEW; + device_initialize(dev); + device_set_pm_not_required(dev); + dev->parent = &port->dev; + dev->bus = &cxl_bus_type; + dev->type = &cxl_nvdimm_bridge_type; + + return cxl_nvb; +} + +static void unregister_nvb(void *_cxl_nvb) +{ + struct cxl_nvdimm_bridge *cxl_nvb = _cxl_nvb; + bool flush; + + /* + * If the bridge was ever activated then there might be in-flight state + * work to flush. Once the state has been changed to 'dead' then no new + * work can be queued by user-triggered bind. + */ + device_lock(&cxl_nvb->dev); + flush = cxl_nvb->state != CXL_NVB_NEW; + cxl_nvb->state = CXL_NVB_DEAD; + device_unlock(&cxl_nvb->dev); + + /* + * Even though the device core will trigger device_release_driver() + * before the unregister, it does not know about the fact that + * cxl_nvdimm_bridge_driver defers ->remove() work. So, do the driver + * release not and flush it before tearing down the nvdimm device + * hierarchy. + */ + device_release_driver(&cxl_nvb->dev); + if (flush) + flush_work(&cxl_nvb->state_work); + device_unregister(&cxl_nvb->dev); +} + +struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, + struct cxl_port *port) +{ + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + int rc; + + if (!IS_ENABLED(CONFIG_CXL_PMEM)) + return ERR_PTR(-ENXIO); + + cxl_nvb = cxl_nvdimm_bridge_alloc(port); + if (IS_ERR(cxl_nvb)) + return cxl_nvb; + + dev = &cxl_nvb->dev; + rc = dev_set_name(dev, "nvdimm-bridge"); + if (rc) + goto err; + + rc = device_add(dev); + if (rc) + goto err; + + rc = devm_add_action_or_reset(host, unregister_nvb, cxl_nvb); + if (rc) + return ERR_PTR(rc); + + return cxl_nvb; + +err: + put_device(dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_GPL(devm_cxl_add_nvdimm_bridge); + +static void cxl_nvdimm_release(struct device *dev) +{ + struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev); + + kfree(cxl_nvd); +} + +static const struct attribute_group *cxl_nvdimm_attribute_groups[] = { + &cxl_base_attribute_group, + NULL, +}; + +static const struct device_type cxl_nvdimm_type = { + .name = "cxl_nvdimm", + .release = cxl_nvdimm_release, + .groups = cxl_nvdimm_attribute_groups, +}; + +bool is_cxl_nvdimm(struct device *dev) +{ + return dev->type == &cxl_nvdimm_type; +} +EXPORT_SYMBOL_GPL(is_cxl_nvdimm); + +struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev) +{ + if (dev_WARN_ONCE(dev, !is_cxl_nvdimm(dev), + "not a cxl_nvdimm device\n")) + return NULL; + return container_of(dev, struct cxl_nvdimm, dev); +} +EXPORT_SYMBOL_GPL(to_cxl_nvdimm); + +static struct cxl_nvdimm *cxl_nvdimm_alloc(struct cxl_memdev *cxlmd) +{ + struct cxl_nvdimm *cxl_nvd; + struct device *dev; + + cxl_nvd = kzalloc(sizeof(*cxl_nvd), GFP_KERNEL); + if (!cxl_nvd) + return ERR_PTR(-ENOMEM); + + dev = &cxl_nvd->dev; + cxl_nvd->cxlmd = cxlmd; + device_initialize(dev); + device_set_pm_not_required(dev); + dev->parent = &cxlmd->dev; + dev->bus = &cxl_bus_type; + dev->type = &cxl_nvdimm_type; + + return cxl_nvd; +} + +int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd) +{ + struct cxl_nvdimm *cxl_nvd; + struct device *dev; + int rc; + + cxl_nvd = cxl_nvdimm_alloc(cxlmd); + if (IS_ERR(cxl_nvd)) + return PTR_ERR(cxl_nvd); + + dev = &cxl_nvd->dev; + rc = dev_set_name(dev, "pmem%d", cxlmd->id); + if (rc) + goto err; + + rc = device_add(dev); + if (rc) + goto err; + + dev_dbg(host, "%s: register %s\n", dev_name(dev->parent), + dev_name(dev)); + + return devm_add_action_or_reset(host, unregister_dev, dev); + +err: + put_device(dev); + return rc; +} +EXPORT_SYMBOL_GPL(devm_cxl_add_nvdimm); + +/** + * cxl_probe_device_regs() - Detect CXL Device register blocks + * @dev: Host device of the @base mapping + * @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface + * @map: Map object describing the register block information found + * + * Probe for device register information and return it in map object. + */ +void cxl_probe_device_regs(struct device *dev, void __iomem *base, + struct cxl_device_reg_map *map) +{ + int cap, cap_count; + u64 cap_array; + + *map = (struct cxl_device_reg_map){ 0 }; + + cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET); + if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) != + CXLDEV_CAP_ARRAY_CAP_ID) + return; + + cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array); + + for (cap = 1; cap <= cap_count; cap++) { + u32 offset, length; + u16 cap_id; + + cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK, + readl(base + cap * 0x10)); + offset = readl(base + cap * 0x10 + 0x4); + length = readl(base + cap * 0x10 + 0x8); + + switch (cap_id) { + case CXLDEV_CAP_CAP_ID_DEVICE_STATUS: + dev_dbg(dev, "found Status capability (0x%x)\n", offset); + + map->status.valid = true; + map->status.offset = offset; + map->status.size = length; + break; + case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX: + dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); + map->mbox.valid = true; + map->mbox.offset = offset; + map->mbox.size = length; + break; + case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX: + dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); + break; + case CXLDEV_CAP_CAP_ID_MEMDEV: + dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); + map->memdev.valid = true; + map->memdev.offset = offset; + map->memdev.size = length; + break; + default: + if (cap_id >= 0x8000) + dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset); + else + dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset); + break; + } + } +} +EXPORT_SYMBOL_GPL(cxl_probe_device_regs); + +static void __iomem *devm_cxl_iomap_block(struct device *dev, + resource_size_t addr, + resource_size_t length) +{ + void __iomem *ret_val; + struct resource *res; + + res = devm_request_mem_region(dev, addr, length, dev_name(dev)); + if (!res) { + resource_size_t end = addr + length - 1; + + dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end); + return NULL; + } + + ret_val = devm_ioremap(dev, addr, length); + if (!ret_val) + dev_err(dev, "Failed to map region %pr\n", res); + + return ret_val; +} + +int cxl_map_component_regs(struct pci_dev *pdev, + struct cxl_component_regs *regs, + struct cxl_register_map *map) +{ + struct device *dev = &pdev->dev; + resource_size_t phys_addr; + resource_size_t length; + + phys_addr = pci_resource_start(pdev, map->barno); + phys_addr += map->block_offset; + + phys_addr += map->component_map.hdm_decoder.offset; + length = map->component_map.hdm_decoder.size; + regs->hdm_decoder = devm_cxl_iomap_block(dev, phys_addr, length); + if (!regs->hdm_decoder) + return -ENOMEM; + + return 0; +} +EXPORT_SYMBOL_GPL(cxl_map_component_regs); + +int cxl_map_device_regs(struct pci_dev *pdev, + struct cxl_device_regs *regs, + struct cxl_register_map *map) +{ + struct device *dev = &pdev->dev; + resource_size_t phys_addr; + + phys_addr = pci_resource_start(pdev, map->barno); + phys_addr += map->block_offset; + + if (map->device_map.status.valid) { + resource_size_t addr; + resource_size_t length; + + addr = phys_addr + map->device_map.status.offset; + length = map->device_map.status.size; + regs->status = devm_cxl_iomap_block(dev, addr, length); + if (!regs->status) + return -ENOMEM; + } + + if (map->device_map.mbox.valid) { + resource_size_t addr; + resource_size_t length; + + addr = phys_addr + map->device_map.mbox.offset; + length = map->device_map.mbox.size; + regs->mbox = devm_cxl_iomap_block(dev, addr, length); + if (!regs->mbox) + return -ENOMEM; + } + + if (map->device_map.memdev.valid) { + resource_size_t addr; + resource_size_t length; + + addr = phys_addr + map->device_map.memdev.offset; + length = map->device_map.memdev.size; + regs->memdev = devm_cxl_iomap_block(dev, addr, length); + if (!regs->memdev) + return -ENOMEM; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cxl_map_device_regs); + +/** + * __cxl_driver_register - register a driver for the cxl bus + * @cxl_drv: cxl driver structure to attach + * @owner: owning module/driver + * @modname: KBUILD_MODNAME for parent driver + */ +int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, + const char *modname) +{ + if (!cxl_drv->probe) { + pr_debug("%s ->probe() must be specified\n", modname); + return -EINVAL; + } + + if (!cxl_drv->name) { + pr_debug("%s ->name must be specified\n", modname); + return -EINVAL; + } + + if (!cxl_drv->id) { + pr_debug("%s ->id must be specified\n", modname); + return -EINVAL; + } + + cxl_drv->drv.bus = &cxl_bus_type; + cxl_drv->drv.owner = owner; + cxl_drv->drv.mod_name = modname; + cxl_drv->drv.name = cxl_drv->name; + + return driver_register(&cxl_drv->drv); +} +EXPORT_SYMBOL_GPL(__cxl_driver_register); + +void cxl_driver_unregister(struct cxl_driver *cxl_drv) +{ + driver_unregister(&cxl_drv->drv); +} +EXPORT_SYMBOL_GPL(cxl_driver_unregister); + +static int cxl_device_id(struct device *dev) +{ + if (dev->type == &cxl_nvdimm_bridge_type) + return CXL_DEVICE_NVDIMM_BRIDGE; + if (dev->type == &cxl_nvdimm_type) + return CXL_DEVICE_NVDIMM; + return 0; +} + +static int cxl_bus_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + return add_uevent_var(env, "MODALIAS=" CXL_MODALIAS_FMT, + cxl_device_id(dev)); +} + +static int cxl_bus_match(struct device *dev, struct device_driver *drv) +{ + return cxl_device_id(dev) == to_cxl_drv(drv)->id; +} + +static int cxl_bus_probe(struct device *dev) +{ + return to_cxl_drv(dev->driver)->probe(dev); +} + +static int cxl_bus_remove(struct device *dev) +{ + struct cxl_driver *cxl_drv = to_cxl_drv(dev->driver); + + if (cxl_drv->remove) + cxl_drv->remove(dev); + return 0; +} + +struct bus_type cxl_bus_type = { + .name = "cxl", + .uevent = cxl_bus_uevent, + .match = cxl_bus_match, + .probe = cxl_bus_probe, + .remove = cxl_bus_remove, +}; +EXPORT_SYMBOL_GPL(cxl_bus_type); + +static __init int cxl_core_init(void) +{ + return bus_register(&cxl_bus_type); +} + +static void cxl_core_exit(void) +{ + bus_unregister(&cxl_bus_type); +} + +module_init(cxl_core_init); +module_exit(cxl_core_exit); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 6f14838c2d25..b6bda39a59e3 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -4,10 +4,51 @@ #ifndef __CXL_H__ #define __CXL_H__ +#include #include #include #include +/** + * DOC: cxl objects + * + * The CXL core objects like ports, decoders, and regions are shared + * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers + * (port-driver, region-driver, nvdimm object-drivers... etc). + */ + +/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ +#define CXL_CM_OFFSET 0x1000 +#define CXL_CM_CAP_HDR_OFFSET 0x0 +#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) +#define CM_CAP_HDR_CAP_ID 1 +#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) +#define CM_CAP_HDR_CAP_VERSION 1 +#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) +#define CM_CAP_HDR_CACHE_MEM_VERSION 1 +#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) +#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) + +#define CXL_CM_CAP_CAP_ID_HDM 0x5 +#define CXL_CM_CAP_CAP_HDM_VERSION 1 + +/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ +#define CXL_HDM_DECODER_CAP_OFFSET 0x0 +#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) +#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) +#define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10 +#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14 +#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET 0x18 +#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c +#define CXL_HDM_DECODER0_CTRL_OFFSET 0x20 + +static inline int cxl_hdm_decoder_count(u32 cap_hdr) +{ + int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); + + return val ? val * 2 : 1; +} + /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 #define CXLDEV_CAP_ARRAY_CAP_ID 0 @@ -34,62 +75,253 @@ #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 -/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ -#define CXLMDEV_STATUS_OFFSET 0x0 -#define CXLMDEV_DEV_FATAL BIT(0) -#define CXLMDEV_FW_HALT BIT(1) -#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) -#define CXLMDEV_MS_NOT_READY 0 -#define CXLMDEV_MS_READY 1 -#define CXLMDEV_MS_ERROR 2 -#define CXLMDEV_MS_DISABLED 3 -#define CXLMDEV_READY(status) \ - (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ - CXLMDEV_MS_READY) -#define CXLMDEV_MBOX_IF_READY BIT(4) -#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) -#define CXLMDEV_RESET_NEEDED_NOT 0 -#define CXLMDEV_RESET_NEEDED_COLD 1 -#define CXLMDEV_RESET_NEEDED_WARM 2 -#define CXLMDEV_RESET_NEEDED_HOT 3 -#define CXLMDEV_RESET_NEEDED_CXL 4 -#define CXLMDEV_RESET_NEEDED(status) \ - (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ - CXLMDEV_RESET_NEEDED_NOT) +#define CXL_COMPONENT_REGS() \ + void __iomem *hdm_decoder -struct cxl_memdev; -/** - * struct cxl_mem - A CXL memory device - * @pdev: The PCI device associated with this CXL device. - * @regs: IO mappings to the device's MMIO - * @status_regs: CXL 2.0 8.2.8.3 Device Status Registers - * @mbox_regs: CXL 2.0 8.2.8.4 Mailbox Registers - * @memdev_regs: CXL 2.0 8.2.8.5 Memory Device Registers - * @payload_size: Size of space for payload - * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) - * @mbox_mutex: Mutex to synchronize mailbox access. - * @firmware_version: Firmware version for the memory device. - * @enabled_commands: Hardware commands found enabled in CEL. - * @pmem_range: Persistent memory capacity information. - * @ram_range: Volatile memory capacity information. +#define CXL_DEVICE_REGS() \ + void __iomem *status; \ + void __iomem *mbox; \ + void __iomem *memdev + +/* See note for 'struct cxl_regs' for the rationale of this organization */ +/* + * CXL_COMPONENT_REGS - Common set of CXL Component register block base pointers + * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ -struct cxl_mem { - struct pci_dev *pdev; - void __iomem *regs; - struct cxl_memdev *cxlmd; - - void __iomem *status_regs; - void __iomem *mbox_regs; - void __iomem *memdev_regs; - - size_t payload_size; - struct mutex mbox_mutex; /* Protects device mailbox and firmware */ - char firmware_version[0x10]; - unsigned long *enabled_cmds; - - struct range pmem_range; - struct range ram_range; +struct cxl_component_regs { + CXL_COMPONENT_REGS(); }; +/* See note for 'struct cxl_regs' for the rationale of this organization */ +/* + * CXL_DEVICE_REGS - Common set of CXL Device register block base pointers + * @status: CXL 2.0 8.2.8.3 Device Status Registers + * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers + * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers + */ +struct cxl_device_regs { + CXL_DEVICE_REGS(); +}; + +/* + * Note, the anonymous union organization allows for per + * register-block-type helper routines, without requiring block-type + * agnostic code to include the prefix. + */ +struct cxl_regs { + union { + struct { + CXL_COMPONENT_REGS(); + }; + struct cxl_component_regs component; + }; + union { + struct { + CXL_DEVICE_REGS(); + }; + struct cxl_device_regs device_regs; + }; +}; + +struct cxl_reg_map { + bool valid; + unsigned long offset; + unsigned long size; +}; + +struct cxl_component_reg_map { + struct cxl_reg_map hdm_decoder; +}; + +struct cxl_device_reg_map { + struct cxl_reg_map status; + struct cxl_reg_map mbox; + struct cxl_reg_map memdev; +}; + +struct cxl_register_map { + struct list_head list; + u64 block_offset; + u8 reg_type; + u8 barno; + union { + struct cxl_component_reg_map component_map; + struct cxl_device_reg_map device_map; + }; +}; + +void cxl_probe_component_regs(struct device *dev, void __iomem *base, + struct cxl_component_reg_map *map); +void cxl_probe_device_regs(struct device *dev, void __iomem *base, + struct cxl_device_reg_map *map); +int cxl_map_component_regs(struct pci_dev *pdev, + struct cxl_component_regs *regs, + struct cxl_register_map *map); +int cxl_map_device_regs(struct pci_dev *pdev, + struct cxl_device_regs *regs, + struct cxl_register_map *map); + +#define CXL_RESOURCE_NONE ((resource_size_t) -1) +#define CXL_TARGET_STRLEN 20 + +/* + * cxl_decoder flags that define the type of memory / devices this + * decoder supports as well as configuration lock status See "CXL 2.0 + * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. + */ +#define CXL_DECODER_F_RAM BIT(0) +#define CXL_DECODER_F_PMEM BIT(1) +#define CXL_DECODER_F_TYPE2 BIT(2) +#define CXL_DECODER_F_TYPE3 BIT(3) +#define CXL_DECODER_F_LOCK BIT(4) +#define CXL_DECODER_F_MASK GENMASK(4, 0) + +enum cxl_decoder_type { + CXL_DECODER_ACCELERATOR = 2, + CXL_DECODER_EXPANDER = 3, +}; + +/** + * struct cxl_decoder - CXL address range decode configuration + * @dev: this decoder's device + * @id: kernel device name id + * @range: address range considered by this decoder + * @interleave_ways: number of cxl_dports in this decode + * @interleave_granularity: data stride per dport + * @target_type: accelerator vs expander (type2 vs type3) selector + * @flags: memory type capabilities and locking + * @target: active ordered target list in current decoder configuration + */ +struct cxl_decoder { + struct device dev; + int id; + struct range range; + int interleave_ways; + int interleave_granularity; + enum cxl_decoder_type target_type; + unsigned long flags; + struct cxl_dport *target[]; +}; + + +enum cxl_nvdimm_brige_state { + CXL_NVB_NEW, + CXL_NVB_DEAD, + CXL_NVB_ONLINE, + CXL_NVB_OFFLINE, +}; + +struct cxl_nvdimm_bridge { + struct device dev; + struct cxl_port *port; + struct nvdimm_bus *nvdimm_bus; + struct nvdimm_bus_descriptor nd_desc; + struct work_struct state_work; + enum cxl_nvdimm_brige_state state; +}; + +struct cxl_nvdimm { + struct device dev; + struct cxl_memdev *cxlmd; + struct nvdimm *nvdimm; +}; + +/** + * struct cxl_port - logical collection of upstream port devices and + * downstream port devices to construct a CXL memory + * decode hierarchy. + * @dev: this port's device + * @uport: PCI or platform device implementing the upstream port capability + * @id: id for port device-name + * @dports: cxl_dport instances referenced by decoders + * @decoder_ida: allocator for decoder ids + * @component_reg_phys: component register capability base address (optional) + */ +struct cxl_port { + struct device dev; + struct device *uport; + int id; + struct list_head dports; + struct ida decoder_ida; + resource_size_t component_reg_phys; +}; + +/** + * struct cxl_dport - CXL downstream port + * @dport: PCI bridge or firmware device representing the downstream link + * @port_id: unique hardware identifier for dport in decoder target list + * @component_reg_phys: downstream port component registers + * @port: reference to cxl_port that contains this downstream port + * @list: node for a cxl_port's list of cxl_dport instances + */ +struct cxl_dport { + struct device *dport; + int port_id; + resource_size_t component_reg_phys; + struct cxl_port *port; + struct list_head list; +}; + +struct cxl_port *to_cxl_port(struct device *dev); +struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, + resource_size_t component_reg_phys, + struct cxl_port *parent_port); + +int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id, + resource_size_t component_reg_phys); + +struct cxl_decoder *to_cxl_decoder(struct device *dev); +bool is_root_decoder(struct device *dev); +struct cxl_decoder * +devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets, + resource_size_t base, resource_size_t len, + int interleave_ways, int interleave_granularity, + enum cxl_decoder_type type, unsigned long flags); + +/* + * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure) + * single ported host-bridges need not publish a decoder capability when a + * passthrough decode can be assumed, i.e. all transactions that the uport sees + * are claimed and passed to the single dport. Default the range a 0-base + * 0-length until the first CXL region is activated. + */ +static inline struct cxl_decoder * +devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port) +{ + return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE, + CXL_DECODER_EXPANDER, 0); +} + extern struct bus_type cxl_bus_type; + +struct cxl_driver { + const char *name; + int (*probe)(struct device *dev); + void (*remove)(struct device *dev); + struct device_driver drv; + int id; +}; + +static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) +{ + return container_of(drv, struct cxl_driver, drv); +} + +int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, + const char *modname); +#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) +void cxl_driver_unregister(struct cxl_driver *cxl_drv); + +#define CXL_DEVICE_NVDIMM_BRIDGE 1 +#define CXL_DEVICE_NVDIMM 2 + +#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") +#define CXL_MODALIAS_FMT "cxl:t%d" + +struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); +struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, + struct cxl_port *port); +struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); +bool is_cxl_nvdimm(struct device *dev); +int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd); #endif /* __CXL_H__ */ diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h new file mode 100644 index 000000000000..8f02d02b26b4 --- /dev/null +++ b/drivers/cxl/mem.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2020-2021 Intel Corporation. */ +#ifndef __CXL_MEM_H__ +#define __CXL_MEM_H__ +#include +#include "cxl.h" + +/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ +#define CXLMDEV_STATUS_OFFSET 0x0 +#define CXLMDEV_DEV_FATAL BIT(0) +#define CXLMDEV_FW_HALT BIT(1) +#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) +#define CXLMDEV_MS_NOT_READY 0 +#define CXLMDEV_MS_READY 1 +#define CXLMDEV_MS_ERROR 2 +#define CXLMDEV_MS_DISABLED 3 +#define CXLMDEV_READY(status) \ + (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ + CXLMDEV_MS_READY) +#define CXLMDEV_MBOX_IF_READY BIT(4) +#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) +#define CXLMDEV_RESET_NEEDED_NOT 0 +#define CXLMDEV_RESET_NEEDED_COLD 1 +#define CXLMDEV_RESET_NEEDED_WARM 2 +#define CXLMDEV_RESET_NEEDED_HOT 3 +#define CXLMDEV_RESET_NEEDED_CXL 4 +#define CXLMDEV_RESET_NEEDED(status) \ + (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ + CXLMDEV_RESET_NEEDED_NOT) + +/* + * An entire PCI topology full of devices should be enough for any + * config + */ +#define CXL_MEM_MAX_DEVS 65536 + +/** + * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device + * @dev: driver core device object + * @cdev: char dev core object for ioctl operations + * @cxlm: pointer to the parent device driver data + * @id: id number of this memdev instance. + */ +struct cxl_memdev { + struct device dev; + struct cdev cdev; + struct cxl_mem *cxlm; + int id; +}; + +/** + * struct cxl_mem - A CXL memory device + * @pdev: The PCI device associated with this CXL device. + * @cxlmd: Logical memory device chardev / interface + * @regs: Parsed register blocks + * @payload_size: Size of space for payload + * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) + * @lsa_size: Size of Label Storage Area + * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) + * @mbox_mutex: Mutex to synchronize mailbox access. + * @firmware_version: Firmware version for the memory device. + * @enabled_cmds: Hardware commands found enabled in CEL. + * @pmem_range: Persistent memory capacity information. + * @ram_range: Volatile memory capacity information. + */ +struct cxl_mem { + struct pci_dev *pdev; + struct cxl_memdev *cxlmd; + + struct cxl_regs regs; + + size_t payload_size; + size_t lsa_size; + struct mutex mbox_mutex; /* Protects device mailbox and firmware */ + char firmware_version[0x10]; + unsigned long *enabled_cmds; + + struct range pmem_range; + struct range ram_range; +}; +#endif /* __CXL_MEM_H__ */ diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c similarity index 86% rename from drivers/cxl/mem.c rename to drivers/cxl/pci.c index 2acc6173da36..4cf351a3cf99 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/pci.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -13,12 +14,14 @@ #include #include "pci.h" #include "cxl.h" +#include "mem.h" /** - * DOC: cxl mem + * DOC: cxl pci * - * This implements a CXL memory device ("type-3") as it is defined by the - * Compute Express Link specification. + * This implements the PCI exclusive functionality for a CXL device as it is + * defined by the Compute Express Link specification. CXL devices may surface + * certain functionality even if it isn't CXL enabled. * * The driver has several responsibilities, mainly: * - Create the memX device and register on the CXL bus. @@ -26,18 +29,10 @@ * - Probe the device attributes to establish sysfs interface. * - Provide an IOCTL interface to userspace to communicate with the device for * things like firmware update. - * - Support management of interleave sets. - * - Handle and manage error conditions. */ -/* - * An entire PCI topology full of devices should be enough for any - * config - */ -#define CXL_MEM_MAX_DEVS 65536 - #define cxl_doorbell_busy(cxlm) \ - (readl((cxlm)->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET) & \ + (readl((cxlm)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ CXLDEV_MBOX_CTRL_DOORBELL) /* CXL 2.0 - 8.2.8.4 */ @@ -56,7 +51,14 @@ enum opcode { CXL_MBOX_OP_GET_LSA = 0x4102, CXL_MBOX_OP_SET_LSA = 0x4103, CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, + CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, + CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, + CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, + CXL_MBOX_OP_GET_POISON = 0x4300, + CXL_MBOX_OP_INJECT_POISON = 0x4301, + CXL_MBOX_OP_CLEAR_POISON = 0x4302, + CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, CXL_MBOX_OP_SCAN_MEDIA = 0x4304, CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, CXL_MBOX_OP_MAX = 0x10000 @@ -92,20 +94,6 @@ struct mbox_cmd { #define CXL_MBOX_SUCCESS 0 }; -/** - * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device - * @dev: driver core device object - * @cdev: char dev core object for ioctl operations - * @cxlm: pointer to the parent device driver data - * @id: id number of this memdev instance. - */ -struct cxl_memdev { - struct device dev; - struct cdev cdev; - struct cxl_mem *cxlm; - int id; -}; - static int cxl_mem_major; static DEFINE_IDA(cxl_memdev_ida); static DECLARE_RWSEM(cxl_memdev_rwsem); @@ -178,6 +166,18 @@ static struct cxl_mem_command mem_commands[CXL_MEM_COMMAND_ID_MAX] = { CXL_CMD(GET_LSA, 0x8, ~0, 0), CXL_CMD(GET_HEALTH_INFO, 0, 0x12, 0), CXL_CMD(GET_LOG, 0x18, ~0, CXL_CMD_FLAG_FORCE_ENABLE), + CXL_CMD(SET_PARTITION_INFO, 0x0a, 0, 0), + CXL_CMD(SET_LSA, ~0, 0, 0), + CXL_CMD(GET_ALERT_CONFIG, 0, 0x10, 0), + CXL_CMD(SET_ALERT_CONFIG, 0xc, 0, 0), + CXL_CMD(GET_SHUTDOWN_STATE, 0, 0x1, 0), + CXL_CMD(SET_SHUTDOWN_STATE, 0x1, 0, 0), + CXL_CMD(GET_POISON, 0x10, ~0, 0), + CXL_CMD(INJECT_POISON, 0x8, 0, 0), + CXL_CMD(CLEAR_POISON, 0x48, 0, 0), + CXL_CMD(GET_SCAN_MEDIA_CAPS, 0x10, 0x4, 0), + CXL_CMD(SCAN_MEDIA, 0x11, 0, 0), + CXL_CMD(GET_SCAN_MEDIA, 0, ~0, 0), }; /* @@ -292,7 +292,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, struct mbox_cmd *mbox_cmd) { - void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; + void __iomem *payload = cxlm->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; u64 cmd_reg, status_reg; size_t out_len; int rc; @@ -335,12 +335,12 @@ static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, } /* #2, #3 */ - writeq(cmd_reg, cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); + writeq(cmd_reg, cxlm->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); /* #4 */ dev_dbg(&cxlm->pdev->dev, "Sending command\n"); writel(CXLDEV_MBOX_CTRL_DOORBELL, - cxlm->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET); + cxlm->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); /* #5 */ rc = cxl_mem_wait_for_doorbell(cxlm); @@ -350,7 +350,7 @@ static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, } /* #6 */ - status_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_STATUS_OFFSET); + status_reg = readq(cxlm->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); mbox_cmd->return_code = FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); @@ -360,7 +360,7 @@ static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, } /* #7 */ - cmd_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); + cmd_reg = readq(cxlm->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); /* #8 */ @@ -421,7 +421,7 @@ static int cxl_mem_mbox_get(struct cxl_mem *cxlm) goto out; } - md_status = readq(cxlm->memdev_regs + CXLMDEV_STATUS_OFFSET); + md_status = readq(cxlm->regs.memdev + CXLMDEV_STATUS_OFFSET); if (!(md_status & CXLMDEV_MBOX_IF_READY && CXLMDEV_READY(md_status))) { dev_err(dev, "mbox: reported doorbell ready, but not mbox ready\n"); rc = -EBUSY; @@ -890,75 +890,9 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, return 0; } -/** - * cxl_mem_setup_regs() - Setup necessary MMIO. - * @cxlm: The CXL memory device to communicate with. - * - * Return: 0 if all necessary registers mapped. - * - * A memory device is required by spec to implement a certain set of MMIO - * regions. The purpose of this function is to enumerate and map those - * registers. - */ -static int cxl_mem_setup_regs(struct cxl_mem *cxlm) -{ - struct device *dev = &cxlm->pdev->dev; - int cap, cap_count; - u64 cap_array; - - cap_array = readq(cxlm->regs + CXLDEV_CAP_ARRAY_OFFSET); - if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) != - CXLDEV_CAP_ARRAY_CAP_ID) - return -ENODEV; - - cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array); - - for (cap = 1; cap <= cap_count; cap++) { - void __iomem *register_block; - u32 offset; - u16 cap_id; - - cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK, - readl(cxlm->regs + cap * 0x10)); - offset = readl(cxlm->regs + cap * 0x10 + 0x4); - register_block = cxlm->regs + offset; - - switch (cap_id) { - case CXLDEV_CAP_CAP_ID_DEVICE_STATUS: - dev_dbg(dev, "found Status capability (0x%x)\n", offset); - cxlm->status_regs = register_block; - break; - case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX: - dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); - cxlm->mbox_regs = register_block; - break; - case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX: - dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); - break; - case CXLDEV_CAP_CAP_ID_MEMDEV: - dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); - cxlm->memdev_regs = register_block; - break; - default: - dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset); - break; - } - } - - if (!cxlm->status_regs || !cxlm->mbox_regs || !cxlm->memdev_regs) { - dev_err(dev, "registers not found: %s%s%s\n", - !cxlm->status_regs ? "status " : "", - !cxlm->mbox_regs ? "mbox " : "", - !cxlm->memdev_regs ? "memdev" : ""); - return -ENXIO; - } - - return 0; -} - static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm) { - const int cap = readl(cxlm->mbox_regs + CXLDEV_MBOX_CAPS_OFFSET); + const int cap = readl(cxlm->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); cxlm->payload_size = 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); @@ -983,55 +917,62 @@ static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm) return 0; } -static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, - u32 reg_hi) +static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev) { struct device *dev = &pdev->dev; struct cxl_mem *cxlm; - void __iomem *regs; - u64 offset; - u8 bar; - int rc; - cxlm = devm_kzalloc(&pdev->dev, sizeof(*cxlm), GFP_KERNEL); + cxlm = devm_kzalloc(dev, sizeof(*cxlm), GFP_KERNEL); if (!cxlm) { dev_err(dev, "No memory available\n"); - return NULL; + return ERR_PTR(-ENOMEM); } - offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK); - bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); - - /* Basic sanity check that BAR is big enough */ - if (pci_resource_len(pdev, bar) < offset) { - dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, - &pdev->resource[bar], (unsigned long long)offset); - return NULL; - } - - rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev)); - if (rc) { - dev_err(dev, "failed to map registers\n"); - return NULL; - } - regs = pcim_iomap_table(pdev)[bar]; - mutex_init(&cxlm->mbox_mutex); cxlm->pdev = pdev; - cxlm->regs = regs + offset; cxlm->enabled_cmds = devm_kmalloc_array(dev, BITS_TO_LONGS(cxl_cmd_count), sizeof(unsigned long), GFP_KERNEL | __GFP_ZERO); if (!cxlm->enabled_cmds) { dev_err(dev, "No memory available for bitmap\n"); - return NULL; + return ERR_PTR(-ENOMEM); } - dev_dbg(dev, "Mapped CXL Memory Device resource\n"); return cxlm; } +static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm, + u8 bar, u64 offset) +{ + struct pci_dev *pdev = cxlm->pdev; + struct device *dev = &pdev->dev; + void __iomem *addr; + + /* Basic sanity check that BAR is big enough */ + if (pci_resource_len(pdev, bar) < offset) { + dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, + &pdev->resource[bar], (unsigned long long)offset); + return IOMEM_ERR_PTR(-ENXIO); + } + + addr = pci_iomap(pdev, bar, 0); + if (!addr) { + dev_err(dev, "failed to map registers\n"); + return addr; + } + + dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n", + bar, offset); + + return addr; +} + +static void cxl_mem_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base) +{ + pci_iounmap(cxlm->pdev, base); +} + static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) { int pos; @@ -1055,6 +996,171 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) return 0; } +static int cxl_probe_regs(struct cxl_mem *cxlm, void __iomem *base, + struct cxl_register_map *map) +{ + struct pci_dev *pdev = cxlm->pdev; + struct device *dev = &pdev->dev; + struct cxl_component_reg_map *comp_map; + struct cxl_device_reg_map *dev_map; + + switch (map->reg_type) { + case CXL_REGLOC_RBI_COMPONENT: + comp_map = &map->component_map; + cxl_probe_component_regs(dev, base, comp_map); + if (!comp_map->hdm_decoder.valid) { + dev_err(dev, "HDM decoder registers not found\n"); + return -ENXIO; + } + + dev_dbg(dev, "Set up component registers\n"); + break; + case CXL_REGLOC_RBI_MEMDEV: + dev_map = &map->device_map; + cxl_probe_device_regs(dev, base, dev_map); + if (!dev_map->status.valid || !dev_map->mbox.valid || + !dev_map->memdev.valid) { + dev_err(dev, "registers not found: %s%s%s\n", + !dev_map->status.valid ? "status " : "", + !dev_map->mbox.valid ? "status " : "", + !dev_map->memdev.valid ? "status " : ""); + return -ENXIO; + } + + dev_dbg(dev, "Probing device registers...\n"); + break; + default: + break; + } + + return 0; +} + +static int cxl_map_regs(struct cxl_mem *cxlm, struct cxl_register_map *map) +{ + struct pci_dev *pdev = cxlm->pdev; + struct device *dev = &pdev->dev; + + switch (map->reg_type) { + case CXL_REGLOC_RBI_COMPONENT: + cxl_map_component_regs(pdev, &cxlm->regs.component, map); + dev_dbg(dev, "Mapping component registers...\n"); + break; + case CXL_REGLOC_RBI_MEMDEV: + cxl_map_device_regs(pdev, &cxlm->regs.device_regs, map); + dev_dbg(dev, "Probing device registers...\n"); + break; + default: + break; + } + + return 0; +} + +static void cxl_decode_register_block(u32 reg_lo, u32 reg_hi, + u8 *bar, u64 *offset, u8 *reg_type) +{ + *offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK); + *bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); + *reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); +} + +/** + * cxl_mem_setup_regs() - Setup necessary MMIO. + * @cxlm: The CXL memory device to communicate with. + * + * Return: 0 if all necessary registers mapped. + * + * A memory device is required by spec to implement a certain set of MMIO + * regions. The purpose of this function is to enumerate and map those + * registers. + */ +static int cxl_mem_setup_regs(struct cxl_mem *cxlm) +{ + struct pci_dev *pdev = cxlm->pdev; + struct device *dev = &pdev->dev; + u32 regloc_size, regblocks; + void __iomem *base; + int regloc, i; + struct cxl_register_map *map, *n; + LIST_HEAD(register_maps); + int ret = 0; + + regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID); + if (!regloc) { + dev_err(dev, "register location dvsec not found\n"); + return -ENXIO; + } + + if (pci_request_mem_regions(pdev, pci_name(pdev))) + return -ENODEV; + + /* Get the size of the Register Locator DVSEC */ + pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); + regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); + + regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; + regblocks = (regloc_size - PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET) / 8; + + for (i = 0; i < regblocks; i++, regloc += 8) { + u32 reg_lo, reg_hi; + u8 reg_type; + u64 offset; + u8 bar; + + map = kzalloc(sizeof(*map), GFP_KERNEL); + if (!map) { + ret = -ENOMEM; + goto free_maps; + } + + list_add(&map->list, ®ister_maps); + + pci_read_config_dword(pdev, regloc, ®_lo); + pci_read_config_dword(pdev, regloc + 4, ®_hi); + + cxl_decode_register_block(reg_lo, reg_hi, &bar, &offset, + ®_type); + + dev_dbg(dev, "Found register block in bar %u @ 0x%llx of type %u\n", + bar, offset, reg_type); + + base = cxl_mem_map_regblock(cxlm, bar, offset); + if (!base) { + ret = -ENOMEM; + goto free_maps; + } + + map->barno = bar; + map->block_offset = offset; + map->reg_type = reg_type; + + ret = cxl_probe_regs(cxlm, base + offset, map); + + /* Always unmap the regblock regardless of probe success */ + cxl_mem_unmap_regblock(cxlm, base); + + if (ret) + goto free_maps; + } + + pci_release_mem_regions(pdev); + + list_for_each_entry(map, ®ister_maps, list) { + ret = cxl_map_regs(cxlm, map); + if (ret) + goto free_maps; + } + +free_maps: + list_for_each_entry_safe(map, n, ®ister_maps, list) { + list_del(&map->list); + kfree(map); + } + + return ret; +} + static struct cxl_memdev *to_cxl_memdev(struct device *dev) { return container_of(dev, struct cxl_memdev, dev); @@ -1094,6 +1200,16 @@ static ssize_t payload_max_show(struct device *dev, } static DEVICE_ATTR_RO(payload_max); +static ssize_t label_storage_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_mem *cxlm = cxlmd->cxlm; + + return sysfs_emit(buf, "%zu\n", cxlm->lsa_size); +} +static DEVICE_ATTR_RO(label_storage_size); + static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1123,6 +1239,7 @@ static struct device_attribute dev_attr_pmem_size = static struct attribute *cxl_memdev_attributes[] = { &dev_attr_firmware_version.attr, &dev_attr_payload_max.attr, + &dev_attr_label_storage_size.attr, NULL, }; @@ -1215,7 +1332,8 @@ err: return ERR_PTR(rc); } -static int cxl_mem_add_memdev(struct cxl_mem *cxlm) +static struct cxl_memdev *devm_cxl_add_memdev(struct device *host, + struct cxl_mem *cxlm) { struct cxl_memdev *cxlmd; struct device *dev; @@ -1224,7 +1342,7 @@ static int cxl_mem_add_memdev(struct cxl_mem *cxlm) cxlmd = cxl_memdev_alloc(cxlm); if (IS_ERR(cxlmd)) - return PTR_ERR(cxlmd); + return cxlmd; dev = &cxlmd->dev; rc = dev_set_name(dev, "mem%d", cxlmd->id); @@ -1242,8 +1360,10 @@ static int cxl_mem_add_memdev(struct cxl_mem *cxlm) if (rc) goto err; - return devm_add_action_or_reset(dev->parent, cxl_memdev_unregister, - cxlmd); + rc = devm_add_action_or_reset(host, cxl_memdev_unregister, cxlmd); + if (rc) + return ERR_PTR(rc); + return cxlmd; err: /* @@ -1252,7 +1372,7 @@ err: */ cxl_memdev_shutdown(cxlmd); put_device(dev); - return rc; + return ERR_PTR(rc); } static int cxl_xfer_log(struct cxl_mem *cxlm, uuid_t *uuid, u32 size, u8 *out) @@ -1455,6 +1575,7 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) cxlm->pmem_range.end = le64_to_cpu(id.persistent_capacity) * SZ_256M - 1; + cxlm->lsa_size = le32_to_cpu(id.lsa_size); memcpy(cxlm->firmware_version, id.fw_revision, sizeof(id.fw_revision)); return 0; @@ -1462,46 +1583,17 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - struct device *dev = &pdev->dev; - struct cxl_mem *cxlm = NULL; - u32 regloc_size, regblocks; - int rc, regloc, i; + struct cxl_memdev *cxlmd; + struct cxl_mem *cxlm; + int rc; rc = pcim_enable_device(pdev); if (rc) return rc; - regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET); - if (!regloc) { - dev_err(dev, "register location dvsec not found\n"); - return -ENXIO; - } - - /* Get the size of the Register Locator DVSEC */ - pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); - regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); - - regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; - regblocks = (regloc_size - PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET) / 8; - - for (i = 0; i < regblocks; i++, regloc += 8) { - u32 reg_lo, reg_hi; - u8 reg_type; - - /* "register low and high" contain other bits */ - pci_read_config_dword(pdev, regloc, ®_lo); - pci_read_config_dword(pdev, regloc + 4, ®_hi); - - reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); - - if (reg_type == CXL_REGLOC_RBI_MEMDEV) { - cxlm = cxl_mem_create(pdev, reg_lo, reg_hi); - break; - } - } - - if (!cxlm) - return -ENODEV; + cxlm = cxl_mem_create(pdev); + if (IS_ERR(cxlm)) + return PTR_ERR(cxlm); rc = cxl_mem_setup_regs(cxlm); if (rc) @@ -1519,7 +1611,14 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; - return cxl_mem_add_memdev(cxlm); + cxlmd = devm_cxl_add_memdev(&pdev->dev, cxlm); + if (IS_ERR(cxlmd)) + return PTR_ERR(cxlmd); + + if (range_len(&cxlm->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM)) + rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd); + + return rc; } static const struct pci_device_id cxl_mem_pci_tbl[] = { @@ -1544,6 +1643,10 @@ static __init int cxl_mem_init(void) dev_t devt; int rc; + /* Double check the anonymous union trickery in struct cxl_regs */ + BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != + offsetof(struct cxl_regs, device_regs.memdev)); + rc = alloc_chrdev_region(&devt, 0, CXL_MEM_MAX_DEVS, "cxl"); if (rc) return rc; diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h index af3ec078cf6c..dad7a831f65f 100644 --- a/drivers/cxl/pci.h +++ b/drivers/cxl/pci.h @@ -13,7 +13,7 @@ #define PCI_DVSEC_VENDOR_ID_CXL 0x1E98 #define PCI_DVSEC_ID_CXL 0x0 -#define PCI_DVSEC_ID_CXL_REGLOC_OFFSET 0x8 +#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8 #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC /* BAR Indicator Register (BIR) */ diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c new file mode 100644 index 000000000000..0088e41dd2f3 --- /dev/null +++ b/drivers/cxl/pmem.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2021 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include "mem.h" +#include "cxl.h" + +/* + * Ordered workqueue for cxl nvdimm device arrival and departure + * to coordinate bus rescans when a bridge arrives and trigger remove + * operations when the bridge is removed. + */ +static struct workqueue_struct *cxl_pmem_wq; + +static void unregister_nvdimm(void *nvdimm) +{ + nvdimm_delete(nvdimm); +} + +static int match_nvdimm_bridge(struct device *dev, const void *data) +{ + return strcmp(dev_name(dev), "nvdimm-bridge") == 0; +} + +static struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(void) +{ + struct device *dev; + + dev = bus_find_device(&cxl_bus_type, NULL, NULL, match_nvdimm_bridge); + if (!dev) + return NULL; + return to_cxl_nvdimm_bridge(dev); +} + +static int cxl_nvdimm_probe(struct device *dev) +{ + struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev); + struct cxl_nvdimm_bridge *cxl_nvb; + unsigned long flags = 0; + struct nvdimm *nvdimm; + int rc = -ENXIO; + + cxl_nvb = cxl_find_nvdimm_bridge(); + if (!cxl_nvb) + return -ENXIO; + + device_lock(&cxl_nvb->dev); + if (!cxl_nvb->nvdimm_bus) + goto out; + + set_bit(NDD_LABELING, &flags); + nvdimm = nvdimm_create(cxl_nvb->nvdimm_bus, cxl_nvd, NULL, flags, 0, 0, + NULL); + if (!nvdimm) + goto out; + + rc = devm_add_action_or_reset(dev, unregister_nvdimm, nvdimm); +out: + device_unlock(&cxl_nvb->dev); + put_device(&cxl_nvb->dev); + + return rc; +} + +static struct cxl_driver cxl_nvdimm_driver = { + .name = "cxl_nvdimm", + .probe = cxl_nvdimm_probe, + .id = CXL_DEVICE_NVDIMM, +}; + +static int cxl_pmem_ctl(struct nvdimm_bus_descriptor *nd_desc, + struct nvdimm *nvdimm, unsigned int cmd, void *buf, + unsigned int buf_len, int *cmd_rc) +{ + return -ENOTTY; +} + +static bool online_nvdimm_bus(struct cxl_nvdimm_bridge *cxl_nvb) +{ + if (cxl_nvb->nvdimm_bus) + return true; + cxl_nvb->nvdimm_bus = + nvdimm_bus_register(&cxl_nvb->dev, &cxl_nvb->nd_desc); + return cxl_nvb->nvdimm_bus != NULL; +} + +static int cxl_nvdimm_release_driver(struct device *dev, void *data) +{ + if (!is_cxl_nvdimm(dev)) + return 0; + device_release_driver(dev); + return 0; +} + +static void offline_nvdimm_bus(struct nvdimm_bus *nvdimm_bus) +{ + if (!nvdimm_bus) + return; + + /* + * Set the state of cxl_nvdimm devices to unbound / idle before + * nvdimm_bus_unregister() rips the nvdimm objects out from + * underneath them. + */ + bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_nvdimm_release_driver); + nvdimm_bus_unregister(nvdimm_bus); +} + +static void cxl_nvb_update_state(struct work_struct *work) +{ + struct cxl_nvdimm_bridge *cxl_nvb = + container_of(work, typeof(*cxl_nvb), state_work); + struct nvdimm_bus *victim_bus = NULL; + bool release = false, rescan = false; + + device_lock(&cxl_nvb->dev); + switch (cxl_nvb->state) { + case CXL_NVB_ONLINE: + if (!online_nvdimm_bus(cxl_nvb)) { + dev_err(&cxl_nvb->dev, + "failed to establish nvdimm bus\n"); + release = true; + } else + rescan = true; + break; + case CXL_NVB_OFFLINE: + case CXL_NVB_DEAD: + victim_bus = cxl_nvb->nvdimm_bus; + cxl_nvb->nvdimm_bus = NULL; + break; + default: + break; + } + device_unlock(&cxl_nvb->dev); + + if (release) + device_release_driver(&cxl_nvb->dev); + if (rescan) { + int rc = bus_rescan_devices(&cxl_bus_type); + + dev_dbg(&cxl_nvb->dev, "rescan: %d\n", rc); + } + offline_nvdimm_bus(victim_bus); + + put_device(&cxl_nvb->dev); +} + +static void cxl_nvdimm_bridge_remove(struct device *dev) +{ + struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev); + + if (cxl_nvb->state == CXL_NVB_ONLINE) + cxl_nvb->state = CXL_NVB_OFFLINE; + if (queue_work(cxl_pmem_wq, &cxl_nvb->state_work)) + get_device(&cxl_nvb->dev); +} + +static int cxl_nvdimm_bridge_probe(struct device *dev) +{ + struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev); + + if (cxl_nvb->state == CXL_NVB_DEAD) + return -ENXIO; + + if (cxl_nvb->state == CXL_NVB_NEW) { + cxl_nvb->nd_desc = (struct nvdimm_bus_descriptor) { + .provider_name = "CXL", + .module = THIS_MODULE, + .ndctl = cxl_pmem_ctl, + }; + + INIT_WORK(&cxl_nvb->state_work, cxl_nvb_update_state); + } + + cxl_nvb->state = CXL_NVB_ONLINE; + if (queue_work(cxl_pmem_wq, &cxl_nvb->state_work)) + get_device(&cxl_nvb->dev); + + return 0; +} + +static struct cxl_driver cxl_nvdimm_bridge_driver = { + .name = "cxl_nvdimm_bridge", + .probe = cxl_nvdimm_bridge_probe, + .remove = cxl_nvdimm_bridge_remove, + .id = CXL_DEVICE_NVDIMM_BRIDGE, +}; + +static __init int cxl_pmem_init(void) +{ + int rc; + + cxl_pmem_wq = alloc_ordered_workqueue("cxl_pmem", 0); + if (!cxl_pmem_wq) + return -ENXIO; + + rc = cxl_driver_register(&cxl_nvdimm_bridge_driver); + if (rc) + goto err_bridge; + + rc = cxl_driver_register(&cxl_nvdimm_driver); + if (rc) + goto err_nvdimm; + + return 0; + +err_nvdimm: + cxl_driver_unregister(&cxl_nvdimm_bridge_driver); +err_bridge: + destroy_workqueue(cxl_pmem_wq); + return rc; +} + +static __exit void cxl_pmem_exit(void) +{ + cxl_driver_unregister(&cxl_nvdimm_driver); + cxl_driver_unregister(&cxl_nvdimm_bridge_driver); + destroy_workqueue(cxl_pmem_wq); +} + +MODULE_LICENSE("GPL v2"); +module_init(cxl_pmem_init); +module_exit(cxl_pmem_exit); +MODULE_IMPORT_NS(CXL); +MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM_BRIDGE); +MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM); diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 7577874ca99b..e480f5b65ad5 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -234,7 +234,7 @@ retry: shared_count = fobj->shared_count; else shared_count = 0; - fence_excl = rcu_dereference(resv->fence_excl); + fence_excl = dma_resv_excl_fence(resv); if (read_seqcount_retry(&resv->seq, seq)) { rcu_read_unlock(); goto retry; @@ -1147,8 +1147,7 @@ static int __dma_buf_begin_cpu_access(struct dma_buf *dmabuf, long ret; /* Wait on any implicit rendering fences */ - ret = dma_resv_wait_timeout_rcu(resv, write, true, - MAX_SCHEDULE_TIMEOUT); + ret = dma_resv_wait_timeout(resv, write, true, MAX_SCHEDULE_TIMEOUT); if (ret < 0) return ret; @@ -1402,15 +1401,14 @@ EXPORT_SYMBOL_GPL(dma_buf_get_flags); #ifdef CONFIG_DEBUG_FS static int dma_buf_debug_show(struct seq_file *s, void *unused) { - int ret; struct dma_buf *buf_obj; struct dma_buf_attachment *attach_obj; struct dma_resv *robj; struct dma_resv_list *fobj; struct dma_fence *fence; - unsigned seq; int count = 0, attach_count, shared_count, i; size_t size = 0; + int ret; ret = mutex_lock_interruptible(&db_list.lock); @@ -1436,33 +1434,24 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) buf_obj->name ?: ""); robj = buf_obj->resv; - while (true) { - seq = read_seqcount_begin(&robj->seq); - rcu_read_lock(); - fobj = rcu_dereference(robj->fence); - shared_count = fobj ? fobj->shared_count : 0; - fence = rcu_dereference(robj->fence_excl); - if (!read_seqcount_retry(&robj->seq, seq)) - break; - rcu_read_unlock(); - } - + fence = dma_resv_excl_fence(robj); if (fence) seq_printf(s, "\tExclusive fence: %s %s %ssignalled\n", fence->ops->get_driver_name(fence), fence->ops->get_timeline_name(fence), dma_fence_is_signaled(fence) ? "" : "un"); + + fobj = rcu_dereference_protected(robj->fence, + dma_resv_held(robj)); + shared_count = fobj ? fobj->shared_count : 0; for (i = 0; i < shared_count; i++) { - fence = rcu_dereference(fobj->shared[i]); - if (!dma_fence_get_rcu(fence)) - continue; + fence = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(robj)); seq_printf(s, "\tShared fence: %s %s %ssignalled\n", fence->ops->get_driver_name(fence), fence->ops->get_timeline_name(fence), dma_fence_is_signaled(fence) ? "" : "un"); - dma_fence_put(fence); } - rcu_read_unlock(); seq_puts(s, "\tAttached Devices:\n"); attach_count = 0; diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 6ddbeb5dfbf6..f26c71747d43 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) * @@ -92,49 +93,6 @@ static void dma_resv_list_free(struct dma_resv_list *list) kfree_rcu(list, rcu); } -#if IS_ENABLED(CONFIG_LOCKDEP) -static int __init dma_resv_lockdep(void) -{ - struct mm_struct *mm = mm_alloc(); - struct ww_acquire_ctx ctx; - struct dma_resv obj; - struct address_space mapping; - int ret; - - if (!mm) - return -ENOMEM; - - dma_resv_init(&obj); - address_space_init_once(&mapping); - - mmap_read_lock(mm); - ww_acquire_init(&ctx, &reservation_ww_class); - ret = dma_resv_lock(&obj, &ctx); - if (ret == -EDEADLK) - dma_resv_lock_slow(&obj, &ctx); - fs_reclaim_acquire(GFP_KERNEL); - /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ - i_mmap_lock_write(&mapping); - i_mmap_unlock_write(&mapping); -#ifdef CONFIG_MMU_NOTIFIER - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); - __dma_fence_might_wait(); - lock_map_release(&__mmu_notifier_invalidate_range_start_map); -#else - __dma_fence_might_wait(); -#endif - fs_reclaim_release(GFP_KERNEL); - ww_mutex_unlock(&obj.lock); - ww_acquire_fini(&ctx); - mmap_read_unlock(mm); - - mmput(mm); - - return 0; -} -subsys_initcall(dma_resv_lockdep); -#endif - /** * dma_resv_init - initialize a reservation object * @obj: the reservation object @@ -191,14 +149,11 @@ int dma_resv_reserve_shared(struct dma_resv *obj, unsigned int num_fences) dma_resv_assert_held(obj); - old = dma_resv_get_list(obj); - + old = dma_resv_shared_list(obj); if (old && old->shared_max) { if ((old->shared_count + num_fences) <= old->shared_max) return 0; - else - max = max(old->shared_count + num_fences, - old->shared_max * 2); + max = max(old->shared_count + num_fences, old->shared_max * 2); } else { max = max(4ul, roundup_pow_of_two(num_fences)); } @@ -252,6 +207,28 @@ int dma_resv_reserve_shared(struct dma_resv *obj, unsigned int num_fences) } EXPORT_SYMBOL(dma_resv_reserve_shared); +#ifdef CONFIG_DEBUG_MUTEXES +/** + * dma_resv_reset_shared_max - reset shared fences for debugging + * @obj: the dma_resv object to reset + * + * Reset the number of pre-reserved shared slots to test that drivers do + * correct slot allocation using dma_resv_reserve_shared(). See also + * &dma_resv_list.shared_max. + */ +void dma_resv_reset_shared_max(struct dma_resv *obj) +{ + struct dma_resv_list *fences = dma_resv_shared_list(obj); + + dma_resv_assert_held(obj); + + /* Test shared fence slot reservation */ + if (fences) + fences->shared_max = fences->shared_count; +} +EXPORT_SYMBOL(dma_resv_reset_shared_max); +#endif + /** * dma_resv_add_shared_fence - Add a fence to a shared slot * @obj: the reservation object @@ -270,7 +247,7 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) dma_resv_assert_held(obj); - fobj = dma_resv_get_list(obj); + fobj = dma_resv_shared_list(obj); count = fobj->shared_count; write_seqcount_begin(&obj->seq); @@ -307,13 +284,13 @@ EXPORT_SYMBOL(dma_resv_add_shared_fence); */ void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) { - struct dma_fence *old_fence = dma_resv_get_excl(obj); + struct dma_fence *old_fence = dma_resv_excl_fence(obj); struct dma_resv_list *old; u32 i = 0; dma_resv_assert_held(obj); - old = dma_resv_get_list(obj); + old = dma_resv_shared_list(obj); if (old) i = old->shared_count; @@ -337,26 +314,26 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) EXPORT_SYMBOL(dma_resv_add_excl_fence); /** -* dma_resv_copy_fences - Copy all fences from src to dst. -* @dst: the destination reservation object -* @src: the source reservation object -* -* Copy all fences from src to dst. dst-lock must be held. -*/ + * dma_resv_copy_fences - Copy all fences from src to dst. + * @dst: the destination reservation object + * @src: the source reservation object + * + * Copy all fences from src to dst. dst-lock must be held. + */ int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) { struct dma_resv_list *src_list, *dst_list; struct dma_fence *old, *new; - unsigned i; + unsigned int i; dma_resv_assert_held(dst); rcu_read_lock(); - src_list = rcu_dereference(src->fence); + src_list = dma_resv_shared_list(src); retry: if (src_list) { - unsigned shared_count = src_list->shared_count; + unsigned int shared_count = src_list->shared_count; rcu_read_unlock(); @@ -365,7 +342,7 @@ retry: return -ENOMEM; rcu_read_lock(); - src_list = rcu_dereference(src->fence); + src_list = dma_resv_shared_list(src); if (!src_list || src_list->shared_count > shared_count) { kfree(dst_list); goto retry; @@ -373,6 +350,7 @@ retry: dst_list->shared_count = 0; for (i = 0; i < src_list->shared_count; ++i) { + struct dma_fence __rcu **dst; struct dma_fence *fence; fence = rcu_dereference(src_list->shared[i]); @@ -382,7 +360,7 @@ retry: if (!dma_fence_get_rcu(fence)) { dma_resv_list_free(dst_list); - src_list = rcu_dereference(src->fence); + src_list = dma_resv_shared_list(src); goto retry; } @@ -391,7 +369,8 @@ retry: continue; } - rcu_assign_pointer(dst_list->shared[dst_list->shared_count++], fence); + dst = &dst_list->shared[dst_list->shared_count++]; + rcu_assign_pointer(*dst, fence); } } else { dst_list = NULL; @@ -400,8 +379,8 @@ retry: new = dma_fence_get_rcu_safe(&src->fence_excl); rcu_read_unlock(); - src_list = dma_resv_get_list(dst); - old = dma_resv_get_excl(dst); + src_list = dma_resv_shared_list(dst); + old = dma_resv_excl_fence(dst); write_seqcount_begin(&dst->seq); /* write_seqcount_begin provides the necessary memory barrier */ @@ -417,7 +396,7 @@ retry: EXPORT_SYMBOL(dma_resv_copy_fences); /** - * dma_resv_get_fences_rcu - Get an object's shared and exclusive + * dma_resv_get_fences - Get an object's shared and exclusive * fences without update side lock held * @obj: the reservation object * @pfence_excl: the returned exclusive fence (or NULL) @@ -429,10 +408,9 @@ EXPORT_SYMBOL(dma_resv_copy_fences); * exclusive fence is not specified the fence is put into the array of the * shared fences as well. Returns either zero or -ENOMEM. */ -int dma_resv_get_fences_rcu(struct dma_resv *obj, - struct dma_fence **pfence_excl, - unsigned *pshared_count, - struct dma_fence ***pshared) +int dma_resv_get_fences(struct dma_resv *obj, struct dma_fence **pfence_excl, + unsigned int *pshared_count, + struct dma_fence ***pshared) { struct dma_fence **shared = NULL; struct dma_fence *fence_excl; @@ -449,11 +427,11 @@ int dma_resv_get_fences_rcu(struct dma_resv *obj, rcu_read_lock(); seq = read_seqcount_begin(&obj->seq); - fence_excl = rcu_dereference(obj->fence_excl); + fence_excl = dma_resv_excl_fence(obj); if (fence_excl && !dma_fence_get_rcu(fence_excl)) goto unlock; - fobj = rcu_dereference(obj->fence); + fobj = dma_resv_shared_list(obj); if (fobj) sz += sizeof(*shared) * fobj->shared_max; @@ -515,27 +493,28 @@ unlock: *pshared = shared; return ret; } -EXPORT_SYMBOL_GPL(dma_resv_get_fences_rcu); +EXPORT_SYMBOL_GPL(dma_resv_get_fences); /** - * dma_resv_wait_timeout_rcu - Wait on reservation's objects + * dma_resv_wait_timeout - Wait on reservation's objects * shared and/or exclusive fences. * @obj: the reservation object * @wait_all: if true, wait on all fences, else wait on just exclusive fence * @intr: if true, do interruptible wait * @timeout: timeout value in jiffies or zero to return immediately * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already * RETURNS * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or * greater than zer on success. */ -long dma_resv_wait_timeout_rcu(struct dma_resv *obj, - bool wait_all, bool intr, - unsigned long timeout) +long dma_resv_wait_timeout(struct dma_resv *obj, bool wait_all, bool intr, + unsigned long timeout) { - struct dma_fence *fence; - unsigned seq, shared_count; long ret = timeout ? timeout : 1; + unsigned int seq, shared_count; + struct dma_fence *fence; int i; retry: @@ -544,7 +523,7 @@ retry: rcu_read_lock(); i = -1; - fence = rcu_dereference(obj->fence_excl); + fence = dma_resv_excl_fence(obj); if (fence && !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { if (!dma_fence_get_rcu(fence)) goto unlock_retry; @@ -559,14 +538,15 @@ retry: } if (wait_all) { - struct dma_resv_list *fobj = rcu_dereference(obj->fence); + struct dma_resv_list *fobj = dma_resv_shared_list(obj); if (fobj) shared_count = fobj->shared_count; for (i = 0; !fence && i < shared_count; ++i) { - struct dma_fence *lfence = rcu_dereference(fobj->shared[i]); + struct dma_fence *lfence; + lfence = rcu_dereference(fobj->shared[i]); if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &lfence->flags)) continue; @@ -602,7 +582,7 @@ unlock_retry: rcu_read_unlock(); goto retry; } -EXPORT_SYMBOL_GPL(dma_resv_wait_timeout_rcu); +EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); static inline int dma_resv_test_signaled_single(struct dma_fence *passed_fence) @@ -622,18 +602,20 @@ static inline int dma_resv_test_signaled_single(struct dma_fence *passed_fence) } /** - * dma_resv_test_signaled_rcu - Test if a reservation object's - * fences have been signaled. + * dma_resv_test_signaled - Test if a reservation object's fences have been + * signaled. * @obj: the reservation object * @test_all: if true, test all fences, otherwise only test the exclusive * fence * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already * RETURNS * true if all fences signaled, else false */ -bool dma_resv_test_signaled_rcu(struct dma_resv *obj, bool test_all) +bool dma_resv_test_signaled(struct dma_resv *obj, bool test_all) { - unsigned seq, shared_count; + unsigned int seq, shared_count; int ret; rcu_read_lock(); @@ -643,16 +625,16 @@ retry: seq = read_seqcount_begin(&obj->seq); if (test_all) { - unsigned i; - - struct dma_resv_list *fobj = rcu_dereference(obj->fence); + struct dma_resv_list *fobj = dma_resv_shared_list(obj); + unsigned int i; if (fobj) shared_count = fobj->shared_count; for (i = 0; i < shared_count; ++i) { - struct dma_fence *fence = rcu_dereference(fobj->shared[i]); + struct dma_fence *fence; + fence = rcu_dereference(fobj->shared[i]); ret = dma_resv_test_signaled_single(fence); if (ret < 0) goto retry; @@ -665,7 +647,7 @@ retry: } if (!shared_count) { - struct dma_fence *fence_excl = rcu_dereference(obj->fence_excl); + struct dma_fence *fence_excl = dma_resv_excl_fence(obj); if (fence_excl) { ret = dma_resv_test_signaled_single(fence_excl); @@ -680,4 +662,47 @@ retry: rcu_read_unlock(); return ret; } -EXPORT_SYMBOL_GPL(dma_resv_test_signaled_rcu); +EXPORT_SYMBOL_GPL(dma_resv_test_signaled); + +#if IS_ENABLED(CONFIG_LOCKDEP) +static int __init dma_resv_lockdep(void) +{ + struct mm_struct *mm = mm_alloc(); + struct ww_acquire_ctx ctx; + struct dma_resv obj; + struct address_space mapping; + int ret; + + if (!mm) + return -ENOMEM; + + dma_resv_init(&obj); + address_space_init_once(&mapping); + + mmap_read_lock(mm); + ww_acquire_init(&ctx, &reservation_ww_class); + ret = dma_resv_lock(&obj, &ctx); + if (ret == -EDEADLK) + dma_resv_lock_slow(&obj, &ctx); + fs_reclaim_acquire(GFP_KERNEL); + /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ + i_mmap_lock_write(&mapping); + i_mmap_unlock_write(&mapping); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif + fs_reclaim_release(GFP_KERNEL); + ww_mutex_unlock(&obj.lock); + ww_acquire_fini(&ctx); + mmap_read_unlock(mm); + + mmput(mm); + + return 0; +} +subsys_initcall(dma_resv_lockdep); +#endif diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c index 9a841ce5f0c5..0fe0676f8e1d 100644 --- a/drivers/dma/altera-msgdma.c +++ b/drivers/dma/altera-msgdma.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "dmaengine.h" @@ -888,6 +889,13 @@ static int msgdma_probe(struct platform_device *pdev) if (ret) goto fail; + ret = of_dma_controller_register(pdev->dev.of_node, + of_dma_xlate_by_chan_id, dma_dev); + if (ret == -EINVAL) + dev_warn(&pdev->dev, "device was not probed from DT"); + else if (ret && ret != -ENODEV) + goto fail; + dev_notice(&pdev->dev, "Altera mSGDMA driver probe success\n"); return 0; @@ -908,6 +916,8 @@ static int msgdma_remove(struct platform_device *pdev) { struct msgdma_device *mdev = platform_get_drvdata(pdev); + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&mdev->dmadev); msgdma_dev_remove(mdev); @@ -916,9 +926,19 @@ static int msgdma_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_OF +static const struct of_device_id msgdma_match[] = { + { .compatible = "altr,socfpga-msgdma", }, + { } +}; + +MODULE_DEVICE_TABLE(of, msgdma_match); +#endif + static struct platform_driver msgdma_driver = { .driver = { .name = "altera-msgdma", + .of_match_table = of_match_ptr(msgdma_match), }, .probe = msgdma_probe, .remove = msgdma_remove, diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c index ed2ab46b15e7..045ead46ec8f 100644 --- a/drivers/dma/fsl-qdma.c +++ b/drivers/dma/fsl-qdma.c @@ -1235,7 +1235,11 @@ static int fsl_qdma_probe(struct platform_device *pdev) fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize; fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all; - dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + if (ret) { + dev_err(&pdev->dev, "dma_set_mask failure.\n"); + return ret; + } platform_set_drvdata(pdev, fsl_qdma); diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c index 025d8ad5a63c..92caae55aece 100644 --- a/drivers/dma/hsu/hsu.c +++ b/drivers/dma/hsu/hsu.c @@ -201,6 +201,7 @@ EXPORT_SYMBOL_GPL(hsu_dma_get_status); */ int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status) { + struct dma_chan_percpu *stat; struct hsu_dma_chan *hsuc; struct hsu_dma_desc *desc; unsigned long flags; @@ -210,6 +211,7 @@ int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status) return 0; hsuc = &chip->hsu->chan[nr]; + stat = this_cpu_ptr(hsuc->vchan.chan.local); spin_lock_irqsave(&hsuc->vchan.lock, flags); desc = hsuc->desc; @@ -221,6 +223,7 @@ int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status) } else { vchan_cookie_complete(&desc->vdesc); desc->status = DMA_COMPLETE; + stat->bytes_transferred += desc->length; hsu_dma_start_transfer(hsuc); } } diff --git a/drivers/dma/idxd/cdev.c b/drivers/dma/idxd/cdev.c index d4419bf1fede..e9def577c697 100644 --- a/drivers/dma/idxd/cdev.c +++ b/drivers/dma/idxd/cdev.c @@ -296,9 +296,7 @@ int idxd_wq_add_cdev(struct idxd_wq *wq) void idxd_wq_del_cdev(struct idxd_wq *wq) { struct idxd_cdev *idxd_cdev; - struct idxd_cdev_context *cdev_ctx; - cdev_ctx = &ictx[wq->idxd->data->type]; idxd_cdev = wq->idxd_cdev; wq->idxd_cdev = NULL; cdev_device_del(&idxd_cdev->cdev, &idxd_cdev->dev); diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c index 442d55c11a5f..c8ae41d36040 100644 --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c @@ -351,7 +351,8 @@ static int idxd_setup_internals(struct idxd_device *idxd) init_waitqueue_head(&idxd->cmd_waitq); if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) { - idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL); + idxd->int_handles = kcalloc_node(idxd->max_wqs, sizeof(int), GFP_KERNEL, + dev_to_node(dev)); if (!idxd->int_handles) return -ENOMEM; } diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index d5590c08db51..8070fd664bfc 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -35,7 +35,6 @@ #include #include -#include #include #include #include @@ -181,6 +180,61 @@ BIT(DMA_MEM_TO_DEV) | \ BIT(DMA_DEV_TO_DEV)) +/** + * struct sdma_script_start_addrs - SDMA script start pointers + * + * start addresses of the different functions in the physical + * address space of the SDMA engine. + */ +struct sdma_script_start_addrs { + s32 ap_2_ap_addr; + s32 ap_2_bp_addr; + s32 ap_2_ap_fixed_addr; + s32 bp_2_ap_addr; + s32 loopback_on_dsp_side_addr; + s32 mcu_interrupt_only_addr; + s32 firi_2_per_addr; + s32 firi_2_mcu_addr; + s32 per_2_firi_addr; + s32 mcu_2_firi_addr; + s32 uart_2_per_addr; + s32 uart_2_mcu_addr; + s32 per_2_app_addr; + s32 mcu_2_app_addr; + s32 per_2_per_addr; + s32 uartsh_2_per_addr; + s32 uartsh_2_mcu_addr; + s32 per_2_shp_addr; + s32 mcu_2_shp_addr; + s32 ata_2_mcu_addr; + s32 mcu_2_ata_addr; + s32 app_2_per_addr; + s32 app_2_mcu_addr; + s32 shp_2_per_addr; + s32 shp_2_mcu_addr; + s32 mshc_2_mcu_addr; + s32 mcu_2_mshc_addr; + s32 spdif_2_mcu_addr; + s32 mcu_2_spdif_addr; + s32 asrc_2_mcu_addr; + s32 ext_mem_2_ipu_addr; + s32 descrambler_addr; + s32 dptc_dvfs_addr; + s32 utra_addr; + s32 ram_code_start_addr; + /* End of v1 array */ + s32 mcu_2_ssish_addr; + s32 ssish_2_mcu_addr; + s32 hdmi_dma_addr; + /* End of v2 array */ + s32 zcanfd_2_mcu_addr; + s32 zqspi_2_mcu_addr; + s32 mcu_2_ecspi_addr; + /* End of v3 array */ + s32 mcu_2_zqspi_addr; + /* End of v4 array */ +}; + /* * Mode/Count of data node descriptors - IPCv2 */ @@ -1829,7 +1883,7 @@ static int sdma_get_firmware(struct sdma_engine *sdma, int ret; ret = request_firmware_nowait(THIS_MODULE, - FW_ACTION_HOTPLUG, fw_name, sdma->dev, + FW_ACTION_UEVENT, fw_name, sdma->dev, GFP_KERNEL, sdma, sdma_load_firmware); return ret; diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 43ac3ab23d4c..1a1b7d8458c9 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -2282,6 +2282,7 @@ static int gpi_probe(struct platform_device *pdev) static const struct of_device_id gpi_of_match[] = { { .compatible = "qcom,sdm845-gpi-dma" }, { .compatible = "qcom,sm8150-gpi-dma" }, + { .compatible = "qcom,sm8250-gpi-dma" }, { }, }; MODULE_DEVICE_TABLE(of, gpi_of_match); diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index c4c4e8575764..f12606aeff87 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -94,6 +94,7 @@ sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src, { struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); struct sf_pdma_desc *desc; + unsigned long iflags; if (chan && (!len || !dest || !src)) { dev_err(chan->pdma->dma_dev.dev, @@ -109,10 +110,10 @@ sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src, desc->dirn = DMA_MEM_TO_MEM; desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); - spin_lock_irqsave(&chan->vchan.lock, flags); + spin_lock_irqsave(&chan->vchan.lock, iflags); chan->desc = desc; sf_pdma_fill_desc(desc, dest, src, len); - spin_unlock_irqrestore(&chan->vchan.lock, flags); + spin_unlock_irqrestore(&chan->vchan.lock, iflags); return desc->async_tx; } diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile index 112fbd22bb3f..abdf10341725 100644 --- a/drivers/dma/sh/Makefile +++ b/drivers/dma/sh/Makefile @@ -3,7 +3,7 @@ # DMA Engine Helpers # -obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o +obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o # # DMA Controllers diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c deleted file mode 100644 index be89dd894328..000000000000 --- a/drivers/dma/sh/shdma-of.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SHDMA Device Tree glue - * - * Copyright (C) 2013 Renesas Electronics Inc. - * Author: Guennadi Liakhovetski - */ - -#include -#include -#include -#include -#include -#include -#include - -#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan) - -static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) -{ - u32 id = dma_spec->args[0]; - dma_cap_mask_t mask; - struct dma_chan *chan; - - if (dma_spec->args_count != 1) - return NULL; - - dma_cap_zero(mask); - /* Only slave DMA channels can be allocated via DT */ - dma_cap_set(DMA_SLAVE, mask); - - chan = dma_request_channel(mask, shdma_chan_filter, - (void *)(uintptr_t)id); - if (chan) - to_shdma_chan(chan)->hw_req = id; - - return chan; -} - -static int shdma_of_probe(struct platform_device *pdev) -{ - const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev); - int ret; - - ret = of_dma_controller_register(pdev->dev.of_node, - shdma_of_xlate, pdev); - if (ret < 0) - return ret; - - ret = of_platform_populate(pdev->dev.of_node, NULL, lookup, &pdev->dev); - if (ret < 0) - of_dma_controller_free(pdev->dev.of_node); - - return ret; -} - -static const struct of_device_id shdma_of_match[] = { - { .compatible = "renesas,shdma-mux", }, - { } -}; -MODULE_DEVICE_TABLE(of, sh_dmae_of_match); - -static struct platform_driver shdma_of = { - .driver = { - .name = "shdma-of", - .of_match_table = shdma_of_match, - }, - .probe = shdma_of_probe, -}; - -module_platform_driver(shdma_of); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("SH-DMA driver DT glue"); -MODULE_AUTHOR("Guennadi Liakhovetski "); diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index e8b6633ae661..93f1645ae928 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -1042,9 +1042,8 @@ handle_pending: * Move the promise into the completed list now that * we're done with it */ - list_del(&vchan->processing->list); - list_add_tail(&vchan->processing->list, - &contract->completed_demands); + list_move_tail(&vchan->processing->list, + &contract->completed_demands); /* * Cyclic DMA transfers are special: diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c index 268a08058714..7cb577e6587b 100644 --- a/drivers/dma/ti/omap-dma.c +++ b/drivers/dma/ti/omap-dma.c @@ -1608,7 +1608,8 @@ static int omap_dma_context_notifier(struct notifier_block *nb, return NOTIFY_BAD; omap_dma_context_save(od); break; - case CPU_CLUSTER_PM_ENTER_FAILED: + case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ + break; case CPU_CLUSTER_PM_EXIT: omap_dma_context_restore(od); break; diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c index 6c709803203a..b280a53e8570 100644 --- a/drivers/dma/xilinx/xilinx_dpdma.c +++ b/drivers/dma/xilinx/xilinx_dpdma.c @@ -531,7 +531,7 @@ static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev, for (i = 1; i < num_src_addr; i++) { u32 *addr = &hw_desc->src_addr2; - addr[i-1] = lower_32_bits(dma_addr[i]); + addr[i - 1] = lower_32_bits(dma_addr[i]); if (xdev->ext_addr) { u32 *addr_ext = &hw_desc->addr_ext_23; @@ -703,8 +703,9 @@ xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan, size_t stride = hsize + xt->sgl[0].icg; if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) { - dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n", - XILINX_DPDMA_ALIGN_BYTES); + dev_err(chan->xdev->dev, + "chan%u: buffer should be aligned at %d B\n", + chan->id, XILINX_DPDMA_ALIGN_BYTES); return NULL; } @@ -917,7 +918,7 @@ static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan) } /** - * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event + * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event * @chan: DPDMA channel * * Notify waiters for no outstanding event, so waiters can stop the channel @@ -936,7 +937,9 @@ static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan) cnt = xilinx_dpdma_chan_ostand(chan); if (cnt) { - dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt); + dev_dbg(chan->xdev->dev, + "chan%u: %d outstanding transactions\n", + chan->id, cnt); return -EWOULDBLOCK; } @@ -972,8 +975,8 @@ static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan) return 0; } - dev_err(chan->xdev->dev, "not ready to stop: %d trans\n", - xilinx_dpdma_chan_ostand(chan)); + dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", + chan->id, xilinx_dpdma_chan_ostand(chan)); if (ret == 0) return -ETIMEDOUT; @@ -1007,8 +1010,8 @@ static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan) return 0; } - dev_err(chan->xdev->dev, "not ready to stop: %d trans\n", - xilinx_dpdma_chan_ostand(chan)); + dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", + chan->id, xilinx_dpdma_chan_ostand(chan)); return -ETIMEDOUT; } @@ -1062,7 +1065,8 @@ static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan) vchan_cyclic_callback(&active->vdesc); else dev_warn(chan->xdev->dev, - "DONE IRQ with no active descriptor!\n"); + "chan%u: DONE IRQ with no active descriptor!\n", + chan->id); spin_unlock_irqrestore(&chan->lock, flags); } @@ -1094,8 +1098,12 @@ static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) /* If the retrigger raced with vsync, retry at the next frame. */ sw_desc = list_first_entry(&pending->descriptors, struct xilinx_dpdma_sw_desc, node); - if (sw_desc->hw.desc_id != desc_id) + if (sw_desc->hw.desc_id != desc_id) { + dev_dbg(chan->xdev->dev, + "chan%u: vsync race lost (%u != %u), retrying\n", + chan->id, sw_desc->hw.desc_id, desc_id); goto out; + } /* * Complete the active descriptor, if any, promote the pending @@ -1151,10 +1159,12 @@ static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) spin_lock_irqsave(&chan->lock, flags); - dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n", + dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n", + chan->id, dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE), dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR)); - dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n", + dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n", + chan->id, dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE), dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR)); @@ -1170,7 +1180,8 @@ static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) xilinx_dpdma_chan_dump_tx_desc(chan, active); if (active->error) - dev_dbg(xdev->dev, "repeated error on desc\n"); + dev_dbg(xdev->dev, "chan%u: repeated error on desc\n", + chan->id); /* Reschedule if there's no new descriptor */ if (!chan->desc.pending && @@ -1235,7 +1246,8 @@ static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan) align, 0); if (!chan->desc_pool) { dev_err(chan->xdev->dev, - "failed to allocate a descriptor pool\n"); + "chan%u: failed to allocate a descriptor pool\n", + chan->id); return -ENOMEM; } @@ -1588,7 +1600,7 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { struct xilinx_dpdma_device *xdev = ofdma->of_dma_data; - uint32_t chan_id = dma_spec->args[0]; + u32 chan_id = dma_spec->args[0]; if (chan_id >= ARRAY_SIZE(xdev->chan)) return NULL; diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 5f7fd79ec82f..61c21bd880a4 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/eisa/eisa-bus.c b/drivers/eisa/eisa-bus.c index d9a16ba2ccc2..65bffde137e3 100644 --- a/drivers/eisa/eisa-bus.c +++ b/drivers/eisa/eisa-bus.c @@ -155,34 +155,29 @@ void eisa_driver_unregister(struct eisa_driver *edrv) } EXPORT_SYMBOL(eisa_driver_unregister); -static ssize_t eisa_show_sig(struct device *dev, struct device_attribute *attr, - char *buf) +static ssize_t signature_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct eisa_device *edev = to_eisa_device(dev); return sprintf(buf, "%s\n", edev->id.sig); } +static DEVICE_ATTR_RO(signature); -static DEVICE_ATTR(signature, S_IRUGO, eisa_show_sig, NULL); - -static ssize_t eisa_show_state(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t enabled_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct eisa_device *edev = to_eisa_device(dev); return sprintf(buf, "%d\n", edev->state & EISA_CONFIG_ENABLED); } +static DEVICE_ATTR_RO(enabled); -static DEVICE_ATTR(enabled, S_IRUGO, eisa_show_state, NULL); - -static ssize_t eisa_show_modalias(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t modalias_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct eisa_device *edev = to_eisa_device(dev); return sprintf(buf, EISA_DEVICE_MODALIAS_FMT "\n", edev->id.sig); } - -static DEVICE_ATTR(modalias, S_IRUGO, eisa_show_modalias, NULL); +static DEVICE_ATTR_RO(modalias); static int __init eisa_init_device(struct eisa_root_device *root, struct eisa_device *edev, diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index e3db936becfd..c69d40ae5619 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -154,7 +154,7 @@ config EXTCON_RT8973A from abnormal high input voltage (up to 28V). config EXTCON_SM5502 - tristate "Silicon Mitus SM5502 EXTCON support" + tristate "Silicon Mitus SM5502/SM5504 EXTCON support" depends on I2C select IRQ_DOMAIN select REGMAP_I2C diff --git a/drivers/extcon/extcon-intel-mrfld.c b/drivers/extcon/extcon-intel-mrfld.c index f47016fb28a8..cd1a5f230077 100644 --- a/drivers/extcon/extcon-intel-mrfld.c +++ b/drivers/extcon/extcon-intel-mrfld.c @@ -197,6 +197,7 @@ static int mrfld_extcon_probe(struct platform_device *pdev) struct intel_soc_pmic *pmic = dev_get_drvdata(dev->parent); struct regmap *regmap = pmic->regmap; struct mrfld_extcon_data *data; + unsigned int status; unsigned int id; int irq, ret; @@ -244,6 +245,14 @@ static int mrfld_extcon_probe(struct platform_device *pdev) /* Get initial state */ mrfld_extcon_role_detect(data); + /* + * Cached status value is used for cable detection, see comments + * in mrfld_extcon_cable_detect(), we need to sync cached value + * with a real state of the hardware. + */ + regmap_read(regmap, BCOVE_SCHGRIRQ1, &status); + data->status = status; + mrfld_extcon_clear(data, BCOVE_MIRQLVL1, BCOVE_LVL1_CHGR); mrfld_extcon_clear(data, BCOVE_MCHGRIRQ1, BCOVE_CHGRIRQ_ALL); diff --git a/drivers/extcon/extcon-max8997.c b/drivers/extcon/extcon-max8997.c index bbc592823570..9cddf08e0696 100644 --- a/drivers/extcon/extcon-max8997.c +++ b/drivers/extcon/extcon-max8997.c @@ -773,3 +773,4 @@ module_platform_driver(max8997_muic_driver); MODULE_DESCRIPTION("Maxim MAX8997 Extcon driver"); MODULE_AUTHOR("Donggeun Kim "); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:max8997-muic"); diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c index db41d1c58efd..93da2d8379b1 100644 --- a/drivers/extcon/extcon-sm5502.c +++ b/drivers/extcon/extcon-sm5502.c @@ -40,17 +40,13 @@ struct sm5502_muic_info { struct i2c_client *i2c; struct regmap *regmap; + const struct sm5502_type *type; struct regmap_irq_chip_data *irq_data; - struct muic_irq *muic_irqs; - unsigned int num_muic_irqs; int irq; bool irq_attach; bool irq_detach; struct work_struct irq_work; - struct reg_data *reg_data; - unsigned int num_reg_data; - struct mutex mutex; /* @@ -62,6 +58,18 @@ struct sm5502_muic_info { struct delayed_work wq_detcable; }; +struct sm5502_type { + struct muic_irq *muic_irqs; + unsigned int num_muic_irqs; + const struct regmap_irq_chip *irq_chip; + + struct reg_data *reg_data; + unsigned int num_reg_data; + + unsigned int otg_dev_type1; + int (*parse_irq)(struct sm5502_muic_info *info, int irq_type); +}; + /* Default value of SM5502 register to bring up MUIC device. */ static struct reg_data sm5502_reg_data[] = { { @@ -88,7 +96,33 @@ static struct reg_data sm5502_reg_data[] = { | SM5502_REG_INTM2_MHL_MASK, .invert = true, }, - { } +}; + +/* Default value of SM5504 register to bring up MUIC device. */ +static struct reg_data sm5504_reg_data[] = { + { + .reg = SM5502_REG_RESET, + .val = SM5502_REG_RESET_MASK, + .invert = true, + }, { + .reg = SM5502_REG_INTMASK1, + .val = SM5504_REG_INTM1_ATTACH_MASK + | SM5504_REG_INTM1_DETACH_MASK, + .invert = false, + }, { + .reg = SM5502_REG_INTMASK2, + .val = SM5504_REG_INTM2_RID_CHG_MASK + | SM5504_REG_INTM2_UVLO_MASK + | SM5504_REG_INTM2_POR_MASK, + .invert = true, + }, { + .reg = SM5502_REG_CONTROL, + .val = SM5502_REG_CONTROL_MANUAL_SW_MASK + | SM5504_REG_CONTROL_CHGTYP_MASK + | SM5504_REG_CONTROL_USBCHDEN_MASK + | SM5504_REG_CONTROL_ADC_EN_MASK, + .invert = true, + }, }; /* List of detectable cables */ @@ -199,6 +233,55 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = { .num_irqs = ARRAY_SIZE(sm5502_irqs), }; +/* List of supported interrupt for SM5504 */ +static struct muic_irq sm5504_muic_irqs[] = { + { SM5504_IRQ_INT1_ATTACH, "muic-attach" }, + { SM5504_IRQ_INT1_DETACH, "muic-detach" }, + { SM5504_IRQ_INT1_CHG_DET, "muic-chg-det" }, + { SM5504_IRQ_INT1_DCD_OUT, "muic-dcd-out" }, + { SM5504_IRQ_INT1_OVP_EVENT, "muic-ovp-event" }, + { SM5504_IRQ_INT1_CONNECT, "muic-connect" }, + { SM5504_IRQ_INT1_ADC_CHG, "muic-adc-chg" }, + { SM5504_IRQ_INT2_RID_CHG, "muic-rid-chg" }, + { SM5504_IRQ_INT2_UVLO, "muic-uvlo" }, + { SM5504_IRQ_INT2_POR, "muic-por" }, + { SM5504_IRQ_INT2_OVP_FET, "muic-ovp-fet" }, + { SM5504_IRQ_INT2_OCP_LATCH, "muic-ocp-latch" }, + { SM5504_IRQ_INT2_OCP_EVENT, "muic-ocp-event" }, + { SM5504_IRQ_INT2_OVP_OCP_EVENT, "muic-ovp-ocp-event" }, +}; + +/* Define interrupt list of SM5504 to register regmap_irq */ +static const struct regmap_irq sm5504_irqs[] = { + /* INT1 interrupts */ + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_ATTACH_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_DETACH_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_CHG_DET_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_DCD_OUT_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_OVP_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_CONNECT_MASK, }, + { .reg_offset = 0, .mask = SM5504_IRQ_INT1_ADC_CHG_MASK, }, + + /* INT2 interrupts */ + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_RID_CHG_MASK,}, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_UVLO_MASK, }, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_POR_MASK, }, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_FET_MASK, }, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_LATCH_MASK, }, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_EVENT_MASK, }, + { .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK, }, +}; + +static const struct regmap_irq_chip sm5504_muic_irq_chip = { + .name = "sm5504", + .status_base = SM5502_REG_INT1, + .mask_base = SM5502_REG_INTMASK1, + .mask_invert = false, + .num_regs = 2, + .irqs = sm5504_irqs, + .num_irqs = ARRAY_SIZE(sm5504_irqs), +}; + /* Define regmap configuration of SM5502 for I2C communication */ static bool sm5502_muic_volatile_reg(struct device *dev, unsigned int reg) { @@ -302,11 +385,9 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info) return ret; } - switch (dev_type1) { - case SM5502_REG_DEV_TYPE1_USB_OTG_MASK: + if (dev_type1 == info->type->otg_dev_type1) { cable_type = SM5502_MUIC_ADC_GROUND_USB_OTG; - break; - default: + } else { dev_dbg(info->dev, "cannot identify the cable type: adc(0x%x), dev_type1(0x%x)\n", adc, dev_type1); @@ -359,6 +440,11 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info) return ret; } + if (dev_type1 == info->type->otg_dev_type1) { + cable_type = SM5502_MUIC_ADC_OPEN_USB_OTG; + break; + } + switch (dev_type1) { case SM5502_REG_DEV_TYPE1_USB_SDP_MASK: cable_type = SM5502_MUIC_ADC_OPEN_USB; @@ -366,9 +452,6 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info) case SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK: cable_type = SM5502_MUIC_ADC_OPEN_TA; break; - case SM5502_REG_DEV_TYPE1_USB_OTG_MASK: - cable_type = SM5502_MUIC_ADC_OPEN_USB_OTG; - break; default: dev_dbg(info->dev, "cannot identify the cable type: adc(0x%x)\n", @@ -498,16 +581,44 @@ static int sm5502_parse_irq(struct sm5502_muic_info *info, int irq_type) return 0; } +static int sm5504_parse_irq(struct sm5502_muic_info *info, int irq_type) +{ + switch (irq_type) { + case SM5504_IRQ_INT1_ATTACH: + info->irq_attach = true; + break; + case SM5504_IRQ_INT1_DETACH: + info->irq_detach = true; + break; + case SM5504_IRQ_INT1_CHG_DET: + case SM5504_IRQ_INT1_DCD_OUT: + case SM5504_IRQ_INT1_OVP_EVENT: + case SM5504_IRQ_INT1_CONNECT: + case SM5504_IRQ_INT1_ADC_CHG: + case SM5504_IRQ_INT2_RID_CHG: + case SM5504_IRQ_INT2_UVLO: + case SM5504_IRQ_INT2_POR: + case SM5504_IRQ_INT2_OVP_FET: + case SM5504_IRQ_INT2_OCP_LATCH: + case SM5504_IRQ_INT2_OCP_EVENT: + case SM5504_IRQ_INT2_OVP_OCP_EVENT: + default: + break; + } + + return 0; +} + static irqreturn_t sm5502_muic_irq_handler(int irq, void *data) { struct sm5502_muic_info *info = data; int i, irq_type = -1, ret; - for (i = 0; i < info->num_muic_irqs; i++) - if (irq == info->muic_irqs[i].virq) - irq_type = info->muic_irqs[i].irq; + for (i = 0; i < info->type->num_muic_irqs; i++) + if (irq == info->type->muic_irqs[i].virq) + irq_type = info->type->muic_irqs[i].irq; - ret = sm5502_parse_irq(info, irq_type); + ret = info->type->parse_irq(info, irq_type); if (ret < 0) { dev_warn(info->dev, "cannot handle is interrupt:%d\n", irq_type); @@ -552,19 +663,18 @@ static void sm5502_init_dev_type(struct sm5502_muic_info *info) version_id, vendor_id); /* Initiazle the register of SM5502 device to bring-up */ - for (i = 0; i < info->num_reg_data; i++) { + for (i = 0; i < info->type->num_reg_data; i++) { unsigned int val = 0; - if (!info->reg_data[i].invert) - val |= ~info->reg_data[i].val; + if (!info->type->reg_data[i].invert) + val |= ~info->type->reg_data[i].val; else - val = info->reg_data[i].val; - regmap_write(info->regmap, info->reg_data[i].reg, val); + val = info->type->reg_data[i].val; + regmap_write(info->regmap, info->type->reg_data[i].reg, val); } } -static int sm5022_muic_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) +static int sm5022_muic_i2c_probe(struct i2c_client *i2c) { struct device_node *np = i2c->dev.of_node; struct sm5502_muic_info *info; @@ -581,10 +691,13 @@ static int sm5022_muic_i2c_probe(struct i2c_client *i2c, info->dev = &i2c->dev; info->i2c = i2c; info->irq = i2c->irq; - info->muic_irqs = sm5502_muic_irqs; - info->num_muic_irqs = ARRAY_SIZE(sm5502_muic_irqs); - info->reg_data = sm5502_reg_data; - info->num_reg_data = ARRAY_SIZE(sm5502_reg_data); + info->type = device_get_match_data(info->dev); + if (!info->type) + return -EINVAL; + if (!info->type->parse_irq) { + dev_err(info->dev, "parse_irq missing in struct sm5502_type\n"); + return -EINVAL; + } mutex_init(&info->mutex); @@ -600,16 +713,17 @@ static int sm5022_muic_i2c_probe(struct i2c_client *i2c, /* Support irq domain for SM5502 MUIC device */ irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT | IRQF_SHARED; - ret = regmap_add_irq_chip(info->regmap, info->irq, irq_flags, 0, - &sm5502_muic_irq_chip, &info->irq_data); + ret = devm_regmap_add_irq_chip(info->dev, info->regmap, info->irq, + irq_flags, 0, info->type->irq_chip, + &info->irq_data); if (ret != 0) { dev_err(info->dev, "failed to request IRQ %d: %d\n", info->irq, ret); return ret; } - for (i = 0; i < info->num_muic_irqs; i++) { - struct muic_irq *muic_irq = &info->muic_irqs[i]; + for (i = 0; i < info->type->num_muic_irqs; i++) { + struct muic_irq *muic_irq = &info->type->muic_irqs[i]; int virq = 0; virq = regmap_irq_get_virq(info->irq_data, muic_irq->irq); @@ -661,17 +775,29 @@ static int sm5022_muic_i2c_probe(struct i2c_client *i2c, return 0; } -static int sm5502_muic_i2c_remove(struct i2c_client *i2c) -{ - struct sm5502_muic_info *info = i2c_get_clientdata(i2c); +static const struct sm5502_type sm5502_data = { + .muic_irqs = sm5502_muic_irqs, + .num_muic_irqs = ARRAY_SIZE(sm5502_muic_irqs), + .irq_chip = &sm5502_muic_irq_chip, + .reg_data = sm5502_reg_data, + .num_reg_data = ARRAY_SIZE(sm5502_reg_data), + .otg_dev_type1 = SM5502_REG_DEV_TYPE1_USB_OTG_MASK, + .parse_irq = sm5502_parse_irq, +}; - regmap_del_irq_chip(info->irq, info->irq_data); - - return 0; -} +static const struct sm5502_type sm5504_data = { + .muic_irqs = sm5504_muic_irqs, + .num_muic_irqs = ARRAY_SIZE(sm5504_muic_irqs), + .irq_chip = &sm5504_muic_irq_chip, + .reg_data = sm5504_reg_data, + .num_reg_data = ARRAY_SIZE(sm5504_reg_data), + .otg_dev_type1 = SM5504_REG_DEV_TYPE1_USB_OTG_MASK, + .parse_irq = sm5504_parse_irq, +}; static const struct of_device_id sm5502_dt_match[] = { - { .compatible = "siliconmitus,sm5502-muic" }, + { .compatible = "siliconmitus,sm5502-muic", .data = &sm5502_data }, + { .compatible = "siliconmitus,sm5504-muic", .data = &sm5504_data }, { }, }; MODULE_DEVICE_TABLE(of, sm5502_dt_match); @@ -702,7 +828,8 @@ static SIMPLE_DEV_PM_OPS(sm5502_muic_pm_ops, sm5502_muic_suspend, sm5502_muic_resume); static const struct i2c_device_id sm5502_i2c_id[] = { - { "sm5502", TYPE_SM5502 }, + { "sm5502", (kernel_ulong_t)&sm5502_data }, + { "sm5504", (kernel_ulong_t)&sm5504_data }, { } }; MODULE_DEVICE_TABLE(i2c, sm5502_i2c_id); @@ -713,8 +840,7 @@ static struct i2c_driver sm5502_muic_i2c_driver = { .pm = &sm5502_muic_pm_ops, .of_match_table = sm5502_dt_match, }, - .probe = sm5022_muic_i2c_probe, - .remove = sm5502_muic_i2c_remove, + .probe_new = sm5022_muic_i2c_probe, .id_table = sm5502_i2c_id, }; diff --git a/drivers/extcon/extcon-sm5502.h b/drivers/extcon/extcon-sm5502.h index ce1f1ec310c4..9c04315d48e2 100644 --- a/drivers/extcon/extcon-sm5502.h +++ b/drivers/extcon/extcon-sm5502.h @@ -8,10 +8,6 @@ #ifndef __LINUX_EXTCON_SM5502_H #define __LINUX_EXTCON_SM5502_H -enum sm5502_types { - TYPE_SM5502, -}; - /* SM5502 registers */ enum sm5502_reg { SM5502_REG_DEVICE_ID = 0x01, @@ -93,6 +89,13 @@ enum sm5502_reg { #define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT) #define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT) +#define SM5504_REG_CONTROL_CHGTYP_SHIFT 5 +#define SM5504_REG_CONTROL_USBCHDEN_SHIFT 6 +#define SM5504_REG_CONTROL_ADC_EN_SHIFT 7 +#define SM5504_REG_CONTROL_CHGTYP_MASK (0x1 << SM5504_REG_CONTROL_CHGTYP_SHIFT) +#define SM5504_REG_CONTROL_USBCHDEN_MASK (0x1 << SM5504_REG_CONTROL_USBCHDEN_SHIFT) +#define SM5504_REG_CONTROL_ADC_EN_MASK (0x1 << SM5504_REG_CONTROL_ADC_EN_SHIFT) + #define SM5502_REG_INTM1_ATTACH_SHIFT 0 #define SM5502_REG_INTM1_DETACH_SHIFT 1 #define SM5502_REG_INTM1_KP_SHIFT 2 @@ -123,6 +126,36 @@ enum sm5502_reg { #define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT) #define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT) +#define SM5504_REG_INTM1_ATTACH_SHIFT 0 +#define SM5504_REG_INTM1_DETACH_SHIFT 1 +#define SM5504_REG_INTM1_CHG_DET_SHIFT 2 +#define SM5504_REG_INTM1_DCD_OUT_SHIFT 3 +#define SM5504_REG_INTM1_OVP_EVENT_SHIFT 4 +#define SM5504_REG_INTM1_CONNECT_SHIFT 5 +#define SM5504_REG_INTM1_ADC_CHG_SHIFT 6 +#define SM5504_REG_INTM1_ATTACH_MASK (0x1 << SM5504_REG_INTM1_ATTACH_SHIFT) +#define SM5504_REG_INTM1_DETACH_MASK (0x1 << SM5504_REG_INTM1_DETACH_SHIFT) +#define SM5504_REG_INTM1_CHG_DET_MASK (0x1 << SM5504_REG_INTM1_CHG_DET_SHIFT) +#define SM5504_REG_INTM1_DCD_OUT_MASK (0x1 << SM5504_REG_INTM1_DCD_OUT_SHIFT) +#define SM5504_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5504_REG_INTM1_OVP_EVENT_SHIFT) +#define SM5504_REG_INTM1_CONNECT_MASK (0x1 << SM5504_REG_INTM1_CONNECT_SHIFT) +#define SM5504_REG_INTM1_ADC_CHG_MASK (0x1 << SM5504_REG_INTM1_ADC_CHG_SHIFT) + +#define SM5504_REG_INTM2_RID_CHG_SHIFT 0 +#define SM5504_REG_INTM2_UVLO_SHIFT 1 +#define SM5504_REG_INTM2_POR_SHIFT 2 +#define SM5504_REG_INTM2_OVP_FET_SHIFT 4 +#define SM5504_REG_INTM2_OCP_LATCH_SHIFT 5 +#define SM5504_REG_INTM2_OCP_EVENT_SHIFT 6 +#define SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT 7 +#define SM5504_REG_INTM2_RID_CHG_MASK (0x1 << SM5504_REG_INTM2_RID_CHG_SHIFT) +#define SM5504_REG_INTM2_UVLO_MASK (0x1 << SM5504_REG_INTM2_UVLO_SHIFT) +#define SM5504_REG_INTM2_POR_MASK (0x1 << SM5504_REG_INTM2_POR_SHIFT) +#define SM5504_REG_INTM2_OVP_FET_MASK (0x1 << SM5504_REG_INTM2_OVP_FET_SHIFT) +#define SM5504_REG_INTM2_OCP_LATCH_MASK (0x1 << SM5504_REG_INTM2_OCP_LATCH_SHIFT) +#define SM5504_REG_INTM2_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OCP_EVENT_SHIFT) +#define SM5504_REG_INTM2_OVP_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT) + #define SM5502_REG_ADC_SHIFT 0 #define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT) @@ -199,6 +232,9 @@ enum sm5502_reg { #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT) #define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT) +#define SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT 0 +#define SM5504_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT) + #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0 #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1 #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2 @@ -277,4 +313,42 @@ enum sm5502_irq { #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4) #define SM5502_IRQ_INT2_MHL_MASK BIT(5) +/* SM5504 Interrupts */ +enum sm5504_irq { + /* INT1 */ + SM5504_IRQ_INT1_ATTACH, + SM5504_IRQ_INT1_DETACH, + SM5504_IRQ_INT1_CHG_DET, + SM5504_IRQ_INT1_DCD_OUT, + SM5504_IRQ_INT1_OVP_EVENT, + SM5504_IRQ_INT1_CONNECT, + SM5504_IRQ_INT1_ADC_CHG, + + /* INT2 */ + SM5504_IRQ_INT2_RID_CHG, + SM5504_IRQ_INT2_UVLO, + SM5504_IRQ_INT2_POR, + SM5504_IRQ_INT2_OVP_FET, + SM5504_IRQ_INT2_OCP_LATCH, + SM5504_IRQ_INT2_OCP_EVENT, + SM5504_IRQ_INT2_OVP_OCP_EVENT, + + SM5504_IRQ_NUM, +}; + +#define SM5504_IRQ_INT1_ATTACH_MASK BIT(0) +#define SM5504_IRQ_INT1_DETACH_MASK BIT(1) +#define SM5504_IRQ_INT1_CHG_DET_MASK BIT(2) +#define SM5504_IRQ_INT1_DCD_OUT_MASK BIT(3) +#define SM5504_IRQ_INT1_OVP_MASK BIT(4) +#define SM5504_IRQ_INT1_CONNECT_MASK BIT(5) +#define SM5504_IRQ_INT1_ADC_CHG_MASK BIT(6) +#define SM5504_IRQ_INT2_RID_CHG_MASK BIT(0) +#define SM5504_IRQ_INT2_UVLO_MASK BIT(1) +#define SM5504_IRQ_INT2_POR_MASK BIT(2) +#define SM5504_IRQ_INT2_OVP_FET_MASK BIT(4) +#define SM5504_IRQ_INT2_OCP_LATCH_MASK BIT(5) +#define SM5504_IRQ_INT2_OCP_EVENT_MASK BIT(6) +#define SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK BIT(7) + #endif /* __LINUX_EXTCON_SM5502_H */ diff --git a/drivers/firewire/nosy.c b/drivers/firewire/nosy.c index 88ed971e32c0..b0d671db178a 100644 --- a/drivers/firewire/nosy.c +++ b/drivers/firewire/nosy.c @@ -511,12 +511,12 @@ remove_card(struct pci_dev *dev) wake_up_interruptible(&client->buffer.wait); spin_unlock_irq(&lynx->client_list_lock); - pci_free_consistent(lynx->pci_device, sizeof(struct pcl), - lynx->rcv_start_pcl, lynx->rcv_start_pcl_bus); - pci_free_consistent(lynx->pci_device, sizeof(struct pcl), - lynx->rcv_pcl, lynx->rcv_pcl_bus); - pci_free_consistent(lynx->pci_device, PAGE_SIZE, - lynx->rcv_buffer, lynx->rcv_buffer_bus); + dma_free_coherent(&lynx->pci_device->dev, sizeof(struct pcl), + lynx->rcv_start_pcl, lynx->rcv_start_pcl_bus); + dma_free_coherent(&lynx->pci_device->dev, sizeof(struct pcl), + lynx->rcv_pcl, lynx->rcv_pcl_bus); + dma_free_coherent(&lynx->pci_device->dev, PAGE_SIZE, lynx->rcv_buffer, + lynx->rcv_buffer_bus); iounmap(lynx->registers); pci_disable_device(dev); @@ -532,7 +532,7 @@ add_card(struct pci_dev *dev, const struct pci_device_id *unused) u32 p, end; int ret, i; - if (pci_set_dma_mask(dev, DMA_BIT_MASK(32))) { + if (dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) { dev_err(&dev->dev, "DMA address limits not supported for PCILynx hardware\n"); return -ENXIO; @@ -564,12 +564,16 @@ add_card(struct pci_dev *dev, const struct pci_device_id *unused) goto fail_deallocate_lynx; } - lynx->rcv_start_pcl = pci_alloc_consistent(lynx->pci_device, - sizeof(struct pcl), &lynx->rcv_start_pcl_bus); - lynx->rcv_pcl = pci_alloc_consistent(lynx->pci_device, - sizeof(struct pcl), &lynx->rcv_pcl_bus); - lynx->rcv_buffer = pci_alloc_consistent(lynx->pci_device, - RCV_BUFFER_SIZE, &lynx->rcv_buffer_bus); + lynx->rcv_start_pcl = dma_alloc_coherent(&lynx->pci_device->dev, + sizeof(struct pcl), + &lynx->rcv_start_pcl_bus, + GFP_KERNEL); + lynx->rcv_pcl = dma_alloc_coherent(&lynx->pci_device->dev, + sizeof(struct pcl), + &lynx->rcv_pcl_bus, GFP_KERNEL); + lynx->rcv_buffer = dma_alloc_coherent(&lynx->pci_device->dev, + RCV_BUFFER_SIZE, + &lynx->rcv_buffer_bus, GFP_KERNEL); if (lynx->rcv_start_pcl == NULL || lynx->rcv_pcl == NULL || lynx->rcv_buffer == NULL) { @@ -667,14 +671,15 @@ fail_free_irq: fail_deallocate_buffers: if (lynx->rcv_start_pcl) - pci_free_consistent(lynx->pci_device, sizeof(struct pcl), - lynx->rcv_start_pcl, lynx->rcv_start_pcl_bus); + dma_free_coherent(&lynx->pci_device->dev, sizeof(struct pcl), + lynx->rcv_start_pcl, + lynx->rcv_start_pcl_bus); if (lynx->rcv_pcl) - pci_free_consistent(lynx->pci_device, sizeof(struct pcl), - lynx->rcv_pcl, lynx->rcv_pcl_bus); + dma_free_coherent(&lynx->pci_device->dev, sizeof(struct pcl), + lynx->rcv_pcl, lynx->rcv_pcl_bus); if (lynx->rcv_buffer) - pci_free_consistent(lynx->pci_device, PAGE_SIZE, - lynx->rcv_buffer, lynx->rcv_buffer_bus); + dma_free_coherent(&lynx->pci_device->dev, PAGE_SIZE, + lynx->rcv_buffer, lynx->rcv_buffer_bus); iounmap(lynx->registers); fail_deallocate_lynx: diff --git a/drivers/firmware/google/gsmi.c b/drivers/firmware/google/gsmi.c index bb6e77ee3898..adaa492c3d2d 100644 --- a/drivers/firmware/google/gsmi.c +++ b/drivers/firmware/google/gsmi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 3aa489dba30a..2a7687911c09 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -1034,24 +1034,32 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) /* add svc client device(s) */ svc = devm_kzalloc(dev, sizeof(*svc), GFP_KERNEL); - if (!svc) - return -ENOMEM; + if (!svc) { + ret = -ENOMEM; + goto err_free_kfifo; + } svc->stratix10_svc_rsu = platform_device_alloc(STRATIX10_RSU, 0); if (!svc->stratix10_svc_rsu) { dev_err(dev, "failed to allocate %s device\n", STRATIX10_RSU); - return -ENOMEM; + ret = -ENOMEM; + goto err_free_kfifo; } ret = platform_device_add(svc->stratix10_svc_rsu); - if (ret) { - platform_device_put(svc->stratix10_svc_rsu); - return ret; - } + if (ret) + goto err_put_device; + dev_set_drvdata(dev, svc); pr_info("Intel Service Layer Driver Initialized\n"); + return 0; + +err_put_device: + platform_device_put(svc->stratix10_svc_rsu); +err_free_kfifo: + kfifo_free(&controller->svc_fifo); return ret; } diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 33e15058d0dc..8cd454ee20c0 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -7,7 +7,7 @@ menuconfig FPGA tristate "FPGA Configuration Framework" help Say Y here if you want support for configuring FPGAs from the - kernel. The FPGA framework adds a FPGA manager class and FPGA + kernel. The FPGA framework adds an FPGA manager class and FPGA manager drivers. if FPGA @@ -134,7 +134,7 @@ config FPGA_REGION tristate "FPGA Region" depends on FPGA_BRIDGE help - FPGA Region common code. A FPGA Region controls a FPGA Manager + FPGA Region common code. An FPGA Region controls an FPGA Manager and the FPGA Bridges associated with either a reconfigurable region of an FPGA or a whole FPGA. diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c index 5b130c4d9882..dfdf21ed34c4 100644 --- a/drivers/fpga/altera-pr-ip-core.c +++ b/drivers/fpga/altera-pr-ip-core.c @@ -199,16 +199,6 @@ int alt_pr_register(struct device *dev, void __iomem *reg_base) } EXPORT_SYMBOL_GPL(alt_pr_register); -void alt_pr_unregister(struct device *dev) -{ - struct fpga_manager *mgr = dev_get_drvdata(dev); - - dev_dbg(dev, "%s\n", __func__); - - fpga_mgr_unregister(mgr); -} -EXPORT_SYMBOL_GPL(alt_pr_unregister); - MODULE_AUTHOR("Matthew Gerlach "); MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index e9266b2a357f..2bfb2ff86930 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -85,14 +85,14 @@ err_dev: } /** - * of_fpga_bridge_get - get an exclusive reference to a fpga bridge + * of_fpga_bridge_get - get an exclusive reference to an fpga bridge * - * @np: node pointer of a FPGA bridge + * @np: node pointer of an FPGA bridge * @info: fpga image specific information * * Return fpga_bridge struct if successful. * Return -EBUSY if someone already has a reference to the bridge. - * Return -ENODEV if @np is not a FPGA Bridge. + * Return -ENODEV if @np is not an FPGA Bridge. */ struct fpga_bridge *of_fpga_bridge_get(struct device_node *np, struct fpga_image_info *info) @@ -113,11 +113,11 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data) } /** - * fpga_bridge_get - get an exclusive reference to a fpga bridge + * fpga_bridge_get - get an exclusive reference to an fpga bridge * @dev: parent device that fpga bridge was registered with * @info: fpga manager info * - * Given a device, get an exclusive reference to a fpga bridge. + * Given a device, get an exclusive reference to an fpga bridge. * * Return: fpga bridge struct or IS_ERR() condition containing error code. */ @@ -224,7 +224,7 @@ EXPORT_SYMBOL_GPL(fpga_bridges_put); /** * of_fpga_bridge_get_to_list - get a bridge, add it to a list * - * @np: node pointer of a FPGA bridge + * @np: node pointer of an FPGA bridge * @info: fpga image specific information * @bridge_list: list of FPGA bridges * @@ -313,7 +313,7 @@ ATTRIBUTE_GROUPS(fpga_bridge); /** * fpga_bridge_create - create and initialize a struct fpga_bridge - * @dev: FPGA bridge device from pdev + * @parent: FPGA bridge device from pdev * @name: FPGA bridge name * @br_ops: pointer to structure of fpga bridge ops * @priv: FPGA bridge private data @@ -323,7 +323,7 @@ ATTRIBUTE_GROUPS(fpga_bridge); * * Return: struct fpga_bridge or NULL */ -struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name, +struct fpga_bridge *fpga_bridge_create(struct device *parent, const char *name, const struct fpga_bridge_ops *br_ops, void *priv) { @@ -331,7 +331,7 @@ struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name, int id, ret; if (!name || !strlen(name)) { - dev_err(dev, "Attempt to register with no name!\n"); + dev_err(parent, "Attempt to register with no name!\n"); return NULL; } @@ -353,8 +353,8 @@ struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name, device_initialize(&bridge->dev); bridge->dev.groups = br_ops->groups; bridge->dev.class = fpga_bridge_class; - bridge->dev.parent = dev; - bridge->dev.of_node = dev->of_node; + bridge->dev.parent = parent; + bridge->dev.of_node = parent->of_node; bridge->dev.id = id; ret = dev_set_name(&bridge->dev, "br%d", id); @@ -373,7 +373,7 @@ error_kfree: EXPORT_SYMBOL_GPL(fpga_bridge_create); /** - * fpga_bridge_free - free a fpga bridge created by fpga_bridge_create() + * fpga_bridge_free - free an fpga bridge created by fpga_bridge_create() * @bridge: FPGA bridge struct */ void fpga_bridge_free(struct fpga_bridge *bridge) @@ -392,12 +392,12 @@ static void devm_fpga_bridge_release(struct device *dev, void *res) /** * devm_fpga_bridge_create - create and init a managed struct fpga_bridge - * @dev: FPGA bridge device from pdev + * @parent: FPGA bridge device from pdev * @name: FPGA bridge name * @br_ops: pointer to structure of fpga bridge ops * @priv: FPGA bridge private data * - * This function is intended for use in a FPGA bridge driver's probe function. + * This function is intended for use in an FPGA bridge driver's probe function. * After the bridge driver creates the struct with devm_fpga_bridge_create(), it * should register the bridge with fpga_bridge_register(). The bridge driver's * remove function should call fpga_bridge_unregister(). The bridge struct @@ -408,7 +408,7 @@ static void devm_fpga_bridge_release(struct device *dev, void *res) * Return: struct fpga_bridge or NULL */ struct fpga_bridge -*devm_fpga_bridge_create(struct device *dev, const char *name, +*devm_fpga_bridge_create(struct device *parent, const char *name, const struct fpga_bridge_ops *br_ops, void *priv) { struct fpga_bridge **ptr, *bridge; @@ -417,12 +417,12 @@ struct fpga_bridge if (!ptr) return NULL; - bridge = fpga_bridge_create(dev, name, br_ops, priv); + bridge = fpga_bridge_create(parent, name, br_ops, priv); if (!bridge) { devres_free(ptr); } else { *ptr = bridge; - devres_add(dev, ptr); + devres_add(parent, ptr); } return bridge; @@ -430,7 +430,7 @@ struct fpga_bridge EXPORT_SYMBOL_GPL(devm_fpga_bridge_create); /** - * fpga_bridge_register - register a FPGA bridge + * fpga_bridge_register - register an FPGA bridge * * @bridge: FPGA bridge struct * @@ -454,11 +454,11 @@ int fpga_bridge_register(struct fpga_bridge *bridge) EXPORT_SYMBOL_GPL(fpga_bridge_register); /** - * fpga_bridge_unregister - unregister a FPGA bridge + * fpga_bridge_unregister - unregister an FPGA bridge * * @bridge: FPGA bridge struct * - * This function is intended for use in a FPGA bridge driver's remove function. + * This function is intended for use in an FPGA bridge driver's remove function. */ void fpga_bridge_unregister(struct fpga_bridge *bridge) { diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index b85bc47c91a9..ecb4c3c795fa 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -26,7 +26,7 @@ struct fpga_mgr_devres { }; /** - * fpga_image_info_alloc - Allocate a FPGA image info struct + * fpga_image_info_alloc - Allocate an FPGA image info struct * @dev: owning device * * Return: struct fpga_image_info or NULL @@ -50,7 +50,7 @@ struct fpga_image_info *fpga_image_info_alloc(struct device *dev) EXPORT_SYMBOL_GPL(fpga_image_info_alloc); /** - * fpga_image_info_free - Free a FPGA image info struct + * fpga_image_info_free - Free an FPGA image info struct * @info: FPGA image info struct to free */ void fpga_image_info_free(struct fpga_image_info *info) @@ -470,7 +470,7 @@ static int fpga_mgr_dev_match(struct device *dev, const void *data) } /** - * fpga_mgr_get - Given a device, get a reference to a fpga mgr. + * fpga_mgr_get - Given a device, get a reference to an fpga mgr. * @dev: parent device that fpga mgr was registered with * * Return: fpga manager struct or IS_ERR() condition containing error code. @@ -487,7 +487,7 @@ struct fpga_manager *fpga_mgr_get(struct device *dev) EXPORT_SYMBOL_GPL(fpga_mgr_get); /** - * of_fpga_mgr_get - Given a device node, get a reference to a fpga mgr. + * of_fpga_mgr_get - Given a device node, get a reference to an fpga mgr. * * @node: device node * @@ -506,7 +506,7 @@ struct fpga_manager *of_fpga_mgr_get(struct device_node *node) EXPORT_SYMBOL_GPL(of_fpga_mgr_get); /** - * fpga_mgr_put - release a reference to a fpga manager + * fpga_mgr_put - release a reference to an fpga manager * @mgr: fpga manager structure */ void fpga_mgr_put(struct fpga_manager *mgr) @@ -550,8 +550,8 @@ void fpga_mgr_unlock(struct fpga_manager *mgr) EXPORT_SYMBOL_GPL(fpga_mgr_unlock); /** - * fpga_mgr_create - create and initialize a FPGA manager struct - * @dev: fpga manager device from pdev + * fpga_mgr_create - create and initialize an FPGA manager struct + * @parent: fpga manager device from pdev * @name: fpga manager name * @mops: pointer to structure of fpga manager ops * @priv: fpga manager private data @@ -561,7 +561,7 @@ EXPORT_SYMBOL_GPL(fpga_mgr_unlock); * * Return: pointer to struct fpga_manager or NULL */ -struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, +struct fpga_manager *fpga_mgr_create(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv) { @@ -571,12 +571,12 @@ struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, if (!mops || !mops->write_complete || !mops->state || !mops->write_init || (!mops->write && !mops->write_sg) || (mops->write && mops->write_sg)) { - dev_err(dev, "Attempt to register without fpga_manager_ops\n"); + dev_err(parent, "Attempt to register without fpga_manager_ops\n"); return NULL; } if (!name || !strlen(name)) { - dev_err(dev, "Attempt to register with no name!\n"); + dev_err(parent, "Attempt to register with no name!\n"); return NULL; } @@ -597,8 +597,8 @@ struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, device_initialize(&mgr->dev); mgr->dev.class = fpga_mgr_class; mgr->dev.groups = mops->groups; - mgr->dev.parent = dev; - mgr->dev.of_node = dev->of_node; + mgr->dev.parent = parent; + mgr->dev.of_node = parent->of_node; mgr->dev.id = id; ret = dev_set_name(&mgr->dev, "fpga%d", id); @@ -617,7 +617,7 @@ error_kfree: EXPORT_SYMBOL_GPL(fpga_mgr_create); /** - * fpga_mgr_free - free a FPGA manager created with fpga_mgr_create() + * fpga_mgr_free - free an FPGA manager created with fpga_mgr_create() * @mgr: fpga manager struct */ void fpga_mgr_free(struct fpga_manager *mgr) @@ -636,12 +636,12 @@ static void devm_fpga_mgr_release(struct device *dev, void *res) /** * devm_fpga_mgr_create - create and initialize a managed FPGA manager struct - * @dev: fpga manager device from pdev + * @parent: fpga manager device from pdev * @name: fpga manager name * @mops: pointer to structure of fpga manager ops * @priv: fpga manager private data * - * This function is intended for use in a FPGA manager driver's probe function. + * This function is intended for use in an FPGA manager driver's probe function. * After the manager driver creates the manager struct with * devm_fpga_mgr_create(), it should register it with fpga_mgr_register(). The * manager driver's remove function should call fpga_mgr_unregister(). The @@ -651,7 +651,7 @@ static void devm_fpga_mgr_release(struct device *dev, void *res) * * Return: pointer to struct fpga_manager or NULL */ -struct fpga_manager *devm_fpga_mgr_create(struct device *dev, const char *name, +struct fpga_manager *devm_fpga_mgr_create(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv) { @@ -661,20 +661,20 @@ struct fpga_manager *devm_fpga_mgr_create(struct device *dev, const char *name, if (!dr) return NULL; - dr->mgr = fpga_mgr_create(dev, name, mops, priv); + dr->mgr = fpga_mgr_create(parent, name, mops, priv); if (!dr->mgr) { devres_free(dr); return NULL; } - devres_add(dev, dr); + devres_add(parent, dr); return dr->mgr; } EXPORT_SYMBOL_GPL(devm_fpga_mgr_create); /** - * fpga_mgr_register - register a FPGA manager + * fpga_mgr_register - register an FPGA manager * @mgr: fpga manager struct * * Return: 0 on success, negative error code otherwise. @@ -706,10 +706,10 @@ error_device: EXPORT_SYMBOL_GPL(fpga_mgr_register); /** - * fpga_mgr_unregister - unregister a FPGA manager + * fpga_mgr_unregister - unregister an FPGA manager * @mgr: fpga manager struct * - * This function is intended for use in a FPGA manager driver's remove function. + * This function is intended for use in an FPGA manager driver's remove function. */ void fpga_mgr_unregister(struct fpga_manager *mgr) { diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index c3134b89c3fe..a4838715221f 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -33,14 +33,14 @@ struct fpga_region *fpga_region_class_find( EXPORT_SYMBOL_GPL(fpga_region_class_find); /** - * fpga_region_get - get an exclusive reference to a fpga region + * fpga_region_get - get an exclusive reference to an fpga region * @region: FPGA Region struct * * Caller should call fpga_region_put() when done with region. * * Return fpga_region struct if successful. * Return -EBUSY if someone already has a reference to the region. - * Return -ENODEV if @np is not a FPGA Region. + * Return -ENODEV if @np is not an FPGA Region. */ static struct fpga_region *fpga_region_get(struct fpga_region *region) { @@ -181,7 +181,7 @@ ATTRIBUTE_GROUPS(fpga_region); /** * fpga_region_create - alloc and init a struct fpga_region - * @dev: device parent + * @parent: device parent * @mgr: manager that programs this region * @get_bridges: optional function to get bridges to a list * @@ -192,7 +192,7 @@ ATTRIBUTE_GROUPS(fpga_region); * Return: struct fpga_region or NULL */ struct fpga_region -*fpga_region_create(struct device *dev, +*fpga_region_create(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region *)) { @@ -214,8 +214,8 @@ struct fpga_region device_initialize(®ion->dev); region->dev.class = fpga_region_class; - region->dev.parent = dev; - region->dev.of_node = dev->of_node; + region->dev.parent = parent; + region->dev.of_node = parent->of_node; region->dev.id = id; ret = dev_set_name(®ion->dev, "region%d", id); @@ -234,7 +234,7 @@ err_free: EXPORT_SYMBOL_GPL(fpga_region_create); /** - * fpga_region_free - free a FPGA region created by fpga_region_create() + * fpga_region_free - free an FPGA region created by fpga_region_create() * @region: FPGA region */ void fpga_region_free(struct fpga_region *region) @@ -253,11 +253,11 @@ static void devm_fpga_region_release(struct device *dev, void *res) /** * devm_fpga_region_create - create and initialize a managed FPGA region struct - * @dev: device parent + * @parent: device parent * @mgr: manager that programs this region * @get_bridges: optional function to get bridges to a list * - * This function is intended for use in a FPGA region driver's probe function. + * This function is intended for use in an FPGA region driver's probe function. * After the region driver creates the region struct with * devm_fpga_region_create(), it should register it with fpga_region_register(). * The region driver's remove function should call fpga_region_unregister(). @@ -268,7 +268,7 @@ static void devm_fpga_region_release(struct device *dev, void *res) * Return: struct fpga_region or NULL */ struct fpga_region -*devm_fpga_region_create(struct device *dev, +*devm_fpga_region_create(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region *)) { @@ -278,12 +278,12 @@ struct fpga_region if (!ptr) return NULL; - region = fpga_region_create(dev, mgr, get_bridges); + region = fpga_region_create(parent, mgr, get_bridges); if (!region) { devres_free(ptr); } else { *ptr = region; - devres_add(dev, ptr); + devres_add(parent, ptr); } return region; @@ -291,7 +291,7 @@ struct fpga_region EXPORT_SYMBOL_GPL(devm_fpga_region_create); /** - * fpga_region_register - register a FPGA region + * fpga_region_register - register an FPGA region * @region: FPGA region * * Return: 0 or -errno @@ -303,10 +303,10 @@ int fpga_region_register(struct fpga_region *region) EXPORT_SYMBOL_GPL(fpga_region_register); /** - * fpga_region_unregister - unregister a FPGA region + * fpga_region_unregister - unregister an FPGA region * @region: FPGA region * - * This function is intended for use in a FPGA region driver's remove function. + * This function is intended for use in an FPGA region driver's remove function. */ void fpga_region_unregister(struct fpga_region *region) { diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 114a64d2b7a4..1afb41aa20d7 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -374,11 +374,13 @@ static int machxo2_spi_probe(struct spi_device *spi) return devm_fpga_mgr_register(dev, mgr); } +#ifdef CONFIG_OF static const struct of_device_id of_match[] = { { .compatible = "lattice,machxo2-slave-spi", }, {} }; MODULE_DEVICE_TABLE(of, of_match); +#endif static const struct spi_device_id lattice_ids[] = { { "machxo2-slave-spi", 0 }, diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index e405309baadc..e3c25576b6b9 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -181,7 +181,7 @@ static int child_regions_with_firmware(struct device_node *overlay) * @region: FPGA region * @overlay: overlay applied to the FPGA region * - * Given an overlay applied to a FPGA region, parse the FPGA image specific + * Given an overlay applied to an FPGA region, parse the FPGA image specific * info in the overlay and do some checking. * * Returns: @@ -273,7 +273,7 @@ ret_no_info: * @region: FPGA region that the overlay was applied to * @nd: overlay notification data * - * Called when an overlay targeted to a FPGA Region is about to be applied. + * Called when an overlay targeted to an FPGA Region is about to be applied. * Parses the overlay for properties that influence how the FPGA will be * programmed and does some checking. If the checks pass, programs the FPGA. * If the checks fail, overlay is rejected and does not get added to the @@ -336,8 +336,8 @@ static void of_fpga_region_notify_post_remove(struct fpga_region *region, * @action: notifier action * @arg: reconfig data * - * This notifier handles programming a FPGA when a "firmware-name" property is - * added to a fpga-region. + * This notifier handles programming an FPGA when a "firmware-name" property is + * added to an fpga-region. * * Returns NOTIFY_OK or error if FPGA programming fails. */ diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 657a70c5fc99..a2cea500f7cc 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -271,7 +271,7 @@ static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count) } /* - * Send a FPGA image to privileged layers to write to the FPGA. When done + * Send an FPGA image to privileged layers to write to the FPGA. When done * sending, free all service layer buffers we allocated in write_init. */ static int s10_ops_write(struct fpga_manager *mgr, const char *buf, @@ -454,6 +454,7 @@ static int s10_remove(struct platform_device *pdev) struct s10_priv *priv = mgr->priv; fpga_mgr_unregister(mgr); + fpga_mgr_free(mgr); stratix10_svc_free_channel(priv->chan); return 0; diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 4e60e84cd17a..59ddc9fd5bca 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -724,7 +724,7 @@ static ssize_t cfam_read(struct file *filep, char __user *buf, size_t count, rc = count; fail: *offset = off; - return count; + return rc; } static ssize_t cfam_write(struct file *filep, const char __user *buf, @@ -761,7 +761,7 @@ static ssize_t cfam_write(struct file *filep, const char __user *buf, rc = count; fail: *offset = off; - return count; + return rc; } static loff_t cfam_llseek(struct file *file, loff_t offset, int whence) diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index 90dbe58ca1ed..8606e55c1721 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -92,7 +92,7 @@ static const u32 fsi_base = 0xa0000000; static u16 aspeed_fsi_divisor = FSI_DIVISOR_DEFAULT; module_param_named(bus_div,aspeed_fsi_divisor, ushort, 0); -#define OPB_POLL_TIMEOUT 10000 +#define OPB_POLL_TIMEOUT 500 static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, u32 val, u32 transfer_size) @@ -101,11 +101,15 @@ static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, u32 reg, status; int ret; - writel(CMD_WRITE, base + OPB0_RW); - writel(transfer_size, base + OPB0_XFER_SIZE); - writel(addr, base + OPB0_FSI_ADDR); - writel(val, base + OPB0_FSI_DATA_W); - writel(0x1, base + OPB_IRQ_CLEAR); + /* + * The ordering of these writes up until the trigger + * write does not matter, so use writel_relaxed. + */ + writel_relaxed(CMD_WRITE, base + OPB0_RW); + writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); + writel_relaxed(addr, base + OPB0_FSI_ADDR); + writel_relaxed(val, base + OPB0_FSI_DATA_W); + writel_relaxed(0x1, base + OPB_IRQ_CLEAR); writel(0x1, base + OPB_TRIGGER); ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, @@ -149,10 +153,14 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, u32 result, reg; int status, ret; - writel(CMD_READ, base + OPB0_RW); - writel(transfer_size, base + OPB0_XFER_SIZE); - writel(addr, base + OPB0_FSI_ADDR); - writel(0x1, base + OPB_IRQ_CLEAR); + /* + * The ordering of these writes up until the trigger + * write does not matter, so use writel_relaxed. + */ + writel_relaxed(CMD_READ, base + OPB0_RW); + writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); + writel_relaxed(addr, base + OPB0_FSI_ADDR); + writel_relaxed(0x1, base + OPB_IRQ_CLEAR); writel(0x1, base + OPB_TRIGGER); ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, @@ -525,7 +533,6 @@ static int tacoma_cabled_fsi_fixup(struct device *dev) static int fsi_master_aspeed_probe(struct platform_device *pdev) { struct fsi_master_aspeed *aspeed; - struct resource *res; int rc, links, reg; __be32 raw; @@ -541,8 +548,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) aspeed->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - aspeed->base = devm_ioremap_resource(&pdev->dev, res); + aspeed->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(aspeed->base)) return PTR_ERR(aspeed->base); @@ -645,6 +651,7 @@ static const struct of_device_id fsi_master_aspeed_match[] = { { .compatible = "aspeed,ast2600-fsi-master" }, { }, }; +MODULE_DEVICE_TABLE(of, fsi_master_aspeed_match); static struct platform_driver fsi_master_aspeed_driver = { .driver = { diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c index 57a779a89b07..24292acdbaf8 100644 --- a/drivers/fsi/fsi-master-ast-cf.c +++ b/drivers/fsi/fsi-master-ast-cf.c @@ -1309,7 +1309,6 @@ static int fsi_master_acf_probe(struct platform_device *pdev) master->cf_mem = devm_ioremap_resource(&pdev->dev, &res); if (IS_ERR(master->cf_mem)) { rc = PTR_ERR(master->cf_mem); - dev_err(&pdev->dev, "Error %d mapping coldfire memory\n", rc); goto err_free; } dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr); @@ -1427,6 +1426,7 @@ static const struct of_device_id fsi_master_acf_match[] = { { .compatible = "aspeed,ast2500-cf-fsi-master" }, { }, }; +MODULE_DEVICE_TABLE(of, fsi_master_acf_match); static struct platform_driver fsi_master_acf = { .driver = { diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index aa97c4a250cb..7d5f29b4b595 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -882,6 +882,7 @@ static const struct of_device_id fsi_master_gpio_match[] = { { .compatible = "fsi-master-gpio" }, { }, }; +MODULE_DEVICE_TABLE(of, fsi_master_gpio_match); static struct platform_driver fsi_master_gpio_driver = { .driver = { diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c index 10ca2e290655..b223f0ef337b 100644 --- a/drivers/fsi/fsi-occ.c +++ b/drivers/fsi/fsi-occ.c @@ -223,7 +223,8 @@ static const struct file_operations occ_fops = { .release = occ_release, }; -static int occ_verify_checksum(struct occ_response *resp, u16 data_length) +static int occ_verify_checksum(struct occ *occ, struct occ_response *resp, + u16 data_length) { /* Fetch the two bytes after the data for the checksum. */ u16 checksum_resp = get_unaligned_be16(&resp->data[data_length]); @@ -238,8 +239,11 @@ static int occ_verify_checksum(struct occ_response *resp, u16 data_length) for (i = 0; i < data_length; ++i) checksum += resp->data[i]; - if (checksum != checksum_resp) + if (checksum != checksum_resp) { + dev_err(occ->dev, "Bad checksum: %04x!=%04x\n", checksum, + checksum_resp); return -EBADMSG; + } return 0; } @@ -495,6 +499,7 @@ int fsi_occ_submit(struct device *dev, const void *request, size_t req_len, goto done; if (resp->return_status == OCC_RESP_CMD_IN_PRG || + resp->return_status == OCC_RESP_CRIT_INIT || resp->seq_no != seq_no) { rc = -ETIMEDOUT; @@ -532,7 +537,7 @@ int fsi_occ_submit(struct device *dev, const void *request, size_t req_len, } *resp_len = resp_data_length + 7; - rc = occ_verify_checksum(resp, resp_data_length); + rc = occ_verify_checksum(occ, resp, resp_data_length); done: mutex_unlock(&occ->occ_lock); @@ -635,6 +640,7 @@ static const struct of_device_id occ_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, occ_match); static struct platform_driver occ_driver = { .driver = { diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c index bfd5e5da8020..84cb965bfed5 100644 --- a/drivers/fsi/fsi-sbefifo.c +++ b/drivers/fsi/fsi-sbefifo.c @@ -325,7 +325,8 @@ static int sbefifo_up_write(struct sbefifo *sbefifo, __be32 word) static int sbefifo_request_reset(struct sbefifo *sbefifo) { struct device *dev = &sbefifo->fsi_dev->dev; - u32 status, timeout; + unsigned long end_time; + u32 status; int rc; dev_dbg(dev, "Requesting FIFO reset\n"); @@ -341,7 +342,8 @@ static int sbefifo_request_reset(struct sbefifo *sbefifo) } /* Wait for it to complete */ - for (timeout = 0; timeout < SBEFIFO_RESET_TIMEOUT; timeout++) { + end_time = jiffies + msecs_to_jiffies(SBEFIFO_RESET_TIMEOUT); + while (!time_after(jiffies, end_time)) { rc = sbefifo_regr(sbefifo, SBEFIFO_UP | SBEFIFO_STS, &status); if (rc) { dev_err(dev, "Failed to read UP fifo status during reset" @@ -355,7 +357,7 @@ static int sbefifo_request_reset(struct sbefifo *sbefifo) return 0; } - msleep(1); + cond_resched(); } dev_err(dev, "FIFO reset timed out\n"); @@ -400,7 +402,7 @@ static int sbefifo_cleanup_hw(struct sbefifo *sbefifo) /* The FIFO already contains a reset request from the SBE ? */ if (down_status & SBEFIFO_STS_RESET_REQ) { dev_info(dev, "Cleanup: FIFO reset request set, resetting\n"); - rc = sbefifo_regw(sbefifo, SBEFIFO_UP, SBEFIFO_PERFORM_RESET); + rc = sbefifo_regw(sbefifo, SBEFIFO_DOWN, SBEFIFO_PERFORM_RESET); if (rc) { sbefifo->broken = true; dev_err(dev, "Cleanup: Reset reg write failed, rc=%d\n", rc); diff --git a/drivers/fsi/fsi-scom.c b/drivers/fsi/fsi-scom.c index b45bfab7b7f5..da1486bb6a14 100644 --- a/drivers/fsi/fsi-scom.c +++ b/drivers/fsi/fsi-scom.c @@ -38,9 +38,10 @@ #define SCOM_STATUS_PIB_RESP_MASK 0x00007000 #define SCOM_STATUS_PIB_RESP_SHIFT 12 -#define SCOM_STATUS_ANY_ERR (SCOM_STATUS_PROTECTION | \ - SCOM_STATUS_PARITY | \ - SCOM_STATUS_PIB_ABORT | \ +#define SCOM_STATUS_FSI2PIB_ERROR (SCOM_STATUS_PROTECTION | \ + SCOM_STATUS_PARITY | \ + SCOM_STATUS_PIB_ABORT) +#define SCOM_STATUS_ANY_ERR (SCOM_STATUS_FSI2PIB_ERROR | \ SCOM_STATUS_PIB_RESP_MASK) /* SCOM address encodings */ #define XSCOM_ADDR_IND_FLAG BIT_ULL(63) @@ -60,7 +61,6 @@ #define XSCOM_ADDR_FORM1_HI_SHIFT 20 /* Retries */ -#define SCOM_MAX_RETRIES 100 /* Retries on busy */ #define SCOM_MAX_IND_RETRIES 10 /* Retries indirect not ready */ struct scom_device { @@ -240,14 +240,15 @@ static int handle_fsi2pib_status(struct scom_device *scom, uint32_t status) { uint32_t dummy = -1; - if (status & SCOM_STATUS_PROTECTION) - return -EPERM; - if (status & SCOM_STATUS_PARITY) { + if (status & SCOM_STATUS_FSI2PIB_ERROR) fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, &dummy, sizeof(uint32_t)); + + if (status & SCOM_STATUS_PROTECTION) + return -EPERM; + if (status & SCOM_STATUS_PARITY) return -EIO; - } - /* Return -EBUSY on PIB abort to force a retry */ + if (status & SCOM_STATUS_PIB_ABORT) return -EBUSY; return 0; @@ -284,69 +285,39 @@ static int handle_pib_status(struct scom_device *scom, uint8_t status) static int put_scom(struct scom_device *scom, uint64_t value, uint64_t addr) { - uint32_t status, dummy = -1; - int rc, retries; + uint32_t status; + int rc; - for (retries = 0; retries < SCOM_MAX_RETRIES; retries++) { - rc = raw_put_scom(scom, value, addr, &status); - if (rc) { - /* Try resetting the bridge if FSI fails */ - if (rc != -ENODEV && retries == 0) { - fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, - &dummy, sizeof(uint32_t)); - rc = -EBUSY; - } else - return rc; - } else - rc = handle_fsi2pib_status(scom, status); - if (rc && rc != -EBUSY) - break; - if (rc == 0) { - rc = handle_pib_status(scom, - (status & SCOM_STATUS_PIB_RESP_MASK) - >> SCOM_STATUS_PIB_RESP_SHIFT); - if (rc && rc != -EBUSY) - break; - } - if (rc == 0) - break; - msleep(1); - } - return rc; + rc = raw_put_scom(scom, value, addr, &status); + if (rc == -ENODEV) + return rc; + + rc = handle_fsi2pib_status(scom, status); + if (rc) + return rc; + + return handle_pib_status(scom, + (status & SCOM_STATUS_PIB_RESP_MASK) + >> SCOM_STATUS_PIB_RESP_SHIFT); } static int get_scom(struct scom_device *scom, uint64_t *value, uint64_t addr) { - uint32_t status, dummy = -1; - int rc, retries; + uint32_t status; + int rc; - for (retries = 0; retries < SCOM_MAX_RETRIES; retries++) { - rc = raw_get_scom(scom, value, addr, &status); - if (rc) { - /* Try resetting the bridge if FSI fails */ - if (rc != -ENODEV && retries == 0) { - fsi_device_write(scom->fsi_dev, SCOM_FSI2PIB_RESET_REG, - &dummy, sizeof(uint32_t)); - rc = -EBUSY; - } else - return rc; - } else - rc = handle_fsi2pib_status(scom, status); - if (rc && rc != -EBUSY) - break; - if (rc == 0) { - rc = handle_pib_status(scom, - (status & SCOM_STATUS_PIB_RESP_MASK) - >> SCOM_STATUS_PIB_RESP_SHIFT); - if (rc && rc != -EBUSY) - break; - } - if (rc == 0) - break; - msleep(1); - } - return rc; + rc = raw_get_scom(scom, value, addr, &status); + if (rc == -ENODEV) + return rc; + + rc = handle_fsi2pib_status(scom, status); + if (rc) + return rc; + + return handle_pib_status(scom, + (status & SCOM_STATUS_PIB_RESP_MASK) + >> SCOM_STATUS_PIB_RESP_SHIFT); } static ssize_t scom_read(struct file *filep, char __user *buf, size_t len, diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 63b84ba161dc..fab571016adf 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -782,6 +782,18 @@ config GPIO_MSC313 Say Y here to support the main GPIO block on MStar/SigmaStar ARMv7 based SoCs. +config GPIO_IDT3243X + tristate "IDT 79RC3243X GPIO support" + depends on MIKROTIK_RB532 || COMPILE_TEST + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Select this option to enable GPIO driver for + IDT 79RC3243X based devices like Mikrotik RB532. + + To compile this driver as a module, choose M here: the module will + be called gpio-idt3243x. + endmenu menu "Port-mapped I/O GPIO drivers" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d7c81e1611a4..32a32659866a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_GPIO_HISI) += gpio-hisi.o obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o +obj-$(CONFIG_GPIO_IDT3243X) += gpio-idt3243x.o obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o diff --git a/drivers/gpio/gpio-104-idio-16.c b/drivers/gpio/gpio-104-idio-16.c index 50ad0280fd78..55b40299ebfa 100644 --- a/drivers/gpio/gpio-104-idio-16.c +++ b/drivers/gpio/gpio-104-idio-16.c @@ -44,11 +44,12 @@ struct idio_16_gpio { struct gpio_chip chip; raw_spinlock_t lock; unsigned long irq_mask; - unsigned base; - unsigned out_state; + unsigned int base; + unsigned int out_state; }; -static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +static int idio_16_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) { if (offset > 15) return GPIO_LINE_DIRECTION_IN; @@ -56,22 +57,23 @@ static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset) return GPIO_LINE_DIRECTION_OUT; } -static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int idio_16_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) { return 0; } static int idio_16_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) + unsigned int offset, int value) { chip->set(chip, offset, value); return 0; } -static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset) +static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); - const unsigned mask = BIT(offset-16); + const unsigned int mask = BIT(offset-16); if (offset < 16) return -EINVAL; @@ -96,10 +98,11 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *chip, return 0; } -static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); - const unsigned mask = BIT(offset); + const unsigned int mask = BIT(offset); unsigned long flags; if (offset > 15) @@ -180,7 +183,7 @@ static void idio_16_irq_unmask(struct irq_data *data) } } -static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type) +static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type) { /* The only valid irq types are none and both-edges */ if (flow_type != IRQ_TYPE_NONE && diff --git a/drivers/gpio/gpio-adp5520.c b/drivers/gpio/gpio-adp5520.c index 0386ede53f3a..c55e821c63b6 100644 --- a/drivers/gpio/gpio-adp5520.c +++ b/drivers/gpio/gpio-adp5520.c @@ -113,10 +113,8 @@ static int adp5520_gpio_probe(struct platform_device *pdev) if (pdata->gpio_en_mask & (1 << i)) dev->lut[gpios++] = 1 << i; - if (gpios < 1) { - ret = -EINVAL; - goto err; - } + if (gpios < 1) + return -EINVAL; gc = &dev->gpio_chip; gc->direction_input = adp5520_gpio_direction_input; @@ -148,18 +146,10 @@ static int adp5520_gpio_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "failed to write\n"); - goto err; + return ret; } - ret = devm_gpiochip_add_data(&pdev->dev, &dev->gpio_chip, dev); - if (ret) - goto err; - - platform_set_drvdata(pdev, dev); - return 0; - -err: - return ret; + return devm_gpiochip_add_data(&pdev->dev, &dev->gpio_chip, dev); } static struct platform_driver adp5520_gpio_driver = { diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c index b5917c48e4dc..6af51feda06f 100644 --- a/drivers/gpio/gpio-altera-a10sr.c +++ b/drivers/gpio/gpio-altera-a10sr.c @@ -78,7 +78,6 @@ static const struct gpio_chip altr_a10sr_gc = { static int altr_a10sr_gpio_probe(struct platform_device *pdev) { struct altr_a10sr_gpio *gpio; - int ret; struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent); gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); @@ -91,15 +90,7 @@ static int altr_a10sr_gpio_probe(struct platform_device *pdev) gpio->gp.parent = pdev->dev.parent; gpio->gp.of_node = pdev->dev.of_node; - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, gpio); - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); } static const struct of_device_id altr_a10sr_gpio_of_match[] = { diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index 678ddd375891..9b780dc5d390 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -234,7 +234,6 @@ static int ath79_gpio_probe(struct platform_device *pdev) ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) return -ENOMEM; - platform_set_drvdata(pdev, ctrl); if (np) { err = of_property_read_u32(np, "ngpios", &ath79_gpio_count); @@ -290,13 +289,7 @@ static int ath79_gpio_probe(struct platform_device *pdev) girq->handler = handle_simple_irq; } - err = devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); - if (err) { - dev_err(dev, - "cannot add AR71xx GPIO chip, error=%d", err); - return err; - } - return 0; + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); } static struct platform_driver ath79_gpio_driver = { diff --git a/drivers/gpio/gpio-bd9571mwv.c b/drivers/gpio/gpio-bd9571mwv.c index df6102b57734..9a4d55f703bb 100644 --- a/drivers/gpio/gpio-bd9571mwv.c +++ b/drivers/gpio/gpio-bd9571mwv.c @@ -97,25 +97,16 @@ static const struct gpio_chip template_chip = { static int bd9571mwv_gpio_probe(struct platform_device *pdev) { struct bd9571mwv_gpio *gpio; - int ret; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) return -ENOMEM; - platform_set_drvdata(pdev, gpio); - gpio->regmap = dev_get_regmap(pdev->dev.parent, NULL); gpio->chip = template_chip; gpio->chip.parent = pdev->dev.parent; - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); } static const struct platform_device_id bd9571mwv_gpio_id_table[] = { diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c index 9aa59afdcbbf..559188d80c2b 100644 --- a/drivers/gpio/gpio-da9052.c +++ b/drivers/gpio/gpio-da9052.c @@ -196,7 +196,6 @@ static int da9052_gpio_probe(struct platform_device *pdev) { struct da9052_gpio *gpio; struct da9052_pdata *pdata; - int ret; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -209,15 +208,7 @@ static int da9052_gpio_probe(struct platform_device *pdev) if (pdata && pdata->gpio_base) gpio->gp.base = pdata->gpio_base; - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, gpio); - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); } static struct platform_driver da9052_gpio_driver = { diff --git a/drivers/gpio/gpio-da9055.c b/drivers/gpio/gpio-da9055.c index 6ad0c37b862e..49446a030f10 100644 --- a/drivers/gpio/gpio-da9055.c +++ b/drivers/gpio/gpio-da9055.c @@ -133,7 +133,6 @@ static int da9055_gpio_probe(struct platform_device *pdev) { struct da9055_gpio *gpio; struct da9055_pdata *pdata; - int ret; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -146,15 +145,7 @@ static int da9055_gpio_probe(struct platform_device *pdev) if (pdata && pdata->gpio_base) gpio->gp.base = pdata->gpio_base; - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, gpio); - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio); } static struct platform_driver da9055_gpio_driver = { diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c index d3233cc4b76b..3eb13d6d31ef 100644 --- a/drivers/gpio/gpio-dwapb.c +++ b/drivers/gpio/gpio-dwapb.c @@ -13,17 +13,15 @@ #include #include #include +#include #include #include -#include -#include -#include +#include #include #include #include -#include -#include #include +#include #include "gpiolib.h" #include "gpiolib-acpi.h" @@ -297,9 +295,6 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type) irq_hw_number_t bit = irqd_to_hwirq(d); unsigned long level, polarity, flags; - if (type & ~IRQ_TYPE_SENSE_MASK) - return -EINVAL; - spin_lock_irqsave(&gc->bgpio_lock, flags); level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); polarity = dwapb_read(gpio, GPIO_INT_POLARITY); @@ -531,17 +526,13 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, struct dwapb_port_property *pp) { - struct device_node *np = NULL; - int irq = -ENXIO, j; - - if (fwnode_property_read_bool(fwnode, "interrupt-controller")) - np = to_of_node(fwnode); + int irq, j; for (j = 0; j < pp->ngpio; j++) { - if (np) - irq = of_irq_get(np, j); - else if (has_acpi_companion(dev)) + if (has_acpi_companion(dev)) irq = platform_get_irq_optional(to_platform_device(dev), j); + else + irq = fwnode_irq_get(fwnode, j); if (irq > 0) pp->irq[j] = irq; } diff --git a/drivers/gpio/gpio-idt3243x.c b/drivers/gpio/gpio-idt3243x.c new file mode 100644 index 000000000000..50003ad2e589 --- /dev/null +++ b/drivers/gpio/gpio-idt3243x.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Driver for IDT/Renesas 79RC3243x Interrupt Controller */ + +#include +#include +#include +#include +#include +#include +#include + +#define IDT_PIC_IRQ_PEND 0x00 +#define IDT_PIC_IRQ_MASK 0x08 + +#define IDT_GPIO_DIR 0x00 +#define IDT_GPIO_DATA 0x04 +#define IDT_GPIO_ILEVEL 0x08 +#define IDT_GPIO_ISTAT 0x0C + +struct idt_gpio_ctrl { + struct gpio_chip gc; + void __iomem *pic; + void __iomem *gpio; + u32 mask_cache; +}; + +static void idt_gpio_dispatch(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + struct irq_chip *host_chip = irq_desc_get_chip(desc); + unsigned int bit, virq; + unsigned long pending; + + chained_irq_enter(host_chip, desc); + + pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND); + pending &= ~ctrl->mask_cache; + for_each_set_bit(bit, &pending, gc->ngpio) { + virq = irq_linear_revmap(gc->irq.domain, bit); + if (virq) + generic_handle_irq(virq); + } + + chained_irq_exit(host_chip, desc); +} + +static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK; + unsigned long flags; + u32 ilevel; + + /* hardware only supports level triggered */ + if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH)) + return -EINVAL; + + spin_lock_irqsave(&gc->bgpio_lock, flags); + + ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL); + if (sense & IRQ_TYPE_LEVEL_HIGH) + ilevel |= BIT(d->hwirq); + else if (sense & IRQ_TYPE_LEVEL_LOW) + ilevel &= ~BIT(d->hwirq); + + writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL); + irq_set_handler_locked(d, handle_level_irq); + + spin_unlock_irqrestore(&gc->bgpio_lock, flags); + return 0; +} + +static void idt_gpio_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + + writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT); +} + +static void idt_gpio_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + unsigned long flags; + + spin_lock_irqsave(&gc->bgpio_lock, flags); + + ctrl->mask_cache |= BIT(d->hwirq); + writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); + + spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + +static void idt_gpio_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + unsigned long flags; + + spin_lock_irqsave(&gc->bgpio_lock, flags); + + ctrl->mask_cache &= ~BIT(d->hwirq); + writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); + + spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + +static int idt_gpio_irq_init_hw(struct gpio_chip *gc) +{ + struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); + + /* Mask interrupts. */ + ctrl->mask_cache = 0xffffffff; + writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); + + return 0; +} + +static struct irq_chip idt_gpio_irqchip = { + .name = "IDTGPIO", + .irq_mask = idt_gpio_mask, + .irq_ack = idt_gpio_ack, + .irq_unmask = idt_gpio_unmask, + .irq_set_type = idt_gpio_irq_set_type +}; + +static int idt_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + struct idt_gpio_ctrl *ctrl; + unsigned int parent_irq; + int ngpios; + int ret; + + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->gpio = devm_platform_ioremap_resource_byname(pdev, "gpio"); + if (IS_ERR(ctrl->gpio)) + return PTR_ERR(ctrl->gpio); + + ctrl->gc.parent = dev; + + ret = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA, + NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0); + if (ret) { + dev_err(dev, "bgpio_init failed\n"); + return ret; + } + + ret = device_property_read_u32(dev, "ngpios", &ngpios); + if (!ret) + ctrl->gc.ngpio = ngpios; + + if (device_property_read_bool(dev, "interrupt-controller")) { + ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic"); + if (IS_ERR(ctrl->pic)) + return PTR_ERR(ctrl->pic); + + parent_irq = platform_get_irq(pdev, 0); + if (!parent_irq) + return -EINVAL; + + girq = &ctrl->gc.irq; + girq->chip = &idt_gpio_irqchip; + girq->init_hw = idt_gpio_irq_init_hw; + girq->parent_handler = idt_gpio_dispatch; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + girq->parents[0] = parent_irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + } + + return devm_gpiochip_add_data(&pdev->dev, &ctrl->gc, ctrl); +} + +static const struct of_device_id idt_gpio_of_match[] = { + { .compatible = "idt,32434-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, idt_gpio_of_match); + +static struct platform_driver idt_gpio_driver = { + .probe = idt_gpio_probe, + .driver = { + .name = "idt3243x-gpio", + .of_match_table = idt_gpio_of_match, + }, +}; +module_platform_driver(idt_gpio_driver); + +MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver"); +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/gpio-logicvc.c b/drivers/gpio/gpio-logicvc.c index 015632cf159f..992cc958a43f 100644 --- a/drivers/gpio/gpio-logicvc.c +++ b/drivers/gpio/gpio-logicvc.c @@ -114,10 +114,8 @@ static int logicvc_gpio_probe(struct platform_device *pdev) } base = devm_ioremap_resource(dev, &res); - if (IS_ERR(base)) { - dev_err(dev, "Failed to map I/O base\n"); + if (IS_ERR(base)) return PTR_ERR(base); - } logicvc_gpio_regmap_config.max_register = resource_size(&res) - logicvc_gpio_regmap_config.reg_stride; diff --git a/drivers/gpio/gpio-lp87565.c b/drivers/gpio/gpio-lp87565.c index e1244520cf7d..fcde6708b5df 100644 --- a/drivers/gpio/gpio-lp87565.c +++ b/drivers/gpio/gpio-lp87565.c @@ -123,14 +123,14 @@ static int lp87565_gpio_set_config(struct gpio_chip *gc, unsigned int offset, return regmap_update_bits(gpio->map, LP87565_REG_GPIO_CONFIG, BIT(offset + - __ffs(LP87565_GOIO1_OD)), + __ffs(LP87565_GPIO1_OD)), BIT(offset + - __ffs(LP87565_GOIO1_OD))); + __ffs(LP87565_GPIO1_OD))); case PIN_CONFIG_DRIVE_PUSH_PULL: return regmap_update_bits(gpio->map, LP87565_REG_GPIO_CONFIG, BIT(offset + - __ffs(LP87565_GOIO1_OD)), 0); + __ffs(LP87565_GPIO1_OD)), 0); default: return -ENOTSUPP; } diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c index d7e73876a3b9..0a9d746a0fe0 100644 --- a/drivers/gpio/gpio-mockup.c +++ b/drivers/gpio/gpio-mockup.c @@ -144,12 +144,9 @@ static void gpio_mockup_set_multiple(struct gpio_chip *gc, static int gpio_mockup_apply_pull(struct gpio_mockup_chip *chip, unsigned int offset, int value) { + struct gpio_chip *gc = &chip->gc; + struct gpio_desc *desc = gpiochip_get_desc(gc, offset); int curr, irq, irq_type, ret = 0; - struct gpio_desc *desc; - struct gpio_chip *gc; - - gc = &chip->gc; - desc = &gc->gpiodev->descs[offset]; mutex_lock(&chip->lock); @@ -369,7 +366,7 @@ static void gpio_mockup_debugfs_setup(struct device *dev, priv->chip = chip; priv->offset = i; - priv->desc = &gc->gpiodev->descs[i]; + priv->desc = gpiochip_get_desc(gc, i); debugfs_create_file(name, 0200, chip->dbg_dir, priv, &gpio_mockup_debugfs_ops); diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index 524b668eb1ac..31a336b86ff2 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -229,14 +229,14 @@ static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base) return rv; } -static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) { struct mxs_gpio_port *port = gpiochip_get_data(gc); return irq_find_mapping(port->domain, offset); } -static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset) +static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { struct mxs_gpio_port *port = gpiochip_get_data(gc); u32 mask = 1 << offset; diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index c91d05651596..f5cfc0698799 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -1241,6 +1241,7 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, + { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, { } diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 134cedf151a7..69c219742083 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -178,12 +178,6 @@ static int gpio_regmap_direction_output(struct gpio_chip *chip, return gpio_regmap_set_direction(chip, offset, true); } -void gpio_regmap_set_drvdata(struct gpio_regmap *gpio, void *data) -{ - gpio->driver_data = data; -} -EXPORT_SYMBOL_GPL(gpio_regmap_set_drvdata); - void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) { return gpio->driver_data; @@ -226,6 +220,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config return ERR_PTR(-ENOMEM); gpio->parent = config->parent; + gpio->driver_data = config->drvdata; gpio->regmap = config->regmap; gpio->ngpio_per_reg = config->ngpio_per_reg; gpio->reg_stride = config->reg_stride; @@ -311,9 +306,9 @@ void gpio_regmap_unregister(struct gpio_regmap *gpio) } EXPORT_SYMBOL_GPL(gpio_regmap_unregister); -static void devm_gpio_regmap_unregister(struct device *dev, void *res) +static void devm_gpio_regmap_unregister(void *res) { - gpio_regmap_unregister(*(struct gpio_regmap **)res); + gpio_regmap_unregister(res); } /** @@ -330,20 +325,17 @@ static void devm_gpio_regmap_unregister(struct device *dev, void *res) struct gpio_regmap *devm_gpio_regmap_register(struct device *dev, const struct gpio_regmap_config *config) { - struct gpio_regmap **ptr, *gpio; - - ptr = devres_alloc(devm_gpio_regmap_unregister, sizeof(*ptr), - GFP_KERNEL); - if (!ptr) - return ERR_PTR(-ENOMEM); + struct gpio_regmap *gpio; + int ret; gpio = gpio_regmap_register(config); - if (!IS_ERR(gpio)) { - *ptr = gpio; - devres_add(dev, ptr); - } else { - devres_free(ptr); - } + + if (IS_ERR(gpio)) + return gpio; + + ret = devm_add_action_or_reset(dev, devm_gpio_regmap_unregister, gpio); + if (ret) + return ERR_PTR(ret); return gpio; } diff --git a/drivers/gpio/gpio-spear-spics.c b/drivers/gpio/gpio-spear-spics.c index 6eca531b7d96..49aac2bb8d2c 100644 --- a/drivers/gpio/gpio-spear-spics.c +++ b/drivers/gpio/gpio-spear-spics.c @@ -122,7 +122,6 @@ static int spics_gpio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct spear_spics *spics; - int ret; spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL); if (!spics) @@ -148,8 +147,6 @@ static int spics_gpio_probe(struct platform_device *pdev) &spics->cs_enable_shift)) goto err_dt_data; - platform_set_drvdata(pdev, spics); - spics->chip.ngpio = NUM_OF_GPIO; spics->chip.base = -1; spics->chip.request = spics_request; @@ -163,14 +160,7 @@ static int spics_gpio_probe(struct platform_device *pdev) spics->chip.owner = THIS_MODULE; spics->last_off = -1; - ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics); - if (ret) { - dev_err(&pdev->dev, "unable to add gpio chip\n"); - return ret; - } - - dev_info(&pdev->dev, "spear spics registered\n"); - return 0; + return devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics); err_dt_data: dev_err(&pdev->dev, "DT probe failed\n"); diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c index 36ea8a3bd451..25c37edcbc6c 100644 --- a/drivers/gpio/gpio-sprd.c +++ b/drivers/gpio/gpio-sprd.c @@ -222,7 +222,6 @@ static int sprd_gpio_probe(struct platform_device *pdev) { struct gpio_irq_chip *irq; struct sprd_gpio *sprd_gpio; - int ret; sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL); if (!sprd_gpio) @@ -259,14 +258,7 @@ static int sprd_gpio_probe(struct platform_device *pdev) irq->num_parents = 1; irq->parents = &sprd_gpio->irq; - ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, sprd_gpio); - return 0; + return devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio); } static const struct of_device_id sprd_gpio_of_match[] = { diff --git a/drivers/gpio/gpio-sta2x11.c b/drivers/gpio/gpio-sta2x11.c index a74bb97a41e2..392fcab06ab8 100644 --- a/drivers/gpio/gpio-sta2x11.c +++ b/drivers/gpio/gpio-sta2x11.c @@ -398,15 +398,7 @@ static int gsta_probe(struct platform_device *dev) return err; } - err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip); - if (err < 0) { - dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n", - -err); - return err; - } - - platform_set_drvdata(dev, chip); - return 0; + return devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip); } static struct platform_driver sta2x11_gpio_platform_driver = { diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c index b94ef8181428..dd4d58b4ae49 100644 --- a/drivers/gpio/gpio-stmpe.c +++ b/drivers/gpio/gpio-stmpe.c @@ -449,6 +449,11 @@ static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, } } +static void stmpe_gpio_disable(void *stmpe) +{ + stmpe_disable(stmpe, STMPE_BLOCK_GPIO); +} + static int stmpe_gpio_probe(struct platform_device *pdev) { struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); @@ -461,7 +466,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev) return -EINVAL; } - stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL); + stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL); if (!stmpe_gpio) return -ENOMEM; @@ -489,7 +494,11 @@ static int stmpe_gpio_probe(struct platform_device *pdev) ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); if (ret) - goto out_free; + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe); + if (ret) + return ret; if (irq > 0) { struct gpio_irq_chip *girq; @@ -499,7 +508,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev) "stmpe-gpio", stmpe_gpio); if (ret) { dev_err(&pdev->dev, "unable to get irq: %d\n", ret); - goto out_disable; + return ret; } girq = &stmpe_gpio->chip.irq; @@ -514,22 +523,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev) girq->init_valid_mask = stmpe_init_irq_valid_mask; } - ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio); - if (ret) { - dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - goto out_disable; - } - - platform_set_drvdata(pdev, stmpe_gpio); - - return 0; - -out_disable: - stmpe_disable(stmpe, STMPE_BLOCK_GPIO); - gpiochip_remove(&stmpe_gpio->chip); -out_free: - kfree(stmpe_gpio); - return ret; + return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio); } static struct platform_driver stmpe_gpio_driver = { diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c index 55b8dbd13d11..8d158492488f 100644 --- a/drivers/gpio/gpio-tc3589x.c +++ b/drivers/gpio/gpio-tc3589x.c @@ -357,16 +357,7 @@ static int tc3589x_gpio_probe(struct platform_device *pdev) return ret; } - ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, - tc3589x_gpio); - if (ret) { - dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, tc3589x_gpio); - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio); } static struct platform_driver tc3589x_gpio_driver = { diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 05974b760796..d38980b9923a 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -730,18 +730,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev) offset += port->pins; } - platform_set_drvdata(pdev, gpio); - - err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); - if (err < 0) - return err; - - return 0; -} - -static int tegra186_gpio_remove(struct platform_device *pdev) -{ - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); } #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -913,7 +902,6 @@ static struct platform_driver tegra186_gpio_driver = { .of_match_table = tegra186_gpio_of_match, }, .probe = tegra186_gpio_probe, - .remove = tegra186_gpio_remove, }; module_platform_driver(tegra186_gpio_driver); diff --git a/drivers/gpio/gpio-tps65218.c b/drivers/gpio/gpio-tps65218.c index 43a1150055ce..3517debe2b0b 100644 --- a/drivers/gpio/gpio-tps65218.c +++ b/drivers/gpio/gpio-tps65218.c @@ -187,7 +187,6 @@ static int tps65218_gpio_probe(struct platform_device *pdev) { struct tps65218 *tps65218 = dev_get_drvdata(pdev->dev.parent); struct tps65218_gpio *tps65218_gpio; - int ret; tps65218_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps65218_gpio), GFP_KERNEL); @@ -201,16 +200,8 @@ static int tps65218_gpio_probe(struct platform_device *pdev) tps65218_gpio->gpio_chip.of_node = pdev->dev.of_node; #endif - ret = devm_gpiochip_add_data(&pdev->dev, &tps65218_gpio->gpio_chip, - tps65218_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, tps65218_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &tps65218_gpio->gpio_chip, + tps65218_gpio); } static const struct of_device_id tps65218_dt_match[] = { diff --git a/drivers/gpio/gpio-tps6586x.c b/drivers/gpio/gpio-tps6586x.c index 9b6cc74f47c8..da0304b764a5 100644 --- a/drivers/gpio/gpio-tps6586x.c +++ b/drivers/gpio/gpio-tps6586x.c @@ -76,7 +76,6 @@ static int tps6586x_gpio_probe(struct platform_device *pdev) { struct tps6586x_platform_data *pdata; struct tps6586x_gpio *tps6586x_gpio; - int ret; pdata = dev_get_platdata(pdev->dev.parent); tps6586x_gpio = devm_kzalloc(&pdev->dev, @@ -106,16 +105,8 @@ static int tps6586x_gpio_probe(struct platform_device *pdev) else tps6586x_gpio->gpio_chip.base = -1; - ret = devm_gpiochip_add_data(&pdev->dev, &tps6586x_gpio->gpio_chip, - tps6586x_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, tps6586x_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &tps6586x_gpio->gpio_chip, + tps6586x_gpio); } static struct platform_driver tps6586x_gpio_driver = { diff --git a/drivers/gpio/gpio-tps65910.c b/drivers/gpio/gpio-tps65910.c index 0c0b445c75c0..7fa8c841081f 100644 --- a/drivers/gpio/gpio-tps65910.c +++ b/drivers/gpio/gpio-tps65910.c @@ -165,16 +165,8 @@ static int tps65910_gpio_probe(struct platform_device *pdev) } skip_init: - ret = devm_gpiochip_add_data(&pdev->dev, &tps65910_gpio->gpio_chip, - tps65910_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, tps65910_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &tps65910_gpio->gpio_chip, + tps65910_gpio); } static struct platform_driver tps65910_gpio_driver = { diff --git a/drivers/gpio/gpio-tps65912.c b/drivers/gpio/gpio-tps65912.c index 510d9ed9fd2a..fab771cb6a87 100644 --- a/drivers/gpio/gpio-tps65912.c +++ b/drivers/gpio/gpio-tps65912.c @@ -99,7 +99,6 @@ static int tps65912_gpio_probe(struct platform_device *pdev) { struct tps65912 *tps = dev_get_drvdata(pdev->dev.parent); struct tps65912_gpio *gpio; - int ret; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -109,16 +108,7 @@ static int tps65912_gpio_probe(struct platform_device *pdev) gpio->gpio_chip = template_chip; gpio->gpio_chip.parent = tps->dev; - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, - gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, gpio); - - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, gpio); } static const struct platform_device_id tps65912_gpio_id_table[] = { diff --git a/drivers/gpio/gpio-tps68470.c b/drivers/gpio/gpio-tps68470.c index f7f5f770e0fb..423b7bc30ae8 100644 --- a/drivers/gpio/gpio-tps68470.c +++ b/drivers/gpio/gpio-tps68470.c @@ -125,7 +125,6 @@ static const char *tps68470_names[TPS68470_N_GPIO] = { static int tps68470_gpio_probe(struct platform_device *pdev) { struct tps68470_gpio_data *tps68470_gpio; - int ret; tps68470_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps68470_gpio), GFP_KERNEL); @@ -146,16 +145,7 @@ static int tps68470_gpio_probe(struct platform_device *pdev) tps68470_gpio->gc.base = -1; tps68470_gpio->gc.parent = &pdev->dev; - ret = devm_gpiochip_add_data(&pdev->dev, &tps68470_gpio->gc, - tps68470_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to register gpio_chip: %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, tps68470_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &tps68470_gpio->gc, tps68470_gpio); } static struct platform_driver tps68470_gpio_driver = { diff --git a/drivers/gpio/gpio-visconti.c b/drivers/gpio/gpio-visconti.c index 0e3d19828eb1..47455810bdb9 100644 --- a/drivers/gpio/gpio-visconti.c +++ b/drivers/gpio/gpio-visconti.c @@ -187,15 +187,7 @@ static int visconti_gpio_probe(struct platform_device *pdev) girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); - if (ret) { - dev_err(dev, "failed to add GPIO chip\n"); - return ret; - } - - platform_set_drvdata(pdev, priv); - - return ret; + return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); } static const struct of_device_id visconti_gpio_of_match[] = { diff --git a/drivers/gpio/gpio-wm831x.c b/drivers/gpio/gpio-wm831x.c index a3a32a77041f..9cf1e5ebb352 100644 --- a/drivers/gpio/gpio-wm831x.c +++ b/drivers/gpio/gpio-wm831x.c @@ -261,7 +261,6 @@ static int wm831x_gpio_probe(struct platform_device *pdev) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = &wm831x->pdata; struct wm831x_gpio *wm831x_gpio; - int ret; wm831x_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm831x_gpio), GFP_KERNEL); @@ -280,16 +279,7 @@ static int wm831x_gpio_probe(struct platform_device *pdev) wm831x_gpio->gpio_chip.of_node = wm831x->dev->of_node; #endif - ret = devm_gpiochip_add_data(&pdev->dev, &wm831x_gpio->gpio_chip, - wm831x_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, wm831x_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &wm831x_gpio->gpio_chip, wm831x_gpio); } static struct platform_driver wm831x_gpio_driver = { diff --git a/drivers/gpio/gpio-wm8350.c b/drivers/gpio/gpio-wm8350.c index 460f0a4b04bd..b1b131fb9804 100644 --- a/drivers/gpio/gpio-wm8350.c +++ b/drivers/gpio/gpio-wm8350.c @@ -105,7 +105,6 @@ static int wm8350_gpio_probe(struct platform_device *pdev) struct wm8350 *wm8350 = dev_get_drvdata(pdev->dev.parent); struct wm8350_platform_data *pdata = dev_get_platdata(wm8350->dev); struct wm8350_gpio_data *wm8350_gpio; - int ret; wm8350_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm8350_gpio), GFP_KERNEL); @@ -121,16 +120,7 @@ static int wm8350_gpio_probe(struct platform_device *pdev) else wm8350_gpio->gpio_chip.base = -1; - ret = devm_gpiochip_add_data(&pdev->dev, &wm8350_gpio->gpio_chip, - wm8350_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); - return ret; - } - - platform_set_drvdata(pdev, wm8350_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &wm8350_gpio->gpio_chip, wm8350_gpio); } static struct platform_driver wm8350_gpio_driver = { diff --git a/drivers/gpio/gpio-wm8994.c b/drivers/gpio/gpio-wm8994.c index 9af89cf7f6bc..f4a474cef32d 100644 --- a/drivers/gpio/gpio-wm8994.c +++ b/drivers/gpio/gpio-wm8994.c @@ -263,7 +263,6 @@ static int wm8994_gpio_probe(struct platform_device *pdev) struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent); struct wm8994_pdata *pdata = dev_get_platdata(wm8994->dev); struct wm8994_gpio *wm8994_gpio; - int ret; wm8994_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm8994_gpio), GFP_KERNEL); @@ -279,17 +278,7 @@ static int wm8994_gpio_probe(struct platform_device *pdev) else wm8994_gpio->gpio_chip.base = -1; - ret = devm_gpiochip_add_data(&pdev->dev, &wm8994_gpio->gpio_chip, - wm8994_gpio); - if (ret < 0) { - dev_err(&pdev->dev, "Could not register gpiochip, %d\n", - ret); - return ret; - } - - platform_set_drvdata(pdev, wm8994_gpio); - - return ret; + return devm_gpiochip_add_data(&pdev->dev, &wm8994_gpio->gpio_chip, wm8994_gpio); } static struct platform_driver wm8994_gpio_driver = { diff --git a/drivers/gpio/gpio-xgene.c b/drivers/gpio/gpio-xgene.c index 532b0df8a1f2..fb4b0c67aeef 100644 --- a/drivers/gpio/gpio-xgene.c +++ b/drivers/gpio/gpio-xgene.c @@ -159,7 +159,6 @@ static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume); static int xgene_gpio_probe(struct platform_device *pdev) { struct xgene_gpio *gpio; - int err = 0; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -183,15 +182,7 @@ static int xgene_gpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gpio); - err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); - if (err) { - dev_err(&pdev->dev, - "failed to register gpiochip.\n"); - return err; - } - - dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n"); - return 0; + return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); } static const struct of_device_id xgene_gpio_of_match[] = { diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 136557e7dd3c..c329c3a606e8 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -5,6 +5,7 @@ * Copyright 2008 - 2013 Xilinx, Inc. */ +#include #include #include #include @@ -23,7 +24,8 @@ #define XGPIO_DATA_OFFSET (0x0) /* Data register */ #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ -#define XGPIO_CHANNEL_OFFSET 0x8 +#define XGPIO_CHANNEL0_OFFSET 0x0 +#define XGPIO_CHANNEL1_OFFSET 0x8 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ #define XGPIO_GIER_IE BIT(31) @@ -43,56 +45,101 @@ * struct xgpio_instance - Stores information about GPIO device * @gc: GPIO chip * @regs: register block - * @gpio_width: GPIO width for every channel - * @gpio_state: GPIO write state shadow register - * @gpio_last_irq_read: GPIO read state register from last interrupt - * @gpio_dir: GPIO direction shadow register + * @hw_map: GPIO pin mapping on hardware side + * @sw_map: GPIO pin mapping on software side + * @state: GPIO write state shadow register + * @last_irq_read: GPIO read state register from last interrupt + * @dir: GPIO direction shadow register * @gpio_lock: Lock used for synchronization * @irq: IRQ used by GPIO device * @irqchip: IRQ chip - * @irq_enable: GPIO IRQ enable/disable bitfield - * @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield - * @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield + * @enable: GPIO IRQ enable/disable bitfield + * @rising_edge: GPIO IRQ rising edge enable/disable bitfield + * @falling_edge: GPIO IRQ falling edge enable/disable bitfield * @clk: clock resource for this driver */ struct xgpio_instance { struct gpio_chip gc; void __iomem *regs; - unsigned int gpio_width[2]; - u32 gpio_state[2]; - u32 gpio_last_irq_read[2]; - u32 gpio_dir[2]; + DECLARE_BITMAP(hw_map, 64); + DECLARE_BITMAP(sw_map, 64); + DECLARE_BITMAP(state, 64); + DECLARE_BITMAP(last_irq_read, 64); + DECLARE_BITMAP(dir, 64); spinlock_t gpio_lock; /* For serializing operations */ int irq; struct irq_chip irqchip; - u32 irq_enable[2]; - u32 irq_rising_edge[2]; - u32 irq_falling_edge[2]; + DECLARE_BITMAP(enable, 64); + DECLARE_BITMAP(rising_edge, 64); + DECLARE_BITMAP(falling_edge, 64); struct clk *clk; }; -static inline int xgpio_index(struct xgpio_instance *chip, int gpio) +static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) { - if (gpio >= chip->gpio_width[0]) - return 1; - - return 0; + return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); } -static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio) +static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) { - if (xgpio_index(chip, gpio)) - return XGPIO_CHANNEL_OFFSET; - - return 0; + return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); } -static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) +static inline u32 xgpio_get_value32(const unsigned long *map, int bit) { - if (xgpio_index(chip, gpio)) - return gpio - chip->gpio_width[0]; + const size_t index = BIT_WORD(bit); + const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); - return gpio; + return (map[index] >> offset) & 0xFFFFFFFFul; +} + +static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) +{ + const size_t index = BIT_WORD(bit); + const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); + + map[index] &= ~(0xFFFFFFFFul << offset); + map[index] |= v << offset; +} + +static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) +{ + switch (ch) { + case 0: + return XGPIO_CHANNEL0_OFFSET; + case 1: + return XGPIO_CHANNEL1_OFFSET; + default: + return -EINVAL; + } +} + +static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) +{ + void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); + xgpio_set_value32(a, bit, xgpio_readreg(addr)); +} + +static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) +{ + void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); + xgpio_writereg(addr, xgpio_get_value32(a, bit)); +} + +static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) +{ + int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); + + for (bit = 0; bit <= lastbit ; bit += 32) + xgpio_read_ch(chip, reg, bit, a); +} + +static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) +{ + int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); + + for (bit = 0; bit <= lastbit ; bit += 32) + xgpio_write_ch(chip, reg, bit, a); } /** @@ -109,12 +156,12 @@ static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { struct xgpio_instance *chip = gpiochip_get_data(gc); - u32 val; + int bit = xgpio_to_bit(chip, gpio); + DECLARE_BITMAP(state, 64); - val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio)); + xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); - return !!(val & BIT(xgpio_offset(chip, gpio))); + return test_bit(bit, state); } /** @@ -130,19 +177,14 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signal and set its direction to output */ - if (val) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); + __assign_bit(bit, chip->state, val); - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_state[index]); + xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -159,37 +201,22 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { + DECLARE_BITMAP(hw_mask, 64); + DECLARE_BITMAP(hw_bits, 64); + DECLARE_BITMAP(state, 64); unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; + + bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); + bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); spin_lock_irqsave(&chip->gpio_lock, flags); - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock, flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock, flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } - } + bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); + xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); + + bitmap_copy(chip->state, state, 64); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -207,15 +234,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ - chip->gpio_dir[index] |= BIT(offset); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); + __set_bit(bit, chip->dir); + xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -238,23 +263,17 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Write state of GPIO signal */ - if (val) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_state[index]); + __assign_bit(bit, chip->state, val); + xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); /* Clear the GPIO bit in shadow register and set direction as output */ - chip->gpio_dir[index] &= ~BIT(offset); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); + __clear_bit(bit, chip->dir); + xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -267,16 +286,8 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) */ static void xgpio_save_regs(struct xgpio_instance *chip) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); - - if (!chip->gpio_width[1]) - return; - - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, - chip->gpio_state[1]); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, - chip->gpio_dir[1]); + xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); + xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); } static int xgpio_request(struct gpio_chip *chip, unsigned int offset) @@ -302,8 +313,8 @@ static int __maybe_unused xgpio_suspend(struct device *dev) struct irq_data *data = irq_get_irq_data(gpio->irq); if (!data) { - dev_err(dev, "irq_get_irq_data() failed\n"); - return -EINVAL; + dev_dbg(dev, "IRQ not connected\n"); + return pm_runtime_force_suspend(dev); } if (!irqd_is_wakeup_set(data)) @@ -348,8 +359,8 @@ static int __maybe_unused xgpio_resume(struct device *dev) struct irq_data *data = irq_get_irq_data(gpio->irq); if (!data) { - dev_err(dev, "irq_get_irq_data() failed\n"); - return -EINVAL; + dev_dbg(dev, "IRQ not connected\n"); + return pm_runtime_force_resume(dev); } if (!irqd_is_wakeup_set(data)) @@ -391,18 +402,17 @@ static void xgpio_irq_mask(struct irq_data *irq_data) unsigned long flags; struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); + int bit = xgpio_to_bit(chip, irq_offset); + u32 mask = BIT(bit / 32), temp; spin_lock_irqsave(&chip->gpio_lock, flags); - chip->irq_enable[index] &= ~BIT(offset); + __clear_bit(bit, chip->enable); - if (!chip->irq_enable[index]) { + if (xgpio_get_value32(chip->enable, bit) == 0) { /* Disable per channel interrupt */ - u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); - - temp &= ~BIT(index); + temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); + temp &= ~mask; xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); } spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -417,30 +427,26 @@ static void xgpio_irq_unmask(struct irq_data *irq_data) unsigned long flags; struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); - u32 old_enable = chip->irq_enable[index]; + int bit = xgpio_to_bit(chip, irq_offset); + u32 old_enable = xgpio_get_value32(chip->enable, bit); + u32 mask = BIT(bit / 32), val; spin_lock_irqsave(&chip->gpio_lock, flags); - chip->irq_enable[index] |= BIT(offset); + __set_bit(bit, chip->enable); - if (!old_enable) { + if (old_enable == 0) { /* Clear any existing per-channel interrupts */ - u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & - BIT(index); - - if (val) - xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); + val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + val &= mask; + xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); /* Update GPIO IRQ read data before enabling interrupt*/ - val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET); - chip->gpio_last_irq_read[index] = val; + xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); /* Enable per channel interrupt */ val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); - val |= BIT(index); + val |= mask; xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); } @@ -459,8 +465,7 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) { struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); + int bit = xgpio_to_bit(chip, irq_offset); /* * The Xilinx GPIO hardware provides a single interrupt status @@ -470,16 +475,16 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) */ switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_BOTH: - chip->irq_rising_edge[index] |= BIT(offset); - chip->irq_falling_edge[index] |= BIT(offset); + __set_bit(bit, chip->rising_edge); + __set_bit(bit, chip->falling_edge); break; case IRQ_TYPE_EDGE_RISING: - chip->irq_rising_edge[index] |= BIT(offset); - chip->irq_falling_edge[index] &= ~BIT(offset); + __set_bit(bit, chip->rising_edge); + __clear_bit(bit, chip->falling_edge); break; case IRQ_TYPE_EDGE_FALLING: - chip->irq_rising_edge[index] &= ~BIT(offset); - chip->irq_falling_edge[index] |= BIT(offset); + __clear_bit(bit, chip->rising_edge); + __set_bit(bit, chip->falling_edge); break; default: return -EINVAL; @@ -496,46 +501,44 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) static void xgpio_irqhandler(struct irq_desc *desc) { struct xgpio_instance *chip = irq_desc_get_handler_data(desc); + struct gpio_chip *gc = &chip->gc; struct irq_chip *irqchip = irq_desc_get_chip(desc); - u32 num_channels = chip->gpio_width[1] ? 2 : 1; - u32 offset = 0, index; - u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + DECLARE_BITMAP(rising, 64); + DECLARE_BITMAP(falling, 64); + DECLARE_BITMAP(all, 64); + int irq_offset; + u32 status; + u32 bit; + status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); chained_irq_enter(irqchip, desc); - for (index = 0; index < num_channels; index++) { - if ((status & BIT(index))) { - unsigned long rising_events, falling_events, all_events; - unsigned long flags; - u32 data, bit; - unsigned int irq; - spin_lock_irqsave(&chip->gpio_lock, flags); - data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET); - rising_events = data & - ~chip->gpio_last_irq_read[index] & - chip->irq_enable[index] & - chip->irq_rising_edge[index]; - falling_events = ~data & - chip->gpio_last_irq_read[index] & - chip->irq_enable[index] & - chip->irq_falling_edge[index]; - dev_dbg(chip->gc.parent, - "IRQ chan %u rising 0x%lx falling 0x%lx\n", - index, rising_events, falling_events); - all_events = rising_events | falling_events; - chip->gpio_last_irq_read[index] = data; - spin_unlock_irqrestore(&chip->gpio_lock, flags); + spin_lock(&chip->gpio_lock); - for_each_set_bit(bit, &all_events, 32) { - irq = irq_find_mapping(chip->gc.irq.domain, - offset + bit); - generic_handle_irq(irq); - } - } - offset += chip->gpio_width[index]; + xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); + + bitmap_complement(rising, chip->last_irq_read, 64); + bitmap_and(rising, rising, all, 64); + bitmap_and(rising, rising, chip->enable, 64); + bitmap_and(rising, rising, chip->rising_edge, 64); + + bitmap_complement(falling, all, 64); + bitmap_and(falling, falling, chip->last_irq_read, 64); + bitmap_and(falling, falling, chip->enable, 64); + bitmap_and(falling, falling, chip->falling_edge, 64); + + bitmap_copy(chip->last_irq_read, all, 64); + bitmap_or(all, rising, falling, 64); + + spin_unlock(&chip->gpio_lock); + + dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); + + for_each_set_bit(bit, all, 64) { + irq_offset = xgpio_from_bit(chip, bit); + generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset)); } chained_irq_exit(irqchip, desc); @@ -556,6 +559,9 @@ static int xgpio_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; u32 is_dual = 0; u32 cells = 2; + u32 width[2]; + u32 state[2]; + u32 dir[2]; struct gpio_irq_chip *girq; u32 temp; @@ -565,13 +571,25 @@ static int xgpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, chip); + /* First, check if the device is dual-channel */ + of_property_read_u32(np, "xlnx,is-dual", &is_dual); + + /* Setup defaults */ + memset32(width, 0, ARRAY_SIZE(width)); + memset32(state, 0, ARRAY_SIZE(state)); + memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); + /* Update GPIO state shadow register with default value */ - if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0])) - chip->gpio_state[0] = 0x0; + of_property_read_u32(np, "xlnx,dout-default", &state[0]); + of_property_read_u32(np, "xlnx,dout-default-2", &state[1]); + + bitmap_from_arr32(chip->state, state, 64); /* Update GPIO direction shadow register with default value */ - if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) - chip->gpio_dir[0] = 0xFFFFFFFF; + of_property_read_u32(np, "xlnx,tri-default", &dir[0]); + of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]); + + bitmap_from_arr32(chip->dir, dir, 64); /* Update cells with gpio-cells value */ if (of_property_read_u32(np, "#gpio-cells", &cells)) @@ -586,42 +604,29 @@ static int xgpio_probe(struct platform_device *pdev) * Check device node and parent device node for device width * and assume default width of 32 */ - if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) - chip->gpio_width[0] = 32; + if (of_property_read_u32(np, "xlnx,gpio-width", &width[0])) + width[0] = 32; - if (chip->gpio_width[0] > 32) + if (width[0] > 32) return -EINVAL; + if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1])) + width[1] = 32; + + if (width[1] > 32) + return -EINVAL; + + /* Setup software pin mapping */ + bitmap_set(chip->sw_map, 0, width[0] + width[1]); + + /* Setup hardware pin mapping */ + bitmap_set(chip->hw_map, 0, width[0]); + bitmap_set(chip->hw_map, 32, width[1]); + spin_lock_init(&chip->gpio_lock); - if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) - is_dual = 0; - - if (is_dual) { - /* Update GPIO state shadow register with default value */ - if (of_property_read_u32(np, "xlnx,dout-default-2", - &chip->gpio_state[1])) - chip->gpio_state[1] = 0x0; - - /* Update GPIO direction shadow register with default value */ - if (of_property_read_u32(np, "xlnx,tri-default-2", - &chip->gpio_dir[1])) - chip->gpio_dir[1] = 0xFFFFFFFF; - - /* - * Check device node and parent device node for device width - * and assume default width of 32 - */ - if (of_property_read_u32(np, "xlnx,gpio2-width", - &chip->gpio_width[1])) - chip->gpio_width[1] = 32; - - if (chip->gpio_width[1] > 32) - return -EINVAL; - } - chip->gc.base = -1; - chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; + chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); chip->gc.parent = &pdev->dev; chip->gc.direction_input = xgpio_dir_in; chip->gc.direction_output = xgpio_dir_out; diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 3521c1dc3ac0..f0cb8ccd03ed 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -736,6 +736,11 @@ static int __maybe_unused zynq_gpio_suspend(struct device *dev) struct zynq_gpio *gpio = dev_get_drvdata(dev); struct irq_data *data = irq_get_irq_data(gpio->irq); + if (!data) { + dev_err(dev, "irq_get_irq_data() failed\n"); + return -EINVAL; + } + if (!device_may_wakeup(dev)) disable_irq(gpio->irq); @@ -753,6 +758,11 @@ static int __maybe_unused zynq_gpio_resume(struct device *dev) struct irq_data *data = irq_get_irq_data(gpio->irq); int ret; + if (!data) { + dev_err(dev, "irq_get_irq_data() failed\n"); + return -EINVAL; + } + if (!device_may_wakeup(dev)) enable_irq(gpio->irq); @@ -1001,8 +1011,11 @@ err_pm_dis: static int zynq_gpio_remove(struct platform_device *pdev) { struct zynq_gpio *gpio = platform_get_drvdata(pdev); + int ret; - pm_runtime_get_sync(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) + dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n"); gpiochip_remove(&gpio->chip); clk_disable_unprepare(gpio->clk); device_set_wakeup_capable(&pdev->dev, 0); @@ -1020,22 +1033,7 @@ static struct platform_driver zynq_gpio_driver = { .remove = zynq_gpio_remove, }; -/** - * zynq_gpio_init - Initial driver registration call - * - * Return: value from platform_driver_register - */ -static int __init zynq_gpio_init(void) -{ - return platform_driver_register(&zynq_gpio_driver); -} -postcore_initcall(zynq_gpio_init); - -static void __exit zynq_gpio_exit(void) -{ - platform_driver_unregister(&zynq_gpio_driver); -} -module_exit(zynq_gpio_exit); +module_platform_driver(zynq_gpio_driver); MODULE_AUTHOR("Xilinx Inc."); MODULE_DESCRIPTION("Zynq GPIO driver"); diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c index ae49bb23c6ed..4098bc7f88b7 100644 --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c @@ -66,9 +66,8 @@ static ssize_t direction_show(struct device *dev, mutex_lock(&data->mutex); gpiod_get_direction(desc); - status = sprintf(buf, "%s\n", - test_bit(FLAG_IS_OUT, &desc->flags) - ? "out" : "in"); + status = sysfs_emit(buf, "%s\n", + test_bit(FLAG_IS_OUT, &desc->flags) ? "out" : "in"); mutex_unlock(&data->mutex); @@ -109,13 +108,9 @@ static ssize_t value_show(struct device *dev, mutex_lock(&data->mutex); status = gpiod_get_value_cansleep(desc); - if (status < 0) - goto err; + if (status >= 0) + status = sysfs_emit(buf, "%zd\n", status); - buf[0] = '0' + status; - buf[1] = '\n'; - status = 2; -err: mutex_unlock(&data->mutex); return status; @@ -249,11 +244,11 @@ static ssize_t edge_show(struct device *dev, mutex_lock(&data->mutex); for (i = 0; i < ARRAY_SIZE(trigger_types); i++) { - if (data->irq_flags == trigger_types[i].flags) { - status = sprintf(buf, "%s\n", trigger_types[i].name); + if (data->irq_flags == trigger_types[i].flags) break; - } } + if (i < ARRAY_SIZE(trigger_types)) + status = sysfs_emit(buf, "%s\n", trigger_types[i].name); mutex_unlock(&data->mutex); @@ -312,10 +307,7 @@ static int gpio_sysfs_set_active_low(struct device *dev, int value) if (!!test_bit(FLAG_ACTIVE_LOW, &desc->flags) == !!value) return 0; - if (value) - set_bit(FLAG_ACTIVE_LOW, &desc->flags); - else - clear_bit(FLAG_ACTIVE_LOW, &desc->flags); + assign_bit(FLAG_ACTIVE_LOW, &desc->flags, value); /* reconfigure poll(2) support if enabled on one edge only */ if (flags == GPIO_IRQF_TRIGGER_FALLING || @@ -336,8 +328,8 @@ static ssize_t active_low_show(struct device *dev, mutex_lock(&data->mutex); - status = sprintf(buf, "%d\n", - !!test_bit(FLAG_ACTIVE_LOW, &desc->flags)); + status = sysfs_emit(buf, "%d\n", + !!test_bit(FLAG_ACTIVE_LOW, &desc->flags)); mutex_unlock(&data->mutex); @@ -415,7 +407,7 @@ static ssize_t base_show(struct device *dev, { const struct gpio_chip *chip = dev_get_drvdata(dev); - return sprintf(buf, "%d\n", chip->base); + return sysfs_emit(buf, "%d\n", chip->base); } static DEVICE_ATTR_RO(base); @@ -424,7 +416,7 @@ static ssize_t label_show(struct device *dev, { const struct gpio_chip *chip = dev_get_drvdata(dev); - return sprintf(buf, "%s\n", chip->label ? : ""); + return sysfs_emit(buf, "%s\n", chip->label ?: ""); } static DEVICE_ATTR_RO(label); @@ -433,7 +425,7 @@ static ssize_t ngpio_show(struct device *dev, { const struct gpio_chip *chip = dev_get_drvdata(dev); - return sprintf(buf, "%u\n", chip->ngpio); + return sysfs_emit(buf, "%u\n", chip->ngpio); } static DEVICE_ATTR_RO(ngpio); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 1427c1be749b..27c07108496d 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2004,9 +2004,6 @@ const char *gpiochip_is_requested(struct gpio_chip *gc, unsigned int offset) { struct gpio_desc *desc; - if (offset >= gc->ngpio) - return NULL; - desc = gpiochip_get_desc(gc, offset); if (IS_ERR(desc)) return NULL; @@ -2543,21 +2540,28 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep, while (i < array_size) { struct gpio_chip *gc = desc_array[i]->gdev->chip; - unsigned long fastpath[2 * BITS_TO_LONGS(FASTPATH_NGPIO)]; + DECLARE_BITMAP(fastpath_mask, FASTPATH_NGPIO); + DECLARE_BITMAP(fastpath_bits, FASTPATH_NGPIO); unsigned long *mask, *bits; int first, j; if (likely(gc->ngpio <= FASTPATH_NGPIO)) { - mask = fastpath; + mask = fastpath_mask; + bits = fastpath_bits; } else { - mask = kmalloc_array(2 * BITS_TO_LONGS(gc->ngpio), - sizeof(*mask), - can_sleep ? GFP_KERNEL : GFP_ATOMIC); + gfp_t flags = can_sleep ? GFP_KERNEL : GFP_ATOMIC; + + mask = bitmap_alloc(gc->ngpio, flags); if (!mask) return -ENOMEM; + + bits = bitmap_alloc(gc->ngpio, flags); + if (!bits) { + bitmap_free(mask); + return -ENOMEM; + } } - bits = mask + BITS_TO_LONGS(gc->ngpio); bitmap_zero(mask, gc->ngpio); if (!can_sleep) @@ -2580,8 +2584,10 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep, ret = gpio_chip_get_multiple(gc, mask, bits); if (ret) { - if (mask != fastpath) - kfree(mask); + if (mask != fastpath_mask) + bitmap_free(mask); + if (bits != fastpath_bits) + bitmap_free(bits); return ret; } @@ -2601,8 +2607,10 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep, j); } - if (mask != fastpath) - kfree(mask); + if (mask != fastpath_mask) + bitmap_free(mask); + if (bits != fastpath_bits) + bitmap_free(bits); } return 0; } @@ -2826,21 +2834,28 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep, while (i < array_size) { struct gpio_chip *gc = desc_array[i]->gdev->chip; - unsigned long fastpath[2 * BITS_TO_LONGS(FASTPATH_NGPIO)]; + DECLARE_BITMAP(fastpath_mask, FASTPATH_NGPIO); + DECLARE_BITMAP(fastpath_bits, FASTPATH_NGPIO); unsigned long *mask, *bits; int count = 0; if (likely(gc->ngpio <= FASTPATH_NGPIO)) { - mask = fastpath; + mask = fastpath_mask; + bits = fastpath_bits; } else { - mask = kmalloc_array(2 * BITS_TO_LONGS(gc->ngpio), - sizeof(*mask), - can_sleep ? GFP_KERNEL : GFP_ATOMIC); + gfp_t flags = can_sleep ? GFP_KERNEL : GFP_ATOMIC; + + mask = bitmap_alloc(gc->ngpio, flags); if (!mask) return -ENOMEM; + + bits = bitmap_alloc(gc->ngpio, flags); + if (!bits) { + bitmap_free(mask); + return -ENOMEM; + } } - bits = mask + BITS_TO_LONGS(gc->ngpio); bitmap_zero(mask, gc->ngpio); if (!can_sleep) @@ -2885,8 +2900,10 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep, if (count != 0) gpio_chip_set_multiple(gc, mask, bits); - if (mask != fastpath) - kfree(mask); + if (mask != fastpath_mask) + bitmap_free(mask); + if (bits != fastpath_bits) + bitmap_free(bits); } return 0; } diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 3c16bd1afd87..7ff89690a976 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -80,23 +80,6 @@ config DRM_KMS_HELPER help CRTC helpers for KMS drivers. -config DRM_KMS_FB_HELPER - bool - depends on DRM_KMS_HELPER - select FB - select FRAMEBUFFER_CONSOLE if !EXPERT - select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE - select FB_SYS_FOPS - select FB_SYS_FILLRECT - select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - select FB_DEFERRED_IO - help - FBDEV helpers for KMS drivers. - config DRM_DEBUG_DP_MST_TOPOLOGY_REFS bool "Enable refcount backtrace history in the DP MST helpers" depends on STACKTRACE_SUPPORT @@ -115,8 +98,18 @@ config DRM_DEBUG_DP_MST_TOPOLOGY_REFS config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" depends on DRM + depends on FB select DRM_KMS_HELPER - select DRM_KMS_FB_HELPER + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FRAMEBUFFER_CONSOLE if !EXPERT + select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE default y help Choose this option if you have a need for the legacy fbdev @@ -386,6 +379,19 @@ source "drivers/gpu/drm/xlnx/Kconfig" source "drivers/gpu/drm/gud/Kconfig" +config DRM_HYPERV + tristate "DRM Support for Hyper-V synthetic video device" + depends on DRM && PCI && MMU && HYPERV + select DRM_KMS_HELPER + select DRM_GEM_SHMEM_HELPER + help + This is a KMS driver for Hyper-V synthetic video device. Choose this + option if you would like to enable drm driver for Hyper-V virtual + machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so + that DRM driver is used by default. + + If M is selected the module will be called hyperv_drm. + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 5279db4392df..a118692a6df7 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -3,7 +3,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -drm-y := drm_auth.o drm_cache.o \ +drm-y := drm_aperture.o drm_auth.o drm_cache.o \ drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_drv.o \ drm_sysfs.o drm_hashtab.o drm_mm.o \ @@ -20,15 +20,15 @@ drm-y := drm_auth.o drm_cache.o \ drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o \ drm_managed.o drm_vblank_work.o -drm-$(CONFIG_DRM_LEGACY) += drm_bufs.o drm_context.o drm_dma.o drm_legacy_misc.o drm_lock.o \ - drm_memory.o drm_scatter.o drm_vm.o +drm-$(CONFIG_DRM_LEGACY) += drm_agpsupport.o drm_bufs.o drm_context.o drm_dma.o \ + drm_legacy_misc.o drm_lock.o drm_memory.o drm_scatter.o \ + drm_vm.o drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o drm-$(CONFIG_COMPAT) += drm_ioc32.o drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o drm-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_gem_shmem_helper.o drm-$(CONFIG_DRM_PANEL) += drm_panel.o drm-$(CONFIG_OF) += drm_of.o -drm-$(CONFIG_AGP) += drm_agpsupport.o drm-$(CONFIG_PCI) += drm_pci.o drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o @@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_MCDE) += mcde/ obj-$(CONFIG_DRM_TIDSS) += tidss/ obj-y += xlnx/ obj-y += gud/ +obj-$(CONFIG_DRM_HYPERV) += hyperv/ diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index ee85e8aba636..c56320e78c0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -51,12 +51,15 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ - amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \ - amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \ - amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ + amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \ + amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \ + amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \ + amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ - amdgpu_fw_attestation.o amdgpu_securedisplay.o + amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o + +amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o @@ -71,7 +74,8 @@ amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \ - nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o + nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \ + beige_goby_reg_init.o yellow_carp_reg_init.o # add DF block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index 65b1dca4b02e..148f6c3343ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -227,7 +227,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) break; default: break; - }; + } } /* Reinit NBIF block */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 264176a01e16..c0316eaba547 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -107,6 +107,7 @@ #include "amdgpu_gfxhub.h" #include "amdgpu_df.h" #include "amdgpu_smuio.h" +#include "amdgpu_fdinfo.h" #define MAX_GPU_INSTANCE 16 @@ -129,6 +130,13 @@ struct amdgpu_mgpu_info bool pending_reset; }; +enum amdgpu_ss { + AMDGPU_SS_DRV_LOAD, + AMDGPU_SS_DEV_D0, + AMDGPU_SS_DEV_D3, + AMDGPU_SS_DRV_UNLOAD +}; + struct amdgpu_watchdog_timer { bool timeout_fatal_disable; @@ -203,6 +211,7 @@ extern int amdgpu_discovery; extern int amdgpu_mes; extern int amdgpu_noretry; extern int amdgpu_force_asic_type; +extern int amdgpu_smartshift_bias; #ifdef CONFIG_HSA_AMD extern int sched_policy; extern bool debug_evictions; @@ -260,6 +269,10 @@ extern int amdgpu_num_kcq; #define CIK_CURSOR_WIDTH 128 #define CIK_CURSOR_HEIGHT 128 +/* smasrt shift bias level limits */ +#define AMDGPU_SMARTSHIFT_MAX_BIAS (100) +#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) + struct amdgpu_device; struct amdgpu_ib; struct amdgpu_cs_parser; @@ -267,7 +280,6 @@ struct amdgpu_job; struct amdgpu_irq_src; struct amdgpu_fpriv; struct amdgpu_bo_va_mapping; -struct amdgpu_atif; struct kfd_vm_fault_info; struct amdgpu_hive_info; struct amdgpu_reset_context; @@ -681,20 +693,6 @@ struct amdgpu_vram_scratch { u64 gpu_addr; }; -/* - * ACPI - */ -struct amdgpu_atcs_functions { - bool get_ext_state; - bool pcie_perf_req; - bool pcie_dev_rdy; - bool pcie_bus_width; -}; - -struct amdgpu_atcs { - struct amdgpu_atcs_functions functions; -}; - /* * CGS */ @@ -824,8 +822,6 @@ struct amdgpu_device { struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; struct debugfs_blob_wrapper debugfs_vbios_blob; - struct amdgpu_atif *atif; - struct amdgpu_atcs atcs; struct mutex srbm_mutex; /* GRBM index mutex. Protects concurrent access to GRBM index */ struct mutex grbm_idx_mutex; @@ -1074,9 +1070,10 @@ struct amdgpu_device { atomic_t throttling_logging_enabled; struct ratelimit_state throttling_logging_rs; - uint32_t ras_features; + uint32_t ras_hw_enabled; + uint32_t ras_enabled; - bool in_pci_err_recovery; + bool no_hw_access; struct pci_saved_state *pci_state; struct amdgpu_reset_control *reset_cntl; @@ -1099,7 +1096,9 @@ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) int amdgpu_device_init(struct amdgpu_device *adev, uint32_t flags); -void amdgpu_device_fini(struct amdgpu_device *adev); +void amdgpu_device_fini_hw(struct amdgpu_device *adev); +void amdgpu_device_fini_sw(struct amdgpu_device *adev); + int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, @@ -1142,6 +1141,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); * Registers read & write functions. */ #define AMDGPU_REGS_NO_KIQ (1<<1) +#define AMDGPU_REGS_RLC (1<<2) #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) @@ -1278,12 +1278,18 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev); bool amdgpu_device_supports_atpx(struct drm_device *dev); bool amdgpu_device_supports_px(struct drm_device *dev); bool amdgpu_device_supports_boco(struct drm_device *dev); +bool amdgpu_device_supports_smart_shift(struct drm_device *dev); bool amdgpu_device_supports_baco(struct drm_device *dev); bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev); int amdgpu_device_baco_enter(struct drm_device *dev); int amdgpu_device_baco_exit(struct drm_device *dev); +void amdgpu_device_flush_hdp(struct amdgpu_device *adev, + struct amdgpu_ring *ring); +void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, + struct amdgpu_ring *ring); + /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) void amdgpu_register_atpx_handler(void); @@ -1319,6 +1325,8 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev); int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); void amdgpu_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); +void amdgpu_driver_release_kms(struct drm_device *dev); + int amdgpu_device_ip_suspend(struct amdgpu_device *adev); int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); int amdgpu_device_resume(struct drm_device *dev, bool fbcon); @@ -1350,21 +1358,38 @@ struct amdgpu_afmt_acr { struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); /* amdgpu_acpi.c */ + +/* ATCS Device/Driver State */ +#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 +#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 +#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 +#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 + #if defined(CONFIG_ACPI) int amdgpu_acpi_init(struct amdgpu_device *adev); void amdgpu_acpi_fini(struct amdgpu_device *adev); bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); +bool amdgpu_acpi_is_power_shift_control_supported(void); int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, u8 perf_req, bool advertise); +int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, + u8 dev_state, bool drv_state); +int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); -void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, - struct amdgpu_dm_backlight_caps *caps); +void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); +void amdgpu_acpi_detect(void); #else static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } +static inline void amdgpu_acpi_detect(void) { } +static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } +static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, + u8 dev_state, bool drv_state) { return 0; } +static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, + enum amdgpu_ss ss_state) { return 0; } #endif int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 2e9b16fb3fcd..84a1b4bc9bb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -71,12 +71,31 @@ struct amdgpu_atif { struct amdgpu_dm_backlight_caps backlight_caps; }; +struct amdgpu_atcs_functions { + bool get_ext_state; + bool pcie_perf_req; + bool pcie_dev_rdy; + bool pcie_bus_width; + bool power_shift_control; +}; + +struct amdgpu_atcs { + acpi_handle handle; + + struct amdgpu_atcs_functions functions; +}; + +static struct amdgpu_acpi_priv { + struct amdgpu_atif atif; + struct amdgpu_atcs atcs; +} amdgpu_acpi_priv; + /* Call the ATIF method */ /** * amdgpu_atif_call - call an ATIF method * - * @handle: acpi handle + * @atif: atif structure * @function: the ATIF function to execute * @params: ATIF function params * @@ -166,7 +185,6 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas /** * amdgpu_atif_verify_interface - verify ATIF * - * @handle: acpi handle * @atif: amdgpu atif struct * * Execute the ATIF_FUNCTION_VERIFY_INTERFACE ATIF function @@ -208,40 +226,10 @@ out: return err; } -static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle) -{ - acpi_handle handle = NULL; - char acpi_method_name[255] = { 0 }; - struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name }; - acpi_status status; - - /* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on dGPU only - * systems, ATIF is in the dGPU's namespace. - */ - status = acpi_get_handle(dhandle, "ATIF", &handle); - if (ACPI_SUCCESS(status)) - goto out; - - if (amdgpu_has_atpx()) { - status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF", - &handle); - if (ACPI_SUCCESS(status)) - goto out; - } - - DRM_DEBUG_DRIVER("No ATIF handle found\n"); - return NULL; -out: - acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer); - DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name); - return handle; -} - /** * amdgpu_atif_get_notification_params - determine notify configuration * - * @handle: acpi handle - * @n: atif notification configuration struct + * @atif: acpi handle * * Execute the ATIF_FUNCTION_GET_SYSTEM_PARAMETERS ATIF function * to determine if a notifier is used and if so which one @@ -304,7 +292,7 @@ out: /** * amdgpu_atif_query_backlight_caps - get min and max backlight input signal * - * @handle: acpi handle + * @atif: acpi handle * * Execute the QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS ATIF function * to determine the acceptable range of backlight values @@ -363,7 +351,7 @@ out: /** * amdgpu_atif_get_sbios_requests - get requested sbios event * - * @handle: acpi handle + * @atif: acpi handle * @req: atif sbios request struct * * Execute the ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS ATIF function @@ -416,7 +404,7 @@ out: static int amdgpu_atif_handler(struct amdgpu_device *adev, struct acpi_bus_event *event) { - struct amdgpu_atif *atif = adev->atif; + struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif; int count; DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n", @@ -426,8 +414,7 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, return NOTIFY_DONE; /* Is this actually our event? */ - if (!atif || - !atif->notification_cfg.enabled || + if (!atif->notification_cfg.enabled || event->type != atif->notification_cfg.command_code) { /* These events will generate keypresses otherwise */ if (event->type == ACPI_VIDEO_NOTIFY_PROBE) @@ -487,14 +474,15 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, /** * amdgpu_atcs_call - call an ATCS method * - * @handle: acpi handle + * @atcs: atcs structure * @function: the ATCS function to execute * @params: ATCS function params * * Executes the requested ATCS function (all asics). * Returns a pointer to the acpi output buffer. */ -static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function, +static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs, + int function, struct acpi_buffer *params) { acpi_status status; @@ -518,7 +506,7 @@ static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function, atcs_arg_elements[1].integer.value = 0; } - status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer); + status = acpi_evaluate_object(atcs->handle, NULL, &atcs_arg, &buffer); /* Fail only if calling the method fails and ATIF is supported */ if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { @@ -547,12 +535,12 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; + f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED; } /** * amdgpu_atcs_verify_interface - verify ATCS * - * @handle: acpi handle * @atcs: amdgpu atcs struct * * Execute the ATCS_FUNCTION_VERIFY_INTERFACE ATCS function @@ -560,15 +548,14 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas * (all asics). * returns 0 on success, error on failure. */ -static int amdgpu_atcs_verify_interface(acpi_handle handle, - struct amdgpu_atcs *atcs) +static int amdgpu_atcs_verify_interface(struct amdgpu_atcs *atcs) { union acpi_object *info; struct atcs_verify_interface output; size_t size; int err = 0; - info = amdgpu_atcs_call(handle, ATCS_FUNCTION_VERIFY_INTERFACE, NULL); + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_VERIFY_INTERFACE, NULL); if (!info) return -EIO; @@ -605,7 +592,7 @@ out: */ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev) { - struct amdgpu_atcs *atcs = &adev->atcs; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; if (atcs->functions.pcie_perf_req && atcs->functions.pcie_dev_rdy) return true; @@ -613,6 +600,18 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade return false; } +/** + * amdgpu_acpi_is_power_shift_control_supported + * + * Check if the ATCS power shift control method + * is supported. + * returns true if supported, false if not. + */ +bool amdgpu_acpi_is_power_shift_control_supported(void) +{ + return amdgpu_acpi_priv.atcs.functions.power_shift_control; +} + /** * amdgpu_acpi_pcie_notify_device_ready * @@ -624,19 +623,13 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade */ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev) { - acpi_handle handle; union acpi_object *info; - struct amdgpu_atcs *atcs = &adev->atcs; - - /* Get the device handle */ - handle = ACPI_HANDLE(&adev->pdev->dev); - if (!handle) - return -EINVAL; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; if (!atcs->functions.pcie_dev_rdy) return -EINVAL; - info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL); + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL); if (!info) return -EIO; @@ -659,9 +652,8 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev) int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, u8 perf_req, bool advertise) { - acpi_handle handle; union acpi_object *info; - struct amdgpu_atcs *atcs = &adev->atcs; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; struct atcs_pref_req_input atcs_input; struct atcs_pref_req_output atcs_output; struct acpi_buffer params; @@ -671,11 +663,6 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, if (amdgpu_acpi_pcie_notify_device_ready(adev)) return -EINVAL; - /* Get the device handle */ - handle = ACPI_HANDLE(&adev->pdev->dev); - if (!handle) - return -EINVAL; - if (!atcs->functions.pcie_perf_req) return -EINVAL; @@ -693,7 +680,7 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, params.pointer = &atcs_input; while (retry--) { - info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, ¶ms); + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, ¶ms); if (!info) return -EIO; @@ -726,6 +713,96 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, return 0; } +/** + * amdgpu_acpi_power_shift_control + * + * @adev: amdgpu_device pointer + * @dev_state: device acpi state + * @drv_state: driver state + * + * Executes the POWER_SHIFT_CONTROL method to + * communicate current dGPU device state and + * driver state to APU/SBIOS. + * returns 0 on success, error on failure. + */ +int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, + u8 dev_state, bool drv_state) +{ + union acpi_object *info; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; + struct atcs_pwr_shift_input atcs_input; + struct acpi_buffer params; + + if (!amdgpu_acpi_is_power_shift_control_supported()) + return -EINVAL; + + atcs_input.size = sizeof(struct atcs_pwr_shift_input); + /* dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ + atcs_input.dgpu_id = adev->pdev->devfn | (adev->pdev->bus->number << 8); + atcs_input.dev_acpi_state = dev_state; + atcs_input.drv_state = drv_state; + + params.length = sizeof(struct atcs_pwr_shift_input); + params.pointer = &atcs_input; + + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_POWER_SHIFT_CONTROL, ¶ms); + if (!info) { + DRM_ERROR("ATCS PSC update failed\n"); + return -EIO; + } + + return 0; +} + +/** + * amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS + * + * @dev: drm_device pointer + * @ss_state: current smart shift event + * + * returns 0 on success, + * otherwise return error number. + */ +int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + int r; + + if (!amdgpu_device_supports_smart_shift(dev)) + return 0; + + switch (ss_state) { + /* SBIOS trigger “stop”, “enable” and “start” at D0, Driver Operational. + * SBIOS trigger “stop” at D3, Driver Not Operational. + * SBIOS trigger “stop” and “disable” at D0, Driver NOT operational. + */ + case AMDGPU_SS_DRV_LOAD: + r = amdgpu_acpi_power_shift_control(adev, + AMDGPU_ATCS_PSC_DEV_STATE_D0, + AMDGPU_ATCS_PSC_DRV_STATE_OPR); + break; + case AMDGPU_SS_DEV_D0: + r = amdgpu_acpi_power_shift_control(adev, + AMDGPU_ATCS_PSC_DEV_STATE_D0, + AMDGPU_ATCS_PSC_DRV_STATE_OPR); + break; + case AMDGPU_SS_DEV_D3: + r = amdgpu_acpi_power_shift_control(adev, + AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT, + AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR); + break; + case AMDGPU_SS_DRV_UNLOAD: + r = amdgpu_acpi_power_shift_control(adev, + AMDGPU_ATCS_PSC_DEV_STATE_D0, + AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR); + break; + default: + return -EINVAL; + } + + return r; +} + /** * amdgpu_acpi_event - handle notify events * @@ -769,50 +846,15 @@ static int amdgpu_acpi_event(struct notifier_block *nb, */ int amdgpu_acpi_init(struct amdgpu_device *adev) { - acpi_handle handle, atif_handle; - struct amdgpu_atif *atif; - struct amdgpu_atcs *atcs = &adev->atcs; - int ret; - - /* Get the device handle */ - handle = ACPI_HANDLE(&adev->pdev->dev); - - if (!adev->bios || !handle) - return 0; - - /* Call the ATCS method */ - ret = amdgpu_atcs_verify_interface(handle, atcs); - if (ret) { - DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret); - } - - /* Probe for ATIF, and initialize it if found */ - atif_handle = amdgpu_atif_probe_handle(handle); - if (!atif_handle) - goto out; - - atif = kzalloc(sizeof(*atif), GFP_KERNEL); - if (!atif) { - DRM_WARN("Not enough memory to initialize ATIF\n"); - goto out; - } - atif->handle = atif_handle; - - /* Call the ATIF method */ - ret = amdgpu_atif_verify_interface(atif); - if (ret) { - DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret); - kfree(atif); - goto out; - } - adev->atif = atif; + struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif; #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) if (atif->notifications.brightness_change) { if (amdgpu_device_has_dc_support(adev)) { #if defined(CONFIG_DRM_AMD_DC) struct amdgpu_display_manager *dm = &adev->dm; - atif->bd = dm->backlight_dev; + if (dm->backlight_dev) + atif->bd = dm->backlight_dev; #endif } else { struct drm_encoder *tmp; @@ -834,6 +876,129 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) } } #endif + adev->acpi_nb.notifier_call = amdgpu_acpi_event; + register_acpi_notifier(&adev->acpi_nb); + + return 0; +} + +void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) +{ + struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif; + + caps->caps_valid = atif->backlight_caps.caps_valid; + caps->min_input_signal = atif->backlight_caps.min_input_signal; + caps->max_input_signal = atif->backlight_caps.max_input_signal; +} + +/** + * amdgpu_acpi_fini - tear down driver acpi support + * + * @adev: amdgpu_device pointer + * + * Unregisters with the acpi notifier chain (all asics). + */ +void amdgpu_acpi_fini(struct amdgpu_device *adev) +{ + unregister_acpi_notifier(&adev->acpi_nb); +} + +/** + * amdgpu_atif_pci_probe_handle - look up the ATIF handle + * + * @pdev: pci device + * + * Look up the ATIF handles (all asics). + * Returns true if the handle is found, false if not. + */ +static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev) +{ + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; + acpi_handle dhandle, atif_handle; + acpi_status status; + int ret; + + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return false; + + status = acpi_get_handle(dhandle, "ATIF", &atif_handle); + if (ACPI_FAILURE(status)) { + return false; + } + amdgpu_acpi_priv.atif.handle = atif_handle; + acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer); + DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name); + ret = amdgpu_atif_verify_interface(&amdgpu_acpi_priv.atif); + if (ret) { + amdgpu_acpi_priv.atif.handle = 0; + return false; + } + return true; +} + +/** + * amdgpu_atcs_pci_probe_handle - look up the ATCS handle + * + * @pdev: pci device + * + * Look up the ATCS handles (all asics). + * Returns true if the handle is found, false if not. + */ +static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev) +{ + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name }; + acpi_handle dhandle, atcs_handle; + acpi_status status; + int ret; + + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return false; + + status = acpi_get_handle(dhandle, "ATCS", &atcs_handle); + if (ACPI_FAILURE(status)) { + return false; + } + amdgpu_acpi_priv.atcs.handle = atcs_handle; + acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer); + DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name); + ret = amdgpu_atcs_verify_interface(&amdgpu_acpi_priv.atcs); + if (ret) { + amdgpu_acpi_priv.atcs.handle = 0; + return false; + } + return true; +} + +/* + * amdgpu_acpi_detect - detect ACPI ATIF/ATCS methods + * + * Check if we have the ATIF/ATCS methods and populate + * the structures in the driver. + */ +void amdgpu_acpi_detect(void) +{ + struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; + struct pci_dev *pdev = NULL; + int ret; + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + if (!atif->handle) + amdgpu_atif_pci_probe_handle(pdev); + if (!atcs->handle) + amdgpu_atcs_pci_probe_handle(pdev); + } + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { + if (!atif->handle) + amdgpu_atif_pci_probe_handle(pdev); + if (!atcs->handle) + amdgpu_atcs_pci_probe_handle(pdev); + } if (atif->functions.sbios_requests && !atif->functions.system_params) { /* XXX check this workraround, if sbios request function is @@ -863,42 +1028,13 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) } else { atif->backlight_caps.caps_valid = false; } - -out: - adev->acpi_nb.notifier_call = amdgpu_acpi_event; - register_acpi_notifier(&adev->acpi_nb); - - return ret; -} - -void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, - struct amdgpu_dm_backlight_caps *caps) -{ - if (!adev->atif) { - caps->caps_valid = false; - return; - } - caps->caps_valid = adev->atif->backlight_caps.caps_valid; - caps->min_input_signal = adev->atif->backlight_caps.min_input_signal; - caps->max_input_signal = adev->atif->backlight_caps.max_input_signal; -} - -/** - * amdgpu_acpi_fini - tear down driver acpi support - * - * @adev: amdgpu_device pointer - * - * Unregisters with the acpi notifier chain (all asics). - */ -void amdgpu_acpi_fini(struct amdgpu_device *adev) -{ - unregister_acpi_notifier(&adev->acpi_nb); - kfree(adev->atif); } /** * amdgpu_acpi_is_s0ix_supported * + * @adev: amdgpu_device_pointer + * * returns true if supported, false if not. */ bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 5f6696a3c778..f9c01bdc3d4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -170,7 +170,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) } } -void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) +void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) { if (adev->kfd.dev) { kgd2kfd_device_exit(adev->kfd.dev); @@ -670,10 +670,10 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) return 0; } -int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid) +int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, + enum TLB_FLUSH_TYPE flush_type) { struct amdgpu_device *adev = (struct amdgpu_device *)kgd; - const uint32_t flush_type = 0; bool all_hub = false; if (adev->family == AMDGPU_FAMILY_AI) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5ffb07b02810..db16b3e83694 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -36,13 +36,26 @@ extern uint64_t amdgpu_amdkfd_total_mem_size; +enum TLB_FLUSH_TYPE { + TLB_FLUSH_LEGACY = 0, + TLB_FLUSH_LIGHTWEIGHT, + TLB_FLUSH_HEAVYWEIGHT +}; + struct amdgpu_device; -struct kfd_bo_va_list { - struct list_head bo_list; - struct amdgpu_bo_va *bo_va; - void *kgd_dev; +enum kfd_mem_attachment_type { + KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ + KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ + KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ +}; + +struct kfd_mem_attachment { + struct list_head list; + enum kfd_mem_attachment_type type; bool is_mapped; + struct amdgpu_bo_va *bo_va; + struct amdgpu_device *adev; uint64_t va; uint64_t pte_flags; }; @@ -50,7 +63,8 @@ struct kfd_bo_va_list { struct kgd_mem { struct mutex lock; struct amdgpu_bo *bo; - struct list_head bo_va_list; + struct dma_buf *dmabuf; + struct list_head attachments; /* protected by amdkfd_process_info.lock */ struct ttm_validate_buffer validate_list; struct ttm_validate_buffer resv_list; @@ -75,6 +89,7 @@ struct amdgpu_amdkfd_fence { struct mm_struct *mm; spinlock_t lock; char timeline_name[TASK_COMM_LEN]; + struct svm_range_bo *svm_bo; }; struct amdgpu_kfd_dev { @@ -127,14 +142,15 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, const void *ih_ring_entry); void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); -void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev); +void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, uint32_t vmid, uint64_t gpu_addr, uint32_t *ib_cmd, uint32_t ib_len); void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd); int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid); -int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid); +int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, + enum TLB_FLUSH_TYPE flush_type); bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); @@ -148,7 +164,8 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, int queue_bit); struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, - struct mm_struct *mm); + struct mm_struct *mm, + struct svm_range_bo *svm_bo); #if IS_ENABLED(CONFIG_HSA_AMD) bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); @@ -234,22 +251,27 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s }) /* GPUVM API */ +#define drm_priv_to_vm(drm_priv) \ + (&((struct amdgpu_fpriv *) \ + ((struct drm_file *)(drm_priv))->driver_priv)->vm) + int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, struct file *filp, u32 pasid, - void **vm, void **process_info, + void **process_info, struct dma_fence **ef); -void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm); -uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm); +void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv); +uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct kgd_dev *kgd, uint64_t va, uint64_t size, - void *vm, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size); + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, + uint64_t *size); int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, void *vm); + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed); int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, void *vm); + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); int amdgpu_amdkfd_gpuvm_sync_memory( struct kgd_dev *kgd, struct kgd_mem *mem, bool intr); int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, @@ -260,7 +282,7 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, struct kfd_vm_fault_info *info); int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, struct dma_buf *dmabuf, - uint64_t va, void *vm, + uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset); int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, @@ -270,6 +292,7 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void); void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); +void amdgpu_amdkfd_reserve_system_mem(uint64_t size); #else static inline void amdgpu_amdkfd_gpuvm_init_mem_limits(void) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 9ef9f3ddad48..6409d6b1b2df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -25,6 +25,7 @@ #include #include "amdgpu.h" #include "amdgpu_amdkfd.h" +#include "amdgpu_amdkfd_arcturus.h" #include "sdma0/sdma0_4_2_2_offset.h" #include "sdma0/sdma0_4_2_2_sh_mask.h" #include "sdma1/sdma1_4_2_2_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 5af464933976..1d0dbff87d3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -28,6 +28,7 @@ #include #include #include "amdgpu_amdkfd.h" +#include "kfd_svm.h" static const struct dma_fence_ops amdkfd_fence_ops; static atomic_t fence_seq = ATOMIC_INIT(0); @@ -60,7 +61,8 @@ static atomic_t fence_seq = ATOMIC_INIT(0); */ struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, - struct mm_struct *mm) + struct mm_struct *mm, + struct svm_range_bo *svm_bo) { struct amdgpu_amdkfd_fence *fence; @@ -73,7 +75,7 @@ struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, fence->mm = mm; get_task_comm(fence->timeline_name, current); spin_lock_init(&fence->lock); - + fence->svm_bo = svm_bo; dma_fence_init(&fence->base, &amdkfd_fence_ops, &fence->lock, context, atomic_inc_return(&fence_seq)); @@ -111,6 +113,8 @@ static const char *amdkfd_fence_get_timeline_name(struct dma_fence *f) * a KFD BO and schedules a job to move the BO. * If fence is already signaled return true. * If fence is not signaled schedule a evict KFD process work item. + * + * @f: dma_fence */ static bool amdkfd_fence_enable_signaling(struct dma_fence *f) { @@ -122,16 +126,20 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f) if (dma_fence_is_signaled(f)) return true; - if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f)) - return true; - + if (!fence->svm_bo) { + if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f)) + return true; + } else { + if (!svm_range_schedule_evict_svm_bo(fence)) + return true; + } return false; } /** * amdkfd_fence_release - callback that fence can be freed * - * @fence: fence + * @f: dma_fence * * This function is called when the reference count becomes zero. * Drops the mm_struct reference and RCU schedules freeing up the fence. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c index 62aa1a6f64ed..491acdf92f73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c @@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, lock_srbm(kgd, 0, 0, 0, vmid); - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); /* APE1 no longer exists on GFX9 */ unlock_srbm(kgd); @@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) lock_srbm(kgd, mec, pipe, 0, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), + WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); @@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, for (reg = hqd_base; reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) - WREG32(reg, mqd_hqd[reg - hqd_base]); + WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); /* Activate doorbell logic before triggering WPTR poll. */ data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); if (wptr) { /* Don't read wptr with get_user because the user @@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, lower_32_bits(guessed_wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, upper_32_bits(guessed_wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, lower_32_bits((uint64_t)wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, upper_32_bits((uint64_t)wptr)); pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), + WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); } /* Start the EOP fetcher */ - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), + WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); release_queue(kgd); @@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd, if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ break; \ (*dump)[i][0] = (addr) << 2; \ - (*dump)[i++][1] = RREG32(addr); \ + (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ } while (0) *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); @@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t low, high; acquire_queue(kgd, pipe_id, queue_id); - act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); + act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); if (act) { low = lower_32_bits(queue_address >> 8); high = upper_32_bits(queue_address >> 8); - if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && - high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) + if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) && + high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) retval = true; } release_queue(kgd); @@ -621,11 +621,11 @@ loop: preempt_enable(); #endif - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { - temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); + temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; if (time_after(jiffies, end_jiffies)) { @@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, mutex_lock(&adev->grbm_idx_mutex); - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); - WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); + WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); data = REG_SET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); @@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); mutex_unlock(&adev->grbm_idx_mutex); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c index d39cff4a1fe3..1f5620cc3570 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c @@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid, lock_srbm(kgd, 0, 0, 0, vmid); - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); /* APE1 no longer exists on GFX9 */ unlock_srbm(kgd); @@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id) lock_srbm(kgd, mec, pipe, 0, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), + WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); @@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", mec, pipe, queue_id); - value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); + value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, ((mec << 5) | (pipe << 3) | queue_id | 0x80)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); + WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value); } /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ @@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, for (reg = hqd_base; reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) - WREG32(reg, mqd_hqd[reg - hqd_base]); + WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); /* Activate doorbell logic before triggering WPTR poll. */ data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); if (wptr) { /* Don't read wptr with get_user because the user @@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, lower_32_bits(guessed_wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, upper_32_bits(guessed_wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, lower_32_bits((uint64_t)wptr)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, upper_32_bits((uint64_t)wptr)); pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), + WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); } @@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); release_queue(kgd); @@ -350,7 +350,7 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd, if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ break; \ (*dump)[i][0] = (addr) << 2; \ - (*dump)[i++][1] = RREG32(addr); \ + (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ } while (0) *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); @@ -482,13 +482,13 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address, uint32_t low, high; acquire_queue(kgd, pipe_id, queue_id); - act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); + act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); if (act) { low = lower_32_bits(queue_address >> 8); high = upper_32_bits(queue_address >> 8); - if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && - high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) + if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) && + high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) retval = true; } release_queue(kgd); @@ -542,11 +542,11 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd, break; } - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { - temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); + temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; if (time_after(jiffies, end_jiffies)) { @@ -626,7 +626,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd, mutex_lock(&adev->grbm_idx_mutex); - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); data = REG_SET_FIELD(data, GRBM_GFX_INDEX, @@ -636,7 +636,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd, data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); mutex_unlock(&adev->grbm_idx_mutex); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index b43e68fc1378..ed3014fbb563 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -719,7 +719,7 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev) } /** - * @get_wave_count: Read device registers to get number of waves in flight for + * get_wave_count: Read device registers to get number of waves in flight for * a particular queue. The method also returns the VMID associated with the * queue. * @@ -755,19 +755,19 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, } /** - * @kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each + * kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each * shader engine and aggregates the number of waves that are in flight for the * process whose pasid is provided as a parameter. The process could have ZERO * or more queues running and submitting waves to compute units. * * @kgd: Handle of device from which to get number of waves in flight * @pasid: Identifies the process for which this query call is invoked - * @wave_cnt: Output parameter updated with number of waves in flight that + * @pasid_wave_cnt: Output parameter updated with number of waves in flight that * belong to process with given pasid * @max_waves_per_cu: Output parameter updated with maximum number of waves * possible per Compute Unit * - * @note: It's possible that the device has too many queues (oversubscription) + * Note: It's possible that the device has too many queues (oversubscription) * in which case a VMID could be remapped to a different PASID. This could lead * to an iaccurate wave count. Following is a high-level sequence: * Time T1: vmid = getVmid(); vmid is associated with Pasid P1 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7d4118c8128a..3b8e1ee8c475 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -33,9 +33,6 @@ #include #include "amdgpu_xgmi.h" -/* BO flag to indicate a KFD userptr BO */ -#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63) - /* Userptr restore delay, just long enough to allow consecutive VM * changes to accumulate */ @@ -50,12 +47,6 @@ static struct { spinlock_t mem_limit_lock; } kfd_mem_limit; -/* Struct used for amdgpu_amdkfd_bo_validate */ -struct amdgpu_vm_parser { - uint32_t domain; - bool wait; -}; - static const char * const domain_bit_to_string[] = { "CPU", "GTT", @@ -75,16 +66,16 @@ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) return (struct amdgpu_device *)kgd; } -static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm, +static bool kfd_mem_is_attached(struct amdgpu_vm *avm, struct kgd_mem *mem) { - struct kfd_bo_va_list *entry; + struct kfd_mem_attachment *entry; - list_for_each_entry(entry, &mem->bo_va_list, bo_list) + list_for_each_entry(entry, &mem->attachments, list) if (entry->bo_va->base.vm == avm) - return false; + return true; - return true; + return false; } /* Set memory usage limits. Current, limits are @@ -108,6 +99,11 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void) (kfd_mem_limit.max_ttm_mem_limit >> 20)); } +void amdgpu_amdkfd_reserve_system_mem(uint64_t size) +{ + kfd_mem_limit.system_mem_used += size; +} + /* Estimate page table size needed to represent a given memory size * * With 4KB pages, we need one 8 byte PTE for each 4KB of memory @@ -217,7 +213,7 @@ void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) u32 domain = bo->preferred_domains; bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU); - if (bo->flags & AMDGPU_AMDKFD_USERPTR_BO) { + if (bo->flags & AMDGPU_AMDKFD_CREATE_USERPTR_BO) { domain = AMDGPU_GEM_DOMAIN_CPU; sg = false; } @@ -245,7 +241,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, if (!ef) return -EINVAL; - old = dma_resv_get_list(resv); + old = dma_resv_shared_list(resv); if (!old) return 0; @@ -276,7 +272,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, write_seqcount_end(&resv->seq); /* Drop the references to the removed fences or move them to ef_list */ - for (i = j, k = 0; i < old->shared_count; ++i) { + for (i = j; i < old->shared_count; ++i) { struct dma_fence *f; f = rcu_dereference_protected(new->shared[i], @@ -346,11 +342,9 @@ validate_fail: return ret; } -static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo) +static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) { - struct amdgpu_vm_parser *p = param; - - return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait); + return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false); } /* vm_validate_pt_pd_bos - Validate page table and directory BOs @@ -362,28 +356,23 @@ static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo) */ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) { - struct amdgpu_bo *pd = vm->root.base.bo; + struct amdgpu_bo *pd = vm->root.bo; struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); - struct amdgpu_vm_parser param; int ret; - param.domain = AMDGPU_GEM_DOMAIN_VRAM; - param.wait = false; - - ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate, - ¶m); + ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL); if (ret) { pr_err("failed to validate PT BOs\n"); return ret; } - ret = amdgpu_amdkfd_validate(¶m, pd); + ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd); if (ret) { pr_err("failed to validate PD\n"); return ret; } - vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo); + vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo); if (vm->use_cpu_for_update) { ret = amdgpu_bo_kmap(pd, NULL); @@ -398,7 +387,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) { - struct amdgpu_bo *pd = vm->root.base.bo; + struct amdgpu_bo *pd = vm->root.bo; struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); int ret; @@ -431,7 +420,8 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) mapping_flags |= coherent ? AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW; else - mapping_flags |= AMDGPU_VM_MTYPE_UC; + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; } else { mapping_flags |= coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; @@ -450,7 +440,8 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) if (adev->gmc.xgmi.connected_to_cpu) snoop = true; } else { - mapping_flags |= AMDGPU_VM_MTYPE_UC; + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; if (amdgpu_xgmi_same_hive(adev, bo_adev)) snoop = true; } @@ -471,87 +462,320 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) return pte_flags; } -/* add_bo_to_vm - Add a BO to a VM +static int +kfd_mem_dmamap_userptr(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + enum dma_data_direction direction = + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + struct ttm_operation_ctx ctx = {.interruptible = true}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + struct amdgpu_device *adev = attachment->adev; + struct ttm_tt *src_ttm = mem->bo->tbo.ttm; + struct ttm_tt *ttm = bo->tbo.ttm; + int ret; + + ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL); + if (unlikely(!ttm->sg)) + return -ENOMEM; + + if (WARN_ON(ttm->num_pages != src_ttm->num_pages)) + return -EINVAL; + + /* Same sequence as in amdgpu_ttm_tt_pin_userptr */ + ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages, + ttm->num_pages, 0, + (u64)ttm->num_pages << PAGE_SHIFT, + GFP_KERNEL); + if (unlikely(ret)) + goto free_sg; + + ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); + if (unlikely(ret)) + goto release_sg; + + drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address, + ttm->num_pages); + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + goto unmap_sg; + + return 0; + +unmap_sg: + dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); +release_sg: + pr_err("DMA map userptr failed: %d\n", ret); + sg_free_table(ttm->sg); +free_sg: + kfree(ttm->sg); + ttm->sg = NULL; + return ret; +} + +static int +kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment) +{ + struct ttm_operation_ctx ctx = {.interruptible = true}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +} + +static int +kfd_mem_dmamap_attachment(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + switch (attachment->type) { + case KFD_MEM_ATT_SHARED: + return 0; + case KFD_MEM_ATT_USERPTR: + return kfd_mem_dmamap_userptr(mem, attachment); + case KFD_MEM_ATT_DMABUF: + return kfd_mem_dmamap_dmabuf(attachment); + default: + WARN_ON_ONCE(1); + } + return -EINVAL; +} + +static void +kfd_mem_dmaunmap_userptr(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + enum dma_data_direction direction = + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + struct ttm_operation_ctx ctx = {.interruptible = false}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + struct amdgpu_device *adev = attachment->adev; + struct ttm_tt *ttm = bo->tbo.ttm; + + if (unlikely(!ttm->sg)) + return; + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + + dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); + sg_free_table(ttm->sg); + ttm->sg = NULL; +} + +static void +kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment) +{ + struct ttm_operation_ctx ctx = {.interruptible = true}; + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +} + +static void +kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, + struct kfd_mem_attachment *attachment) +{ + switch (attachment->type) { + case KFD_MEM_ATT_SHARED: + break; + case KFD_MEM_ATT_USERPTR: + kfd_mem_dmaunmap_userptr(mem, attachment); + break; + case KFD_MEM_ATT_DMABUF: + kfd_mem_dmaunmap_dmabuf(attachment); + break; + default: + WARN_ON_ONCE(1); + } +} + +static int +kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem, + struct amdgpu_bo **bo) +{ + unsigned long bo_size = mem->bo->tbo.base.size; + struct drm_gem_object *gobj; + int ret; + + ret = amdgpu_bo_reserve(mem->bo, false); + if (ret) + return ret; + + ret = amdgpu_gem_object_create(adev, bo_size, 1, + AMDGPU_GEM_DOMAIN_CPU, + AMDGPU_GEM_CREATE_PREEMPTIBLE, + ttm_bo_type_sg, mem->bo->tbo.base.resv, + &gobj); + amdgpu_bo_unreserve(mem->bo); + if (ret) + return ret; + + *bo = gem_to_amdgpu_bo(gobj); + (*bo)->parent = amdgpu_bo_ref(mem->bo); + + return 0; +} + +static int +kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, + struct amdgpu_bo **bo) +{ + struct drm_gem_object *gobj; + int ret; + + if (!mem->dmabuf) { + mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0); + if (IS_ERR(mem->dmabuf)) { + ret = PTR_ERR(mem->dmabuf); + mem->dmabuf = NULL; + return ret; + } + } + + gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); + if (IS_ERR(gobj)) + return PTR_ERR(gobj); + + /* Import takes an extra reference on the dmabuf. Drop it now to + * avoid leaking it. We only need the one reference in + * kgd_mem->dmabuf. + */ + dma_buf_put(mem->dmabuf); + + *bo = gem_to_amdgpu_bo(gobj); + (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; + (*bo)->parent = amdgpu_bo_ref(mem->bo); + + return 0; +} + +/* kfd_mem_attach - Add a BO to a VM * * Everything that needs to bo done only once when a BO is first added * to a VM. It can later be mapped and unmapped many times without * repeating these steps. * + * 0. Create BO for DMA mapping, if needed * 1. Allocate and initialize BO VA entry data structure * 2. Add BO to the VM * 3. Determine ASIC-specific PTE flags * 4. Alloc page tables and directories if needed * 4a. Validate new page tables and directories */ -static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem, - struct amdgpu_vm *vm, bool is_aql, - struct kfd_bo_va_list **p_bo_va_entry) +static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, + struct amdgpu_vm *vm, bool is_aql) { - int ret; - struct kfd_bo_va_list *bo_va_entry; - struct amdgpu_bo *bo = mem->bo; + struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + unsigned long bo_size = mem->bo->tbo.base.size; uint64_t va = mem->va; - struct list_head *list_bo_va = &mem->bo_va_list; - unsigned long bo_size = bo->tbo.base.size; + struct kfd_mem_attachment *attachment[2] = {NULL, NULL}; + struct amdgpu_bo *bo[2] = {NULL, NULL}; + int i, ret; if (!va) { pr_err("Invalid VA when adding BO to VM\n"); return -EINVAL; } - if (is_aql) + for (i = 0; i <= is_aql; i++) { + attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL); + if (unlikely(!attachment[i])) { + ret = -ENOMEM; + goto unwind; + } + + pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, + va + bo_size, vm); + + if (adev == bo_adev || (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && + amdgpu_xgmi_same_hive(adev, bo_adev))) { + /* Mappings on the local GPU and VRAM mappings in the + * local hive share the original BO + */ + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); + } else if (i > 0) { + /* Multiple mappings on the same GPU share the BO */ + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = bo[0]; + drm_gem_object_get(&bo[i]->tbo.base); + } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { + /* Create an SG BO to DMA-map userptrs on other GPUs */ + attachment[i]->type = KFD_MEM_ATT_USERPTR; + ret = kfd_mem_attach_userptr(adev, mem, &bo[i]); + if (ret) + goto unwind; + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT && + mem->bo->tbo.type != ttm_bo_type_sg) { + /* GTT BOs use DMA-mapping ability of dynamic-attach + * DMA bufs. TODO: The same should work for VRAM on + * large-BAR GPUs. + */ + attachment[i]->type = KFD_MEM_ATT_DMABUF; + ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); + if (ret) + goto unwind; + } else { + /* FIXME: Need to DMA-map other BO types: + * large-BAR VRAM, doorbells, MMIO remap + */ + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); + } + + /* Add BO to VM internal data structures */ + attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); + if (unlikely(!attachment[i]->bo_va)) { + ret = -ENOMEM; + pr_err("Failed to add BO object to VM. ret == %d\n", + ret); + goto unwind; + } + + attachment[i]->va = va; + attachment[i]->pte_flags = get_pte_flags(adev, mem); + attachment[i]->adev = adev; + list_add(&attachment[i]->list, &mem->attachments); + va += bo_size; - - bo_va_entry = kzalloc(sizeof(*bo_va_entry), GFP_KERNEL); - if (!bo_va_entry) - return -ENOMEM; - - pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, - va + bo_size, vm); - - /* Add BO to VM internal data structures*/ - bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, vm, bo); - if (!bo_va_entry->bo_va) { - ret = -EINVAL; - pr_err("Failed to add BO object to VM. ret == %d\n", - ret); - goto err_vmadd; - } - - bo_va_entry->va = va; - bo_va_entry->pte_flags = get_pte_flags(adev, mem); - bo_va_entry->kgd_dev = (void *)adev; - list_add(&bo_va_entry->bo_list, list_bo_va); - - if (p_bo_va_entry) - *p_bo_va_entry = bo_va_entry; - - /* Allocate validate page tables if needed */ - ret = vm_validate_pt_pd_bos(vm); - if (ret) { - pr_err("validate_pt_pd_bos() failed\n"); - goto err_alloc_pts; } return 0; -err_alloc_pts: - amdgpu_vm_bo_rmv(adev, bo_va_entry->bo_va); - list_del(&bo_va_entry->bo_list); -err_vmadd: - kfree(bo_va_entry); +unwind: + for (; i >= 0; i--) { + if (!attachment[i]) + continue; + if (attachment[i]->bo_va) { + amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va); + list_del(&attachment[i]->list); + } + if (bo[i]) + drm_gem_object_put(&bo[i]->tbo.base); + kfree(attachment[i]); + } return ret; } -static void remove_bo_from_vm(struct amdgpu_device *adev, - struct kfd_bo_va_list *entry, unsigned long size) +static void kfd_mem_detach(struct kfd_mem_attachment *attachment) { - pr_debug("\t remove VA 0x%llx - 0x%llx in entry %p\n", - entry->va, - entry->va + size, entry); - amdgpu_vm_bo_rmv(adev, entry->bo_va); - list_del(&entry->bo_list); - kfree(entry); + struct amdgpu_bo *bo = attachment->bo_va->base.bo; + + pr_debug("\t remove VA 0x%llx in entry %p\n", + attachment->va, attachment); + amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va); + drm_gem_object_put(&bo->tbo.base); + list_del(&attachment->list); + kfree(attachment); } static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem, @@ -726,7 +950,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem, struct bo_vm_reservation_context *ctx) { struct amdgpu_bo *bo = mem->bo; - struct kfd_bo_va_list *entry; + struct kfd_mem_attachment *entry; unsigned int i; int ret; @@ -738,7 +962,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem, INIT_LIST_HEAD(&ctx->list); INIT_LIST_HEAD(&ctx->duplicates); - list_for_each_entry(entry, &mem->bo_va_list, bo_list) { + list_for_each_entry(entry, &mem->attachments, list) { if ((vm && vm != entry->bo_va->base.vm) || (entry->is_mapped != map_type && map_type != BO_VM_ALL)) @@ -760,7 +984,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem, list_add(&ctx->kfd_bo.tv.head, &ctx->list); i = 0; - list_for_each_entry(entry, &mem->bo_va_list, bo_list) { + list_for_each_entry(entry, &mem->attachments, list) { if ((vm && vm != entry->bo_va->base.vm) || (entry->is_mapped != map_type && map_type != BO_VM_ALL)) @@ -814,11 +1038,12 @@ static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx, return ret; } -static int unmap_bo_from_gpuvm(struct amdgpu_device *adev, - struct kfd_bo_va_list *entry, +static void unmap_bo_from_gpuvm(struct kgd_mem *mem, + struct kfd_mem_attachment *entry, struct amdgpu_sync *sync) { struct amdgpu_bo_va *bo_va = entry->bo_va; + struct amdgpu_device *adev = entry->adev; struct amdgpu_vm *vm = bo_va->base.vm; amdgpu_vm_bo_unmap(adev, bo_va, entry->va); @@ -827,18 +1052,24 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev, amdgpu_sync_fence(sync, bo_va->last_pt_update); - return 0; + kfd_mem_dmaunmap_attachment(mem, entry); } -static int update_gpuvm_pte(struct amdgpu_device *adev, - struct kfd_bo_va_list *entry, - struct amdgpu_sync *sync) +static int update_gpuvm_pte(struct kgd_mem *mem, + struct kfd_mem_attachment *entry, + struct amdgpu_sync *sync, + bool *table_freed) { - int ret; struct amdgpu_bo_va *bo_va = entry->bo_va; + struct amdgpu_device *adev = entry->adev; + int ret; + + ret = kfd_mem_dmamap_attachment(mem, entry); + if (ret) + return ret; /* Update the page tables */ - ret = amdgpu_vm_bo_update(adev, bo_va, false); + ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed); if (ret) { pr_err("amdgpu_vm_bo_update failed\n"); return ret; @@ -847,14 +1078,16 @@ static int update_gpuvm_pte(struct amdgpu_device *adev, return amdgpu_sync_fence(sync, bo_va->last_pt_update); } -static int map_bo_to_gpuvm(struct amdgpu_device *adev, - struct kfd_bo_va_list *entry, struct amdgpu_sync *sync, - bool no_update_pte) +static int map_bo_to_gpuvm(struct kgd_mem *mem, + struct kfd_mem_attachment *entry, + struct amdgpu_sync *sync, + bool no_update_pte, + bool *table_freed) { int ret; /* Set virtual address for the allocation */ - ret = amdgpu_vm_bo_map(adev, entry->bo_va, entry->va, 0, + ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0, amdgpu_bo_size(entry->bo_va->base.bo), entry->pte_flags); if (ret) { @@ -866,7 +1099,7 @@ static int map_bo_to_gpuvm(struct amdgpu_device *adev, if (no_update_pte) return 0; - ret = update_gpuvm_pte(adev, entry, sync); + ret = update_gpuvm_pte(mem, entry, sync, table_freed); if (ret) { pr_err("update_gpuvm_pte() failed\n"); goto update_gpuvm_pte_failed; @@ -875,7 +1108,7 @@ static int map_bo_to_gpuvm(struct amdgpu_device *adev, return 0; update_gpuvm_pte_failed: - unmap_bo_from_gpuvm(adev, entry, sync); + unmap_bo_from_gpuvm(mem, entry, sync); return ret; } @@ -920,7 +1153,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, list_for_each_entry(peer_vm, &process_info->vm_list_head, vm_list_node) { - struct amdgpu_bo *pd = peer_vm->root.base.bo; + struct amdgpu_bo *pd = peer_vm->root.bo; ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, AMDGPU_SYNC_NE_OWNER, @@ -967,7 +1200,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, info->eviction_fence = amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), - current->mm); + current->mm, + NULL); if (!info->eviction_fence) { pr_err("Failed to create eviction fence\n"); ret = -ENOMEM; @@ -986,7 +1220,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, vm->process_info = *process_info; /* Validate page directory and attach eviction fence */ - ret = amdgpu_bo_reserve(vm->root.base.bo, true); + ret = amdgpu_bo_reserve(vm->root.bo, true); if (ret) goto reserve_pd_fail; ret = vm_validate_pt_pd_bos(vm); @@ -994,16 +1228,16 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, pr_err("validate_pt_pd_bos() failed\n"); goto validate_pd_fail; } - ret = amdgpu_bo_sync_wait(vm->root.base.bo, + ret = amdgpu_bo_sync_wait(vm->root.bo, AMDGPU_FENCE_OWNER_KFD, false); if (ret) goto wait_pd_fail; - ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1); + ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1); if (ret) goto reserve_shared_fail; - amdgpu_bo_fence(vm->root.base.bo, + amdgpu_bo_fence(vm->root.bo, &vm->process_info->eviction_fence->base, true); - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); /* Update process info */ mutex_lock(&vm->process_info->lock); @@ -1017,7 +1251,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, reserve_shared_fail: wait_pd_fail: validate_pd_fail: - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); reserve_pd_fail: vm->process_info = NULL; if (info) { @@ -1036,15 +1270,19 @@ create_evict_fence_fail: int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, struct file *filp, u32 pasid, - void **vm, void **process_info, + void **process_info, struct dma_fence **ef) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct drm_file *drm_priv = filp->private_data; - struct amdgpu_fpriv *drv_priv = drm_priv->driver_priv; - struct amdgpu_vm *avm = &drv_priv->vm; + struct amdgpu_fpriv *drv_priv; + struct amdgpu_vm *avm; int ret; + ret = amdgpu_file_to_fpriv(filp, &drv_priv); + if (ret) + return ret; + avm = &drv_priv->vm; + /* Already a compute VM? */ if (avm->process_info) return -EINVAL; @@ -1059,7 +1297,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, if (ret) return ret; - *vm = (void *)avm; + amdgpu_vm_set_task_info(avm); return 0; } @@ -1068,7 +1306,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdkfd_process_info *process_info = vm->process_info; - struct amdgpu_bo *pd = vm->root.base.bo; + struct amdgpu_bo *pd = vm->root.bo; if (!process_info) return; @@ -1100,15 +1338,17 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, } } -void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm) +void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct amdgpu_vm *avm = (struct amdgpu_vm *)vm; + struct amdgpu_vm *avm; - if (WARN_ON(!kgd || !vm)) + if (WARN_ON(!kgd || !drm_priv)) return; - pr_debug("Releasing process vm %p\n", vm); + avm = drm_priv_to_vm(drm_priv); + + pr_debug("Releasing process vm %p\n", avm); /* The original pasid of amdgpu vm has already been * released during making a amdgpu vm to a compute vm @@ -1119,10 +1359,10 @@ void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm) amdgpu_vm_release_compute(adev, avm); } -uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm) +uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv) { - struct amdgpu_vm *avm = (struct amdgpu_vm *)vm; - struct amdgpu_bo *pd = avm->root.base.bo; + struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); + struct amdgpu_bo *pd = avm->root.bo; struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); if (adev->asic_type < CHIP_VEGA10) @@ -1132,11 +1372,11 @@ uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm) int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct kgd_dev *kgd, uint64_t va, uint64_t size, - void *vm, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct amdgpu_vm *avm = (struct amdgpu_vm *)vm; + struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); enum ttm_bo_type bo_type = ttm_bo_type_device; struct sg_table *sg = NULL; uint64_t user_addr = 0; @@ -1161,7 +1401,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { domain = AMDGPU_GEM_DOMAIN_GTT; alloc_domain = AMDGPU_GEM_DOMAIN_CPU; - alloc_flags = 0; + alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE; if (!offset || !*offset) return -EINVAL; user_addr = untagged_addr(*offset); @@ -1185,7 +1425,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( ret = -ENOMEM; goto err; } - INIT_LIST_HEAD(&(*mem)->bo_va_list); + INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM); @@ -1216,6 +1456,11 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( domain_string(alloc_domain), ret); goto err_bo_create; } + ret = drm_vma_node_allow(&gobj->vma_node, drm_priv); + if (ret) { + pr_debug("Failed to allow vma node access. ret %d\n", ret); + goto err_node_allow; + } bo = gem_to_amdgpu_bo(gobj); if (bo_type == ttm_bo_type_sg) { bo->tbo.sg = sg; @@ -1224,7 +1469,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( bo->kfd_bo = *mem; (*mem)->bo = bo; if (user_addr) - bo->flags |= AMDGPU_AMDKFD_USERPTR_BO; + bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO; (*mem)->va = va; (*mem)->domain = domain; @@ -1245,6 +1490,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( allocate_init_user_pages_failed: remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info); + drm_vma_node_revoke(&gobj->vma_node, drm_priv); +err_node_allow: amdgpu_bo_unref(&bo); /* Don't unreserve system mem limit twice */ goto err_reserve_limit; @@ -1262,11 +1509,12 @@ err: } int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size) + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, + uint64_t *size) { struct amdkfd_process_info *process_info = mem->process_info; unsigned long bo_size = mem->bo->tbo.base.size; - struct kfd_bo_va_list *entry, *tmp; + struct kfd_mem_attachment *entry, *tmp; struct bo_vm_reservation_context ctx; struct ttm_validate_buffer *bo_list_entry; unsigned int mapped_to_gpu_memory; @@ -1309,13 +1557,12 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va, mem->va + bo_size * (1 + mem->aql_queue)); - /* Remove from VM internal data structures */ - list_for_each_entry_safe(entry, tmp, &mem->bo_va_list, bo_list) - remove_bo_from_vm((struct amdgpu_device *)entry->kgd_dev, - entry, bo_size); - ret = unreserve_bo_and_vms(&ctx, false, false); + /* Remove from VM internal data structures */ + list_for_each_entry_safe(entry, tmp, &mem->attachments, list) + kfd_mem_detach(entry); + /* Free the sync object */ amdgpu_sync_free(&mem->sync); @@ -1339,6 +1586,9 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( } /* Free the BO*/ + drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); + if (mem->dmabuf) + dma_buf_put(mem->dmabuf); drm_gem_object_put(&mem->bo->tbo.base); mutex_destroy(&mem->lock); kfree(mem); @@ -1347,17 +1597,16 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( } int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, void *vm) + struct kgd_dev *kgd, struct kgd_mem *mem, + void *drm_priv, bool *table_freed) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct amdgpu_vm *avm = (struct amdgpu_vm *)vm; + struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); int ret; struct amdgpu_bo *bo; uint32_t domain; - struct kfd_bo_va_list *entry; + struct kfd_mem_attachment *entry; struct bo_vm_reservation_context ctx; - struct kfd_bo_va_list *bo_va_entry = NULL; - struct kfd_bo_va_list *bo_va_entry_aql = NULL; unsigned long bo_size; bool is_invalid_userptr = false; @@ -1391,9 +1640,15 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n", mem->va, mem->va + bo_size * (1 + mem->aql_queue), - vm, domain_string(domain)); + avm, domain_string(domain)); - ret = reserve_bo_and_vm(mem, vm, &ctx); + if (!kfd_mem_is_attached(avm, mem)) { + ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue); + if (ret) + goto out; + } + + ret = reserve_bo_and_vm(mem, avm, &ctx); if (unlikely(ret)) goto out; @@ -1403,25 +1658,12 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( * the next restore worker */ if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && - bo->tbo.mem.mem_type == TTM_PL_SYSTEM) + bo->tbo.resource->mem_type == TTM_PL_SYSTEM) is_invalid_userptr = true; - if (check_if_add_bo_to_vm(avm, mem)) { - ret = add_bo_to_vm(adev, mem, avm, false, - &bo_va_entry); - if (ret) - goto add_bo_to_vm_failed; - if (mem->aql_queue) { - ret = add_bo_to_vm(adev, mem, avm, - true, &bo_va_entry_aql); - if (ret) - goto add_bo_to_vm_failed_aql; - } - } else { - ret = vm_validate_pt_pd_bos(avm); - if (unlikely(ret)) - goto add_bo_to_vm_failed; - } + ret = vm_validate_pt_pd_bos(avm); + if (unlikely(ret)) + goto out_unreserve; if (mem->mapped_to_gpu_memory == 0 && !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { @@ -1432,34 +1674,34 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( ret = amdgpu_amdkfd_bo_validate(bo, domain, true); if (ret) { pr_debug("Validate failed\n"); - goto map_bo_to_gpuvm_failed; + goto out_unreserve; } } - list_for_each_entry(entry, &mem->bo_va_list, bo_list) { - if (entry->bo_va->base.vm == vm && !entry->is_mapped) { - pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n", - entry->va, entry->va + bo_size, - entry); + list_for_each_entry(entry, &mem->attachments, list) { + if (entry->bo_va->base.vm != avm || entry->is_mapped) + continue; - ret = map_bo_to_gpuvm(adev, entry, ctx.sync, - is_invalid_userptr); - if (ret) { - pr_err("Failed to map bo to gpuvm\n"); - goto map_bo_to_gpuvm_failed; - } + pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n", + entry->va, entry->va + bo_size, entry); - ret = vm_update_pds(vm, ctx.sync); - if (ret) { - pr_err("Failed to update page directories\n"); - goto map_bo_to_gpuvm_failed; - } - - entry->is_mapped = true; - mem->mapped_to_gpu_memory++; - pr_debug("\t INC mapping count %d\n", - mem->mapped_to_gpu_memory); + ret = map_bo_to_gpuvm(mem, entry, ctx.sync, + is_invalid_userptr, table_freed); + if (ret) { + pr_err("Failed to map bo to gpuvm\n"); + goto out_unreserve; } + + ret = vm_update_pds(avm, ctx.sync); + if (ret) { + pr_err("Failed to update page directories\n"); + goto out_unreserve; + } + + entry->is_mapped = true; + mem->mapped_to_gpu_memory++; + pr_debug("\t INC mapping count %d\n", + mem->mapped_to_gpu_memory); } if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count) @@ -1470,13 +1712,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( goto out; -map_bo_to_gpuvm_failed: - if (bo_va_entry_aql) - remove_bo_from_vm(adev, bo_va_entry_aql, bo_size); -add_bo_to_vm_failed_aql: - if (bo_va_entry) - remove_bo_from_vm(adev, bo_va_entry, bo_size); -add_bo_to_vm_failed: +out_unreserve: unreserve_bo_and_vms(&ctx, false, false); out: mutex_unlock(&mem->process_info->lock); @@ -1485,19 +1721,18 @@ out: } int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - struct kgd_dev *kgd, struct kgd_mem *mem, void *vm) + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv) { - struct amdgpu_device *adev = get_amdgpu_device(kgd); - struct amdkfd_process_info *process_info = - ((struct amdgpu_vm *)vm)->process_info; + struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); + struct amdkfd_process_info *process_info = avm->process_info; unsigned long bo_size = mem->bo->tbo.base.size; - struct kfd_bo_va_list *entry; + struct kfd_mem_attachment *entry; struct bo_vm_reservation_context ctx; int ret; mutex_lock(&mem->lock); - ret = reserve_bo_and_cond_vms(mem, vm, BO_VM_MAPPED, &ctx); + ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx); if (unlikely(ret)) goto out; /* If no VMs were reserved, it means the BO wasn't actually mapped */ @@ -1506,35 +1741,28 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( goto unreserve_out; } - ret = vm_validate_pt_pd_bos((struct amdgpu_vm *)vm); + ret = vm_validate_pt_pd_bos(avm); if (unlikely(ret)) goto unreserve_out; pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n", mem->va, mem->va + bo_size * (1 + mem->aql_queue), - vm); + avm); - list_for_each_entry(entry, &mem->bo_va_list, bo_list) { - if (entry->bo_va->base.vm == vm && entry->is_mapped) { - pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n", - entry->va, - entry->va + bo_size, - entry); + list_for_each_entry(entry, &mem->attachments, list) { + if (entry->bo_va->base.vm != avm || !entry->is_mapped) + continue; - ret = unmap_bo_from_gpuvm(adev, entry, ctx.sync); - if (ret == 0) { - entry->is_mapped = false; - } else { - pr_err("failed to unmap VA 0x%llx\n", - mem->va); - goto unreserve_out; - } + pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n", + entry->va, entry->va + bo_size, entry); - mem->mapped_to_gpu_memory--; - pr_debug("\t DEC mapping count %d\n", - mem->mapped_to_gpu_memory); - } + unmap_bo_from_gpuvm(mem, entry, ctx.sync); + entry->is_mapped = false; + + mem->mapped_to_gpu_memory--; + pr_debug("\t DEC mapping count %d\n", + mem->mapped_to_gpu_memory); } /* If BO is unmapped from all VMs, unfence it. It can be evicted if @@ -1642,14 +1870,15 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, struct dma_buf *dma_buf, - uint64_t va, void *vm, + uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset) { struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct drm_gem_object *obj; struct amdgpu_bo *bo; - struct amdgpu_vm *avm = (struct amdgpu_vm *)vm; + int ret; if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ @@ -1670,13 +1899,19 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, if (!*mem) return -ENOMEM; + ret = drm_vma_node_allow(&obj->vma_node, drm_priv); + if (ret) { + kfree(mem); + return ret; + } + if (size) *size = amdgpu_bo_size(bo); if (mmap_offset) *mmap_offset = amdgpu_bo_mmap_offset(bo); - INIT_LIST_HEAD(&(*mem)->bo_va_list); + INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); (*mem)->alloc_flags = @@ -1873,7 +2108,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) list_for_each_entry_safe(mem, tmp_mem, &process_info->userptr_inval_list, validate_list.head) { - struct kfd_bo_va_list *bo_va_entry; + struct kfd_mem_attachment *attachment; bo = mem->bo; @@ -1896,13 +2131,12 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) * VM faults if the GPU tries to access the invalid * memory. */ - list_for_each_entry(bo_va_entry, &mem->bo_va_list, bo_list) { - if (!bo_va_entry->is_mapped) + list_for_each_entry(attachment, &mem->attachments, list) { + if (!attachment->is_mapped) continue; - ret = update_gpuvm_pte((struct amdgpu_device *) - bo_va_entry->kgd_dev, - bo_va_entry, &sync); + kfd_mem_dmaunmap_attachment(mem, attachment); + ret = update_gpuvm_pte(mem, attachment, &sync, NULL); if (ret) { pr_err("%s: update PTE failed\n", __func__); /* make sure this gets validated again */ @@ -2083,7 +2317,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) struct amdgpu_bo *bo = mem->bo; uint32_t domain = mem->domain; - struct kfd_bo_va_list *bo_va_entry; + struct kfd_mem_attachment *attachment; total_size += amdgpu_bo_size(bo); @@ -2103,12 +2337,12 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) pr_debug("Memory eviction: Sync BO fence failed. Try again\n"); goto validate_map_fail; } - list_for_each_entry(bo_va_entry, &mem->bo_va_list, - bo_list) { - ret = update_gpuvm_pte((struct amdgpu_device *) - bo_va_entry->kgd_dev, - bo_va_entry, - &sync_obj); + list_for_each_entry(attachment, &mem->attachments, list) { + if (!attachment->is_mapped) + continue; + + kfd_mem_dmaunmap_attachment(mem, attachment); + ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL); if (ret) { pr_debug("Memory eviction: update PTE failed. Try again\n"); goto validate_map_fail; @@ -2135,7 +2369,8 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) */ new_fence = amdgpu_amdkfd_fence_create( process_info->eviction_fence->base.context, - process_info->eviction_fence->mm); + process_info->eviction_fence->mm, + NULL); if (!new_fence) { pr_err("Failed to create eviction fence\n"); ret = -ENOMEM; @@ -2154,7 +2389,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) /* Attach eviction fence to PD / PT BOs */ list_for_each_entry(peer_vm, &process_info->vm_list_head, vm_list_node) { - struct amdgpu_bo *bo = peer_vm->root.base.bo; + struct amdgpu_bo *bo = peer_vm->root.bo; amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true); } @@ -2182,7 +2417,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem return -ENOMEM; mutex_init(&(*mem)->lock); - INIT_LIST_HEAD(&(*mem)->bo_va_list); + INIT_LIST_HEAD(&(*mem)->attachments); (*mem)->bo = amdgpu_bo_ref(gws_bo); (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS; (*mem)->process_info = process_info; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 494b2e1717d5..96b7bb13a2dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1768,6 +1768,15 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); +static struct attribute *amdgpu_vbios_version_attrs[] = { + &dev_attr_vbios_version.attr, + NULL +}; + +const struct attribute_group amdgpu_vbios_version_attr_group = { + .attrs = amdgpu_vbios_version_attrs +}; + /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios * @@ -1787,7 +1796,6 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; - device_remove_file(adev->dev, &dev_attr_vbios_version); } /** @@ -1804,7 +1812,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); - int ret; if (!atom_card_info) return -ENOMEM; @@ -1828,17 +1835,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) if (adev->is_atom_fw) { amdgpu_atomfirmware_scratch_regs_init(adev); amdgpu_atomfirmware_allocate_fb_scratch(adev); + /* cached firmware_flags for further usage */ + adev->mode_info.firmware_flags = + amdgpu_atomfirmware_query_firmware_capability(adev); } else { amdgpu_atombios_scratch_regs_init(adev); amdgpu_atombios_allocate_fb_scratch(adev); } - ret = device_create_file(adev->dev, &dev_attr_vbios_version); - if (ret) { - DRM_ERROR("Failed to create device file for VBIOS version\n"); - return ret; - } - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 60716b35444b..3b5d13189073 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -29,23 +29,59 @@ #include "atombios.h" #include "soc15_hw_ip.h" -bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) +union firmware_info { + struct atom_firmware_info_v3_1 v31; + struct atom_firmware_info_v3_2 v32; + struct atom_firmware_info_v3_3 v33; + struct atom_firmware_info_v3_4 v34; +}; + +/* + * Helper function to query firmware capability + * + * @adev: amdgpu_device pointer + * + * Return firmware_capability in firmwareinfo table on success or 0 if not + */ +uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev) { - int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, - firmwareinfo); - uint16_t data_offset; + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index; + u16 data_offset, size; + union firmware_info *firmware_info; + u8 frev, crev; + u32 fw_cap = 0; - if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, - NULL, NULL, &data_offset)) { - struct atom_firmware_info_v3_1 *firmware_info = - (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + - data_offset); + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); - if (le32_to_cpu(firmware_info->firmware_capability) & - ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) - return true; + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, + index, &size, &frev, &crev, &data_offset)) { + /* support firmware_info 3.1 + */ + if ((frev == 3 && crev >=1) || (frev > 3)) { + firmware_info = (union firmware_info *) + (mode_info->atom_context->bios + data_offset); + fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); + } } - return false; + + return fw_cap; +} + +/* + * Helper function to query gpu virtualizaiton capability + * + * @adev: amdgpu_device pointer + * + * Return true if gpu virtualization is supported or false if not + */ +bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev) +{ + u32 fw_cap; + + fw_cap = adev->mode_info.firmware_flags; + + return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false; } void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) @@ -400,41 +436,36 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) return ecc_default_enabled; } -union firmware_info { - struct atom_firmware_info_v3_1 v31; - struct atom_firmware_info_v3_2 v32; - struct atom_firmware_info_v3_3 v33; - struct atom_firmware_info_v3_4 v34; -}; - /* + * Helper function to query sram ecc capablity + * + * @adev: amdgpu_device pointer + * * Return true if vbios supports sram ecc or false if not */ bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev) { - struct amdgpu_mode_info *mode_info = &adev->mode_info; - int index; - u16 data_offset, size; - union firmware_info *firmware_info; - u8 frev, crev; - bool sram_ecc_supported = false; + u32 fw_cap; - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, - firmwareinfo); + fw_cap = adev->mode_info.firmware_flags; - if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, - index, &size, &frev, &crev, &data_offset)) { - /* support firmware_info 3.1 + */ - if ((frev == 3 && crev >=1) || (frev > 3)) { - firmware_info = (union firmware_info *) - (mode_info->atom_context->bios + data_offset); - sram_ecc_supported = - (le32_to_cpu(firmware_info->v31.firmware_capability) & - ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; - } - } + return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; +} - return sram_ecc_supported; +/* + * Helper function to query dynamic boot config capability + * + * @adev: amdgpu_device pointer + * + * Return true if vbios supports dynamic boot config or false if not + */ +bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev) +{ + u32 fw_cap; + + fw_cap = adev->mode_info.firmware_flags; + + return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false; } union smu_info { @@ -466,10 +497,6 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) adev->pm.current_sclk = adev->clock.default_sclk; adev->pm.current_mclk = adev->clock.default_mclk; - /* not technically a clock, but... */ - adev->mode_info.firmware_flags = - le32_to_cpu(firmware_info->v31.firmware_capability); - ret = 0; } @@ -519,6 +546,21 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) ret = 0; } + /* if asic is Navi+, the rlc reference clock is used for system clock + * from vbios gfx_info table */ + if (adev->asic_type >= CHIP_NAVI10) { + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + gfx_info); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + struct atom_gfx_info_v2_2 *gfx_info = (struct atom_gfx_info_v2_2*) + (mode_info->atom_context->bios + data_offset); + if ((frev == 2) && (crev >= 2)) + spll->reference_freq = le32_to_cpu(gfx_info->rlc_gpu_timer_refclk); + ret = 0; + } + } + return ret; } @@ -584,67 +626,19 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) } /* - * Check if VBIOS supports GDDR6 training data save/restore + * Helper function to query two stage mem training capability + * + * @adev: amdgpu_device pointer + * + * Return true if two stage mem training is supported or false if not */ -static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev) +bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev) { - uint16_t data_offset; - int index; + u32 fw_cap; - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, - firmwareinfo); - if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, - NULL, NULL, &data_offset)) { - struct atom_firmware_info_v3_1 *firmware_info = - (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + - data_offset); + fw_cap = adev->mode_info.firmware_flags; - DRM_DEBUG("atom firmware capability:0x%08x.\n", - le32_to_cpu(firmware_info->firmware_capability)); - - if (le32_to_cpu(firmware_info->firmware_capability) & - ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) - return true; - } - - return false; -} - -int amdgpu_mem_train_support(struct amdgpu_device *adev) -{ - int ret; - uint32_t major, minor, revision, hw_v; - - if (gddr6_mem_train_vbios_support(adev)) { - amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision); - hw_v = HW_REV(major, minor, revision); - /* - * treat 0 revision as a special case since register for MP0 and MMHUB is missing - * for some Navi10 A0, preventing driver from discovering the hwip information since - * none of the functions will be initialized, it should not cause any problems - */ - switch (hw_v) { - case HW_REV(11, 0, 0): - case HW_REV(11, 0, 5): - case HW_REV(11, 0, 7): - case HW_REV(11, 0, 11): - case HW_REV(11, 0, 12): - ret = 1; - break; - default: - DRM_ERROR("memory training vbios supports but psp hw(%08x)" - " doesn't support!\n", hw_v); - ret = -1; - break; - } - } else { - ret = 0; - hw_v = -1; - } - - - DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret); - return ret; + return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false; } int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h index 9f0d4356e8df..1bbbb195015d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h @@ -26,7 +26,8 @@ #define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t)) -bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev); +uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev); +bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev); void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev); int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev); int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, @@ -35,7 +36,8 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev); int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev); bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev); bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev); +bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev); +bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev); int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev); -int amdgpu_mem_train_support(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index b5c766998045..76fe5b71e35d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, spin_unlock(&adev->mm_stats.lock); } -static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, - struct amdgpu_bo *bo) +static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_cs_parser *p = param; struct ttm_operation_ctx ctx = { .interruptible = true, .no_wait_gpu = false, @@ -451,21 +451,6 @@ retry: return r; } -static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) -{ - struct amdgpu_cs_parser *p = param; - int r; - - r = amdgpu_cs_bo_validate(p, bo); - if (r) - return r; - - if (bo->shadow) - r = amdgpu_cs_bo_validate(p, bo->shadow); - - return r; -} - static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, struct list_head *validated) { @@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, lobj->user_pages); } - r = amdgpu_cs_validate(p, bo); + r = amdgpu_cs_bo_validate(p, bo); if (r) return r; @@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bytes_moved_vis = 0; r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, - amdgpu_cs_validate, p); + amdgpu_cs_bo_validate, p); if (r) { DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); goto error_validate; @@ -672,12 +657,12 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) } /** - * cs_parser_fini() - clean parser states + * amdgpu_cs_parser_fini() - clean parser states * @parser: parser structure holding parsing context. * @error: error number * @backoff: indicator to backoff the reservation * - * If error is set than unvalidate buffer, otherwise just free memory + * If error is set then unvalidate buffer, otherwise just free memory * used by parsing context. **/ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, @@ -796,7 +781,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) if (r) return r; - r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); + r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL); if (r) return r; @@ -807,7 +792,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { bo_va = fpriv->csa_va; BUG_ON(!bo_va); - r = amdgpu_vm_bo_update(adev, bo_va, false); + r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); if (r) return r; @@ -826,7 +811,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) if (bo_va == NULL) continue; - r = amdgpu_vm_bo_update(adev, bo_va, false); + r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); if (r) return r; @@ -847,7 +832,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) if (r) return r; - p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo); + p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo); if (amdgpu_vm_debug) { /* Invalidate all BOs to test for userspace bugs */ @@ -1488,7 +1473,7 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, } /** - * amdgpu_cs_wait_all_fence - wait on all fences to signal + * amdgpu_cs_wait_all_fences - wait on all fences to signal * * @adev: amdgpu device * @filp: file private @@ -1639,7 +1624,7 @@ err_free_fences: } /** - * amdgpu_cs_find_bo_va - find bo_va for VM address + * amdgpu_cs_find_mapping - find bo_va for VM address * * @parser: command submission parser context * @addr: VM address diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 6819fe5612d9..e7a010b7ca1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev, return 0; } +#define AMDGPU_RAS_COUNTE_DELAY_MS 3000 + static int amdgpu_ctx_query2(struct amdgpu_device *adev, - struct amdgpu_fpriv *fpriv, uint32_t id, - union drm_amdgpu_ctx_out *out) + struct amdgpu_fpriv *fpriv, uint32_t id, + union drm_amdgpu_ctx_out *out) { + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ctx *ctx; struct amdgpu_ctx_mgr *mgr; @@ -361,6 +364,30 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, if (atomic_read(&ctx->guilty)) out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; + if (adev->ras_enabled && con) { + /* Return the cached values in O(1), + * and schedule delayed work to cache + * new vaues. + */ + int ce_count, ue_count; + + ce_count = atomic_read(&con->ras_ce_count); + ue_count = atomic_read(&con->ras_ue_count); + + if (ce_count != ctx->ras_counter_ce) { + ctx->ras_counter_ce = ce_count; + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; + } + + if (ue_count != ctx->ras_counter_ue) { + ctx->ras_counter_ue = ue_count; + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; + } + + schedule_delayed_work(&con->ras_counte_delay_work, + msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); + } + mutex_unlock(&mgr->lock); return 0; } @@ -635,3 +662,81 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) idr_destroy(&mgr->ctx_handles); mutex_destroy(&mgr->lock); } + +static void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, + struct amdgpu_ctx_entity *centity, ktime_t *total, ktime_t *max) +{ + ktime_t now, t1; + uint32_t i; + + *total = *max = 0; + + now = ktime_get(); + for (i = 0; i < amdgpu_sched_jobs; i++) { + struct dma_fence *fence; + struct drm_sched_fence *s_fence; + + spin_lock(&ctx->ring_lock); + fence = dma_fence_get(centity->fences[i]); + spin_unlock(&ctx->ring_lock); + if (!fence) + continue; + s_fence = to_drm_sched_fence(fence); + if (!dma_fence_is_signaled(&s_fence->scheduled)) { + dma_fence_put(fence); + continue; + } + t1 = s_fence->scheduled.timestamp; + if (!ktime_before(t1, now)) { + dma_fence_put(fence); + continue; + } + if (dma_fence_is_signaled(&s_fence->finished) && + s_fence->finished.timestamp < now) + *total += ktime_sub(s_fence->finished.timestamp, t1); + else + *total += ktime_sub(now, t1); + t1 = ktime_sub(now, t1); + dma_fence_put(fence); + *max = max(t1, *max); + } +} + +ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip, + uint32_t idx, uint64_t *elapsed) +{ + struct idr *idp; + struct amdgpu_ctx *ctx; + uint32_t id; + struct amdgpu_ctx_entity *centity; + ktime_t total = 0, max = 0; + + if (idx >= AMDGPU_MAX_ENTITY_NUM) + return 0; + idp = &mgr->ctx_handles; + mutex_lock(&mgr->lock); + idr_for_each_entry(idp, ctx, id) { + ktime_t ttotal, tmax; + + if (!ctx->entities[hwip][idx]) + continue; + + centity = ctx->entities[hwip][idx]; + amdgpu_ctx_fence_time(ctx, centity, &ttotal, &tmax); + + /* Harmonic mean approximation diverges for very small + * values. If ratio < 0.01% ignore + */ + if (AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(tmax, ttotal)) + continue; + + total = ktime_add(total, ttotal); + max = ktime_after(tmax, max) ? tmax : max; + } + + mutex_unlock(&mgr->lock); + if (elapsed) + *elapsed = max; + + return total; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index f54e10314661..14db16bc3322 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -30,6 +30,7 @@ struct drm_file; struct amdgpu_fpriv; #define AMDGPU_MAX_ENTITY_NUM 4 +#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total)) struct amdgpu_ctx_entity { uint64_t sequence; @@ -87,5 +88,6 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout); void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); - +ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip, + uint32_t idx, uint64_t *elapsed); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index bcaf271b39bf..536005bff24a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -990,7 +990,7 @@ err: } /** - * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF + * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF * * @f: open file handle * @buf: User buffer to write data from @@ -1041,7 +1041,7 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu /** - * amdgpu_debugfs_regs_gfxoff_status - read gfxoff status + * amdgpu_debugfs_gfxoff_read - read gfxoff status * * @f: open file handle * @buf: User buffer to store read data in @@ -1304,11 +1304,11 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) seq_printf(m, "pid:%d\tProcess:%s ----------\n", vm->task_info.pid, vm->task_info.process_name); - r = amdgpu_bo_reserve(vm->root.base.bo, true); + r = amdgpu_bo_reserve(vm->root.bo, true); if (r) break; amdgpu_debugfs_vm_bo_info(vm, m); - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); } mutex_unlock(&dev->filelist_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 57ec108b5972..130a9adf09ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -71,6 +71,8 @@ #include #include +#include + MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); @@ -82,6 +84,7 @@ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin"); #define AMDGPU_RESUME_MS 2000 @@ -119,6 +122,8 @@ const char *amdgpu_asic_name[] = { "NAVY_FLOUNDER", "VANGOGH", "DIMGREY_CAVEFISH", + "BEIGE_GOBY", + "YELLOW_CARP", "LAST", }; @@ -262,6 +267,21 @@ bool amdgpu_device_supports_baco(struct drm_device *dev) return amdgpu_asic_supports_baco(adev); } +/** + * amdgpu_device_supports_smart_shift - Is the device dGPU with + * smart shift support + * + * @dev: drm_device pointer + * + * Returns true if the device is a dGPU with Smart Shift support, + * otherwise returns false. + */ +bool amdgpu_device_supports_smart_shift(struct drm_device *dev) +{ + return (amdgpu_device_supports_boco(dev) && + amdgpu_acpi_is_power_shift_control_supported()); +} + /* * VRAM access helper functions */ @@ -281,7 +301,10 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, unsigned long flags; uint32_t hi = ~0; uint64_t last; + int idx; + if (!drm_dev_enter(&adev->ddev, &idx)) + return; #ifdef CONFIG_64BIT last = min(pos + size, adev->gmc.visible_vram_size); @@ -292,15 +315,15 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, if (write) { memcpy_toio(addr, buf, count); mb(); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_device_flush_hdp(adev, NULL); } else { - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_device_invalidate_hdp(adev, NULL); mb(); memcpy_fromio(buf, addr, count); } if (count == size) - return; + goto exit; pos += count; buf += count / 4; @@ -323,6 +346,11 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, *buf++ = RREG32_NO_KIQ(mmMM_DATA); } spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); + +#ifdef CONFIG_64BIT +exit: +#endif + drm_dev_exit(idx); } /* @@ -332,7 +360,7 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, /* Check if hw access should be skipped because of hotplug or device error */ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) { - if (adev->in_pci_err_recovery) + if (adev->no_hw_access) return true; #ifdef CONFIG_LOCKDEP @@ -490,7 +518,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->is_rlcg_access_range) { if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0); + return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0); } else { writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); } @@ -1820,6 +1848,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: default: return 0; case CHIP_VEGA10: @@ -1857,6 +1886,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) case CHIP_VANGOGH: chip_name = "vangogh"; break; + case CHIP_YELLOW_CARP: + chip_name = "yellow_carp"; + break; } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); @@ -2033,9 +2065,13 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: if (adev->asic_type == CHIP_VANGOGH) adev->family = AMDGPU_FAMILY_VGH; + else if (adev->asic_type == CHIP_YELLOW_CARP) + adev->family = AMDGPU_FAMILY_YC; else adev->family = AMDGPU_FAMILY_NV; @@ -2571,34 +2607,26 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) return 0; } -/** - * amdgpu_device_ip_fini - run fini for hardware IPs - * - * @adev: amdgpu_device pointer - * - * Main teardown pass for hardware IPs. The list of all the hardware - * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks - * are run. hw_fini tears down the hardware associated with each IP - * and sw_fini tears down any software state associated with each IP. - * Returns 0 on success, negative error code on failure. - */ -static int amdgpu_device_ip_fini(struct amdgpu_device *adev) +static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) { int i, r; - if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) - amdgpu_virt_release_ras_err_handler_data(adev); + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].version->funcs->early_fini) + continue; - amdgpu_ras_pre_fini(adev); + r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); + if (r) { + DRM_DEBUG("early_fini of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + } + } - if (adev->gmc.xgmi.num_physical_nodes > 1) - amdgpu_xgmi_remove_device(adev); + amdgpu_amdkfd_suspend(adev, false); amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); - amdgpu_amdkfd_device_fini(adev); - /* need to disable SMC first */ for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.hw) @@ -2629,6 +2657,33 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = false; } + return 0; +} + +/** + * amdgpu_device_ip_fini - run fini for hardware IPs + * + * @adev: amdgpu_device pointer + * + * Main teardown pass for hardware IPs. The list of all the hardware + * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks + * are run. hw_fini tears down the hardware associated with each IP + * and sw_fini tears down any software state associated with each IP. + * Returns 0 on success, negative error code on failure. + */ +static int amdgpu_device_ip_fini(struct amdgpu_device *adev) +{ + int i, r; + + if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) + amdgpu_virt_release_ras_err_handler_data(adev); + + amdgpu_ras_pre_fini(adev); + + if (adev->gmc.xgmi.num_physical_nodes > 1) + amdgpu_xgmi_remove_device(adev); + + amdgpu_amdkfd_device_fini_sw(adev); for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_blocks[i].status.sw) @@ -2856,7 +2911,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) AMD_IP_BLOCK_TYPE_IH, }; - for (i = 0; i < ARRAY_SIZE(ip_order); i++) { + for (i = 0; i < adev->num_ip_blocks; i++) { int j; struct amdgpu_ip_block *block; @@ -3034,7 +3089,7 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) { if (amdgpu_sriov_vf(adev)) { if (adev->is_atom_fw) { - if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) + if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; } else { if (amdgpu_atombios_has_gpu_virtualization_table(adev)) @@ -3097,7 +3152,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: #endif return amdgpu_dc != 0; #endif @@ -3181,8 +3238,8 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) int ret = 0; /* - * By default timeout for non compute jobs is 10000. - * And there is no timeout enforced on compute jobs. + * By default timeout for non compute jobs is 10000 + * and 60000 for compute jobs. * In SR-IOV or passthrough mode, timeout for compute * jobs are 60000 by default. */ @@ -3191,10 +3248,8 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) if (amdgpu_sriov_vf(adev)) adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? msecs_to_jiffies(60000) : msecs_to_jiffies(10000); - else if (amdgpu_passthrough(adev)) - adev->compute_timeout = msecs_to_jiffies(60000); else - adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; + adev->compute_timeout = msecs_to_jiffies(60000); if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { while ((timeout_setting = strsep(&input, ",")) && @@ -3251,7 +3306,6 @@ static const struct attribute *amdgpu_dev_attributes[] = { NULL }; - /** * amdgpu_device_init - initialize the driver * @@ -3653,6 +3707,27 @@ failed_unmap: return r; } +static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) +{ + /* Clear all CPU mappings pointing to this device */ + unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); + + /* Unmap all mapped bars - Doorbell, registers and VRAM */ + amdgpu_device_doorbell_fini(adev); + + iounmap(adev->rmmio); + adev->rmmio = NULL; + if (adev->mman.aper_base_kaddr) + iounmap(adev->mman.aper_base_kaddr); + adev->mman.aper_base_kaddr = NULL; + + /* Memory manager related */ + if (!adev->gmc.xgmi.connected_to_cpu) { + arch_phys_wc_del(adev->gmc.vram_mtrr); + arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); + } +} + /** * amdgpu_device_fini - tear down the driver * @@ -3661,15 +3736,13 @@ failed_unmap: * Tear down the driver info (all asics). * Called at driver shutdown. */ -void amdgpu_device_fini(struct amdgpu_device *adev) +void amdgpu_device_fini_hw(struct amdgpu_device *adev) { dev_info(adev->dev, "amdgpu: finishing device.\n"); flush_delayed_work(&adev->delayed_init_work); ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); adev->shutdown = true; - kfree(adev->pci_state); - /* make sure IB test finished before entering exclusive mode * to avoid preemption on IB test * */ @@ -3686,11 +3759,29 @@ void amdgpu_device_fini(struct amdgpu_device *adev) else drm_atomic_helper_shutdown(adev_to_drm(adev)); } - amdgpu_fence_driver_fini(adev); + amdgpu_fence_driver_fini_hw(adev); + if (adev->pm_sysfs_en) amdgpu_pm_sysfs_fini(adev); + if (adev->ucode_sysfs_en) + amdgpu_ucode_sysfs_fini(adev); + sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); + amdgpu_fbdev_fini(adev); + + amdgpu_irq_fini_hw(adev); + + amdgpu_device_ip_fini_early(adev); + + amdgpu_gart_dummy_page_fini(adev); + + amdgpu_device_unmap_mmio(adev); +} + +void amdgpu_device_fini_sw(struct amdgpu_device *adev) +{ amdgpu_device_ip_fini(adev); + amdgpu_fence_driver_fini_sw(adev); release_firmware(adev->firmware.gpu_info_fw); adev->firmware.gpu_info_fw = NULL; adev->accel_working = false; @@ -3712,18 +3803,14 @@ void amdgpu_device_fini(struct amdgpu_device *adev) } if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, NULL, NULL, NULL); - iounmap(adev->rmmio); - adev->rmmio = NULL; - amdgpu_device_doorbell_fini(adev); - if (adev->ucode_sysfs_en) - amdgpu_ucode_sysfs_fini(adev); - - sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); if (IS_ENABLED(CONFIG_PERF_EVENTS)) amdgpu_pmu_fini(adev); if (adev->mman.discovery_bin) amdgpu_discovery_fini(adev); + + kfree(adev->pci_state); + } @@ -3743,12 +3830,15 @@ void amdgpu_device_fini(struct amdgpu_device *adev) int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) { struct amdgpu_device *adev = drm_to_adev(dev); - int r; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; adev->in_suspend = true; + + if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) + DRM_WARN("smart shift update failed\n"); + drm_kms_helper_poll_disable(dev); if (fbcon) @@ -3758,7 +3848,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) amdgpu_ras_suspend(adev); - r = amdgpu_device_ip_suspend_phase1(adev); + amdgpu_device_ip_suspend_phase1(adev); if (!adev->in_s0ix) amdgpu_amdkfd_suspend(adev, adev->in_runpm); @@ -3768,7 +3858,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) amdgpu_fence_driver_suspend(adev); - r = amdgpu_device_ip_suspend_phase2(adev); + amdgpu_device_ip_suspend_phase2(adev); /* evict remaining vram memory * This second call to evict vram is to evict the gart page table * using the CPU. @@ -3858,6 +3948,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) #endif adev->in_suspend = false; + if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) + DRM_WARN("smart shift update failed\n"); + return 0; } @@ -4031,6 +4124,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) { struct dma_fence *fence = NULL, *next = NULL; struct amdgpu_bo *shadow; + struct amdgpu_bo_vm *vmbo; long r = 1, tmo; if (amdgpu_sriov_runtime(adev)) @@ -4040,12 +4134,12 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) dev_info(adev->dev, "recover vram bo from shadow start\n"); mutex_lock(&adev->shadow_list_lock); - list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { - + list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { + shadow = &vmbo->bo; /* No need to recover an evicted BO */ - if (shadow->tbo.mem.mem_type != TTM_PL_TT || - shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || - shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) + if (shadow->tbo.resource->mem_type != TTM_PL_TT || + shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || + shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) continue; r = amdgpu_bo_restore_shadow(shadow, &next); @@ -4634,7 +4728,7 @@ static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) return 0; } -void amdgpu_device_recheck_guilty_jobs( +static void amdgpu_device_recheck_guilty_jobs( struct amdgpu_device *adev, struct list_head *device_list_handle, struct amdgpu_reset_context *reset_context) { @@ -4937,6 +5031,8 @@ skip_hw_reset: amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); } else { dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); + if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) + DRM_WARN("smart shift update failed\n"); } } @@ -5125,7 +5221,8 @@ int amdgpu_device_baco_enter(struct drm_device *dev) if (!amdgpu_device_supports_baco(adev_to_drm(adev))) return -ENOTSUPP; - if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) + if (ras && adev->ras_enabled && + adev->nbio.funcs->enable_doorbell_interrupt) adev->nbio.funcs->enable_doorbell_interrupt(adev, false); return amdgpu_dpm_baco_enter(adev); @@ -5144,7 +5241,8 @@ int amdgpu_device_baco_exit(struct drm_device *dev) if (ret) return ret; - if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) + if (ras && adev->ras_enabled && + adev->nbio.funcs->enable_doorbell_interrupt) adev->nbio.funcs->enable_doorbell_interrupt(adev, true); return 0; @@ -5290,9 +5388,9 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); - adev->in_pci_err_recovery = true; + adev->no_hw_access = true; r = amdgpu_device_pre_asic_reset(adev, &reset_context); - adev->in_pci_err_recovery = false; + adev->no_hw_access = false; if (r) goto out; @@ -5387,4 +5485,31 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev) return true; } +void amdgpu_device_flush_hdp(struct amdgpu_device *adev, + struct amdgpu_ring *ring) +{ +#ifdef CONFIG_X86_64 + if (adev->flags & AMD_IS_APU) + return; +#endif + if (adev->gmc.xgmi.connected_to_cpu) + return; + if (ring && ring->funcs->emit_hdp_flush) + amdgpu_ring_emit_hdp_flush(ring); + else + amdgpu_asic_flush_hdp(adev, ring); +} + +void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, + struct amdgpu_ring *ring) +{ +#ifdef CONFIG_X86_64 + if (adev->flags & AMD_IS_APU) + return; +#endif + if (adev->gmc.xgmi.connected_to_cpu) + return; + + amdgpu_asic_invalidate_hdp(adev, ring); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index e1b6f5891759..43e7b61d1c5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -325,7 +325,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) return 0; } -int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, +int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, int *major, int *minor, int *revision) { struct binary_header *bhdr; @@ -357,7 +357,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, for (j = 0; j < num_ips; j++) { ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); - if (le16_to_cpu(ip->hw_id) == hw_id) { + if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { if (major) *major = ip->major; if (minor) @@ -373,6 +373,14 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, return -EINVAL; } + +int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance, + int *major, int *minor, int *revision) +{ + return amdgpu_discovery_get_ip_version(adev, VCN_HWID, + vcn_instance, major, minor, revision); +} + void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) { struct binary_header *bhdr; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 1b1ae21b1037..48e6b88cfdfe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -30,8 +30,11 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev); int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev); void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev); -int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, +int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, int *major, int *minor, int *revision); + +int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance, + int *major, int *minor, int *revision); int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev); #endif /* __AMDGPU_DISCOVERY__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2a4cd7d377bf..8e5a7ac8c36f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -203,9 +203,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, goto unpin; } - r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, - &work->shared_count, - &work->shared); + r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl, + &work->shared_count, &work->shared); if (unlikely(r != 0)) { DRM_ERROR("failed to get fences for buffer\n"); goto unpin; @@ -1075,12 +1074,9 @@ int amdgpu_display_gem_fb_verify_and_init( /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, mode_cmd->modifier[0])) { - struct drm_format_name_buf format_name; drm_dbg_kms(dev, - "unsupported pixel format %s / modifier 0x%llx\n", - drm_get_format_name(mode_cmd->pixel_format, - &format_name), - mode_cmd->modifier[0]); + "unsupported pixel format %p4cc / modifier 0x%llx\n", + &mode_cmd->pixel_format, mode_cmd->modifier[0]); ret = -EINVAL; goto err; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 37ec59365080..a9475b207510 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -42,52 +42,6 @@ #include #include -/** - * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation - * @obj: GEM BO - * @vma: Virtual memory area - * - * Sets up a userspace mapping of the BO's memory in the given - * virtual memory area. - * - * Returns: - * 0 on success or a negative error code on failure. - */ -int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, - struct vm_area_struct *vma) -{ - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - unsigned asize = amdgpu_bo_size(bo); - int ret; - - if (!vma->vm_file) - return -ENODEV; - - if (adev == NULL) - return -ENODEV; - - /* Check for valid size. */ - if (asize < vma->vm_end - vma->vm_start) - return -EINVAL; - - if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || - (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { - return -EPERM; - } - vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; - - /* prime mmap does not need to check access, so allow here */ - ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); - if (ret) - return ret; - - ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); - drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); - - return ret; -} - static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -95,10 +49,10 @@ __dma_resv_make_exclusive(struct dma_resv *obj) unsigned int count; int r; - if (!dma_resv_get_list(obj)) /* no shared fences to convert */ + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ return 0; - r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences); + r = dma_resv_get_fences(obj, NULL, &count, &fences); if (r) return r; @@ -284,12 +238,12 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, if (r) return ERR_PTR(r); - } else if (!(amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type) & + } else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) & AMDGPU_GEM_DOMAIN_GTT)) { return ERR_PTR(-EBUSY); } - switch (bo->tbo.mem.mem_type) { + switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: sgt = drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, @@ -303,8 +257,9 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, break; case TTM_PL_VRAM: - r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, 0, - bo->tbo.base.size, attach->dev, dir, &sgt); + r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0, + bo->tbo.base.size, attach->dev, + dir, &sgt); if (r) return ERR_PTR(r); break; @@ -494,7 +449,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) struct amdgpu_vm_bo_base *bo_base; int r; - if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM) + if (bo->tbo.resource->mem_type == TTM_PL_SYSTEM) return; r = ttm_bo_validate(&bo->tbo, &placement, &ctx); @@ -505,7 +460,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; + struct dma_resv *resv = vm->root.bo->tbo.base.resv; if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index 39b5b9616fd8..3e93b9b407a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -31,8 +31,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); -int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, - struct vm_area_struct *vma); extern const struct dma_buf_ops amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f93883db2b46..6f30c525caac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -42,7 +43,7 @@ #include "amdgpu_irq.h" #include "amdgpu_dma_buf.h" #include "amdgpu_sched.h" - +#include "amdgpu_fdinfo.h" #include "amdgpu_amdkfd.h" #include "amdgpu_ras.h" @@ -94,9 +95,10 @@ * - 3.39.0 - DMABUF implicit sync does a full pipeline sync * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ * - 3.41.0 - Add video codec query + * - 3.42.0 - Add 16bpc fixed point display support */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 41 +#define KMS_DRIVER_MINOR 42 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit; @@ -171,6 +173,7 @@ int amdgpu_tmz = -1; /* auto */ uint amdgpu_freesync_vid_mode; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; +int amdgpu_smartshift_bias; static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); @@ -287,9 +290,9 @@ module_param_named(msi, amdgpu_msi, int, 0444); * for SDMA and Video. * * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) - * jobs is 10000. And there is no timeout enforced on compute jobs. + * jobs is 10000. The timeout for compute is 60000. */ -MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " +MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " "for passthrough or sriov, 10000 for all jobs." " 0: keep default value. negative: infinity timeout), " "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " @@ -640,7 +643,8 @@ module_param_named(mes, amdgpu_mes, int, 0444); /** * DOC: noretry (int) - * Disable retry faults in the GPU memory controller. + * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that + * do not support per-process XNACK this also disables retry page faults. * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) */ MODULE_PARM_DESC(noretry, @@ -833,8 +837,23 @@ module_param_named(tmz, amdgpu_tmz, int, 0444); /** * DOC: freesync_video (uint) - * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience - * when setting a freesync supported mode for which full modeset is not needed. + * Enable the optimization to adjust front porch timing to achieve seamless + * mode change experience when setting a freesync supported mode for which full + * modeset is not needed. + * + * The Display Core will add a set of modes derived from the base FreeSync + * video mode into the corresponding connector's mode list based on commonly + * used refresh rates and VRR range of the connected display, when users enable + * this feature. From the userspace perspective, they can see a seamless mode + * change experience when the change between different refresh rates under the + * same resolution. Additionally, userspace applications such as Video playback + * can read this modeset list and change the refresh rate based on the video + * frame rate. Finally, the userspace can also derive an appropriate mode for a + * particular refresh rate based on the FreeSync Mode and add it to the + * connector's mode list. + * + * Note: This is an experimental feature. + * * The default value: 0 (off). */ MODULE_PARM_DESC( @@ -1185,6 +1204,7 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, {0, 0, 0} }; @@ -1258,7 +1278,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, #endif /* Get rid of things like offb */ - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); if (ret) return ret; @@ -1310,14 +1330,16 @@ amdgpu_pci_remove(struct pci_dev *pdev) { struct drm_device *dev = pci_get_drvdata(pdev); -#ifdef MODULE - if (THIS_MODULE->state != MODULE_STATE_GOING) -#endif - DRM_ERROR("Hotplug removal is not supported\n"); drm_dev_unplug(dev); amdgpu_driver_unload_kms(dev); + + /* + * Flush any in flight DMA operations from device. + * Clear the Bus Master Enable bit and then wait on the PCIe Device + * StatusTransactions Pending bit. + */ pci_disable_device(pdev); - pci_set_drvdata(pdev, NULL); + pci_wait_for_pending_transaction(pdev); } static void @@ -1552,6 +1574,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) if (!adev->runpm) return -EINVAL; + /* Avoids registers access if device is physically gone */ + if (!pci_device_is_present(adev->pdev)) + adev->no_hw_access = true; + if (amdgpu_device_supports_px(drm_dev)) { drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; @@ -1597,17 +1623,15 @@ static int amdgpu_pmops_runtime_idle(struct device *dev) if (amdgpu_device_has_dc_support(adev)) { struct drm_crtc *crtc; - drm_modeset_lock_all(drm_dev); - drm_for_each_crtc(crtc, drm_dev) { - if (crtc->state->active) { + drm_modeset_lock(&crtc->mutex, NULL); + if (crtc->state->active) ret = -EBUSY; + drm_modeset_unlock(&crtc->mutex); + if (ret < 0) break; - } } - drm_modeset_unlock_all(drm_dev); - } else { struct drm_connector *list_connector; struct drm_connector_list_iter iter; @@ -1688,12 +1712,15 @@ static const struct file_operations amdgpu_driver_kms_fops = { .flush = amdgpu_flush, .release = drm_release, .unlocked_ioctl = amdgpu_drm_ioctl, - .mmap = amdgpu_mmap, + .mmap = drm_gem_mmap, .poll = drm_poll, .read = drm_read, #ifdef CONFIG_COMPAT .compat_ioctl = amdgpu_kms_compat_ioctl, #endif +#ifdef CONFIG_PROC_FS + .show_fdinfo = amdgpu_show_fdinfo +#endif }; int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) @@ -1747,11 +1774,12 @@ static const struct drm_driver amdgpu_kms_driver = { .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, .fops = &amdgpu_driver_kms_fops, + .release = &amdgpu_driver_release_kms, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = amdgpu_gem_prime_import, - .gem_prime_mmap = amdgpu_gem_prime_mmap, + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, @@ -1768,6 +1796,18 @@ static struct pci_error_handlers amdgpu_pci_err_handler = { .resume = amdgpu_pci_resume, }; +extern const struct attribute_group amdgpu_vram_mgr_attr_group; +extern const struct attribute_group amdgpu_gtt_mgr_attr_group; +extern const struct attribute_group amdgpu_vbios_version_attr_group; + +static const struct attribute_group *amdgpu_sysfs_groups[] = { + &amdgpu_vram_mgr_attr_group, + &amdgpu_gtt_mgr_attr_group, + &amdgpu_vbios_version_attr_group, + NULL, +}; + + static struct pci_driver amdgpu_kms_pci_driver = { .name = DRIVER_NAME, .id_table = pciidlist, @@ -1776,6 +1816,7 @@ static struct pci_driver amdgpu_kms_pci_driver = { .shutdown = amdgpu_pci_shutdown, .driver.pm = &amdgpu_pm_ops, .err_handler = &amdgpu_pci_err_handler, + .dev_groups = amdgpu_sysfs_groups, }; static int __init amdgpu_init(void) @@ -1797,6 +1838,7 @@ static int __init amdgpu_init(void) DRM_INFO("amdgpu kernel modesetting enabled.\n"); amdgpu_register_atpx_handler(); + amdgpu_acpi_detect(); /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ amdgpu_amdkfd_init(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c new file mode 100644 index 000000000000..d94c5419ec25 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: MIT +/* Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: David Nieto + * Roy Sun + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "amdgpu.h" +#include "amdgpu_vm.h" +#include "amdgpu_gem.h" +#include "amdgpu_ctx.h" +#include "amdgpu_fdinfo.h" + + +static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = { + [AMDGPU_HW_IP_GFX] = "gfx", + [AMDGPU_HW_IP_COMPUTE] = "compute", + [AMDGPU_HW_IP_DMA] = "dma", + [AMDGPU_HW_IP_UVD] = "dec", + [AMDGPU_HW_IP_VCE] = "enc", + [AMDGPU_HW_IP_UVD_ENC] = "enc_1", + [AMDGPU_HW_IP_VCN_DEC] = "dec", + [AMDGPU_HW_IP_VCN_ENC] = "enc", + [AMDGPU_HW_IP_VCN_JPEG] = "jpeg", +}; + +void amdgpu_show_fdinfo(struct seq_file *m, struct file *f) +{ + struct amdgpu_fpriv *fpriv; + uint32_t bus, dev, fn, i, domain; + uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0; + struct drm_file *file = f->private_data; + struct amdgpu_device *adev = drm_to_adev(file->minor->dev); + int ret; + + ret = amdgpu_file_to_fpriv(f, &fpriv); + if (ret) + return; + bus = adev->pdev->bus->number; + domain = pci_domain_nr(adev->pdev->bus); + dev = PCI_SLOT(adev->pdev->devfn); + fn = PCI_FUNC(adev->pdev->devfn); + + ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false); + if (ret) { + DRM_ERROR("Fail to reserve bo\n"); + return; + } + amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, >t_mem, &cpu_mem); + amdgpu_bo_unreserve(fpriv->vm.root.bo); + seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus, + dev, fn, fpriv->vm.pasid); + seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL); + seq_printf(m, "gtt mem:\t%llu kB\n", gtt_mem/1024UL); + seq_printf(m, "cpu mem:\t%llu kB\n", cpu_mem/1024UL); + for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { + uint32_t count = amdgpu_ctx_num_entities[i]; + int idx = 0; + uint64_t total = 0, min = 0; + uint32_t perc, frac; + + for (idx = 0; idx < count; idx++) { + total = amdgpu_ctx_mgr_fence_usage(&fpriv->ctx_mgr, + i, idx, &min); + if ((total == 0) || (min == 0)) + continue; + + perc = div64_u64(10000 * total, min); + frac = perc % 100; + + seq_printf(m, "%s%d:\t%d.%d%%\n", + amdgpu_ip_name[i], + idx, perc/100, frac); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h new file mode 100644 index 000000000000..41a4c7056729 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: MIT + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: David Nieto + * Roy Sun + */ +#ifndef __AMDGPU_SMI_H__ +#define __AMDGPU_SMI_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include "amdgpu_sync.h" +#include "amdgpu_ring.h" +#include "amdgpu_ids.h" + +uint32_t amdgpu_get_ip_count(struct amdgpu_device *adev, int id); +void amdgpu_show_fdinfo(struct seq_file *m, struct file *f); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 47ea46859618..72d9b92b1754 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -36,6 +36,7 @@ #include #include +#include #include "amdgpu.h" #include "amdgpu_trace.h" @@ -434,6 +435,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, * * @ring: ring to init the fence driver on * @num_hw_submission: number of entries on the hardware queue + * @sched_score: optional score atomic shared with other schedulers * * Init the fence driver for the requested ring (all asics). * Helper function for amdgpu_fence_driver_init(). @@ -523,10 +525,9 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev) * * Tear down the fence driver for all possible rings (all asics). */ -void amdgpu_fence_driver_fini(struct amdgpu_device *adev) +void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev) { - unsigned i, j; - int r; + int i, r; for (i = 0; i < AMDGPU_MAX_RINGS; i++) { struct amdgpu_ring *ring = adev->rings[i]; @@ -535,16 +536,33 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) continue; if (!ring->no_scheduler) drm_sched_fini(&ring->sched); - r = amdgpu_fence_wait_empty(ring); - if (r) { - /* no need to trigger GPU reset as we are unloading */ + /* You can't wait for HW to signal if it's gone */ + if (!drm_dev_is_unplugged(&adev->ddev)) + r = amdgpu_fence_wait_empty(ring); + else + r = -ENODEV; + /* no need to trigger GPU reset as we are unloading */ + if (r) amdgpu_fence_driver_force_completion(ring); - } + if (ring->fence_drv.irq_src) amdgpu_irq_put(adev, ring->fence_drv.irq_src, ring->fence_drv.irq_type); del_timer_sync(&ring->fence_drv.fallback_timer); + } +} + +void amdgpu_fence_driver_fini_sw(struct amdgpu_device *adev) +{ + unsigned int i, j; + + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->fence_drv.initialized) + continue; + for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) dma_fence_put(ring->fence_drv.fences[j]); kfree(ring->fence_drv.fences); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c index 8d1ad294cb02..2ca3c329de6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c @@ -121,6 +121,9 @@ static const struct file_operations amdgpu_fw_attestation_debugfs_ops = { static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev) { + if (adev->flags & AMD_IS_APU) + return 0; + if (adev->asic_type >= CHIP_SIENNA_CICHLID) return 1; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index c5a9a4fb10d2..b36405170ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -60,7 +60,7 @@ */ /** - * amdgpu_dummy_page_init - init dummy page used by the driver + * amdgpu_gart_dummy_page_init - init dummy page used by the driver * * @adev: amdgpu_device pointer * @@ -86,13 +86,13 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) } /** - * amdgpu_dummy_page_fini - free dummy page used by the driver + * amdgpu_gart_dummy_page_fini - free dummy page used by the driver * * @adev: amdgpu_device pointer * * Frees the dummy page used by the driver (all asics). */ -static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) +void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) { if (!adev->dummy_page_addr) return; @@ -250,7 +250,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, } } mb(); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_device_flush_hdp(adev, NULL); for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); @@ -300,7 +300,6 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, * @adev: amdgpu_device pointer * @offset: offset into the GPU's gart aperture * @pages: number of pages to bind - * @pagelist: pages to bind * @dma_addr: DMA addresses of pages * @flags: page table entry flags * @@ -309,11 +308,9 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, * Returns 0 for success, -EINVAL for failure. */ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, - int pages, struct page **pagelist, dma_addr_t *dma_addr, + int pages, dma_addr_t *dma_addr, uint64_t flags) { - int r, i; - if (!adev->gart.ready) { WARN(1, "trying to bind memory to uninitialized GART !\n"); return -EINVAL; @@ -322,16 +319,26 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, if (!adev->gart.ptr) return 0; - r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, - adev->gart.ptr); - if (r) - return r; + return amdgpu_gart_map(adev, offset, pages, dma_addr, flags, + adev->gart.ptr); +} + +/** + * amdgpu_gart_invalidate_tlb - invalidate gart TLB + * + * @adev: amdgpu device driver pointer + * + * Invalidate gart TLB which can be use as a way to flush gart changes + * + */ +void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) +{ + int i; mb(); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_device_flush_hdp(adev, NULL); for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); - return 0; } /** @@ -365,15 +372,3 @@ int amdgpu_gart_init(struct amdgpu_device *adev) return 0; } - -/** - * amdgpu_gart_fini - tear down the driver info for managing the gart - * - * @adev: amdgpu_device pointer - * - * Tear down the gart driver info and free the dummy page (all asics). - */ -void amdgpu_gart_fini(struct amdgpu_device *adev) -{ - amdgpu_gart_dummy_page_fini(adev); -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index a25fe97b0196..78895413cf9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -57,14 +57,13 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev); -void amdgpu_gart_fini(struct amdgpu_device *adev); +void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev); int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int pages); int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags, void *dst); int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, - int pages, struct page **pagelist, - dma_addr_t *dma_addr, uint64_t flags); - + int pages, dma_addr_t *dma_addr, uint64_t flags); +void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 311bcdc59eda..b3404c43a911 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -32,6 +32,7 @@ #include #include +#include #include #include "amdgpu.h" @@ -41,6 +42,46 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; +static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vmf->vma->vm_private_data; + struct drm_device *ddev = bo->base.dev; + vm_fault_t ret; + int idx; + + ret = ttm_bo_vm_reserve(bo, vmf); + if (ret) + return ret; + + if (drm_dev_enter(ddev, &idx)) { + ret = amdgpu_bo_fault_reserve_notify(bo); + if (ret) { + drm_dev_exit(idx); + goto unlock; + } + + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT, 1); + + drm_dev_exit(idx); + } else { + ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); + } + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) + return ret; + +unlock: + dma_resv_unlock(bo->base.resv); + return ret; +} + +static const struct vm_operations_struct amdgpu_gem_vm_ops = { + .fault = amdgpu_gem_fault, + .open = ttm_bo_vm_open, + .close = ttm_bo_vm_close, + .access = ttm_bo_vm_access +}; + static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); @@ -129,7 +170,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, return -EPERM; if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && - abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) + abo->tbo.base.resv != vm->root.bo->tbo.base.resv) return -EPERM; r = amdgpu_bo_reserve(abo, false); @@ -185,7 +226,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, if (!amdgpu_vm_ready(vm)) goto out_unlock; - fence = dma_resv_get_excl(bo->tbo.base.resv); + fence = dma_resv_excl_fence(bo->tbo.base.resv); if (fence) { amdgpu_bo_fence(bo, fence, true); fence = NULL; @@ -205,6 +246,18 @@ out_unlock: ttm_eu_backoff_reservation(&ticket, &list); } +static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) + return -EPERM; + if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) + return -EPERM; + + return drm_gem_ttm_mmap(obj, vma); +} + static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, @@ -212,6 +265,8 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .export = amdgpu_gem_prime_export, .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, + .mmap = amdgpu_gem_object_mmap, + .vm_ops = &amdgpu_gem_vm_ops, }; /* @@ -265,11 +320,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, } if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { - r = amdgpu_bo_reserve(vm->root.base.bo, false); + r = amdgpu_bo_reserve(vm->root.bo, false); if (r) return r; - resv = vm->root.base.bo->tbo.base.resv; + resv = vm->root.bo->tbo.base.resv; } initial_domain = (u32)(0xffffffff & args->in.domains); @@ -298,9 +353,9 @@ retry: if (!r) { struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); - abo->parent = amdgpu_bo_ref(vm->root.base.bo); + abo->parent = amdgpu_bo_ref(vm->root.bo); } - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); } if (r) return r; @@ -471,8 +526,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); - ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, - timeout); + ret = dma_resv_wait_timeout(robj->tbo.base.resv, true, true, timeout); /* ret == 0 means not signaled, * ret > 0 means signaled @@ -558,7 +612,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, if (operation == AMDGPU_VA_OP_MAP || operation == AMDGPU_VA_OP_REPLACE) { - r = amdgpu_vm_bo_update(adev, bo_va, false); + r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); if (r) goto error; } @@ -766,7 +820,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, void __user *out = u64_to_user_ptr(args->value); info.bo_size = robj->tbo.base.size; - info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; + info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; info.domains = robj->preferred_domains; info.domain_flags = robj->flags; amdgpu_bo_unreserve(robj); @@ -787,7 +841,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, } for (base = robj->vm_bo; base; base = base->next) if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), - amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { + amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { r = -EINVAL; amdgpu_bo_unreserve(robj); goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 95d4f43a03df..a0be0772c8b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -607,7 +607,6 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) struct ras_ih_if ih_info = { .cb = amdgpu_gfx_process_ras_data_cb, }; - struct ras_query_if info = { 0 }; if (!adev->gfx.ras_if) { adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); @@ -625,12 +624,8 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) goto free; if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) { - if (adev->gmc.xgmi.connected_to_cpu) { - info.head = *adev->gfx.ras_if; - amdgpu_ras_query_error_status(adev, &info); - } else { + if (!amdgpu_persistent_edc_harvesting_supported(adev)) amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX); - } r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h index 66ebc2e3b2ad..beabab515836 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h @@ -34,6 +34,7 @@ struct amdgpu_gfxhub_funcs { void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value); void (*init)(struct amdgpu_device *adev); int (*get_xgmi_info)(struct amdgpu_device *adev); + void (*utcl2_harvest)(struct amdgpu_device *adev); }; struct amdgpu_gfxhub { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index c39ed9eb0987..0174f7817ce2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -31,6 +31,8 @@ #include "amdgpu_ras.h" #include "amdgpu_xgmi.h" +#include + /** * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 * @@ -99,7 +101,7 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - switch (bo->tbo.mem.mem_type) { + switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: *addr = bo->tbo.ttm->dma_address[0]; break; @@ -110,7 +112,7 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, *addr = 0; break; } - *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); + *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); amdgpu_gmc_get_vm_pde(adev, level, addr, flags); } @@ -151,6 +153,10 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, { void __iomem *ptr = (void *)cpu_pt_addr; uint64_t value; + int idx; + + if (!drm_dev_enter(&adev->ddev, &idx)) + return 0; /* * The following is for PTE only. GART does not have PDEs. @@ -158,6 +164,9 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, value = addr & 0x0000FFFFFFFFF000ULL; value |= flags; writeq(value, ptr + (gpu_page_idx * 8)); + + drm_dev_exit(idx); + return 0; } @@ -332,6 +341,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) mc->agp_size >> 20, mc->agp_start, mc->agp_end); } +/** + * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid + * + * @addr: 48 bit physical address, page aligned (36 significant bits) + * @pasid: 16 bit process address space identifier + */ +static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) +{ + return addr << 4 | pasid; +} + /** * amdgpu_gmc_filter_faults - filter VM faults * @@ -348,8 +368,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, uint16_t pasid, uint64_t timestamp) { struct amdgpu_gmc *gmc = &adev->gmc; - - uint64_t stamp, key = addr << 4 | pasid; + uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); struct amdgpu_gmc_fault *fault; uint32_t hash; @@ -365,7 +384,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, while (fault->timestamp >= stamp) { uint64_t tmp; - if (fault->key == key) + if (atomic64_read(&fault->key) == key) return true; tmp = fault->timestamp; @@ -378,7 +397,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, /* Add the fault to the ring */ fault = &gmc->fault_ring[gmc->last_fault]; - fault->key = key; + atomic64_set(&fault->key, key); fault->timestamp = timestamp; /* And update the hash */ @@ -387,6 +406,36 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, return false; } +/** + * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter + * + * @adev: amdgpu device structure + * @addr: address of the VM fault + * @pasid: PASID of the process causing the fault + * + * Remove the address from fault filter, then future vm fault on this address + * will pass to retry fault handler to recover. + */ +void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, + uint16_t pasid) +{ + struct amdgpu_gmc *gmc = &adev->gmc; + uint64_t key = amdgpu_gmc_fault_key(addr, pasid); + struct amdgpu_gmc_fault *fault; + uint32_t hash; + uint64_t tmp; + + hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); + fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; + do { + if (atomic64_cmpxchg(&fault->key, key, 0) == key) + break; + + tmp = fault->timestamp; + fault = &gmc->fault_ring[fault->next]; + } while (fault->timestamp < tmp); +} + int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) { int r; @@ -415,6 +464,13 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) return r; } + if (adev->hdp.ras_funcs && + adev->hdp.ras_funcs->ras_late_init) { + r = adev->hdp.ras_funcs->ras_late_init(adev); + if (r) + return r; + } + return 0; } @@ -426,11 +482,15 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) if (adev->mmhub.ras_funcs && adev->mmhub.ras_funcs->ras_fini) - amdgpu_mmhub_ras_fini(adev); + adev->mmhub.ras_funcs->ras_fini(adev); if (adev->gmc.xgmi.ras_funcs && adev->gmc.xgmi.ras_funcs->ras_fini) adev->gmc.xgmi.ras_funcs->ras_fini(adev); + + if (adev->hdp.ras_funcs && + adev->hdp.ras_funcs->ras_fini) + adev->hdp.ras_funcs->ras_fini(adev); } /* @@ -477,7 +537,7 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) } /** - * amdgpu_tmz_set -- check and set if a device supports TMZ + * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ * @adev: amdgpu_device pointer * * Check and set if an the device @adev supports Trusted Memory @@ -523,7 +583,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) } /** - * amdgpu_noretry_set -- set per asic noretry defaults + * amdgpu_gmc_noretry_set -- set per asic noretry defaults * @adev: amdgpu_device pointer * * Set a per asic default for the no-retry parameter. @@ -578,13 +638,18 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, for (i = 0; i < 16; i++) { reg = hub->vm_context0_cntl + hub->ctx_distance * i; - tmp = RREG32(reg); + tmp = (hub_type == AMDGPU_GFXHUB_0) ? + RREG32_SOC15_IP(GC, reg) : + RREG32_SOC15_IP(MMHUB, reg); + if (enable) tmp |= hub->vm_cntx_cntl_vm_fault; else tmp &= ~hub->vm_cntx_cntl_vm_fault; - WREG32(reg, tmp); + (hub_type == AMDGPU_GFXHUB_0) ? + WREG32_SOC15_IP(GC, reg, tmp) : + WREG32_SOC15_IP(MMHUB, reg, tmp); } } @@ -720,3 +785,22 @@ uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo { return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; } + +void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev) +{ + /* Some ASICs need to reserve a region of video memory to avoid access + * from driver */ + adev->mman.stolen_reserved_offset = 0; + adev->mman.stolen_reserved_size = 0; + + switch (adev->asic_type) { + case CHIP_YELLOW_CARP: + if (amdgpu_discovery == 0) { + adev->mman.stolen_reserved_offset = 0x1ffb0000; + adev->mman.stolen_reserved_size = 64 * PAGE_SIZE; + } + break; + default: + break; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 9d11c02a3938..e55201134a01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -66,9 +66,9 @@ struct firmware; * GMC page fault information */ struct amdgpu_gmc_fault { - uint64_t timestamp; + uint64_t timestamp:48; uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; - uint64_t key:52; + atomic64_t key; }; /* @@ -318,6 +318,8 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, uint16_t pasid, uint64_t timestamp); +void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, + uint16_t pasid); int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); @@ -330,6 +332,7 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, bool enable); void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); +void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev); void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 540c01052b21..ec96e0b26b11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -22,17 +22,26 @@ * Authors: Christian König */ +#include + #include "amdgpu.h" -static inline struct amdgpu_gtt_mgr *to_gtt_mgr(struct ttm_resource_manager *man) +struct amdgpu_gtt_node { + struct ttm_buffer_object *tbo; + struct ttm_range_mgr_node base; +}; + +static inline struct amdgpu_gtt_mgr * +to_gtt_mgr(struct ttm_resource_manager *man) { return container_of(man, struct amdgpu_gtt_mgr, manager); } -struct amdgpu_gtt_node { - struct drm_mm_node node; - struct ttm_buffer_object *tbo; -}; +static inline struct amdgpu_gtt_node * +to_amdgpu_gtt_node(struct ttm_resource *res) +{ + return container_of(res, struct amdgpu_gtt_node, base.base); +} /** * DOC: mem_info_gtt_total @@ -43,12 +52,14 @@ struct amdgpu_gtt_node { * the GTT block, in bytes */ static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, + char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); + struct ttm_resource_manager *man; + man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); return sysfs_emit(buf, "%llu\n", man->size * PAGE_SIZE); } @@ -61,12 +72,14 @@ static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev, * size of the GTT block, in bytes */ static ssize_t amdgpu_mem_info_gtt_used_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, + char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); + struct ttm_resource_manager *man; + man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); return sysfs_emit(buf, "%llu\n", amdgpu_gtt_mgr_usage(man)); } @@ -75,90 +88,28 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO, static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO, amdgpu_mem_info_gtt_used_show, NULL); -static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func; -/** - * amdgpu_gtt_mgr_init - init GTT manager and DRM MM - * - * @adev: amdgpu_device pointer - * @gtt_size: maximum size of GTT - * - * Allocate and initialize the GTT manager. - */ -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) -{ - struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; - struct ttm_resource_manager *man = &mgr->manager; - uint64_t start, size; - int ret; +static struct attribute *amdgpu_gtt_mgr_attributes[] = { + &dev_attr_mem_info_gtt_total.attr, + &dev_attr_mem_info_gtt_used.attr, + NULL +}; - man->use_tt = true; - man->func = &amdgpu_gtt_mgr_func; - - ttm_resource_manager_init(man, gtt_size >> PAGE_SHIFT); - - start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; - drm_mm_init(&mgr->mm, start, size); - spin_lock_init(&mgr->lock); - atomic64_set(&mgr->available, gtt_size >> PAGE_SHIFT); - - ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total); - if (ret) { - DRM_ERROR("Failed to create device file mem_info_gtt_total\n"); - return ret; - } - ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used); - if (ret) { - DRM_ERROR("Failed to create device file mem_info_gtt_used\n"); - return ret; - } - - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); - ttm_resource_manager_set_used(man, true); - return 0; -} - -/** - * amdgpu_gtt_mgr_fini - free and destroy GTT manager - * - * @adev: amdgpu_device pointer - * - * Destroy and free the GTT manager, returns -EBUSY if ranges are still - * allocated inside it. - */ -void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) -{ - struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - - ttm_resource_manager_set_used(man, false); - - ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - if (ret) - return; - - spin_lock(&mgr->lock); - drm_mm_takedown(&mgr->mm); - spin_unlock(&mgr->lock); - - device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total); - device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used); - - ttm_resource_manager_cleanup(man); - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); -} +const struct attribute_group amdgpu_gtt_mgr_attr_group = { + .attrs = amdgpu_gtt_mgr_attributes +}; /** * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space * - * @mem: the mem object to check + * @res: the mem object to check * * Check if a mem object has already address space allocated. */ -bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem) +bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *res) { - return mem->mm_node != NULL; + struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res); + + return drm_mm_node_allocated(&node->base.mm_nodes[0]); } /** @@ -174,54 +125,57 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem) static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man, struct ttm_buffer_object *tbo, const struct ttm_place *place, - struct ttm_resource *mem) + struct ttm_resource **res) { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); + uint32_t num_pages = PFN_UP(tbo->base.size); struct amdgpu_gtt_node *node; int r; spin_lock(&mgr->lock); - if ((&tbo->mem == mem || tbo->mem.mem_type != TTM_PL_TT) && - atomic64_read(&mgr->available) < mem->num_pages) { + if (tbo->resource && tbo->resource->mem_type != TTM_PL_TT && + atomic64_read(&mgr->available) < num_pages) { spin_unlock(&mgr->lock); return -ENOSPC; } - atomic64_sub(mem->num_pages, &mgr->available); + atomic64_sub(num_pages, &mgr->available); spin_unlock(&mgr->lock); - if (!place->lpfn) { - mem->mm_node = NULL; - mem->start = AMDGPU_BO_INVALID_OFFSET; - return 0; - } - - node = kzalloc(sizeof(*node), GFP_KERNEL); + node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); if (!node) { r = -ENOMEM; goto err_out; } node->tbo = tbo; + ttm_resource_init(tbo, place, &node->base.base); - spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages, - mem->page_alignment, 0, place->fpfn, - place->lpfn, DRM_MM_INSERT_BEST); - spin_unlock(&mgr->lock); + if (place->lpfn) { + spin_lock(&mgr->lock); + r = drm_mm_insert_node_in_range(&mgr->mm, + &node->base.mm_nodes[0], + num_pages, tbo->page_alignment, + 0, place->fpfn, place->lpfn, + DRM_MM_INSERT_BEST); + spin_unlock(&mgr->lock); + if (unlikely(r)) + goto err_free; - if (unlikely(r)) - goto err_free; - - mem->mm_node = node; - mem->start = node->node.start; + node->base.base.start = node->base.mm_nodes[0].start; + } else { + node->base.mm_nodes[0].start = 0; + node->base.mm_nodes[0].size = node->base.base.num_pages; + node->base.base.start = AMDGPU_BO_INVALID_OFFSET; + } + *res = &node->base.base; return 0; err_free: kfree(node); err_out: - atomic64_add(mem->num_pages, &mgr->available); + atomic64_add(num_pages, &mgr->available); return r; } @@ -235,19 +189,18 @@ err_out: * Free the allocated GTT again. */ static void amdgpu_gtt_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *mem) + struct ttm_resource *res) { + struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res); struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); - struct amdgpu_gtt_node *node = mem->mm_node; - if (node) { - spin_lock(&mgr->lock); - drm_mm_remove_node(&node->node); - spin_unlock(&mgr->lock); - kfree(node); - } + spin_lock(&mgr->lock); + if (drm_mm_node_allocated(&node->base.mm_nodes[0])) + drm_mm_remove_node(&node->base.mm_nodes[0]); + spin_unlock(&mgr->lock); + atomic64_add(res->num_pages, &mgr->available); - atomic64_add(mem->num_pages, &mgr->available); + kfree(node); } /** @@ -265,22 +218,33 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man) return (result > 0 ? result : 0) * PAGE_SIZE; } +/** + * amdgpu_gtt_mgr_recover - re-init gart + * + * @man: TTM memory type manager + * + * Re-init the gart for each known BO in the GTT. + */ int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man) { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); + struct amdgpu_device *adev; struct amdgpu_gtt_node *node; struct drm_mm_node *mm_node; int r = 0; + adev = container_of(mgr, typeof(*adev), mman.gtt_mgr); spin_lock(&mgr->lock); drm_mm_for_each_node(mm_node, &mgr->mm) { - node = container_of(mm_node, struct amdgpu_gtt_node, node); + node = container_of(mm_node, typeof(*node), base.mm_nodes[0]); r = amdgpu_ttm_recover_gart(node->tbo); if (r) break; } spin_unlock(&mgr->lock); + amdgpu_gart_invalidate_tlb(adev); + return r; } @@ -311,3 +275,61 @@ static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = { .free = amdgpu_gtt_mgr_del, .debug = amdgpu_gtt_mgr_debug }; + +/** + * amdgpu_gtt_mgr_init - init GTT manager and DRM MM + * + * @adev: amdgpu_device pointer + * @gtt_size: maximum size of GTT + * + * Allocate and initialize the GTT manager. + */ +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) +{ + struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; + struct ttm_resource_manager *man = &mgr->manager; + uint64_t start, size; + + man->use_tt = true; + man->func = &amdgpu_gtt_mgr_func; + + ttm_resource_manager_init(man, gtt_size >> PAGE_SHIFT); + + start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; + size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; + drm_mm_init(&mgr->mm, start, size); + spin_lock_init(&mgr->lock); + atomic64_set(&mgr->available, gtt_size >> PAGE_SHIFT); + + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_gtt_mgr_fini - free and destroy GTT manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the GTT manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + spin_lock(&mgr->lock); + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c new file mode 100644 index 000000000000..1d50d534d77c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c @@ -0,0 +1,69 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" +#include "amdgpu_ras.h" + +int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev) +{ + int r; + struct ras_ih_if ih_info = { + .cb = NULL, + }; + struct ras_fs_if fs_info = { + .sysfs_name = "hdp_err_count", + }; + + if (!adev->hdp.ras_if) { + adev->hdp.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); + if (!adev->hdp.ras_if) + return -ENOMEM; + adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP; + adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; + adev->hdp.ras_if->sub_block_index = 0; + strcpy(adev->hdp.ras_if->name, "hdp"); + } + ih_info.head = fs_info.head = *adev->hdp.ras_if; + r = amdgpu_ras_late_init(adev, adev->hdp.ras_if, + &fs_info, &ih_info); + if (r || !amdgpu_ras_is_supported(adev, adev->hdp.ras_if->block)) { + kfree(adev->hdp.ras_if); + adev->hdp.ras_if = NULL; + } + + return r; +} + +void amdgpu_hdp_ras_fini(struct amdgpu_device *adev) +{ + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) && + adev->hdp.ras_if) { + struct ras_common_if *ras_if = adev->hdp.ras_if; + struct ras_ih_if ih_info = { + .cb = NULL, + }; + + amdgpu_ras_late_fini(adev, ras_if, &ih_info); + kfree(ras_if); + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h index 43caf9f8cc11..7ec99d591584 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h @@ -23,18 +23,29 @@ #ifndef __AMDGPU_HDP_H__ #define __AMDGPU_HDP_H__ +struct amdgpu_hdp_ras_funcs { + int (*ras_late_init)(struct amdgpu_device *adev); + void (*ras_fini)(struct amdgpu_device *adev); + void (*query_ras_error_count)(struct amdgpu_device *adev, + void *ras_error_status); + void (*reset_ras_error_count)(struct amdgpu_device *adev); +}; + struct amdgpu_hdp_funcs { void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); void (*invalidate_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); - void (*reset_ras_error_count)(struct amdgpu_device *adev); void (*update_clock_gating)(struct amdgpu_device *adev, bool enable); void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags); void (*init_registers)(struct amdgpu_device *adev); }; struct amdgpu_hdp { + struct ras_common_if *ras_if; const struct amdgpu_hdp_funcs *funcs; + const struct amdgpu_hdp_ras_funcs *ras_funcs; }; +int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev); +void amdgpu_hdp_ras_fini(struct amdgpu_device *adev); #endif /* __AMDGPU_HDP_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index a2fe2dac32c1..ec65ab0ddf89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -130,7 +130,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, struct amdgpu_device *adev = ring->adev; struct amdgpu_ib *ib = &ibs[0]; struct dma_fence *tmp = NULL; - bool skip_preamble, need_ctx_switch; + bool need_ctx_switch; unsigned patch_offset = ~0; struct amdgpu_vm *vm; uint64_t fence_ctx; @@ -214,20 +214,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, if (job && ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring); -#ifdef CONFIG_X86_64 - if (!(adev->flags & AMD_IS_APU)) -#endif - { - if (ring->funcs->emit_hdp_flush) - amdgpu_ring_emit_hdp_flush(ring); - else - amdgpu_asic_flush_hdp(adev, ring); - } + amdgpu_device_flush_hdp(adev, ring); if (need_ctx_switch) status |= AMDGPU_HAVE_CTX_SWITCH; - skip_preamble = ring->current_ctx == fence_ctx; if (job && ring->funcs->emit_cntxcntl) { status |= job->preamble_status; status |= job->preemption_status; @@ -245,14 +236,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, for (i = 0; i < num_ibs; ++i) { ib = &ibs[i]; - /* drop preamble IBs if we don't have a context switch */ - if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && - skip_preamble && - !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && - !amdgpu_mcbp && - !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ - continue; - if (job && ring->funcs->emit_frame_cntl) { if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { amdgpu_ring_emit_frame_cntl(ring, false, secure); @@ -268,10 +251,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, if (job && ring->funcs->emit_frame_cntl) amdgpu_ring_emit_frame_cntl(ring, false, secure); -#ifdef CONFIG_X86_64 - if (!(adev->flags & AMD_IS_APU)) -#endif - amdgpu_asic_invalidate_hdp(adev, ring); + amdgpu_device_invalidate_hdp(adev, ring); if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; @@ -328,7 +308,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev) for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { if (i == AMDGPU_IB_POOL_DIRECT) - size = PAGE_SIZE * 2; + size = PAGE_SIZE * 6; else size = AMDGPU_IB_POOL_SIZE; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index b4971e90b98c..b7fb72bff2c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -112,7 +112,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv, unsigned count; int r; - r = dma_resv_get_fences_rcu(resv, NULL, &count, &fences); + r = dma_resv_get_fences(resv, NULL, &count, &fences); if (r) goto fallback; @@ -156,8 +156,7 @@ fallback: /* Not enough memory for the delayed delete, as last resort * block for all the fences to complete. */ - dma_resv_wait_timeout_rcu(resv, true, false, - MAX_SCHEDULE_TIMEOUT); + dma_resv_wait_timeout(resv, true, false, MAX_SCHEDULE_TIMEOUT); amdgpu_pasid_free(pasid); } @@ -183,7 +182,7 @@ bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, } /** - * amdgpu_vm_grab_idle - grab idle VMID + * amdgpu_vmid_grab_idle - grab idle VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to @@ -256,7 +255,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm, } /** - * amdgpu_vm_grab_reserved - try to assign reserved VMID + * amdgpu_vmid_grab_reserved - try to assign reserved VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to @@ -325,7 +324,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm, } /** - * amdgpu_vm_grab_used - try to reuse a VMID + * amdgpu_vmid_grab_used - try to reuse a VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to @@ -397,7 +396,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm, } /** - * amdgpu_vm_grab_id - allocate the next free VMID + * amdgpu_vmid_grab - allocate the next free VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index faaa6aa2faaf..f3d62e196901 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -115,9 +115,11 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, */ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { + + if (!ih->ring) + return; + if (ih->use_bus_addr) { - if (!ih->ring) - return; /* add 8 bytes for the rptr/wptr shadows and * add them to the end of the ring allocation. @@ -175,7 +177,9 @@ static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev, cur_rptr += ih->ptr_mask + 1; *prev_rptr = cur_rptr; - return cur_rptr >= checkpoint_wptr; + /* check ring is empty to workaround missing wptr overflow flag */ + return cur_rptr >= checkpoint_wptr || + (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 90f50561b43a..32ce0e679dc7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -49,6 +49,7 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_ih.h" #include "atom.h" @@ -348,6 +349,25 @@ int amdgpu_irq_init(struct amdgpu_device *adev) return 0; } + +void amdgpu_irq_fini_hw(struct amdgpu_device *adev) +{ + if (adev->irq.installed) { + drm_irq_uninstall(&adev->ddev); + adev->irq.installed = false; + if (adev->irq.msi_enabled) + pci_free_irq_vectors(adev->pdev); + + if (!amdgpu_device_has_dc_support(adev)) + flush_work(&adev->hotplug_work); + } + + amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); + amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_ih_ring_fini(adev, &adev->irq.ih1); + amdgpu_ih_ring_fini(adev, &adev->irq.ih2); +} + /** * amdgpu_irq_fini - shut down interrupt handling * @@ -357,19 +377,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev) * functionality, shuts down vblank, hotplug and reset interrupt handling, * turns off interrupts from all sources (all ASICs). */ -void amdgpu_irq_fini(struct amdgpu_device *adev) +void amdgpu_irq_fini_sw(struct amdgpu_device *adev) { unsigned i, j; - if (adev->irq.installed) { - drm_irq_uninstall(adev_to_drm(adev)); - adev->irq.installed = false; - if (adev->irq.msi_enabled) - pci_free_irq_vectors(adev->pdev); - if (!amdgpu_device_has_dc_support(adev)) - flush_work(&adev->hotplug_work); - } - for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { if (!adev->irq.client[i].sources) continue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index cf6116648322..78ad4784cc74 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -103,7 +103,8 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev); irqreturn_t amdgpu_irq_handler(int irq, void *arg); int amdgpu_irq_init(struct amdgpu_device *adev); -void amdgpu_irq_fini(struct amdgpu_device *adev); +void amdgpu_irq_fini_sw(struct amdgpu_device *adev); +void amdgpu_irq_fini_hw(struct amdgpu_device *adev); int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned client_id, unsigned src_id, struct amdgpu_irq_src *source); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 759b34799221..d33e6d97cc89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -25,6 +25,8 @@ #include #include +#include + #include "amdgpu.h" #include "amdgpu_trace.h" @@ -34,6 +36,15 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) struct amdgpu_job *job = to_amdgpu_job(s_job); struct amdgpu_task_info ti; struct amdgpu_device *adev = ring->adev; + int idx; + + if (!drm_dev_enter(&adev->ddev, &idx)) { + DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s", + __func__, s_job->sched->name); + + /* Effectively the job is aborted as the device is gone */ + return DRM_GPU_SCHED_STAT_ENODEV; + } memset(&ti, 0, sizeof(struct amdgpu_task_info)); @@ -41,7 +52,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { DRM_ERROR("ring %s timeout, but soft recovered\n", s_job->sched->name); - return DRM_GPU_SCHED_STAT_NOMINAL; + goto exit; } amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); @@ -53,13 +64,15 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) if (amdgpu_device_should_recover_gpu(ring->adev)) { amdgpu_device_gpu_recover(ring->adev, job); - return DRM_GPU_SCHED_STAT_NOMINAL; } else { drm_sched_suspend_timeout(&ring->sched); if (amdgpu_sriov_vf(adev)) adev->virt.tdr_debug = true; - return DRM_GPU_SCHED_STAT_NOMINAL; } + +exit: + drm_dev_exit(idx); + return DRM_GPU_SCHED_STAT_NOMINAL; } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 39ee88d29cca..96ef3f1051d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -28,6 +28,7 @@ #include "amdgpu.h" #include +#include #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "atom.h" @@ -91,8 +92,11 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) pm_runtime_forbid(dev->dev); } + if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) + DRM_WARN("smart shift update failed\n"); + amdgpu_acpi_fini(adev); - amdgpu_device_fini(adev); + amdgpu_device_fini_hw(adev); } void amdgpu_register_gpu_instance(struct amdgpu_device *adev) @@ -120,6 +124,22 @@ void amdgpu_register_gpu_instance(struct amdgpu_device *adev) mutex_unlock(&mgpu_info.mutex); } +static void amdgpu_get_audio_func(struct amdgpu_device *adev) +{ + struct pci_dev *p = NULL; + + p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), + adev->pdev->bus->number, 1); + if (p) { + pm_runtime_get_sync(&p->dev); + + pm_runtime_mark_last_busy(&p->dev); + pm_runtime_put_autosuspend(&p->dev); + + pci_dev_put(p); + } +} + /** * amdgpu_driver_load_kms - Main load function for KMS. * @@ -209,11 +229,40 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) DPM_FLAG_MAY_SKIP_RESUME); pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); + pm_runtime_allow(dev->dev); + pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); + + /* + * For runpm implemented via BACO, PMFW will handle the + * timing for BACO in and out: + * - put ASIC into BACO state only when both video and + * audio functions are in D3 state. + * - pull ASIC out of BACO state when either video or + * audio function is in D0 state. + * Also, at startup, PMFW assumes both functions are in + * D0 state. + * + * So if snd driver was loaded prior to amdgpu driver + * and audio function was put into D3 state, there will + * be no PMFW-aware D-state transition(D0->D3) on runpm + * suspend. Thus the BACO will be not correctly kicked in. + * + * Via amdgpu_get_audio_func(), the audio dev is put + * into D0 state. Then there will be a PMFW-aware D-state + * transition(D0->D3) on runpm suspend. + */ + if (amdgpu_device_supports_baco(dev) && + !(adev->flags & AMD_IS_APU) && + (adev->asic_type >= CHIP_NAVI10)) + amdgpu_get_audio_func(adev); } + if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) + DRM_WARN("smart shift update failed\n"); + out: if (r) { /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ @@ -861,6 +910,21 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) min((size_t)size, (size_t)(bios_size - bios_offset))) ? -EFAULT : 0; } + case AMDGPU_INFO_VBIOS_INFO: { + struct drm_amdgpu_info_vbios vbios_info = {}; + struct atom_context *atom_context; + + atom_context = adev->mode_info.atom_context; + memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); + memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); + vbios_info.version = atom_context->version; + memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, + sizeof(atom_context->vbios_ver_str)); + memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); + + return copy_to_user(out, &vbios_info, + min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; + } default: DRM_DEBUG_KMS("Invalid request %d\n", info->vbios_info.type); @@ -986,7 +1050,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (!ras) return -EINVAL; - ras_mask = (uint64_t)ras->supported << 32 | ras->features; + ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; return copy_to_user(out, &ras_mask, min_t(u64, size, sizeof(ras_mask))) ? @@ -1114,7 +1178,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) dev_warn(adev->dev, "No more PASIDs available!"); pasid = 0; } - r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); + + r = amdgpu_vm_init(adev, &fpriv->vm, pasid); if (r) goto error_pasid; @@ -1197,7 +1262,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, } pasid = fpriv->vm.pasid; - pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); + pd = amdgpu_bo_ref(fpriv->vm.root.bo); amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); amdgpu_vm_fini(adev, &fpriv->vm); @@ -1219,6 +1284,15 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } + +void amdgpu_driver_release_kms(struct drm_device *dev) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + + amdgpu_device_fini_sw(adev); + pci_set_drvdata(adev->pdev, NULL); +} + /* * VBlank related functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index 11aa29933c1f..b27fcbccce2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -28,6 +28,7 @@ struct amdgpu_mmhub_ras_funcs { void *ras_error_status); void (*query_ras_error_status)(struct amdgpu_device *adev); void (*reset_ras_error_count)(struct amdgpu_device *adev); + void (*reset_ras_error_status)(struct amdgpu_device *adev); }; struct amdgpu_mmhub_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c index 828b5167ff12..d6c54c7f7679 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -75,8 +75,8 @@ static bool amdgpu_mn_invalidate_gfx(struct mmu_interval_notifier *mni, mmu_interval_set_seq(mni, cur_seq); - r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, true, false, - MAX_SCHEDULE_TIMEOUT); + r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, + MAX_SCHEDULE_TIMEOUT); mutex_unlock(&adev->notifier_lock); if (r <= 0) DRM_ERROR("(%ld) failed to wait for user bo\n", r); @@ -155,3 +155,89 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo) mmu_interval_notifier_remove(&bo->notifier); bo->notifier.mm = NULL; } + +int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, + struct mm_struct *mm, struct page **pages, + uint64_t start, uint64_t npages, + struct hmm_range **phmm_range, bool readonly, + bool mmap_locked) +{ + struct hmm_range *hmm_range; + unsigned long timeout; + unsigned long i; + unsigned long *pfns; + int r = 0; + + hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); + if (unlikely(!hmm_range)) + return -ENOMEM; + + pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); + if (unlikely(!pfns)) { + r = -ENOMEM; + goto out_free_range; + } + + hmm_range->notifier = notifier; + hmm_range->default_flags = HMM_PFN_REQ_FAULT; + if (!readonly) + hmm_range->default_flags |= HMM_PFN_REQ_WRITE; + hmm_range->hmm_pfns = pfns; + hmm_range->start = start; + hmm_range->end = start + npages * PAGE_SIZE; + + /* Assuming 512MB takes maxmium 1 second to fault page address */ + timeout = max(npages >> 17, 1ULL) * HMM_RANGE_DEFAULT_TIMEOUT; + timeout = jiffies + msecs_to_jiffies(timeout); + +retry: + hmm_range->notifier_seq = mmu_interval_read_begin(notifier); + + if (likely(!mmap_locked)) + mmap_read_lock(mm); + + r = hmm_range_fault(hmm_range); + + if (likely(!mmap_locked)) + mmap_read_unlock(mm); + if (unlikely(r)) { + /* + * FIXME: This timeout should encompass the retry from + * mmu_interval_read_retry() as well. + */ + if (r == -EBUSY && !time_after(jiffies, timeout)) + goto retry; + goto out_free_pfns; + } + + /* + * Due to default_flags, all pages are HMM_PFN_VALID or + * hmm_range_fault() fails. FIXME: The pages cannot be touched outside + * the notifier_lock, and mmu_interval_read_retry() must be done first. + */ + for (i = 0; pages && i < npages; i++) + pages[i] = hmm_pfn_to_page(pfns[i]); + + *phmm_range = hmm_range; + + return 0; + +out_free_pfns: + kvfree(pfns); +out_free_range: + kfree(hmm_range); + + return r; +} + +int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) +{ + int r; + + r = mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); + kvfree(hmm_range->hmm_pfns); + kfree(hmm_range); + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h index a292238f75eb..7f7d37a457c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h @@ -30,6 +30,13 @@ #include #include +int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, + struct mm_struct *mm, struct page **pages, + uint64_t start, uint64_t npages, + struct hmm_range **phmm_range, bool readonly, + bool mmap_locked); +int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); + #if defined(CONFIG_HMM_MIRROR) int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_mn_unregister(struct amdgpu_bo *bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index cb0b581bbce7..89fb372ed49c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -344,7 +344,7 @@ struct amdgpu_mode_info { /* pointer to fbdev info structure */ struct amdgpu_fbdev *rfbdev; /* firmware flags */ - u16 firmware_flags; + u32 firmware_flags; /* pointer to backlight encoder */ struct amdgpu_encoder *bl_encoder; u8 bl_level; /* saved backlight level */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f9434bc2f9b2..795fa7445abe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -52,55 +52,44 @@ * */ -/** - * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting - * - * @bo: &amdgpu_bo buffer object - * - * This function is called when a BO stops being pinned, and updates the - * &amdgpu_device pin_size values accordingly. - */ -static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - - if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { - atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); - atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), - &adev->visible_pin_size); - } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { - atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); - } -} - static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) { - struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); - struct amdgpu_bo_user *ubo; - - if (bo->tbo.pin_count > 0) - amdgpu_bo_subtract_pin_size(bo); amdgpu_bo_kunmap(bo); if (bo->tbo.base.import_attach) drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); drm_gem_object_release(&bo->tbo.base); + amdgpu_bo_unref(&bo->parent); + kvfree(bo); +} + +static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) +{ + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + struct amdgpu_bo_user *ubo; + + ubo = to_amdgpu_bo_user(bo); + kfree(ubo->metadata); + amdgpu_bo_destroy(tbo); +} + +static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + struct amdgpu_bo_vm *vmbo; + + vmbo = to_amdgpu_bo_vm(bo); /* in case amdgpu_device_recover_vram got NULL of bo->parent */ - if (!list_empty(&bo->shadow_list)) { + if (!list_empty(&vmbo->shadow_list)) { mutex_lock(&adev->shadow_list_lock); - list_del_init(&bo->shadow_list); + list_del_init(&vmbo->shadow_list); mutex_unlock(&adev->shadow_list_lock); } - amdgpu_bo_unref(&bo->parent); - if (bo->tbo.type == ttm_bo_type_device) { - ubo = to_amdgpu_bo_user(bo); - kfree(ubo->metadata); - } - - kvfree(bo); + amdgpu_bo_destroy(tbo); } /** @@ -115,8 +104,11 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) */ bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) { - if (bo->destroy == &amdgpu_bo_destroy) + if (bo->destroy == &amdgpu_bo_destroy || + bo->destroy == &amdgpu_bo_user_destroy || + bo->destroy == &amdgpu_bo_vm_destroy) return true; + return false; } @@ -157,7 +149,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (domain & AMDGPU_GEM_DOMAIN_GTT) { places[c].fpfn = 0; places[c].lpfn = 0; - places[c].mem_type = TTM_PL_TT; + places[c].mem_type = + abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? + AMDGPU_PL_PREEMPT : TTM_PL_TT; places[c].flags = 0; c++; } @@ -386,14 +380,14 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, if (cpu_addr) amdgpu_bo_kunmap(*bo_ptr); - ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); + ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; } r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, - &(*bo_ptr)->tbo.mem, &ctx); + &(*bo_ptr)->tbo.resource, &ctx); if (r) goto error; @@ -515,7 +509,18 @@ bool amdgpu_bo_support_uswc(u64 bo_flags) #endif } -static int amdgpu_bo_do_create(struct amdgpu_device *adev, +/** + * amdgpu_bo_create - create an &amdgpu_bo buffer object + * @adev: amdgpu device object + * @bp: parameters to be used for the buffer object + * @bo_ptr: pointer to the buffer object pointer + * + * Creates an &amdgpu_bo buffer object. + * + * Returns: + * 0 for success or a negative error code on failure. + */ +int amdgpu_bo_create(struct amdgpu_device *adev, struct amdgpu_bo_param *bp, struct amdgpu_bo **bo_ptr) { @@ -556,7 +561,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, if (bo == NULL) return -ENOMEM; drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); - INIT_LIST_HEAD(&bo->shadow_list); bo->vm_bo = NULL; bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : bp->domain; @@ -579,22 +583,25 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_kernel) bo->tbo.priority = 1; + if (!bp->destroy) + bp->destroy = &amdgpu_bo_destroy; + r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, &bo->placement, page_align, &ctx, NULL, - bp->resv, &amdgpu_bo_destroy); + bp->resv, bp->destroy); if (unlikely(r != 0)) return r; if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && - bo->tbo.mem.mem_type == TTM_PL_VRAM && - bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) + bo->tbo.resource->mem_type == TTM_PL_VRAM && + bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT) amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, ctx.bytes_moved); else amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && - bo->tbo.mem.mem_type == TTM_PL_VRAM) { + bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); @@ -625,80 +632,6 @@ fail_unreserve: return r; } -static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, - unsigned long size, - struct amdgpu_bo *bo) -{ - struct amdgpu_bo_param bp; - int r; - - if (bo->shadow) - return 0; - - memset(&bp, 0, sizeof(bp)); - bp.size = size; - bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | - AMDGPU_GEM_CREATE_SHADOW; - bp.type = ttm_bo_type_kernel; - bp.resv = bo->tbo.base.resv; - bp.bo_ptr_size = sizeof(struct amdgpu_bo); - - r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); - if (!r) { - bo->shadow->parent = amdgpu_bo_ref(bo); - mutex_lock(&adev->shadow_list_lock); - list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); - mutex_unlock(&adev->shadow_list_lock); - } - - return r; -} - -/** - * amdgpu_bo_create - create an &amdgpu_bo buffer object - * @adev: amdgpu device object - * @bp: parameters to be used for the buffer object - * @bo_ptr: pointer to the buffer object pointer - * - * Creates an &amdgpu_bo buffer object; and if requested, also creates a - * shadow object. - * Shadow object is used to backup the original buffer object, and is always - * in GTT. - * - * Returns: - * 0 for success or a negative error code on failure. - */ -int amdgpu_bo_create(struct amdgpu_device *adev, - struct amdgpu_bo_param *bp, - struct amdgpu_bo **bo_ptr) -{ - u64 flags = bp->flags; - int r; - - bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; - - r = amdgpu_bo_do_create(adev, bp, bo_ptr); - if (r) - return r; - - if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { - if (!bp->resv) - WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, - NULL)); - - r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); - - if (!bp->resv) - dma_resv_unlock((*bo_ptr)->tbo.base.resv); - - if (r) - amdgpu_bo_unref(bo_ptr); - } - - return r; -} - /** * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object * @adev: amdgpu device object @@ -718,15 +651,49 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev, struct amdgpu_bo *bo_ptr; int r; - bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); - r = amdgpu_bo_do_create(adev, bp, &bo_ptr); + bp->destroy = &amdgpu_bo_user_destroy; + r = amdgpu_bo_create(adev, bp, &bo_ptr); if (r) return r; *ubo_ptr = to_amdgpu_bo_user(bo_ptr); return r; } + +/** + * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object + * @adev: amdgpu device object + * @bp: parameters to be used for the buffer object + * @vmbo_ptr: pointer to the buffer object pointer + * + * Create a BO to be for GPUVM. + * + * Returns: + * 0 for success or a negative error code on failure. + */ + +int amdgpu_bo_create_vm(struct amdgpu_device *adev, + struct amdgpu_bo_param *bp, + struct amdgpu_bo_vm **vmbo_ptr) +{ + struct amdgpu_bo *bo_ptr; + int r; + + /* bo_ptr_size will be determined by the caller and it depends on + * num of amdgpu_vm_pt entries. + */ + BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); + bp->destroy = &amdgpu_bo_vm_destroy; + r = amdgpu_bo_create(adev, bp, &bo_ptr); + if (r) + return r; + + *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); + INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); + return r; +} + /** * amdgpu_bo_validate - validate an &amdgpu_bo buffer object * @bo: pointer to the buffer object @@ -761,6 +728,22 @@ retry: return r; } +/** + * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list + * + * @bo: BO that will be inserted into the shadow list + * + * Insert a BO to the shadow list. + */ +void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); + + mutex_lock(&adev->shadow_list_lock); + list_add_tail(&vmbo->shadow_list, &adev->shadow_list); + mutex_unlock(&adev->shadow_list_lock); +} + /** * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow * @@ -815,12 +798,12 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) return 0; } - r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, - MAX_SCHEDULE_TIMEOUT); + r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false, + MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; - r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap); + r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap); if (r) return r; @@ -943,8 +926,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); if (bo->tbo.pin_count) { - uint32_t mem_type = bo->tbo.mem.mem_type; - uint32_t mem_flags = bo->tbo.mem.placement; + uint32_t mem_type = bo->tbo.resource->mem_type; + uint32_t mem_flags = bo->tbo.resource->placement; if (!(domain & amdgpu_mem_type_to_domain(mem_type))) return -EINVAL; @@ -994,7 +977,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, ttm_bo_pin(&bo->tbo); - domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); + domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), @@ -1037,14 +1020,22 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) */ void amdgpu_bo_unpin(struct amdgpu_bo *bo) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + ttm_bo_unpin(&bo->tbo); if (bo->tbo.pin_count) return; - amdgpu_bo_subtract_pin_size(bo); - if (bo->tbo.base.import_attach) dma_buf_unpin(bo->tbo.base.import_attach); + + if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { + atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); + atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), + &adev->visible_pin_size); + } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { + atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); + } } /** @@ -1123,10 +1114,6 @@ int amdgpu_bo_init(struct amdgpu_device *adev) void amdgpu_bo_fini(struct amdgpu_device *adev) { amdgpu_ttm_fini(adev); - if (!adev->gmc.xgmi.connected_to_cpu) { - arch_phys_wc_del(adev->gmc.vram_mtrr); - arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); - } } /** @@ -1246,6 +1233,9 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, BUG_ON(bo->tbo.type == ttm_bo_type_kernel); ubo = to_amdgpu_bo_user(bo); + if (metadata_size) + *metadata_size = ubo->metadata_size; + if (buffer) { if (buffer_size < ubo->metadata_size) return -EINVAL; @@ -1254,8 +1244,6 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, memcpy(buffer, ubo->metadata, ubo->metadata_size); } - if (metadata_size) - *metadata_size = ubo->metadata_size; if (flags) *flags = ubo->metadata_flags; @@ -1278,7 +1266,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo; - struct ttm_resource *old_mem = &bo->mem; + struct ttm_resource *old_mem = bo->resource; if (!amdgpu_bo_is_amdgpu_bo(bo)) return; @@ -1289,7 +1277,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, amdgpu_bo_kunmap(abo); if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && - bo->mem.mem_type != TTM_PL_SYSTEM) + bo->resource->mem_type != TTM_PL_SYSTEM) dma_buf_move_notify(abo->tbo.base.dma_buf); /* remember the eviction */ @@ -1304,6 +1292,26 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); } +void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, + uint64_t *gtt_mem, uint64_t *cpu_mem) +{ + unsigned int domain; + + domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); + switch (domain) { + case AMDGPU_GEM_DOMAIN_VRAM: + *vram_mem += amdgpu_bo_size(bo); + break; + case AMDGPU_GEM_DOMAIN_GTT: + *gtt_mem += amdgpu_bo_size(bo); + break; + case AMDGPU_GEM_DOMAIN_CPU: + default: + *cpu_mem += amdgpu_bo_size(bo); + break; + } +} + /** * amdgpu_bo_release_notify - notification about a BO being released * @bo: pointer to a buffer object @@ -1331,7 +1339,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (bo->base.resv == &bo->base._resv) amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); - if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || + if (bo->resource->mem_type != TTM_PL_VRAM || !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) return; @@ -1362,18 +1370,17 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); - unsigned long offset, size; + unsigned long offset; int r; /* Remember that this BO was accessed by the CPU */ abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - if (bo->mem.mem_type != TTM_PL_VRAM) + if (bo->resource->mem_type != TTM_PL_VRAM) return 0; - size = bo->mem.num_pages << PAGE_SHIFT; - offset = bo->mem.start << PAGE_SHIFT; - if ((offset + size) <= adev->gmc.visible_vram_size) + offset = bo->resource->start << PAGE_SHIFT; + if ((offset + bo->base.size) <= adev->gmc.visible_vram_size) return 0; /* Can't move a pinned BO to visible VRAM */ @@ -1395,10 +1402,10 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) else if (unlikely(r)) return VM_FAULT_SIGBUS; - offset = bo->mem.start << PAGE_SHIFT; + offset = bo->resource->start << PAGE_SHIFT; /* this should never happen */ - if (bo->mem.mem_type == TTM_PL_VRAM && - (offset + size) > adev->gmc.visible_vram_size) + if (bo->resource->mem_type == TTM_PL_VRAM && + (offset + bo->base.size) > adev->gmc.visible_vram_size) return VM_FAULT_SIGBUS; ttm_bo_move_to_lru_tail_unlocked(bo); @@ -1482,11 +1489,11 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) */ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { - WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); + WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); - WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); - WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && + WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); + WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); return amdgpu_bo_gpu_offset_no_check(bo); @@ -1504,8 +1511,8 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); uint64_t offset; - offset = (bo->tbo.mem.start << PAGE_SHIFT) + - amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); + offset = (bo->tbo.resource->start << PAGE_SHIFT) + + amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); return amdgpu_gmc_sign_extend(offset); } @@ -1558,7 +1565,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) unsigned int pin_count; u64 size; - domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); + domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); switch (domain) { case AMDGPU_GEM_DOMAIN_VRAM: placement = "VRAM"; @@ -1592,7 +1599,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); - amdgpu_bo_print_flag(m, bo, SHADOW); amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 2d1fefbe1e99..38c834d0f930 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -30,6 +30,8 @@ #include #include "amdgpu.h" +#include "amdgpu_res_cursor.h" + #ifdef CONFIG_MMU_NOTIFIER #include #endif @@ -37,7 +39,12 @@ #define AMDGPU_BO_INVALID_OFFSET LONG_MAX #define AMDGPU_BO_MAX_PLACEMENTS 3 +/* BO flag to indicate a KFD userptr BO */ +#define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63) +#define AMDGPU_AMDKFD_CREATE_SVM_BO (1ULL << 62) + #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo) +#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo) struct amdgpu_bo_param { unsigned long size; @@ -48,7 +55,8 @@ struct amdgpu_bo_param { u64 flags; enum ttm_bo_type type; bool no_wait_gpu; - struct dma_resv *resv; + struct dma_resv *resv; + void (*destroy)(struct ttm_buffer_object *bo); }; /* bo virtual addresses in a vm */ @@ -97,16 +105,10 @@ struct amdgpu_bo { struct amdgpu_vm_bo_base *vm_bo; /* Constant after initialization */ struct amdgpu_bo *parent; - struct amdgpu_bo *shadow; - - #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; #endif - - struct list_head shadow_list; - struct kgd_mem *kfd_bo; }; @@ -119,6 +121,13 @@ struct amdgpu_bo_user { }; +struct amdgpu_bo_vm { + struct amdgpu_bo bo; + struct amdgpu_bo *shadow; + struct list_head shadow_list; + struct amdgpu_vm_bo_base entries[]; +}; + static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) { return container_of(tbo, struct amdgpu_bo, tbo); @@ -191,7 +200,7 @@ static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) { - return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; + return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; } /** @@ -211,18 +220,19 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; - struct drm_mm_node *node = bo->tbo.mem.mm_node; - unsigned long pages_left; + struct amdgpu_res_cursor cursor; - if (bo->tbo.mem.mem_type != TTM_PL_VRAM) + if (bo->tbo.resource->mem_type != TTM_PL_VRAM) return false; - for (pages_left = bo->tbo.mem.num_pages; pages_left; - pages_left -= node->size, node++) - if (node->start < fpfn) + amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); + while (cursor.remaining) { + if (cursor.start < adev->gmc.visible_vram_size) return true; + amdgpu_res_next(&cursor, cursor.size); + } + return false; } @@ -245,6 +255,22 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; } +/** + * amdgpu_bo_shadowed - check if the BO is shadowed + * + * @bo: BO to be tested. + * + * Returns: + * NULL if not shadowed or else return a BO pointer. + */ +static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) +{ + if (bo->tbo.type == ttm_bo_type_kernel) + return to_amdgpu_bo_vm(bo)->shadow; + + return NULL; +} + bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); @@ -265,6 +291,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, int amdgpu_bo_create_user(struct amdgpu_device *adev, struct amdgpu_bo_param *bp, struct amdgpu_bo_user **ubo_ptr); +int amdgpu_bo_create_vm(struct amdgpu_device *adev, + struct amdgpu_bo_param *bp, + struct amdgpu_bo_vm **ubo_ptr); void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, void **cpu_addr); int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); @@ -300,6 +329,9 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); int amdgpu_bo_validate(struct amdgpu_bo *bo); +void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, + uint64_t *gtt_mem, uint64_t *cpu_mem); +void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence); uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c new file mode 100644 index 000000000000..d02c8637f909 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2016-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König, Felix Kuehling + */ + +#include "amdgpu.h" + +static inline struct amdgpu_preempt_mgr * +to_preempt_mgr(struct ttm_resource_manager *man) +{ + return container_of(man, struct amdgpu_preempt_mgr, manager); +} + +/** + * DOC: mem_info_preempt_used + * + * The amdgpu driver provides a sysfs API for reporting current total amount of + * used preemptible memory. + * The file mem_info_preempt_used is used for this, and returns the current + * used size of the preemptible block, in bytes + */ +static ssize_t mem_info_preempt_used_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct ttm_resource_manager *man; + + man = ttm_manager_type(&adev->mman.bdev, AMDGPU_PL_PREEMPT); + return sysfs_emit(buf, "%llu\n", amdgpu_preempt_mgr_usage(man)); +} + +static DEVICE_ATTR_RO(mem_info_preempt_used); + +/** + * amdgpu_preempt_mgr_new - allocate a new node + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: the resulting mem object + * + * Dummy, just count the space used without allocating resources or any limit. + */ +static int amdgpu_preempt_mgr_new(struct ttm_resource_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_resource **res) +{ + struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man); + + *res = kzalloc(sizeof(**res), GFP_KERNEL); + if (!*res) + return -ENOMEM; + + ttm_resource_init(tbo, place, *res); + (*res)->start = AMDGPU_BO_INVALID_OFFSET; + + atomic64_add((*res)->num_pages, &mgr->used); + return 0; +} + +/** + * amdgpu_preempt_mgr_del - free ranges + * + * @man: TTM memory type manager + * @mem: TTM memory object + * + * Free the allocated GTT again. + */ +static void amdgpu_preempt_mgr_del(struct ttm_resource_manager *man, + struct ttm_resource *res) +{ + struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man); + + atomic64_sub(res->num_pages, &mgr->used); + kfree(res); +} + +/** + * amdgpu_preempt_mgr_usage - return usage of PREEMPT domain + * + * @man: TTM memory type manager + * + * Return how many bytes are used in the GTT domain + */ +uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man) +{ + struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man); + s64 result = atomic64_read(&mgr->used); + + return (result > 0 ? result : 0) * PAGE_SIZE; +} + +/** + * amdgpu_preempt_mgr_debug - dump VRAM table + * + * @man: TTM memory type manager + * @printer: DRM printer to use + * + * Dump the table content using printk. + */ +static void amdgpu_preempt_mgr_debug(struct ttm_resource_manager *man, + struct drm_printer *printer) +{ + struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man); + + drm_printf(printer, "man size:%llu pages, preempt used:%lld pages\n", + man->size, (u64)atomic64_read(&mgr->used)); +} + +static const struct ttm_resource_manager_func amdgpu_preempt_mgr_func = { + .alloc = amdgpu_preempt_mgr_new, + .free = amdgpu_preempt_mgr_del, + .debug = amdgpu_preempt_mgr_debug +}; + +/** + * amdgpu_preempt_mgr_init - init PREEMPT manager and DRM MM + * + * @adev: amdgpu_device pointer + * + * Allocate and initialize the GTT manager. + */ +int amdgpu_preempt_mgr_init(struct amdgpu_device *adev) +{ + struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + man->use_tt = true; + man->func = &amdgpu_preempt_mgr_func; + + ttm_resource_manager_init(man, (1 << 30)); + + atomic64_set(&mgr->used, 0); + + ret = device_create_file(adev->dev, &dev_attr_mem_info_preempt_used); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_preempt_used\n"); + return ret; + } + + ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT, + &mgr->manager); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_preempt_mgr_fini - free and destroy GTT manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the GTT manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + device_remove_file(adev->dev, &dev_attr_mem_info_preempt_used); + + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT, NULL); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a09483beb968..3ec5099ffeb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -25,6 +25,7 @@ #include #include +#include #include "amdgpu.h" #include "amdgpu_psp.h" @@ -38,6 +39,9 @@ #include "amdgpu_ras.h" #include "amdgpu_securedisplay.h" +#include "amdgpu_atomfirmware.h" + +#include static int psp_sysfs_init(struct amdgpu_device *adev); static void psp_sysfs_fini(struct amdgpu_device *adev); @@ -104,6 +108,7 @@ static int psp_early_init(void *handle) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: psp_v11_0_set_psp_funcs(psp); psp->autoload_supported = true; break; @@ -113,6 +118,10 @@ static int psp_early_init(void *handle) case CHIP_ALDEBARAN: psp_v13_0_set_psp_funcs(psp); break; + case CHIP_YELLOW_CARP: + psp_v13_0_set_psp_funcs(psp); + psp->autoload_supported = true; + break; default: return -EINVAL; } @@ -162,11 +171,81 @@ Err_out: return ret; } +/* + * Helper funciton to query psp runtime database entry + * + * @adev: amdgpu_device pointer + * @entry_type: the type of psp runtime database entry + * @db_entry: runtime database entry pointer + * + * Return false if runtime database doesn't exit or entry is invalid + * or true if the specific database entry is found, and copy to @db_entry + */ +static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, + enum psp_runtime_entry_type entry_type, + void *db_entry) +{ + uint64_t db_header_pos, db_dir_pos; + struct psp_runtime_data_header db_header = {0}; + struct psp_runtime_data_directory db_dir = {0}; + bool ret = false; + int i; + + db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; + db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); + + /* read runtime db header from vram */ + amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, + sizeof(struct psp_runtime_data_header), false); + + if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { + /* runtime db doesn't exist, exit */ + dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); + return false; + } + + /* read runtime database entry from vram */ + amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, + sizeof(struct psp_runtime_data_directory), false); + + if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { + /* invalid db entry count, exit */ + dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); + return false; + } + + /* look up for requested entry type */ + for (i = 0; i < db_dir.entry_count && !ret; i++) { + if (db_dir.entry_list[i].entry_type == entry_type) { + switch (entry_type) { + case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: + if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { + /* invalid db entry size */ + dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); + return false; + } + /* read runtime database entry */ + amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, + (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); + ret = true; + break; + default: + ret = false; + break; + } + } + } + + return ret; +} + static int psp_sw_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct psp_context *psp = &adev->psp; int ret; + struct psp_runtime_boot_cfg_entry boot_cfg_entry; + struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; if (!amdgpu_sriov_vf(adev)) { ret = psp_init_microcode(psp); @@ -174,17 +253,47 @@ static int psp_sw_init(void *handle) DRM_ERROR("Failed to load psp firmware!\n"); return ret; } + } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { + ret = psp_init_ta_microcode(psp, "aldebaran"); + if (ret) { + DRM_ERROR("Failed to initialize ta microcode!\n"); + return ret; + } } - ret = psp_memory_training_init(psp); - if (ret) { - DRM_ERROR("Failed to initialize memory training!\n"); - return ret; + memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); + if (psp_get_runtime_db_entry(adev, + PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, + &boot_cfg_entry)) { + psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; + if ((psp->boot_cfg_bitmask) & + BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { + /* If psp runtime database exists, then + * only enable two stage memory training + * when TWO_STAGE_DRAM_TRAINING bit is set + * in runtime database */ + mem_training_ctx->enable_mem_training = true; + } + + } else { + /* If psp runtime database doesn't exist or + * is invalid, force enable two stage memory + * training */ + mem_training_ctx->enable_mem_training = true; } - ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); - if (ret) { - DRM_ERROR("Failed to process memory training!\n"); - return ret; + + if (mem_training_ctx->enable_mem_training) { + ret = psp_memory_training_init(psp); + if (ret) { + DRM_ERROR("Failed to initialize memory training!\n"); + return ret; + } + + ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); + if (ret) { + DRM_ERROR("Failed to process memory training!\n"); + return ret; + } } if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { @@ -229,7 +338,7 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index, int i; struct amdgpu_device *adev = psp->adev; - if (psp->adev->in_pci_err_recovery) + if (psp->adev->no_hw_access) return 0; for (i = 0; i < adev->usec_timeout; i++) { @@ -253,12 +362,15 @@ psp_cmd_submit_buf(struct psp_context *psp, struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) { int ret; - int index; + int index, idx; int timeout = 20000; bool ras_intr = false; bool skip_unsupport = false; - if (psp->adev->in_pci_err_recovery) + if (psp->adev->no_hw_access) + return 0; + + if (!drm_dev_enter(&psp->adev->ddev, &idx)) return 0; mutex_lock(&psp->mutex); @@ -271,11 +383,10 @@ psp_cmd_submit_buf(struct psp_context *psp, ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); if (ret) { atomic_dec(&psp->fence_value); - mutex_unlock(&psp->mutex); - return ret; + goto exit; } - amdgpu_asic_invalidate_hdp(psp->adev, NULL); + amdgpu_device_invalidate_hdp(psp->adev, NULL); while (*((unsigned int *)psp->fence_buf) != index) { if (--timeout == 0) break; @@ -288,7 +399,7 @@ psp_cmd_submit_buf(struct psp_context *psp, if (ras_intr) break; usleep_range(10, 100); - amdgpu_asic_invalidate_hdp(psp->adev, NULL); + amdgpu_device_invalidate_hdp(psp->adev, NULL); } /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ @@ -312,8 +423,8 @@ psp_cmd_submit_buf(struct psp_context *psp, psp->cmd_buf_mem->cmd_id, psp->cmd_buf_mem->resp.status); if (!timeout) { - mutex_unlock(&psp->mutex); - return -EINVAL; + ret = -EINVAL; + goto exit; } } @@ -321,8 +432,10 @@ psp_cmd_submit_buf(struct psp_context *psp, ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; } - mutex_unlock(&psp->mutex); +exit: + mutex_unlock(&psp->mutex); + drm_dev_exit(idx); return ret; } @@ -366,8 +479,7 @@ static int psp_load_toc(struct psp_context *psp, if (!cmd) return -ENOMEM; /* Copy toc to psp firmware private buffer */ - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); + psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); @@ -417,31 +529,12 @@ static int psp_tmr_init(struct psp_context *psp) return ret; } -static int psp_clear_vf_fw(struct psp_context *psp) -{ - int ret; - struct psp_gfx_cmd_resp *cmd; - - if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) - return 0; - - cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); - if (!cmd) - return -ENOMEM; - - cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; - - ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); - kfree(cmd); - - return ret; -} - static bool psp_skip_tmr(struct psp_context *psp) { switch (psp->adev->asic_type) { case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: + case CHIP_ALDEBARAN: return true; default: return false; @@ -552,20 +645,43 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp, return ret; } -static int psp_boot_config_set(struct amdgpu_device *adev) +static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) +{ + struct psp_context *psp = &adev->psp; + struct psp_gfx_cmd_resp *cmd = psp->cmd; + int ret; + + if (amdgpu_sriov_vf(adev)) + return 0; + + memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); + + cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; + cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (!ret) { + *boot_cfg = + (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; + } + + return ret; +} + +static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) { struct psp_context *psp = &adev->psp; struct psp_gfx_cmd_resp *cmd = psp->cmd; - if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) return 0; memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; - cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; - cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; + cmd->cmd.boot_cfg.boot_config = boot_cfg; + cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); } @@ -621,8 +737,7 @@ static int psp_asd_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); + psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_ucode_size); @@ -696,6 +811,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, psp_prep_reg_prog_cmd_buf(cmd, reg, value); ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + DRM_ERROR("PSP failed to program reg id %d", reg); kfree(cmd); return ret; @@ -777,8 +894,7 @@ static int psp_xgmi_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); + psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, @@ -1034,8 +1150,14 @@ static int psp_ras_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); + psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); + + ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; + + if (psp->adev->gmc.xgmi.connected_to_cpu) + ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; + else + ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, @@ -1046,8 +1168,6 @@ static int psp_ras_load(struct psp_context *psp) ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); - ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; - if (!ret) { psp->ras.session_id = cmd->resp.session_id; @@ -1128,6 +1248,31 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) return ret; } +static int psp_ras_status_to_errno(struct amdgpu_device *adev, + enum ta_ras_status ras_status) +{ + int ret = -EINVAL; + + switch (ras_status) { + case TA_RAS_STATUS__SUCCESS: + ret = 0; + break; + case TA_RAS_STATUS__RESET_NEEDED: + ret = -EAGAIN; + break; + case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: + dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); + break; + case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: + dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); + break; + default: + dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); + } + + return ret; +} + int psp_ras_enable_features(struct psp_context *psp, union ta_ras_cmd_input *info, bool enable) { @@ -1151,7 +1296,7 @@ int psp_ras_enable_features(struct psp_context *psp, if (ret) return -EINVAL; - return ras_cmd->ras_status; + return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); } static int psp_ras_terminate(struct psp_context *psp) @@ -1184,19 +1329,62 @@ static int psp_ras_terminate(struct psp_context *psp) static int psp_ras_initialize(struct psp_context *psp) { int ret; + uint32_t boot_cfg = 0xFF; + struct amdgpu_device *adev = psp->adev; /* * TODO: bypass the initialize in sriov for now */ - if (amdgpu_sriov_vf(psp->adev)) + if (amdgpu_sriov_vf(adev)) return 0; - if (!psp->adev->psp.ta_ras_ucode_size || - !psp->adev->psp.ta_ras_start_addr) { - dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); + if (!adev->psp.ta_ras_ucode_size || + !adev->psp.ta_ras_start_addr) { + dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); return 0; } + if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { + /* query GECC enablement status from boot config + * boot_cfg: 1: GECC is enabled or 0: GECC is disabled + */ + ret = psp_boot_config_get(adev, &boot_cfg); + if (ret) + dev_warn(adev->dev, "PSP get boot config failed\n"); + + if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { + if (!boot_cfg) { + dev_info(adev->dev, "GECC is disabled\n"); + } else { + /* disable GECC in next boot cycle if ras is + * disabled by module parameter amdgpu_ras_enable + * and/or amdgpu_ras_mask, or boot_config_get call + * is failed + */ + ret = psp_boot_config_set(adev, 0); + if (ret) + dev_warn(adev->dev, "PSP set boot config failed\n"); + else + dev_warn(adev->dev, "GECC will be disabled in next boot cycle " + "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); + } + } else { + if (1 == boot_cfg) { + dev_info(adev->dev, "GECC is enabled\n"); + } else { + /* enable GECC in next boot cycle if it is disabled + * in boot config, or force enable GECC if failed to + * get boot configuration + */ + ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); + if (ret) + dev_warn(adev->dev, "PSP set boot config failed\n"); + else + dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); + } + } + } + if (!psp->ras.ras_initialized) { ret = psp_ras_init_shared_buf(psp); if (ret) @@ -1234,7 +1422,7 @@ int psp_ras_trigger_error(struct psp_context *psp, if (amdgpu_ras_intr_triggered()) return 0; - return ras_cmd->ras_status; + return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); } // ras end @@ -1271,9 +1459,8 @@ static int psp_hdcp_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, - psp->ta_hdcp_ucode_size); + psp_copy_fw(psp, psp->ta_hdcp_start_addr, + psp->ta_hdcp_ucode_size); psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, @@ -1423,8 +1610,7 @@ static int psp_dtm_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); + psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, @@ -1569,8 +1755,7 @@ static int psp_rap_load(struct psp_context *psp) if (!cmd) return -ENOMEM; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); + psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, @@ -1920,17 +2105,6 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_clear_vf_fw(psp); - if (ret) { - DRM_ERROR("PSP clear vf fw!\n"); - return ret; - } - - ret = psp_boot_config_set(adev); - if (ret) { - DRM_WARN("PSP set boot config@\n"); - } - ret = psp_tmr_init(psp); if (ret) { DRM_ERROR("PSP tmr init failed!\n"); @@ -2166,12 +2340,9 @@ static int psp_load_smu_fw(struct psp_context *psp) return 0; if ((amdgpu_in_reset(adev) && - ras && ras->supported && + ras && adev->ras_enabled && (adev->asic_type == CHIP_ARCTURUS || - adev->asic_type == CHIP_VEGA20)) || - (adev->in_runpm && - adev->asic_type >= CHIP_NAVI10 && - adev->asic_type <= CHIP_NAVI12)) { + adev->asic_type == CHIP_VEGA20))) { ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); if (ret) { DRM_WARN("Failed to set MP1 state prepare for reload\n"); @@ -2311,11 +2482,20 @@ static int psp_load_fw(struct amdgpu_device *adev) if (!psp->cmd) return -ENOMEM; - ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - AMDGPU_GEM_DOMAIN_GTT, - &psp->fw_pri_bo, - &psp->fw_pri_mc_addr, - &psp->fw_pri_buf); + if (amdgpu_sriov_vf(adev)) { + ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, + AMDGPU_GEM_DOMAIN_VRAM, + &psp->fw_pri_bo, + &psp->fw_pri_mc_addr, + &psp->fw_pri_buf); + } else { + ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, + AMDGPU_GEM_DOMAIN_GTT, + &psp->fw_pri_bo, + &psp->fw_pri_mc_addr, + &psp->fw_pri_buf); + } + if (ret) goto failed; @@ -2434,7 +2614,6 @@ static int psp_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct psp_context *psp = &adev->psp; - int ret; if (psp->adev->psp.ta_fw) { psp_ras_terminate(psp); @@ -2445,11 +2624,6 @@ static int psp_hw_fini(void *handle) } psp_asd_unload(psp); - ret = psp_clear_vf_fw(psp); - if (ret) { - DRM_ERROR("PSP clear vf fw!\n"); - return ret; - } psp_tmr_terminate(psp); psp_ring_destroy(psp, PSP_RING_TYPE__KM); @@ -2539,10 +2713,12 @@ static int psp_resume(void *handle) DRM_INFO("PSP is resuming...\n"); - ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); - if (ret) { - DRM_ERROR("Failed to process memory training!\n"); - return ret; + if (psp->mem_train_ctx.enable_mem_training) { + ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); + if (ret) { + DRM_ERROR("Failed to process memory training!\n"); + return ret; + } } mutex_lock(&adev->firmware.mutex); @@ -2694,7 +2870,7 @@ int psp_ring_cmd_submit(struct psp_context *psp, write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_value = index; - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_device_flush_hdp(adev, NULL); /* Update the write Pointer in DWORDs */ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; @@ -2726,7 +2902,7 @@ int psp_init_asd_microcode(struct psp_context *psp, asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); - adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); + adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); adev->psp.asd_start_addr = (uint8_t *)asd_hdr + le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); @@ -2762,7 +2938,7 @@ int psp_init_toc_microcode(struct psp_context *psp, toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); - adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); + adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version); adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); adev->psp.toc_start_addr = (uint8_t *)toc_hdr + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); @@ -2774,6 +2950,50 @@ out: return err; } +static int psp_init_sos_base_fw(struct amdgpu_device *adev) +{ + const struct psp_firmware_header_v1_0 *sos_hdr; + const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; + uint8_t *ucode_array_start_addr; + + sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; + ucode_array_start_addr = (uint8_t *)sos_hdr + + le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); + + if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { + adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); + adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version); + + adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes); + adev->psp.sys_start_addr = ucode_array_start_addr; + + adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes); + adev->psp.sos_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr->sos.offset_bytes); + } else { + /* Load alternate PSP SOS FW */ + sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; + + adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); + adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); + + adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); + adev->psp.sys_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); + + adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); + adev->psp.sos_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); + } + + if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) { + dev_warn(adev->dev, "PSP SOS FW not available"); + return -EINVAL; + } + + return 0; +} + int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) { @@ -2784,6 +3004,7 @@ int psp_init_sos_microcode(struct psp_context *psp, const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; int err = 0; + uint8_t *ucode_array_start_addr; if (!chip_name) { dev_err(adev->dev, "invalid chip name for sos microcode\n"); @@ -2800,47 +3021,45 @@ int psp_init_sos_microcode(struct psp_context *psp, goto out; sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; + ucode_array_start_addr = (uint8_t *)sos_hdr + + le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); amdgpu_ucode_print_psp_hdr(&sos_hdr->header); switch (sos_hdr->header.header_version_major) { case 1: - adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); - adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); - adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); - adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); - adev->psp.sys_start_addr = (uint8_t *)sos_hdr + - le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); - adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr->sos_offset_bytes); + err = psp_init_sos_base_fw(adev); + if (err) + goto out; + if (sos_hdr->header.header_version_minor == 1) { sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; - adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); + adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); - adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); + le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); + adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); + le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); } if (sos_hdr->header.header_version_minor == 2) { sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; - adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); + adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); + le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); } if (sos_hdr->header.header_version_minor == 3) { sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; - adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); - adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); - adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); - adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); - adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); - adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); - adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); - adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + - le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); + adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); + adev->psp.toc_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); + adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); + adev->psp.kdb_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); + adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); + adev->psp.spl_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); + adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); + adev->psp.rl_start_addr = ucode_array_start_addr + + le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); } break; default: @@ -3018,7 +3237,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, struct amdgpu_device *adev = drm_to_adev(ddev); void *cpu_addr; dma_addr_t dma_addr; - int ret; + int ret, idx; char fw_name[100]; const struct firmware *usbc_pd_fw; @@ -3027,6 +3246,9 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, return -EBUSY; } + if (!drm_dev_enter(ddev, &idx)) + return -ENODEV; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); if (ret) @@ -3058,16 +3280,29 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, rel_buf: dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); release_firmware(usbc_pd_fw); - fail: if (ret) { DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); - return ret; + count = ret; } + drm_dev_exit(idx); return count; } +void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) +{ + int idx; + + if (!drm_dev_enter(&psp->adev->ddev, &idx)) + return; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + memcpy(psp->fw_pri_buf, start_addr, bin_size); + + drm_dev_exit(idx); +} + static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, psp_usbc_pd_fw_sysfs_read, psp_usbc_pd_fw_sysfs_write); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 60aa99a39a74..3030ec24eb3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -225,6 +225,61 @@ struct psp_memory_training_context { enum psp_memory_training_init_flag init; u32 training_cnt; + bool enable_mem_training; +}; + +/** PSP runtime DB **/ +#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 +#define PSP_RUNTIME_DB_OFFSET 0x100000 +#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 +#define PSP_RUNTIME_DB_VER_1 0x0100 +#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 + +enum psp_runtime_entry_type { + PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, + PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, + PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ + PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ + PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ + PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ +}; + +/* PSP runtime DB header */ +struct psp_runtime_data_header { + /* determine the existence of runtime db */ + uint16_t cookie; + /* version of runtime db */ + uint16_t version; +}; + +/* PSP runtime DB entry */ +struct psp_runtime_entry { + /* type of runtime db entry */ + uint32_t entry_type; + /* offset of entry in bytes */ + uint16_t offset; + /* size of entry in bytes */ + uint16_t size; +}; + +/* PSP runtime DB directory */ +struct psp_runtime_data_directory { + /* number of valid entries */ + uint16_t entry_count; + /* db entries*/ + struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; +}; + +/* PSP runtime DB boot config feature bitmask */ +enum psp_runtime_boot_cfg_feature { + BOOT_CFG_FEATURE_GECC = 0x1, + BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, +}; + +/* PSP runtime DB boot config entry */ +struct psp_runtime_boot_cfg_entry { + uint32_t boot_cfg_bitmask; + uint32_t reserved; }; struct psp_context @@ -325,6 +380,8 @@ struct psp_context struct psp_securedisplay_context securedisplay_context; struct mutex mutex; struct psp_memory_training_context mem_train_ctx; + + uint32_t boot_cfg_bitmask; }; struct amdgpu_psp_funcs { @@ -424,4 +481,6 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp, int psp_load_fw_list(struct psp_context *psp, struct amdgpu_firmware_info **ucode_list, int ucode_count); +void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b0d2fc9454ca..c13b02caf8c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -27,12 +27,14 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_ras.h" #include "amdgpu_atomfirmware.h" #include "amdgpu_xgmi.h" #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" +#include "atom.h" static const char *RAS_FS_NAME = "ras"; @@ -320,11 +322,14 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, * "disable" requires only the block. * "enable" requires the block and error type. * "inject" requires the block, error type, address, and value. + * * The block is one of: umc, sdma, gfx, etc. * see ras_block_string[] for details + * * The error type is one of: ue, ce, where, * ue is multi-uncorrectable * ce is single-correctable + * * The sub-block is a the sub-block index, pass 0 if there is no sub-block. * The address and value are hexadecimal numbers, leading 0x is optional. * @@ -531,7 +536,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return NULL; if (head->block >= AMDGPU_RAS_BLOCK_COUNT) @@ -558,7 +563,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, struct ras_manager *obj; int i; - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return NULL; if (head) { @@ -585,36 +590,11 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, } /* obj end */ -static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, - const char* invoke_type, - const char* block_name, - enum ta_ras_status ret) -{ - switch (ret) { - case TA_RAS_STATUS__SUCCESS: - return; - case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: - dev_warn(adev->dev, - "RAS WARN: %s %s currently unavailable\n", - invoke_type, - block_name); - break; - default: - dev_err(adev->dev, - "RAS ERROR: %s %s error failed ret 0x%X\n", - invoke_type, - block_name, - ret); - } -} - /* feature ctl begin */ static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, - struct ras_common_if *head) + struct ras_common_if *head) { - struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - - return con->hw_supported & BIT(head->block); + return adev->ras_hw_enabled & BIT(head->block); } static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, @@ -658,11 +638,7 @@ static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, con->features |= BIT(head->block); } else { if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { - /* skip clean gfx ras context feature for VEGA20 Gaming. - * will clean later - */ - if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX))) - con->features &= ~BIT(head->block); + con->features &= ~BIT(head->block); put_obj(obj); } } @@ -708,15 +684,10 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, if (!amdgpu_ras_intr_triggered()) { ret = psp_ras_enable_features(&adev->psp, info, enable); if (ret) { - amdgpu_ras_parse_status_code(adev, - enable ? "enable":"disable", - ras_block_str(head->block), - (enum ta_ras_status)ret); - if (ret == TA_RAS_STATUS__RESET_NEEDED) - ret = -EAGAIN; - else - ret = -EINVAL; - + dev_err(adev->dev, "ras %s %s failed %d\n", + enable ? "enable":"disable", + ras_block_str(head->block), + ret); goto out; } } @@ -770,6 +741,10 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, con->features |= BIT(head->block); ret = amdgpu_ras_feature_enable(adev, head, 0); + + /* clean gfx block ras features flag */ + if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) + con->features &= ~BIT(head->block); } } else ret = amdgpu_ras_feature_enable(adev, head, enable); @@ -890,6 +865,11 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, adev->gmc.xgmi.ras_funcs->query_ras_error_count) adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data); break; + case AMDGPU_RAS_BLOCK__HDP: + if (adev->hdp.ras_funcs && + adev->hdp.ras_funcs->query_ras_error_count) + adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data); + break; default: break; } @@ -901,17 +881,42 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, info->ce_count = obj->err_data.ce_count; if (err_data.ce_count) { - dev_info(adev->dev, "%ld correctable hardware errors " + if (adev->smuio.funcs && + adev->smuio.funcs->get_socket_id && + adev->smuio.funcs->get_die_id) { + dev_info(adev->dev, "socket: %d, die: %d " + "%ld correctable hardware errors " + "detected in %s block, no user " + "action is needed.\n", + adev->smuio.funcs->get_socket_id(adev), + adev->smuio.funcs->get_die_id(adev), + obj->err_data.ce_count, + ras_block_str(info->head.block)); + } else { + dev_info(adev->dev, "%ld correctable hardware errors " "detected in %s block, no user " "action is needed.\n", obj->err_data.ce_count, ras_block_str(info->head.block)); + } } if (err_data.ue_count) { - dev_info(adev->dev, "%ld uncorrectable hardware errors " + if (adev->smuio.funcs && + adev->smuio.funcs->get_socket_id && + adev->smuio.funcs->get_die_id) { + dev_info(adev->dev, "socket: %d, die: %d " + "%ld uncorrectable hardware errors " + "detected in %s block\n", + adev->smuio.funcs->get_socket_id(adev), + adev->smuio.funcs->get_die_id(adev), + obj->err_data.ue_count, + ras_block_str(info->head.block)); + } else { + dev_info(adev->dev, "%ld uncorrectable hardware errors " "detected in %s block\n", obj->err_data.ue_count, ras_block_str(info->head.block)); + } } return 0; @@ -937,11 +942,20 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, if (adev->mmhub.ras_funcs && adev->mmhub.ras_funcs->reset_ras_error_count) adev->mmhub.ras_funcs->reset_ras_error_count(adev); + + if (adev->mmhub.ras_funcs && + adev->mmhub.ras_funcs->reset_ras_error_status) + adev->mmhub.ras_funcs->reset_ras_error_status(adev); break; case AMDGPU_RAS_BLOCK__SDMA: if (adev->sdma.funcs->reset_ras_error_count) adev->sdma.funcs->reset_ras_error_count(adev); break; + case AMDGPU_RAS_BLOCK__HDP: + if (adev->hdp.ras_funcs && + adev->hdp.ras_funcs->reset_ras_error_count) + adev->hdp.ras_funcs->reset_ras_error_count(adev); + break; default: break; } @@ -1022,38 +1036,44 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, ret = -EINVAL; } - amdgpu_ras_parse_status_code(adev, - "inject", - ras_block_str(info->head.block), - (enum ta_ras_status)ret); + if (ret) + dev_err(adev->dev, "ras inject %s failed %d\n", + ras_block_str(info->head.block), ret); return ret; } /* get the total error counts on all IPs */ -unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, - bool is_ce) +void amdgpu_ras_query_error_count(struct amdgpu_device *adev, + unsigned long *ce_count, + unsigned long *ue_count) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - struct ras_err_data data = {0, 0}; + unsigned long ce, ue; - if (!adev->ras_features || !con) - return 0; + if (!adev->ras_enabled || !con) + return; + ce = 0; + ue = 0; list_for_each_entry(obj, &con->head, node) { struct ras_query_if info = { .head = obj->head, }; if (amdgpu_ras_query_error_status(adev, &info)) - return 0; + return; - data.ce_count += info.ce_count; - data.ue_count += info.ue_count; + ce += info.ce_count; + ue += info.ue_count; } - return is_ce ? data.ce_count : data.ue_count; + if (ce_count) + *ce_count = ce; + + if (ue_count) + *ue_count = ue; } /* query/inject/cure end */ @@ -1265,8 +1285,8 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - struct dentry *dir; - struct drm_minor *minor = adev_to_drm(adev)->primary; + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *dir; dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, @@ -1275,6 +1295,8 @@ static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device * &amdgpu_ras_debugfs_eeprom_ops); debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, &con->bad_page_cnt_threshold); + debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); + debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); /* * After one uncorrectable error happens, usually GPU recovery will @@ -1561,7 +1583,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return; list_for_each_entry(obj, &con->head, node) { @@ -1611,7 +1633,7 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return; list_for_each_entry(obj, &con->head, node) { @@ -1925,7 +1947,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) bool exc_err_limit = false; int ret; - if (adev->ras_features && con) + if (adev->ras_enabled && con) data = &con->eh_data; else return 0; @@ -1962,6 +1984,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) ret = amdgpu_ras_load_bad_pages(adev); if (ret) goto free; + + if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); } return 0; @@ -2028,6 +2053,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) adev->asic_type == CHIP_SIENNA_CICHLID; } +/* + * this is workaround for vega20 workstation sku, + * force enable gfx ras, ignore vbios gfx ras flag + * due to GC EDC can not write + */ +static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + + if (!ctx) + return; + + if (strnstr(ctx->vbios_version, "D16406", + sizeof(ctx->vbios_version)) || + strnstr(ctx->vbios_version, "D36002", + sizeof(ctx->vbios_version))) + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); +} + /* * check hardware's ras ability which will be saved in hw_supported. * if hardware does not support ras, we can skip some ras initializtion and @@ -2037,11 +2081,9 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) * we have to initialize ras as normal. but need check if operation is * allowed or not in each function. */ -static void amdgpu_ras_check_supported(struct amdgpu_device *adev, - uint32_t *hw_supported, uint32_t *supported) +static void amdgpu_ras_check_supported(struct amdgpu_device *adev) { - *hw_supported = 0; - *supported = 0; + adev->ras_hw_enabled = adev->ras_enabled = 0; if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || !amdgpu_ras_asic_supported(adev)) @@ -2050,33 +2092,58 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev, if (!adev->gmc.xgmi.connected_to_cpu) { if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { dev_info(adev->dev, "MEM ECC is active.\n"); - *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | - 1 << AMDGPU_RAS_BLOCK__DF); + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | + 1 << AMDGPU_RAS_BLOCK__DF); } else { dev_info(adev->dev, "MEM ECC is not presented.\n"); } if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { dev_info(adev->dev, "SRAM ECC is active.\n"); - *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | - 1 << AMDGPU_RAS_BLOCK__DF); + adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | + 1 << AMDGPU_RAS_BLOCK__DF); } else { dev_info(adev->dev, "SRAM ECC is not presented.\n"); } } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX | - 1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | + 1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } - /* hw_supported needs to be aligned with RAS block mask. */ - *hw_supported &= AMDGPU_RAS_BLOCK_MASK; + amdgpu_ras_get_quirks(adev); - *supported = amdgpu_ras_enable == 0 ? - 0 : *hw_supported & amdgpu_ras_mask; - adev->ras_features = *supported; + /* hw_supported needs to be aligned with RAS block mask. */ + adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; + + adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : + adev->ras_hw_enabled & amdgpu_ras_mask; +} + +static void amdgpu_ras_counte_dw(struct work_struct *work) +{ + struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, + ras_counte_delay_work.work); + struct amdgpu_device *adev = con->adev; + struct drm_device *dev = adev_to_drm(adev); + unsigned long ce_count, ue_count; + int res; + + res = pm_runtime_get_sync(dev->dev); + if (res < 0) + goto Out; + + /* Cache new values. + */ + amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); + atomic_set(&con->ras_ce_count, ce_count); + atomic_set(&con->ras_ue_count, ue_count); + + pm_runtime_mark_last_busy(dev->dev); +Out: + pm_runtime_put_autosuspend(dev->dev); } int amdgpu_ras_init(struct amdgpu_device *adev) @@ -2093,17 +2160,22 @@ int amdgpu_ras_init(struct amdgpu_device *adev) if (!con) return -ENOMEM; + con->adev = adev; + INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); + atomic_set(&con->ras_ce_count, 0); + atomic_set(&con->ras_ue_count, 0); + con->objs = (struct ras_manager *)(con + 1); amdgpu_ras_set_context(adev, con); - amdgpu_ras_check_supported(adev, &con->hw_supported, - &con->supported); - if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) { + amdgpu_ras_check_supported(adev); + + if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { /* set gfx block ras context feature for VEGA20 Gaming * send ras disable cmd to ras ta during ras late init. */ - if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) { + if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); return 0; @@ -2153,8 +2225,9 @@ int amdgpu_ras_init(struct amdgpu_device *adev) } dev_info(adev->dev, "RAS INFO: ras initialized successfully, " - "hardware ability[%x] ras_mask[%x]\n", - con->hw_supported, con->supported); + "hardware ability[%x] ras_mask[%x]\n", + adev->ras_hw_enabled, adev->ras_enabled); + return 0; release_con: amdgpu_ras_set_context(adev, NULL); @@ -2163,7 +2236,7 @@ release_con: return r; } -static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) +int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) { if (adev->gmc.xgmi.connected_to_cpu) return 1; @@ -2195,6 +2268,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev, struct ras_fs_if *fs_info, struct ras_ih_if *ih_info) { + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + unsigned long ue_count, ce_count; int r; /* disable RAS feature per IP block if it is not supported */ @@ -2235,6 +2310,12 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev, if (r) goto sysfs; + /* Those are the cached values at init. + */ + amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); + atomic_set(&con->ras_ce_count, ce_count); + atomic_set(&con->ras_ue_count, ue_count); + return 0; cleanup: amdgpu_ras_sysfs_remove(adev, ras_block); @@ -2268,7 +2349,7 @@ void amdgpu_ras_resume(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj, *tmp; - if (!adev->ras_features || !con) { + if (!adev->ras_enabled || !con) { /* clean ras context for VEGA20 Gaming after send ras disable cmd */ amdgpu_release_ras_context(adev); @@ -2314,7 +2395,7 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return; amdgpu_ras_disable_all_features(adev, 0); @@ -2328,9 +2409,10 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return 0; + /* Need disable ras on all IPs here before ip [hw/sw]fini */ amdgpu_ras_disable_all_features(adev, 0); amdgpu_ras_recovery_fini(adev); @@ -2341,7 +2423,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - if (!adev->ras_features || !con) + if (!adev->ras_enabled || !con) return 0; amdgpu_ras_fs_fini(adev); @@ -2352,6 +2434,8 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) if (con->features) amdgpu_ras_disable_all_features(adev, 1); + cancel_delayed_work_sync(&con->ras_counte_delay_work); + amdgpu_ras_set_context(adev, NULL); kfree(con); @@ -2360,10 +2444,8 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) { - uint32_t hw_supported, supported; - - amdgpu_ras_check_supported(adev, &hw_supported, &supported); - if (!hw_supported) + amdgpu_ras_check_supported(adev); + if (!adev->ras_hw_enabled) return; if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { @@ -2392,7 +2474,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) if (!con) return; - if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { + if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); amdgpu_ras_set_context(adev, NULL); kfree(con); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 60df268a0c66..256cea5d34f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -313,9 +313,6 @@ struct ras_common_if { struct amdgpu_ras { /* ras infrastructure */ /* for ras itself. */ - uint32_t hw_supported; - /* for IP to check its ras ability. */ - uint32_t supported; uint32_t features; struct list_head head; /* sysfs */ @@ -343,6 +340,11 @@ struct amdgpu_ras { /* disable ras error count harvest in recovery */ bool disable_ras_err_cnt_harvest; + + /* RAS count errors delayed work */ + struct delayed_work ras_counte_delay_work; + atomic_t ras_ue_count; + atomic_t ras_ce_count; }; struct ras_fs_data { @@ -478,7 +480,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, if (block >= AMDGPU_RAS_BLOCK_COUNT) return 0; - return ras && (ras->supported & (1 << block)); + return ras && (adev->ras_enabled & (1 << block)); } int amdgpu_ras_recovery_init(struct amdgpu_device *adev); @@ -488,8 +490,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, void amdgpu_ras_resume(struct amdgpu_device *adev); void amdgpu_ras_suspend(struct amdgpu_device *adev); -unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, - bool is_ce); +void amdgpu_ras_query_error_count(struct amdgpu_device *adev, + unsigned long *ce_count, + unsigned long *ue_count); /* error handling functions */ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, @@ -628,4 +631,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); void amdgpu_release_ras_context(struct amdgpu_device *adev); + +int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h index 40f2adf305bc..59e0fefb15aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h @@ -28,6 +28,7 @@ #include #include +#include /* state back for walking over vram_mgr and gtt_mgr allocations */ struct amdgpu_res_cursor { @@ -53,7 +54,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res, { struct drm_mm_node *node; - if (!res || !res->mm_node) { + if (!res) { cur->start = start; cur->size = size; cur->remaining = size; @@ -63,7 +64,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res, BUG_ON(start + size > res->num_pages << PAGE_SHIFT); - node = res->mm_node; + node = to_ttm_range_mgr_node(res)->mm_nodes; while (start >= node->size << PAGE_SHIFT) start -= node++->size << PAGE_SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 688624ebe421..7b634a1517f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -158,6 +158,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) * @irq_src: interrupt source to use for this ring * @irq_type: interrupt type to use for this ring * @hw_prio: ring priority (NORMAL/HIGH) + * @sched_score: optional score atomic shared with other schedulers * * Initialize the driver information for the selected ring (all asics). * Returns 0 on success, error on failure. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index ca1622835296..e7d3d0dbdd96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -107,7 +107,8 @@ struct amdgpu_fence_driver { }; int amdgpu_fence_driver_init(struct amdgpu_device *adev); -void amdgpu_fence_driver_fini(struct amdgpu_device *adev); +void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev); +void amdgpu_fence_driver_fini_sw(struct amdgpu_device *adev); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 4fc2ce8ce8ab..7a4775ab6804 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs { void (*reset)(struct amdgpu_device *adev); void (*start)(struct amdgpu_device *adev); void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid); - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag); - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag); + void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip); + u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip); bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c index 5369c8dd0764..123453999093 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c @@ -86,6 +86,8 @@ void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedispla (*cmd)->cmd_id = command_id; } +#if defined(CONFIG_DEBUG_FS) + static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) { @@ -162,6 +164,8 @@ static const struct file_operations amdgpu_securedisplay_debugfs_ops = { .llseek = default_llseek }; +#endif + void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h index b860ec913ac5..484bb3dcec47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h @@ -29,6 +29,7 @@ struct amdgpu_smuio_funcs { void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable); void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags); u32 (*get_die_id)(struct amdgpu_device *adev); + u32 (*get_socket_id)(struct amdgpu_device *adev); bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev); }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 4e558632a5d2..1b2ceccaf5b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -210,10 +210,10 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, return -EINVAL; /* always sync to the exclusive fence */ - f = dma_resv_get_excl(resv); + f = dma_resv_excl_fence(resv); r = amdgpu_sync_fence(sync, f); - flist = dma_resv_get_list(resv); + flist = dma_resv_shared_list(resv); if (!flist || r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 792d20261846..d855cb53c7e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -127,8 +127,8 @@ TRACE_EVENT(amdgpu_bo_create, TP_fast_assign( __entry->bo = bo; - __entry->pages = bo->tbo.mem.num_pages; - __entry->type = bo->tbo.mem.mem_type; + __entry->pages = bo->tbo.resource->num_pages; + __entry->type = bo->tbo.resource->mem_type; __entry->prefer = bo->preferred_domains; __entry->allow = bo->allowed_domains; __entry->visible = bo->flags; @@ -176,10 +176,10 @@ TRACE_EVENT(amdgpu_cs_ioctl, TP_fast_assign( __entry->sched_job_id = job->base.id; - __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring, to_amdgpu_ring(job->base.sched)->name) + __assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", @@ -201,10 +201,10 @@ TRACE_EVENT(amdgpu_sched_run_job, TP_fast_assign( __entry->sched_job_id = job->base.id; - __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring, to_amdgpu_ring(job->base.sched)->name) + __assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", @@ -229,7 +229,7 @@ TRACE_EVENT(amdgpu_vm_grab_id, TP_fast_assign( __entry->pasid = vm->pasid; - __assign_str(ring, ring->name) + __assign_str(ring, ring->name); __entry->vmid = job->vmid; __entry->vm_hub = ring->funcs->vmhub, __entry->pd_addr = job->vm_pd_addr; @@ -424,7 +424,7 @@ TRACE_EVENT(amdgpu_vm_flush, ), TP_fast_assign( - __assign_str(ring, ring->name) + __assign_str(ring, ring->name); __entry->vmid = vmid; __entry->vm_hub = ring->funcs->vmhub; __entry->pd_addr = pd_addr; @@ -525,7 +525,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, ), TP_fast_assign( - __assign_str(ring, sched_job->base.sched->name) + __assign_str(ring, sched_job->base.sched->name); __entry->id = sched_job->base.id; __entry->fence = fence; __entry->ctx = fence->context; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 61c4fb1b87fe..cdfc20b0b2eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -32,7 +32,6 @@ #include #include -#include #include #include #include @@ -46,6 +45,7 @@ #include #include #include +#include #include @@ -112,7 +112,22 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } abo = ttm_to_amdgpu_bo(bo); - switch (bo->mem.mem_type) { + if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { + struct dma_fence *fence; + struct dma_resv *resv = &bo->base._resv; + + rcu_read_lock(); + fence = rcu_dereference(resv->fence_excl); + if (fence && !fence->ops->signaled) + dma_fence_enable_sw_signaling(fence); + + placement->num_placement = 0; + placement->num_busy_placement = 0; + rcu_read_unlock(); + return; + } + + switch (bo->resource->mem_type) { case AMDGPU_PL_GDS: case AMDGPU_PL_GWS: case AMDGPU_PL_OA: @@ -145,6 +160,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } break; case TTM_PL_TT: + case AMDGPU_PL_PREEMPT: default: amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); break; @@ -152,32 +168,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, *placement = abo->placement; } -/** - * amdgpu_verify_access - Verify access for a mmap call - * - * @bo: The buffer object to map - * @filp: The file pointer from the process performing the mmap - * - * This is called by ttm_bo_mmap() to verify whether a process - * has the right to mmap a BO to their process space. - */ -static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) -{ - struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); - - /* - * Don't verify access for KFD BOs. They don't have a GEM - * object associated with them. - */ - if (abo->kfd_bo) - return 0; - - if (amdgpu_ttm_tt_get_usermm(bo->ttm)) - return -EPERM; - return drm_vma_node_verify_access(&abo->tbo.base.vma_node, - filp->private_data); -} - /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @bo: buffer object to map @@ -211,6 +201,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); + BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); /* Map only what can't be accessed directly */ if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { @@ -288,7 +279,7 @@ error_free: } /** - * amdgpu_copy_ttm_mem_to_mem - Helper function for copy + * amdgpu_ttm_copy_mem_to_mem - Helper function for copy * @adev: amdgpu device * @src: buffer/address where to read from * @dst: buffer/address where to write to @@ -471,10 +462,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, { struct amdgpu_device *adev; struct amdgpu_bo *abo; - struct ttm_resource *old_mem = &bo->mem; + struct ttm_resource *old_mem = bo->resource; int r; - if (new_mem->mem_type == TTM_PL_TT) { + if (new_mem->mem_type == TTM_PL_TT || + new_mem->mem_type == AMDGPU_PL_PREEMPT) { r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); if (r) return r; @@ -492,18 +484,20 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, goto out; } if (old_mem->mem_type == TTM_PL_SYSTEM && - new_mem->mem_type == TTM_PL_TT) { + (new_mem->mem_type == TTM_PL_TT || + new_mem->mem_type == AMDGPU_PL_PREEMPT)) { ttm_bo_move_null(bo, new_mem); goto out; } - if (old_mem->mem_type == TTM_PL_TT && + if ((old_mem->mem_type == TTM_PL_TT || + old_mem->mem_type == AMDGPU_PL_PREEMPT) && new_mem->mem_type == TTM_PL_SYSTEM) { r = ttm_bo_wait_ctx(bo, ctx); if (r) return r; amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); - ttm_resource_free(bo, &bo->mem); + ttm_resource_free(bo, &bo->resource); ttm_bo_assign_mem(bo, new_mem); goto out; } @@ -570,10 +564,10 @@ out: * * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() */ -static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem) +static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, + struct ttm_resource *mem) { struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); - struct drm_mm_node *mm_node = mem->mm_node; size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; switch (mem->mem_type) { @@ -581,18 +575,16 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resourc /* system memory */ return 0; case TTM_PL_TT: + case AMDGPU_PL_PREEMPT: break; case TTM_PL_VRAM: mem->bus.offset = mem->start << PAGE_SHIFT; /* check if it's visible */ if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) return -EINVAL; - /* Only physically contiguous buffers apply. In a contiguous - * buffer, size of the first mm_node would match the number of - * pages in ttm_resource. - */ + if (adev->mman.aper_base_kaddr && - (mm_node->size == mem->num_pages)) + mem->placement & TTM_PL_FLAG_CONTIGUOUS) mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + mem->bus.offset; @@ -615,7 +607,8 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_res_cursor cursor; - amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor); + amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, + &cursor); return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; } @@ -670,10 +663,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) struct amdgpu_ttm_tt *gtt = (void *)ttm; unsigned long start = gtt->userptr; struct vm_area_struct *vma; - struct hmm_range *range; - unsigned long timeout; struct mm_struct *mm; - unsigned long i; + bool readonly; int r = 0; mm = bo->notifier.mm; @@ -689,25 +680,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) if (!mmget_not_zero(mm)) /* Happens during process shutdown */ return -ESRCH; - range = kzalloc(sizeof(*range), GFP_KERNEL); - if (unlikely(!range)) { - r = -ENOMEM; - goto out; - } - range->notifier = &bo->notifier; - range->start = bo->notifier.interval_tree.start; - range->end = bo->notifier.interval_tree.last + 1; - range->default_flags = HMM_PFN_REQ_FAULT; - if (!amdgpu_ttm_tt_is_readonly(ttm)) - range->default_flags |= HMM_PFN_REQ_WRITE; - - range->hmm_pfns = kvmalloc_array(ttm->num_pages, - sizeof(*range->hmm_pfns), GFP_KERNEL); - if (unlikely(!range->hmm_pfns)) { - r = -ENOMEM; - goto out_free_ranges; - } - mmap_read_lock(mm); vma = vma_lookup(mm, start); if (unlikely(!vma)) { @@ -719,46 +691,15 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) r = -EPERM; goto out_unlock; } - mmap_read_unlock(mm); - timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); - -retry: - range->notifier_seq = mmu_interval_read_begin(&bo->notifier); - - mmap_read_lock(mm); - r = hmm_range_fault(range); - mmap_read_unlock(mm); - if (unlikely(r)) { - /* - * FIXME: This timeout should encompass the retry from - * mmu_interval_read_retry() as well. - */ - if (r == -EBUSY && !time_after(jiffies, timeout)) - goto retry; - goto out_free_pfns; - } - - /* - * Due to default_flags, all pages are HMM_PFN_VALID or - * hmm_range_fault() fails. FIXME: The pages cannot be touched outside - * the notifier_lock, and mmu_interval_read_retry() must be done first. - */ - for (i = 0; i < ttm->num_pages; i++) - pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); - - gtt->range = range; - mmput(mm); - - return 0; + readonly = amdgpu_ttm_tt_is_readonly(ttm); + r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, + ttm->num_pages, >t->range, readonly, + true); out_unlock: mmap_read_unlock(mm); -out_free_pfns: - kvfree(range->hmm_pfns); -out_free_ranges: - kfree(range); -out: mmput(mm); + return r; } @@ -787,10 +728,7 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) * FIXME: Must always hold notifier_lock for this, and must * not ignore the return code. */ - r = mmu_interval_read_retry(gtt->range->notifier, - gtt->range->notifier_seq); - kvfree(gtt->range->hmm_pfns); - kfree(gtt->range); + r = amdgpu_hmm_range_get_pages_done(gtt->range); gtt->range = NULL; } @@ -903,7 +841,7 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, uint64_t page_idx = 1; r = amdgpu_gart_bind(adev, gtt->offset, page_idx, - ttm->pages, gtt->ttm.dma_address, flags); + gtt->ttm.dma_address, flags); if (r) goto gart_bind_fail; @@ -917,11 +855,10 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, r = amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT), ttm->num_pages - page_idx, - &ttm->pages[page_idx], &(gtt->ttm.dma_address[page_idx]), flags); } else { r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, - ttm->pages, gtt->ttm.dma_address, flags); + gtt->ttm.dma_address, flags); } gart_bind_fail: @@ -959,7 +896,23 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, DRM_ERROR("failed to pin userptr\n"); return r; } + } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) { + if (!ttm->sg) { + struct dma_buf_attachment *attach; + struct sg_table *sgt; + + attach = gtt->gobj->import_attach; + sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); + if (IS_ERR(sgt)) + return PTR_ERR(sgt); + + ttm->sg = sgt; + } + + drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, + ttm->num_pages); } + if (!ttm->num_pages) { WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", ttm->num_pages, bo_mem, ttm); @@ -981,7 +934,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, /* bind pages into GART page tables */ gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, - ttm->pages, gtt->ttm.dma_address, flags); + gtt->ttm.dma_address, flags); if (r) DRM_ERROR("failed to bind %u pages at 0x%08llX\n", @@ -1003,51 +956,50 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; - struct ttm_resource tmp; struct ttm_placement placement; struct ttm_place placements; + struct ttm_resource *tmp; uint64_t addr, flags; int r; - if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) + if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) return 0; addr = amdgpu_gmc_agp_addr(bo); if (addr != AMDGPU_BO_INVALID_OFFSET) { - bo->mem.start = addr >> PAGE_SHIFT; - } else { - - /* allocate GART space */ - tmp = bo->mem; - tmp.mm_node = NULL; - placement.num_placement = 1; - placement.placement = &placements; - placement.num_busy_placement = 1; - placement.busy_placement = &placements; - placements.fpfn = 0; - placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; - placements.mem_type = TTM_PL_TT; - placements.flags = bo->mem.placement; - - r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); - if (unlikely(r)) - return r; - - /* compute PTE flags for this buffer object */ - flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); - - /* Bind pages */ - gtt->offset = (u64)tmp.start << PAGE_SHIFT; - r = amdgpu_ttm_gart_bind(adev, bo, flags); - if (unlikely(r)) { - ttm_resource_free(bo, &tmp); - return r; - } - - ttm_resource_free(bo, &bo->mem); - bo->mem = tmp; + bo->resource->start = addr >> PAGE_SHIFT; + return 0; } + /* allocate GART space */ + placement.num_placement = 1; + placement.placement = &placements; + placement.num_busy_placement = 1; + placement.busy_placement = &placements; + placements.fpfn = 0; + placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; + placements.mem_type = TTM_PL_TT; + placements.flags = bo->resource->placement; + + r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); + if (unlikely(r)) + return r; + + /* compute PTE flags for this buffer object */ + flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); + + /* Bind pages */ + gtt->offset = (u64)tmp->start << PAGE_SHIFT; + r = amdgpu_ttm_gart_bind(adev, bo, flags); + if (unlikely(r)) { + ttm_resource_free(bo, &tmp); + return r; + } + + amdgpu_gart_invalidate_tlb(adev); + ttm_resource_free(bo, &bo->resource); + ttm_bo_assign_mem(bo, tmp); + return 0; } @@ -1066,7 +1018,7 @@ int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) if (!tbo->ttm) return 0; - flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); + flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); r = amdgpu_ttm_gart_bind(adev, tbo, flags); return r; @@ -1086,8 +1038,15 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, int r; /* if the pages have userptr pinning then clear that first */ - if (gtt->userptr) + if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); + } else if (ttm->sg && gtt->gobj->import_attach) { + struct dma_buf_attachment *attach; + + attach = gtt->gobj->import_attach; + dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); + ttm->sg = NULL; + } if (!gtt->bound) return; @@ -1169,28 +1128,11 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); if (!ttm->sg) return -ENOMEM; - - ttm->page_flags |= TTM_PAGE_FLAG_SG; return 0; } - if (ttm->page_flags & TTM_PAGE_FLAG_SG) { - if (!ttm->sg) { - struct dma_buf_attachment *attach; - struct sg_table *sgt; - - attach = gtt->gobj->import_attach; - sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); - if (IS_ERR(sgt)) - return PTR_ERR(sgt); - - ttm->sg = sgt; - } - - drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, - ttm->num_pages); + if (ttm->page_flags & TTM_PAGE_FLAG_SG) return 0; - } return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); } @@ -1211,16 +1153,6 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, amdgpu_ttm_tt_set_user_pages(ttm, NULL); kfree(ttm->sg); ttm->sg = NULL; - ttm->page_flags &= ~TTM_PAGE_FLAG_SG; - return; - } - - if (ttm->sg && gtt->gobj->import_attach) { - struct dma_buf_attachment *attach; - - attach = gtt->gobj->import_attach; - dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); - ttm->sg = NULL; return; } @@ -1254,6 +1186,9 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, return -ENOMEM; } + /* Set TTM_PAGE_FLAG_SG before populate but after create. */ + bo->ttm->page_flags |= TTM_PAGE_FLAG_SG; + gtt = (void *)bo->ttm; gtt->userptr = addr; gtt->userflags = flags; @@ -1347,7 +1282,8 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) if (mem && mem->mem_type != TTM_PL_SYSTEM) flags |= AMDGPU_PTE_VALID; - if (mem && mem->mem_type == TTM_PL_TT) { + if (mem && (mem->mem_type == TTM_PL_TT || + mem->mem_type == AMDGPU_PL_PREEMPT)) { flags |= AMDGPU_PTE_SYSTEM; if (ttm->caching == ttm_cached) @@ -1396,12 +1332,16 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, const struct ttm_place *place) { - unsigned long num_pages = bo->mem.num_pages; + unsigned long num_pages = bo->resource->num_pages; struct amdgpu_res_cursor cursor; struct dma_resv_list *flist; struct dma_fence *f; int i; + /* Swapout? */ + if (bo->resource->mem_type == TTM_PL_SYSTEM) + return true; + if (bo->type == ttm_bo_type_kernel && !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) return false; @@ -1410,7 +1350,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * If true, then return false as any KFD process needs all its BOs to * be resident to run successfully */ - flist = dma_resv_get_list(bo->base.resv); + flist = dma_resv_shared_list(bo->base.resv); if (flist) { for (i = 0; i < flist->shared_count; ++i) { f = rcu_dereference_protected(flist->shared[i], @@ -1420,7 +1360,16 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, } } - switch (bo->mem.mem_type) { + switch (bo->resource->mem_type) { + case AMDGPU_PL_PREEMPT: + /* Preemptible BOs don't own system resources managed by the + * driver (pages, VRAM, GART space). They point to resources + * owned by someone else (e.g. pageable memory in user mode + * or a DMABuf). They are used in a preemptible context so we + * can guarantee no deadlocks and good QoS in case of MMU + * notifiers or DMABuf move notifiers from the resource owner. + */ + return false; case TTM_PL_TT: if (amdgpu_bo_is_amdgpu_bo(bo) && amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) @@ -1429,7 +1378,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, case TTM_PL_VRAM: /* Check each drm MM node individually */ - amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT, + amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, &cursor); while (cursor.remaining) { if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) @@ -1471,10 +1420,10 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, uint32_t value = 0; int ret = 0; - if (bo->mem.mem_type != TTM_PL_VRAM) + if (bo->resource->mem_type != TTM_PL_VRAM) return -EIO; - amdgpu_res_first(&bo->mem, offset, len, &cursor); + amdgpu_res_first(bo->resource, offset, len, &cursor); while (cursor.remaining) { uint64_t aligned_pos = cursor.start & ~(uint64_t)3; uint64_t bytes = 4 - (cursor.start & 3); @@ -1530,7 +1479,6 @@ static struct ttm_device_funcs amdgpu_bo_driver = { .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, - .verify_access = &amdgpu_verify_access, .delete_mem_notify = &amdgpu_bo_delete_mem_notify, .release_notify = &amdgpu_bo_release_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, @@ -1633,11 +1581,8 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) bool mem_train_support = false; if (!amdgpu_sriov_vf(adev)) { - ret = amdgpu_mem_train_support(adev); - if (ret == 1) + if (amdgpu_atomfirmware_mem_training_supported(adev)) mem_train_support = true; - else if (ret == -1) - return -EINVAL; else DRM_DEBUG("memory training does not support!\n"); } @@ -1779,6 +1724,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) NULL); if (r) return r; + r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, + adev->mman.stolen_reserved_size, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->mman.stolen_reserved_memory, + NULL); + if (r) + return r; DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); @@ -1805,6 +1757,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of GTT memory ready.\n", (unsigned)(gtt_size / (1024 * 1024))); + /* Initialize preemptible memory pool */ + r = amdgpu_preempt_mgr_init(adev); + if (r) { + DRM_ERROR("Failed initializing PREEMPT heap.\n"); + return r; + } + /* Initialize various on-chip memory pools */ r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); if (r) { @@ -1841,14 +1800,14 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); /* return the IP Discovery TMR memory back to VRAM */ amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); + if (adev->mman.stolen_reserved_size) + amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, + NULL, NULL); amdgpu_ttm_fw_reserve_vram_fini(adev); - if (adev->mman.aper_base_kaddr) - iounmap(adev->mman.aper_base_kaddr); - adev->mman.aper_base_kaddr = NULL; - amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); + amdgpu_preempt_mgr_fini(adev); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); @@ -1905,50 +1864,6 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) adev->mman.buffer_funcs_enabled = enable; } -static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) -{ - struct ttm_buffer_object *bo = vmf->vma->vm_private_data; - vm_fault_t ret; - - ret = ttm_bo_vm_reserve(bo, vmf); - if (ret) - return ret; - - ret = amdgpu_bo_fault_reserve_notify(bo); - if (ret) - goto unlock; - - ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT, 1); - if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) - return ret; - -unlock: - dma_resv_unlock(bo->base.resv); - return ret; -} - -static const struct vm_operations_struct amdgpu_ttm_vm_ops = { - .fault = amdgpu_ttm_fault, - .open = ttm_bo_vm_open, - .close = ttm_bo_vm_close, - .access = ttm_bo_vm_access -}; - -int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) -{ - struct drm_file *file_priv = filp->private_data; - struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); - int r; - - r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); - if (unlikely(r != 0)) - return r; - - vma->vm_ops = &amdgpu_ttm_vm_ops; - return 0; -} - int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, @@ -2043,16 +1958,21 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, return -EINVAL; } - if (bo->tbo.mem.mem_type == TTM_PL_TT) { + if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { + DRM_ERROR("Trying to clear preemptible memory.\n"); + return -EINVAL; + } + + if (bo->tbo.resource->mem_type == TTM_PL_TT) { r = amdgpu_ttm_alloc_gart(&bo->tbo); if (r) return r; } - num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT; + num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; num_loops = 0; - amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); + amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); while (cursor.remaining) { num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); amdgpu_res_next(&cursor, cursor.size); @@ -2077,12 +1997,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, } } - amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor); + amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); while (cursor.remaining) { uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); uint64_t dst_addr = cursor.start; - dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); + dst_addr += amdgpu_ttm_domain_start(adev, + bo->tbo.resource->mem_type); amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, cur_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 9e38475e0f8d..e69f3e8e06e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -31,17 +31,13 @@ #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) +#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 #define AMDGPU_POISON 0xd0bed0be -struct amdgpu_vram_reservation { - struct list_head node; - struct drm_mm_node mm_node; -}; - struct amdgpu_vram_mgr { struct ttm_resource_manager manager; struct drm_mm mm; @@ -59,6 +55,11 @@ struct amdgpu_gtt_mgr { atomic64_t available; }; +struct amdgpu_preempt_mgr { + struct ttm_resource_manager manager; + atomic64_t used; +}; + struct amdgpu_mman { struct ttm_device bdev; bool initialized; @@ -75,6 +76,7 @@ struct amdgpu_mman { struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; + struct amdgpu_preempt_mgr preempt_mgr; uint64_t stolen_vga_size; struct amdgpu_bo *stolen_vga_memory; @@ -82,6 +84,10 @@ struct amdgpu_mman { struct amdgpu_bo *stolen_extended_memory; bool keep_stolen_vga_memory; + struct amdgpu_bo *stolen_reserved_memory; + uint64_t stolen_reserved_offset; + uint64_t stolen_reserved_size; + /* discovery */ uint8_t *discovery_bin; uint32_t discovery_tmr_size; @@ -102,6 +108,8 @@ struct amdgpu_copy_mem { int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); +int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); +void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); int amdgpu_vram_mgr_init(struct amdgpu_device *adev); void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); @@ -109,6 +117,8 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man); int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man); +uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); + u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, struct ttm_resource *mem, @@ -147,7 +157,6 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence); -int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 9733224117e3..2834981f8c08 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -257,36 +257,36 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) container_of(hdr, struct psp_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", - le32_to_cpu(psp_hdr->ucode_feature_version)); + le32_to_cpu(psp_hdr->sos.fw_version)); DRM_DEBUG("sos_offset_bytes: %u\n", - le32_to_cpu(psp_hdr->sos_offset_bytes)); + le32_to_cpu(psp_hdr->sos.offset_bytes)); DRM_DEBUG("sos_size_bytes: %u\n", - le32_to_cpu(psp_hdr->sos_size_bytes)); + le32_to_cpu(psp_hdr->sos.size_bytes)); if (version_minor == 1) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); DRM_DEBUG("toc_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_1->toc_header_version)); + le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); + le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); + le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_1->kdb_header_version)); + le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes)); + le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); + le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); } if (version_minor == 2) { const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); DRM_DEBUG("kdb_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_2->kdb_header_version)); + le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes)); + le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes)); + le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); } if (version_minor == 3) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = @@ -294,23 +294,23 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); DRM_DEBUG("toc_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version)); + le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes)); + le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes)); + le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version)); + le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes)); + le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes)); + le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); DRM_DEBUG("spl_header_version: %u\n", - le32_to_cpu(psp_hdr_v1_3->spl_header_version)); + le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); DRM_DEBUG("spl_offset_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes)); + le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); DRM_DEBUG("spl_size_bytes: %u\n", - le32_to_cpu(psp_hdr_v1_3->spl_size_bytes)); + le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); } } else { DRM_ERROR("Unknown PSP ucode version: %u.%u\n", @@ -403,6 +403,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: case CHIP_ALDEBARAN: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 2c42874f7784..270309e7f5f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -71,43 +71,39 @@ struct smc_firmware_header_v2_1 { uint32_t pptable_entry_offset; }; +struct psp_fw_bin_desc { + uint32_t fw_version; + uint32_t offset_bytes; + uint32_t size_bytes; +}; + /* version_major=1, version_minor=0 */ struct psp_firmware_header_v1_0 { struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t sos_offset_bytes; - uint32_t sos_size_bytes; + struct psp_fw_bin_desc sos; }; /* version_major=1, version_minor=1 */ struct psp_firmware_header_v1_1 { struct psp_firmware_header_v1_0 v1_0; - uint32_t toc_header_version; - uint32_t toc_offset_bytes; - uint32_t toc_size_bytes; - uint32_t kdb_header_version; - uint32_t kdb_offset_bytes; - uint32_t kdb_size_bytes; + struct psp_fw_bin_desc toc; + struct psp_fw_bin_desc kdb; }; /* version_major=1, version_minor=2 */ struct psp_firmware_header_v1_2 { struct psp_firmware_header_v1_0 v1_0; - uint32_t reserve[3]; - uint32_t kdb_header_version; - uint32_t kdb_offset_bytes; - uint32_t kdb_size_bytes; + struct psp_fw_bin_desc res; + struct psp_fw_bin_desc kdb; }; /* version_major=1, version_minor=3 */ struct psp_firmware_header_v1_3 { struct psp_firmware_header_v1_1 v1_1; - uint32_t spl_header_version; - uint32_t spl_offset_bytes; - uint32_t spl_size_bytes; - uint32_t rl_header_version; - uint32_t rl_offset_bytes; - uint32_t rl_size_bytes; + struct psp_fw_bin_desc spl; + struct psp_fw_bin_desc rl; + struct psp_fw_bin_desc sys_drv_aux; + struct psp_fw_bin_desc sos_aux; }; /* version_major=1, version_minor=0 */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index ea6f99be070b..f4489773715e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -94,6 +94,7 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); if (adev->umc.ras_funcs && @@ -131,6 +132,9 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, amdgpu_ras_add_bad_pages(adev, err_data->err_addr, err_data->err_addr_cnt); amdgpu_ras_save_bad_pages(adev); + + if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); } amdgpu_ras_reset_gpu(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h index bbcccf53080d..e5a75fb788dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h @@ -21,6 +21,11 @@ #ifndef __AMDGPU_UMC_H__ #define __AMDGPU_UMC_H__ +/* + * (addr / 256) * 4096, the higher 26 bits in ErrorAddr + * is the index of 4KB block + */ +#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) /* * (addr / 256) * 8192, the higher 26 bits in ErrorAddr * is the index of 8KB block diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index c6dbc0801604..0f576f294d8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -32,6 +32,7 @@ #include #include +#include #include "amdgpu.h" #include "amdgpu_pm.h" @@ -375,7 +376,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) { unsigned size; void *ptr; - int i, j; + int i, j, idx; bool in_ras_intr = amdgpu_ras_intr_triggered(); cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -403,11 +404,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) if (!adev->uvd.inst[j].saved_bo) return -ENOMEM; - /* re-write 0 since err_event_athub will corrupt VCPU buffer */ - if (in_ras_intr) - memset(adev->uvd.inst[j].saved_bo, 0, size); - else - memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); + if (drm_dev_enter(&adev->ddev, &idx)) { + /* re-write 0 since err_event_athub will corrupt VCPU buffer */ + if (in_ras_intr) + memset(adev->uvd.inst[j].saved_bo, 0, size); + else + memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); + + drm_dev_exit(idx); + } } if (in_ras_intr) @@ -420,7 +425,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) { unsigned size; void *ptr; - int i; + int i, idx; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) @@ -432,7 +437,10 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) ptr = adev->uvd.inst[i].cpu_addr; if (adev->uvd.inst[i].saved_bo != NULL) { - memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); + drm_dev_exit(idx); + } kvfree(adev->uvd.inst[i].saved_bo); adev->uvd.inst[i].saved_bo = NULL; } else { @@ -442,8 +450,11 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) hdr = (const struct common_firmware_header *)adev->uvd.fw->data; if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { offset = le32_to_cpu(hdr->ucode_array_offset_bytes); - memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, - le32_to_cpu(hdr->ucode_size_bytes)); + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, + le32_to_cpu(hdr->ucode_size_bytes)); + drm_dev_exit(idx); + } size -= le32_to_cpu(hdr->ucode_size_bytes); ptr += le32_to_cpu(hdr->ucode_size_bytes); } @@ -829,9 +840,8 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, default: DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); - return -EINVAL; } - BUG(); + return -EINVAL; } @@ -1115,9 +1125,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, ib->length_dw = 16; if (direct) { - r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, - true, false, - msecs_to_jiffies(10)); + r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, + msecs_to_jiffies(10)); if (r == 0) r = -ETIMEDOUT; if (r < 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index ea6a62f67e38..1ae7f824adc7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -29,6 +29,7 @@ #include #include +#include #include "amdgpu.h" #include "amdgpu_pm.h" @@ -87,7 +88,7 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, bool direct, struct dma_fence **fence); /** - * amdgpu_vce_init - allocate memory, load vce firmware + * amdgpu_vce_sw_init - allocate memory, load vce firmware * * @adev: amdgpu_device pointer * @size: size for the new BO @@ -204,7 +205,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) } /** - * amdgpu_vce_fini - free memory + * amdgpu_vce_sw_fini - free memory * * @adev: amdgpu_device pointer * @@ -293,7 +294,7 @@ int amdgpu_vce_resume(struct amdgpu_device *adev) void *cpu_addr; const struct common_firmware_header *hdr; unsigned offset; - int r; + int r, idx; if (adev->vce.vcpu_bo == NULL) return -EINVAL; @@ -313,8 +314,12 @@ int amdgpu_vce_resume(struct amdgpu_device *adev) hdr = (const struct common_firmware_header *)adev->vce.fw->data; offset = le32_to_cpu(hdr->ucode_array_offset_bytes); - memcpy_toio(cpu_addr, adev->vce.fw->data + offset, - adev->vce.fw->size - offset); + + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_toio(cpu_addr, adev->vce.fw->data + offset, + adev->vce.fw->size - offset); + drm_dev_exit(idx); + } amdgpu_bo_kunmap(adev->vce.vcpu_bo); @@ -574,7 +579,7 @@ err: } /** - * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary + * amdgpu_vce_validate_bo - make sure not to cross 4GB boundary * * @p: parser context * @ib_idx: indirect buffer to use @@ -715,7 +720,7 @@ static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p, } /** - * amdgpu_vce_cs_parse - parse and validate the command stream + * amdgpu_vce_ring_parse_cs - parse and validate the command stream * * @p: parser context * @ib_idx: indirect buffer to use @@ -951,7 +956,7 @@ out: } /** - * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode + * amdgpu_vce_ring_parse_cs_vm - parse the command stream in VM mode * * @p: parser context * @ib_idx: indirect buffer to use diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 201645963ba5..6780df0fb265 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_pm.h" @@ -48,6 +49,8 @@ #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" +#define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" +#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); MODULE_FIRMWARE(FIRMWARE_PICASSO); @@ -63,6 +66,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); MODULE_FIRMWARE(FIRMWARE_VANGOGH); MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); +MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); +MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); @@ -151,6 +156,18 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; + case CHIP_BEIGE_GOBY: + fw_name = FIRMWARE_BEIGE_GOBY; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) + adev->vcn.indirect_sram = true; + break; + case CHIP_YELLOW_CARP: + fw_name = FIRMWARE_YELLOW_CARP; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) + adev->vcn.indirect_sram = true; + break; default: return -EINVAL; } @@ -271,11 +288,34 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) return 0; } +bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) +{ + bool ret = false; + + int major; + int minor; + int revision; + + /* if cannot find IP data, then this VCN does not exist */ + if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0) + return true; + + if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) { + ret = true; + } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) { + ret = true; + } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) { + ret = true; + } + + return ret; +} + int amdgpu_vcn_suspend(struct amdgpu_device *adev) { unsigned size; void *ptr; - int i; + int i, idx; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -292,7 +332,10 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev) if (!adev->vcn.inst[i].saved_bo) return -ENOMEM; - memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); + drm_dev_exit(idx); + } } return 0; } @@ -301,7 +344,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) { unsigned size; void *ptr; - int i; + int i, idx; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { if (adev->vcn.harvest_config & (1 << i)) @@ -313,7 +356,10 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) ptr = adev->vcn.inst[i].cpu_addr; if (adev->vcn.inst[i].saved_bo != NULL) { - memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); + drm_dev_exit(idx); + } kvfree(adev->vcn.inst[i].saved_bo); adev->vcn.inst[i].saved_bo = NULL; } else { @@ -323,8 +369,11 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) hdr = (const struct common_firmware_header *)adev->vcn.fw->data; if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { offset = le32_to_cpu(hdr->ucode_array_offset_bytes); - memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, - le32_to_cpu(hdr->ucode_size_bytes)); + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, + le32_to_cpu(hdr->ucode_size_bytes)); + drm_dev_exit(idx); + } size -= le32_to_cpu(hdr->ucode_size_bytes); ptr += le32_to_cpu(hdr->ucode_size_bytes); } @@ -367,7 +416,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) } if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { - amdgpu_gfx_off_ctrl(adev, true); amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_GATE); r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, @@ -387,7 +435,6 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) atomic_inc(&adev->vcn.total_submission_cnt); if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { - amdgpu_gfx_off_ctrl(adev, false); r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, true); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index bc76cab67697..d74c62b49795 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -280,6 +280,16 @@ struct amdgpu_vcn_decode_buffer { uint32_t pad[30]; }; +#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80 +#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40 +#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0 + +enum vcn_ring_type { + VCN_ENCODE_RING, + VCN_DECODE_RING, + VCN_UNIFIED_RING, +}; + int amdgpu_vcn_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); int amdgpu_vcn_suspend(struct amdgpu_device *adev); @@ -287,6 +297,9 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev); void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); +bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, + enum vcn_ring_type type, uint32_t vcn_instance); + int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 0c9c5255aa42..b71dd1deeb2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -50,9 +50,12 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) struct drm_device *ddev = adev_to_drm(adev); /* enable virtual display */ - if (adev->mode_info.num_crtc == 0) - adev->mode_info.num_crtc = 1; - adev->enable_virtual_display = true; + if (adev->asic_type != CHIP_ALDEBARAN && + adev->asic_type != CHIP_ARCTURUS) { + if (adev->mode_info.num_crtc == 0) + adev->mode_info.num_crtc = 1; + adev->enable_virtual_display = true; + } ddev->driver_features &= ~DRIVER_ATOMIC; adev->cg_flags = 0; adev->pg_flags = 0; @@ -429,6 +432,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) uint32_t checksum; uint32_t checkval; + uint32_t i; + uint32_t tmp; + if (adev->virt.fw_reserve.p_pf2vf == NULL) return -EINVAL; @@ -469,6 +475,29 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) adev->virt.reg_access = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; + adev->virt.decode_max_dimension_pixels = 0; + adev->virt.decode_max_frame_pixels = 0; + adev->virt.encode_max_dimension_pixels = 0; + adev->virt.encode_max_frame_pixels = 0; + adev->virt.is_mm_bw_enabled = false; + for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { + tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; + adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); + + tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; + adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); + + tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; + adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); + + tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; + adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); + } + if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) + adev->virt.is_mm_bw_enabled = true; + + adev->unique_id = + ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; break; default: DRM_ERROR("invalid pf2vf version\n"); @@ -679,6 +708,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) case CHIP_VEGA10: case CHIP_VEGA20: case CHIP_ARCTURUS: + case CHIP_ALDEBARAN: soc15_set_virt_ops(adev); break; case CHIP_NAVI10: @@ -740,3 +770,35 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad return mode; } + +void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, + struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, + struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) +{ + uint32_t i; + + if (!adev->virt.is_mm_bw_enabled) + return; + + if (encode) { + for (i = 0; i < encode_array_size; i++) { + encode[i].max_width = adev->virt.encode_max_dimension_pixels; + encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; + if (encode[i].max_width > 0) + encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; + else + encode[i].max_height = 0; + } + } + + if (decode) { + for (i = 0; i < decode_array_size; i++) { + decode[i].max_width = adev->virt.decode_max_dimension_pixels; + decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; + if (decode[i].max_width > 0) + decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; + else + decode[i].max_height = 0; + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 383d4bdc3fb5..8d4c20bb71c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -233,8 +233,17 @@ struct amdgpu_virt { /* vf2pf message */ struct delayed_work vf2pf_work; uint32_t vf2pf_update_interval_ms; + + /* multimedia bandwidth config */ + bool is_mm_bw_enabled; + uint32_t decode_max_dimension_pixels; + uint32_t decode_max_frame_pixels; + uint32_t encode_max_dimension_pixels; + uint32_t encode_max_frame_pixels; }; +struct amdgpu_video_codec_info; + #define amdgpu_sriov_enabled(adev) \ ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) @@ -307,4 +316,8 @@ int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); + +void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, + struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, + struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 9acee4a5b2ba..79cfa2d68487 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -25,18 +25,22 @@ * Alex Deucher * Jerome Glisse */ + #include #include #include #include #include +#include #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" #include "amdgpu_gmc.h" #include "amdgpu_xgmi.h" #include "amdgpu_dma_buf.h" +#include "amdgpu_res_cursor.h" +#include "kfd_svm.h" /** * DOC: GPUVM @@ -328,7 +332,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, base->next = bo->vm_bo; bo->vm_bo = base; - if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) + if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv) return; vm->bulk_moveable = false; @@ -338,7 +342,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, amdgpu_vm_bo_idle(base); if (bo->preferred_domains & - amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) + amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)) return; /* @@ -357,14 +361,14 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, * Helper to get the parent entry for the child page table. NULL if we are at * the root page directory. */ -static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) +static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt) { - struct amdgpu_bo *parent = pt->base.bo->parent; + struct amdgpu_bo *parent = pt->bo->parent; if (!parent) return NULL; - return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); + return parent->vm_bo; } /* @@ -372,8 +376,8 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) */ struct amdgpu_vm_pt_cursor { uint64_t pfn; - struct amdgpu_vm_pt *parent; - struct amdgpu_vm_pt *entry; + struct amdgpu_vm_bo_base *parent; + struct amdgpu_vm_bo_base *entry; unsigned level; }; @@ -412,17 +416,17 @@ static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, { unsigned mask, shift, idx; - if (!cursor->entry->entries) + if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry || + !cursor->entry->bo) return false; - BUG_ON(!cursor->entry->base.bo); mask = amdgpu_vm_entries_mask(adev, cursor->level); shift = amdgpu_vm_level_shift(adev, cursor->level); ++cursor->level; idx = (cursor->pfn >> shift) & mask; cursor->parent = cursor->entry; - cursor->entry = &cursor->entry->entries[idx]; + cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx]; return true; } @@ -449,7 +453,7 @@ static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, shift = amdgpu_vm_level_shift(adev, cursor->level - 1); num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); - if (cursor->entry == &cursor->parent->entries[num_entries - 1]) + if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1]) return false; cursor->pfn += 1ULL << shift; @@ -535,7 +539,7 @@ static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, * True when the search should continue, false otherwise. */ static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start, - struct amdgpu_vm_pt *entry) + struct amdgpu_vm_bo_base *entry) { return entry && (!start || entry != start->entry); } @@ -586,7 +590,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct amdgpu_bo_list_entry *entry) { entry->priority = 0; - entry->tv.bo = &vm->root.base.bo->tbo; + entry->tv.bo = &vm->root.bo->tbo; /* Two for VM updates, one for TTM and one for the CS job */ entry->tv.num_shared = 4; entry->user_pages = NULL; @@ -618,7 +622,7 @@ void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) + if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv) vm->bulk_moveable = false; } @@ -649,15 +653,16 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, spin_lock(&adev->mman.bdev.lru_lock); list_for_each_entry(bo_base, &vm->idle, vm_status) { struct amdgpu_bo *bo = bo_base->bo; + struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo); if (!bo->parent) continue; - ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem, + ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource, &vm->lru_bulk_move); - if (bo->shadow) - ttm_bo_move_to_lru_tail(&bo->shadow->tbo, - &bo->shadow->tbo.mem, + if (shadow) + ttm_bo_move_to_lru_tail(&shadow->tbo, + shadow->tbo.resource, &vm->lru_bulk_move); } spin_unlock(&adev->mman.bdev.lru_lock); @@ -689,15 +694,21 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { struct amdgpu_bo *bo = bo_base->bo; + struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo); r = validate(param, bo); if (r) return r; + if (shadow) { + r = validate(param, shadow); + if (r) + return r; + } if (bo->tbo.type != ttm_bo_type_kernel) { amdgpu_vm_bo_moved(bo_base); } else { - vm->update_funcs->map_table(bo); + vm->update_funcs->map_table(to_amdgpu_bo_vm(bo)); amdgpu_vm_bo_relocated(bo_base); } } @@ -729,7 +740,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) * * @adev: amdgpu_device pointer * @vm: VM to clear BO from - * @bo: BO to clear + * @vmbo: BO to clear * @immediate: use an immediate update * * Root PD needs to be reserved when calling this. @@ -739,13 +750,14 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) */ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct amdgpu_bo *bo, + struct amdgpu_bo_vm *vmbo, bool immediate) { struct ttm_operation_ctx ctx = { true, false }; unsigned level = adev->vm_manager.root_level; struct amdgpu_vm_update_params params; - struct amdgpu_bo *ancestor = bo; + struct amdgpu_bo *ancestor = &vmbo->bo; + struct amdgpu_bo *bo = &vmbo->bo; unsigned entries, ats_entries; uint64_t addr; int r; @@ -769,11 +781,11 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, entries -= ats_entries; } else { - struct amdgpu_vm_pt *pt; + struct amdgpu_vm_bo_base *pt; - pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); + pt = ancestor->vm_bo; ats_entries = amdgpu_vm_num_ats_entries(adev); - if ((pt - vm->root.entries) >= ats_entries) { + if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) { ats_entries = 0; } else { ats_entries = entries; @@ -785,14 +797,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) return r; - if (bo->shadow) { - r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, - &ctx); + if (vmbo->shadow) { + struct amdgpu_bo *shadow = vmbo->shadow; + + r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx); if (r) return r; } - r = vm->update_funcs->map_table(bo); + r = vm->update_funcs->map_table(vmbo); if (r) return r; @@ -816,7 +829,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, amdgpu_gmc_get_vm_pde(adev, level, &value, &flags); } - r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries, + r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries, value, flags); if (r) return r; @@ -839,7 +852,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, } } - r = vm->update_funcs->update(¶ms, bo, addr, 0, entries, + r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries, value, flags); if (r) return r; @@ -849,35 +862,85 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, } /** - * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation + * amdgpu_vm_pt_create - create bo for PD/PT * * @adev: amdgpu_device pointer * @vm: requesting vm * @level: the page table level * @immediate: use a immediate update - * @bp: resulting BO allocation parameters + * @vmbo: pointer to the buffer object pointer */ -static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, +static int amdgpu_vm_pt_create(struct amdgpu_device *adev, + struct amdgpu_vm *vm, int level, bool immediate, - struct amdgpu_bo_param *bp) + struct amdgpu_bo_vm **vmbo) { - memset(bp, 0, sizeof(*bp)); + struct amdgpu_bo_param bp; + struct amdgpu_bo *bo; + struct dma_resv *resv; + unsigned int num_entries; + int r; - bp->size = amdgpu_vm_bo_size(adev, level); - bp->byte_align = AMDGPU_GPU_PAGE_SIZE; - bp->domain = AMDGPU_GEM_DOMAIN_VRAM; - bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); - bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + memset(&bp, 0, sizeof(bp)); + + bp.size = amdgpu_vm_bo_size(adev, level); + bp.byte_align = AMDGPU_GPU_PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain); + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_CPU_GTT_USWC; - bp->bo_ptr_size = sizeof(struct amdgpu_bo); + + if (level < AMDGPU_VM_PTB) + num_entries = amdgpu_vm_num_entries(adev, level); + else + num_entries = 0; + + bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries); + if (vm->use_cpu_for_update) - bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - else if (!vm->root.base.bo || vm->root.base.bo->shadow) - bp->flags |= AMDGPU_GEM_CREATE_SHADOW; - bp->type = ttm_bo_type_kernel; - bp->no_wait_gpu = immediate; - if (vm->root.base.bo) - bp->resv = vm->root.base.bo->tbo.base.resv; + bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + + bp.type = ttm_bo_type_kernel; + bp.no_wait_gpu = immediate; + if (vm->root.bo) + bp.resv = vm->root.bo->tbo.base.resv; + + r = amdgpu_bo_create_vm(adev, &bp, vmbo); + if (r) + return r; + + bo = &(*vmbo)->bo; + if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) { + (*vmbo)->shadow = NULL; + return 0; + } + + if (!bp.resv) + WARN_ON(dma_resv_lock(bo->tbo.base.resv, + NULL)); + resv = bp.resv; + memset(&bp, 0, sizeof(bp)); + bp.size = amdgpu_vm_bo_size(adev, level); + bp.domain = AMDGPU_GEM_DOMAIN_GTT; + bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + bp.type = ttm_bo_type_kernel; + bp.resv = bo->tbo.base.resv; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); + + r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); + + if (!resv) + dma_resv_unlock(bo->tbo.base.resv); + + if (r) { + amdgpu_bo_unref(&bo); + return r; + } + + (*vmbo)->shadow->parent = amdgpu_bo_ref(bo); + amdgpu_bo_add_to_shadow_list(*vmbo); + + return 0; } /** @@ -899,37 +962,24 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, struct amdgpu_vm_pt_cursor *cursor, bool immediate) { - struct amdgpu_vm_pt *entry = cursor->entry; - struct amdgpu_bo_param bp; - struct amdgpu_bo *pt; + struct amdgpu_vm_bo_base *entry = cursor->entry; + struct amdgpu_bo *pt_bo; + struct amdgpu_bo_vm *pt; int r; - if (cursor->level < AMDGPU_VM_PTB && !entry->entries) { - unsigned num_entries; - - num_entries = amdgpu_vm_num_entries(adev, cursor->level); - entry->entries = kvmalloc_array(num_entries, - sizeof(*entry->entries), - GFP_KERNEL | __GFP_ZERO); - if (!entry->entries) - return -ENOMEM; - } - - if (entry->base.bo) + if (entry->bo) return 0; - amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, &bp); - - r = amdgpu_bo_create(adev, &bp, &pt); + r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt); if (r) return r; /* Keep a reference to the root directory to avoid * freeing them up in the wrong order. */ - pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); - amdgpu_vm_bo_base_init(&entry->base, vm, pt); - + pt_bo = &pt->bo; + pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo); + amdgpu_vm_bo_base_init(entry, vm, pt_bo); r = amdgpu_vm_clear_bo(adev, vm, pt, immediate); if (r) goto error_free_pt; @@ -938,7 +988,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, error_free_pt: amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); + amdgpu_bo_unref(&pt_bo); return r; } @@ -947,16 +997,17 @@ error_free_pt: * * @entry: PDE to free */ -static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry) +static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry) { - if (entry->base.bo) { - entry->base.bo->vm_bo = NULL; - list_del(&entry->base.vm_status); - amdgpu_bo_unref(&entry->base.bo->shadow); - amdgpu_bo_unref(&entry->base.bo); - } - kvfree(entry->entries); - entry->entries = NULL; + struct amdgpu_bo *shadow; + + if (!entry->bo) + return; + shadow = amdgpu_bo_shadowed(entry->bo); + entry->bo->vm_bo = NULL; + list_del(&entry->vm_status); + amdgpu_bo_unref(&shadow); + amdgpu_bo_unref(&entry->bo); } /** @@ -973,7 +1024,7 @@ static void amdgpu_vm_free_pts(struct amdgpu_device *adev, struct amdgpu_vm_pt_cursor *start) { struct amdgpu_vm_pt_cursor cursor; - struct amdgpu_vm_pt *entry; + struct amdgpu_vm_bo_base *entry; vm->bulk_moveable = false; @@ -1241,10 +1292,10 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) */ static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, struct amdgpu_vm *vm, - struct amdgpu_vm_pt *entry) + struct amdgpu_vm_bo_base *entry) { - struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry); - struct amdgpu_bo *bo = parent->base.bo, *pbo; + struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry); + struct amdgpu_bo *bo = parent->bo, *pbo; uint64_t pde, pt, flags; unsigned level; @@ -1252,9 +1303,10 @@ static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, pbo = pbo->parent; level += params->adev->vm_manager.root_level; - amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); - pde = (entry - parent->entries) * 8; - return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags); + amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags); + pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8; + return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt, + 1, 0, flags); } /** @@ -1269,11 +1321,11 @@ static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_vm_pt_cursor cursor; - struct amdgpu_vm_pt *entry; + struct amdgpu_vm_bo_base *entry; for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) - if (entry->base.bo && !entry->base.moved) - amdgpu_vm_bo_relocated(&entry->base); + if (entry->bo && !entry->moved) + amdgpu_vm_bo_relocated(entry); } /** @@ -1307,11 +1359,12 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, return r; while (!list_empty(&vm->relocated)) { - struct amdgpu_vm_pt *entry; + struct amdgpu_vm_bo_base *entry; - entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, - base.vm_status); - amdgpu_vm_bo_idle(&entry->base); + entry = list_first_entry(&vm->relocated, + struct amdgpu_vm_bo_base, + vm_status); + amdgpu_vm_bo_idle(entry); r = amdgpu_vm_update_pde(¶ms, vm, entry); if (r) @@ -1334,9 +1387,9 @@ error: * Make sure to set the right flags for the PTEs at the desired level. */ static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, - struct amdgpu_bo *bo, unsigned level, + struct amdgpu_bo_vm *pt, unsigned int level, uint64_t pe, uint64_t addr, - unsigned count, uint32_t incr, + unsigned int count, uint32_t incr, uint64_t flags) { @@ -1352,7 +1405,7 @@ static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, flags |= AMDGPU_PTE_EXECUTABLE; } - params->vm->update_funcs->update(params, bo, pe, addr, count, incr, + params->vm->update_funcs->update(params, pt, pe, addr, count, incr, flags); } @@ -1491,7 +1544,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, continue; } - pt = cursor.entry->base.bo; + pt = cursor.entry->bo; if (!pt) { /* We need all PDs and PTs for mapping something, */ if (flags & AMDGPU_PTE_VALID) @@ -1503,7 +1556,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, if (!amdgpu_vm_pt_ancestor(&cursor)) return -EINVAL; - pt = cursor.entry->base.bo; + pt = cursor.entry->bo; shift = parent_shift; frag_end = max(frag_end, ALIGN(frag_start + 1, 1ULL << shift)); @@ -1532,9 +1585,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, nptes, dst, incr, upd_flags, vm->task_info.pid, vm->immediate.fence_context); - amdgpu_vm_update_flags(params, pt, cursor.level, - pe_start, dst, nptes, incr, - upd_flags); + amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt), + cursor.level, pe_start, dst, + nptes, incr, upd_flags); pe_start += nptes * 8; dst += nptes * incr; @@ -1557,7 +1610,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, * completely covered by the range and so potentially still in use. */ while (cursor.pfn < frag_start) { - amdgpu_vm_free_pts(adev, params->vm, &cursor); + /* Make sure previous mapping is freed */ + if (cursor.entry->bo) { + params->table_freed = true; + amdgpu_vm_free_pts(adev, params->vm, &cursor); + } amdgpu_vm_pt_next(adev, &cursor); } @@ -1583,29 +1640,34 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, * @last: last mapped entry * @flags: flags for the entries * @offset: offset into nodes and pages_addr - * @nodes: array of drm_mm_nodes with the MC addresses + * @res: ttm_resource to map * @pages_addr: DMA addresses to use for mapping * @fence: optional resulting fence + * @table_freed: return true if page table is freed * * Fill in the page table entries between @start and @last. * * Returns: * 0 for success, -EINVAL for failure. */ -static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, - struct amdgpu_device *bo_adev, - struct amdgpu_vm *vm, bool immediate, - bool unlocked, struct dma_resv *resv, - uint64_t start, uint64_t last, - uint64_t flags, uint64_t offset, - struct drm_mm_node *nodes, - dma_addr_t *pages_addr, - struct dma_fence **fence) +int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, + struct amdgpu_device *bo_adev, + struct amdgpu_vm *vm, bool immediate, + bool unlocked, struct dma_resv *resv, + uint64_t start, uint64_t last, + uint64_t flags, uint64_t offset, + struct ttm_resource *res, + dma_addr_t *pages_addr, + struct dma_fence **fence, + bool *table_freed) { struct amdgpu_vm_update_params params; + struct amdgpu_res_cursor cursor; enum amdgpu_sync_mode sync_mode; - uint64_t pfn; - int r; + int r, idx; + + if (!drm_dev_enter(&adev->ddev, &idx)) + return -ENODEV; memset(¶ms, 0, sizeof(params)); params.adev = adev; @@ -1622,14 +1684,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, else sync_mode = AMDGPU_SYNC_EXPLICIT; - pfn = offset >> PAGE_SHIFT; - if (nodes) { - while (pfn >= nodes->size) { - pfn -= nodes->size; - ++nodes; - } - } - amdgpu_vm_eviction_lock(vm); if (vm->evicting) { r = -EBUSY; @@ -1639,7 +1693,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) { struct dma_fence *tmp = dma_fence_get_stub(); - amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true); + amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true); swap(vm->last_unlocked, tmp); dma_fence_put(tmp); } @@ -1648,23 +1702,17 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_unlock; - do { + amdgpu_res_first(pages_addr ? NULL : res, offset, + (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor); + while (cursor.remaining) { uint64_t tmp, num_entries, addr; - - num_entries = last - start + 1; - if (nodes) { - addr = nodes->start << PAGE_SHIFT; - num_entries = min((nodes->size - pfn) * - AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries); - } else { - addr = 0; - } - + num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; if (pages_addr) { bool contiguous = true; if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { + uint64_t pfn = cursor.start >> PAGE_SHIFT; uint64_t count; contiguous = pages_addr[pfn + 1] == @@ -1684,16 +1732,18 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, } if (!contiguous) { - addr = pfn << PAGE_SHIFT; + addr = cursor.start; params.pages_addr = pages_addr; } else { - addr = pages_addr[pfn]; + addr = pages_addr[cursor.start >> PAGE_SHIFT]; params.pages_addr = NULL; } } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) { - addr += bo_adev->vm_manager.vram_base_offset; - addr += pfn << PAGE_SHIFT; + addr = bo_adev->vm_manager.vram_base_offset + + cursor.start; + } else { + addr = 0; } tmp = start + num_entries; @@ -1701,28 +1751,72 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_unlock; - pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; - if (nodes && nodes->size == pfn) { - pfn = 0; - ++nodes; - } + amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE); start = tmp; - - } while (unlikely(start != last + 1)); + } r = vm->update_funcs->commit(¶ms, fence); + if (table_freed) + *table_freed = *table_freed || params.table_freed; + error_unlock: amdgpu_vm_eviction_unlock(vm); + drm_dev_exit(idx); return r; } +void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, + uint64_t *gtt_mem, uint64_t *cpu_mem) +{ + struct amdgpu_bo_va *bo_va, *tmp; + + list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + spin_lock(&vm->invalidated_lock); + list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) { + if (!bo_va->base.bo) + continue; + amdgpu_bo_get_memory(bo_va->base.bo, vram_mem, + gtt_mem, cpu_mem); + } + spin_unlock(&vm->invalidated_lock); +} /** * amdgpu_vm_bo_update - update all BO mappings in the vm page table * * @adev: amdgpu_device pointer * @bo_va: requested BO and VM object * @clear: if true clear the entries + * @table_freed: return true if page table is freed * * Fill in the page table entries for @bo_va. * @@ -1730,14 +1824,13 @@ error_unlock: * 0 for success, -EINVAL for failure. */ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, - bool clear) + bool clear, bool *table_freed) { struct amdgpu_bo *bo = bo_va->base.bo; struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_bo_va_mapping *mapping; dma_addr_t *pages_addr = NULL; struct ttm_resource *mem; - struct drm_mm_node *nodes; struct dma_fence **last_update; struct dma_resv *resv; uint64_t flags; @@ -1746,8 +1839,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (clear || !bo) { mem = NULL; - nodes = NULL; - resv = vm->root.base.bo->tbo.base.resv; + resv = vm->root.bo->tbo.base.resv; } else { struct drm_gem_object *obj = &bo->tbo.base; @@ -1757,12 +1849,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, struct drm_gem_object *gobj = dma_buf->priv; struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); - if (abo->tbo.mem.mem_type == TTM_PL_VRAM) + if (abo->tbo.resource->mem_type == TTM_PL_VRAM) bo = gem_to_amdgpu_bo(gobj); } - mem = &bo->tbo.mem; - nodes = mem->mm_node; - if (mem->mem_type == TTM_PL_TT) + mem = bo->tbo.resource; + if (mem->mem_type == TTM_PL_TT || + mem->mem_type == AMDGPU_PL_PREEMPT) pages_addr = bo->tbo.ttm->dma_address; } @@ -1778,7 +1870,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, } if (clear || (bo && bo->tbo.base.resv == - vm->root.base.bo->tbo.base.resv)) + vm->root.bo->tbo.base.resv)) last_update = &vm->last_update; else last_update = &bo_va->last_pt_update; @@ -1810,8 +1902,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false, resv, mapping->start, mapping->last, update_flags, - mapping->offset, nodes, - pages_addr, last_update); + mapping->offset, mem, + pages_addr, last_update, table_freed); if (r) return r; } @@ -1820,8 +1912,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, * the evicted list so that it gets validated again on the * next command submission. */ - if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { - uint32_t mem_type = bo->tbo.mem.mem_type; + if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) { + uint32_t mem_type = bo->tbo.resource->mem_type; if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) @@ -1957,18 +2049,17 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; + struct dma_resv *resv = vm->root.bo->tbo.base.resv; struct dma_fence *excl, **shared; unsigned i, shared_count; int r; - r = dma_resv_get_fences_rcu(resv, &excl, - &shared_count, &shared); + r = dma_resv_get_fences(resv, &excl, &shared_count, &shared); if (r) { /* Not enough memory to grab the fence list, as last resort * block for all the fences to complete. */ - dma_resv_wait_timeout_rcu(resv, true, false, + dma_resv_wait_timeout(resv, true, false, MAX_SCHEDULE_TIMEOUT); return; } @@ -2004,7 +2095,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence) { - struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; + struct dma_resv *resv = vm->root.bo->tbo.base.resv; struct amdgpu_bo_va_mapping *mapping; uint64_t init_pte_value = 0; struct dma_fence *f = NULL; @@ -2022,7 +2113,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false, resv, mapping->start, mapping->last, init_pte_value, - 0, NULL, NULL, &f); + 0, NULL, NULL, &f, NULL); amdgpu_vm_free_mapping(adev, vm, mapping, f); if (r) { dma_fence_put(f); @@ -2064,7 +2155,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { /* Per VM BOs never need to bo cleared in the page tables */ - r = amdgpu_vm_bo_update(adev, bo_va, false); + r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); if (r) return r; } @@ -2083,7 +2174,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, else clear = true; - r = amdgpu_vm_bo_update(adev, bo_va, clear); + r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL); if (r) return r; @@ -2163,7 +2254,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, if (mapping->flags & AMDGPU_PTE_PRT) amdgpu_vm_prt_get(adev); - if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv && + if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv && !bo_va->base.moved) { list_move(&bo_va->base.vm_status, &vm->moved); } @@ -2525,7 +2616,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_vm_bo_base **base; if (bo) { - if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) + if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv) vm->bulk_moveable = false; for (base = &bo_va->base.bo->vm_bo; *base; @@ -2580,7 +2671,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo) return true; /* Don't evict VM page tables while they are busy */ - if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true)) + if (!dma_resv_test_signaled(bo->tbo.base.resv, true)) return false; /* Try to block ongoing updates */ @@ -2613,13 +2704,13 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, struct amdgpu_vm_bo_base *bo_base; /* shadow bo doesn't have bo base, its validation needs its parent */ - if (bo->parent && bo->parent->shadow == bo) + if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo)) bo = bo->parent; for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { + if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) { amdgpu_vm_bo_evicted(bo_base); continue; } @@ -2630,7 +2721,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, if (bo->tbo.type == ttm_bo_type_kernel) amdgpu_vm_bo_relocated(bo_base); - else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) + else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv) amdgpu_vm_bo_moved(bo_base); else amdgpu_vm_bo_invalidated(bo_base); @@ -2760,8 +2851,8 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, */ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) { - timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv, - true, true, timeout); + timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true, + true, timeout); if (timeout <= 0) return timeout; @@ -2773,7 +2864,6 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) * * @adev: amdgpu_device pointer * @vm: requested vm - * @vm_context: Indicates if it GFX or Compute context * @pasid: Process address space identifier * * Init @vm fields. @@ -2781,11 +2871,10 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) * Returns: * 0 for success, error for failure. */ -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, - int vm_context, u32 pasid) +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid) { - struct amdgpu_bo_param bp; - struct amdgpu_bo *root; + struct amdgpu_bo *root_bo; + struct amdgpu_bo_vm *root; int r, i; vm->va = RB_ROOT_CACHED; @@ -2816,16 +2905,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->pte_support_ats = false; vm->is_compute_context = false; - if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { - vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & - AMDGPU_VM_USE_CPU_FOR_COMPUTE); + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & + AMDGPU_VM_USE_CPU_FOR_GFX); - if (adev->asic_type == CHIP_RAVEN) - vm->pte_support_ats = true; - } else { - vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & - AMDGPU_VM_USE_CPU_FOR_GFX); - } DRM_DEBUG_DRIVER("VM update mode is %s\n", vm->use_cpu_for_update ? "CPU" : "SDMA"); WARN_ONCE((vm->use_cpu_for_update && @@ -2842,28 +2924,26 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, mutex_init(&vm->eviction_lock); vm->evicting = false; - amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp); - if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) - bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; - r = amdgpu_bo_create(adev, &bp, &root); + r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level, + false, &root); if (r) goto error_free_delayed; - - r = amdgpu_bo_reserve(root, true); + root_bo = &root->bo; + r = amdgpu_bo_reserve(root_bo, true); if (r) goto error_free_root; - r = dma_resv_reserve_shared(root->tbo.base.resv, 1); + r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1); if (r) goto error_unreserve; - amdgpu_vm_bo_base_init(&vm->root.base, vm, root); + amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); r = amdgpu_vm_clear_bo(adev, vm, root, false); if (r) goto error_unreserve; - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); if (pasid) { unsigned long flags; @@ -2883,12 +2963,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, return 0; error_unreserve: - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); error_free_root: - amdgpu_bo_unref(&vm->root.base.bo->shadow); - amdgpu_bo_unref(&vm->root.base.bo); - vm->root.base.bo = NULL; + amdgpu_bo_unref(&root->shadow); + amdgpu_bo_unref(&root_bo); + vm->root.bo = NULL; error_free_delayed: dma_fence_put(vm->last_unlocked); @@ -2914,17 +2994,14 @@ error_free_immediate: * 0 if this VM is clean */ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev, - struct amdgpu_vm *vm) + struct amdgpu_vm *vm) { enum amdgpu_vm_level root = adev->vm_manager.root_level; unsigned int entries = amdgpu_vm_num_entries(adev, root); unsigned int i = 0; - if (!(vm->root.entries)) - return 0; - for (i = 0; i < entries; i++) { - if (vm->root.entries[i].base.bo) + if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo) return -EINVAL; } @@ -2958,7 +3035,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); int r; - r = amdgpu_bo_reserve(vm->root.base.bo, true); + r = amdgpu_bo_reserve(vm->root.bo, true); if (r) return r; @@ -2985,7 +3062,9 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, */ if (pte_support_ats != vm->pte_support_ats) { vm->pte_support_ats = pte_support_ats; - r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false); + r = amdgpu_vm_clear_bo(adev, vm, + to_amdgpu_bo_vm(vm->root.bo), + false); if (r) goto free_idr; } @@ -3001,7 +3080,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (vm->use_cpu_for_update) { /* Sync with last SDMA update/clear before switching to CPU */ - r = amdgpu_bo_sync_wait(vm->root.base.bo, + r = amdgpu_bo_sync_wait(vm->root.bo, AMDGPU_FENCE_OWNER_UNDEFINED, true); if (r) goto free_idr; @@ -3029,7 +3108,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, } /* Free the shadow bo for compute VM */ - amdgpu_bo_unref(&vm->root.base.bo->shadow); + amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow); if (pasid) vm->pasid = pasid; @@ -3045,7 +3124,7 @@ free_idr: spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); } unreserve_bo: - amdgpu_bo_unreserve(vm->root.base.bo); + amdgpu_bo_unreserve(vm->root.bo); return r; } @@ -3088,7 +3167,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); - root = amdgpu_bo_ref(vm->root.base.bo); + root = amdgpu_bo_ref(vm->root.bo); amdgpu_bo_reserve(root, true); if (vm->pasid) { unsigned long flags; @@ -3115,7 +3194,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_vm_free_pts(adev, vm, NULL); amdgpu_bo_unreserve(root); amdgpu_bo_unref(&root); - WARN_ON(vm->root.base.bo); + WARN_ON(vm->root.bo); drm_sched_entity_destroy(&vm->immediate); drm_sched_entity_destroy(&vm->delayed); @@ -3232,7 +3311,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) /* Wait vm idle to make sure the vmid set in SPM_VMID is * not referenced anymore. */ - r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true); + r = amdgpu_bo_reserve(fpriv->vm.root.bo, true); if (r) return r; @@ -3240,7 +3319,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (r < 0) return r; - amdgpu_bo_unreserve(fpriv->vm.root.base.bo); + amdgpu_bo_unreserve(fpriv->vm.root.bo); amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); break; default: @@ -3304,47 +3383,57 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, uint64_t addr) { + bool is_compute_context = false; struct amdgpu_bo *root; + unsigned long irqflags; uint64_t value, flags; struct amdgpu_vm *vm; int r; - spin_lock(&adev->vm_manager.pasid_lock); + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); vm = idr_find(&adev->vm_manager.pasid_idr, pasid); - if (vm) - root = amdgpu_bo_ref(vm->root.base.bo); - else + if (vm) { + root = amdgpu_bo_ref(vm->root.bo); + is_compute_context = vm->is_compute_context; + } else { root = NULL; - spin_unlock(&adev->vm_manager.pasid_lock); + } + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); if (!root) return false; + addr /= AMDGPU_GPU_PAGE_SIZE; + + if (is_compute_context && + !svm_range_restore_pages(adev, pasid, addr)) { + amdgpu_bo_unref(&root); + return true; + } + r = amdgpu_bo_reserve(root, true); if (r) goto error_unref; /* Double check that the VM still exists */ - spin_lock(&adev->vm_manager.pasid_lock); + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); vm = idr_find(&adev->vm_manager.pasid_idr, pasid); - if (vm && vm->root.base.bo != root) + if (vm && vm->root.bo != root) vm = NULL; - spin_unlock(&adev->vm_manager.pasid_lock); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); if (!vm) goto error_unlock; - addr /= AMDGPU_GPU_PAGE_SIZE; flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED | AMDGPU_PTE_SYSTEM; - if (vm->is_compute_context) { + if (is_compute_context) { /* Intentionally setting invalid PTE flag * combination to force a no-retry-fault */ flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | AMDGPU_PTE_TF; value = 0; - } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) { /* Redirect the access to the dummy page */ value = adev->dummy_page_addr; @@ -3363,7 +3452,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, } r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr, - addr, flags, value, NULL, NULL, + addr, flags, value, NULL, NULL, NULL, NULL); if (r) goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 4e140288159c..ddb85a85cbba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -39,6 +39,7 @@ struct amdgpu_bo_va; struct amdgpu_job; struct amdgpu_bo_list_entry; +struct amdgpu_bo_vm; /* * GPUVM handling @@ -121,9 +122,6 @@ struct amdgpu_bo_list_entry; /* max vmids dedicated for process */ #define AMDGPU_VM_MAX_RESERVED_VMID 1 -#define AMDGPU_VM_CONTEXT_GFX 0 -#define AMDGPU_VM_CONTEXT_COMPUTE 1 - /* See vm_update_mode */ #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) @@ -154,13 +152,6 @@ struct amdgpu_vm_bo_base { bool moved; }; -struct amdgpu_vm_pt { - struct amdgpu_vm_bo_base base; - - /* array of page tables, one for each directory entry */ - struct amdgpu_vm_pt *entries; -}; - /* provided by hw blocks that can write ptes, e.g., sdma */ struct amdgpu_vm_pte_funcs { /* number of dw to reserve per operation */ @@ -234,14 +225,19 @@ struct amdgpu_vm_update_params { * @num_dw_left: number of dw left for the IB */ unsigned int num_dw_left; + + /** + * @table_freed: return true if page table is freed when updating + */ + bool table_freed; }; struct amdgpu_vm_update_funcs { - int (*map_table)(struct amdgpu_bo *bo); + int (*map_table)(struct amdgpu_bo_vm *bo); int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, enum amdgpu_sync_mode sync_mode); int (*update)(struct amdgpu_vm_update_params *p, - struct amdgpu_bo *bo, uint64_t pe, uint64_t addr, + struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags); int (*commit)(struct amdgpu_vm_update_params *p, struct dma_fence **fence); @@ -281,7 +277,7 @@ struct amdgpu_vm { struct list_head done; /* contains the page directory */ - struct amdgpu_vm_pt root; + struct amdgpu_vm_bo_base root; struct dma_fence *last_update; /* Scheduler entities for page table updates */ @@ -367,6 +363,8 @@ struct amdgpu_vm_manager { spinlock_t pasid_lock; }; +struct amdgpu_bo_va_mapping; + #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) @@ -378,8 +376,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev); void amdgpu_vm_manager_fini(struct amdgpu_device *adev); long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, - int vm_context, u32 pasid); +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); @@ -398,9 +395,18 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct dma_fence **fence); int amdgpu_vm_handle_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, + struct amdgpu_device *bo_adev, + struct amdgpu_vm *vm, bool immediate, + bool unlocked, struct dma_resv *resv, + uint64_t start, uint64_t last, + uint64_t flags, uint64_t offset, + struct ttm_resource *res, + dma_addr_t *pages_addr, + struct dma_fence **fence, bool *free_table); int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, - bool clear); + bool clear, bool *table_freed); bool amdgpu_vm_evictable(struct amdgpu_bo *bo); void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, struct amdgpu_bo *bo, bool evicted); @@ -447,6 +453,8 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo); +void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, + uint64_t *gtt_mem, uint64_t *cpu_mem); #if defined(CONFIG_DEBUG_FS) void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index ac45d9c7a4e9..e3fbf0f10add 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -29,9 +29,9 @@ * * @table: newly allocated or validated PD/PT */ -static int amdgpu_vm_cpu_map_table(struct amdgpu_bo *table) +static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table) { - return amdgpu_bo_kmap(table, NULL); + return amdgpu_bo_kmap(&table->bo, NULL); } /** @@ -58,7 +58,7 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, * amdgpu_vm_cpu_update - helper to update page tables via CPU * * @p: see amdgpu_vm_update_params definition - * @bo: PD/PT to update + * @vmbo: PD/PT to update * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB * @addr: dst addr to write into pe * @count: number of page entries to update @@ -68,7 +68,7 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, * Write count number of PT/PD entries directly. */ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, - struct amdgpu_bo *bo, uint64_t pe, + struct amdgpu_bo_vm *vmbo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { @@ -76,13 +76,13 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, uint64_t value; int r; - if (bo->tbo.moving) { - r = dma_fence_wait(bo->tbo.moving, true); + if (vmbo->bo.tbo.moving) { + r = dma_fence_wait(vmbo->bo.tbo.moving, true); if (r) return r; } - pe += (unsigned long)amdgpu_bo_kptr(bo); + pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo); trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); @@ -110,7 +110,7 @@ static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p, { /* Flush HDP */ mb(); - amdgpu_asic_flush_hdp(p->adev, NULL); + amdgpu_device_flush_hdp(p->adev, NULL); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index a83a646759c5..dbb551762805 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -33,11 +33,11 @@ * * @table: newly allocated or validated PD/PT */ -static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table) +static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) { int r; - r = amdgpu_ttm_alloc_gart(&table->tbo); + r = amdgpu_ttm_alloc_gart(&table->bo.tbo); if (r) return r; @@ -112,7 +112,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, swap(p->vm->last_unlocked, f); dma_fence_put(tmp); } else { - amdgpu_bo_fence(p->vm->root.base.bo, f, true); + amdgpu_bo_fence(p->vm->root.bo, f, true); } if (fence && !p->immediate) @@ -186,7 +186,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p, * amdgpu_vm_sdma_update - execute VM update * * @p: see amdgpu_vm_update_params definition - * @bo: PD/PT to update + * @vmbo: PD/PT to update * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB * @addr: dst addr to write into pe * @count: number of page entries to update @@ -197,10 +197,11 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p, * the IB. */ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, - struct amdgpu_bo *bo, uint64_t pe, + struct amdgpu_bo_vm *vmbo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { + struct amdgpu_bo *bo = &vmbo->bo; enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE : AMDGPU_IB_POOL_DELAYED; unsigned int i, ndw, nptes; @@ -238,8 +239,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, if (!p->pages_addr) { /* set page commands needed */ - if (bo->shadow) - amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr, + if (vmbo->shadow) + amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, count, incr, flags); amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); @@ -248,7 +249,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, /* copy commands needed */ ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * - (bo->shadow ? 2 : 1); + (vmbo->shadow ? 2 : 1); /* for padding */ ndw -= 7; @@ -263,8 +264,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, pte[i] |= flags; } - if (bo->shadow) - amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes); + if (vmbo->shadow) + amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); pe += nptes * 8; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index bce105e2973e..436ec246a7da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -23,18 +23,27 @@ */ #include +#include + #include "amdgpu.h" #include "amdgpu_vm.h" #include "amdgpu_res_cursor.h" #include "amdgpu_atomfirmware.h" #include "atom.h" -static inline struct amdgpu_vram_mgr *to_vram_mgr(struct ttm_resource_manager *man) +struct amdgpu_vram_reservation { + struct list_head node; + struct drm_mm_node mm_node; +}; + +static inline struct amdgpu_vram_mgr * +to_vram_mgr(struct ttm_resource_manager *man) { return container_of(man, struct amdgpu_vram_mgr, manager); } -static inline struct amdgpu_device *to_amdgpu_device(struct amdgpu_vram_mgr *mgr) +static inline struct amdgpu_device * +to_amdgpu_device(struct amdgpu_vram_mgr *mgr) { return container_of(mgr, struct amdgpu_device, mman.vram_mgr); } @@ -82,12 +91,14 @@ static ssize_t amdgpu_mem_info_vis_vram_total_show(struct device *dev, * amount of currently used VRAM in bytes */ static ssize_t amdgpu_mem_info_vram_used_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, + char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); + struct ttm_resource_manager *man; + man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); return sysfs_emit(buf, "%llu\n", amdgpu_vram_mgr_usage(man)); } @@ -100,18 +111,28 @@ static ssize_t amdgpu_mem_info_vram_used_show(struct device *dev, * amount of currently used visible VRAM in bytes */ static ssize_t amdgpu_mem_info_vis_vram_used_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, + char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); + struct ttm_resource_manager *man; + man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); return sysfs_emit(buf, "%llu\n", amdgpu_vram_mgr_vis_usage(man)); } +/** + * DOC: mem_info_vram_vendor + * + * The amdgpu driver provides a sysfs API for reporting the vendor of the + * installed VRAM + * The file mem_info_vram_vendor is used for this and returns the name of the + * vendor. + */ static ssize_t amdgpu_mem_info_vram_vendor(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); @@ -153,7 +174,7 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO, static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO, amdgpu_mem_info_vram_vendor, NULL); -static const struct attribute *amdgpu_vram_mgr_attributes[] = { +static struct attribute *amdgpu_vram_mgr_attributes[] = { &dev_attr_mem_info_vram_total.attr, &dev_attr_mem_info_vis_vram_total.attr, &dev_attr_mem_info_vram_used.attr, @@ -162,77 +183,9 @@ static const struct attribute *amdgpu_vram_mgr_attributes[] = { NULL }; -static const struct ttm_resource_manager_func amdgpu_vram_mgr_func; - -/** - * amdgpu_vram_mgr_init - init VRAM manager and DRM MM - * - * @adev: amdgpu_device pointer - * - * Allocate and initialize the VRAM manager. - */ -int amdgpu_vram_mgr_init(struct amdgpu_device *adev) -{ - struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - - ttm_resource_manager_init(man, adev->gmc.real_vram_size >> PAGE_SHIFT); - - man->func = &amdgpu_vram_mgr_func; - - drm_mm_init(&mgr->mm, 0, man->size); - spin_lock_init(&mgr->lock); - INIT_LIST_HEAD(&mgr->reservations_pending); - INIT_LIST_HEAD(&mgr->reserved_pages); - - /* Add the two VRAM-related sysfs files */ - ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); - if (ret) - DRM_ERROR("Failed to register sysfs\n"); - - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, &mgr->manager); - ttm_resource_manager_set_used(man, true); - return 0; -} - -/** - * amdgpu_vram_mgr_fini - free and destroy VRAM manager - * - * @adev: amdgpu_device pointer - * - * Destroy and free the VRAM manager, returns -EBUSY if ranges are still - * allocated inside it. - */ -void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) -{ - struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - struct amdgpu_vram_reservation *rsv, *temp; - - ttm_resource_manager_set_used(man, false); - - ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - if (ret) - return; - - spin_lock(&mgr->lock); - list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node) - kfree(rsv); - - list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, node) { - drm_mm_remove_node(&rsv->mm_node); - kfree(rsv); - } - drm_mm_takedown(&mgr->mm); - spin_unlock(&mgr->lock); - - sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); - - ttm_resource_manager_cleanup(man); - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); -} +const struct attribute_group amdgpu_vram_mgr_attr_group = { + .attrs = amdgpu_vram_mgr_attributes +}; /** * amdgpu_vram_mgr_vis_size - Calculate visible node size @@ -266,23 +219,25 @@ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev, u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct ttm_resource *mem = &bo->tbo.mem; - struct drm_mm_node *nodes = mem->mm_node; - unsigned pages = mem->num_pages; + struct ttm_resource *res = bo->tbo.resource; + unsigned pages = res->num_pages; + struct drm_mm_node *mm; u64 usage; if (amdgpu_gmc_vram_full_visible(&adev->gmc)) return amdgpu_bo_size(bo); - if (mem->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT) + if (res->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT) return 0; - for (usage = 0; nodes && pages; pages -= nodes->size, nodes++) - usage += amdgpu_vram_mgr_vis_size(adev, nodes); + mm = &container_of(res, struct ttm_range_mgr_node, base)->mm_nodes[0]; + for (usage = 0; pages; pages -= mm->size, mm++) + usage += amdgpu_vram_mgr_vis_size(adev, mm); return usage; } +/* Commit the reservation of VRAM pages */ static void amdgpu_vram_mgr_do_reserve(struct ttm_resource_manager *man) { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); @@ -413,15 +368,15 @@ static void amdgpu_vram_mgr_virt_start(struct ttm_resource *mem, static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, struct ttm_buffer_object *tbo, const struct ttm_place *place, - struct ttm_resource *mem) + struct ttm_resource **res) { + unsigned long lpfn, num_nodes, pages_per_node, pages_left, pages; struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct amdgpu_device *adev = to_amdgpu_device(mgr); - struct drm_mm *mm = &mgr->mm; - struct drm_mm_node *nodes; - enum drm_mm_insert_mode mode; - unsigned long lpfn, num_nodes, pages_per_node, pages_left; uint64_t vis_usage = 0, mem_bytes, max_bytes; + struct ttm_range_mgr_node *node; + struct drm_mm *mm = &mgr->mm; + enum drm_mm_insert_mode mode; unsigned i; int r; @@ -434,10 +389,10 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, max_bytes -= AMDGPU_VM_RESERVED_VRAM; /* bail out quickly if there's likely not enough VRAM for this BO */ - mem_bytes = (u64)mem->num_pages << PAGE_SHIFT; + mem_bytes = tbo->base.size; if (atomic64_add_return(mem_bytes, &mgr->usage) > max_bytes) { - atomic64_sub(mem_bytes, &mgr->usage); - return -ENOSPC; + r = -ENOSPC; + goto error_sub; } if (place->flags & TTM_PL_FLAG_CONTIGUOUS) { @@ -448,78 +403,78 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, pages_per_node = HPAGE_PMD_NR; #else /* default to 2MB */ - pages_per_node = (2UL << (20UL - PAGE_SHIFT)); + pages_per_node = 2UL << (20UL - PAGE_SHIFT); #endif - pages_per_node = max((uint32_t)pages_per_node, mem->page_alignment); - num_nodes = DIV_ROUND_UP(mem->num_pages, pages_per_node); + pages_per_node = max_t(uint32_t, pages_per_node, + tbo->page_alignment); + num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes), pages_per_node); } - nodes = kvmalloc_array((uint32_t)num_nodes, sizeof(*nodes), - GFP_KERNEL | __GFP_ZERO); - if (!nodes) { - atomic64_sub(mem_bytes, &mgr->usage); - return -ENOMEM; + node = kvmalloc(struct_size(node, mm_nodes, num_nodes), + GFP_KERNEL | __GFP_ZERO); + if (!node) { + r = -ENOMEM; + goto error_sub; } + ttm_resource_init(tbo, place, &node->base); + mode = DRM_MM_INSERT_BEST; if (place->flags & TTM_PL_FLAG_TOPDOWN) mode = DRM_MM_INSERT_HIGH; - mem->start = 0; - pages_left = mem->num_pages; + pages_left = node->base.num_pages; + /* Limit maximum size to 2GB due to SG table limitations */ + pages = min(pages_left, 2UL << (30 - PAGE_SHIFT)); + + i = 0; spin_lock(&mgr->lock); - for (i = 0; pages_left >= pages_per_node; ++i) { - unsigned long pages = rounddown_pow_of_two(pages_left); + while (pages_left) { + uint32_t alignment = tbo->page_alignment; - /* Limit maximum size to 2GB due to SG table limitations */ - pages = min(pages, (2UL << (30 - PAGE_SHIFT))); - - r = drm_mm_insert_node_in_range(mm, &nodes[i], pages, - pages_per_node, 0, - place->fpfn, lpfn, - mode); - if (unlikely(r)) - break; - - vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]); - amdgpu_vram_mgr_virt_start(mem, &nodes[i]); - pages_left -= pages; - } - - for (; pages_left; ++i) { - unsigned long pages = min(pages_left, pages_per_node); - uint32_t alignment = mem->page_alignment; - - if (pages == pages_per_node) + if (pages >= pages_per_node) alignment = pages_per_node; - r = drm_mm_insert_node_in_range(mm, &nodes[i], - pages, alignment, 0, - place->fpfn, lpfn, - mode); - if (unlikely(r)) - goto error; + r = drm_mm_insert_node_in_range(mm, &node->mm_nodes[i], pages, + alignment, 0, place->fpfn, + lpfn, mode); + if (unlikely(r)) { + if (pages > pages_per_node) { + if (is_power_of_2(pages)) + pages = pages / 2; + else + pages = rounddown_pow_of_two(pages); + continue; + } + goto error_free; + } - vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]); - amdgpu_vram_mgr_virt_start(mem, &nodes[i]); + vis_usage += amdgpu_vram_mgr_vis_size(adev, &node->mm_nodes[i]); + amdgpu_vram_mgr_virt_start(&node->base, &node->mm_nodes[i]); pages_left -= pages; + ++i; + + if (pages > pages_left) + pages = pages_left; } spin_unlock(&mgr->lock); + if (i == 1) + node->base.placement |= TTM_PL_FLAG_CONTIGUOUS; + atomic64_add(vis_usage, &mgr->vis_usage); - - mem->mm_node = nodes; - + *res = &node->base; return 0; -error: +error_free: while (i--) - drm_mm_remove_node(&nodes[i]); + drm_mm_remove_node(&node->mm_nodes[i]); spin_unlock(&mgr->lock); - atomic64_sub(mem->num_pages << PAGE_SHIFT, &mgr->usage); + kvfree(node); - kvfree(nodes); +error_sub: + atomic64_sub(mem_bytes, &mgr->usage); return r; } @@ -532,24 +487,22 @@ error: * Free the allocated VRAM again. */ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *mem) + struct ttm_resource *res) { + struct ttm_range_mgr_node *node = to_ttm_range_mgr_node(res); struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct amdgpu_device *adev = to_amdgpu_device(mgr); - struct drm_mm_node *nodes = mem->mm_node; uint64_t usage = 0, vis_usage = 0; - unsigned pages = mem->num_pages; - - if (!mem->mm_node) - return; + unsigned i, pages; spin_lock(&mgr->lock); - while (pages) { - pages -= nodes->size; - drm_mm_remove_node(nodes); - usage += nodes->size << PAGE_SHIFT; - vis_usage += amdgpu_vram_mgr_vis_size(adev, nodes); - ++nodes; + for (i = 0, pages = res->num_pages; pages; + pages -= node->mm_nodes[i].size, ++i) { + struct drm_mm_node *mm = &node->mm_nodes[i]; + + drm_mm_remove_node(mm); + usage += mm->size << PAGE_SHIFT; + vis_usage += amdgpu_vram_mgr_vis_size(adev, mm); } amdgpu_vram_mgr_do_reserve(man); spin_unlock(&mgr->lock); @@ -557,8 +510,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, atomic64_sub(usage, &mgr->usage); atomic64_sub(vis_usage, &mgr->vis_usage); - kvfree(mem->mm_node); - mem->mm_node = NULL; + kvfree(node); } /** @@ -575,7 +527,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, * Allocate and fill a sg table from a VRAM allocation. */ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, - struct ttm_resource *mem, + struct ttm_resource *res, u64 offset, u64 length, struct device *dev, enum dma_data_direction dir, @@ -591,7 +543,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, return -ENOMEM; /* Determine the number of DRM_MM nodes to export */ - amdgpu_res_first(mem, offset, length, &cursor); + amdgpu_res_first(res, offset, length, &cursor); while (cursor.remaining) { num_entries++; amdgpu_res_next(&cursor, cursor.size); @@ -611,7 +563,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, * and the number of bytes from it. Access the following * DRM_MM node(s) if more buffer needs to exported */ - amdgpu_res_first(mem, offset, length, &cursor); + amdgpu_res_first(res, offset, length, &cursor); for_each_sgtable_sg((*sgt), sg, i) { phys_addr_t phys = cursor.start + adev->gmc.aper_base; size_t size = cursor.size; @@ -727,3 +679,65 @@ static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = { .free = amdgpu_vram_mgr_del, .debug = amdgpu_vram_mgr_debug }; + +/** + * amdgpu_vram_mgr_init - init VRAM manager and DRM MM + * + * @adev: amdgpu_device pointer + * + * Allocate and initialize the VRAM manager. + */ +int amdgpu_vram_mgr_init(struct amdgpu_device *adev) +{ + struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; + struct ttm_resource_manager *man = &mgr->manager; + + ttm_resource_manager_init(man, adev->gmc.real_vram_size >> PAGE_SHIFT); + + man->func = &amdgpu_vram_mgr_func; + + drm_mm_init(&mgr->mm, 0, man->size); + spin_lock_init(&mgr->lock); + INIT_LIST_HEAD(&mgr->reservations_pending); + INIT_LIST_HEAD(&mgr->reserved_pages); + + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, &mgr->manager); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_vram_mgr_fini - free and destroy VRAM manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the VRAM manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + struct amdgpu_vram_reservation *rsv, *temp; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + spin_lock(&mgr->lock); + list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node) + kfree(rsv); + + list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, node) { + drm_mm_remove_node(&rsv->mm_node); + kfree(rsv); + } + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 1a8f6d4baab2..a434c71fde8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -56,6 +56,8 @@ #define AMD_SRIOV_MSG_RESERVE_UCODE 24 +#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 + enum amd_sriov_ucode_engine_id { AMD_SRIOV_UCODE_ID_VCE = 0, AMD_SRIOV_UCODE_ID_UVD, @@ -98,10 +100,10 @@ union amd_sriov_msg_feature_flags { union amd_sriov_reg_access_flags { struct { - uint32_t vf_reg_access_ih : 1; + uint32_t vf_reg_access_ih : 1; uint32_t vf_reg_access_mmhub : 1; - uint32_t vf_reg_access_gc : 1; - uint32_t reserved : 29; + uint32_t vf_reg_access_gc : 1; + uint32_t reserved : 29; } flags; uint32_t all; }; @@ -114,6 +116,37 @@ union amd_sriov_msg_os_info { uint32_t all; }; +struct amd_sriov_msg_uuid_info { + union { + struct { + uint32_t did : 16; + uint32_t fcn : 8; + uint32_t asic_7 : 8; + }; + uint32_t time_low; + }; + + struct { + uint32_t time_mid : 16; + uint32_t time_high : 12; + uint32_t version : 4; + }; + + struct { + struct { + uint8_t clk_seq_hi : 6; + uint8_t variant : 2; + }; + union { + uint8_t clk_seq_low; + uint8_t asic_6; + }; + uint16_t asic_4; + }; + + uint32_t asic_0; +}; + struct amd_sriov_msg_pf2vf_info_header { /* the total structure size in byte */ uint32_t size; @@ -160,10 +193,19 @@ struct amd_sriov_msg_pf2vf_info { /* identification in ROCm SMI */ uint64_t uuid; uint32_t fcn_idx; - /* flags which indicate the register access method VF should use */ + /* flags to indicate which register access method VF should use */ union amd_sriov_reg_access_flags reg_access_flags; + /* MM BW management */ + struct { + uint32_t decode_max_dimension_pixels; + uint32_t decode_max_frame_pixels; + uint32_t encode_max_dimension_pixels; + uint32_t encode_max_frame_pixels; + } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; + /* UUID info */ + struct amd_sriov_msg_uuid_info uuid_info; /* reserved */ - uint32_t reserved[256-27]; + uint32_t reserved[256 - 47]; }; struct amd_sriov_msg_vf2pf_info_header { diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c index 2ac4988ea0ff..c12c2900732b 100644 --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c @@ -74,6 +74,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE); break; diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 3dcb8b32f48b..6fa2229b7229 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -31,6 +31,7 @@ #define ATOM_DEBUG +#include "atomfirmware.h" #include "atom.h" #include "atom-names.h" #include "atom-bits.h" @@ -1299,12 +1300,168 @@ static void atom_index_iio(struct atom_context *ctx, int base) } } +static void atom_get_vbios_name(struct atom_context *ctx) +{ + unsigned char *p_rom; + unsigned char str_num; + unsigned short off_to_vbios_str; + unsigned char *c_ptr; + int name_size; + int i; + + const char *na = "--N/A--"; + char *back; + + p_rom = ctx->bios; + + str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS); + if (str_num != 0) { + off_to_vbios_str = + *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START); + + c_ptr = (unsigned char *)(p_rom + off_to_vbios_str); + } else { + /* do not know where to find name */ + memcpy(ctx->name, na, 7); + ctx->name[7] = 0; + return; + } + + /* + * skip the atombios strings, usually 4 + * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type + */ + for (i = 0; i < str_num; i++) { + while (*c_ptr != 0) + c_ptr++; + c_ptr++; + } + + /* skip the following 2 chars: 0x0D 0x0A */ + c_ptr += 2; + + name_size = strnlen(c_ptr, STRLEN_LONG - 1); + memcpy(ctx->name, c_ptr, name_size); + back = ctx->name + name_size; + while ((*--back) == ' ') + ; + *(back + 1) = '\0'; +} + +static void atom_get_vbios_date(struct atom_context *ctx) +{ + unsigned char *p_rom; + unsigned char *date_in_rom; + + p_rom = ctx->bios; + + date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE; + + ctx->date[0] = '2'; + ctx->date[1] = '0'; + ctx->date[2] = date_in_rom[6]; + ctx->date[3] = date_in_rom[7]; + ctx->date[4] = '/'; + ctx->date[5] = date_in_rom[0]; + ctx->date[6] = date_in_rom[1]; + ctx->date[7] = '/'; + ctx->date[8] = date_in_rom[3]; + ctx->date[9] = date_in_rom[4]; + ctx->date[10] = ' '; + ctx->date[11] = date_in_rom[9]; + ctx->date[12] = date_in_rom[10]; + ctx->date[13] = date_in_rom[11]; + ctx->date[14] = date_in_rom[12]; + ctx->date[15] = date_in_rom[13]; + ctx->date[16] = '\0'; +} + +static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start, + int end, int maxlen) +{ + unsigned long str_off; + unsigned char *p_rom; + unsigned short str_len; + + str_off = 0; + str_len = strnlen(str, maxlen); + p_rom = ctx->bios; + + for (; start <= end; ++start) { + for (str_off = 0; str_off < str_len; ++str_off) { + if (str[str_off] != *(p_rom + start + str_off)) + break; + } + + if (str_off == str_len || str[str_off] == 0) + return p_rom + start; + } + return NULL; +} + +static void atom_get_vbios_pn(struct atom_context *ctx) +{ + unsigned char *p_rom; + unsigned short off_to_vbios_str; + unsigned char *vbios_str; + int count; + + off_to_vbios_str = 0; + p_rom = ctx->bios; + + if (*(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS) != 0) { + off_to_vbios_str = + *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START); + + vbios_str = (unsigned char *)(p_rom + off_to_vbios_str); + } else { + vbios_str = p_rom + OFFSET_TO_VBIOS_PART_NUMBER; + } + + if (*vbios_str == 0) { + vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64); + if (vbios_str == NULL) + vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1; + } + if (vbios_str != NULL && *vbios_str == 0) + vbios_str++; + + if (vbios_str != NULL) { + count = 0; + while ((count < BIOS_STRING_LENGTH) && vbios_str[count] >= ' ' && + vbios_str[count] <= 'z') { + ctx->vbios_pn[count] = vbios_str[count]; + count++; + } + + ctx->vbios_pn[count] = 0; + } +} + +static void atom_get_vbios_version(struct atom_context *ctx) +{ + unsigned char *vbios_ver; + + /* find anchor ATOMBIOSBK-AMD */ + vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64); + if (vbios_ver != NULL) { + /* skip ATOMBIOSBK-AMD VER */ + vbios_ver += 18; + memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL); + } else { + ctx->vbios_ver_str[0] = '\0'; + } +} + struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) { int base; struct atom_context *ctx = kzalloc(sizeof(struct atom_context), GFP_KERNEL); char *str; + struct _ATOM_ROM_HEADER *atom_rom_header; + struct _ATOM_MASTER_DATA_TABLE *master_table; + struct _ATOM_FIRMWARE_INFO *atom_fw_info; u16 idx; if (!ctx) @@ -1353,6 +1510,21 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); } + atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base); + if (atom_rom_header->usMasterDataTableOffset != 0) { + master_table = (struct _ATOM_MASTER_DATA_TABLE *) + CSTR(atom_rom_header->usMasterDataTableOffset); + if (master_table->ListOfDataTables.FirmwareInfo != 0) { + atom_fw_info = (struct _ATOM_FIRMWARE_INFO *) + CSTR(master_table->ListOfDataTables.FirmwareInfo); + ctx->version = atom_fw_info->ulFirmwareRevision; + } + } + + atom_get_vbios_name(ctx); + atom_get_vbios_pn(ctx); + atom_get_vbios_date(ctx); + atom_get_vbios_version(ctx); return ctx; } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index d279759cab47..0c1839824520 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -112,6 +112,10 @@ struct drm_device; #define ATOM_IO_SYSIO 2 #define ATOM_IO_IIO 0x80 +#define STRLEN_NORMAL 32 +#define STRLEN_LONG 64 +#define STRLEN_VERYLONG 254 + struct card_info { struct drm_device *dev; void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ @@ -140,6 +144,12 @@ struct atom_context { uint32_t *scratch; int scratch_size_bytes; char vbios_version[20]; + + uint8_t name[STRLEN_LONG]; + uint8_t vbios_pn[STRLEN_LONG]; + uint32_t version; + uint8_t vbios_ver_str[STRLEN_NORMAL]; + uint8_t date[STRLEN_NORMAL]; }; extern int amdgpu_atom_debug; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index a3ba9ca11e98..f327becb022f 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -188,6 +188,8 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) { amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; + drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = true; } @@ -610,7 +612,7 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); + drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { @@ -675,7 +677,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c b/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c new file mode 100644 index 000000000000..608a113ce354 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c @@ -0,0 +1,54 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "nv.h" + +#include "soc15_common.h" +#include "soc15_hw_ip.h" +#include "beige_goby_ip_offset.h" + +int beige_goby_reg_base_init(struct amdgpu_device *adev) +{ + /* HW has more IP blocks, only initialize the block needed by driver */ + uint32_t i; + for (i = 0 ; i < MAX_INSTANCE ; ++i) { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index d3745711d55f..df385ffc9768 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -309,8 +309,7 @@ static int cik_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index c4bb8eed246d..c8ebd108548d 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -720,7 +720,7 @@ err0: } /** - * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART + * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART * * @ib: indirect buffer to fill with commands * @pe: addr of the page entry @@ -746,7 +746,7 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, } /** - * cik_sdma_vm_write_pages - update PTEs by writing them manually + * cik_sdma_vm_write_pte - update PTEs by writing them manually * * @ib: indirect buffer to fill with commands * @pe: addr of the page entry @@ -775,7 +775,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, } /** - * cik_sdma_vm_set_pages - update the page tables using sDMA + * cik_sdma_vm_set_pte_pde - update the page tables using sDMA * * @ib: indirect buffer to fill with commands * @pe: addr of the page entry @@ -804,7 +804,7 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, } /** - * cik_sdma_vm_pad_ib - pad the IB to the required number of dw + * cik_sdma_ring_pad_ib - pad the IB to the required number of dw * * @ring: amdgpu_ring structure holding ring information * @ib: indirect buffer to fill with padding diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 307c01301c87..b8c47e0cf37a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -301,8 +301,7 @@ static int cz_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index dbcb09cf83e6..c7803dc2b2d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -456,7 +456,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) } /** - * cik_get_number_of_dram_channels - get the number of dram channels + * si_get_number_of_dram_channels - get the number of dram channels * * @adev: amdgpu_device pointer * diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index 5c11144da051..33324427b555 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -421,6 +421,11 @@ static int dce_virtual_sw_init(void *handle) static int dce_virtual_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i = 0; + + for (i = 0; i < adev->mode_info.num_crtc; i++) + if (adev->mode_info.crtcs[i]) + hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); kfree(adev->mode_info.bios_hardcoded_edid); @@ -480,13 +485,6 @@ static int dce_virtual_hw_init(void *handle) static int dce_virtual_hw_fini(void *handle) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int i = 0; - - for (i = 0; imode_info.num_crtc; i++) - if (adev->mode_info.crtcs[i]) - hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c index 0d8459d63bac..14514a145c17 100644 --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c @@ -219,11 +219,11 @@ static void df_v3_6_query_hashes(struct amdgpu_device *adev) adev->df.hash_status.hash_2m = false; adev->df.hash_status.hash_1g = false; - if (adev->asic_type != CHIP_ARCTURUS) - return; - - /* encoding for hash-enabled on Arcturus */ - if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) { + /* encoding for hash-enabled on Arcturus and Aldebaran */ + if ((adev->asic_type == CHIP_ARCTURUS && + adev->df.funcs->get_fb_channel_number(adev) == 0xe) || + (adev->asic_type == CHIP_ALDEBARAN && + adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) { tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl); adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, DF_CS_UMC_AON0_DfGlobalCtrl, @@ -277,8 +277,14 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) { u32 tmp; - tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); - tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; + if (adev->asic_type == CHIP_ALDEBARAN) { + tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0); + tmp &= + ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; + } else { + tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); + tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; + } tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; return tmp; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0597aeb5f0e8..2d56b60bc058 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -47,7 +47,7 @@ #include "gfx_v10_0.h" #include "nbio_v2_3.h" -/** +/* * Navi10 has two graphic rings to share each graphic pipe. * 1. Primary ring * 2. Async ring @@ -235,6 +235,20 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); + static const struct soc15_reg_golden golden_settings_gc_10_1[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), @@ -1428,38 +1442,36 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) }; -static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write) +static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, + int write, u32 *rlcg_flag) { - /* always programed by rlcg, only for gc */ - if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) || - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) || - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) || - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) || - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) || - offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) { - if (!amdgpu_sriov_reg_indirect_gc(adev)) - *flag = GFX_RLCG_GC_WRITE_OLD; - else - *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; + switch (hwip) { + case GC_HWIP: + if (amdgpu_sriov_reg_indirect_gc(adev)) { + *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; - return true; + return true; + /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */ + } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) { + *rlcg_flag = GFX_RLCG_GC_WRITE_OLD; + + return true; + } + + break; + case MMHUB_HWIP: + if (amdgpu_sriov_reg_indirect_mmhub(adev) && + (acc_flags & AMDGPU_REGS_RLC) && write) { + *rlcg_flag = GFX_RLCG_MMHUB_WRITE; + return true; + } + + break; + default: + DRM_DEBUG("Not program register by RLCG\n"); } - /* currently support gc read/write, mmhub write */ - if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) && - offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) { - if (amdgpu_sriov_reg_indirect_gc(adev)) - *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; - else - return false; - } else { - if (amdgpu_sriov_reg_indirect_mmhub(adev)) - *flag = GFX_RLCG_MMHUB_WRITE; - else - return false; - } - - return true; + return false; } static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag) @@ -1526,36 +1538,34 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 return ret; } -static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag) +static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip) { - uint32_t rlcg_flag; + u32 rlcg_flag; - if (amdgpu_sriov_fullaccess(adev) && - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) { + if (!amdgpu_sriov_runtime(adev) && + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) { gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag); - return; } - if (flag & AMDGPU_REGS_NO_KIQ) + + if (acc_flags & AMDGPU_REGS_NO_KIQ) WREG32_NO_KIQ(offset, value); else WREG32(offset, value); } -static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag) +static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip) { - uint32_t rlcg_flag; + u32 rlcg_flag; - if (amdgpu_sriov_fullaccess(adev) && - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0)) + if (!amdgpu_sriov_runtime(adev) && + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag)) return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag); - if (flag & AMDGPU_REGS_NO_KIQ) + if (acc_flags & AMDGPU_REGS_NO_KIQ) return RREG32_NO_KIQ(offset); else return RREG32(offset); - - return 0; } static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = @@ -3377,6 +3387,30 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), }; +static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = +{ + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) +}; + static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), @@ -3416,6 +3450,41 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) }; +static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) +}; + #define DEFAULT_SH_MEM_CONFIG \ ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ @@ -3631,11 +3700,21 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_gc_10_3_vangogh, (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); break; + case CHIP_YELLOW_CARP: + soc15_program_register_sequence(adev, + golden_settings_gc_10_3_3, + (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); + break; case CHIP_DIMGREY_CAVEFISH: soc15_program_register_sequence(adev, golden_settings_gc_10_3_4, (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); break; + case CHIP_BEIGE_GOBY: + soc15_program_register_sequence(adev, + golden_settings_gc_10_3_5, + (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); + break; default: break; } @@ -3821,6 +3900,8 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfx.cp_fw_write_wait = true; break; default: @@ -3897,7 +3978,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) { const char *chip_name; char fw_name[40]; - char wks[10]; + char *wks = ""; int err; struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; @@ -3910,7 +3991,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); - memset(wks, 0, sizeof(wks)); switch (adev->asic_type) { case CHIP_NAVI10: chip_name = "navi10"; @@ -3919,7 +3999,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) chip_name = "navi14"; if (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)) - snprintf(wks, sizeof(wks), "_wks"); + wks = "_wks"; break; case CHIP_NAVI12: chip_name = "navi12"; @@ -3936,6 +4016,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) case CHIP_DIMGREY_CAVEFISH: chip_name = "dimgrey_cavefish"; break; + case CHIP_BEIGE_GOBY: + chip_name = "beige_goby"; + break; + case CHIP_YELLOW_CARP: + chip_name = "yellow_carp"; + break; default: BUG(); } @@ -4504,6 +4590,8 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfx.config.max_hw_contexts = 8; adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; @@ -4628,6 +4716,8 @@ static int gfx_v10_0_sw_init(void *handle) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfx.me.num_me = 1; adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; @@ -4860,7 +4950,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { bitmap = i * adev->gfx.config.max_sh_per_se + j; - if ((adev->asic_type == CHIP_SIENNA_CICHLID) && + if (((adev->asic_type == CHIP_SIENNA_CICHLID) || + (adev->asic_type == CHIP_YELLOW_CARP)) && ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) continue; gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); @@ -5190,10 +5281,10 @@ static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) uint32_t tmp; /* enable Save Restore Machine */ - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); + WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); } static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) @@ -6135,6 +6226,8 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); @@ -6270,6 +6363,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); break; default: @@ -6282,6 +6377,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); @@ -6378,6 +6475,8 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); tmp &= 0xffffff00; tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); @@ -7092,6 +7191,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); @@ -7105,6 +7205,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) } break; case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: return true; default: data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); @@ -7126,6 +7227,9 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) { uint32_t data; + if (amdgpu_sriov_vf(adev)) + return; + /* initialize cam_index to 0 * index will auto-inc after each data writting */ WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); @@ -7135,6 +7239,8 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << GRBM_CAM_DATA__CAM_ADDR__SHIFT) | @@ -7344,7 +7450,7 @@ static int gfx_v10_0_hw_fini(void *handle) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); - if (!adev->in_pci_err_recovery) { + if (!adev->no_hw_access) { #ifndef BRING_UP_DEBUG if (amdgpu_async_gfx_ring) { r = gfx_v10_0_kiq_disable_kgq(adev); @@ -7450,6 +7556,8 @@ static int gfx_v10_0_soft_reset(void *handle) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, @@ -7503,6 +7611,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) mutex_lock(&adev->gfx.gpu_clock_mutex); switch (adev->asic_type) { case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); break; @@ -7559,6 +7668,8 @@ static int gfx_v10_0_early_init(void *handle) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; break; default: @@ -7615,6 +7726,8 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); /* wait for RLC_SAFE_MODE */ @@ -7649,6 +7762,8 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); break; default: @@ -7891,12 +8006,12 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) { u32 reg, data; - + /* not for *_SOC15 */ reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev)) data = RREG32_NO_KIQ(reg); else - data = RREG32(reg); + data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; @@ -7951,12 +8066,23 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) * in refclk count. Note that RLC FW is modified to take 16 bits from * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. * - * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20) - * as part of CGPG enablement starting point. + * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) + * of CGPG enablement starting point. + * Power/performance team will optimize it and might give a new value later. */ - if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) { - data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; - WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { + switch (adev->asic_type) { + case CHIP_VANGOGH: + data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; + WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); + break; + case CHIP_YELLOW_CARP: + data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; + WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); + break; + default: + break; + } } } @@ -8016,9 +8142,11 @@ static int gfx_v10_0_set_powergating_state(void *handle, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: amdgpu_gfx_off_ctrl(adev, enable); break; case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: gfx_v10_cntl_pg(adev, enable); amdgpu_gfx_off_ctrl(adev, enable); break; @@ -8044,6 +8172,8 @@ static int gfx_v10_0_set_clockgating_state(void *handle, case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: gfx_v10_0_update_gfx_clock_gating(adev, state == AMD_CG_STATE_GATE); break; @@ -8636,16 +8766,16 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(cp_int_cntl_reg); + cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 0); - WREG32(cp_int_cntl_reg, cp_int_cntl); + WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(cp_int_cntl_reg); + cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 1); - WREG32(cp_int_cntl_reg, cp_int_cntl); + WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); break; default: break; @@ -8689,16 +8819,16 @@ static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE, 0); - WREG32(mec_int_cntl_reg, mec_int_cntl); + WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE, 1); - WREG32(mec_int_cntl_reg, mec_int_cntl); + WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); break; default: break; @@ -8894,20 +9024,20 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, GENERIC2_INT_ENABLE, 0); WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); - tmp = RREG32(target); + tmp = RREG32_SOC15_IP(GC, target); tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, GENERIC2_INT_ENABLE, 0); - WREG32(target, tmp); + WREG32_SOC15_IP(GC, target, tmp); } else { tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, GENERIC2_INT_ENABLE, 1); WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); - tmp = RREG32(target); + tmp = RREG32_SOC15_IP(GC, target); tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, GENERIC2_INT_ENABLE, 1); - WREG32(target, tmp); + WREG32_SOC15_IP(GC, target, tmp); } break; default: @@ -9150,13 +9280,15 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_NAVI10: case CHIP_NAVI14: - case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; break; case CHIP_NAVI12: + case CHIP_SIENNA_CICHLID: adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; break; default: @@ -9239,7 +9371,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { bitmap = i * adev->gfx.config.max_sh_per_se + j; - if ((adev->asic_type == CHIP_SIENNA_CICHLID) && + if (((adev->asic_type == CHIP_SIENNA_CICHLID) || + (adev->asic_type == CHIP_YELLOW_CARP)) && ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) continue; mask = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index c35fdd2ef2d4..685212c3ddae 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2116,7 +2116,7 @@ error_free_scratch: } /** - * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp + * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp * * @ring: amdgpu_ring structure holding ring information * @@ -2242,7 +2242,7 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, * IB stuff */ /** - * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring + * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring * * @ring: amdgpu_ring structure holding ring information * @job: job to retrieve vmid from @@ -3196,7 +3196,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) } /** - * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP + * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP * * @ring: the ring to emit the commands to * diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 516467e962b7..044076ec1d03 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -734,7 +734,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, }; -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag) +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag) { static void *scratch_reg0; static void *scratch_reg1; @@ -787,15 +787,17 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 } -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag) +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, + u32 v, u32 acc_flags, u32 hwip) { - if (amdgpu_sriov_fullaccess(adev)) { - gfx_v9_0_rlcg_rw(adev, offset, v, flag); + if ((acc_flags & AMDGPU_REGS_RLC) && + amdgpu_sriov_fullaccess(adev)) { + gfx_v9_0_rlcg_w(adev, offset, v, acc_flags); return; } - if (flag & AMDGPU_REGS_NO_KIQ) + if (acc_flags & AMDGPU_REGS_NO_KIQ) WREG32_NO_KIQ(offset, v); else WREG32(offset, v); @@ -3937,7 +3939,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) { u32 tmp; - if (adev->asic_type != CHIP_ARCTURUS) + if (adev->asic_type != CHIP_ARCTURUS && + adev->asic_type != CHIP_ALDEBARAN) return; tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); @@ -4559,8 +4562,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) if (!ring->sched.ready) return 0; - if (adev->asic_type == CHIP_ARCTURUS || - adev->asic_type == CHIP_ALDEBARAN) { + if (adev->asic_type == CHIP_ARCTURUS) { vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); vgpr_init_regs_ptr = vgpr_init_regs_arcturus; @@ -4745,7 +4747,11 @@ static int gfx_v9_0_ecc_late_init(void *handle) } /* requires IBs so do in late init after IB pool is initialized */ - r = gfx_v9_0_do_edc_gpr_workarounds(adev); + if (adev->asic_type == CHIP_ALDEBARAN) + r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); + else + r = gfx_v9_0_do_edc_gpr_workarounds(adev); + if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index a30c7c10cd9a..1769c4cba2ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -22,6 +22,7 @@ */ #include "amdgpu.h" #include "soc15.h" +#include "soc15d.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" @@ -31,6 +32,11 @@ #include "amdgpu_ras.h" #include "amdgpu_gfx.h" +#define SE_ID_MAX 8 +#define CU_ID_MAX 16 +#define SIMD_ID_MAX 4 +#define WAVE_ID_MAX 10 + enum gfx_v9_4_2_utc_type { VML2_MEM, VML2_WALKER_MEM, @@ -79,6 +85,634 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20), }; +/** + * This shader is used to clear VGPRS and LDS, and also write the input + * pattern into the write back buffer, which will be used by driver to + * check whether all SIMDs have been covered. +*/ +static const u32 vgpr_init_compute_shader_aldebaran[] = { + 0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280, + 0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208, + 0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xd3d94000, + 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 0xd3d94003, + 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 0xd3d94006, + 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 0xd3d94009, + 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 0xd3d9400c, + 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 0xd3d9400f, + 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 0xd3d94012, + 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 0xd3d94015, + 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 0xd3d94018, + 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 0xd3d9401b, + 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 0xd3d9401e, + 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 0xd3d94021, + 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 0xd3d94024, + 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 0xd3d94027, + 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 0xd3d9402a, + 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 0xd3d9402d, + 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 0xd3d94030, + 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 0xd3d94033, + 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 0xd3d94036, + 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 0xd3d94039, + 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 0xd3d9403c, + 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 0xd3d9403f, + 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 0xd3d94042, + 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 0xd3d94045, + 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 0xd3d94048, + 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 0xd3d9404b, + 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 0xd3d9404e, + 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 0xd3d94051, + 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 0xd3d94054, + 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 0xd3d94057, + 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 0xd3d9405a, + 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 0xd3d9405d, + 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 0xd3d94060, + 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 0xd3d94063, + 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 0xd3d94066, + 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 0xd3d94069, + 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 0xd3d9406c, + 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 0xd3d9406f, + 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 0xd3d94072, + 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 0xd3d94075, + 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 0xd3d94078, + 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 0xd3d9407b, + 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 0xd3d9407e, + 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 0xd3d94081, + 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 0xd3d94084, + 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 0xd3d94087, + 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 0xd3d9408a, + 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 0xd3d9408d, + 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 0xd3d94090, + 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 0xd3d94093, + 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 0xd3d94096, + 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 0xd3d94099, + 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 0xd3d9409c, + 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 0xd3d9409f, + 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 0xd3d940a2, + 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 0xd3d940a5, + 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 0xd3d940a8, + 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 0xd3d940ab, + 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 0xd3d940ae, + 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 0xd3d940b1, + 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 0xd3d940b4, + 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 0xd3d940b7, + 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 0xd3d940ba, + 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 0xd3d940bd, + 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 0xd3d940c0, + 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 0xd3d940c3, + 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 0xd3d940c6, + 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 0xd3d940c9, + 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 0xd3d940cc, + 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 0xd3d940cf, + 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 0xd3d940d2, + 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 0xd3d940d5, + 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 0xd3d940d8, + 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 0xd3d940db, + 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 0xd3d940de, + 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 0xd3d940e1, + 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 0xd3d940e4, + 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 0xd3d940e7, + 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 0xd3d940ea, + 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 0xd3d940ed, + 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 0xd3d940f0, + 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 0xd3d940f3, + 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 0xd3d940f6, + 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 0xd3d940f9, + 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 0xd3d940fc, + 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 0xd3d940ff, + 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 0x7e000280, + 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 0x7e0c0280, + 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 0xd28c0001, + 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xbe8b0004, 0xb78b4000, + 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 0x00020201, + 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 0xbf84fff8, + 0xbf810000, +}; + +const struct soc15_reg_entry vgpr_init_regs_aldebaran[] = { + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 4 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0xbf }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x400006 }, /* 64KB LDS */ + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x3F }, /* 63 - accum-offset = 256 */ + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, +}; + +/** + * The below shaders are used to clear SGPRS, and also write the input + * pattern into the write back buffer. The first two dispatch should be + * scheduled simultaneously which make sure that all SGPRS could be + * allocated, so the dispatch 1 need check write back buffer before scheduled, + * make sure that waves of dispatch 0 are all dispacthed to all simds + * balanced. both dispatch 0 and dispatch 1 should be halted until all waves + * are dispatched, and then driver write a pattern to the shared memory to make + * all waves continue. +*/ +static const u32 sgpr112_init_compute_shader_aldebaran[] = { + 0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280, + 0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208, + 0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200, + 0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102, + 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080, + 0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080, + 0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080, + 0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080, + 0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080, + 0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080, + 0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080, + 0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080, + 0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080, + 0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080, + 0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080, + 0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080, + 0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080, + 0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080, + 0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080, + 0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080, + 0xbeda0080, 0xbedb0080, 0xbedc0080, 0xbedd0080, 0xbede0080, 0xbedf0080, + 0xbee00080, 0xbee10080, 0xbee20080, 0xbee30080, 0xbee40080, 0xbee50080, + 0xbf810000 +}; + +const struct soc15_reg_entry sgpr112_init_regs_aldebaran[] = { + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 8 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x340 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, +}; + +static const u32 sgpr96_init_compute_shader_aldebaran[] = { + 0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280, + 0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208, + 0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200, + 0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102, + 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080, + 0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080, + 0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080, + 0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080, + 0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080, + 0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080, + 0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080, + 0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080, + 0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080, + 0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080, + 0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080, + 0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080, + 0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080, + 0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080, + 0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080, + 0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080, + 0xbf810000, +}; + +const struct soc15_reg_entry sgpr96_init_regs_aldebaran[] = { + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0xc }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x2c0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, +}; + +/** + * This shader is used to clear the uninitiated sgprs after the above + * two dispatches, because of hardware feature, dispath 0 couldn't clear + * top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs +*/ +static const u32 sgpr64_init_compute_shader_aldebaran[] = { + 0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280, + 0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208, + 0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200, + 0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102, + 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080, + 0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080, + 0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080, + 0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080, + 0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080, + 0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080, + 0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080, + 0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080, + 0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080, + 0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080, + 0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbf810000, +}; + +const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = { + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0x10 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x1c0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, +}; + +static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + const u32 *shader_ptr, u32 shader_size, + const struct soc15_reg_entry *init_regs, u32 regs_size, + u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern, + struct dma_fence **fence_ptr) +{ + int r, i; + uint32_t total_size, shader_offset; + u64 gpu_addr; + + total_size = (regs_size * 3 + 4 + 5 + 5) * 4; + total_size = ALIGN(total_size, 256); + shader_offset = total_size; + total_size += ALIGN(shader_size, 256); + + /* allocate an indirect buffer to put the commands in */ + memset(ib, 0, sizeof(*ib)); + r = amdgpu_ib_get(adev, NULL, total_size, + AMDGPU_IB_POOL_DIRECT, ib); + if (r) { + dev_err(adev->dev, "failed to get ib (%d).\n", r); + return r; + } + + /* load the compute shaders */ + for (i = 0; i < shader_size/sizeof(u32); i++) + ib->ptr[i + (shader_offset / 4)] = shader_ptr[i]; + + /* init the ib length to 0 */ + ib->length_dw = 0; + + /* write the register state for the compute dispatch */ + for (i = 0; i < regs_size; i++) { + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); + ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) + - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = init_regs[i].reg_value; + } + + /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ + gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8; + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); + ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_PGM_LO) + - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr); + ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr); + + /* write the wb buffer address */ + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3); + ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_USER_DATA_0) + - PACKET3_SET_SH_REG_START; + ib->ptr[ib->length_dw++] = lower_32_bits(wb_gpu_addr); + ib->ptr[ib->length_dw++] = upper_32_bits(wb_gpu_addr); + ib->ptr[ib->length_dw++] = pattern; + + /* write dispatch packet */ + ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); + ib->ptr[ib->length_dw++] = compute_dim_x; /* x */ + ib->ptr[ib->length_dw++] = 1; /* y */ + ib->ptr[ib->length_dw++] = 1; /* z */ + ib->ptr[ib->length_dw++] = + REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); + + /* shedule the ib on the ring */ + r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr); + if (r) { + dev_err(adev->dev, "ib submit failed (%d).\n", r); + amdgpu_ib_free(adev, ib, NULL); + } + return r; +} + +static void gfx_v9_4_2_log_wave_assignment(struct amdgpu_device *adev, uint32_t *wb_ptr) +{ + uint32_t se, cu, simd, wave; + uint32_t offset = 0; + char *str; + int size; + + str = kmalloc(256, GFP_KERNEL); + if (!str) + return; + + dev_dbg(adev->dev, "wave assignment:\n"); + + for (se = 0; se < adev->gfx.config.max_shader_engines; se++) { + for (cu = 0; cu < CU_ID_MAX; cu++) { + memset(str, 0, 256); + size = sprintf(str, "SE[%02d]CU[%02d]: ", se, cu); + for (simd = 0; simd < SIMD_ID_MAX; simd++) { + size += sprintf(str + size, "["); + for (wave = 0; wave < WAVE_ID_MAX; wave++) { + size += sprintf(str + size, "%x", wb_ptr[offset]); + offset++; + } + size += sprintf(str + size, "] "); + } + dev_dbg(adev->dev, "%s\n", str); + } + } + + kfree(str); +} + +static int gfx_v9_4_2_wait_for_waves_assigned(struct amdgpu_device *adev, + uint32_t *wb_ptr, uint32_t mask, + uint32_t pattern, uint32_t num_wave, bool wait) +{ + uint32_t se, cu, simd, wave; + uint32_t loop = 0; + uint32_t wave_cnt; + uint32_t offset; + + do { + wave_cnt = 0; + offset = 0; + + for (se = 0; se < adev->gfx.config.max_shader_engines; se++) + for (cu = 0; cu < CU_ID_MAX; cu++) + for (simd = 0; simd < SIMD_ID_MAX; simd++) + for (wave = 0; wave < WAVE_ID_MAX; wave++) { + if (((1 << wave) & mask) && + (wb_ptr[offset] == pattern)) + wave_cnt++; + + offset++; + } + + if (wave_cnt == num_wave) + return 0; + + mdelay(1); + } while (++loop < 2000 && wait); + + dev_err(adev->dev, "actual wave num: %d, expected wave num: %d\n", + wave_cnt, num_wave); + + gfx_v9_4_2_log_wave_assignment(adev, wb_ptr); + + return -EBADSLT; +} + +static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev) +{ + int r; + int wb_size = adev->gfx.config.max_shader_engines * + CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX; + struct amdgpu_ib wb_ib; + struct amdgpu_ib disp_ibs[3]; + struct dma_fence *fences[3]; + u32 pattern[3] = { 0x1, 0x5, 0xa }; + + /* bail if the compute ring is not ready */ + if (!adev->gfx.compute_ring[0].sched.ready || + !adev->gfx.compute_ring[1].sched.ready) + return 0; + + /* allocate the write-back buffer from IB */ + memset(&wb_ib, 0, sizeof(wb_ib)); + r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t), + AMDGPU_IB_POOL_DIRECT, &wb_ib); + if (r) { + dev_err(adev->dev, "failed to get ib (%d) for wb\n", r); + return r; + } + memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t)); + + r = gfx_v9_4_2_run_shader(adev, + &adev->gfx.compute_ring[0], + &disp_ibs[0], + sgpr112_init_compute_shader_aldebaran, + sizeof(sgpr112_init_compute_shader_aldebaran), + sgpr112_init_regs_aldebaran, + ARRAY_SIZE(sgpr112_init_regs_aldebaran), + adev->gfx.cu_info.number, + wb_ib.gpu_addr, pattern[0], &fences[0]); + if (r) { + dev_err(adev->dev, "failed to clear first 224 sgprs\n"); + goto pro_end; + } + + r = gfx_v9_4_2_wait_for_waves_assigned(adev, + &wb_ib.ptr[1], 0b11, + pattern[0], + adev->gfx.cu_info.number * SIMD_ID_MAX * 2, + true); + if (r) { + dev_err(adev->dev, "wave coverage failed when clear first 224 sgprs\n"); + wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ + goto disp0_failed; + } + + r = gfx_v9_4_2_run_shader(adev, + &adev->gfx.compute_ring[1], + &disp_ibs[1], + sgpr96_init_compute_shader_aldebaran, + sizeof(sgpr96_init_compute_shader_aldebaran), + sgpr96_init_regs_aldebaran, + ARRAY_SIZE(sgpr96_init_regs_aldebaran), + adev->gfx.cu_info.number * 2, + wb_ib.gpu_addr, pattern[1], &fences[1]); + if (r) { + dev_err(adev->dev, "failed to clear next 576 sgprs\n"); + goto disp0_failed; + } + + r = gfx_v9_4_2_wait_for_waves_assigned(adev, + &wb_ib.ptr[1], 0b11111100, + pattern[1], adev->gfx.cu_info.number * SIMD_ID_MAX * 6, + true); + if (r) { + dev_err(adev->dev, "wave coverage failed when clear first 576 sgprs\n"); + wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ + goto disp1_failed; + } + + wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ + + /* wait for the GPU to finish processing the IB */ + r = dma_fence_wait(fences[0], false); + if (r) { + dev_err(adev->dev, "timeout to clear first 224 sgprs\n"); + goto disp1_failed; + } + + r = dma_fence_wait(fences[1], false); + if (r) { + dev_err(adev->dev, "timeout to clear first 576 sgprs\n"); + goto disp1_failed; + } + + memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t)); + r = gfx_v9_4_2_run_shader(adev, + &adev->gfx.compute_ring[0], + &disp_ibs[2], + sgpr64_init_compute_shader_aldebaran, + sizeof(sgpr64_init_compute_shader_aldebaran), + sgpr64_init_regs_aldebaran, + ARRAY_SIZE(sgpr64_init_regs_aldebaran), + adev->gfx.cu_info.number, + wb_ib.gpu_addr, pattern[2], &fences[2]); + if (r) { + dev_err(adev->dev, "failed to clear first 256 sgprs\n"); + goto disp1_failed; + } + + r = gfx_v9_4_2_wait_for_waves_assigned(adev, + &wb_ib.ptr[1], 0b1111, + pattern[2], + adev->gfx.cu_info.number * SIMD_ID_MAX * 4, + true); + if (r) { + dev_err(adev->dev, "wave coverage failed when clear first 256 sgprs\n"); + wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ + goto disp2_failed; + } + + wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */ + + r = dma_fence_wait(fences[2], false); + if (r) { + dev_err(adev->dev, "timeout to clear first 256 sgprs\n"); + goto disp2_failed; + } + +disp2_failed: + amdgpu_ib_free(adev, &disp_ibs[2], NULL); + dma_fence_put(fences[2]); +disp1_failed: + amdgpu_ib_free(adev, &disp_ibs[1], NULL); + dma_fence_put(fences[1]); +disp0_failed: + amdgpu_ib_free(adev, &disp_ibs[0], NULL); + dma_fence_put(fences[0]); +pro_end: + amdgpu_ib_free(adev, &wb_ib, NULL); + + if (r) + dev_info(adev->dev, "Init SGPRS Failed\n"); + else + dev_info(adev->dev, "Init SGPRS Successfully\n"); + + return r; +} + +static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev) +{ + int r; + /* CU_ID: 0~15, SIMD_ID: 0~3, WAVE_ID: 0 ~ 9 */ + int wb_size = adev->gfx.config.max_shader_engines * + CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX; + struct amdgpu_ib wb_ib; + struct amdgpu_ib disp_ib; + struct dma_fence *fence; + u32 pattern = 0xa; + + /* bail if the compute ring is not ready */ + if (!adev->gfx.compute_ring[0].sched.ready) + return 0; + + /* allocate the write-back buffer from IB */ + memset(&wb_ib, 0, sizeof(wb_ib)); + r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t), + AMDGPU_IB_POOL_DIRECT, &wb_ib); + if (r) { + dev_err(adev->dev, "failed to get ib (%d) for wb.\n", r); + return r; + } + memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t)); + + r = gfx_v9_4_2_run_shader(adev, + &adev->gfx.compute_ring[0], + &disp_ib, + vgpr_init_compute_shader_aldebaran, + sizeof(vgpr_init_compute_shader_aldebaran), + vgpr_init_regs_aldebaran, + ARRAY_SIZE(vgpr_init_regs_aldebaran), + adev->gfx.cu_info.number, + wb_ib.gpu_addr, pattern, &fence); + if (r) { + dev_err(adev->dev, "failed to clear vgprs\n"); + goto pro_end; + } + + /* wait for the GPU to finish processing the IB */ + r = dma_fence_wait(fence, false); + if (r) { + dev_err(adev->dev, "timeout to clear vgprs\n"); + goto disp_failed; + } + + r = gfx_v9_4_2_wait_for_waves_assigned(adev, + &wb_ib.ptr[1], 0b1, + pattern, + adev->gfx.cu_info.number * SIMD_ID_MAX, + false); + if (r) { + dev_err(adev->dev, "failed to cover all simds when clearing vgprs\n"); + goto disp_failed; + } + +disp_failed: + amdgpu_ib_free(adev, &disp_ib, NULL); + dma_fence_put(fence); +pro_end: + amdgpu_ib_free(adev, &wb_ib, NULL); + + if (r) + dev_info(adev->dev, "Init VGPRS Failed\n"); + else + dev_info(adev->dev, "Init VGPRS Successfully\n"); + + return r; +} + +int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev) +{ + /* only support when RAS is enabled */ + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) + return 0; + + gfx_v9_4_2_do_sgprs_init(adev); + + gfx_v9_4_2_do_vgprs_init(adev); + + return 0; +} + static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev); static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev); @@ -148,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1); WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); - WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); - tmp = 0; - tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1); - WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp); - WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); tmp = 0; tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12); @@ -808,8 +1437,9 @@ static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = { REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) }, }; -static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = - { SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 }; +static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = { + SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 +}; static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, @@ -1006,8 +1636,8 @@ static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev, return 0; } -int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, - void *ras_error_status) +static int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) { struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; uint32_t sec_count = 0, ded_count = 0; @@ -1039,20 +1669,24 @@ static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev) static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev) { uint32_t i, j; + uint32_t value; mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance; j++) { gfx_v9_4_2_select_se_sh(adev, i, 0, j); - WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10); + value = RREG32(SOC15_REG_ENTRY_OFFSET( + gfx_v9_4_2_ea_err_status_regs)); + value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1); + WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value); } } gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); } -void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) +static void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) { if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) return; @@ -1061,7 +1695,7 @@ void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL); } -int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if) +static int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if) { struct ras_inject_if *info = (struct ras_inject_if *)inject_if; int ret; @@ -1096,6 +1730,7 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) gfx_v9_4_2_select_se_sh(adev, i, 0, j); reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( gfx_v9_4_2_ea_err_status_regs)); + if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { @@ -1103,7 +1738,9 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) j, reg_value); } /* clear after read */ - WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10); + reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, + CLEAR_ERROR_STATUS, 0x1); + WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value); } } @@ -1134,7 +1771,7 @@ static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev) } } -void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) +static void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) { if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) return; @@ -1144,7 +1781,7 @@ void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) gfx_v9_4_2_query_sq_timeout_status(adev); } -void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) +static void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) { if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) return; @@ -1154,7 +1791,7 @@ void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) gfx_v9_4_2_reset_sq_timeout_status(adev); } -void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) +static void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) { uint32_t i; uint32_t data; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h index 81c5833b6b9f..6db1f88509af 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h @@ -29,6 +29,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, uint32_t die_id); void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev); +int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev); extern const struct amdgpu_gfx_ras_funcs gfx_v9_4_2_ras_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 1e4678cb98f0..bda1542ef1dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -283,10 +283,14 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, block_size); - /* Send no-retry XNACK on fault to suppress VM fault storm. */ + /* Send no-retry XNACK on fault to suppress VM fault storm. + * On Aldebaran, XNACK can be enabled in the SQ per-process. + * Retry faults need to be enabled for that to work. + */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, - !adev->gmc.noretry); + !adev->gmc.noretry || + adev->asic_type == CHIP_ALDEBARAN); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance, tmp); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, @@ -317,18 +321,6 @@ static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) { - if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { - /* - * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are - * VF copy registers so vbios post doesn't program them, for - * SRIOV driver need to program them - */ - WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, - adev->gmc.vram_start >> 24); - WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, - adev->gmc.vram_end >> 24); - } - /* GART Enable. */ gfxhub_v1_0_init_gart_aperture_regs(adev); gfxhub_v1_0_init_system_aperture_regs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c index 41807817de7d..1a374ec0514a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c @@ -31,6 +31,9 @@ #include "soc15_common.h" +#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8 +#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0 + static const char *gfxhub_client_ids[] = { "CB/DB", "Reserved", @@ -531,6 +534,42 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) return 0; } +static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) +{ + int i; + u32 tmp = 0, disabled_sa = 0; + u32 efuse_setting, vbios_setting; + + u32 max_sa_mask = amdgpu_gfx_create_bitmask( + adev->gfx.config.max_sh_per_se * + adev->gfx.config.max_shader_engines); + + if (adev->asic_type == CHIP_YELLOW_CARP) { + /* Get SA disabled bitmap from eFuse setting */ + efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); + efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; + efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; + + /* Get SA disabled bitmap from VBIOS setting */ + vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); + vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; + vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; + + disabled_sa |= efuse_setting | vbios_setting; + /* Make sure not to report harvested SAs beyond the max SA count */ + disabled_sa &= max_sa_mask; + + for (i = 0; disabled_sa > 0; i++) { + if (disabled_sa & 1) + tmp |= 0x3 << (i * 2); + disabled_sa >>= 1; + } + disabled_sa = tmp; + + WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa); + } +} + const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { .get_fb_location = gfxhub_v2_1_get_fb_location, .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, @@ -540,4 +579,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, .init = gfxhub_v2_1_init, .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, + .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 498b28a35f5b..4523df2785d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -229,6 +229,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, /* Use register 17 for GART */ const unsigned eng = 17; unsigned int i; + unsigned char hub_ip = 0; + + hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? + GC_HWIP : MMHUB_HWIP; spin_lock(&adev->gmc.invalidate_lock); /* @@ -242,8 +246,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, if (use_semaphore) { for (i = 0; i < adev->usec_timeout; i++) { /* a read return value of 1 means semaphore acuqire */ - tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + - hub->eng_distance * eng); + tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + + hub->eng_distance * eng, hub_ip); + if (tmp & 0x1) break; udelay(1); @@ -253,7 +258,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); } - WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); + WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + + hub->eng_distance * eng, + inv_req, hub_ip); /* * Issue a dummy read to wait for the ACK register to be cleared @@ -261,12 +268,14 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, */ if ((vmhub == AMDGPU_GFXHUB_0) && (adev->asic_type < CHIP_SIENNA_CICHLID)) - RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); + RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + + hub->eng_distance * eng, hub_ip); /* Wait for ACK with a delay.*/ for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + - hub->eng_distance * eng); + tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + + hub->eng_distance * eng, hub_ip); + tmp &= 1 << vmid; if (tmp) break; @@ -280,15 +289,15 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, * add semaphore release after invalidation, * write with 0 means semaphore release */ - WREG32_NO_KIQ(hub->vm_inv_eng0_sem + - hub->eng_distance * eng, 0); + WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + + hub->eng_distance * eng, 0, hub_ip); spin_unlock(&adev->gmc.invalidate_lock); if (i < adev->usec_timeout) return; - DRM_ERROR("Timeout waiting for VM flush ACK!\n"); + DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); } /** @@ -666,6 +675,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: adev->mmhub.funcs = &mmhub_v2_3_funcs; break; default: @@ -681,6 +691,8 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->gfxhub.funcs = &gfxhub_v2_1_funcs; break; default: @@ -796,6 +808,8 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: default: adev->gmc.gart_size = 512ULL << 20; break; @@ -863,6 +877,8 @@ static int gmc_v10_0_sw_init(void *handle) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->num_vmhubs = 2; /* * To fulfill 4-level page support, @@ -920,6 +936,7 @@ static int gmc_v10_0_sw_init(void *handle) return r; amdgpu_gmc_get_vbios_allocations(adev); + amdgpu_gmc_get_reserved_allocation(adev); /* Memory manager */ r = amdgpu_bo_init(adev); @@ -944,7 +961,7 @@ static int gmc_v10_0_sw_init(void *handle) } /** - * gmc_v8_0_gart_fini - vm fini callback + * gmc_v10_0_gart_fini - vm fini callback * * @adev: amdgpu_device pointer * @@ -953,7 +970,6 @@ static int gmc_v10_0_sw_init(void *handle) static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) { amdgpu_gart_table_vram_free(adev); - amdgpu_gart_fini(adev); } static int gmc_v10_0_sw_fini(void *handle) @@ -978,6 +994,8 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: break; default: break; @@ -1041,6 +1059,13 @@ static int gmc_v10_0_hw_init(void *handle) /* The sequence of these two function calls matters.*/ gmc_v10_0_init_golden_registers(adev); + /* + * harvestable groups in gc_utcl2 need to be programmed before any GFX block + * register setup within GMC, or else system hang when harvesting SA. + */ + if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) + adev->gfxhub.funcs->utcl2_harvest(adev); + r = gmc_v10_0_gart_enable(adev); if (r) return r; @@ -1133,7 +1158,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle, return r; if (adev->asic_type >= CHIP_SIENNA_CICHLID && - adev->asic_type <= CHIP_DIMGREY_CAVEFISH) + adev->asic_type <= CHIP_YELLOW_CARP) return athub_v2_1_set_clockgating(adev, state); else return athub_v2_0_set_clockgating(adev, state); @@ -1146,7 +1171,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) adev->mmhub.funcs->get_clockgating(adev, flags); if (adev->asic_type >= CHIP_SIENNA_CICHLID && - adev->asic_type <= CHIP_DIMGREY_CAVEFISH) + adev->asic_type <= CHIP_YELLOW_CARP) athub_v2_1_get_clockgating(adev, flags); else athub_v2_0_get_clockgating(adev, flags); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 405d6ad09022..0e81e03e9b49 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -898,7 +898,6 @@ static int gmc_v6_0_sw_fini(void *handle) amdgpu_vm_manager_fini(adev); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - amdgpu_gart_fini(adev); release_firmware(adev->gmc.fw); adev->gmc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 210ada2289ec..0a50fdaced7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -516,7 +516,7 @@ static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, } /** - * gmc_v8_0_set_fault_enable_default - update VM fault handling + * gmc_v7_0_set_fault_enable_default - update VM fault handling * * @adev: amdgpu_device pointer * @value: true redirects VM faults to the default page @@ -1085,7 +1085,6 @@ static int gmc_v7_0_sw_fini(void *handle) kfree(adev->gmc.vm_fault_info); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - amdgpu_gart_fini(adev); release_firmware(adev->gmc.fw); adev->gmc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index e4f27b3f28fb..492ebed2915b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1201,7 +1201,6 @@ static int gmc_v8_0_sw_fini(void *handle) kfree(adev->gmc.vm_fault_info); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - amdgpu_gart_fini(adev); release_firmware(adev->gmc.fw); adev->gmc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 455bb91060d0..7eb70d69f760 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -53,6 +53,7 @@ #include "mmhub_v1_7.h" #include "umc_v6_1.h" #include "umc_v6_0.h" +#include "hdp_v4_0.h" #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" @@ -1210,6 +1211,11 @@ static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) adev->gfxhub.funcs = &gfxhub_v1_0_funcs; } +static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) +{ + adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs; +} + static int gmc_v9_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1230,6 +1236,7 @@ static int gmc_v9_0_early_init(void *handle) gmc_v9_0_set_mmhub_funcs(adev); gmc_v9_0_set_mmhub_ras_funcs(adev); gmc_v9_0_set_gfxhub_funcs(adev); + gmc_v9_0_set_hdp_ras_funcs(adev); adev->gmc.shared_aperture_start = 0x2000000000000000ULL; adev->gmc.shared_aperture_end = @@ -1255,15 +1262,21 @@ static int gmc_v9_0_late_init(void *handle) * writes, while disables HBM ECC for vega10. */ if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { - if (!(adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC))) { + if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { if (adev->df.funcs->enable_ecc_force_par_wr_rmw) adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); } } - if (adev->mmhub.ras_funcs && - adev->mmhub.ras_funcs->reset_ras_error_count) - adev->mmhub.ras_funcs->reset_ras_error_count(adev); + if (!amdgpu_persistent_edc_harvesting_supported(adev)) { + if (adev->mmhub.ras_funcs && + adev->mmhub.ras_funcs->reset_ras_error_count) + adev->mmhub.ras_funcs->reset_ras_error_count(adev); + + if (adev->hdp.ras_funcs && + adev->hdp.ras_funcs->reset_ras_error_count) + adev->hdp.ras_funcs->reset_ras_error_count(adev); + } r = amdgpu_gmc_ras_late_init(adev); if (r) @@ -1275,10 +1288,7 @@ static int gmc_v9_0_late_init(void *handle) static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) { - u64 base = 0; - - if (!amdgpu_sriov_vf(adev)) - base = adev->mmhub.funcs->get_fb_location(adev); + u64 base = adev->mmhub.funcs->get_fb_location(adev); /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; @@ -1602,7 +1612,6 @@ static int gmc_v9_0_sw_fini(void *handle) amdgpu_gart_table_vram_free(adev); amdgpu_bo_unref(&adev->gmc.pdb0_bo); amdgpu_bo_fini(adev); - amdgpu_gart_fini(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index edbd35d293eb..74b90cc2bf48 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -59,12 +59,31 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); } +static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) +{ + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + + err_data->ue_count = 0; + err_data->ce_count = 0; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) + return; + + /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */ + err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); +}; + static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev) { if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) return; - /*read back hdp ras counter to reset it to 0 */ - RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); + + if (adev->asic_type >= CHIP_ALDEBARAN) + WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); + else + /*read back hdp ras counter to reset it to 0 */ + RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); } static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev, @@ -130,10 +149,16 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); } +const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = { + .ras_late_init = amdgpu_hdp_ras_late_init, + .ras_fini = amdgpu_hdp_ras_fini, + .query_ras_error_count = hdp_v4_0_query_ras_error_count, + .reset_ras_error_count = hdp_v4_0_reset_ras_error_count, +}; + const struct amdgpu_hdp_funcs hdp_v4_0_funcs = { .flush_hdp = hdp_v4_0_flush_hdp, .invalidate_hdp = hdp_v4_0_invalidate_hdp, - .reset_ras_error_count = hdp_v4_0_reset_ras_error_count, .update_clock_gating = hdp_v4_0_update_clock_gating, .get_clock_gating_state = hdp_v4_0_get_clockgating_state, .init_registers = hdp_v4_0_init_registers, diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h index d1e6399e8c46..dc3a1b81dd62 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h @@ -27,5 +27,6 @@ #include "soc15_common.h" extern const struct amdgpu_hdp_funcs hdp_v4_0_funcs; +extern const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index cc957471f31e..ddfe4eaeea05 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -300,8 +300,7 @@ static int iceland_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index bd77794315bc..01c242c5abc3 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -49,10 +49,13 @@ static int jpeg_v3_0_set_powergating_state(void *handle, static int jpeg_v3_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); - if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) - return -ENOENT; + if (adev->asic_type != CHIP_YELLOW_CARP) { + u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); + + if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) + return -ENOENT; + } adev->jpeg.num_jpeg_inst = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c index 0103a5ab28e6..f80a14a1b82d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c @@ -111,6 +111,9 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + if (amdgpu_sriov_vf(adev)) + return; + /* Program the system aperture low logical page number. */ WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); @@ -129,8 +132,6 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); } - if (amdgpu_sriov_vf(adev)) - return; /* Set default page address. */ value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); @@ -296,10 +297,12 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, block_size); - /* Send no-retry XNACK on fault to suppress VM fault storm. */ + /* On Aldebaran, XNACK can be enabled in the SQ per-process. + * Retry faults need to be enabled for that to work. + */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, - !adev->gmc.noretry); + 1); WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, @@ -330,18 +333,6 @@ static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev) static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev) { - if (amdgpu_sriov_vf(adev)) { - /* - * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are - * VF copy registers so vbios post doesn't program them, for - * SRIOV driver need to program them - */ - WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, - adev->gmc.vram_start >> 24); - WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, - adev->gmc.vram_end >> 24); - } - /* GART Enable. */ mmhub_v1_7_init_gart_aperture_regs(adev); mmhub_v1_7_init_system_aperture_regs(adev); @@ -1313,12 +1304,31 @@ static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev) } } +static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev) +{ + int i; + uint32_t reg_value; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) + return; + + for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) { + reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( + mmhub_v1_7_ea_err_status_regs[i])); + reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS, + CLEAR_ERROR_STATUS, 0x01); + WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]), + reg_value); + } +} + const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = { .ras_late_init = amdgpu_mmhub_ras_late_init, .ras_fini = amdgpu_mmhub_ras_fini, .query_ras_error_count = mmhub_v1_7_query_ras_error_count, .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count, .query_ras_error_status = mmhub_v1_7_query_ras_error_status, + .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status, }; const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index ac76081b91d5..f7e93bbc4e15 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -29,6 +29,7 @@ #include "mmhub/mmhub_2_0_0_default.h" #include "navi10_enum.h" +#include "gc/gc_10_1_0_offset.h" #include "soc15_common.h" #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d @@ -93,6 +94,30 @@ static const char *mmhub_client_ids_sienna_cichlid[][2] = { [15][1] = "OSS", }; +static const char *mmhub_client_ids_beige_goby[][2] = { + [3][0] = "DCEDMC", + [4][0] = "DCEVGA", + [5][0] = "MP0", + [6][0] = "MP1", + [8][0] = "VMC", + [9][0] = "VCNU0", + [11][0] = "VCN0", + [14][0] = "HDP", + [15][0] = "OSS", + [0][1] = "DBGU0", + [1][1] = "DBGU1", + [2][1] = "DCEDWB", + [3][1] = "DCEDMC", + [4][1] = "DCEVGA", + [5][1] = "MP0", + [6][1] = "MP1", + [7][1] = "XDP", + [9][1] = "VCNU0", + [11][1] = "VCN0", + [14][1] = "HDP", + [15][1] = "OSS", +}; + static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid, uint32_t flush_type) { @@ -139,6 +164,9 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, case CHIP_DIMGREY_CAVEFISH: mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; break; + case CHIP_BEIGE_GOBY: + mmhub_cid = mmhub_client_ids_beige_goby[cid][rw]; + break; default: mmhub_cid = NULL; break; @@ -165,11 +193,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); } @@ -180,14 +208,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, (u32)(adev->gmc.gart_start >> 12)); - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, (u32)(adev->gmc.gart_start >> 44)); - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, (u32)(adev->gmc.gart_end >> 12)); - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, (u32)(adev->gmc.gart_end >> 44)); } @@ -196,12 +224,12 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Program the AGP BAR */ - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); - if (!amdgpu_sriov_vf(adev)) { + /* Program the AGP BAR */ + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + /* Program the system aperture low logical page number. */ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); @@ -308,7 +336,7 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); } static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) @@ -370,16 +398,16 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, !adev->gmc.noretry); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance, tmp); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i * hub->ctx_addr_distance, 0); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i * hub->ctx_addr_distance, 0); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i * hub->ctx_addr_distance, lower_32_bits(adev->vm_manager.max_pfn - 1)); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i * hub->ctx_addr_distance, upper_32_bits(adev->vm_manager.max_pfn - 1)); } @@ -391,9 +419,9 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) unsigned i; for (i = 0; i < 18; ++i) { - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, i * hub->eng_addr_distance, 0xffffffff); - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, i * hub->eng_addr_distance, 0x1f); } } @@ -422,7 +450,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) /* Disable all tables */ for (i = 0; i < AMDGPU_NUM_VMID; i++) - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i * hub->ctx_distance, 0); /* Setup TLB control */ @@ -544,6 +572,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); break; @@ -578,6 +607,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: if (def != data) WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); if (def1 != data1) @@ -601,6 +631,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); break; default: @@ -618,6 +649,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); break; default: @@ -640,6 +672,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: mmhub_v2_0_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); mmhub_v2_0_update_medium_grain_light_sleep(adev, @@ -663,6 +696,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); break; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c index a9899335d0b1..88e457a150e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c @@ -92,6 +92,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, status); switch (adev->asic_type) { case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: mmhub_cid = mmhub_client_ids_vangogh[cid][rw]; break; default: @@ -569,9 +570,9 @@ static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev, return 0; mmhub_v2_3_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); mmhub_v2_3_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c index 47c8dd9d1c78..c4ef822bbe8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c @@ -436,7 +436,7 @@ static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev) } /** - * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling + * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling * * @adev: amdgpu_device pointer * @value: true redirects VM faults to the default page diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index f4e4040bbd25..530011622801 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev, ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, RB_USED_INT_THRESHOLD, threshold); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) + return; + } else { + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); + } + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, RB_USED_INT_THRESHOLD, threshold); - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) + return; + } else { + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); + } + WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); } @@ -151,7 +163,13 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); - WREG32(ih_regs->ih_rb_cntl, tmp); + + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) + return -ETIMEDOUT; + } else { + WREG32(ih_regs->ih_rb_cntl, tmp); + } if (enable) { ih->enabled = true; @@ -261,7 +279,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev, tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); } - WREG32(ih_regs->ih_rb_cntl, tmp); + + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { + DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); + return -ETIMEDOUT; + } + } else { + WREG32(ih_regs->ih_rb_cntl, tmp); + } if (ih == &adev->irq.ih) { /* set the ih ring 0 writeback address whether it's enabled or not */ @@ -311,6 +337,8 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); @@ -569,11 +597,7 @@ static int navi10_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); - amdgpu_ih_ring_fini(adev, &adev->irq.ih2); - amdgpu_ih_ring_fini(adev, &adev->irq.ih1); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c index 598ce0e93627..8f2a315e7c73 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c @@ -28,6 +28,25 @@ #include "nbio/nbio_7_2_0_sh_mask.h" #include +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN_YC 0x0100 +#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2 +#define regBIF1_PCIE_MST_CTRL_3 0x4601c6 +#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5 +#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \ + 0x1b +#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \ + 0x1c +#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \ + 0x08000000L +#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \ + 0x30000000L +#define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187 +#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5 +#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L +#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L + static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) { WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, @@ -38,7 +57,12 @@ static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) { - u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); + u32 tmp; + + if (adev->asic_type == CHIP_YELLOW_CARP) + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC); + else + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; @@ -49,11 +73,19 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, - BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | - BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); + if (adev->asic_type == CHIP_YELLOW_CARP) + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | + BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); + else + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | + BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); else - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); + if (adev->asic_type == CHIP_YELLOW_CARP) + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0); + else + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); } static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev) @@ -92,13 +124,13 @@ static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do if (use_doorbell) { doorbell_range = REG_SET_FIELD(doorbell_range, - GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, - doorbell_index); + GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, + doorbell_index); doorbell_range = REG_SET_FIELD(doorbell_range, - GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); + GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); } else { doorbell_range = REG_SET_FIELD(doorbell_range, - GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); + GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); } WREG32_PCIE_PORT(reg, doorbell_range); @@ -123,22 +155,22 @@ static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *ad if (enable) { tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, - DOORBELL_SELFRING_GPA_APER_EN, 1) | - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, - DOORBELL_SELFRING_GPA_APER_MODE, 1) | - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, - DOORBELL_SELFRING_GPA_APER_SIZE, 0); + DOORBELL_SELFRING_GPA_APER_EN, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_MODE, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_SIZE, 0); WREG32_SOC15(NBIO, 0, - regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, - lower_32_bits(adev->doorbell.base)); + regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, + lower_32_bits(adev->doorbell.base)); WREG32_SOC15(NBIO, 0, - regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, - upper_32_bits(adev->doorbell.base)); + regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, + upper_32_bits(adev->doorbell.base)); } WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, - tmp); + tmp); } @@ -218,19 +250,42 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev { uint32_t def, data; - def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { - data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | - PCIE_CNTL2__MST_MEM_LS_EN_MASK | - PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); - } else { - data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | - PCIE_CNTL2__MST_MEM_LS_EN_MASK | - PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); - } + if (adev->asic_type == CHIP_YELLOW_CARP) { + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) + data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; + else + data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; - if (def != data) - WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); + if (def != data) + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); + + data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1)); + def = data; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) + data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | + BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); + else + data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | + BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); + + if (def != data) + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), + data); + } else { + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) + data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + else + data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + + if (def != data) + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); + } } static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, @@ -297,14 +352,25 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = { static void nbio_v7_2_init_registers(struct amdgpu_device *adev) { uint32_t def, data; + if (adev->asic_type == CHIP_YELLOW_CARP) { + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3)); + data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); + data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); - def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); - data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); - data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); + if (def != data) + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data); + } else { + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); - if (def != data) - WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), - data); + if (def != data) + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data); + } } const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index d290ca0b06da..455d0425787c 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -218,14 +218,118 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode = .codec_array = sc_video_codecs_decode_array, }; +/* SRIOV Sienna Cichlid, not const since data is controlled by host */ +static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 4096, + .max_height = 2304, + .max_pixels_per_frame = 4096 * 2304, + .max_level = 0, + }, +}; + +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = +{ + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 3, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 5, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 52, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 4, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 186, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, + .max_width = 4096, + .max_height = 4096, + .max_pixels_per_frame = 4096 * 4096, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 0, + }, + { + .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, + .max_width = 8192, + .max_height = 4352, + .max_pixels_per_frame = 8192 * 4352, + .max_level = 0, + }, +}; + +static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = +{ + .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), + .codec_array = sriov_sc_video_codecs_encode_array, +}; + +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = +{ + .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), + .codec_array = sriov_sc_video_codecs_decode_array, +}; + static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, const struct amdgpu_video_codecs **codecs) { switch (adev->asic_type) { case CHIP_SIENNA_CICHLID: + if (amdgpu_sriov_vf(adev)) { + if (encode) + *codecs = &sriov_sc_video_codecs_encode; + else + *codecs = &sriov_sc_video_codecs_decode; + } else { + if (encode) + *codecs = &nv_video_codecs_encode; + else + *codecs = &sc_video_codecs_decode; + } + return 0; case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: if (encode) *codecs = &nv_video_codecs_encode; else @@ -363,7 +467,7 @@ void nv_grbm_select(struct amdgpu_device *adev, grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); + WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); } static void nv_vga_set_state(struct amdgpu_device *adev, bool state) @@ -530,10 +634,12 @@ nv_asic_reset_method(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: return AMD_RESET_METHOD_MODE2; case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: return AMD_RESET_METHOD_MODE1; default: if (amdgpu_dpm_is_baco_supported(adev)) @@ -598,7 +704,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev) static void nv_program_aspm(struct amdgpu_device *adev) { - if (amdgpu_aspm != 1) + if (!amdgpu_aspm) return; if (!(adev->flags & AMD_IS_APU) && @@ -675,6 +781,12 @@ legacy_init: case CHIP_DIMGREY_CAVEFISH: dimgrey_cavefish_reg_base_init(adev); break; + case CHIP_BEIGE_GOBY: + beige_goby_reg_base_init(adev); + break; + case CHIP_YELLOW_CARP: + yellow_carp_reg_base_init(adev); + break; default: return -EINVAL; } @@ -742,8 +854,13 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) case CHIP_NAVI12: amdgpu_device_ip_block_add(adev, &nv_common_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + if (!amdgpu_sriov_vf(adev)) { + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + } else { + amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + } if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) @@ -764,9 +881,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: amdgpu_device_ip_block_add(adev, &nv_common_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + if (!amdgpu_sriov_vf(adev)) { + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + } else { + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + } if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && is_support_sw_smu(adev)) amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); @@ -845,6 +968,48 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); break; + case CHIP_BEIGE_GOBY: + amdgpu_device_ip_block_add(adev, &nv_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && + is_support_sw_smu(adev)) + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); +#if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) + amdgpu_device_ip_block_add(adev, &dm_ip_block); +#endif + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && + is_support_sw_smu(adev)) + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); + break; + case CHIP_YELLOW_CARP: + amdgpu_device_ip_block_add(adev, &nv_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); + if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); +#if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) + amdgpu_device_ip_block_add(adev, &dm_ip_block); +#endif + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); + amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); + break; default: return -EINVAL; } @@ -1068,6 +1233,7 @@ static int nv_common_early_init(void *handle) case CHIP_SIENNA_CICHLID: adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_VCN_MGCG | @@ -1091,6 +1257,7 @@ static int nv_common_early_init(void *handle) case CHIP_NAVY_FLOUNDER: adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | @@ -1121,6 +1288,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_JPEG_MGCG; adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_VCN | @@ -1132,6 +1301,7 @@ static int nv_common_early_init(void *handle) case CHIP_DIMGREY_CAVEFISH: adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | @@ -1147,6 +1317,49 @@ static int nv_common_early_init(void *handle) AMD_PG_SUPPORT_MMHUB; adev->external_rev_id = adev->rev_id + 0x3c; break; + case CHIP_BEIGE_GOBY: + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_VCN_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_ATHUB | + AMD_PG_SUPPORT_MMHUB; + adev->external_rev_id = adev->rev_id + 0x46; + break; + case CHIP_YELLOW_CARP: + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_FGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_JPEG; + adev->external_rev_id = adev->rev_id + 0x01; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -1169,8 +1382,12 @@ static int nv_common_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); + amdgpu_virt_update_sriov_video_codec(adev, + sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), + sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); + } return 0; } @@ -1266,6 +1483,7 @@ static int nv_common_set_clockgating_state(void *handle, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: adev->nbio.funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); adev->nbio.funcs->update_medium_grain_light_sleep(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h index 515d67bf249f..eb9aff1e7253 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.h +++ b/drivers/gpu/drm/amd/amdgpu/nv.h @@ -36,4 +36,7 @@ int navi12_reg_base_init(struct amdgpu_device *adev); int sienna_cichlid_reg_base_init(struct amdgpu_device *adev); void vangogh_reg_base_init(struct amdgpu_device *adev); int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev); +int beige_goby_reg_base_init(struct amdgpu_device *adev); +int yellow_carp_reg_base_init(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 96064c343163..dd0dce254901 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -97,7 +97,6 @@ enum psp_gfx_cmd_id GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ - GFX_CMD_ID_CLEAR_VF_FW = 0x0000000D, /* Clear VF FW, to be used on VF shutdown. */ GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */ /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */ GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */ @@ -333,11 +332,16 @@ struct psp_gfx_uresp_fwar_db_info uint32_t fwar_db_addr_hi; }; +/* Command-specific response for boot config. */ +struct psp_gfx_uresp_bootcfg { + uint32_t boot_cfg; /* boot config data */ +}; + /* Union of command-specific responses for GPCOM ring. */ -union psp_gfx_uresp -{ - struct psp_gfx_uresp_reserved reserved; - struct psp_gfx_uresp_fwar_db_info fwar_db_info; +union psp_gfx_uresp { + struct psp_gfx_uresp_reserved reserved; + struct psp_gfx_uresp_bootcfg boot_cfg; + struct psp_gfx_uresp_fwar_db_info fwar_db_info; }; /* Structure of GFX Response buffer. diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 02bba1f3c42e..bc133db2d538 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_psp.h" @@ -63,6 +64,8 @@ MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 @@ -115,6 +118,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) case CHIP_DIMGREY_CAVEFISH: chip_name = "dimgrey_cavefish"; break; + case CHIP_BEIGE_GOBY: + chip_name = "beige_goby"; + break; default: BUG(); } @@ -200,6 +206,14 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) if (err) return err; break; + case CHIP_BEIGE_GOBY: + err = psp_init_sos_microcode(psp, chip_name); + if (err) + return err; + err = psp_init_ta_microcode(psp, chip_name); + if (err) + return err; + break; case CHIP_VANGOGH: err = psp_init_asd_microcode(psp, chip_name); if (err) @@ -269,10 +283,8 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy PSP KDB binary to memory */ - memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); + psp_copy_fw(psp, psp->kdb_start_addr, psp->kdb_bin_size); /* Provide the PSP KDB to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -302,10 +314,8 @@ static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy PSP SPL binary to memory */ - memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size); + psp_copy_fw(psp, psp->spl_start_addr, psp->spl_bin_size); /* Provide the PSP SPL to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -335,10 +345,8 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy PSP System Driver binary to memory */ - memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); + psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size); /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -371,10 +379,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); + psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size); /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -455,6 +461,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp, struct amdgpu_device *adev = psp->adev; if (amdgpu_sriov_vf(adev)) { + ring->ring_wptr = 0; ret = psp_v11_0_ring_stop(psp, ring_type); if (ret) { DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); @@ -608,7 +615,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) uint32_t p2c_header[4]; uint32_t sz; void *buf; - int ret; + int ret, idx; if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { DRM_DEBUG("Memory training is not supported.\n"); @@ -681,17 +688,24 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) return -ENOMEM; } - memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); - ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); - if (ret) { - DRM_ERROR("Send long training msg failed.\n"); - vfree(buf); - return ret; - } + if (drm_dev_enter(&adev->ddev, &idx)) { + memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); + ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); + if (ret) { + DRM_ERROR("Send long training msg failed.\n"); + vfree(buf); + drm_dev_exit(idx); + return ret; + } - memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); - adev->hdp.funcs->flush_hdp(adev, NULL); - vfree(buf); + memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); + adev->hdp.funcs->flush_hdp(adev, NULL); + vfree(buf); + drm_dev_exit(idx); + } else { + vfree(buf); + return -ENODEV; + } } if (ops & PSP_MEM_TRAIN_SAVE) { diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index c4828bd3264b..618e5b6b85d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -138,10 +138,8 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy PSP System Driver binary to memory */ - memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); + psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size); /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -179,10 +177,8 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); + psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size); /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index fcdce46445d6..c8949add88f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -31,6 +31,9 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); static int psp_v13_0_init_microcode(struct psp_context *psp) { @@ -42,17 +45,37 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case CHIP_ALDEBARAN: chip_name = "aldebaran"; break; + case CHIP_YELLOW_CARP: + chip_name = "yellow_carp"; + break; + default: + BUG(); + } + switch (adev->asic_type) { + case CHIP_ALDEBARAN: + err = psp_init_sos_microcode(psp, chip_name); + if (err) + return err; + err = psp_init_ta_microcode(&adev->psp, chip_name); + if (err) + return err; + break; + case CHIP_YELLOW_CARP: + err = psp_init_asd_microcode(psp, chip_name); + if (err) + return err; + err = psp_init_toc_microcode(psp, chip_name); + if (err) + return err; + err = psp_init_ta_microcode(psp, chip_name); + if (err) + return err; + break; default: BUG(); } - err = psp_init_sos_microcode(psp, chip_name); - if (err) - return err; - - err = psp_init_ta_microcode(&adev->psp, chip_name); - - return err; + return 0; } static bool psp_v13_0_is_sos_alive(struct psp_context *psp) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 908664a5774b..b86dcbabb635 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -102,10 +102,8 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy PSP System Driver binary to memory */ - memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); + psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size); /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -143,10 +141,8 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); + psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size); /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -231,6 +227,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp, psp_v3_1_reroute_ih(psp); if (amdgpu_sriov_vf(adev)) { + ring->ring_wptr = 0; ret = psp_v3_1_ring_stop(psp, ring_type); if (ret) { DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 9f0dda040ec8..4509bd4cce2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -271,7 +271,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, } /** - * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring * * @ring: amdgpu ring pointer * diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 5715be6770ec..ae5464e2535a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -754,7 +754,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) } /** - * sdma_v4_0_page_ring_set_wptr - commit the write pointer + * sdma_v4_0_ring_set_wptr - commit the write pointer * * @ring: amdgpu ring pointer * @@ -820,7 +820,7 @@ static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) } /** - * sdma_v4_0_ring_set_wptr - commit the write pointer + * sdma_v4_0_page_ring_set_wptr - commit the write pointer * * @ring: amdgpu ring pointer * @@ -1109,6 +1109,8 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) if (adev->asic_type == CHIP_ARCTURUS && adev->sdma.instance[i].fw_version >= 14) WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); + /* Extend page fault timeout to avoid interrupt storm */ + WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); } } @@ -2227,7 +2229,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, memset(&task_info, 0, sizeof(struct amdgpu_task_info)); amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); - dev_info(adev->dev, + dev_dbg_ratelimited(adev->dev, "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " "pasid:%u, for process %s pid %d thread %s pid %d\n", instance, addr, entry->src_id, entry->ring_id, entry->vmid, @@ -2240,7 +2242,7 @@ static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - dev_err(adev->dev, "MC or SEM address in VM hole\n"); + dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); sdma_v4_0_print_iv_entry(adev, entry); return 0; } @@ -2249,7 +2251,7 @@ static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); + dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); sdma_v4_0_print_iv_entry(adev, entry); return 0; } @@ -2258,7 +2260,7 @@ static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - dev_err(adev->dev, + dev_dbg_ratelimited(adev->dev, "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); sdma_v4_0_print_iv_entry(adev, entry); return 0; @@ -2268,7 +2270,7 @@ static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - dev_err(adev->dev, + dev_dbg_ratelimited(adev->dev, "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); sdma_v4_0_print_iv_entry(adev, entry); return 0; @@ -2597,27 +2599,18 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) { + adev->sdma.trap_irq.num_types = adev->sdma.num_instances; + adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; + /*For Arcturus and Aldebaran, add another 4 irq handler*/ switch (adev->sdma.num_instances) { - case 1: - adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; - adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; - break; case 5: - adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; - adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; - break; case 8: - adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; - adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; + adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; + adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; + adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; break; - case 2: default: - adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; - adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; break; } adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 8859133ce37e..6117ba8a4c3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -328,9 +328,9 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); } else { - wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); + wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); wptr = wptr << 32; - wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); + wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); } @@ -371,9 +371,9 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) lower_32_bits(ring->wptr << 2), ring->me, upper_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); } } @@ -409,18 +409,6 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, unsigned vmid = AMDGPU_JOB_GET_VMID(job); uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); - /* Invalidate L2, because if we don't do it, we might get stale cache - * lines from previous IBs. - */ - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); - amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV | - SDMA_GCR_GL2_WB | - SDMA_GCR_GLM_INV | - SDMA_GCR_GLM_WB) << 16); - amdgpu_ring_write(ring, 0xffffff80); - amdgpu_ring_write(ring, 0xffff); - /* An IB packet must end on a 8 DW boundary--the next dword * must be on a 8-dword boundary. Our IB packet below is 6 * dwords long, thus add x number of NOPs, such that, in @@ -441,6 +429,32 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); } +/** + * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse + * + * @ring: amdgpu ring pointer + * @job: job to retrieve vmid from + * @ib: IB object to schedule + * + * flush the IB by graphics cache rinse. + */ +static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) +{ + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | + SDMA_GCR_GLI_INV(1); + + /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); +} + /** * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring * @@ -534,12 +548,12 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) amdgpu_ttm_set_buffer_funcs_status(adev, false); for (i = 0; i < adev->sdma.num_instances; i++) { - rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); } } @@ -556,7 +570,7 @@ static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) } /** - * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch + * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch * * @adev: amdgpu_device pointer * @enable: enable/disable the DMA MEs context switch. @@ -600,11 +614,11 @@ static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) } if (enable && amdgpu_sdma_phase_quantum) { - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), phase_quantum); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), phase_quantum); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), phase_quantum); } if (!amdgpu_sriov_vf(adev)) @@ -671,58 +685,63 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) /* Set ring buffer size in dwords */ rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); /* Initialize the ring buffer's read and write pointers */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); /* setup the wptr shadow polling */ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); /* set the wb address whether it's enabled or not */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), + ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), + ring->gpu_addr >> 40); ring->wptr = 0; /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), + lower_32_bits(ring->wptr) << 2); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), + upper_32_bits(ring->wptr) << 2); } - doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_DOORBELL_OFFSET)); if (ring->use_doorbell) { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); @@ -731,8 +750,9 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) } else { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); } - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), + doorbell_offset); adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index, 20); @@ -741,7 +761,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) sdma_v5_0_ring_set_wptr(ring); /* set minor_ptr_update to 0 after wptr programed */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); if (!amdgpu_sriov_vf(adev)) { /* set utc l1 enable flag always to 1 */ @@ -775,15 +795,15 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif /* enable DMA IBs */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); ring->sched.ready = true; @@ -1647,6 +1667,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ .emit_ib = sdma_v5_0_ring_emit_ib, + .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync, .emit_fence = sdma_v5_0_ring_emit_fence, .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 240596b25fe4..7486e5306786 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -47,8 +47,10 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); #define SDMA1_REG_OFFSET 0x600 #define SDMA3_REG_OFFSET 0x400 @@ -92,6 +94,8 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: break; default: break; @@ -145,9 +149,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) - return 0; - DRM_DEBUG("\n"); switch (adev->asic_type) { @@ -163,6 +164,12 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) case CHIP_DIMGREY_CAVEFISH: chip_name = "dimgrey_cavefish"; break; + case CHIP_BEIGE_GOBY: + chip_name = "beige_goby"; + break; + case CHIP_YELLOW_CARP: + chip_name = "yellow_carp"; + break; default: BUG(); } @@ -182,6 +189,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) (void *)&adev->sdma.instance[0], sizeof(struct amdgpu_sdma_instance)); + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) + return 0; + DRM_DEBUG("psp_load == '%s'\n", adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); @@ -490,12 +500,12 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) amdgpu_ttm_set_buffer_funcs_status(adev, false); for (i = 0; i < adev->sdma.num_instances; i++) { - rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); } } @@ -512,7 +522,7 @@ static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) } /** - * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch + * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch * * @adev: amdgpu_device pointer * @enable: enable/disable the DMA MEs context switch. @@ -553,11 +563,11 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, AUTO_CTXSW_ENABLE, enable ? 1 : 0); if (enable && amdgpu_sdma_phase_quantum) { - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), phase_quantum); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), phase_quantum); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), phase_quantum); } WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); @@ -615,62 +625,62 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) ring = &adev->sdma.instance[i].ring; wb_offset = (ring->rptr_offs * 4); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); /* Set ring buffer size in dwords */ rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); /* Initialize the ring buffer's read and write pointers */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); /* setup the wptr shadow polling */ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); /* set the wb address whether it's enabled or not */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); ring->wptr = 0; /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); } - doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); if (ring->use_doorbell) { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); @@ -679,8 +689,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) } else { doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); } - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index, @@ -690,7 +700,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) sdma_v5_2_ring_set_wptr(ring); /* set minor_ptr_update to 0 after wptr programed */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); /* set utc l1 enable flag always to 1 */ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); @@ -701,19 +711,19 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); + temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); /* program default cache read and write policy */ - temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); + temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); /* clean read policy and write policy bits */ temp &= 0xFF0FFF; temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); if (!amdgpu_sriov_vf(adev)) { /* unhalt engine */ @@ -724,15 +734,15 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif /* enable DMA IBs */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); ring->sched.ready = true; @@ -1223,6 +1233,8 @@ static int sdma_v5_2_early_init(void *handle) adev->sdma.num_instances = 2; break; case CHIP_VANGOGH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: adev->sdma.num_instances = 1; break; default: @@ -1551,6 +1563,10 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade int i; for (i = 0; i < adev->sdma.num_instances; i++) { + + if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) + adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { /* Enable sdma clock gating */ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); @@ -1584,6 +1600,10 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev int i; for (i = 0; i < adev->sdma.num_instances; i++) { + + if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) + adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { /* Enable sdma mem light sleep */ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); @@ -1615,6 +1635,8 @@ static int sdma_v5_2_set_clockgating_state(void *handle, case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: sdma_v5_2_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); sdma_v5_2_update_medium_grain_light_sleep(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index cb703e307238..195b45bcb8ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -305,7 +305,7 @@ err0: } /** - * cik_dma_vm_copy_pte - update PTEs by copying them from the GART + * si_dma_vm_copy_pte - update PTEs by copying them from the GART * * @ib: indirect buffer to fill with commands * @pe: addr of the page entry @@ -402,7 +402,7 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, } /** - * si_dma_pad_ib - pad the IB to the required number of dw + * si_dma_ring_pad_ib - pad the IB to the required number of dw * * @ring: amdgpu_ring pointer * @ib: indirect buffer to fill with padding @@ -415,7 +415,7 @@ static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) } /** - * cik_sdma_ring_emit_pipeline_sync - sync the pipeline + * si_dma_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer * diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 51880f6ef634..9a24f17a5750 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -175,8 +175,7 @@ static int si_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c index 079b094c48ad..39b7c206770f 100644 --- a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c @@ -89,7 +89,24 @@ static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev) } /** - * smuio_v13_0_supports_host_gpu_xgmi - detect xgmi interface between cpu and gpu/s. + * smuio_v13_0_get_socket_id - query socket id from FCH + * + * @adev: amdgpu device pointer + * + * Returns socket id + */ +static u32 smuio_v13_0_get_socket_id(struct amdgpu_device *adev) +{ + u32 data, socket_id; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); + + return socket_id; +} + +/** + * smuio_v13_0_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s. * * @adev: amdgpu device pointer * @@ -115,6 +132,7 @@ const struct amdgpu_smuio_funcs smuio_v13_0_funcs = { .get_rom_index_offset = smuio_v13_0_get_rom_index_offset, .get_rom_data_offset = smuio_v13_0_get_rom_data_offset, .get_die_id = smuio_v13_0_get_die_id, + .get_socket_id = smuio_v13_0_get_socket_id, .is_host_gpu_xgmi_supported = smuio_v13_0_is_host_gpu_xgmi_supported, .update_rom_clock_gating = smuio_v13_0_update_rom_clock_gating, .get_clock_gating_state = smuio_v13_0_get_clock_gating_state, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index e65c286f93a6..de85577c9cfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -633,7 +633,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, if (entry->and_mask == 0xffffffff) { tmp = entry->or_mask; } else { - tmp = RREG32(reg); + tmp = (entry->hwip == GC_HWIP) ? + RREG32_SOC15_IP(GC, reg) : RREG32(reg); + tmp &= ~(entry->and_mask); tmp |= (entry->or_mask & entry->and_mask); } @@ -644,7 +646,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) WREG32_RLC(reg, tmp); else - WREG32(reg, tmp); + (entry->hwip == GC_HWIP) ? + WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); } @@ -656,7 +659,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) int ret = 0; /* avoid NBIF got stuck when do RAS recovery in BACO reset */ - if (ras && ras->supported) + if (ras && adev->ras_enabled) adev->nbio.funcs->enable_doorbell_interrupt(adev, false); ret = amdgpu_dpm_baco_reset(adev); @@ -664,7 +667,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) return ret; /* re-enable doorbell interrupt after BACO exit */ - if (ras && ras->supported) + if (ras && adev->ras_enabled) adev->nbio.funcs->enable_doorbell_interrupt(adev, true); return 0; @@ -711,7 +714,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev) * 1. PMFW version > 0x284300: all cases use baco * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco */ - if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) + if (ras && adev->ras_enabled && + adev->pm.fw_version <= 0x283400) baco_reset = false; break; case CHIP_ALDEBARAN: @@ -817,7 +821,7 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) static void soc15_program_aspm(struct amdgpu_device *adev) { - if (amdgpu_aspm != 1) + if (!amdgpu_aspm) return; if (!(adev->flags & AMD_IS_APU) && @@ -1521,9 +1525,6 @@ static int soc15_common_late_init(void *handle) if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_get_irq(adev); - if (adev->hdp.funcs->reset_ras_error_count) - adev->hdp.funcs->reset_ras_error_count(adev); - if (adev->nbio.ras_funcs && adev->nbio.ras_funcs->ras_late_init) r = adev->nbio.ras_funcs->ras_late_init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 14bd794bbea6..0eeb5e073be8 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -27,28 +27,51 @@ /* Register Access Macros */ #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \ + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \ + WREG32(reg, value)) + +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \ + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \ + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \ + RREG32(reg)) + #define WREG32_FIELD15(ip, idx, reg, field, val) \ - WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ - (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) + __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ + (__RREG32_SOC15_RLC__( \ + adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ + 0, ip##_HWIP) & \ + ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ + 0, ip##_HWIP) #define RREG32_SOC15(ip, inst, reg) \ - RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ + 0, ip##_HWIP) + +#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP) #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ - RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ + AMDGPU_REGS_NO_KIQ, ip##_HWIP) #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ - RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) + __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP) #define WREG32_SOC15(ip, inst, reg, value) \ - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ + value, 0, ip##_HWIP) + +#define WREG32_SOC15_IP(ip, reg, value) \ + __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP) #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ - WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) + __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ + value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \ + value, 0, ip##_HWIP) #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ ({ int ret = 0; \ @@ -77,12 +100,7 @@ }) #define WREG32_RLC(reg, value) \ - do { \ - if (adev->gfx.rlc.funcs->rlcg_wreg) \ - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \ - else \ - WREG32(reg, value); \ - } while (0) + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP) #define WREG32_RLC_EX(prefix, reg, value) \ do { \ @@ -108,24 +126,19 @@ } \ } while (0) +/* shadow the registers in the callback function */ #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ - WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP) +/* for GC only */ #define RREG32_RLC(reg) \ - (adev->gfx.rlc.funcs->rlcg_rreg ? \ - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg)) + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP) -#define WREG32_RLC_NO_KIQ(reg, value) \ - do { \ - if (adev->gfx.rlc.funcs->rlcg_wreg) \ - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, AMDGPU_REGS_NO_KIQ); \ - else \ - WREG32_NO_KIQ(reg, value); \ - } while (0) +#define WREG32_RLC_NO_KIQ(reg, value, hwip) \ + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) -#define RREG32_RLC_NO_KIQ(reg) \ - (adev->gfx.rlc.funcs->rlcg_rreg ? \ - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg)) +#define RREG32_RLC_NO_KIQ(reg, hwip) \ + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ do { \ @@ -146,12 +159,12 @@ } while (0) #define RREG32_SOC15_RLC(ip, inst, reg) \ - RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP) #define WREG32_SOC15_RLC(ip, inst, reg, value) \ do { \ uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\ - WREG32_RLC(target_reg, value); \ + __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \ } while (0) #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ @@ -161,14 +174,16 @@ } while (0) #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ - WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ - (RREG32_RLC(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ + (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ + AMDGPU_REGS_RLC, ip##_HWIP) & \ + ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ + AMDGPU_REGS_RLC, ip##_HWIP) #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ - WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP) #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ - RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)) + __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP) #endif diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h index 745ed0fba1ed..0f214a398dd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h +++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h @@ -105,6 +105,12 @@ struct ta_ras_trigger_error_input { uint64_t value; // method if error injection. i.e persistent, coherent etc. }; +struct ta_ras_init_flags +{ + uint8_t poison_mode_en; + uint8_t dgpu_mode; +}; + struct ta_ras_output_flags { uint8_t ras_init_success_flag; @@ -115,6 +121,7 @@ struct ta_ras_output_flags /* Common input structure for RAS callbacks */ /**********************************************************/ union ta_ras_cmd_input { + struct ta_ras_init_flags init_flags; struct ta_ras_enable_features_input enable_features; struct ta_ras_disable_features_input disable_features; struct ta_ras_trigger_error_input trigger_error; diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 249fcbee7871..b08905d1c00f 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -312,8 +312,7 @@ static int tonga_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c index 89d20adfa001..af59a35788e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c @@ -234,7 +234,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, err_addr &= ~((0x1ULL << lsb) - 1); /* translate umc channel address to soc pa, 3 parts are included */ - retired_page = ADDR_OF_8KB_BLOCK(err_addr) | + retired_page = ADDR_OF_4KB_BLOCK(err_addr) | ADDR_OF_256B_BLOCK(channel_index) | OFFSET_IN_256B_BLOCK(err_addr); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 284447d7a579..6c0e91495365 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -340,7 +340,7 @@ static int uvd_v3_1_start(struct amdgpu_device *adev) /* enable VCPU clock */ WREG32(mmUVD_VCPU_CNTL, 1 << 9); - /* disable interupt */ + /* disable interrupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); #ifdef __BIG_ENDIAN @@ -405,7 +405,7 @@ static int uvd_v3_1_start(struct amdgpu_device *adev) return r; } - /* enable interupt */ + /* enable interrupt */ WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 0cd98fcb1f9f..939bcfa2a4ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -363,6 +363,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) error: dma_fence_put(fence); + amdgpu_bo_unpin(bo); amdgpu_bo_unreserve(bo); amdgpu_bo_unref(&bo); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 8e238dea7bef..90910d19db12 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -25,6 +25,7 @@ */ #include +#include #include "amdgpu.h" #include "amdgpu_vce.h" @@ -555,16 +556,19 @@ static int vce_v4_0_hw_fini(void *handle) static int vce_v4_0_suspend(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int r; + int r, idx; if (adev->vce.vcpu_bo == NULL) return 0; - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); - void *ptr = adev->vce.cpu_addr; + if (drm_dev_enter(&adev->ddev, &idx)) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); + void *ptr = adev->vce.cpu_addr; - memcpy_fromio(adev->vce.saved_bo, ptr, size); + memcpy_fromio(adev->vce.saved_bo, ptr, size); + } + drm_dev_exit(idx); } r = vce_v4_0_hw_fini(adev); @@ -577,16 +581,20 @@ static int vce_v4_0_suspend(void *handle) static int vce_v4_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int r; + int r, idx; if (adev->vce.vcpu_bo == NULL) return -EINVAL; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); - void *ptr = adev->vce.cpu_addr; - memcpy_toio(ptr, adev->vce.saved_bo, size); + if (drm_dev_enter(&adev->ddev, &idx)) { + unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); + void *ptr = adev->vce.cpu_addr; + + memcpy_toio(ptr, adev->vce.saved_bo, size); + drm_dev_exit(idx); + } } else { r = amdgpu_vce_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 27b1ced145d2..284bb42d6c86 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -769,7 +769,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) } /** - * vcn_v1_0_start - start VCN block + * vcn_v1_0_start_spg_mode - start VCN block * * @adev: amdgpu_device pointer * @@ -1105,7 +1105,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) } /** - * vcn_v1_0_stop - stop VCN block + * vcn_v1_0_stop_spg_mode - stop VCN block * * @adev: amdgpu_device pointer * diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 3b23de996db2..47d4f04cbd69 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -34,6 +34,8 @@ #include "vcn/vcn_3_0_0_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" +#include + #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 @@ -85,16 +87,18 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); static int vcn_v3_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; if (amdgpu_sriov_vf(adev)) { - adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; + for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++) + if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) + adev->vcn.num_vcn_inst++; adev->vcn.harvest_config = 0; adev->vcn.num_enc_rings = 1; } else { if (adev->asic_type == CHIP_SIENNA_CICHLID) { u32 harvest; - int i; adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; for (i = 0; i < adev->vcn.num_vcn_inst; i++) { @@ -110,7 +114,10 @@ static int vcn_v3_0_early_init(void *handle) } else adev->vcn.num_vcn_inst = 1; - adev->vcn.num_enc_rings = 2; + if (adev->asic_type == CHIP_BEIGE_GOBY) + adev->vcn.num_enc_rings = 0; + else + adev->vcn.num_enc_rings = 2; } vcn_v3_0_set_dec_ring_funcs(adev); @@ -146,7 +153,8 @@ static int vcn_v3_0_sw_init(void *handle) adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); - if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { + if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) || + (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) { adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; adev->firmware.fw_size += @@ -268,16 +276,20 @@ static int vcn_v3_0_sw_init(void *handle) static int vcn_v3_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int i, r; + int i, r, idx; - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_fw_shared *fw_shared; + if (drm_dev_enter(&adev->ddev, &idx)) { + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + volatile struct amdgpu_fw_shared *fw_shared; - if (adev->vcn.harvest_config & (1 << i)) - continue; - fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; - fw_shared->present_flag_0 = 0; - fw_shared->sw_ring.is_enabled = false; + if (adev->vcn.harvest_config & (1 << i)) + continue; + fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; + fw_shared->present_flag_0 = 0; + fw_shared->sw_ring.is_enabled = false; + } + + drm_dev_exit(idx); } if (amdgpu_sriov_vf(adev)) @@ -316,19 +328,17 @@ static int vcn_v3_0_hw_init(void *handle) continue; ring = &adev->vcn.inst[i].ring_dec; - if (ring->sched.ready) { - ring->wptr = 0; - ring->wptr_old = 0; - vcn_v3_0_dec_ring_set_wptr(ring); - } + ring->wptr = 0; + ring->wptr_old = 0; + vcn_v3_0_dec_ring_set_wptr(ring); + ring->sched.ready = true; for (j = 0; j < adev->vcn.num_enc_rings; ++j) { ring = &adev->vcn.inst[i].ring_enc[j]; - if (ring->sched.ready) { - ring->wptr = 0; - ring->wptr_old = 0; - vcn_v3_0_enc_ring_set_wptr(ring); - } + ring->wptr = 0; + ring->wptr_old = 0; + vcn_v3_0_enc_ring_set_wptr(ring); + ring->sched.ready = true; } } } else { @@ -1254,23 +1264,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev) fw_shared->rb.wptr = lower_32_bits(ring->wptr); fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); - fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); - ring = &adev->vcn.inst[i].ring_enc[0]; - WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); - WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); - fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + if (adev->asic_type != CHIP_BEIGE_GOBY) { + fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); + ring = &adev->vcn.inst[i].ring_enc[0]; + WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); + fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); - fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); - ring = &adev->vcn.inst[i].ring_enc[1]; - WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); - WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); - fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); + ring = &adev->vcn.inst[i].ring_enc[1]; + WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); + fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + } } return 0; @@ -1293,8 +1305,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) uint32_t table_size; uint32_t size, size_dw; - bool is_vcn_ready; - struct mmsch_v3_0_cmd_direct_write direct_wt = { {0} }; struct mmsch_v3_0_cmd_direct_read_modify_write @@ -1486,30 +1496,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) } } - /* 6, check each VCN's init_status - * if it remains as 0, then this VCN is not assigned to current VF - * do not start ring for this VCN - */ - size = sizeof(struct mmsch_v3_0_init_header); - table_loc = (uint32_t *)table->cpu_addr; - memcpy(&header, (void *)table_loc, size); - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - is_vcn_ready = (header.inst[i].init_status == 1); - if (!is_vcn_ready) - DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); - - ring = &adev->vcn.inst[i].ring_dec; - ring->sched.ready = is_vcn_ready; - for (j = 0; j < adev->vcn.num_enc_rings; ++j) { - ring = &adev->vcn.inst[i].ring_enc[j]; - ring->sched.ready = is_vcn_ready; - } - } - return 0; } @@ -1650,31 +1636,33 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); - /* Restore */ - fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; - fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); - ring = &adev->vcn.inst[inst_idx].ring_enc[0]; - ring->wptr = 0; - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); - fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + if (adev->asic_type != CHIP_BEIGE_GOBY) { + /* Restore */ + fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; + fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); + ring = &adev->vcn.inst[inst_idx].ring_enc[0]; + ring->wptr = 0; + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); - fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); - ring = &adev->vcn.inst[inst_idx].ring_enc[1]; - ring->wptr = 0; - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); - WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); - fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); + fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); + ring = &adev->vcn.inst[inst_idx].ring_enc[1]; + ring->wptr = 0; + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); - /* restore wptr/rptr with pointers saved in FW shared memory*/ - WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); - WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); + /* restore wptr/rptr with pointers saved in FW shared memory*/ + WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); + WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); + } /* Unstall DPG */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), @@ -2131,7 +2119,8 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; adev->vcn.inst[i].ring_enc[j].me = i; } - DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); + if (adev->vcn.num_enc_rings > 0) + DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); } } diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index ca8efa5c6978..a9ca6988009e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -104,6 +104,7 @@ static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, tmp = RREG32(ih_regs->ih_rb_cntl); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); @@ -513,11 +514,7 @@ static int vega10_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); - amdgpu_ih_ring_fini(adev, &adev->irq.ih2); - amdgpu_ih_ring_fini(adev, &adev->irq.ih1); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 8a122b413bf5..f51dfc38ac65 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -565,11 +565,7 @@ static int vega20_ih_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_irq_fini(adev); - amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); - amdgpu_ih_ring_fini(adev, &adev->irq.ih2); - amdgpu_ih_ring_fini(adev, &adev->irq.ih1); - amdgpu_ih_ring_fini(adev, &adev->irq.ih); + amdgpu_irq_fini_sw(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 735ebbd1148f..3d21c0799037 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1136,7 +1136,7 @@ static void vi_program_aspm(struct amdgpu_device *adev) bool bL1SS = false; bool bClkReqSupport = true; - if (amdgpu_aspm != 1) + if (!amdgpu_aspm) return; if (adev->flags & AMD_IS_APU || diff --git a/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c new file mode 100644 index 000000000000..3d89421275ed --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c @@ -0,0 +1,51 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "nv.h" + +#include "soc15_common.h" +#include "soc15_hw_ip.h" +#include "yellow_carp_offset.h" + +int yellow_carp_reg_base_init(struct amdgpu_device *adev) +{ + /* HW has more IP blocks, only initialized the block needed by driver */ + uint32_t i; + for (i = 0 ; i < MAX_INSTANCE ; ++i) { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig index f02c938f75da..8cc0a76ddf9f 100644 --- a/drivers/gpu/drm/amd/amdkfd/Kconfig +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig @@ -12,3 +12,16 @@ config HSA_AMD select DRM_AMDGPU_USERPTR help Enable this if you want to use HSA features on AMD GPU devices. + +config HSA_AMD_SVM + bool "Enable HMM-based shared virtual memory manager" + depends on HSA_AMD && DEVICE_PRIVATE + default y + select HMM_MIRROR + select MMU_NOTIFIER + help + Enable this to use unified memory and managed memory in HIP. This + memory manager supports two modes of operation. One based on + preemptions and one based on page faults. To enable page fault + based memory management on most GFXv9 GPUs, set the module + parameter amdgpu.noretry=0. diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index e1e4115dcf78..c4f3aff11072 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -63,3 +63,8 @@ endif ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o endif + +ifneq ($(CONFIG_HSA_AMD_SVM),) +AMDKFD_FILES += $(AMDKFD_PATH)/kfd_svm.o \ + $(AMDKFD_PATH)/kfd_migrate.o +endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 43de260b2230..67541c30327a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -38,6 +38,7 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_dbgmgr.h" +#include "kfd_svm.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" @@ -1297,7 +1298,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->kgd, args->va_addr, args->size, - pdd->vm, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, (struct kgd_mem **) &mem, &offset, flags); if (err) @@ -1328,7 +1329,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, return 0; err_free: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return err; @@ -1365,7 +1367,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, - (struct kgd_mem *)mem, &size); + (struct kgd_mem *)mem, pdd->drm_priv, &size); /* If freeing the buffer failed, leave the handle in place for * clean-up during process tear-down. @@ -1391,6 +1393,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, long err = 0; int i; uint32_t *devices_arr = NULL; + bool table_freed = false; dev = kfd_device_by_id(GET_GPU_ID(args->handle)); if (!dev) @@ -1448,7 +1451,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, goto get_mem_obj_from_handle_failed; } err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( - peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm); + peer->kgd, (struct kgd_mem *)mem, + peer_pdd->drm_priv, &table_freed); if (err) { pr_err("Failed to map to gpu %d/%d\n", i, args->n_devices); @@ -1466,16 +1470,17 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, } /* Flush TLBs after waiting for the page table updates to complete */ - for (i = 0; i < args->n_devices; i++) { - peer = kfd_device_by_id(devices_arr[i]); - if (WARN_ON_ONCE(!peer)) - continue; - peer_pdd = kfd_get_process_device_data(peer, p); - if (WARN_ON_ONCE(!peer_pdd)) - continue; - kfd_flush_tlb(peer_pdd); + if (table_freed) { + for (i = 0; i < args->n_devices; i++) { + peer = kfd_device_by_id(devices_arr[i]); + if (WARN_ON_ONCE(!peer)) + continue; + peer_pdd = kfd_get_process_device_data(peer, p); + if (WARN_ON_ONCE(!peer_pdd)) + continue; + kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); + } } - kfree(devices_arr); return err; @@ -1555,7 +1560,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, goto get_mem_obj_from_handle_failed; } err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm); + peer->kgd, (struct kgd_mem *)mem, peer_pdd->drm_priv); if (err) { pr_err("Failed to unmap from gpu %d/%d\n", i, args->n_devices); @@ -1563,10 +1568,27 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, } args->n_success = i+1; } - kfree(devices_arr); - mutex_unlock(&p->mutex); + err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true); + if (err) { + pr_debug("Sync memory failed, wait interrupted by user signal\n"); + goto sync_memory_failed; + } + + /* Flush TLBs after waiting for the page table updates to complete */ + for (i = 0; i < args->n_devices; i++) { + peer = kfd_device_by_id(devices_arr[i]); + if (WARN_ON_ONCE(!peer)) + continue; + peer_pdd = kfd_get_process_device_data(peer, p); + if (WARN_ON_ONCE(!peer_pdd)) + continue; + kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); + } + + kfree(devices_arr); + return 0; bind_process_to_device_failed: @@ -1574,6 +1596,7 @@ get_mem_obj_from_handle_failed: unmap_memory_from_gpu_failed: mutex_unlock(&p->mutex); copy_from_user_failed: +sync_memory_failed: kfree(devices_arr); return err; } @@ -1701,7 +1724,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, - args->va_addr, pdd->vm, + args->va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, NULL); if (r) @@ -1721,7 +1744,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, return 0; err_free: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); dma_buf_put(dmabuf); @@ -1742,6 +1766,61 @@ static int kfd_ioctl_smi_events(struct file *filep, return kfd_smi_event_open(dev, &args->anon_fd); } +static int kfd_ioctl_set_xnack_mode(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_set_xnack_mode_args *args = data; + int r = 0; + + mutex_lock(&p->mutex); + if (args->xnack_enabled >= 0) { + if (!list_empty(&p->pqm.queues)) { + pr_debug("Process has user queues running\n"); + mutex_unlock(&p->mutex); + return -EBUSY; + } + if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) + r = -EPERM; + else + p->xnack_enabled = args->xnack_enabled; + } else { + args->xnack_enabled = p->xnack_enabled; + } + mutex_unlock(&p->mutex); + + return r; +} + +#if IS_ENABLED(CONFIG_HSA_AMD_SVM) +static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_svm_args *args = data; + int r = 0; + + pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", + args->start_addr, args->size, args->op, args->nattr); + + if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) + return -EINVAL; + if (!args->start_addr || !args->size) + return -EINVAL; + + mutex_lock(&p->mutex); + + r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, + args->attrs); + + mutex_unlock(&p->mutex); + + return r; +} +#else +static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) +{ + return -EPERM; +} +#endif + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -1840,6 +1919,11 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, kfd_ioctl_smi_events, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, + kfd_ioctl_set_xnack_mode, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index c60e82697385..c6b02aee4993 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -55,7 +55,7 @@ struct kfd_gpu_cache_info { uint32_t cache_level; uint32_t flags; /* Indicates how many Compute Units share this cache - * Value = 1 indicates the cache is not shared + * within a SA. Value = 1 indicates the cache is not shared */ uint32_t num_cu_shared; }; @@ -69,7 +69,6 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), .num_cu_shared = 1, - }, { /* Scalar L1 Instruction Cache (in SQC module) per bank */ @@ -126,9 +125,6 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { /* TODO: Add L2 Cache information */ }; -/* NOTE: In future if more information is added to struct kfd_gpu_cache_info - * the following ASICs may need a separate table. - */ #define hawaii_cache_info kaveri_cache_info #define tonga_cache_info carrizo_cache_info #define fiji_cache_info carrizo_cache_info @@ -136,13 +132,667 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { #define polaris11_cache_info carrizo_cache_info #define polaris12_cache_info carrizo_cache_info #define vegam_cache_info carrizo_cache_info -/* TODO - check & update Vega10 cache details */ -#define vega10_cache_info carrizo_cache_info -#define raven_cache_info carrizo_cache_info -#define renoir_cache_info carrizo_cache_info -/* TODO - check & update Navi10 cache details */ -#define navi10_cache_info carrizo_cache_info -#define vangogh_cache_info carrizo_cache_info + +/* NOTE: L1 cache information has been updated and L2/L3 + * cache information has been added for Vega10 and + * newer ASICs. The unit for cache_size is KiB. + * In future, check & update cache details + * for every new ASIC is required. + */ + +static struct kfd_gpu_cache_info vega10_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 4096, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 16, + }, +}; + +static struct kfd_gpu_cache_info raven_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 1024, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 11, + }, +}; + +static struct kfd_gpu_cache_info renoir_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 1024, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, +}; + +static struct kfd_gpu_cache_info vega12_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 2048, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 5, + }, +}; + +static struct kfd_gpu_cache_info vega20_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 3, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 8192, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 16, + }, +}; + +static struct kfd_gpu_cache_info aldebaran_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 8192, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 14, + }, +}; + +static struct kfd_gpu_cache_info navi10_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 4096, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, +}; + +static struct kfd_gpu_cache_info vangogh_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 1024, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, +}; + +static struct kfd_gpu_cache_info navi14_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 12, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 2048, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 12, + }, +}; + +static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 4096, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, + { + /* L3 Data Cache per GPU */ + .cache_size = 128*1024, + .cache_level = 3, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, +}; + +static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 3072, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, + { + /* L3 Data Cache per GPU */ + .cache_size = 96*1024, + .cache_level = 3, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 10, + }, +}; + +static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 2048, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, + { + /* L3 Data Cache per GPU */ + .cache_size = 32*1024, + .cache_level = 3, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, +}; + +static struct kfd_gpu_cache_info beige_goby_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 1024, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, + { + /* L3 Data Cache per GPU */ + .cache_size = 16*1024, + .cache_level = 3, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 8, + }, +}; + +static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { + { + /* TCP L1 Cache per CU */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 1, + }, + { + /* Scalar L1 Instruction Cache per SQC */ + .cache_size = 32, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_INST_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* Scalar L1 Data Cache per SQC */ + .cache_size = 16, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 2, + }, + { + /* GL1 Data Cache per SA */ + .cache_size = 128, + .cache_level = 1, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 6, + }, + { + /* L2 Data Cache per GPU (Total Tex Cache) */ + .cache_size = 2048, + .cache_level = 2, + .flags = (CRAT_CACHE_FLAGS_ENABLED | + CRAT_CACHE_FLAGS_DATA_CACHE | + CRAT_CACHE_FLAGS_SIMD_CACHE), + .num_cu_shared = 6, + }, +}; static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) @@ -544,7 +1194,7 @@ err: } /* Helper function. See kfd_fill_gpu_cache_info for parameter description */ -static int fill_in_pcache(struct crat_subtype_cache *pcache, +static int fill_in_l1_pcache(struct crat_subtype_cache *pcache, struct kfd_gpu_cache_info *pcache_info, struct kfd_cu_info *cu_info, int mem_available, @@ -597,6 +1247,70 @@ static int fill_in_pcache(struct crat_subtype_cache *pcache, return 1; } +/* Helper function. See kfd_fill_gpu_cache_info for parameter description */ +static int fill_in_l2_l3_pcache(struct crat_subtype_cache *pcache, + struct kfd_gpu_cache_info *pcache_info, + struct kfd_cu_info *cu_info, + int mem_available, + int cache_type, unsigned int cu_processor_id) +{ + unsigned int cu_sibling_map_mask; + int first_active_cu; + int i, j, k; + + /* First check if enough memory is available */ + if (sizeof(struct crat_subtype_cache) > mem_available) + return -ENOMEM; + + cu_sibling_map_mask = cu_info->cu_bitmap[0][0]; + cu_sibling_map_mask &= + ((1 << pcache_info[cache_type].num_cu_shared) - 1); + first_active_cu = ffs(cu_sibling_map_mask); + + /* CU could be inactive. In case of shared cache find the first active + * CU. and incase of non-shared cache check if the CU is inactive. If + * inactive active skip it + */ + if (first_active_cu) { + memset(pcache, 0, sizeof(struct crat_subtype_cache)); + pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY; + pcache->length = sizeof(struct crat_subtype_cache); + pcache->flags = pcache_info[cache_type].flags; + pcache->processor_id_low = cu_processor_id + + (first_active_cu - 1); + pcache->cache_level = pcache_info[cache_type].cache_level; + pcache->cache_size = pcache_info[cache_type].cache_size; + + /* Sibling map is w.r.t processor_id_low, so shift out + * inactive CU + */ + cu_sibling_map_mask = + cu_sibling_map_mask >> (first_active_cu - 1); + k = 0; + for (i = 0; i < cu_info->num_shader_engines; i++) { + for (j = 0; j < cu_info->num_shader_arrays_per_engine; + j++) { + pcache->sibling_map[k] = + (uint8_t)(cu_sibling_map_mask & 0xFF); + pcache->sibling_map[k+1] = + (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); + pcache->sibling_map[k+2] = + (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); + pcache->sibling_map[k+3] = + (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); + k += 4; + cu_sibling_map_mask = + cu_info->cu_bitmap[i % 4][j + i / 4]; + cu_sibling_map_mask &= ( + (1 << pcache_info[cache_type].num_cu_shared) + - 1); + } + } + return 0; + } + return 1; +} + /* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info * tables * @@ -624,6 +1338,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, int mem_available = available_size; unsigned int cu_processor_id; int ret; + unsigned int num_cu_shared; switch (kdev->device_info->asic_family) { case CHIP_KAVERI: @@ -663,13 +1378,22 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, num_of_cache_types = ARRAY_SIZE(vegam_cache_info); break; case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_ARCTURUS: - case CHIP_ALDEBARAN: pcache_info = vega10_cache_info; num_of_cache_types = ARRAY_SIZE(vega10_cache_info); break; + case CHIP_VEGA12: + pcache_info = vega12_cache_info; + num_of_cache_types = ARRAY_SIZE(vega12_cache_info); + break; + case CHIP_VEGA20: + case CHIP_ARCTURUS: + pcache_info = vega20_cache_info; + num_of_cache_types = ARRAY_SIZE(vega20_cache_info); + break; + case CHIP_ALDEBARAN: + pcache_info = aldebaran_cache_info; + num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info); + break; case CHIP_RAVEN: pcache_info = raven_cache_info; num_of_cache_types = ARRAY_SIZE(raven_cache_info); @@ -680,17 +1404,37 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, break; case CHIP_NAVI10: case CHIP_NAVI12: - case CHIP_NAVI14: - case CHIP_SIENNA_CICHLID: - case CHIP_NAVY_FLOUNDER: - case CHIP_DIMGREY_CAVEFISH: pcache_info = navi10_cache_info; num_of_cache_types = ARRAY_SIZE(navi10_cache_info); break; + case CHIP_NAVI14: + pcache_info = navi14_cache_info; + num_of_cache_types = ARRAY_SIZE(navi14_cache_info); + break; + case CHIP_SIENNA_CICHLID: + pcache_info = sienna_cichlid_cache_info; + num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info); + break; + case CHIP_NAVY_FLOUNDER: + pcache_info = navy_flounder_cache_info; + num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info); + break; + case CHIP_DIMGREY_CAVEFISH: + pcache_info = dimgrey_cavefish_cache_info; + num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info); + break; case CHIP_VANGOGH: pcache_info = vangogh_cache_info; num_of_cache_types = ARRAY_SIZE(vangogh_cache_info); break; + case CHIP_BEIGE_GOBY: + pcache_info = beige_goby_cache_info; + num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info); + break; + case CHIP_YELLOW_CARP: + pcache_info = yellow_carp_cache_info; + num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info); + break; default: return -EINVAL; } @@ -709,40 +1453,58 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, */ for (ct = 0; ct < num_of_cache_types; ct++) { - cu_processor_id = gpu_processor_id; - for (i = 0; i < cu_info->num_shader_engines; i++) { - for (j = 0; j < cu_info->num_shader_arrays_per_engine; - j++) { - for (k = 0; k < cu_info->num_cu_per_sh; - k += pcache_info[ct].num_cu_shared) { + cu_processor_id = gpu_processor_id; + if (pcache_info[ct].cache_level == 1) { + for (i = 0; i < cu_info->num_shader_engines; i++) { + for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) { + for (k = 0; k < cu_info->num_cu_per_sh; + k += pcache_info[ct].num_cu_shared) { + ret = fill_in_l1_pcache(pcache, + pcache_info, + cu_info, + mem_available, + cu_info->cu_bitmap[i % 4][j + i / 4], + ct, + cu_processor_id, + k); - ret = fill_in_pcache(pcache, - pcache_info, - cu_info, - mem_available, - cu_info->cu_bitmap[i % 4][j + i / 4], - ct, - cu_processor_id, - k); + if (ret < 0) + break; - if (ret < 0) - break; + if (!ret) { + pcache++; + (*num_of_entries)++; + mem_available -= sizeof(*pcache); + (*size_filled) += sizeof(*pcache); + } - if (!ret) { - pcache++; - (*num_of_entries)++; - mem_available -= - sizeof(*pcache); - (*size_filled) += - sizeof(*pcache); - } - - /* Move to next CU block */ - cu_processor_id += - pcache_info[ct].num_cu_shared; - } - } + /* Move to next CU block */ + num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <= + cu_info->num_cu_per_sh) ? + pcache_info[ct].num_cu_shared : + (cu_info->num_cu_per_sh - k); + cu_processor_id += num_cu_shared; } + } + } + } else { + ret = fill_in_l2_l3_pcache(pcache, + pcache_info, + cu_info, + mem_available, + ct, + cu_processor_id); + + if (ret < 0) + break; + + if (!ret) { + pcache++; + (*num_of_entries)++; + mem_available -= sizeof(*pcache); + (*size_filled) += sizeof(*pcache); + } + } } pr_debug("Added [%d] GPU cache entries\n", *num_of_entries); @@ -1100,6 +1862,92 @@ static int kfd_fill_gpu_memory_affinity(int *avail_size, return 0; } +#ifdef CONFIG_ACPI_NUMA +static void kfd_find_numa_node_in_srat(struct kfd_dev *kdev) +{ + struct acpi_table_header *table_header = NULL; + struct acpi_subtable_header *sub_header = NULL; + unsigned long table_end, subtable_len; + u32 pci_id = pci_domain_nr(kdev->pdev->bus) << 16 | + pci_dev_id(kdev->pdev); + u32 bdf; + acpi_status status; + struct acpi_srat_cpu_affinity *cpu; + struct acpi_srat_generic_affinity *gpu; + int pxm = 0, max_pxm = 0; + int numa_node = NUMA_NO_NODE; + bool found = false; + + /* Fetch the SRAT table from ACPI */ + status = acpi_get_table(ACPI_SIG_SRAT, 0, &table_header); + if (status == AE_NOT_FOUND) { + pr_warn("SRAT table not found\n"); + return; + } else if (ACPI_FAILURE(status)) { + const char *err = acpi_format_exception(status); + pr_err("SRAT table error: %s\n", err); + return; + } + + table_end = (unsigned long)table_header + table_header->length; + + /* Parse all entries looking for a match. */ + sub_header = (struct acpi_subtable_header *) + ((unsigned long)table_header + + sizeof(struct acpi_table_srat)); + subtable_len = sub_header->length; + + while (((unsigned long)sub_header) + subtable_len < table_end) { + /* + * If length is 0, break from this loop to avoid + * infinite loop. + */ + if (subtable_len == 0) { + pr_err("SRAT invalid zero length\n"); + break; + } + + switch (sub_header->type) { + case ACPI_SRAT_TYPE_CPU_AFFINITY: + cpu = (struct acpi_srat_cpu_affinity *)sub_header; + pxm = *((u32 *)cpu->proximity_domain_hi) << 8 | + cpu->proximity_domain_lo; + if (pxm > max_pxm) + max_pxm = pxm; + break; + case ACPI_SRAT_TYPE_GENERIC_AFFINITY: + gpu = (struct acpi_srat_generic_affinity *)sub_header; + bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | + *((u16 *)(&gpu->device_handle[2])); + if (bdf == pci_id) { + found = true; + numa_node = pxm_to_node(gpu->proximity_domain); + } + break; + default: + break; + } + + if (found) + break; + + sub_header = (struct acpi_subtable_header *) + ((unsigned long)sub_header + subtable_len); + subtable_len = sub_header->length; + } + + acpi_put_table(table_header); + + /* Workaround bad cpu-gpu binding case */ + if (found && (numa_node < 0 || + numa_node > pxm_to_node(max_pxm))) + numa_node = 0; + + if (numa_node != NUMA_NO_NODE) + set_dev_node(&kdev->pdev->dev, numa_node); +} +#endif + /* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU * to its NUMA node * @avail_size: Available size in the memory @@ -1140,11 +1988,17 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size, */ sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL; sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI; + sub_type_hdr->num_hops_xgmi = 1; } else { sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS; } sub_type_hdr->proximity_domain_from = proximity_domain; + +#ifdef CONFIG_ACPI_NUMA + if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) + kfd_find_numa_node_in_srat(kdev); +#endif #ifdef CONFIG_NUMA if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) sub_type_hdr->proximity_domain_to = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 357b9bf62a1c..6b57dfd2cd2a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -26,10 +26,12 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" +#include "kfd_pm4_headers_aldebaran.h" #include "cwsr_trap_handler.h" #include "kfd_iommu.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" +#include "kfd_migrate.h" #define MQD_SIZE_ALIGNED 768 @@ -80,6 +82,8 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd, + [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd, + [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd, }; #ifdef KFD_SUPPORT_IOMMU_V2 @@ -556,6 +560,41 @@ static const struct kfd_device_info dimgrey_cavefish_device_info = { .num_sdma_queues_per_engine = 8, }; +static const struct kfd_device_info beige_goby_device_info = { + .asic_family = CHIP_BEIGE_GOBY, + .asic_name = "beige_goby", + .max_pasid_bits = 16, + .max_no_of_hqd = 24, + .doorbell_size = 8, + .ih_ring_entry_size = 8 * sizeof(uint32_t), + .event_interrupt_class = &event_interrupt_class_v9, + .num_of_watch_points = 4, + .mqd_size_aligned = MQD_SIZE_ALIGNED, + .needs_iommu_device = false, + .supports_cwsr = true, + .needs_pci_atomics = true, + .num_sdma_engines = 1, + .num_xgmi_sdma_engines = 0, + .num_sdma_queues_per_engine = 8, +}; + +static const struct kfd_device_info yellow_carp_device_info = { + .asic_family = CHIP_YELLOW_CARP, + .asic_name = "yellow_carp", + .max_pasid_bits = 16, + .max_no_of_hqd = 24, + .doorbell_size = 8, + .ih_ring_entry_size = 8 * sizeof(uint32_t), + .event_interrupt_class = &event_interrupt_class_v9, + .num_of_watch_points = 4, + .mqd_size_aligned = MQD_SIZE_ALIGNED, + .needs_iommu_device = false, + .supports_cwsr = true, + .needs_pci_atomics = false, + .num_sdma_engines = 1, + .num_xgmi_sdma_engines = 0, + .num_sdma_queues_per_engine = 2, +}; /* For each entry, [0] is regular and [1] is virtualisation device. */ static const struct kfd_device_info *kfd_supported_devices[][2] = { @@ -576,7 +615,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = { [CHIP_VEGA20] = {&vega20_device_info, NULL}, [CHIP_RENOIR] = {&renoir_device_info, NULL}, [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, - [CHIP_ALDEBARAN] = {&aldebaran_device_info, NULL}, + [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info}, [CHIP_NAVI10] = {&navi10_device_info, NULL}, [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, [CHIP_NAVI14] = {&navi14_device_info, NULL}, @@ -584,6 +623,8 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = { [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info}, + [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info}, + [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL}, }; static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, @@ -697,7 +738,9 @@ static int kfd_gws_init(struct kfd_dev *kfd) && kfd->device_info->asic_family <= CHIP_RAVEN && kfd->mec2_fw_version >= 0x1b3) || (kfd->device_info->asic_family == CHIP_ARCTURUS - && kfd->mec2_fw_version >= 0x30)) + && kfd->mec2_fw_version >= 0x30) + || (kfd->device_info->asic_family == CHIP_ALDEBARAN + && kfd->mec2_fw_version >= 0x28)) ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); @@ -713,7 +756,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, const struct kgd2kfd_shared_resources *gpu_resources) { - unsigned int size; + unsigned int size, map_process_packet_size; kfd->ddev = ddev; kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, @@ -748,7 +791,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, * calculate max size of runlist packet. * There can be only 2 packets at once */ - size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + + map_process_packet_size = + kfd->device_info->asic_family == CHIP_ALDEBARAN ? + sizeof(struct pm4_mes_map_process_aldebaran) : + sizeof(struct pm4_mes_map_process); + size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) + sizeof(struct pm4_mes_runlist)) * 2; @@ -814,6 +861,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd_cwsr_init(kfd); + svm_migrate_init((struct amdgpu_device *)kfd->kgd); + if (kfd_resume(kfd)) goto kfd_resume_error; @@ -861,7 +910,7 @@ out: void kgd2kfd_device_exit(struct kfd_dev *kfd) { if (kfd->init_complete) { - kgd2kfd_suspend(kfd, false); + svm_migrate_fini((struct amdgpu_device *)kfd->kgd); device_queue_manager_uninit(kfd->dqm); kfd_interrupt_exit(kfd); kfd_topology_remove_device(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index d3eaa1549bd7..16a1713808c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -248,7 +248,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, qpd->vmid, qpd->page_table_base); /* invalidate the VM context after pasid and vmid mapping is set up */ - kfd_flush_tlb(qpd_to_pdd(qpd)); + kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); if (dqm->dev->kfd2kgd->set_scratch_backing_va) dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd, @@ -284,7 +284,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm, if (flush_texture_cache_nocpsch(q->device, qpd)) pr_err("Failed to flush TC\n"); - kfd_flush_tlb(qpd_to_pdd(qpd)); + kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); /* Release the vmid mapping */ set_pasid_vmid_mapping(dqm, 0, qpd->vmid); @@ -486,9 +486,6 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, if (retval == -ETIME) qpd->reset_wavefronts = true; - - mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); - list_del(&q->list); if (list_empty(&qpd->queues_list)) { if (qpd->reset_wavefronts) { @@ -523,6 +520,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, int retval; uint64_t sdma_val = 0; struct kfd_process_device *pdd = qpd_to_pdd(qpd); + struct mqd_manager *mqd_mgr = + dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; /* Get the SDMA queue stats */ if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || @@ -540,6 +539,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, pdd->sdma_past_activity_counter += sdma_val; dqm_unlock(dqm); + mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); + return retval; } @@ -738,7 +739,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, pdd = qpd_to_pdd(qpd); /* Retrieve PD base */ - pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); + pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); dqm_lock(dqm); if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ @@ -760,7 +761,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, dqm->dev->kgd, qpd->vmid, qpd->page_table_base); - kfd_flush_tlb(pdd); + kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); } /* Take a safe reference to the mm_struct, which may otherwise @@ -821,7 +822,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm, pdd = qpd_to_pdd(qpd); /* Retrieve PD base */ - pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); + pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); dqm_lock(dqm); if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ @@ -873,7 +874,7 @@ static int register_process(struct device_queue_manager *dqm, pdd = qpd_to_pdd(qpd); /* Retrieve PD base */ - pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); + pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); dqm_lock(dqm); list_add(&n->list, &dqm->queues); @@ -1629,7 +1630,7 @@ out: static int process_termination_nocpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { - struct queue *q, *next; + struct queue *q; struct device_process_node *cur, *next_dpn; int retval = 0; bool found = false; @@ -1637,12 +1638,19 @@ static int process_termination_nocpsch(struct device_queue_manager *dqm, dqm_lock(dqm); /* Clear all user mode queues */ - list_for_each_entry_safe(q, next, &qpd->queues_list, list) { + while (!list_empty(&qpd->queues_list)) { + struct mqd_manager *mqd_mgr; int ret; + q = list_first_entry(&qpd->queues_list, struct queue, list); + mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( + q->properties.type)]; ret = destroy_queue_nocpsch_locked(dqm, qpd, q); if (ret) retval = ret; + dqm_unlock(dqm); + mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); + dqm_lock(dqm); } /* Unregister process */ @@ -1674,36 +1682,34 @@ static int get_wave_state(struct device_queue_manager *dqm, u32 *save_area_used_size) { struct mqd_manager *mqd_mgr; - int r; dqm_lock(dqm); - if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || - q->properties.is_active || !q->device->cwsr_enabled) { - r = -EINVAL; - goto dqm_unlock; - } - mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; - if (!mqd_mgr->get_wave_state) { - r = -EINVAL; - goto dqm_unlock; + if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || + q->properties.is_active || !q->device->cwsr_enabled || + !mqd_mgr->get_wave_state) { + dqm_unlock(dqm); + return -EINVAL; } - r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, - ctl_stack_used_size, save_area_used_size); - -dqm_unlock: dqm_unlock(dqm); - return r; + + /* + * get_wave_state is outside the dqm lock to prevent circular locking + * and the queue should be protected against destruction by the process + * lock. + */ + return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, + ctl_stack_used_size, save_area_used_size); } static int process_termination_cpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { int retval; - struct queue *q, *next; + struct queue *q; struct kernel_queue *kq, *kq_next; struct mqd_manager *mqd_mgr; struct device_process_node *cur, *next_dpn; @@ -1760,6 +1766,19 @@ static int process_termination_cpsch(struct device_queue_manager *dqm, qpd->reset_wavefronts = false; } + /* Lastly, free mqd resources. + * Do free_mqd() after dqm_unlock to avoid circular locking. + */ + while (!list_empty(&qpd->queues_list)) { + q = list_first_entry(&qpd->queues_list, struct queue, list); + mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( + q->properties.type)]; + list_del(&q->list); + qpd->queue_count--; + dqm_unlock(dqm); + mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); + dqm_lock(dqm); + } dqm_unlock(dqm); /* Outside the DQM lock because under the DQM lock we can't do @@ -1768,17 +1787,6 @@ static int process_termination_cpsch(struct device_queue_manager *dqm, if (found) kfd_dec_compute_active(dqm->dev); - /* Lastly, free mqd resources. - * Do free_mqd() after dqm_unlock to avoid circular locking. - */ - list_for_each_entry_safe(q, next, &qpd->queues_list, list) { - mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( - q->properties.type)]; - list_del(&q->list); - qpd->queue_count--; - mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); - } - return retval; } @@ -1936,6 +1944,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: device_queue_manager_init_v10_navi10(&dqm->asic_ops); break; default: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c index eca6331efa94..b5c3d13643f1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c @@ -61,10 +61,19 @@ static int update_qpd_v9(struct device_queue_manager *dqm, qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; - if (dqm->dev->noretry && - !dqm->dev->use_iommu_v2) + + if (dqm->dev->device_info->asic_family == CHIP_ALDEBARAN) { + /* Aldebaran can safely support different XNACK modes + * per process + */ + if (!pdd->process->xnack_enabled) + qpd->sh_mem_config |= + 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + } else if (dqm->dev->noretry && + !dqm->dev->use_iommu_v2) { qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + } qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index ba2c2ce0c55a..3eea4edee355 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -1050,3 +1050,44 @@ void kfd_signal_reset_event(struct kfd_dev *dev) } srcu_read_unlock(&kfd_processes_srcu, idx); } + +void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid) +{ + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + struct kfd_hsa_memory_exception_data memory_exception_data; + struct kfd_hsa_hw_exception_data hw_exception_data; + struct kfd_event *ev; + uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID; + + if (!p) + return; /* Presumably process exited. */ + + memset(&hw_exception_data, 0, sizeof(hw_exception_data)); + hw_exception_data.gpu_id = dev->id; + hw_exception_data.memory_lost = 1; + hw_exception_data.reset_cause = KFD_HW_EXCEPTION_ECC; + + memset(&memory_exception_data, 0, sizeof(memory_exception_data)); + memory_exception_data.ErrorType = KFD_MEM_ERR_POISON_CONSUMED; + memory_exception_data.gpu_id = dev->id; + memory_exception_data.failure.imprecise = true; + + mutex_lock(&p->event_mutex); + idr_for_each_entry_continue(&p->event_idr, ev, id) { + if (ev->type == KFD_EVENT_TYPE_HW_EXCEPTION) { + ev->hw_exception_data = hw_exception_data; + set_event(ev); + } + + if (ev->type == KFD_EVENT_TYPE_MEMORY) { + ev->memory_exception_data = memory_exception_data; + set_event(ev); + } + } + mutex_unlock(&p->event_mutex); + + /* user application will handle SIGBUS signal */ + send_sig(SIGBUS, p->lead_thread, 0); + + kfd_unref_process(p); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index a2c9063076cc..a9b329f0f862 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -420,6 +420,8 @@ int kfd_init_apertures(struct kfd_process *process) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: kfd_init_apertures_v9(pdd, id); break; default: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index 696944fa0177..12d91e53556c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -25,7 +25,6 @@ #include "soc15_int.h" #include "kfd_device_queue_manager.h" #include "kfd_smi_events.h" -#include "amdgpu.h" enum SQ_INTERRUPT_WORD_ENCODING { SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, @@ -231,7 +230,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, sq_intr_err); if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { - kfd_signal_hw_exception_event(pasid); + kfd_signal_poison_consumed_event(dev, pasid); amdgpu_amdkfd_gpu_reset(dev->kgd); return; } @@ -250,8 +249,13 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, client_id == SOC15_IH_CLIENTID_SDMA5 || client_id == SOC15_IH_CLIENTID_SDMA6 || client_id == SOC15_IH_CLIENTID_SDMA7) { - if (source_id == SOC15_INTSRC_SDMA_TRAP) + if (source_id == SOC15_INTSRC_SDMA_TRAP) { kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + } else if (source_id == SOC15_INTSRC_SDMA_ECC) { + kfd_signal_poison_consumed_event(dev, pasid); + amdgpu_amdkfd_gpu_reset(dev->kgd); + return; + } } else if (client_id == SOC15_IH_CLIENTID_VMC || client_id == SOC15_IH_CLIENTID_VMC1 || client_id == SOC15_IH_CLIENTID_UTCL2) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c new file mode 100644 index 000000000000..2660f03e63a7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -0,0 +1,889 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2020-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include "amdgpu_sync.h" +#include "amdgpu_object.h" +#include "amdgpu_vm.h" +#include "amdgpu_mn.h" +#include "amdgpu_res_cursor.h" +#include "kfd_priv.h" +#include "kfd_svm.h" +#include "kfd_migrate.h" + +static uint64_t +svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, uint64_t addr) +{ + return addr + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); +} + +static int +svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages, + dma_addr_t *addr, uint64_t *gart_addr, uint64_t flags) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_job *job; + unsigned int num_dw, num_bytes; + struct dma_fence *fence; + uint64_t src_addr, dst_addr; + uint64_t pte_flags; + void *cpu_addr; + int r; + + /* use gart window 0 */ + *gart_addr = adev->gmc.gart_start; + + num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); + num_bytes = npages * 8; + + r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, + AMDGPU_IB_POOL_DELAYED, &job); + if (r) + return r; + + src_addr = num_dw * 4; + src_addr += job->ibs[0].gpu_addr; + + dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); + amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, + dst_addr, num_bytes, false); + + amdgpu_ring_pad_ib(ring, &job->ibs[0]); + WARN_ON(job->ibs[0].length_dw > num_dw); + + pte_flags = AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; + pte_flags |= AMDGPU_PTE_SYSTEM | AMDGPU_PTE_SNOOPED; + if (!(flags & KFD_IOCTL_SVM_FLAG_GPU_RO)) + pte_flags |= AMDGPU_PTE_WRITEABLE; + pte_flags |= adev->gart.gart_pte_flags; + + cpu_addr = &job->ibs[0].ptr[num_dw]; + + r = amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr); + if (r) + goto error_free; + + r = amdgpu_job_submit(job, &adev->mman.entity, + AMDGPU_FENCE_OWNER_UNDEFINED, &fence); + if (r) + goto error_free; + + dma_fence_put(fence); + + return r; + +error_free: + amdgpu_job_free(job); + return r; +} + +/** + * svm_migrate_copy_memory_gart - sdma copy data between ram and vram + * + * @adev: amdgpu device the sdma ring running + * @src: source page address array + * @dst: destination page address array + * @npages: number of pages to copy + * @direction: enum MIGRATION_COPY_DIR + * @mfence: output, sdma fence to signal after sdma is done + * + * ram address uses GART table continuous entries mapping to ram pages, + * vram address uses direct mapping of vram pages, which must have npages + * number of continuous pages. + * GART update and sdma uses same buf copy function ring, sdma is splited to + * multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wait for + * the last sdma finish fence which is returned to check copy memory is done. + * + * Context: Process context, takes and releases gtt_window_lock + * + * Return: + * 0 - OK, otherwise error code + */ + +static int +svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, + uint64_t *vram, uint64_t npages, + enum MIGRATION_COPY_DIR direction, + struct dma_fence **mfence) +{ + const uint64_t GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + uint64_t gart_s, gart_d; + struct dma_fence *next; + uint64_t size; + int r; + + mutex_lock(&adev->mman.gtt_window_lock); + + while (npages) { + size = min(GTT_MAX_PAGES, npages); + + if (direction == FROM_VRAM_TO_RAM) { + gart_s = svm_migrate_direct_mapping_addr(adev, *vram); + r = svm_migrate_gart_map(ring, size, sys, &gart_d, 0); + + } else if (direction == FROM_RAM_TO_VRAM) { + r = svm_migrate_gart_map(ring, size, sys, &gart_s, + KFD_IOCTL_SVM_FLAG_GPU_RO); + gart_d = svm_migrate_direct_mapping_addr(adev, *vram); + } + if (r) { + pr_debug("failed %d to create gart mapping\n", r); + goto out_unlock; + } + + r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE, + NULL, &next, false, true, false); + if (r) { + pr_debug("failed %d to copy memory\n", r); + goto out_unlock; + } + + dma_fence_put(*mfence); + *mfence = next; + npages -= size; + if (npages) { + sys += size; + vram += size; + } + } + +out_unlock: + mutex_unlock(&adev->mman.gtt_window_lock); + + return r; +} + +/** + * svm_migrate_copy_done - wait for memory copy sdma is done + * + * @adev: amdgpu device the sdma memory copy is executing on + * @mfence: migrate fence + * + * Wait for dma fence is signaled, if the copy ssplit into multiple sdma + * operations, this is the last sdma operation fence. + * + * Context: called after svm_migrate_copy_memory + * + * Return: + * 0 - success + * otherwise - error code from dma fence signal + */ +static int +svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence) +{ + int r = 0; + + if (mfence) { + r = dma_fence_wait(mfence, false); + dma_fence_put(mfence); + pr_debug("sdma copy memory fence done\n"); + } + + return r; +} + +unsigned long +svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) +{ + return (addr + adev->kfd.dev->pgmap.range.start) >> PAGE_SHIFT; +} + +static void +svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) +{ + struct page *page; + + page = pfn_to_page(pfn); + page->zone_device_data = prange; + get_page(page); + lock_page(page); +} + +static void +svm_migrate_put_vram_page(struct amdgpu_device *adev, unsigned long addr) +{ + struct page *page; + + page = pfn_to_page(svm_migrate_addr_to_pfn(adev, addr)); + unlock_page(page); + put_page(page); +} + +static unsigned long +svm_migrate_addr(struct amdgpu_device *adev, struct page *page) +{ + unsigned long addr; + + addr = page_to_pfn(page) << PAGE_SHIFT; + return (addr - adev->kfd.dev->pgmap.range.start); +} + +static struct page * +svm_migrate_get_sys_page(struct vm_area_struct *vma, unsigned long addr) +{ + struct page *page; + + page = alloc_page_vma(GFP_HIGHUSER, vma, addr); + if (page) + lock_page(page); + + return page; +} + +static void svm_migrate_put_sys_page(unsigned long addr) +{ + struct page *page; + + page = pfn_to_page(addr >> PAGE_SHIFT); + unlock_page(page); + put_page(page); +} + +static int +svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange, + struct migrate_vma *migrate, struct dma_fence **mfence, + dma_addr_t *scratch) +{ + uint64_t npages = migrate->cpages; + struct device *dev = adev->dev; + struct amdgpu_res_cursor cursor; + dma_addr_t *src; + uint64_t *dst; + uint64_t i, j; + int r; + + pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, + prange->last); + + src = scratch; + dst = (uint64_t *)(scratch + npages); + + r = svm_range_vram_node_new(adev, prange, true); + if (r) { + pr_debug("failed %d get 0x%llx pages from vram\n", r, npages); + goto out; + } + + amdgpu_res_first(prange->ttm_res, prange->offset << PAGE_SHIFT, + npages << PAGE_SHIFT, &cursor); + for (i = j = 0; i < npages; i++) { + struct page *spage; + + dst[i] = cursor.start + (j << PAGE_SHIFT); + migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); + svm_migrate_get_vram_page(prange, migrate->dst[i]); + + migrate->dst[i] = migrate_pfn(migrate->dst[i]); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; + + if (migrate->src[i] & MIGRATE_PFN_VALID) { + spage = migrate_pfn_to_page(migrate->src[i]); + src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE, + DMA_TO_DEVICE); + r = dma_mapping_error(dev, src[i]); + if (r) { + pr_debug("failed %d dma_map_page\n", r); + goto out_free_vram_pages; + } + } else { + if (j) { + r = svm_migrate_copy_memory_gart( + adev, src + i - j, + dst + i - j, j, + FROM_RAM_TO_VRAM, + mfence); + if (r) + goto out_free_vram_pages; + amdgpu_res_next(&cursor, j << PAGE_SHIFT); + j = 0; + } else { + amdgpu_res_next(&cursor, PAGE_SIZE); + } + continue; + } + + pr_debug("dma mapping src to 0x%llx, page_to_pfn 0x%lx\n", + src[i] >> PAGE_SHIFT, page_to_pfn(spage)); + + if (j >= (cursor.size >> PAGE_SHIFT) - 1 && i < npages - 1) { + r = svm_migrate_copy_memory_gart(adev, src + i - j, + dst + i - j, j + 1, + FROM_RAM_TO_VRAM, + mfence); + if (r) + goto out_free_vram_pages; + amdgpu_res_next(&cursor, (j + 1) * PAGE_SIZE); + j= 0; + } else { + j++; + } + } + + r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j, + FROM_RAM_TO_VRAM, mfence); + +out_free_vram_pages: + if (r) { + pr_debug("failed %d to copy memory to vram\n", r); + while (i--) { + svm_migrate_put_vram_page(adev, dst[i]); + migrate->dst[i] = 0; + } + } + +out: + return r; +} + +static int +svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange, + struct vm_area_struct *vma, uint64_t start, + uint64_t end) +{ + uint64_t npages = (end - start) >> PAGE_SHIFT; + struct dma_fence *mfence = NULL; + struct migrate_vma migrate; + dma_addr_t *scratch; + size_t size; + void *buf; + int r = -ENOMEM; + int retry = 0; + + memset(&migrate, 0, sizeof(migrate)); + migrate.vma = vma; + migrate.start = start; + migrate.end = end; + migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; + migrate.pgmap_owner = adev; + + size = 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t); + size *= npages; + buf = kvmalloc(size, GFP_KERNEL | __GFP_ZERO); + if (!buf) + goto out; + + migrate.src = buf; + migrate.dst = migrate.src + npages; + scratch = (dma_addr_t *)(migrate.dst + npages); + +retry: + r = migrate_vma_setup(&migrate); + if (r) { + pr_debug("failed %d prepare migrate svms 0x%p [0x%lx 0x%lx]\n", + r, prange->svms, prange->start, prange->last); + goto out_free; + } + if (migrate.cpages != npages) { + pr_debug("collect 0x%lx/0x%llx pages, retry\n", migrate.cpages, + npages); + migrate_vma_finalize(&migrate); + if (retry++ >= 3) { + r = -ENOMEM; + pr_debug("failed %d migrate svms 0x%p [0x%lx 0x%lx]\n", + r, prange->svms, prange->start, prange->last); + goto out_free; + } + + goto retry; + } + + if (migrate.cpages) { + r = svm_migrate_copy_to_vram(adev, prange, &migrate, &mfence, + scratch); + migrate_vma_pages(&migrate); + svm_migrate_copy_done(adev, mfence); + migrate_vma_finalize(&migrate); + } + + svm_range_dma_unmap(adev->dev, scratch, 0, npages); + svm_range_free_dma_mappings(prange); + +out_free: + kvfree(buf); +out: + return r; +} + +/** + * svm_migrate_ram_to_vram - migrate svm range from system to device + * @prange: range structure + * @best_loc: the device to migrate to + * @mm: the process mm structure + * + * Context: Process context, caller hold mmap read lock, svms lock, prange lock + * + * Return: + * 0 - OK, otherwise error code + */ +static int +svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, + struct mm_struct *mm) +{ + unsigned long addr, start, end; + struct vm_area_struct *vma; + struct amdgpu_device *adev; + int r = 0; + + if (prange->actual_loc == best_loc) { + pr_debug("svms 0x%p [0x%lx 0x%lx] already on best_loc 0x%x\n", + prange->svms, prange->start, prange->last, best_loc); + return 0; + } + + adev = svm_range_get_adev_by_id(prange, best_loc); + if (!adev) { + pr_debug("failed to get device by id 0x%x\n", best_loc); + return -ENODEV; + } + + pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange->svms, + prange->start, prange->last, best_loc); + + /* FIXME: workaround for page locking bug with invalid pages */ + svm_range_prefault(prange, mm); + + start = prange->start << PAGE_SHIFT; + end = (prange->last + 1) << PAGE_SHIFT; + + for (addr = start; addr < end;) { + unsigned long next; + + vma = find_vma(mm, addr); + if (!vma || addr < vma->vm_start) + break; + + next = min(vma->vm_end, end); + r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next); + if (r) { + pr_debug("failed to migrate\n"); + break; + } + addr = next; + } + + if (!r) + prange->actual_loc = best_loc; + + return r; +} + +static void svm_migrate_page_free(struct page *page) +{ + /* Keep this function to avoid warning */ +} + +static int +svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, + struct migrate_vma *migrate, struct dma_fence **mfence, + dma_addr_t *scratch) +{ + uint64_t npages = migrate->cpages; + struct device *dev = adev->dev; + uint64_t *src; + dma_addr_t *dst; + struct page *dpage; + uint64_t i = 0, j; + uint64_t addr; + int r = 0; + + pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, + prange->last); + + addr = prange->start << PAGE_SHIFT; + + src = (uint64_t *)(scratch + npages); + dst = scratch; + + for (i = 0, j = 0; i < npages; i++, j++, addr += PAGE_SIZE) { + struct page *spage; + + spage = migrate_pfn_to_page(migrate->src[i]); + if (!spage) { + pr_debug("failed get spage svms 0x%p [0x%lx 0x%lx]\n", + prange->svms, prange->start, prange->last); + r = -ENOMEM; + goto out_oom; + } + src[i] = svm_migrate_addr(adev, spage); + if (i > 0 && src[i] != src[i - 1] + PAGE_SIZE) { + r = svm_migrate_copy_memory_gart(adev, dst + i - j, + src + i - j, j, + FROM_VRAM_TO_RAM, + mfence); + if (r) + goto out_oom; + j = 0; + } + + dpage = svm_migrate_get_sys_page(migrate->vma, addr); + if (!dpage) { + pr_debug("failed get page svms 0x%p [0x%lx 0x%lx]\n", + prange->svms, prange->start, prange->last); + r = -ENOMEM; + goto out_oom; + } + + dst[i] = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_FROM_DEVICE); + r = dma_mapping_error(dev, dst[i]); + if (r) { + pr_debug("failed %d dma_map_page\n", r); + goto out_oom; + } + + pr_debug("dma mapping dst to 0x%llx, page_to_pfn 0x%lx\n", + dst[i] >> PAGE_SHIFT, page_to_pfn(dpage)); + + migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; + } + + r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, + FROM_VRAM_TO_RAM, mfence); + +out_oom: + if (r) { + pr_debug("failed %d copy to ram\n", r); + while (i--) { + svm_migrate_put_sys_page(dst[i]); + migrate->dst[i] = 0; + } + } + + return r; +} + +static int +svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange, + struct vm_area_struct *vma, uint64_t start, uint64_t end) +{ + uint64_t npages = (end - start) >> PAGE_SHIFT; + struct dma_fence *mfence = NULL; + struct migrate_vma migrate; + dma_addr_t *scratch; + size_t size; + void *buf; + int r = -ENOMEM; + + memset(&migrate, 0, sizeof(migrate)); + migrate.vma = vma; + migrate.start = start; + migrate.end = end; + migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + migrate.pgmap_owner = adev; + + size = 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t); + size *= npages; + buf = kvmalloc(size, GFP_KERNEL | __GFP_ZERO); + if (!buf) + goto out; + + migrate.src = buf; + migrate.dst = migrate.src + npages; + scratch = (dma_addr_t *)(migrate.dst + npages); + + r = migrate_vma_setup(&migrate); + if (r) { + pr_debug("failed %d prepare migrate svms 0x%p [0x%lx 0x%lx]\n", + r, prange->svms, prange->start, prange->last); + goto out_free; + } + + pr_debug("cpages %ld\n", migrate.cpages); + + if (migrate.cpages) { + r = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence, + scratch); + migrate_vma_pages(&migrate); + svm_migrate_copy_done(adev, mfence); + migrate_vma_finalize(&migrate); + } else { + pr_debug("failed collect migrate device pages [0x%lx 0x%lx]\n", + prange->start, prange->last); + } + + svm_range_dma_unmap(adev->dev, scratch, 0, npages); + +out_free: + kvfree(buf); +out: + return r; +} + +/** + * svm_migrate_vram_to_ram - migrate svm range from device to system + * @prange: range structure + * @mm: process mm, use current->mm if NULL + * + * Context: Process context, caller hold mmap read lock, svms lock, prange lock + * + * Return: + * 0 - OK, otherwise error code + */ +int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm) +{ + struct amdgpu_device *adev; + struct vm_area_struct *vma; + unsigned long addr; + unsigned long start; + unsigned long end; + int r = 0; + + if (!prange->actual_loc) { + pr_debug("[0x%lx 0x%lx] already migrated to ram\n", + prange->start, prange->last); + return 0; + } + + adev = svm_range_get_adev_by_id(prange, prange->actual_loc); + if (!adev) { + pr_debug("failed to get device by id 0x%x\n", + prange->actual_loc); + return -ENODEV; + } + + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] from gpu 0x%x to ram\n", + prange->svms, prange, prange->start, prange->last, + prange->actual_loc); + + start = prange->start << PAGE_SHIFT; + end = (prange->last + 1) << PAGE_SHIFT; + + for (addr = start; addr < end;) { + unsigned long next; + + vma = find_vma(mm, addr); + if (!vma || addr < vma->vm_start) + break; + + next = min(vma->vm_end, end); + r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next); + if (r) { + pr_debug("failed %d to migrate\n", r); + break; + } + addr = next; + } + + if (!r) { + svm_range_vram_node_free(prange); + prange->actual_loc = 0; + } + return r; +} + +/** + * svm_migrate_vram_to_vram - migrate svm range from device to device + * @prange: range structure + * @best_loc: the device to migrate to + * @mm: process mm, use current->mm if NULL + * + * Context: Process context, caller hold mmap read lock, svms lock, prange lock + * + * Return: + * 0 - OK, otherwise error code + */ +static int +svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc, + struct mm_struct *mm) +{ + int r; + + /* + * TODO: for both devices with PCIe large bar or on same xgmi hive, skip + * system memory as migration bridge + */ + + pr_debug("from gpu 0x%x to gpu 0x%x\n", prange->actual_loc, best_loc); + + r = svm_migrate_vram_to_ram(prange, mm); + if (r) + return r; + + return svm_migrate_ram_to_vram(prange, best_loc, mm); +} + +int +svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, + struct mm_struct *mm) +{ + if (!prange->actual_loc) + return svm_migrate_ram_to_vram(prange, best_loc, mm); + else + return svm_migrate_vram_to_vram(prange, best_loc, mm); + +} + +/** + * svm_migrate_to_ram - CPU page fault handler + * @vmf: CPU vm fault vma, address + * + * Context: vm fault handler, caller holds the mmap read lock + * + * Return: + * 0 - OK + * VM_FAULT_SIGBUS - notice application to have SIGBUS page fault + */ +static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) +{ + unsigned long addr = vmf->address; + struct vm_area_struct *vma; + enum svm_work_list_ops op; + struct svm_range *parent; + struct svm_range *prange; + struct kfd_process *p; + struct mm_struct *mm; + int r = 0; + + vma = vmf->vma; + mm = vma->vm_mm; + + p = kfd_lookup_process_by_mm(vma->vm_mm); + if (!p) { + pr_debug("failed find process at fault address 0x%lx\n", addr); + return VM_FAULT_SIGBUS; + } + addr >>= PAGE_SHIFT; + pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr); + + mutex_lock(&p->svms.lock); + + prange = svm_range_from_addr(&p->svms, addr, &parent); + if (!prange) { + pr_debug("cannot find svm range at 0x%lx\n", addr); + r = -EFAULT; + goto out; + } + + mutex_lock(&parent->migrate_mutex); + if (prange != parent) + mutex_lock_nested(&prange->migrate_mutex, 1); + + if (!prange->actual_loc) + goto out_unlock_prange; + + svm_range_lock(parent); + if (prange != parent) + mutex_lock_nested(&prange->lock, 1); + r = svm_range_split_by_granularity(p, mm, addr, parent, prange); + if (prange != parent) + mutex_unlock(&prange->lock); + svm_range_unlock(parent); + if (r) { + pr_debug("failed %d to split range by granularity\n", r); + goto out_unlock_prange; + } + + r = svm_migrate_vram_to_ram(prange, mm); + if (r) + pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r, + prange, prange->start, prange->last); + + /* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */ + if (p->xnack_enabled && parent == prange) + op = SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP; + else + op = SVM_OP_UPDATE_RANGE_NOTIFIER; + svm_range_add_list_work(&p->svms, parent, mm, op); + schedule_deferred_list_work(&p->svms); + +out_unlock_prange: + if (prange != parent) + mutex_unlock(&prange->migrate_mutex); + mutex_unlock(&parent->migrate_mutex); +out: + mutex_unlock(&p->svms.lock); + kfd_unref_process(p); + + pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr); + + return r ? VM_FAULT_SIGBUS : 0; +} + +static const struct dev_pagemap_ops svm_migrate_pgmap_ops = { + .page_free = svm_migrate_page_free, + .migrate_to_ram = svm_migrate_to_ram, +}; + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +int svm_migrate_init(struct amdgpu_device *adev) +{ + struct kfd_dev *kfddev = adev->kfd.dev; + struct dev_pagemap *pgmap; + struct resource *res; + unsigned long size; + void *r; + + /* Page migration works on Vega10 or newer */ + if (kfddev->device_info->asic_family < CHIP_VEGA10) + return -EINVAL; + + pgmap = &kfddev->pgmap; + memset(pgmap, 0, sizeof(*pgmap)); + + /* TODO: register all vram to HMM for now. + * should remove reserved size + */ + size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); + res = devm_request_free_mem_region(adev->dev, &iomem_resource, size); + if (IS_ERR(res)) + return -ENOMEM; + + pgmap->type = MEMORY_DEVICE_PRIVATE; + pgmap->nr_range = 1; + pgmap->range.start = res->start; + pgmap->range.end = res->end; + pgmap->ops = &svm_migrate_pgmap_ops; + pgmap->owner = adev; + pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + r = devm_memremap_pages(adev->dev, pgmap); + if (IS_ERR(r)) { + pr_err("failed to register HMM device memory\n"); + devm_release_mem_region(adev->dev, res->start, + res->end - res->start + 1); + return PTR_ERR(r); + } + + pr_debug("reserve %ldMB system memory for VRAM pages struct\n", + SVM_HMM_PAGE_STRUCT_SIZE(size) >> 20); + + amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size)); + + pr_info("HMM registered %ldMB device memory\n", size >> 20); + + return 0; +} + +void svm_migrate_fini(struct amdgpu_device *adev) +{ + struct dev_pagemap *pgmap = &adev->kfd.dev->pgmap; + + devm_memunmap_pages(adev->dev, pgmap); + devm_release_mem_region(adev->dev, pgmap->range.start, + pgmap->range.end - pgmap->range.start + 1); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h new file mode 100644 index 000000000000..0de76b5d4973 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2020-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_MIGRATE_H_ +#define KFD_MIGRATE_H_ + +#if IS_ENABLED(CONFIG_HSA_AMD_SVM) + +#include +#include +#include +#include +#include +#include "kfd_priv.h" +#include "kfd_svm.h" + +enum MIGRATION_COPY_DIR { + FROM_RAM_TO_VRAM = 0, + FROM_VRAM_TO_RAM +}; + +int svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, + struct mm_struct *mm); +int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm); +unsigned long +svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr); + +int svm_migrate_init(struct amdgpu_device *adev); +void svm_migrate_fini(struct amdgpu_device *adev); + +#else + +static inline int svm_migrate_init(struct amdgpu_device *adev) +{ + return 0; +} +static inline void svm_migrate_fini(struct amdgpu_device *adev) +{ + /* empty */ +} + +#endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */ + +#endif /* KFD_MIGRATE_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index e840dd581719..d8e940f03102 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -124,14 +124,14 @@ static int pm_create_runlist_ib(struct packet_manager *pm, { unsigned int alloc_size_bytes; unsigned int *rl_buffer, rl_wptr, i; - int retval, proccesses_mapped; + int retval, processes_mapped; struct device_process_node *cur; struct qcm_process_device *qpd; struct queue *q; struct kernel_queue *kq; bool is_over_subscription; - rl_wptr = retval = proccesses_mapped = 0; + rl_wptr = retval = processes_mapped = 0; retval = pm_allocate_runlist_ib(pm, &rl_buffer, rl_gpu_addr, &alloc_size_bytes, &is_over_subscription); @@ -148,7 +148,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm, list_for_each_entry(cur, queues, list) { qpd = cur->qpd; /* build map process packet */ - if (proccesses_mapped >= pm->dqm->processes_count) { + if (processes_mapped >= pm->dqm->processes_count) { pr_debug("Not enough space left in runlist IB\n"); pm_release_ib(pm); return -ENOMEM; @@ -158,7 +158,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm, if (retval) return retval; - proccesses_mapped++; + processes_mapped++; inc_wptr(&rl_wptr, pm->pmf->map_process_size, alloc_size_bytes); @@ -242,7 +242,6 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) case CHIP_RAVEN: case CHIP_RENOIR: case CHIP_ARCTURUS: - case CHIP_ALDEBARAN: case CHIP_NAVI10: case CHIP_NAVI12: case CHIP_NAVI14: @@ -250,8 +249,13 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: pm->pmf = &kfd_v9_pm_funcs; break; + case CHIP_ALDEBARAN: + pm->pmf = &kfd_aldebaran_pm_funcs; + break; default: WARN(1, "Unexpected ASIC family %u", dqm->dev->device_info->asic_family); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c index e3ba0cd3b6fa..7ea3f671b325 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c @@ -24,6 +24,7 @@ #include "kfd_kernel_queue.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_ai.h" +#include "kfd_pm4_headers_aldebaran.h" #include "kfd_pm4_opcodes.h" #include "gc/gc_10_1_0_sh_mask.h" @@ -35,7 +36,6 @@ static int pm_map_process_v9(struct packet_manager *pm, packet = (struct pm4_mes_map_process *)buffer; memset(buffer, 0, sizeof(struct pm4_mes_map_process)); - packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, sizeof(struct pm4_mes_map_process)); packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; @@ -73,6 +73,45 @@ static int pm_map_process_v9(struct packet_manager *pm, return 0; } +static int pm_map_process_aldebaran(struct packet_manager *pm, + uint32_t *buffer, struct qcm_process_device *qpd) +{ + struct pm4_mes_map_process_aldebaran *packet; + uint64_t vm_page_table_base_addr = qpd->page_table_base; + + packet = (struct pm4_mes_map_process_aldebaran *)buffer; + memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran)); + packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, + sizeof(struct pm4_mes_map_process_aldebaran)); + packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; + packet->bitfields2.process_quantum = 10; + packet->bitfields2.pasid = qpd->pqm->process->pasid; + packet->bitfields14.gds_size = qpd->gds_size & 0x3F; + packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF; + packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0; + packet->bitfields14.num_oac = qpd->num_oac; + packet->bitfields14.sdma_enable = 1; + packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count; + + packet->sh_mem_config = qpd->sh_mem_config; + packet->sh_mem_bases = qpd->sh_mem_bases; + if (qpd->tba_addr) { + packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); + packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); + packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); + } + + packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); + packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); + + packet->vm_context_page_table_base_addr_lo32 = + lower_32_bits(vm_page_table_base_addr); + packet->vm_context_page_table_base_addr_hi32 = + upper_32_bits(vm_page_table_base_addr); + + return 0; +} + static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer, uint64_t ib, size_t ib_size_in_dwords, bool chain) { @@ -324,3 +363,20 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = { .query_status_size = sizeof(struct pm4_mes_query_status), .release_mem_size = 0, }; + +const struct packet_manager_funcs kfd_aldebaran_pm_funcs = { + .map_process = pm_map_process_aldebaran, + .runlist = pm_runlist_v9, + .set_resources = pm_set_resources_v9, + .map_queues = pm_map_queues_v9, + .unmap_queues = pm_unmap_queues_v9, + .query_status = pm_query_status_v9, + .release_mem = NULL, + .map_process_size = sizeof(struct pm4_mes_map_process_aldebaran), + .runlist_size = sizeof(struct pm4_mes_runlist), + .set_resources_size = sizeof(struct pm4_mes_set_resources), + .map_queues_size = sizeof(struct pm4_mes_map_queues), + .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), + .query_status_size = sizeof(struct pm4_mes_query_status), + .release_mem_size = 0, +}; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h new file mode 100644 index 000000000000..f795ec815e2a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h @@ -0,0 +1,93 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/ + +#ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED +#define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED + +struct pm4_mes_map_process_aldebaran { + union { + union PM4_MES_TYPE_3_HEADER header; /* header */ + uint32_t ordinal1; + }; + + union { + struct { + uint32_t pasid:16; /* 0 - 15 */ + uint32_t single_memops:1; /* 16 */ + uint32_t reserved1:1; /* 17 */ + uint32_t debug_vmid:4; /* 18 - 21 */ + uint32_t new_debug:1; /* 22 */ + uint32_t tmz:1; /* 23 */ + uint32_t diq_enable:1; /* 24 */ + uint32_t process_quantum:7; /* 25 - 31 */ + } bitfields2; + uint32_t ordinal2; + }; + + uint32_t vm_context_page_table_base_addr_lo32; + + uint32_t vm_context_page_table_base_addr_hi32; + + uint32_t sh_mem_bases; + + uint32_t sh_mem_config; + + uint32_t sq_shader_tba_lo; + + uint32_t sq_shader_tba_hi; + + uint32_t sq_shader_tma_lo; + + uint32_t sq_shader_tma_hi; + + uint32_t reserved6; + + uint32_t gds_addr_lo; + + uint32_t gds_addr_hi; + + union { + struct { + uint32_t num_gws:7; + uint32_t sdma_enable:1; + uint32_t num_oac:4; + uint32_t gds_size_hi:4; + uint32_t gds_size:6; + uint32_t num_queues:10; + } bitfields14; + uint32_t ordinal14; + }; + + uint32_t spi_gdbg_per_vmid_cntl; + + uint32_t tcp_watch_cntl[4]; + + uint32_t completion_signal_lo; + + uint32_t completion_signal_hi; + +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 0b6595f7acda..6dc22fa1e555 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -322,6 +322,9 @@ struct kfd_dev { unsigned int max_doorbell_slices; int noretry; + + /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */ + struct dev_pagemap pgmap; }; enum kfd_mempool { @@ -669,7 +672,7 @@ struct kfd_process_device { /* VM context for GPUVM allocations */ struct file *drm_file; - void *vm; + void *drm_priv; /* GPUVM allocations storage */ struct idr alloc_idr; @@ -731,6 +734,18 @@ struct kfd_process_device { #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) +struct svm_range_list { + struct mutex lock; + struct rb_root_cached objects; + struct list_head list; + struct work_struct deferred_list_work; + struct list_head deferred_range_list; + spinlock_t deferred_list_lock; + atomic_t evicted_ranges; + struct delayed_work restore_work; + DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); +}; + /* Process data */ struct kfd_process { /* @@ -809,6 +824,11 @@ struct kfd_process { struct kobject *kobj; struct kobject *kobj_queues; struct attribute attr_pasid; + + /* shared virtual memory registered by this process */ + struct svm_range_list svms; + + bool xnack_enabled; }; #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ @@ -842,6 +862,20 @@ struct kfd_process *kfd_create_process(struct file *filep); struct kfd_process *kfd_get_process(const struct task_struct *); struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid); struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); + +int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); +int kfd_process_gpuid_from_kgd(struct kfd_process *p, + struct amdgpu_device *adev, uint32_t *gpuid, + uint32_t *gpuidx); +static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, + uint32_t gpuidx, uint32_t *gpuid) { + return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; +} +static inline struct kfd_process_device *kfd_process_device_from_gpuidx( + struct kfd_process *p, uint32_t gpuidx) { + return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; +} + void kfd_unref_process(struct kfd_process *p); int kfd_process_evict_queues(struct kfd_process *p); int kfd_process_restore_queues(struct kfd_process *p); @@ -857,6 +891,8 @@ struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev, struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, struct kfd_process *p); +bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); + int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process, struct vm_area_struct *vma); @@ -1052,6 +1088,7 @@ struct packet_manager_funcs { extern const struct packet_manager_funcs kfd_vi_pm_funcs; extern const struct packet_manager_funcs kfd_v9_pm_funcs; +extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); void pm_uninit(struct packet_manager *pm, bool hanging); @@ -1107,7 +1144,9 @@ void kfd_signal_vm_fault_event(struct kfd_dev *dev, u32 pasid, void kfd_signal_reset_event(struct kfd_dev *dev); -void kfd_flush_tlb(struct kfd_process_device *pdd); +void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid); + +void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type); int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index d97e330a5022..09b98a83f670 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -42,6 +42,7 @@ struct mm_struct; #include "kfd_device_queue_manager.h" #include "kfd_dbgmgr.h" #include "kfd_iommu.h" +#include "kfd_svm.h" /* * List of struct kfd_process (field kfd_process). @@ -108,8 +109,6 @@ static void kfd_sdma_activity_worker(struct work_struct *work) workarea = container_of(work, struct kfd_sdma_activity_handler_workarea, sdma_activity_work); - if (!workarea) - return; pdd = workarea->pdd; if (!pdd) @@ -250,7 +249,7 @@ cleanup: } /** - * @kfd_get_cu_occupancy() - Collect number of waves in-flight on this device + * @kfd_get_cu_occupancy - Collect number of waves in-flight on this device * by current process. Translates acquired wave count into number of compute units * that are occupied. * @@ -647,8 +646,9 @@ static void kfd_process_free_gpuvm(struct kgd_mem *mem, { struct kfd_dev *dev = pdd->dev; - amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(dev->kgd, mem, pdd->vm); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, mem, NULL); + amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(dev->kgd, mem, pdd->drm_priv); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, mem, pdd->drm_priv, + NULL); } /* kfd_process_alloc_gpuvm - Allocate GPU VM for the KFD process @@ -667,11 +667,12 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, gpu_va, size, - pdd->vm, &mem, NULL, flags); + pdd->drm_priv, &mem, NULL, flags); if (err) goto err_alloc_mem; - err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, pdd->vm); + err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, + pdd->drm_priv, NULL); if (err) goto err_map_mem; @@ -712,7 +713,8 @@ sync_memory_failed: return err; err_map_mem: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, mem, pdd->drm_priv, + NULL); err_alloc_mem: *kptr = NULL; return err; @@ -901,13 +903,14 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; - if (!peer_pdd->vm) + if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->kgd, mem, peer_pdd->vm); + peer_pdd->dev->kgd, mem, peer_pdd->drm_priv); } - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->kgd, mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->kgd, mem, + pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } } @@ -932,7 +935,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) if (pdd->drm_file) { amdgpu_amdkfd_gpuvm_release_process_vm( - pdd->dev->kgd, pdd->vm); + pdd->dev->kgd, pdd->drm_priv); fput(pdd->drm_file); } @@ -1000,6 +1003,7 @@ static void kfd_process_wq_release(struct work_struct *work) kfd_iommu_unbind_process(p); kfd_process_free_outstanding_kfd_bos(p); + svm_range_list_fini(p); kfd_process_destroy_pdds(p); dma_fence_put(p->ef); @@ -1058,6 +1062,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); + cancel_delayed_work_sync(&p->svms.restore_work); mutex_lock(&p->mutex); @@ -1186,6 +1191,56 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, } } +bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) +{ + int i; + + /* On most GFXv9 GPUs, the retry mode in the SQ must match the + * boot time retry setting. Mixing processes with different + * XNACK/retry settings can hang the GPU. + * + * Different GPUs can have different noretry settings depending + * on HW bugs or limitations. We need to find at least one + * XNACK mode for this process that's compatible with all GPUs. + * Fortunately GPUs with retry enabled (noretry=0) can run code + * built for XNACK-off. On GFXv9 it may perform slower. + * + * Therefore applications built for XNACK-off can always be + * supported and will be our fallback if any GPU does not + * support retry. + */ + for (i = 0; i < p->n_pdds; i++) { + struct kfd_dev *dev = p->pdds[i]->dev; + + /* Only consider GFXv9 and higher GPUs. Older GPUs don't + * support the SVM APIs and don't need to be considered + * for the XNACK mode selection. + */ + if (dev->device_info->asic_family < CHIP_VEGA10) + continue; + /* Aldebaran can always support XNACK because it can support + * per-process XNACK mode selection. But let the dev->noretry + * setting still influence the default XNACK mode. + */ + if (supported && + dev->device_info->asic_family == CHIP_ALDEBARAN) + continue; + + /* GFXv10 and later GPUs do not support shader preemption + * during page faults. This can lead to poor QoS for queue + * management and memory-manager-related preemptions or + * even deadlocks. + */ + if (dev->device_info->asic_family >= CHIP_NAVI10) + return false; + + if (dev->noretry) + return false; + } + + return true; +} + /* * On return the kfd_process is fully operational and will be freed when the * mm is released @@ -1224,6 +1279,13 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (err != 0) goto err_init_apertures; + /* Check XNACK support after PDDs are created in kfd_init_apertures */ + process->xnack_enabled = kfd_process_xnack_mode(process, false); + + err = svm_range_list_init(process); + if (err) + goto err_init_svm_range_list; + /* alloc_notifier needs to find the process in the hash table */ hash_add_rcu(kfd_processes_table, &process->kfd_processes, (uintptr_t)process->mm); @@ -1246,6 +1308,8 @@ static struct kfd_process *create_process(const struct task_struct *thread) err_register_notifier: hash_del_rcu(&process->kfd_processes); + svm_range_list_fini(process); +err_init_svm_range_list: kfd_process_free_outstanding_kfd_bos(process); kfd_process_destroy_pdds(process); err_init_apertures: @@ -1375,7 +1439,7 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, if (!drm_file) return -EINVAL; - if (pdd->vm) + if (pdd->drm_priv) return -EBUSY; p = pdd->process; @@ -1383,13 +1447,12 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, ret = amdgpu_amdkfd_gpuvm_acquire_process_vm( dev->kgd, drm_file, p->pasid, - &pdd->vm, &p->kgd_process_info, &p->ef); + &p->kgd_process_info, &p->ef); if (ret) { pr_err("Failed to create process VM object\n"); return ret; } - - amdgpu_vm_set_task_info(pdd->vm); + pdd->drm_priv = drm_file->private_data; ret = kfd_process_device_reserve_ib_mem(pdd); if (ret) @@ -1405,7 +1468,7 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, err_init_cwsr: err_reserve_ib_mem: kfd_process_device_free_bos(pdd); - pdd->vm = NULL; + pdd->drm_priv = NULL; return ret; } @@ -1429,7 +1492,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev, return ERR_PTR(-ENOMEM); } - if (!pdd->vm) + if (!pdd->drm_priv) return ERR_PTR(-ENODEV); /* @@ -1600,6 +1663,32 @@ int kfd_process_restore_queues(struct kfd_process *p) return ret; } +int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id) +{ + int i; + + for (i = 0; i < p->n_pdds; i++) + if (p->pdds[i] && gpu_id == p->pdds[i]->dev->id) + return i; + return -EINVAL; +} + +int +kfd_process_gpuid_from_kgd(struct kfd_process *p, struct amdgpu_device *adev, + uint32_t *gpuid, uint32_t *gpuidx) +{ + struct kgd_dev *kgd = (struct kgd_dev *)adev; + int i; + + for (i = 0; i < p->n_pdds; i++) + if (p->pdds[i] && p->pdds[i]->dev->kgd == kgd) { + *gpuid = p->pdds[i]->dev->id; + *gpuidx = i; + return 0; + } + return -EINVAL; +} + static void evict_process_worker(struct work_struct *work) { int ret; @@ -1748,7 +1837,7 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process, KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); } -void kfd_flush_tlb(struct kfd_process_device *pdd) +void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) { struct kfd_dev *dev = pdd->dev; @@ -1761,7 +1850,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd) pdd->qpd.vmid); } else { amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd, - pdd->process->pasid); + pdd->process->pasid, type); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c new file mode 100644 index 000000000000..dff1011dd7ee --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -0,0 +1,3102 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2020-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "amdgpu_sync.h" +#include "amdgpu_object.h" +#include "amdgpu_vm.h" +#include "amdgpu_mn.h" +#include "amdgpu.h" +#include "amdgpu_xgmi.h" +#include "kfd_priv.h" +#include "kfd_svm.h" +#include "kfd_migrate.h" + +#define AMDGPU_SVM_RANGE_RESTORE_DELAY_MS 1 + +/* Long enough to ensure no retry fault comes after svm range is restored and + * page table is updated. + */ +#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING 2000 + +static void svm_range_evict_svm_bo_worker(struct work_struct *work); +static bool +svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni, + const struct mmu_notifier_range *range, + unsigned long cur_seq); + +static const struct mmu_interval_notifier_ops svm_range_mn_ops = { + .invalidate = svm_range_cpu_invalidate_pagetables, +}; + +/** + * svm_range_unlink - unlink svm_range from lists and interval tree + * @prange: svm range structure to be removed + * + * Remove the svm_range from the svms and svm_bo lists and the svms + * interval tree. + * + * Context: The caller must hold svms->lock + */ +static void svm_range_unlink(struct svm_range *prange) +{ + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, + prange, prange->start, prange->last); + + if (prange->svm_bo) { + spin_lock(&prange->svm_bo->list_lock); + list_del(&prange->svm_bo_list); + spin_unlock(&prange->svm_bo->list_lock); + } + + list_del(&prange->list); + if (prange->it_node.start != 0 && prange->it_node.last != 0) + interval_tree_remove(&prange->it_node, &prange->svms->objects); +} + +static void +svm_range_add_notifier_locked(struct mm_struct *mm, struct svm_range *prange) +{ + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, + prange, prange->start, prange->last); + + mmu_interval_notifier_insert_locked(&prange->notifier, mm, + prange->start << PAGE_SHIFT, + prange->npages << PAGE_SHIFT, + &svm_range_mn_ops); +} + +/** + * svm_range_add_to_svms - add svm range to svms + * @prange: svm range structure to be added + * + * Add the svm range to svms interval tree and link list + * + * Context: The caller must hold svms->lock + */ +static void svm_range_add_to_svms(struct svm_range *prange) +{ + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, + prange, prange->start, prange->last); + + list_add_tail(&prange->list, &prange->svms->list); + prange->it_node.start = prange->start; + prange->it_node.last = prange->last; + interval_tree_insert(&prange->it_node, &prange->svms->objects); +} + +static void svm_range_remove_notifier(struct svm_range *prange) +{ + pr_debug("remove notifier svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", + prange->svms, prange, + prange->notifier.interval_tree.start >> PAGE_SHIFT, + prange->notifier.interval_tree.last >> PAGE_SHIFT); + + if (prange->notifier.interval_tree.start != 0 && + prange->notifier.interval_tree.last != 0) + mmu_interval_notifier_remove(&prange->notifier); +} + +static int +svm_range_dma_map_dev(struct device *dev, dma_addr_t **dma_addr, + unsigned long *hmm_pfns, uint64_t npages) +{ + enum dma_data_direction dir = DMA_BIDIRECTIONAL; + dma_addr_t *addr = *dma_addr; + struct page *page; + int i, r; + + if (!addr) { + addr = kvmalloc_array(npages, sizeof(*addr), + GFP_KERNEL | __GFP_ZERO); + if (!addr) + return -ENOMEM; + *dma_addr = addr; + } + + for (i = 0; i < npages; i++) { + if (WARN_ONCE(addr[i] && !dma_mapping_error(dev, addr[i]), + "leaking dma mapping\n")) + dma_unmap_page(dev, addr[i], PAGE_SIZE, dir); + + page = hmm_pfn_to_page(hmm_pfns[i]); + addr[i] = dma_map_page(dev, page, 0, PAGE_SIZE, dir); + r = dma_mapping_error(dev, addr[i]); + if (r) { + pr_debug("failed %d dma_map_page\n", r); + return r; + } + pr_debug("dma mapping 0x%llx for page addr 0x%lx\n", + addr[i] >> PAGE_SHIFT, page_to_pfn(page)); + } + return 0; +} + +static int +svm_range_dma_map(struct svm_range *prange, unsigned long *bitmap, + unsigned long *hmm_pfns) +{ + struct kfd_process *p; + uint32_t gpuidx; + int r; + + p = container_of(prange->svms, struct kfd_process, svms); + + for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) { + struct kfd_process_device *pdd; + struct amdgpu_device *adev; + + pr_debug("mapping to gpu idx 0x%x\n", gpuidx); + pdd = kfd_process_device_from_gpuidx(p, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + return -EINVAL; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + + r = svm_range_dma_map_dev(adev->dev, &prange->dma_addr[gpuidx], + hmm_pfns, prange->npages); + if (r) + break; + } + + return r; +} + +void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr, + unsigned long offset, unsigned long npages) +{ + enum dma_data_direction dir = DMA_BIDIRECTIONAL; + int i; + + if (!dma_addr) + return; + + for (i = offset; i < offset + npages; i++) { + if (!dma_addr[i] || dma_mapping_error(dev, dma_addr[i])) + continue; + pr_debug("dma unmapping 0x%llx\n", dma_addr[i] >> PAGE_SHIFT); + dma_unmap_page(dev, dma_addr[i], PAGE_SIZE, dir); + dma_addr[i] = 0; + } +} + +void svm_range_free_dma_mappings(struct svm_range *prange) +{ + struct kfd_process_device *pdd; + dma_addr_t *dma_addr; + struct device *dev; + struct kfd_process *p; + uint32_t gpuidx; + + p = container_of(prange->svms, struct kfd_process, svms); + + for (gpuidx = 0; gpuidx < MAX_GPU_INSTANCE; gpuidx++) { + dma_addr = prange->dma_addr[gpuidx]; + if (!dma_addr) + continue; + + pdd = kfd_process_device_from_gpuidx(p, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + continue; + } + dev = &pdd->dev->pdev->dev; + svm_range_dma_unmap(dev, dma_addr, 0, prange->npages); + kvfree(dma_addr); + prange->dma_addr[gpuidx] = NULL; + } +} + +static void svm_range_free(struct svm_range *prange) +{ + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, prange, + prange->start, prange->last); + + svm_range_vram_node_free(prange); + svm_range_free_dma_mappings(prange); + mutex_destroy(&prange->lock); + mutex_destroy(&prange->migrate_mutex); + kfree(prange); +} + +static void +svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc, + uint8_t *granularity, uint32_t *flags) +{ + *location = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + *prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + *granularity = 9; + *flags = + KFD_IOCTL_SVM_FLAG_HOST_ACCESS | KFD_IOCTL_SVM_FLAG_COHERENT; +} + +static struct +svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start, + uint64_t last) +{ + uint64_t size = last - start + 1; + struct svm_range *prange; + struct kfd_process *p; + + prange = kzalloc(sizeof(*prange), GFP_KERNEL); + if (!prange) + return NULL; + prange->npages = size; + prange->svms = svms; + prange->start = start; + prange->last = last; + INIT_LIST_HEAD(&prange->list); + INIT_LIST_HEAD(&prange->update_list); + INIT_LIST_HEAD(&prange->remove_list); + INIT_LIST_HEAD(&prange->insert_list); + INIT_LIST_HEAD(&prange->svm_bo_list); + INIT_LIST_HEAD(&prange->deferred_list); + INIT_LIST_HEAD(&prange->child_list); + atomic_set(&prange->invalid, 0); + prange->validate_timestamp = 0; + mutex_init(&prange->migrate_mutex); + mutex_init(&prange->lock); + + p = container_of(svms, struct kfd_process, svms); + if (p->xnack_enabled) + bitmap_copy(prange->bitmap_access, svms->bitmap_supported, + MAX_GPU_INSTANCE); + + svm_range_set_default_attributes(&prange->preferred_loc, + &prange->prefetch_loc, + &prange->granularity, &prange->flags); + + pr_debug("svms 0x%p [0x%llx 0x%llx]\n", svms, start, last); + + return prange; +} + +static bool svm_bo_ref_unless_zero(struct svm_range_bo *svm_bo) +{ + if (!svm_bo || !kref_get_unless_zero(&svm_bo->kref)) + return false; + + return true; +} + +static struct svm_range_bo *svm_range_bo_ref(struct svm_range_bo *svm_bo) +{ + if (svm_bo) + kref_get(&svm_bo->kref); + + return svm_bo; +} + +static void svm_range_bo_release(struct kref *kref) +{ + struct svm_range_bo *svm_bo; + + svm_bo = container_of(kref, struct svm_range_bo, kref); + spin_lock(&svm_bo->list_lock); + while (!list_empty(&svm_bo->range_list)) { + struct svm_range *prange = + list_first_entry(&svm_bo->range_list, + struct svm_range, svm_bo_list); + /* list_del_init tells a concurrent svm_range_vram_node_new when + * it's safe to reuse the svm_bo pointer and svm_bo_list head. + */ + list_del_init(&prange->svm_bo_list); + spin_unlock(&svm_bo->list_lock); + + pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, + prange->start, prange->last); + mutex_lock(&prange->lock); + prange->svm_bo = NULL; + mutex_unlock(&prange->lock); + + spin_lock(&svm_bo->list_lock); + } + spin_unlock(&svm_bo->list_lock); + if (!dma_fence_is_signaled(&svm_bo->eviction_fence->base)) { + /* We're not in the eviction worker. + * Signal the fence and synchronize with any + * pending eviction work. + */ + dma_fence_signal(&svm_bo->eviction_fence->base); + cancel_work_sync(&svm_bo->eviction_work); + } + dma_fence_put(&svm_bo->eviction_fence->base); + amdgpu_bo_unref(&svm_bo->bo); + kfree(svm_bo); +} + +static void svm_range_bo_unref(struct svm_range_bo *svm_bo) +{ + if (!svm_bo) + return; + + kref_put(&svm_bo->kref, svm_range_bo_release); +} + +static bool +svm_range_validate_svm_bo(struct amdgpu_device *adev, struct svm_range *prange) +{ + struct amdgpu_device *bo_adev; + + mutex_lock(&prange->lock); + if (!prange->svm_bo) { + mutex_unlock(&prange->lock); + return false; + } + if (prange->ttm_res) { + /* We still have a reference, all is well */ + mutex_unlock(&prange->lock); + return true; + } + if (svm_bo_ref_unless_zero(prange->svm_bo)) { + /* + * Migrate from GPU to GPU, remove range from source bo_adev + * svm_bo range list, and return false to allocate svm_bo from + * destination adev. + */ + bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev); + if (bo_adev != adev) { + mutex_unlock(&prange->lock); + + spin_lock(&prange->svm_bo->list_lock); + list_del_init(&prange->svm_bo_list); + spin_unlock(&prange->svm_bo->list_lock); + + svm_range_bo_unref(prange->svm_bo); + return false; + } + if (READ_ONCE(prange->svm_bo->evicting)) { + struct dma_fence *f; + struct svm_range_bo *svm_bo; + /* The BO is getting evicted, + * we need to get a new one + */ + mutex_unlock(&prange->lock); + svm_bo = prange->svm_bo; + f = dma_fence_get(&svm_bo->eviction_fence->base); + svm_range_bo_unref(prange->svm_bo); + /* wait for the fence to avoid long spin-loop + * at list_empty_careful + */ + dma_fence_wait(f, false); + dma_fence_put(f); + } else { + /* The BO was still around and we got + * a new reference to it + */ + mutex_unlock(&prange->lock); + pr_debug("reuse old bo svms 0x%p [0x%lx 0x%lx]\n", + prange->svms, prange->start, prange->last); + + prange->ttm_res = prange->svm_bo->bo->tbo.resource; + return true; + } + + } else { + mutex_unlock(&prange->lock); + } + + /* We need a new svm_bo. Spin-loop to wait for concurrent + * svm_range_bo_release to finish removing this range from + * its range list. After this, it is safe to reuse the + * svm_bo pointer and svm_bo_list head. + */ + while (!list_empty_careful(&prange->svm_bo_list)) + ; + + return false; +} + +static struct svm_range_bo *svm_range_bo_new(void) +{ + struct svm_range_bo *svm_bo; + + svm_bo = kzalloc(sizeof(*svm_bo), GFP_KERNEL); + if (!svm_bo) + return NULL; + + kref_init(&svm_bo->kref); + INIT_LIST_HEAD(&svm_bo->range_list); + spin_lock_init(&svm_bo->list_lock); + + return svm_bo; +} + +int +svm_range_vram_node_new(struct amdgpu_device *adev, struct svm_range *prange, + bool clear) +{ + struct amdgpu_bo_param bp; + struct svm_range_bo *svm_bo; + struct amdgpu_bo_user *ubo; + struct amdgpu_bo *bo; + struct kfd_process *p; + struct mm_struct *mm; + int r; + + p = container_of(prange->svms, struct kfd_process, svms); + pr_debug("pasid: %x svms 0x%p [0x%lx 0x%lx]\n", p->pasid, prange->svms, + prange->start, prange->last); + + if (svm_range_validate_svm_bo(adev, prange)) + return 0; + + svm_bo = svm_range_bo_new(); + if (!svm_bo) { + pr_debug("failed to alloc svm bo\n"); + return -ENOMEM; + } + mm = get_task_mm(p->lead_thread); + if (!mm) { + pr_debug("failed to get mm\n"); + kfree(svm_bo); + return -ESRCH; + } + svm_bo->svms = prange->svms; + svm_bo->eviction_fence = + amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), + mm, + svm_bo); + mmput(mm); + INIT_WORK(&svm_bo->eviction_work, svm_range_evict_svm_bo_worker); + svm_bo->evicting = 0; + memset(&bp, 0, sizeof(bp)); + bp.size = prange->npages * PAGE_SIZE; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + bp.flags |= clear ? AMDGPU_GEM_CREATE_VRAM_CLEARED : 0; + bp.flags |= AMDGPU_AMDKFD_CREATE_SVM_BO; + bp.type = ttm_bo_type_device; + bp.resv = NULL; + + r = amdgpu_bo_create_user(adev, &bp, &ubo); + if (r) { + pr_debug("failed %d to create bo\n", r); + goto create_bo_failed; + } + bo = &ubo->bo; + r = amdgpu_bo_reserve(bo, true); + if (r) { + pr_debug("failed %d to reserve bo\n", r); + goto reserve_bo_failed; + } + + r = dma_resv_reserve_shared(bo->tbo.base.resv, 1); + if (r) { + pr_debug("failed %d to reserve bo\n", r); + amdgpu_bo_unreserve(bo); + goto reserve_bo_failed; + } + amdgpu_bo_fence(bo, &svm_bo->eviction_fence->base, true); + + amdgpu_bo_unreserve(bo); + + svm_bo->bo = bo; + prange->svm_bo = svm_bo; + prange->ttm_res = bo->tbo.resource; + prange->offset = 0; + + spin_lock(&svm_bo->list_lock); + list_add(&prange->svm_bo_list, &svm_bo->range_list); + spin_unlock(&svm_bo->list_lock); + + return 0; + +reserve_bo_failed: + amdgpu_bo_unref(&bo); +create_bo_failed: + dma_fence_put(&svm_bo->eviction_fence->base); + kfree(svm_bo); + prange->ttm_res = NULL; + + return r; +} + +void svm_range_vram_node_free(struct svm_range *prange) +{ + svm_range_bo_unref(prange->svm_bo); + prange->ttm_res = NULL; +} + +struct amdgpu_device * +svm_range_get_adev_by_id(struct svm_range *prange, uint32_t gpu_id) +{ + struct kfd_process_device *pdd; + struct kfd_process *p; + int32_t gpu_idx; + + p = container_of(prange->svms, struct kfd_process, svms); + + gpu_idx = kfd_process_gpuidx_from_gpuid(p, gpu_id); + if (gpu_idx < 0) { + pr_debug("failed to get device by id 0x%x\n", gpu_id); + return NULL; + } + pdd = kfd_process_device_from_gpuidx(p, gpu_idx); + if (!pdd) { + pr_debug("failed to get device by idx 0x%x\n", gpu_idx); + return NULL; + } + + return (struct amdgpu_device *)pdd->dev->kgd; +} + +static int svm_range_bo_validate(void *param, struct amdgpu_bo *bo) +{ + struct ttm_operation_ctx ctx = { false, false }; + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); + + return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +} + +static int +svm_range_check_attr(struct kfd_process *p, + uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs) +{ + uint32_t i; + + for (i = 0; i < nattr; i++) { + uint32_t val = attrs[i].value; + int gpuidx = MAX_GPU_INSTANCE; + + switch (attrs[i].type) { + case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: + if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM && + val != KFD_IOCTL_SVM_LOCATION_UNDEFINED) + gpuidx = kfd_process_gpuidx_from_gpuid(p, val); + break; + case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: + if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM) + gpuidx = kfd_process_gpuidx_from_gpuid(p, val); + break; + case KFD_IOCTL_SVM_ATTR_ACCESS: + case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: + case KFD_IOCTL_SVM_ATTR_NO_ACCESS: + gpuidx = kfd_process_gpuidx_from_gpuid(p, val); + break; + case KFD_IOCTL_SVM_ATTR_SET_FLAGS: + break; + case KFD_IOCTL_SVM_ATTR_CLR_FLAGS: + break; + case KFD_IOCTL_SVM_ATTR_GRANULARITY: + break; + default: + pr_debug("unknown attr type 0x%x\n", attrs[i].type); + return -EINVAL; + } + + if (gpuidx < 0) { + pr_debug("no GPU 0x%x found\n", val); + return -EINVAL; + } else if (gpuidx < MAX_GPU_INSTANCE && + !test_bit(gpuidx, p->svms.bitmap_supported)) { + pr_debug("GPU 0x%x not supported\n", val); + return -EINVAL; + } + } + + return 0; +} + +static void +svm_range_apply_attrs(struct kfd_process *p, struct svm_range *prange, + uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs) +{ + uint32_t i; + int gpuidx; + + for (i = 0; i < nattr; i++) { + switch (attrs[i].type) { + case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: + prange->preferred_loc = attrs[i].value; + break; + case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: + prange->prefetch_loc = attrs[i].value; + break; + case KFD_IOCTL_SVM_ATTR_ACCESS: + case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: + case KFD_IOCTL_SVM_ATTR_NO_ACCESS: + gpuidx = kfd_process_gpuidx_from_gpuid(p, + attrs[i].value); + if (attrs[i].type == KFD_IOCTL_SVM_ATTR_NO_ACCESS) { + bitmap_clear(prange->bitmap_access, gpuidx, 1); + bitmap_clear(prange->bitmap_aip, gpuidx, 1); + } else if (attrs[i].type == KFD_IOCTL_SVM_ATTR_ACCESS) { + bitmap_set(prange->bitmap_access, gpuidx, 1); + bitmap_clear(prange->bitmap_aip, gpuidx, 1); + } else { + bitmap_clear(prange->bitmap_access, gpuidx, 1); + bitmap_set(prange->bitmap_aip, gpuidx, 1); + } + break; + case KFD_IOCTL_SVM_ATTR_SET_FLAGS: + prange->flags |= attrs[i].value; + break; + case KFD_IOCTL_SVM_ATTR_CLR_FLAGS: + prange->flags &= ~attrs[i].value; + break; + case KFD_IOCTL_SVM_ATTR_GRANULARITY: + prange->granularity = attrs[i].value; + break; + default: + WARN_ONCE(1, "svm_range_check_attrs wasn't called?"); + } + } +} + +/** + * svm_range_debug_dump - print all range information from svms + * @svms: svm range list header + * + * debug output svm range start, end, prefetch location from svms + * interval tree and link list + * + * Context: The caller must hold svms->lock + */ +static void svm_range_debug_dump(struct svm_range_list *svms) +{ + struct interval_tree_node *node; + struct svm_range *prange; + + pr_debug("dump svms 0x%p list\n", svms); + pr_debug("range\tstart\tpage\tend\t\tlocation\n"); + + list_for_each_entry(prange, &svms->list, list) { + pr_debug("0x%p 0x%lx\t0x%llx\t0x%llx\t0x%x\n", + prange, prange->start, prange->npages, + prange->start + prange->npages - 1, + prange->actual_loc); + } + + pr_debug("dump svms 0x%p interval tree\n", svms); + pr_debug("range\tstart\tpage\tend\t\tlocation\n"); + node = interval_tree_iter_first(&svms->objects, 0, ~0ULL); + while (node) { + prange = container_of(node, struct svm_range, it_node); + pr_debug("0x%p 0x%lx\t0x%llx\t0x%llx\t0x%x\n", + prange, prange->start, prange->npages, + prange->start + prange->npages - 1, + prange->actual_loc); + node = interval_tree_iter_next(node, 0, ~0ULL); + } +} + +static bool +svm_range_is_same_attrs(struct svm_range *old, struct svm_range *new) +{ + return (old->prefetch_loc == new->prefetch_loc && + old->flags == new->flags && + old->granularity == new->granularity); +} + +static int +svm_range_split_array(void *ppnew, void *ppold, size_t size, + uint64_t old_start, uint64_t old_n, + uint64_t new_start, uint64_t new_n) +{ + unsigned char *new, *old, *pold; + uint64_t d; + + if (!ppold) + return 0; + pold = *(unsigned char **)ppold; + if (!pold) + return 0; + + new = kvmalloc_array(new_n, size, GFP_KERNEL); + if (!new) + return -ENOMEM; + + d = (new_start - old_start) * size; + memcpy(new, pold + d, new_n * size); + + old = kvmalloc_array(old_n, size, GFP_KERNEL); + if (!old) { + kvfree(new); + return -ENOMEM; + } + + d = (new_start == old_start) ? new_n * size : 0; + memcpy(old, pold + d, old_n * size); + + kvfree(pold); + *(void **)ppold = old; + *(void **)ppnew = new; + + return 0; +} + +static int +svm_range_split_pages(struct svm_range *new, struct svm_range *old, + uint64_t start, uint64_t last) +{ + uint64_t npages = last - start + 1; + int i, r; + + for (i = 0; i < MAX_GPU_INSTANCE; i++) { + r = svm_range_split_array(&new->dma_addr[i], &old->dma_addr[i], + sizeof(*old->dma_addr[i]), old->start, + npages, new->start, new->npages); + if (r) + return r; + } + + return 0; +} + +static int +svm_range_split_nodes(struct svm_range *new, struct svm_range *old, + uint64_t start, uint64_t last) +{ + uint64_t npages = last - start + 1; + + pr_debug("svms 0x%p new prange 0x%p start 0x%lx [0x%llx 0x%llx]\n", + new->svms, new, new->start, start, last); + + if (new->start == old->start) { + new->offset = old->offset; + old->offset += new->npages; + } else { + new->offset = old->offset + npages; + } + + new->svm_bo = svm_range_bo_ref(old->svm_bo); + new->ttm_res = old->ttm_res; + + spin_lock(&new->svm_bo->list_lock); + list_add(&new->svm_bo_list, &new->svm_bo->range_list); + spin_unlock(&new->svm_bo->list_lock); + + return 0; +} + +/** + * svm_range_split_adjust - split range and adjust + * + * @new: new range + * @old: the old range + * @start: the old range adjust to start address in pages + * @last: the old range adjust to last address in pages + * + * Copy system memory dma_addr or vram ttm_res in old range to new + * range from new_start up to size new->npages, the remaining old range is from + * start to last + * + * Return: + * 0 - OK, -ENOMEM - out of memory + */ +static int +svm_range_split_adjust(struct svm_range *new, struct svm_range *old, + uint64_t start, uint64_t last) +{ + int r; + + pr_debug("svms 0x%p new 0x%lx old [0x%lx 0x%lx] => [0x%llx 0x%llx]\n", + new->svms, new->start, old->start, old->last, start, last); + + if (new->start < old->start || + new->last > old->last) { + WARN_ONCE(1, "invalid new range start or last\n"); + return -EINVAL; + } + + r = svm_range_split_pages(new, old, start, last); + if (r) + return r; + + if (old->actual_loc && old->ttm_res) { + r = svm_range_split_nodes(new, old, start, last); + if (r) + return r; + } + + old->npages = last - start + 1; + old->start = start; + old->last = last; + new->flags = old->flags; + new->preferred_loc = old->preferred_loc; + new->prefetch_loc = old->prefetch_loc; + new->actual_loc = old->actual_loc; + new->granularity = old->granularity; + bitmap_copy(new->bitmap_access, old->bitmap_access, MAX_GPU_INSTANCE); + bitmap_copy(new->bitmap_aip, old->bitmap_aip, MAX_GPU_INSTANCE); + + return 0; +} + +/** + * svm_range_split - split a range in 2 ranges + * + * @prange: the svm range to split + * @start: the remaining range start address in pages + * @last: the remaining range last address in pages + * @new: the result new range generated + * + * Two cases only: + * case 1: if start == prange->start + * prange ==> prange[start, last] + * new range [last + 1, prange->last] + * + * case 2: if last == prange->last + * prange ==> prange[start, last] + * new range [prange->start, start - 1] + * + * Return: + * 0 - OK, -ENOMEM - out of memory, -EINVAL - invalid start, last + */ +static int +svm_range_split(struct svm_range *prange, uint64_t start, uint64_t last, + struct svm_range **new) +{ + uint64_t old_start = prange->start; + uint64_t old_last = prange->last; + struct svm_range_list *svms; + int r = 0; + + pr_debug("svms 0x%p [0x%llx 0x%llx] to [0x%llx 0x%llx]\n", prange->svms, + old_start, old_last, start, last); + + if (old_start != start && old_last != last) + return -EINVAL; + if (start < old_start || last > old_last) + return -EINVAL; + + svms = prange->svms; + if (old_start == start) + *new = svm_range_new(svms, last + 1, old_last); + else + *new = svm_range_new(svms, old_start, start - 1); + if (!*new) + return -ENOMEM; + + r = svm_range_split_adjust(*new, prange, start, last); + if (r) { + pr_debug("failed %d split [0x%llx 0x%llx] to [0x%llx 0x%llx]\n", + r, old_start, old_last, start, last); + svm_range_free(*new); + *new = NULL; + } + + return r; +} + +static int +svm_range_split_tail(struct svm_range *prange, struct svm_range *new, + uint64_t new_last, struct list_head *insert_list) +{ + struct svm_range *tail; + int r = svm_range_split(prange, prange->start, new_last, &tail); + + if (!r) + list_add(&tail->insert_list, insert_list); + return r; +} + +static int +svm_range_split_head(struct svm_range *prange, struct svm_range *new, + uint64_t new_start, struct list_head *insert_list) +{ + struct svm_range *head; + int r = svm_range_split(prange, new_start, prange->last, &head); + + if (!r) + list_add(&head->insert_list, insert_list); + return r; +} + +static void +svm_range_add_child(struct svm_range *prange, struct mm_struct *mm, + struct svm_range *pchild, enum svm_work_list_ops op) +{ + pr_debug("add child 0x%p [0x%lx 0x%lx] to prange 0x%p child list %d\n", + pchild, pchild->start, pchild->last, prange, op); + + pchild->work_item.mm = mm; + pchild->work_item.op = op; + list_add_tail(&pchild->child_list, &prange->child_list); +} + +/** + * svm_range_split_by_granularity - collect ranges within granularity boundary + * + * @p: the process with svms list + * @mm: mm structure + * @addr: the vm fault address in pages, to split the prange + * @parent: parent range if prange is from child list + * @prange: prange to split + * + * Trims @prange to be a single aligned block of prange->granularity if + * possible. The head and tail are added to the child_list in @parent. + * + * Context: caller must hold mmap_read_lock and prange->lock + * + * Return: + * 0 - OK, otherwise error code + */ +int +svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm, + unsigned long addr, struct svm_range *parent, + struct svm_range *prange) +{ + struct svm_range *head, *tail; + unsigned long start, last, size; + int r; + + /* Align splited range start and size to granularity size, then a single + * PTE will be used for whole range, this reduces the number of PTE + * updated and the L1 TLB space used for translation. + */ + size = 1UL << prange->granularity; + start = ALIGN_DOWN(addr, size); + last = ALIGN(addr + 1, size) - 1; + + pr_debug("svms 0x%p split [0x%lx 0x%lx] to [0x%lx 0x%lx] size 0x%lx\n", + prange->svms, prange->start, prange->last, start, last, size); + + if (start > prange->start) { + r = svm_range_split(prange, start, prange->last, &head); + if (r) + return r; + svm_range_add_child(parent, mm, head, SVM_OP_ADD_RANGE); + } + + if (last < prange->last) { + r = svm_range_split(prange, prange->start, last, &tail); + if (r) + return r; + svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE); + } + + /* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */ + if (p->xnack_enabled && prange->work_item.op == SVM_OP_ADD_RANGE) { + prange->work_item.op = SVM_OP_ADD_RANGE_AND_MAP; + pr_debug("change prange 0x%p [0x%lx 0x%lx] op %d\n", + prange, prange->start, prange->last, + SVM_OP_ADD_RANGE_AND_MAP); + } + return 0; +} + +static uint64_t +svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange) +{ + struct amdgpu_device *bo_adev; + uint32_t flags = prange->flags; + uint32_t mapping_flags = 0; + uint64_t pte_flags; + bool snoop = !prange->ttm_res; + bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT; + + if (prange->svm_bo && prange->ttm_res) + bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev); + + switch (adev->asic_type) { + case CHIP_ARCTURUS: + if (prange->svm_bo && prange->ttm_res) { + if (bo_adev == adev) { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW; + } else { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + if (amdgpu_xgmi_same_hive(adev, bo_adev)) + snoop = true; + } + } else { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + } + break; + case CHIP_ALDEBARAN: + if (prange->svm_bo && prange->ttm_res) { + if (bo_adev == adev) { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW; + if (adev->gmc.xgmi.connected_to_cpu) + snoop = true; + } else { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + if (amdgpu_xgmi_same_hive(adev, bo_adev)) + snoop = true; + } + } else { + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + } + break; + default: + mapping_flags |= coherent ? + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + } + + mapping_flags |= AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE; + + if (flags & KFD_IOCTL_SVM_FLAG_GPU_RO) + mapping_flags &= ~AMDGPU_VM_PAGE_WRITEABLE; + if (flags & KFD_IOCTL_SVM_FLAG_GPU_EXEC) + mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; + + pte_flags = AMDGPU_PTE_VALID; + pte_flags |= prange->ttm_res ? 0 : AMDGPU_PTE_SYSTEM; + pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; + + pte_flags |= amdgpu_gem_va_map_flags(adev, mapping_flags); + + pr_debug("svms 0x%p [0x%lx 0x%lx] vram %d PTE 0x%llx mapping 0x%x\n", + prange->svms, prange->start, prange->last, + prange->ttm_res ? 1:0, pte_flags, mapping_flags); + + return pte_flags; +} + +static int +svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, + uint64_t start, uint64_t last, + struct dma_fence **fence) +{ + uint64_t init_pte_value = 0; + + pr_debug("[0x%llx 0x%llx]\n", start, last); + + return amdgpu_vm_bo_update_mapping(adev, adev, vm, false, true, NULL, + start, last, init_pte_value, 0, + NULL, NULL, fence, NULL); +} + +static int +svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, + unsigned long last) +{ + DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE); + struct kfd_process_device *pdd; + struct dma_fence *fence = NULL; + struct amdgpu_device *adev; + struct kfd_process *p; + uint32_t gpuidx; + int r = 0; + + bitmap_or(bitmap, prange->bitmap_access, prange->bitmap_aip, + MAX_GPU_INSTANCE); + p = container_of(prange->svms, struct kfd_process, svms); + + for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) { + pr_debug("unmap from gpu idx 0x%x\n", gpuidx); + pdd = kfd_process_device_from_gpuidx(p, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + return -EINVAL; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + + r = svm_range_unmap_from_gpu(adev, drm_priv_to_vm(pdd->drm_priv), + start, last, &fence); + if (r) + break; + + if (fence) { + r = dma_fence_wait(fence, false); + dma_fence_put(fence); + fence = NULL; + if (r) + break; + } + amdgpu_amdkfd_flush_gpu_tlb_pasid((struct kgd_dev *)adev, + p->pasid, TLB_FLUSH_HEAVYWEIGHT); + } + + return r; +} + +static int +svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct svm_range *prange, dma_addr_t *dma_addr, + struct amdgpu_device *bo_adev, struct dma_fence **fence) +{ + struct amdgpu_bo_va bo_va; + bool table_freed = false; + uint64_t pte_flags; + int r = 0; + + pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, + prange->last); + + if (prange->svm_bo && prange->ttm_res) { + bo_va.is_xgmi = amdgpu_xgmi_same_hive(adev, bo_adev); + prange->mapping.bo_va = &bo_va; + } + + prange->mapping.start = prange->start; + prange->mapping.last = prange->last; + prange->mapping.offset = prange->ttm_res ? prange->offset : 0; + pte_flags = svm_range_get_pte_flags(adev, prange); + + r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false, NULL, + prange->mapping.start, + prange->mapping.last, pte_flags, + prange->mapping.offset, + prange->ttm_res, + dma_addr, &vm->last_update, + &table_freed); + if (r) { + pr_debug("failed %d to map to gpu 0x%lx\n", r, prange->start); + goto out; + } + + r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) { + pr_debug("failed %d to update directories 0x%lx\n", r, + prange->start); + goto out; + } + + if (fence) + *fence = dma_fence_get(vm->last_update); + + if (table_freed) { + struct kfd_process *p; + + p = container_of(prange->svms, struct kfd_process, svms); + amdgpu_amdkfd_flush_gpu_tlb_pasid((struct kgd_dev *)adev, + p->pasid, TLB_FLUSH_LEGACY); + } +out: + prange->mapping.bo_va = NULL; + return r; +} + +static int svm_range_map_to_gpus(struct svm_range *prange, + unsigned long *bitmap, bool wait) +{ + struct kfd_process_device *pdd; + struct amdgpu_device *bo_adev; + struct amdgpu_device *adev; + struct kfd_process *p; + struct dma_fence *fence = NULL; + uint32_t gpuidx; + int r = 0; + + if (prange->svm_bo && prange->ttm_res) + bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev); + else + bo_adev = NULL; + + p = container_of(prange->svms, struct kfd_process, svms); + for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) { + pr_debug("mapping to gpu idx 0x%x\n", gpuidx); + pdd = kfd_process_device_from_gpuidx(p, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + return -EINVAL; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + + pdd = kfd_bind_process_to_device(pdd->dev, p); + if (IS_ERR(pdd)) + return -EINVAL; + + if (bo_adev && adev != bo_adev && + !amdgpu_xgmi_same_hive(adev, bo_adev)) { + pr_debug("cannot map to device idx %d\n", gpuidx); + continue; + } + + r = svm_range_map_to_gpu(adev, drm_priv_to_vm(pdd->drm_priv), + prange, prange->dma_addr[gpuidx], + bo_adev, wait ? &fence : NULL); + if (r) + break; + + if (fence) { + r = dma_fence_wait(fence, false); + dma_fence_put(fence); + fence = NULL; + if (r) { + pr_debug("failed %d to dma fence wait\n", r); + break; + } + } + } + + return r; +} + +struct svm_validate_context { + struct kfd_process *process; + struct svm_range *prange; + bool intr; + unsigned long bitmap[MAX_GPU_INSTANCE]; + struct ttm_validate_buffer tv[MAX_GPU_INSTANCE+1]; + struct list_head validate_list; + struct ww_acquire_ctx ticket; +}; + +static int svm_range_reserve_bos(struct svm_validate_context *ctx) +{ + struct kfd_process_device *pdd; + struct amdgpu_device *adev; + struct amdgpu_vm *vm; + uint32_t gpuidx; + int r; + + INIT_LIST_HEAD(&ctx->validate_list); + for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) { + pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + return -EINVAL; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + vm = drm_priv_to_vm(pdd->drm_priv); + + ctx->tv[gpuidx].bo = &vm->root.bo->tbo; + ctx->tv[gpuidx].num_shared = 4; + list_add(&ctx->tv[gpuidx].head, &ctx->validate_list); + } + if (ctx->prange->svm_bo && ctx->prange->ttm_res) { + ctx->tv[MAX_GPU_INSTANCE].bo = &ctx->prange->svm_bo->bo->tbo; + ctx->tv[MAX_GPU_INSTANCE].num_shared = 1; + list_add(&ctx->tv[MAX_GPU_INSTANCE].head, &ctx->validate_list); + } + + r = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->validate_list, + ctx->intr, NULL); + if (r) { + pr_debug("failed %d to reserve bo\n", r); + return r; + } + + for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) { + pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx); + if (!pdd) { + pr_debug("failed to find device idx %d\n", gpuidx); + r = -EINVAL; + goto unreserve_out; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + + r = amdgpu_vm_validate_pt_bos(adev, drm_priv_to_vm(pdd->drm_priv), + svm_range_bo_validate, NULL); + if (r) { + pr_debug("failed %d validate pt bos\n", r); + goto unreserve_out; + } + } + + return 0; + +unreserve_out: + ttm_eu_backoff_reservation(&ctx->ticket, &ctx->validate_list); + return r; +} + +static void svm_range_unreserve_bos(struct svm_validate_context *ctx) +{ + ttm_eu_backoff_reservation(&ctx->ticket, &ctx->validate_list); +} + +/* + * Validation+GPU mapping with concurrent invalidation (MMU notifiers) + * + * To prevent concurrent destruction or change of range attributes, the + * svm_read_lock must be held. The caller must not hold the svm_write_lock + * because that would block concurrent evictions and lead to deadlocks. To + * serialize concurrent migrations or validations of the same range, the + * prange->migrate_mutex must be held. + * + * For VRAM ranges, the SVM BO must be allocated and valid (protected by its + * eviction fence. + * + * The following sequence ensures race-free validation and GPU mapping: + * + * 1. Reserve page table (and SVM BO if range is in VRAM) + * 2. hmm_range_fault to get page addresses (if system memory) + * 3. DMA-map pages (if system memory) + * 4-a. Take notifier lock + * 4-b. Check that pages still valid (mmu_interval_read_retry) + * 4-c. Check that the range was not split or otherwise invalidated + * 4-d. Update GPU page table + * 4.e. Release notifier lock + * 5. Release page table (and SVM BO) reservation + */ +static int svm_range_validate_and_map(struct mm_struct *mm, + struct svm_range *prange, + int32_t gpuidx, bool intr, bool wait) +{ + struct svm_validate_context ctx; + struct hmm_range *hmm_range; + int r = 0; + + ctx.process = container_of(prange->svms, struct kfd_process, svms); + ctx.prange = prange; + ctx.intr = intr; + + if (gpuidx < MAX_GPU_INSTANCE) { + bitmap_zero(ctx.bitmap, MAX_GPU_INSTANCE); + bitmap_set(ctx.bitmap, gpuidx, 1); + } else if (ctx.process->xnack_enabled) { + bitmap_copy(ctx.bitmap, prange->bitmap_aip, MAX_GPU_INSTANCE); + + /* If prefetch range to GPU, or GPU retry fault migrate range to + * GPU, which has ACCESS attribute to the range, create mapping + * on that GPU. + */ + if (prange->actual_loc) { + gpuidx = kfd_process_gpuidx_from_gpuid(ctx.process, + prange->actual_loc); + if (gpuidx < 0) { + WARN_ONCE(1, "failed get device by id 0x%x\n", + prange->actual_loc); + return -EINVAL; + } + if (test_bit(gpuidx, prange->bitmap_access)) + bitmap_set(ctx.bitmap, gpuidx, 1); + } + } else { + bitmap_or(ctx.bitmap, prange->bitmap_access, + prange->bitmap_aip, MAX_GPU_INSTANCE); + } + + if (bitmap_empty(ctx.bitmap, MAX_GPU_INSTANCE)) + return 0; + + if (prange->actual_loc && !prange->ttm_res) { + /* This should never happen. actual_loc gets set by + * svm_migrate_ram_to_vram after allocating a BO. + */ + WARN(1, "VRAM BO missing during validation\n"); + return -EINVAL; + } + + svm_range_reserve_bos(&ctx); + + if (!prange->actual_loc) { + r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL, + prange->start << PAGE_SHIFT, + prange->npages, &hmm_range, + false, true); + if (r) { + pr_debug("failed %d to get svm range pages\n", r); + goto unreserve_out; + } + + r = svm_range_dma_map(prange, ctx.bitmap, + hmm_range->hmm_pfns); + if (r) { + pr_debug("failed %d to dma map range\n", r); + goto unreserve_out; + } + + prange->validated_once = true; + } + + svm_range_lock(prange); + if (!prange->actual_loc) { + if (amdgpu_hmm_range_get_pages_done(hmm_range)) { + pr_debug("hmm update the range, need validate again\n"); + r = -EAGAIN; + goto unlock_out; + } + } + if (!list_empty(&prange->child_list)) { + pr_debug("range split by unmap in parallel, validate again\n"); + r = -EAGAIN; + goto unlock_out; + } + + r = svm_range_map_to_gpus(prange, ctx.bitmap, wait); + +unlock_out: + svm_range_unlock(prange); +unreserve_out: + svm_range_unreserve_bos(&ctx); + + if (!r) + prange->validate_timestamp = ktime_to_us(ktime_get()); + + return r; +} + +/** + * svm_range_list_lock_and_flush_work - flush pending deferred work + * + * @svms: the svm range list + * @mm: the mm structure + * + * Context: Returns with mmap write lock held, pending deferred work flushed + * + */ +static void +svm_range_list_lock_and_flush_work(struct svm_range_list *svms, + struct mm_struct *mm) +{ +retry_flush_work: + flush_work(&svms->deferred_list_work); + mmap_write_lock(mm); + + if (list_empty(&svms->deferred_range_list)) + return; + mmap_write_unlock(mm); + pr_debug("retry flush\n"); + goto retry_flush_work; +} + +static void svm_range_restore_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct amdkfd_process_info *process_info; + struct svm_range_list *svms; + struct svm_range *prange; + struct kfd_process *p; + struct mm_struct *mm; + int evicted_ranges; + int invalid; + int r; + + svms = container_of(dwork, struct svm_range_list, restore_work); + evicted_ranges = atomic_read(&svms->evicted_ranges); + if (!evicted_ranges) + return; + + pr_debug("restore svm ranges\n"); + + /* kfd_process_notifier_release destroys this worker thread. So during + * the lifetime of this thread, kfd_process and mm will be valid. + */ + p = container_of(svms, struct kfd_process, svms); + process_info = p->kgd_process_info; + mm = p->mm; + if (!mm) + return; + + mutex_lock(&process_info->lock); + svm_range_list_lock_and_flush_work(svms, mm); + mutex_lock(&svms->lock); + + evicted_ranges = atomic_read(&svms->evicted_ranges); + + list_for_each_entry(prange, &svms->list, list) { + invalid = atomic_read(&prange->invalid); + if (!invalid) + continue; + + pr_debug("restoring svms 0x%p prange 0x%p [0x%lx %lx] inv %d\n", + prange->svms, prange, prange->start, prange->last, + invalid); + + /* + * If range is migrating, wait for migration is done. + */ + mutex_lock(&prange->migrate_mutex); + + r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE, + false, true); + if (r) + pr_debug("failed %d to map 0x%lx to gpus\n", r, + prange->start); + + mutex_unlock(&prange->migrate_mutex); + if (r) + goto out_reschedule; + + if (atomic_cmpxchg(&prange->invalid, invalid, 0) != invalid) + goto out_reschedule; + } + + if (atomic_cmpxchg(&svms->evicted_ranges, evicted_ranges, 0) != + evicted_ranges) + goto out_reschedule; + + evicted_ranges = 0; + + r = kgd2kfd_resume_mm(mm); + if (r) { + /* No recovery from this failure. Probably the CP is + * hanging. No point trying again. + */ + pr_debug("failed %d to resume KFD\n", r); + } + + pr_debug("restore svm ranges successfully\n"); + +out_reschedule: + mutex_unlock(&svms->lock); + mmap_write_unlock(mm); + mutex_unlock(&process_info->lock); + + /* If validation failed, reschedule another attempt */ + if (evicted_ranges) { + pr_debug("reschedule to restore svm range\n"); + schedule_delayed_work(&svms->restore_work, + msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS)); + } +} + +/** + * svm_range_evict - evict svm range + * + * Stop all queues of the process to ensure GPU doesn't access the memory, then + * return to let CPU evict the buffer and proceed CPU pagetable update. + * + * Don't need use lock to sync cpu pagetable invalidation with GPU execution. + * If invalidation happens while restore work is running, restore work will + * restart to ensure to get the latest CPU pages mapping to GPU, then start + * the queues. + */ +static int +svm_range_evict(struct svm_range *prange, struct mm_struct *mm, + unsigned long start, unsigned long last) +{ + struct svm_range_list *svms = prange->svms; + struct kfd_process *p; + int r = 0; + + p = container_of(svms, struct kfd_process, svms); + + pr_debug("invalidate svms 0x%p prange [0x%lx 0x%lx] [0x%lx 0x%lx]\n", + svms, prange->start, prange->last, start, last); + + if (!p->xnack_enabled) { + int evicted_ranges; + + atomic_inc(&prange->invalid); + evicted_ranges = atomic_inc_return(&svms->evicted_ranges); + if (evicted_ranges != 1) + return r; + + pr_debug("evicting svms 0x%p range [0x%lx 0x%lx]\n", + prange->svms, prange->start, prange->last); + + /* First eviction, stop the queues */ + r = kgd2kfd_quiesce_mm(mm); + if (r) + pr_debug("failed to quiesce KFD\n"); + + pr_debug("schedule to restore svm %p ranges\n", svms); + schedule_delayed_work(&svms->restore_work, + msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS)); + } else { + struct svm_range *pchild; + unsigned long s, l; + + pr_debug("invalidate unmap svms 0x%p [0x%lx 0x%lx] from GPUs\n", + prange->svms, start, last); + list_for_each_entry(pchild, &prange->child_list, child_list) { + mutex_lock_nested(&pchild->lock, 1); + s = max(start, pchild->start); + l = min(last, pchild->last); + if (l >= s) + svm_range_unmap_from_gpus(pchild, s, l); + mutex_unlock(&pchild->lock); + } + s = max(start, prange->start); + l = min(last, prange->last); + if (l >= s) + svm_range_unmap_from_gpus(prange, s, l); + } + + return r; +} + +static struct svm_range *svm_range_clone(struct svm_range *old) +{ + struct svm_range *new; + + new = svm_range_new(old->svms, old->start, old->last); + if (!new) + return NULL; + + if (old->svm_bo) { + new->ttm_res = old->ttm_res; + new->offset = old->offset; + new->svm_bo = svm_range_bo_ref(old->svm_bo); + spin_lock(&new->svm_bo->list_lock); + list_add(&new->svm_bo_list, &new->svm_bo->range_list); + spin_unlock(&new->svm_bo->list_lock); + } + new->flags = old->flags; + new->preferred_loc = old->preferred_loc; + new->prefetch_loc = old->prefetch_loc; + new->actual_loc = old->actual_loc; + new->granularity = old->granularity; + bitmap_copy(new->bitmap_access, old->bitmap_access, MAX_GPU_INSTANCE); + bitmap_copy(new->bitmap_aip, old->bitmap_aip, MAX_GPU_INSTANCE); + + return new; +} + +/** + * svm_range_handle_overlap - split overlap ranges + * @svms: svm range list header + * @new: range added with this attributes + * @start: range added start address, in pages + * @last: range last address, in pages + * @update_list: output, the ranges attributes are updated. For set_attr, this + * will do validation and map to GPUs. For unmap, this will be + * removed and unmap from GPUs + * @insert_list: output, the ranges will be inserted into svms, attributes are + * not changes. For set_attr, this will add into svms. + * @remove_list:output, the ranges will be removed from svms + * @left: the remaining range after overlap, For set_attr, this will be added + * as new range. + * + * Total have 5 overlap cases. + * + * This function handles overlap of an address interval with existing + * struct svm_ranges for applying new attributes. This may require + * splitting existing struct svm_ranges. All changes should be applied to + * the range_list and interval tree transactionally. If any split operation + * fails, the entire update fails. Therefore the existing overlapping + * svm_ranges are cloned and the original svm_ranges left unchanged. If the + * transaction succeeds, the modified clones are added and the originals + * freed. Otherwise the clones are removed and the old svm_ranges remain. + * + * Context: The caller must hold svms->lock + */ +static int +svm_range_handle_overlap(struct svm_range_list *svms, struct svm_range *new, + unsigned long start, unsigned long last, + struct list_head *update_list, + struct list_head *insert_list, + struct list_head *remove_list, + unsigned long *left) +{ + struct interval_tree_node *node; + struct svm_range *prange; + struct svm_range *tmp; + int r = 0; + + INIT_LIST_HEAD(update_list); + INIT_LIST_HEAD(insert_list); + INIT_LIST_HEAD(remove_list); + + node = interval_tree_iter_first(&svms->objects, start, last); + while (node) { + struct interval_tree_node *next; + struct svm_range *old; + unsigned long next_start; + + pr_debug("found overlap node [0x%lx 0x%lx]\n", node->start, + node->last); + + old = container_of(node, struct svm_range, it_node); + next = interval_tree_iter_next(node, start, last); + next_start = min(node->last, last) + 1; + + if (node->start < start || node->last > last) { + /* node intersects the updated range, clone+split it */ + prange = svm_range_clone(old); + if (!prange) { + r = -ENOMEM; + goto out; + } + + list_add(&old->remove_list, remove_list); + list_add(&prange->insert_list, insert_list); + + if (node->start < start) { + pr_debug("change old range start\n"); + r = svm_range_split_head(prange, new, start, + insert_list); + if (r) + goto out; + } + if (node->last > last) { + pr_debug("change old range last\n"); + r = svm_range_split_tail(prange, new, last, + insert_list); + if (r) + goto out; + } + } else { + /* The node is contained within start..last, + * just update it + */ + prange = old; + } + + if (!svm_range_is_same_attrs(prange, new)) + list_add(&prange->update_list, update_list); + + /* insert a new node if needed */ + if (node->start > start) { + prange = svm_range_new(prange->svms, start, + node->start - 1); + if (!prange) { + r = -ENOMEM; + goto out; + } + + list_add(&prange->insert_list, insert_list); + list_add(&prange->update_list, update_list); + } + + node = next; + start = next_start; + } + + if (left && start <= last) + *left = last - start + 1; + +out: + if (r) + list_for_each_entry_safe(prange, tmp, insert_list, insert_list) + svm_range_free(prange); + + return r; +} + +static void +svm_range_update_notifier_and_interval_tree(struct mm_struct *mm, + struct svm_range *prange) +{ + unsigned long start; + unsigned long last; + + start = prange->notifier.interval_tree.start >> PAGE_SHIFT; + last = prange->notifier.interval_tree.last >> PAGE_SHIFT; + + if (prange->start == start && prange->last == last) + return; + + pr_debug("up notifier 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n", + prange->svms, prange, start, last, prange->start, + prange->last); + + if (start != 0 && last != 0) { + interval_tree_remove(&prange->it_node, &prange->svms->objects); + svm_range_remove_notifier(prange); + } + prange->it_node.start = prange->start; + prange->it_node.last = prange->last; + + interval_tree_insert(&prange->it_node, &prange->svms->objects); + svm_range_add_notifier_locked(mm, prange); +} + +static void +svm_range_handle_list_op(struct svm_range_list *svms, struct svm_range *prange) +{ + struct mm_struct *mm = prange->work_item.mm; + + switch (prange->work_item.op) { + case SVM_OP_NULL: + pr_debug("NULL OP 0x%p prange 0x%p [0x%lx 0x%lx]\n", + svms, prange, prange->start, prange->last); + break; + case SVM_OP_UNMAP_RANGE: + pr_debug("remove 0x%p prange 0x%p [0x%lx 0x%lx]\n", + svms, prange, prange->start, prange->last); + svm_range_unlink(prange); + svm_range_remove_notifier(prange); + svm_range_free(prange); + break; + case SVM_OP_UPDATE_RANGE_NOTIFIER: + pr_debug("update notifier 0x%p prange 0x%p [0x%lx 0x%lx]\n", + svms, prange, prange->start, prange->last); + svm_range_update_notifier_and_interval_tree(mm, prange); + break; + case SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP: + pr_debug("update and map 0x%p prange 0x%p [0x%lx 0x%lx]\n", + svms, prange, prange->start, prange->last); + svm_range_update_notifier_and_interval_tree(mm, prange); + /* TODO: implement deferred validation and mapping */ + break; + case SVM_OP_ADD_RANGE: + pr_debug("add 0x%p prange 0x%p [0x%lx 0x%lx]\n", svms, prange, + prange->start, prange->last); + svm_range_add_to_svms(prange); + svm_range_add_notifier_locked(mm, prange); + break; + case SVM_OP_ADD_RANGE_AND_MAP: + pr_debug("add and map 0x%p prange 0x%p [0x%lx 0x%lx]\n", svms, + prange, prange->start, prange->last); + svm_range_add_to_svms(prange); + svm_range_add_notifier_locked(mm, prange); + /* TODO: implement deferred validation and mapping */ + break; + default: + WARN_ONCE(1, "Unknown prange 0x%p work op %d\n", prange, + prange->work_item.op); + } +} + +static void svm_range_drain_retry_fault(struct svm_range_list *svms) +{ + struct kfd_process_device *pdd; + struct amdgpu_device *adev; + struct kfd_process *p; + uint32_t i; + + p = container_of(svms, struct kfd_process, svms); + + for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) { + pdd = p->pdds[i]; + if (!pdd) + continue; + + pr_debug("drain retry fault gpu %d svms %p\n", i, svms); + adev = (struct amdgpu_device *)pdd->dev->kgd; + + amdgpu_ih_wait_on_checkpoint_process(adev, &adev->irq.ih1); + pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms); + } +} + +static void svm_range_deferred_list_work(struct work_struct *work) +{ + struct svm_range_list *svms; + struct svm_range *prange; + struct mm_struct *mm; + + svms = container_of(work, struct svm_range_list, deferred_list_work); + pr_debug("enter svms 0x%p\n", svms); + + spin_lock(&svms->deferred_list_lock); + while (!list_empty(&svms->deferred_range_list)) { + prange = list_first_entry(&svms->deferred_range_list, + struct svm_range, deferred_list); + spin_unlock(&svms->deferred_list_lock); + pr_debug("prange 0x%p [0x%lx 0x%lx] op %d\n", prange, + prange->start, prange->last, prange->work_item.op); + + /* Make sure no stale retry fault coming after range is freed */ + if (prange->work_item.op == SVM_OP_UNMAP_RANGE) + svm_range_drain_retry_fault(prange->svms); + + mm = prange->work_item.mm; + mmap_write_lock(mm); + mutex_lock(&svms->lock); + + /* Remove from deferred_list must be inside mmap write lock, + * otherwise, svm_range_list_lock_and_flush_work may hold mmap + * write lock, and continue because deferred_list is empty, then + * deferred_list handle is blocked by mmap write lock. + */ + spin_lock(&svms->deferred_list_lock); + list_del_init(&prange->deferred_list); + spin_unlock(&svms->deferred_list_lock); + + mutex_lock(&prange->migrate_mutex); + while (!list_empty(&prange->child_list)) { + struct svm_range *pchild; + + pchild = list_first_entry(&prange->child_list, + struct svm_range, child_list); + pr_debug("child prange 0x%p op %d\n", pchild, + pchild->work_item.op); + list_del_init(&pchild->child_list); + svm_range_handle_list_op(svms, pchild); + } + mutex_unlock(&prange->migrate_mutex); + + svm_range_handle_list_op(svms, prange); + mutex_unlock(&svms->lock); + mmap_write_unlock(mm); + + spin_lock(&svms->deferred_list_lock); + } + spin_unlock(&svms->deferred_list_lock); + + pr_debug("exit svms 0x%p\n", svms); +} + +void +svm_range_add_list_work(struct svm_range_list *svms, struct svm_range *prange, + struct mm_struct *mm, enum svm_work_list_ops op) +{ + spin_lock(&svms->deferred_list_lock); + /* if prange is on the deferred list */ + if (!list_empty(&prange->deferred_list)) { + pr_debug("update exist prange 0x%p work op %d\n", prange, op); + WARN_ONCE(prange->work_item.mm != mm, "unmatch mm\n"); + if (op != SVM_OP_NULL && + prange->work_item.op != SVM_OP_UNMAP_RANGE) + prange->work_item.op = op; + } else { + prange->work_item.op = op; + prange->work_item.mm = mm; + list_add_tail(&prange->deferred_list, + &prange->svms->deferred_range_list); + pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n", + prange, prange->start, prange->last, op); + } + spin_unlock(&svms->deferred_list_lock); +} + +void schedule_deferred_list_work(struct svm_range_list *svms) +{ + spin_lock(&svms->deferred_list_lock); + if (!list_empty(&svms->deferred_range_list)) + schedule_work(&svms->deferred_list_work); + spin_unlock(&svms->deferred_list_lock); +} + +static void +svm_range_unmap_split(struct mm_struct *mm, struct svm_range *parent, + struct svm_range *prange, unsigned long start, + unsigned long last) +{ + struct svm_range *head; + struct svm_range *tail; + + if (prange->work_item.op == SVM_OP_UNMAP_RANGE) { + pr_debug("prange 0x%p [0x%lx 0x%lx] is already freed\n", prange, + prange->start, prange->last); + return; + } + if (start > prange->last || last < prange->start) + return; + + head = tail = prange; + if (start > prange->start) + svm_range_split(prange, prange->start, start - 1, &tail); + if (last < tail->last) + svm_range_split(tail, last + 1, tail->last, &head); + + if (head != prange && tail != prange) { + svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE); + svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE); + } else if (tail != prange) { + svm_range_add_child(parent, mm, tail, SVM_OP_UNMAP_RANGE); + } else if (head != prange) { + svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE); + } else if (parent != prange) { + prange->work_item.op = SVM_OP_UNMAP_RANGE; + } +} + +static void +svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, + unsigned long start, unsigned long last) +{ + struct svm_range_list *svms; + struct svm_range *pchild; + struct kfd_process *p; + unsigned long s, l; + bool unmap_parent; + + p = kfd_lookup_process_by_mm(mm); + if (!p) + return; + svms = &p->svms; + + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n", svms, + prange, prange->start, prange->last, start, last); + + unmap_parent = start <= prange->start && last >= prange->last; + + list_for_each_entry(pchild, &prange->child_list, child_list) { + mutex_lock_nested(&pchild->lock, 1); + s = max(start, pchild->start); + l = min(last, pchild->last); + if (l >= s) + svm_range_unmap_from_gpus(pchild, s, l); + svm_range_unmap_split(mm, prange, pchild, start, last); + mutex_unlock(&pchild->lock); + } + s = max(start, prange->start); + l = min(last, prange->last); + if (l >= s) + svm_range_unmap_from_gpus(prange, s, l); + svm_range_unmap_split(mm, prange, prange, start, last); + + if (unmap_parent) + svm_range_add_list_work(svms, prange, mm, SVM_OP_UNMAP_RANGE); + else + svm_range_add_list_work(svms, prange, mm, + SVM_OP_UPDATE_RANGE_NOTIFIER); + schedule_deferred_list_work(svms); + + kfd_unref_process(p); +} + +/** + * svm_range_cpu_invalidate_pagetables - interval notifier callback + * + * If event is MMU_NOTIFY_UNMAP, this is from CPU unmap range, otherwise, it + * is from migration, or CPU page invalidation callback. + * + * For unmap event, unmap range from GPUs, remove prange from svms in a delayed + * work thread, and split prange if only part of prange is unmapped. + * + * For invalidation event, if GPU retry fault is not enabled, evict the queues, + * then schedule svm_range_restore_work to update GPU mapping and resume queues. + * If GPU retry fault is enabled, unmap the svm range from GPU, retry fault will + * update GPU mapping to recover. + * + * Context: mmap lock, notifier_invalidate_start lock are held + * for invalidate event, prange lock is held if this is from migration + */ +static bool +svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni, + const struct mmu_notifier_range *range, + unsigned long cur_seq) +{ + struct svm_range *prange; + unsigned long start; + unsigned long last; + + if (range->event == MMU_NOTIFY_RELEASE) + return true; + + start = mni->interval_tree.start; + last = mni->interval_tree.last; + start = (start > range->start ? start : range->start) >> PAGE_SHIFT; + last = (last < (range->end - 1) ? last : range->end - 1) >> PAGE_SHIFT; + pr_debug("[0x%lx 0x%lx] range[0x%lx 0x%lx] notifier[0x%lx 0x%lx] %d\n", + start, last, range->start >> PAGE_SHIFT, + (range->end - 1) >> PAGE_SHIFT, + mni->interval_tree.start >> PAGE_SHIFT, + mni->interval_tree.last >> PAGE_SHIFT, range->event); + + prange = container_of(mni, struct svm_range, notifier); + + svm_range_lock(prange); + mmu_interval_set_seq(mni, cur_seq); + + switch (range->event) { + case MMU_NOTIFY_UNMAP: + svm_range_unmap_from_cpu(mni->mm, prange, start, last); + break; + default: + svm_range_evict(prange, mni->mm, start, last); + break; + } + + svm_range_unlock(prange); + + return true; +} + +/** + * svm_range_from_addr - find svm range from fault address + * @svms: svm range list header + * @addr: address to search range interval tree, in pages + * @parent: parent range if range is on child list + * + * Context: The caller must hold svms->lock + * + * Return: the svm_range found or NULL + */ +struct svm_range * +svm_range_from_addr(struct svm_range_list *svms, unsigned long addr, + struct svm_range **parent) +{ + struct interval_tree_node *node; + struct svm_range *prange; + struct svm_range *pchild; + + node = interval_tree_iter_first(&svms->objects, addr, addr); + if (!node) + return NULL; + + prange = container_of(node, struct svm_range, it_node); + pr_debug("address 0x%lx prange [0x%lx 0x%lx] node [0x%lx 0x%lx]\n", + addr, prange->start, prange->last, node->start, node->last); + + if (addr >= prange->start && addr <= prange->last) { + if (parent) + *parent = prange; + return prange; + } + list_for_each_entry(pchild, &prange->child_list, child_list) + if (addr >= pchild->start && addr <= pchild->last) { + pr_debug("found address 0x%lx pchild [0x%lx 0x%lx]\n", + addr, pchild->start, pchild->last); + if (parent) + *parent = prange; + return pchild; + } + + return NULL; +} + +/* svm_range_best_restore_location - decide the best fault restore location + * @prange: svm range structure + * @adev: the GPU on which vm fault happened + * + * This is only called when xnack is on, to decide the best location to restore + * the range mapping after GPU vm fault. Caller uses the best location to do + * migration if actual loc is not best location, then update GPU page table + * mapping to the best location. + * + * If vm fault gpu is range preferred loc, the best_loc is preferred loc. + * If vm fault gpu idx is on range ACCESSIBLE bitmap, best_loc is vm fault gpu + * If vm fault gpu idx is on range ACCESSIBLE_IN_PLACE bitmap, then + * if range actual loc is cpu, best_loc is cpu + * if vm fault gpu is on xgmi same hive of range actual loc gpu, best_loc is + * range actual loc. + * Otherwise, GPU no access, best_loc is -1. + * + * Return: + * -1 means vm fault GPU no access + * 0 for CPU or GPU id + */ +static int32_t +svm_range_best_restore_location(struct svm_range *prange, + struct amdgpu_device *adev, + int32_t *gpuidx) +{ + struct amdgpu_device *bo_adev; + struct kfd_process *p; + uint32_t gpuid; + int r; + + p = container_of(prange->svms, struct kfd_process, svms); + + r = kfd_process_gpuid_from_kgd(p, adev, &gpuid, gpuidx); + if (r < 0) { + pr_debug("failed to get gpuid from kgd\n"); + return -1; + } + + if (prange->preferred_loc == gpuid) + return prange->preferred_loc; + + if (test_bit(*gpuidx, prange->bitmap_access)) + return gpuid; + + if (test_bit(*gpuidx, prange->bitmap_aip)) { + if (!prange->actual_loc) + return 0; + + bo_adev = svm_range_get_adev_by_id(prange, prange->actual_loc); + if (amdgpu_xgmi_same_hive(adev, bo_adev)) + return prange->actual_loc; + else + return 0; + } + + return -1; +} +static int +svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr, + unsigned long *start, unsigned long *last) +{ + struct vm_area_struct *vma; + struct interval_tree_node *node; + unsigned long start_limit, end_limit; + + vma = find_vma(p->mm, addr << PAGE_SHIFT); + if (!vma || (addr << PAGE_SHIFT) < vma->vm_start) { + pr_debug("VMA does not exist in address [0x%llx]\n", addr); + return -EFAULT; + } + start_limit = max(vma->vm_start >> PAGE_SHIFT, + (unsigned long)ALIGN_DOWN(addr, 2UL << 8)); + end_limit = min(vma->vm_end >> PAGE_SHIFT, + (unsigned long)ALIGN(addr + 1, 2UL << 8)); + /* First range that starts after the fault address */ + node = interval_tree_iter_first(&p->svms.objects, addr + 1, ULONG_MAX); + if (node) { + end_limit = min(end_limit, node->start); + /* Last range that ends before the fault address */ + node = container_of(rb_prev(&node->rb), + struct interval_tree_node, rb); + } else { + /* Last range must end before addr because + * there was no range after addr + */ + node = container_of(rb_last(&p->svms.objects.rb_root), + struct interval_tree_node, rb); + } + if (node) { + if (node->last >= addr) { + WARN(1, "Overlap with prev node and page fault addr\n"); + return -EFAULT; + } + start_limit = max(start_limit, node->last + 1); + } + + *start = start_limit; + *last = end_limit - 1; + + pr_debug("vma start: 0x%lx start: 0x%lx vma end: 0x%lx last: 0x%lx\n", + vma->vm_start >> PAGE_SHIFT, *start, + vma->vm_end >> PAGE_SHIFT, *last); + + return 0; + +} +static struct +svm_range *svm_range_create_unregistered_range(struct amdgpu_device *adev, + struct kfd_process *p, + struct mm_struct *mm, + int64_t addr) +{ + struct svm_range *prange = NULL; + unsigned long start, last; + uint32_t gpuid, gpuidx; + + if (svm_range_get_range_boundaries(p, addr, &start, &last)) + return NULL; + + prange = svm_range_new(&p->svms, start, last); + if (!prange) { + pr_debug("Failed to create prange in address [0x%llx]\n", addr); + return NULL; + } + if (kfd_process_gpuid_from_kgd(p, adev, &gpuid, &gpuidx)) { + pr_debug("failed to get gpuid from kgd\n"); + svm_range_free(prange); + return NULL; + } + + svm_range_add_to_svms(prange); + svm_range_add_notifier_locked(mm, prange); + + return prange; +} + +/* svm_range_skip_recover - decide if prange can be recovered + * @prange: svm range structure + * + * GPU vm retry fault handle skip recover the range for cases: + * 1. prange is on deferred list to be removed after unmap, it is stale fault, + * deferred list work will drain the stale fault before free the prange. + * 2. prange is on deferred list to add interval notifier after split, or + * 3. prange is child range, it is split from parent prange, recover later + * after interval notifier is added. + * + * Return: true to skip recover, false to recover + */ +static bool svm_range_skip_recover(struct svm_range *prange) +{ + struct svm_range_list *svms = prange->svms; + + spin_lock(&svms->deferred_list_lock); + if (list_empty(&prange->deferred_list) && + list_empty(&prange->child_list)) { + spin_unlock(&svms->deferred_list_lock); + return false; + } + spin_unlock(&svms->deferred_list_lock); + + if (prange->work_item.op == SVM_OP_UNMAP_RANGE) { + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] unmapped\n", + svms, prange, prange->start, prange->last); + return true; + } + if (prange->work_item.op == SVM_OP_ADD_RANGE_AND_MAP || + prange->work_item.op == SVM_OP_ADD_RANGE) { + pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] not added yet\n", + svms, prange, prange->start, prange->last); + return true; + } + return false; +} + +int +svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, + uint64_t addr) +{ + struct mm_struct *mm = NULL; + struct svm_range_list *svms; + struct svm_range *prange; + struct kfd_process *p; + uint64_t timestamp; + int32_t best_loc, gpuidx; + bool write_locked = false; + int r = 0; + + if (!KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) { + pr_debug("device does not support SVM\n"); + return -EFAULT; + } + + p = kfd_lookup_process_by_pasid(pasid); + if (!p) { + pr_debug("kfd process not founded pasid 0x%x\n", pasid); + return -ESRCH; + } + if (!p->xnack_enabled) { + pr_debug("XNACK not enabled for pasid 0x%x\n", pasid); + return -EFAULT; + } + svms = &p->svms; + + pr_debug("restoring svms 0x%p fault address 0x%llx\n", svms, addr); + + mm = get_task_mm(p->lead_thread); + if (!mm) { + pr_debug("svms 0x%p failed to get mm\n", svms); + r = -ESRCH; + goto out; + } + + mmap_read_lock(mm); +retry_write_locked: + mutex_lock(&svms->lock); + prange = svm_range_from_addr(svms, addr, NULL); + if (!prange) { + pr_debug("failed to find prange svms 0x%p address [0x%llx]\n", + svms, addr); + if (!write_locked) { + /* Need the write lock to create new range with MMU notifier. + * Also flush pending deferred work to make sure the interval + * tree is up to date before we add a new range + */ + mutex_unlock(&svms->lock); + mmap_read_unlock(mm); + mmap_write_lock(mm); + write_locked = true; + goto retry_write_locked; + } + prange = svm_range_create_unregistered_range(adev, p, mm, addr); + if (!prange) { + pr_debug("failed to create unregistered range svms 0x%p address [0x%llx]\n", + svms, addr); + mmap_write_downgrade(mm); + r = -EFAULT; + goto out_unlock_svms; + } + } + if (write_locked) + mmap_write_downgrade(mm); + + mutex_lock(&prange->migrate_mutex); + + if (svm_range_skip_recover(prange)) { + amdgpu_gmc_filter_faults_remove(adev, addr, pasid); + goto out_unlock_range; + } + + timestamp = ktime_to_us(ktime_get()) - prange->validate_timestamp; + /* skip duplicate vm fault on different pages of same range */ + if (timestamp < AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING) { + pr_debug("svms 0x%p [0x%lx %lx] already restored\n", + svms, prange->start, prange->last); + goto out_unlock_range; + } + + best_loc = svm_range_best_restore_location(prange, adev, &gpuidx); + if (best_loc == -1) { + pr_debug("svms %p failed get best restore loc [0x%lx 0x%lx]\n", + svms, prange->start, prange->last); + r = -EACCES; + goto out_unlock_range; + } + + pr_debug("svms %p [0x%lx 0x%lx] best restore 0x%x, actual loc 0x%x\n", + svms, prange->start, prange->last, best_loc, + prange->actual_loc); + + if (prange->actual_loc != best_loc) { + if (best_loc) { + r = svm_migrate_to_vram(prange, best_loc, mm); + if (r) { + pr_debug("svm_migrate_to_vram failed (%d) at %llx, falling back to system memory\n", + r, addr); + /* Fallback to system memory if migration to + * VRAM failed + */ + if (prange->actual_loc) + r = svm_migrate_vram_to_ram(prange, mm); + else + r = 0; + } + } else { + r = svm_migrate_vram_to_ram(prange, mm); + } + if (r) { + pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n", + r, svms, prange->start, prange->last); + goto out_unlock_range; + } + } + + r = svm_range_validate_and_map(mm, prange, gpuidx, false, false); + if (r) + pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n", + r, svms, prange->start, prange->last); + +out_unlock_range: + mutex_unlock(&prange->migrate_mutex); +out_unlock_svms: + mutex_unlock(&svms->lock); + mmap_read_unlock(mm); + mmput(mm); +out: + kfd_unref_process(p); + + if (r == -EAGAIN) { + pr_debug("recover vm fault later\n"); + amdgpu_gmc_filter_faults_remove(adev, addr, pasid); + r = 0; + } + return r; +} + +void svm_range_list_fini(struct kfd_process *p) +{ + struct svm_range *prange; + struct svm_range *next; + + pr_debug("pasid 0x%x svms 0x%p\n", p->pasid, &p->svms); + + /* Ensure list work is finished before process is destroyed */ + flush_work(&p->svms.deferred_list_work); + + list_for_each_entry_safe(prange, next, &p->svms.list, list) { + svm_range_unlink(prange); + svm_range_remove_notifier(prange); + svm_range_free(prange); + } + + mutex_destroy(&p->svms.lock); + + pr_debug("pasid 0x%x svms 0x%p done\n", p->pasid, &p->svms); +} + +int svm_range_list_init(struct kfd_process *p) +{ + struct svm_range_list *svms = &p->svms; + int i; + + svms->objects = RB_ROOT_CACHED; + mutex_init(&svms->lock); + INIT_LIST_HEAD(&svms->list); + atomic_set(&svms->evicted_ranges, 0); + INIT_DELAYED_WORK(&svms->restore_work, svm_range_restore_work); + INIT_WORK(&svms->deferred_list_work, svm_range_deferred_list_work); + INIT_LIST_HEAD(&svms->deferred_range_list); + spin_lock_init(&svms->deferred_list_lock); + + for (i = 0; i < p->n_pdds; i++) + if (KFD_IS_SVM_API_SUPPORTED(p->pdds[i]->dev)) + bitmap_set(svms->bitmap_supported, i, 1); + + return 0; +} + +/** + * svm_range_is_valid - check if virtual address range is valid + * @mm: current process mm_struct + * @start: range start address, in pages + * @size: range size, in pages + * + * Valid virtual address range means it belongs to one or more VMAs + * + * Context: Process context + * + * Return: + * true - valid svm range + * false - invalid svm range + */ +static bool +svm_range_is_valid(struct mm_struct *mm, uint64_t start, uint64_t size) +{ + const unsigned long device_vma = VM_IO | VM_PFNMAP | VM_MIXEDMAP; + struct vm_area_struct *vma; + unsigned long end; + + start <<= PAGE_SHIFT; + end = start + (size << PAGE_SHIFT); + + do { + vma = find_vma(mm, start); + if (!vma || start < vma->vm_start || + (vma->vm_flags & device_vma)) + return false; + start = min(end, vma->vm_end); + } while (start < end); + + return true; +} + +/** + * svm_range_add - add svm range and handle overlap + * @p: the range add to this process svms + * @start: page size aligned + * @size: page size aligned + * @nattr: number of attributes + * @attrs: array of attributes + * @update_list: output, the ranges need validate and update GPU mapping + * @insert_list: output, the ranges need insert to svms + * @remove_list: output, the ranges are replaced and need remove from svms + * + * Check if the virtual address range has overlap with the registered ranges, + * split the overlapped range, copy and adjust pages address and vram nodes in + * old and new ranges. + * + * Context: Process context, caller must hold svms->lock + * + * Return: + * 0 - OK, otherwise error code + */ +static int +svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size, + uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs, + struct list_head *update_list, struct list_head *insert_list, + struct list_head *remove_list) +{ + uint64_t last = start + size - 1UL; + struct svm_range_list *svms; + struct svm_range new = {0}; + struct svm_range *prange; + unsigned long left = 0; + int r = 0; + + pr_debug("svms 0x%p [0x%llx 0x%llx]\n", &p->svms, start, last); + + svm_range_apply_attrs(p, &new, nattr, attrs); + + svms = &p->svms; + + r = svm_range_handle_overlap(svms, &new, start, last, update_list, + insert_list, remove_list, &left); + if (r) + return r; + + if (left) { + prange = svm_range_new(svms, last - left + 1, last); + list_add(&prange->insert_list, insert_list); + list_add(&prange->update_list, update_list); + } + + return 0; +} + +/* svm_range_best_prefetch_location - decide the best prefetch location + * @prange: svm range structure + * + * For xnack off: + * If range map to single GPU, the best acutal location is prefetch loc, which + * can be CPU or GPU. + * + * If range map to multiple GPUs, only if mGPU connection on xgmi same hive, + * the best actual location could be prefetch_loc GPU. If mGPU connection on + * PCIe, the best actual location is always CPU, because GPU cannot access vram + * of other GPUs, assuming PCIe small bar (large bar support is not upstream). + * + * For xnack on: + * The best actual location is prefetch location. If mGPU connection on xgmi + * same hive, range map to multiple GPUs. Otherwise, the range only map to + * actual location GPU. Other GPU access vm fault will trigger migration. + * + * Context: Process context + * + * Return: + * 0 for CPU or GPU id + */ +static uint32_t +svm_range_best_prefetch_location(struct svm_range *prange) +{ + DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE); + uint32_t best_loc = prange->prefetch_loc; + struct kfd_process_device *pdd; + struct amdgpu_device *bo_adev; + struct amdgpu_device *adev; + struct kfd_process *p; + uint32_t gpuidx; + + p = container_of(prange->svms, struct kfd_process, svms); + + /* xnack on */ + if (p->xnack_enabled) + goto out; + + /* xnack off */ + if (!best_loc || best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED) + goto out; + + bo_adev = svm_range_get_adev_by_id(prange, best_loc); + if (!bo_adev) { + WARN_ONCE(1, "failed to get device by id 0x%x\n", best_loc); + best_loc = 0; + goto out; + } + bitmap_or(bitmap, prange->bitmap_access, prange->bitmap_aip, + MAX_GPU_INSTANCE); + + for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) { + pdd = kfd_process_device_from_gpuidx(p, gpuidx); + if (!pdd) { + pr_debug("failed to get device by idx 0x%x\n", gpuidx); + continue; + } + adev = (struct amdgpu_device *)pdd->dev->kgd; + + if (adev == bo_adev) + continue; + + if (!amdgpu_xgmi_same_hive(adev, bo_adev)) { + best_loc = 0; + break; + } + } + +out: + pr_debug("xnack %d svms 0x%p [0x%lx 0x%lx] best loc 0x%x\n", + p->xnack_enabled, &p->svms, prange->start, prange->last, + best_loc); + + return best_loc; +} + +/* FIXME: This is a workaround for page locking bug when some pages are + * invalid during migration to VRAM + */ +void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm) +{ + struct hmm_range *hmm_range; + int r; + + if (prange->validated_once) + return; + + r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL, + prange->start << PAGE_SHIFT, + prange->npages, &hmm_range, + false, true); + if (!r) { + amdgpu_hmm_range_get_pages_done(hmm_range); + prange->validated_once = true; + } +} + +/* svm_range_trigger_migration - start page migration if prefetch loc changed + * @mm: current process mm_struct + * @prange: svm range structure + * @migrated: output, true if migration is triggered + * + * If range perfetch_loc is GPU, actual loc is cpu 0, then migrate the range + * from ram to vram. + * If range prefetch_loc is cpu 0, actual loc is GPU, then migrate the range + * from vram to ram. + * + * If GPU vm fault retry is not enabled, migration interact with MMU notifier + * and restore work: + * 1. migrate_vma_setup invalidate pages, MMU notifier callback svm_range_evict + * stops all queues, schedule restore work + * 2. svm_range_restore_work wait for migration is done by + * a. svm_range_validate_vram takes prange->migrate_mutex + * b. svm_range_validate_ram HMM get pages wait for CPU fault handle returns + * 3. restore work update mappings of GPU, resume all queues. + * + * Context: Process context + * + * Return: + * 0 - OK, otherwise - error code of migration + */ +static int +svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange, + bool *migrated) +{ + uint32_t best_loc; + int r = 0; + + *migrated = false; + best_loc = svm_range_best_prefetch_location(prange); + + if (best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED || + best_loc == prange->actual_loc) + return 0; + + /* + * Prefetch to GPU without host access flag, set actual_loc to gpu, then + * validate on gpu and map to gpus will be handled afterwards. + */ + if (best_loc && !prange->actual_loc && + !(prange->flags & KFD_IOCTL_SVM_FLAG_HOST_ACCESS)) { + prange->actual_loc = best_loc; + return 0; + } + + if (!best_loc) { + r = svm_migrate_vram_to_ram(prange, mm); + *migrated = !r; + return r; + } + + r = svm_migrate_to_vram(prange, best_loc, mm); + *migrated = !r; + + return r; +} + +int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence) +{ + if (!fence) + return -EINVAL; + + if (dma_fence_is_signaled(&fence->base)) + return 0; + + if (fence->svm_bo) { + WRITE_ONCE(fence->svm_bo->evicting, 1); + schedule_work(&fence->svm_bo->eviction_work); + } + + return 0; +} + +static void svm_range_evict_svm_bo_worker(struct work_struct *work) +{ + struct svm_range_bo *svm_bo; + struct kfd_process *p; + struct mm_struct *mm; + + svm_bo = container_of(work, struct svm_range_bo, eviction_work); + if (!svm_bo_ref_unless_zero(svm_bo)) + return; /* svm_bo was freed while eviction was pending */ + + /* svm_range_bo_release destroys this worker thread. So during + * the lifetime of this thread, kfd_process and mm will be valid. + */ + p = container_of(svm_bo->svms, struct kfd_process, svms); + mm = p->mm; + if (!mm) + return; + + mmap_read_lock(mm); + spin_lock(&svm_bo->list_lock); + while (!list_empty(&svm_bo->range_list)) { + struct svm_range *prange = + list_first_entry(&svm_bo->range_list, + struct svm_range, svm_bo_list); + list_del_init(&prange->svm_bo_list); + spin_unlock(&svm_bo->list_lock); + + pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, + prange->start, prange->last); + + mutex_lock(&prange->migrate_mutex); + svm_migrate_vram_to_ram(prange, svm_bo->eviction_fence->mm); + + mutex_lock(&prange->lock); + prange->svm_bo = NULL; + mutex_unlock(&prange->lock); + + mutex_unlock(&prange->migrate_mutex); + + spin_lock(&svm_bo->list_lock); + } + spin_unlock(&svm_bo->list_lock); + mmap_read_unlock(mm); + + dma_fence_signal(&svm_bo->eviction_fence->base); + /* This is the last reference to svm_bo, after svm_range_vram_node_free + * has been called in svm_migrate_vram_to_ram + */ + WARN_ONCE(kref_read(&svm_bo->kref) != 1, "This was not the last reference\n"); + svm_range_bo_unref(svm_bo); +} + +static int +svm_range_set_attr(struct kfd_process *p, uint64_t start, uint64_t size, + uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs) +{ + struct amdkfd_process_info *process_info = p->kgd_process_info; + struct mm_struct *mm = current->mm; + struct list_head update_list; + struct list_head insert_list; + struct list_head remove_list; + struct svm_range_list *svms; + struct svm_range *prange; + struct svm_range *next; + int r = 0; + + pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] pages 0x%llx\n", + p->pasid, &p->svms, start, start + size - 1, size); + + r = svm_range_check_attr(p, nattr, attrs); + if (r) + return r; + + svms = &p->svms; + + mutex_lock(&process_info->lock); + + svm_range_list_lock_and_flush_work(svms, mm); + + if (!svm_range_is_valid(mm, start, size)) { + pr_debug("invalid range\n"); + r = -EFAULT; + mmap_write_unlock(mm); + goto out; + } + + mutex_lock(&svms->lock); + + /* Add new range and split existing ranges as needed */ + r = svm_range_add(p, start, size, nattr, attrs, &update_list, + &insert_list, &remove_list); + if (r) { + mutex_unlock(&svms->lock); + mmap_write_unlock(mm); + goto out; + } + /* Apply changes as a transaction */ + list_for_each_entry_safe(prange, next, &insert_list, insert_list) { + svm_range_add_to_svms(prange); + svm_range_add_notifier_locked(mm, prange); + } + list_for_each_entry(prange, &update_list, update_list) { + svm_range_apply_attrs(p, prange, nattr, attrs); + /* TODO: unmap ranges from GPU that lost access */ + } + list_for_each_entry_safe(prange, next, &remove_list, + remove_list) { + pr_debug("unlink old 0x%p prange 0x%p [0x%lx 0x%lx]\n", + prange->svms, prange, prange->start, + prange->last); + svm_range_unlink(prange); + svm_range_remove_notifier(prange); + svm_range_free(prange); + } + + mmap_write_downgrade(mm); + /* Trigger migrations and revalidate and map to GPUs as needed. If + * this fails we may be left with partially completed actions. There + * is no clean way of rolling back to the previous state in such a + * case because the rollback wouldn't be guaranteed to work either. + */ + list_for_each_entry(prange, &update_list, update_list) { + bool migrated; + + mutex_lock(&prange->migrate_mutex); + + r = svm_range_trigger_migration(mm, prange, &migrated); + if (r) + goto out_unlock_range; + + if (migrated && !p->xnack_enabled) { + pr_debug("restore_work will update mappings of GPUs\n"); + mutex_unlock(&prange->migrate_mutex); + continue; + } + + r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE, + true, true); + if (r) + pr_debug("failed %d to map svm range\n", r); + +out_unlock_range: + mutex_unlock(&prange->migrate_mutex); + if (r) + break; + } + + svm_range_debug_dump(svms); + + mutex_unlock(&svms->lock); + mmap_read_unlock(mm); +out: + mutex_unlock(&process_info->lock); + + pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] done, r=%d\n", p->pasid, + &p->svms, start, start + size - 1, r); + + return r; +} + +static int +svm_range_get_attr(struct kfd_process *p, uint64_t start, uint64_t size, + uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs) +{ + DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE); + DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE); + bool get_preferred_loc = false; + bool get_prefetch_loc = false; + bool get_granularity = false; + bool get_accessible = false; + bool get_flags = false; + uint64_t last = start + size - 1UL; + struct mm_struct *mm = current->mm; + uint8_t granularity = 0xff; + struct interval_tree_node *node; + struct svm_range_list *svms; + struct svm_range *prange; + uint32_t prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + uint32_t location = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + uint32_t flags = 0xffffffff; + int gpuidx; + uint32_t i; + + pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start, + start + size - 1, nattr); + + mmap_read_lock(mm); + if (!svm_range_is_valid(mm, start, size)) { + pr_debug("invalid range\n"); + mmap_read_unlock(mm); + return -EINVAL; + } + mmap_read_unlock(mm); + + for (i = 0; i < nattr; i++) { + switch (attrs[i].type) { + case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: + get_preferred_loc = true; + break; + case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: + get_prefetch_loc = true; + break; + case KFD_IOCTL_SVM_ATTR_ACCESS: + get_accessible = true; + break; + case KFD_IOCTL_SVM_ATTR_SET_FLAGS: + get_flags = true; + break; + case KFD_IOCTL_SVM_ATTR_GRANULARITY: + get_granularity = true; + break; + case KFD_IOCTL_SVM_ATTR_CLR_FLAGS: + case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: + case KFD_IOCTL_SVM_ATTR_NO_ACCESS: + fallthrough; + default: + pr_debug("get invalid attr type 0x%x\n", attrs[i].type); + return -EINVAL; + } + } + + svms = &p->svms; + + mutex_lock(&svms->lock); + + node = interval_tree_iter_first(&svms->objects, start, last); + if (!node) { + pr_debug("range attrs not found return default values\n"); + svm_range_set_default_attributes(&location, &prefetch_loc, + &granularity, &flags); + if (p->xnack_enabled) + bitmap_copy(bitmap_access, svms->bitmap_supported, + MAX_GPU_INSTANCE); + else + bitmap_zero(bitmap_access, MAX_GPU_INSTANCE); + bitmap_zero(bitmap_aip, MAX_GPU_INSTANCE); + goto fill_values; + } + bitmap_copy(bitmap_access, svms->bitmap_supported, MAX_GPU_INSTANCE); + bitmap_copy(bitmap_aip, svms->bitmap_supported, MAX_GPU_INSTANCE); + + while (node) { + struct interval_tree_node *next; + + prange = container_of(node, struct svm_range, it_node); + next = interval_tree_iter_next(node, start, last); + + if (get_preferred_loc) { + if (prange->preferred_loc == + KFD_IOCTL_SVM_LOCATION_UNDEFINED || + (location != KFD_IOCTL_SVM_LOCATION_UNDEFINED && + location != prange->preferred_loc)) { + location = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + get_preferred_loc = false; + } else { + location = prange->preferred_loc; + } + } + if (get_prefetch_loc) { + if (prange->prefetch_loc == + KFD_IOCTL_SVM_LOCATION_UNDEFINED || + (prefetch_loc != KFD_IOCTL_SVM_LOCATION_UNDEFINED && + prefetch_loc != prange->prefetch_loc)) { + prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED; + get_prefetch_loc = false; + } else { + prefetch_loc = prange->prefetch_loc; + } + } + if (get_accessible) { + bitmap_and(bitmap_access, bitmap_access, + prange->bitmap_access, MAX_GPU_INSTANCE); + bitmap_and(bitmap_aip, bitmap_aip, + prange->bitmap_aip, MAX_GPU_INSTANCE); + } + if (get_flags) + flags &= prange->flags; + + if (get_granularity && prange->granularity < granularity) + granularity = prange->granularity; + + node = next; + } +fill_values: + mutex_unlock(&svms->lock); + + for (i = 0; i < nattr; i++) { + switch (attrs[i].type) { + case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: + attrs[i].value = location; + break; + case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: + attrs[i].value = prefetch_loc; + break; + case KFD_IOCTL_SVM_ATTR_ACCESS: + gpuidx = kfd_process_gpuidx_from_gpuid(p, + attrs[i].value); + if (gpuidx < 0) { + pr_debug("invalid gpuid %x\n", attrs[i].value); + return -EINVAL; + } + if (test_bit(gpuidx, bitmap_access)) + attrs[i].type = KFD_IOCTL_SVM_ATTR_ACCESS; + else if (test_bit(gpuidx, bitmap_aip)) + attrs[i].type = + KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE; + else + attrs[i].type = KFD_IOCTL_SVM_ATTR_NO_ACCESS; + break; + case KFD_IOCTL_SVM_ATTR_SET_FLAGS: + attrs[i].value = flags; + break; + case KFD_IOCTL_SVM_ATTR_GRANULARITY: + attrs[i].value = (uint32_t)granularity; + break; + } + } + + return 0; +} + +int +svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start, + uint64_t size, uint32_t nattrs, struct kfd_ioctl_svm_attribute *attrs) +{ + int r; + + start >>= PAGE_SHIFT; + size >>= PAGE_SHIFT; + + switch (op) { + case KFD_IOCTL_SVM_OP_SET_ATTR: + r = svm_range_set_attr(p, start, size, nattrs, attrs); + break; + case KFD_IOCTL_SVM_OP_GET_ATTR: + r = svm_range_get_attr(p, start, size, nattrs, attrs); + break; + default: + r = EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h new file mode 100644 index 000000000000..0c0fc399395e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2020-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_SVM_H_ +#define KFD_SVM_H_ + +#if IS_ENABLED(CONFIG_HSA_AMD_SVM) + +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "kfd_priv.h" + +struct svm_range_bo { + struct amdgpu_bo *bo; + struct kref kref; + struct list_head range_list; /* all svm ranges shared this bo */ + spinlock_t list_lock; + struct amdgpu_amdkfd_fence *eviction_fence; + struct work_struct eviction_work; + struct svm_range_list *svms; + uint32_t evicting; +}; + +enum svm_work_list_ops { + SVM_OP_NULL, + SVM_OP_UNMAP_RANGE, + SVM_OP_UPDATE_RANGE_NOTIFIER, + SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP, + SVM_OP_ADD_RANGE, + SVM_OP_ADD_RANGE_AND_MAP +}; + +struct svm_work_list_item { + enum svm_work_list_ops op; + struct mm_struct *mm; +}; + +/** + * struct svm_range - shared virtual memory range + * + * @svms: list of svm ranges, structure defined in kfd_process + * @migrate_mutex: to serialize range migration, validation and mapping update + * @start: range start address in pages + * @last: range last address in pages + * @it_node: node [start, last] stored in interval tree, start, last are page + * aligned, page size is (last - start + 1) + * @list: link list node, used to scan all ranges of svms + * @update_list:link list node used to add to update_list + * @remove_list:link list node used to add to remove list + * @insert_list:link list node used to add to insert list + * @mapping: bo_va mapping structure to create and update GPU page table + * @npages: number of pages + * @dma_addr: dma mapping address on each GPU for system memory physical page + * @ttm_res: vram ttm resource map + * @offset: range start offset within mm_nodes + * @svm_bo: struct to manage splited amdgpu_bo + * @svm_bo_list:link list node, to scan all ranges which share same svm_bo + * @lock: protect prange start, last, child_list, svm_bo_list + * @saved_flags:save/restore current PF_MEMALLOC flags + * @flags: flags defined as KFD_IOCTL_SVM_FLAG_* + * @perferred_loc: perferred location, 0 for CPU, or GPU id + * @perfetch_loc: last prefetch location, 0 for CPU, or GPU id + * @actual_loc: the actual location, 0 for CPU, or GPU id + * @granularity:migration granularity, log2 num pages + * @invalid: not 0 means cpu page table is invalidated + * @validate_timestamp: system timestamp when range is validated + * @notifier: register mmu interval notifier + * @work_item: deferred work item information + * @deferred_list: list header used to add range to deferred list + * @child_list: list header for split ranges which are not added to svms yet + * @bitmap_access: index bitmap of GPUs which can access the range + * @bitmap_aip: index bitmap of GPUs which can access the range in place + * + * Data structure for virtual memory range shared by CPU and GPUs, it can be + * allocated from system memory ram or device vram, and migrate from ram to vram + * or from vram to ram. + */ +struct svm_range { + struct svm_range_list *svms; + struct mutex migrate_mutex; + unsigned long start; + unsigned long last; + struct interval_tree_node it_node; + struct list_head list; + struct list_head update_list; + struct list_head remove_list; + struct list_head insert_list; + struct amdgpu_bo_va_mapping mapping; + uint64_t npages; + dma_addr_t *dma_addr[MAX_GPU_INSTANCE]; + struct ttm_resource *ttm_res; + uint64_t offset; + struct svm_range_bo *svm_bo; + struct list_head svm_bo_list; + struct mutex lock; + unsigned int saved_flags; + uint32_t flags; + uint32_t preferred_loc; + uint32_t prefetch_loc; + uint32_t actual_loc; + uint8_t granularity; + atomic_t invalid; + uint64_t validate_timestamp; + struct mmu_interval_notifier notifier; + struct svm_work_list_item work_item; + struct list_head deferred_list; + struct list_head child_list; + DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE); + DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE); + bool validated_once; +}; + +static inline void svm_range_lock(struct svm_range *prange) +{ + mutex_lock(&prange->lock); + prange->saved_flags = memalloc_noreclaim_save(); + +} +static inline void svm_range_unlock(struct svm_range *prange) +{ + memalloc_noreclaim_restore(prange->saved_flags); + mutex_unlock(&prange->lock); +} + +int svm_range_list_init(struct kfd_process *p); +void svm_range_list_fini(struct kfd_process *p); +int svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start, + uint64_t size, uint32_t nattrs, + struct kfd_ioctl_svm_attribute *attrs); +struct svm_range *svm_range_from_addr(struct svm_range_list *svms, + unsigned long addr, + struct svm_range **parent); +struct amdgpu_device *svm_range_get_adev_by_id(struct svm_range *prange, + uint32_t id); +int svm_range_vram_node_new(struct amdgpu_device *adev, + struct svm_range *prange, bool clear); +void svm_range_vram_node_free(struct svm_range *prange); +int svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm, + unsigned long addr, struct svm_range *parent, + struct svm_range *prange); +int svm_range_restore_pages(struct amdgpu_device *adev, + unsigned int pasid, uint64_t addr); +int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence); +void svm_range_add_list_work(struct svm_range_list *svms, + struct svm_range *prange, struct mm_struct *mm, + enum svm_work_list_ops op); +void schedule_deferred_list_work(struct svm_range_list *svms); +void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr, + unsigned long offset, unsigned long npages); +void svm_range_free_dma_mappings(struct svm_range *prange); +void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm); + +/* SVM API and HMM page migration work together, device memory type + * is initialized to not 0 when page migration register device memory. + */ +#define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0) + +#else + +struct kfd_process; + +static inline int svm_range_list_init(struct kfd_process *p) +{ + return 0; +} +static inline void svm_range_list_fini(struct kfd_process *p) +{ + /* empty */ +} + +static inline int svm_range_restore_pages(struct amdgpu_device *adev, + unsigned int pasid, uint64_t addr) +{ + return -EFAULT; +} + +static inline int svm_range_schedule_evict_svm_bo( + struct amdgpu_amdkfd_fence *fence) +{ + WARN_ONCE(1, "SVM eviction fence triggered, but SVM is disabled"); + return -EINVAL; +} + +#define KFD_IS_SVM_API_SUPPORTED(dev) false + +#endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */ + +#endif /* KFD_SVM_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index cdef608db4f4..b1ce072aa20b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -36,6 +36,7 @@ #include "kfd_topology.h" #include "kfd_device_queue_manager.h" #include "kfd_iommu.h" +#include "kfd_svm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_ras.h" @@ -1192,40 +1193,83 @@ static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev) mem->mem_clk_max = local_mem_info.mem_clk_max; } +static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, + struct kfd_topology_device *target_gpu_dev, + struct kfd_iolink_properties *link) +{ + /* xgmi always supports atomics between links. */ + if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI) + return; + + /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */ + if (target_gpu_dev) { + uint32_t cap; + + pcie_capability_read_dword(target_gpu_dev->gpu->pdev, + PCI_EXP_DEVCAP2, &cap); + + if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | + PCI_EXP_DEVCAP2_ATOMIC_COMP64))) + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + /* set gpu (dev) flags. */ + } else { + if (!dev->gpu->pci_atomic_requested || + dev->gpu->device_info->asic_family == + CHIP_HAWAII) + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + } +} + +static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev, + struct kfd_iolink_properties *outbound_link, + struct kfd_iolink_properties *inbound_link) +{ + /* CPU -> GPU with PCIe */ + if (!to_dev->gpu && + inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) + inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT; + + if (to_dev->gpu) { + /* GPU <-> GPU with PCIe and + * Vega20 with XGMI + */ + if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS || + (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI && + to_dev->gpu->device_info->asic_family == CHIP_VEGA20)) { + outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT; + inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT; + } + } +} + static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) { - struct kfd_iolink_properties *link, *cpu_link; - struct kfd_topology_device *cpu_dev; - uint32_t cap; - uint32_t cpu_flag = CRAT_IOLINK_FLAGS_ENABLED; - uint32_t flag = CRAT_IOLINK_FLAGS_ENABLED; + struct kfd_iolink_properties *link, *inbound_link; + struct kfd_topology_device *peer_dev; if (!dev || !dev->gpu) return; - pcie_capability_read_dword(dev->gpu->pdev, - PCI_EXP_DEVCAP2, &cap); - - if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | - PCI_EXP_DEVCAP2_ATOMIC_COMP64))) - cpu_flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | - CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; - - if (!dev->gpu->pci_atomic_requested || - dev->gpu->device_info->asic_family == CHIP_HAWAII) - flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | - CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; - /* GPU only creates direct links so apply flags setting to all */ list_for_each_entry(link, &dev->io_link_props, list) { - link->flags = flag; - cpu_dev = kfd_topology_device_by_proximity_domain( + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( link->node_to); - if (cpu_dev) { - list_for_each_entry(cpu_link, - &cpu_dev->io_link_props, list) - if (cpu_link->node_to == link->node_from) - cpu_link->flags = cpu_flag; + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->io_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } } @@ -1378,6 +1422,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu) case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 << HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) & HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK); @@ -1410,15 +1456,18 @@ int kfd_topology_add_device(struct kfd_dev *gpu) adev = (struct amdgpu_device *)(dev->gpu->kgd); /* kfd only concerns sram ecc on GFX and HBM ecc on UMC */ dev->node_props.capability |= - ((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ? + ((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ? HSA_CAP_SRAM_EDCSUPPORTED : 0; - dev->node_props.capability |= ((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ? + dev->node_props.capability |= ((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ? HSA_CAP_MEM_EDCSUPPORTED : 0; if (adev->asic_type != CHIP_VEGA10) - dev->node_props.capability |= (adev->ras_features != 0) ? + dev->node_props.capability |= (adev->ras_enabled != 0) ? HSA_CAP_RASEVENTNOTIFY : 0; + if (KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) + dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED; + kfd_debug_print_topology(); if (!res) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index b8b68087bd7a..8b48c6692007 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -53,8 +53,9 @@ #define HSA_CAP_ASIC_REVISION_MASK 0x03c00000 #define HSA_CAP_ASIC_REVISION_SHIFT 22 #define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000 - -#define HSA_CAP_RESERVED 0xf80f8000 +#define HSA_CAP_SVMAPI_SUPPORTED 0x08000000 +#define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000 +#define HSA_CAP_RESERVED 0xe00f8000 struct kfd_node_properties { uint64_t hive_id; @@ -98,9 +99,9 @@ struct kfd_node_properties { #define HSA_MEM_HEAP_TYPE_GPU_LDS 4 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5 -#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001 -#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 -#define HSA_MEM_FLAGS_RESERVED 0xfffffffc +#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001 +#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 +#define HSA_MEM_FLAGS_RESERVED 0xfffffffc struct kfd_mem_properties { struct list_head list; diff --git a/drivers/gpu/drm/amd/amdkfd/soc15_int.h b/drivers/gpu/drm/amd/amdkfd/soc15_int.h index 0bc0b25cb410..daf3c44547d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/soc15_int.h +++ b/drivers/gpu/drm/amd/amdkfd/soc15_int.h @@ -30,6 +30,7 @@ #define SOC15_INTSRC_SQ_INTERRUPT_MSG 239 #define SOC15_INTSRC_VMC_FAULT 0 #define SOC15_INTSRC_SDMA_TRAP 224 +#define SOC15_INTSRC_SDMA_ECC 220 #define SOC15_CLIENT_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) & 0xff) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index 9a3b7bf8ab0b..91fb72c96545 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -28,7 +28,7 @@ AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o ifneq ($(CONFIG_DRM_AMD_DC),) -AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o +AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o amdgpu_dm_psr.o endif ifdef CONFIG_DRM_AMD_DC_HDCP diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 652cc1a0e450..b5b5ccf0ed71 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -28,6 +28,7 @@ #include "dm_services_types.h" #include "dc.h" +#include "dc_link_dp.h" #include "dc/inc/core_types.h" #include "dal_asic_id.h" #include "dmub/dmub_srv.h" @@ -35,6 +36,7 @@ #include "dc/inc/hw/abm.h" #include "dc/dc_dmub_srv.h" #include "dc/dc_edid_parser.h" +#include "dc/dc_stat.h" #include "amdgpu_dm_trace.h" #include "vid.h" @@ -56,9 +58,11 @@ #if defined(CONFIG_DEBUG_FS) #include "amdgpu_dm_debugfs.h" #endif +#include "amdgpu_dm_psr.h" #include "ivsrcid/ivsrcid_vislands30.h" +#include "i2caux_interface.h" #include #include #include @@ -104,6 +108,10 @@ MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); +#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); +#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); @@ -204,12 +212,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, static void handle_cursor_update(struct drm_plane *plane, struct drm_plane_state *old_plane_state); -static void amdgpu_dm_set_psr_caps(struct dc_link *link); -static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); -static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); -static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); -static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); - static const struct drm_format_info * amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd); @@ -310,10 +312,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev, struct drm_crtc *crtc; struct amdgpu_crtc *amdgpu_crtc; - if (otg_inst == -1) { - WARN_ON(1); + if (WARN_ON(otg_inst == -1)) return adev->mode_info.crtcs[0]; - } list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { amdgpu_crtc = to_amdgpu_crtc(crtc); @@ -392,8 +392,7 @@ static void dm_pflip_high_irq(void *interrupt_params) e = amdgpu_crtc->event; amdgpu_crtc->event = NULL; - if (!e) - WARN_ON(1); + WARN_ON(!e); vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); @@ -596,14 +595,14 @@ static void dm_crtc_high_irq(void *interrupt_params) } #if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) /** * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for * DCN generation ASICs - * @interrupt params - interrupt parameters + * @interrupt_params: interrupt parameters * * Used to set crc window/read out crc value at vertical line 0 position */ -#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) { struct common_irq_params *irq_params = interrupt_params; @@ -618,6 +617,58 @@ static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); } #endif + +/** + * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt + * @interrupt_params: used for determining the Outbox instance + * + * Handles the Outbox Interrupt + * event handler. + */ +#define DMUB_TRACE_MAX_READ 64 +static void dm_dmub_outbox1_low_irq(void *interrupt_params) +{ + struct dmub_notification notify; + struct common_irq_params *irq_params = interrupt_params; + struct amdgpu_device *adev = irq_params->adev; + struct amdgpu_display_manager *dm = &adev->dm; + struct dmcub_trace_buf_entry entry = { 0 }; + uint32_t count = 0; + + if (dc_enable_dmub_notifications(adev->dm.dc)) { + if (irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { + do { + dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); + } while (notify.pending_notification); + + if (adev->dm.dmub_notify) + memcpy(adev->dm.dmub_notify, ¬ify, sizeof(struct dmub_notification)); + if (notify.type == DMUB_NOTIFICATION_AUX_REPLY) + complete(&adev->dm.dmub_aux_transfer_done); + // TODO : HPD Implementation + + } else { + DRM_ERROR("DM: Failed to receive correct outbox IRQ !"); + } + } + + + do { + if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { + trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, + entry.param0, entry.param1); + + DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", + entry.trace_code, entry.tick_count, entry.param0, entry.param1); + } else + break; + + count++; + + } while (count <= DMUB_TRACE_MAX_READ); + + ASSERT(count <= DMUB_TRACE_MAX_READ); +} #endif static int dm_set_clockgating_state(void *handle, @@ -939,32 +990,6 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) } #if defined(CONFIG_DRM_AMD_DC_DCN) -#define DMUB_TRACE_MAX_READ 64 -static void dm_dmub_trace_high_irq(void *interrupt_params) -{ - struct common_irq_params *irq_params = interrupt_params; - struct amdgpu_device *adev = irq_params->adev; - struct amdgpu_display_manager *dm = &adev->dm; - struct dmcub_trace_buf_entry entry = { 0 }; - uint32_t count = 0; - - do { - if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { - trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, - entry.param0, entry.param1); - - DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", - entry.trace_code, entry.tick_count, entry.param0, entry.param1); - } else - break; - - count++; - - } while (count <= DMUB_TRACE_MAX_READ); - - ASSERT(count <= DMUB_TRACE_MAX_READ); -} - static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) { uint64_t pt_base; @@ -1118,11 +1143,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) init_data.flags.disable_dmcu = true; break; -#if defined(CONFIG_DRM_AMD_DC_DCN) case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: init_data.flags.gpu_vm_support = true; break; -#endif default: break; } @@ -1221,6 +1245,16 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); #endif + if (dc_enable_dmub_notifications(adev->dm.dc)) { + init_completion(&adev->dm.dmub_aux_transfer_done); + adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); + if (!adev->dm.dmub_notify) { + DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); + goto error; + } + amdgpu_dm_outbox_init(adev); + } + if (amdgpu_dm_initialize_drm_device(adev)) { DRM_ERROR( "amdgpu: failed to initialize sw for display support.\n"); @@ -1252,6 +1286,15 @@ error: return -EINVAL; } +static int amdgpu_dm_early_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_dm_audio_fini(adev); + + return 0; +} + static void amdgpu_dm_fini(struct amdgpu_device *adev) { int i; @@ -1260,8 +1303,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); } - amdgpu_dm_audio_fini(adev); - amdgpu_dm_destroy_drm_device(&adev->dm); #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) @@ -1289,9 +1330,11 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) } #endif - if (adev->dm.dc->ctx->dmub_srv) { - dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); - adev->dm.dc->ctx->dmub_srv = NULL; + dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); + + if (dc_enable_dmub_notifications(adev->dm.dc)) { + kfree(adev->dm.dmub_notify); + adev->dm.dmub_notify = NULL; } if (adev->dm.dmub_bo) @@ -1358,7 +1401,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: return 0; case CHIP_NAVI12: fw_name_dmcu = FIRMWARE_NAVI12_DMCU; @@ -1473,6 +1518,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) dmub_asic = DMUB_ASIC_DCN302; fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; break; + case CHIP_BEIGE_GOBY: + dmub_asic = DMUB_ASIC_DCN303; + fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; + break; + case CHIP_YELLOW_CARP: + dmub_asic = DMUB_ASIC_DCN31; + fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; + break; default: /* ASIC doesn't support DMUB. */ @@ -1659,7 +1712,6 @@ static int dm_late_init(void *handle) unsigned int linear_lut[16]; int i; struct dmcu *dmcu = NULL; - bool ret = true; dmcu = adev->dm.dc->res_pool->dmcu; @@ -1676,18 +1728,23 @@ static int dm_late_init(void *handle) * 0xFFFF x 0.01 = 0x28F */ params.min_abm_backlight = 0x28F; - /* In the case where abm is implemented on dmcub, - * dmcu object will be null. - * ABM 2.4 and up are implemented on dmcub. - */ - if (dmcu) - ret = dmcu_load_iram(dmcu, params); - else if (adev->dm.dc->ctx->dmub_srv) - ret = dmub_init_abm_config(adev->dm.dc->res_pool, params); + * dmcu object will be null. + * ABM 2.4 and up are implemented on dmcub. + */ + if (dmcu) { + if (!dmcu_load_iram(dmcu, params)) + return -EINVAL; + } else if (adev->dm.dc->ctx->dmub_srv) { + struct dc_link *edp_links[MAX_NUM_EDP]; + int edp_num; - if (!ret) - return -EINVAL; + get_edp_links(adev->dm.dc, edp_links, &edp_num); + for (i = 0; i < edp_num; i++) { + if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) + return -EINVAL; + } + } return detect_mst_link_for_all_connectors(adev_to_drm(adev)); } @@ -1945,9 +2002,6 @@ static int dm_suspend(void *handle) return ret; } -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - amdgpu_dm_crtc_secure_display_suspend(adev); -#endif WARN_ON(adev->dm.cached_state); adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); @@ -2166,6 +2220,15 @@ static int dm_resume(void *handle) = 0xffffffff; } } +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* + * Resource allocation happens for link encoders for newer ASIC in + * dc_validate_global_state, so we need to revalidate it. + * + * This shouldn't fail (it passed once before), so warn if it does. + */ + WARN_ON(dc_validate_global_state(dm->dc, dc_state, false) != DC_OK); +#endif WARN_ON(!dc_commit_state(dm->dc, dc_state)); @@ -2271,10 +2334,6 @@ static int dm_resume(void *handle) dm->cached_state = NULL; -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - amdgpu_dm_crtc_secure_display_resume(adev); -#endif - amdgpu_dm_irq_resume_late(adev); amdgpu_dm_smu_write_watermarks_table(adev); @@ -2298,6 +2357,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = { .late_init = dm_late_init, .sw_init = dm_sw_init, .sw_fini = dm_sw_fini, + .early_fini = amdgpu_dm_early_fini, .hw_init = dm_hw_init, .hw_fini = dm_hw_fini, .suspend = dm_suspend, @@ -2696,6 +2756,7 @@ static void handle_hpd_rx_irq(void *param) enum dc_connection_type new_connection_type = dc_connection_none; struct amdgpu_device *adev = drm_to_adev(dev); union hpd_irq_data hpd_irq_data; + bool lock_flag = 0; memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); @@ -2708,8 +2769,7 @@ static void handle_hpd_rx_irq(void *param) * conflict, after implement i2c helper, this mutex should be * retired. */ - if (dc_link->type != dc_connection_mst_branch) - mutex_lock(&aconnector->hpd_lock); + mutex_lock(&aconnector->hpd_lock); read_hpd_rx_irq_data(dc_link, &hpd_irq_data); @@ -2726,13 +2786,28 @@ static void handle_hpd_rx_irq(void *param) } } - mutex_lock(&adev->dm.dc_lock); + /* + * TODO: We need the lock to avoid touching DC state while it's being + * modified during automated compliance testing, or when link loss + * happens. While this should be split into subhandlers and proper + * interfaces to avoid having to conditionally lock like this in the + * outer layer, we need this workaround temporarily to allow MST + * lightup in some scenarios to avoid timeout. + */ + if (!amdgpu_in_reset(adev) && + (hpd_rx_irq_check_link_loss_status(dc_link, &hpd_irq_data) || + hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST)) { + mutex_lock(&adev->dm.dc_lock); + lock_flag = 1; + } + #ifdef CONFIG_DRM_AMD_DC_HDCP result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL); #else result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL); #endif - mutex_unlock(&adev->dm.dc_lock); + if (!amdgpu_in_reset(adev) && lock_flag) + mutex_unlock(&adev->dm.dc_lock); out: if (result && !is_mst_root_connector) { @@ -2776,10 +2851,10 @@ out: } #endif - if (dc_link->type != dc_connection_mst_branch) { + if (dc_link->type != dc_connection_mst_branch) drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); - mutex_unlock(&aconnector->hpd_lock); - } + + mutex_unlock(&aconnector->hpd_lock); } static void register_hpd_handlers(struct amdgpu_device *adev) @@ -3151,28 +3226,6 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) } - if (dc->ctx->dmub_srv) { - i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT; - r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->dmub_trace_irq); - - if (r) { - DRM_ERROR("Failed to add dmub trace irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); - - c_irq_params = &adev->dm.dmub_trace_params[0]; - - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; - - amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_dmub_trace_high_irq, c_irq_params); - } - /* HPD */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, &adev->hpd_irq); @@ -3185,6 +3238,41 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) return 0; } +/* Register Outbox IRQ sources and initialize IRQ callbacks */ +static int register_outbox_irq_handlers(struct amdgpu_device *adev) +{ + struct dc *dc = adev->dm.dc; + struct common_irq_params *c_irq_params; + struct dc_interrupt_params int_params = {0}; + int r, i; + + int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; + int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; + + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, + &adev->dmub_outbox_irq); + if (r) { + DRM_ERROR("Failed to add outbox irq id!\n"); + return r; + } + + if (dc->ctx->dmub_srv) { + i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; + int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.dmub_outbox_params[0]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_dmub_outbox1_low_irq, c_irq_params); + } + + return 0; +} #endif /* @@ -3342,7 +3430,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) if (dm->backlight_caps.caps_valid) return; - amdgpu_acpi_get_backlight_caps(dm->adev, &caps); + amdgpu_acpi_get_backlight_caps(&caps); if (caps.caps_valid) { dm->backlight_caps.caps_valid = true; if (caps.aux_support) @@ -3410,56 +3498,88 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap max - min); } -static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) +static int amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, + u32 user_brightness) { - struct amdgpu_display_manager *dm = bl_get_data(bd); struct amdgpu_dm_backlight_caps caps; - struct dc_link *link = NULL; - u32 brightness; + struct dc_link *link[AMDGPU_DM_MAX_NUM_EDP]; + u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; bool rc; + int i; amdgpu_dm_update_backlight_caps(dm); caps = dm->backlight_caps; - link = (struct dc_link *)dm->backlight_link; + for (i = 0; i < dm->num_of_edps; i++) { + dm->brightness[i] = user_brightness; + brightness[i] = convert_brightness_from_user(&caps, dm->brightness[i]); + link[i] = (struct dc_link *)dm->backlight_link[i]; + } - brightness = convert_brightness_from_user(&caps, bd->props.brightness); - // Change brightness based on AUX property - if (caps.aux_support) - rc = dc_link_set_backlight_level_nits(link, true, brightness, - AUX_BL_DEFAULT_TRANSITION_TIME_MS); - else - rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0); + /* Change brightness based on AUX property */ + if (caps.aux_support) { + for (i = 0; i < dm->num_of_edps; i++) { + rc = dc_link_set_backlight_level_nits(link[i], true, brightness[i], + AUX_BL_DEFAULT_TRANSITION_TIME_MS); + if (!rc) { + DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", i); + break; + } + } + } else { + for (i = 0; i < dm->num_of_edps; i++) { + rc = dc_link_set_backlight_level(dm->backlight_link[i], brightness[i], 0); + if (!rc) { + DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", i); + break; + } + } + } return rc ? 0 : 1; } -static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) +static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) { struct amdgpu_display_manager *dm = bl_get_data(bd); + + amdgpu_dm_backlight_set_level(dm, bd->props.brightness); + + return 0; +} + +static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm) +{ struct amdgpu_dm_backlight_caps caps; amdgpu_dm_update_backlight_caps(dm); caps = dm->backlight_caps; if (caps.aux_support) { - struct dc_link *link = (struct dc_link *)dm->backlight_link; + struct dc_link *link = (struct dc_link *)dm->backlight_link[0]; u32 avg, peak; bool rc; rc = dc_link_get_backlight_level_nits(link, &avg, &peak); if (!rc) - return bd->props.brightness; + return dm->brightness[0]; return convert_brightness_to_user(&caps, avg); } else { - int ret = dc_link_get_backlight_level(dm->backlight_link); + int ret = dc_link_get_backlight_level(dm->backlight_link[0]); if (ret == DC_ERROR_UNEXPECTED) - return bd->props.brightness; + return dm->brightness[0]; return convert_brightness_to_user(&caps, ret); } } +static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) +{ + struct amdgpu_display_manager *dm = bl_get_data(bd); + + return amdgpu_dm_backlight_get_level(dm); +} + static const struct backlight_ops amdgpu_dm_backlight_ops = { .options = BL_CORE_SUSPENDRESUME, .get_brightness = amdgpu_dm_backlight_get_brightness, @@ -3471,8 +3591,11 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) { char bl_name[16]; struct backlight_properties props = { 0 }; + int i; amdgpu_dm_update_backlight_caps(dm); + for (i = 0; i < dm->num_of_edps; i++) + dm->brightness[i] = AMDGPU_MAX_BL_LEVEL; props.max_brightness = AMDGPU_MAX_BL_LEVEL; props.brightness = AMDGPU_MAX_BL_LEVEL; @@ -3549,10 +3672,13 @@ static void register_backlight_device(struct amdgpu_display_manager *dm, * DM initialization because not having a backlight control * is better then a black screen. */ - amdgpu_dm_register_backlight_device(dm); + if (!dm->backlight_dev) + amdgpu_dm_register_backlight_device(dm); - if (dm->backlight_dev) - dm->backlight_link = link; + if (dm->backlight_dev) { + dm->backlight_link[dm->num_of_edps] = link; + dm->num_of_edps++; + } } #endif } @@ -3643,6 +3769,23 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail; } +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* Use Outbox interrupt */ + switch (adev->asic_type) { + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_YELLOW_CARP: + case CHIP_RENOIR: + if (register_outbox_irq_handlers(dm->adev)) { + DRM_ERROR("DM: Failed to initialize IRQ\n"); + goto fail; + } + break; + default: + DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type); + } +#endif + /* loops over all connectors on the board */ for (i = 0; i < link_cnt; i++) { struct dc_link *link = NULL; @@ -3734,7 +3877,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: case CHIP_VANGOGH: + case CHIP_YELLOW_CARP: if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); goto fail; @@ -3756,7 +3901,6 @@ fail: static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { - drm_mode_config_cleanup(dm->ddev); drm_atomic_private_obj_fini(&dm->atomic_obj); return; } @@ -3907,12 +4051,22 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; + case CHIP_YELLOW_CARP: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; + break; case CHIP_NAVI14: case CHIP_DIMGREY_CAVEFISH: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; break; + case CHIP_BEIGE_GOBY: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 2; + adev->mode_info.num_dig = 2; + break; #endif default: DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); @@ -4138,6 +4292,8 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, if (adev->asic_type == CHIP_SIENNA_CICHLID || adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH || + adev->asic_type == CHIP_BEIGE_GOBY || + adev->asic_type == CHIP_YELLOW_CARP || adev->asic_type == CHIP_VANGOGH) tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; } @@ -4557,6 +4713,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u break; case AMDGPU_FAMILY_NV: case AMDGPU_FAMILY_VGH: + case AMDGPU_FAMILY_YC: if (adev->asic_type >= CHIP_SIENNA_CICHLID) add_gfx10_3_modifiers(adev, mods, &size, &capacity); else @@ -4828,6 +4985,14 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; break; + case DRM_FORMAT_XRGB16161616: + case DRM_FORMAT_ARGB16161616: + plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; + break; + case DRM_FORMAT_XBGR16161616: + case DRM_FORMAT_ABGR16161616: + plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; + break; default: DRM_ERROR( "Unsupported screen format %p4cc\n", @@ -5404,6 +5569,93 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) } } +#if defined(CONFIG_DRM_AMD_DC_DCN) +static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, + struct dc_sink *sink, struct dc_stream_state *stream, + struct dsc_dec_dpcd_caps *dsc_caps) +{ + stream->timing.flags.DSC = 0; + + if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { + dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, + aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, + aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, + dsc_caps); + } +} + +static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, + struct dc_sink *sink, struct dc_stream_state *stream, + struct dsc_dec_dpcd_caps *dsc_caps) +{ + struct drm_connector *drm_connector = &aconnector->base; + uint32_t link_bandwidth_kbps; + + link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, + dc_link_get_link_cap(aconnector->dc_link)); + /* Set DSC policy according to dsc_clock_en */ + dc_dsc_policy_set_enable_dsc_when_not_needed( + aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); + + if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { + + if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], + dsc_caps, + aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, + 0, + link_bandwidth_kbps, + &stream->timing, + &stream->timing.dsc_cfg)) { + stream->timing.flags.DSC = 1; + DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); + } + } + + /* Overwrite the stream flag if DSC is enabled through debugfs */ + if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) + stream->timing.flags.DSC = 1; + + if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) + stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; + + if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) + stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; + + if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) + stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; +} +#endif + +/** + * DOC: FreeSync Video + * + * When a userspace application wants to play a video, the content follows a + * standard format definition that usually specifies the FPS for that format. + * The below list illustrates some video format and the expected FPS, + * respectively: + * + * - TV/NTSC (23.976 FPS) + * - Cinema (24 FPS) + * - TV/PAL (25 FPS) + * - TV/NTSC (29.97 FPS) + * - TV/NTSC (30 FPS) + * - Cinema HFR (48 FPS) + * - TV/PAL (50 FPS) + * - Commonly used (60 FPS) + * - Multiples of 24 (48,72,96 FPS) + * + * The list of standards video format is not huge and can be added to the + * connector modeset list beforehand. With that, userspace can leverage + * FreeSync to extends the front porch in order to attain the target refresh + * rate. Such a switch will happen seamlessly, without screen blanking or + * reprogramming of the output in any other way. If the userspace requests a + * modesetting change compatible with FreeSync modes that only differ in the + * refresh rate, DC will skip the full update and avoid blink during the + * transition. For example, the video player can change the modesetting from + * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without + * causing any display blink. This same concept can be applied to a mode + * setting change. + */ static struct drm_display_mode * get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, bool use_probed_modes) @@ -5506,7 +5758,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, int preferred_refresh = 0; #if defined(CONFIG_DRM_AMD_DC_DCN) struct dsc_dec_dpcd_caps dsc_caps; - uint32_t link_bandwidth_kbps; #endif struct dc_sink *sink = NULL; @@ -5596,45 +5847,12 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, stream, &mode, &aconnector->base, con_state, old_stream, requested_bpc); - stream->timing.flags.DSC = 0; - - if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { #if defined(CONFIG_DRM_AMD_DC_DCN) - dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, - aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, - aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, - &dsc_caps); - link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, - dc_link_get_link_cap(aconnector->dc_link)); - - if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) { - /* Set DSC policy according to dsc_clock_en */ - dc_dsc_policy_set_enable_dsc_when_not_needed( - aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); - - if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], - &dsc_caps, - aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, - 0, - link_bandwidth_kbps, - &stream->timing, - &stream->timing.dsc_cfg)) - stream->timing.flags.DSC = 1; - /* Overwrite the stream flag if DSC is enabled through debugfs */ - if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) - stream->timing.flags.DSC = 1; - - if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) - stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; - - if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) - stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; - - if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) - stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; - } + /* SST DSC determination policy */ + update_dsc_caps(aconnector, sink, stream, &dsc_caps); + if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) + apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); #endif - } update_stream_scaling_settings(&mode, dm_state, stream); @@ -5662,6 +5880,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, stream->use_vsc_sdp_for_colorimetry = true; } mod_build_vsc_infopacket(stream, &stream->vsc_infopacket); + aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; + } finish: dc_sink_release(sink); @@ -6308,25 +6528,6 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, return 0; } -static bool -is_hdr_metadata_different(const struct drm_connector_state *old_state, - const struct drm_connector_state *new_state) -{ - struct drm_property_blob *old_blob = old_state->hdr_output_metadata; - struct drm_property_blob *new_blob = new_state->hdr_output_metadata; - - if (old_blob != new_blob) { - if (old_blob && new_blob && - old_blob->length == new_blob->length) - return memcmp(old_blob->data, new_blob->data, - old_blob->length); - - return true; - } - - return false; -} - static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, struct drm_atomic_state *state) @@ -6344,7 +6545,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; - if (is_hdr_metadata_different(old_con_state, new_con_state)) { + if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { struct dc_info_packet hdr_infopacket; ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); @@ -6452,9 +6653,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, dm_update_crtc_active_planes(crtc, crtc_state); - if (unlikely(!dm_crtc_state->stream && - modeset_required(crtc_state, NULL, dm_crtc_state->stream))) { - WARN_ON(1); + if (WARN_ON(unlikely(!dm_crtc_state->stream && + modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { return ret; } @@ -6579,13 +6779,13 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, { struct dc_stream_state *stream = NULL; struct drm_connector *connector; - struct drm_connector_state *new_con_state, *old_con_state; + struct drm_connector_state *new_con_state; struct amdgpu_dm_connector *aconnector; struct dm_connector_state *dm_conn_state; int i, j, clock, bpp; int vcpi, pbn_div, pbn = 0; - for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { + for_each_new_connector_in_state(state, connector, new_con_state, i) { aconnector = to_amdgpu_dm_connector(connector); @@ -6953,6 +7153,10 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XRGB16161616, + DRM_FORMAT_XBGR16161616, + DRM_FORMAT_ARGB16161616, + DRM_FORMAT_ABGR16161616, DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, @@ -7531,9 +7735,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { - drm_object_attach_property( - &aconnector->base.base, - dm->ddev->mode_config.hdr_output_metadata_property, 0); + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); if (!aconnector->mst_port) drm_connector_attach_vrr_capable_property(&aconnector->base); @@ -8185,15 +8387,14 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) { struct drm_plane *plane; - struct drm_plane_state *old_plane_state, *new_plane_state; + struct drm_plane_state *old_plane_state; int i; /* * TODO: Make this per-stream so we don't issue redundant updates for * commits with multiple streams. */ - for_each_oldnew_plane_in_state(state, plane, old_plane_state, - new_plane_state, i) + for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) handle_cursor_update(plane, old_plane_state); } @@ -8297,9 +8498,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * deadlock during GPU reset when this fence will not signal * but we hold reservation lock for the BO. */ - r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, - false, - msecs_to_jiffies(5000)); + r = dma_resv_wait_timeout(abo->tbo.base.resv, true, false, + msecs_to_jiffies(5000)); if (unlikely(r <= 0)) DRM_ERROR("Waiting for fences timed out!"); @@ -8495,7 +8695,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) && acrtc_state->stream->link->psr_settings.psr_feature_enabled && !acrtc_state->stream->link->psr_settings.psr_allow_active) { - amdgpu_dm_psr_enable(acrtc_state->stream); + struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) + acrtc_state->stream->dm_stream_context; + + if (aconn->psr_skip_count > 0) + aconn->psr_skip_count--; + else + amdgpu_dm_psr_enable(acrtc_state->stream); } mutex_unlock(&dm->dc_lock); @@ -8838,7 +9044,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) dm_old_crtc_state->abm_level; hdr_changed = - is_hdr_metadata_different(old_con_state, new_con_state); + !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); if (!scaling_changed && !abm_changed && !hdr_changed) continue; @@ -8864,7 +9070,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } status = dc_stream_get_status(dm_new_crtc_state->stream); - WARN_ON(!status); + + if (WARN_ON(!status)) + continue; + WARN_ON(!status->plane_count); /* @@ -8914,6 +9123,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) #ifdef CONFIG_DEBUG_FS bool configure_crc = false; enum amdgpu_dm_pipe_crc_source cur_crc_src; +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk; +#endif + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); #endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); @@ -8930,21 +9145,26 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * settings for the stream. */ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); - cur_crc_src = acrtc->dm_irq_params.crc_src; - spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { configure_crc = true; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) - if (amdgpu_dm_crc_window_is_activated(crtc)) - configure_crc = false; + if (amdgpu_dm_crc_window_is_activated(crtc)) { + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + acrtc->dm_irq_params.crc_window.update_win = true; + acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2; + spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); + crc_rd_wrk->crtc = crtc; + spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + } #endif } if (configure_crc) - amdgpu_dm_crtc_configure_crc_source( - crtc, dm_new_crtc_state, cur_crc_src); + if (amdgpu_dm_crtc_configure_crc_source( + crtc, dm_new_crtc_state, cur_crc_src)) + DRM_DEBUG_DRIVER("Failed to configure crc source"); #endif } } @@ -8965,6 +9185,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ + defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + /* restore the backlight level */ + if (dm->backlight_dev) + amdgpu_dm_backlight_set_level(dm, dm->brightness[0]); +#endif /* * send vblank event on all events not handled in flip and * mark consumed event for drm_atomic_helper_commit_hw_done @@ -9464,7 +9690,8 @@ skip_modeset: BUG_ON(dm_new_crtc_state->stream == NULL); /* Scaling or underscan settings */ - if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) + if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || + drm_atomic_crtc_needs_modeset(new_crtc_state)) update_stream_scaling_settings( &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); @@ -9890,11 +10117,11 @@ static int validate_overlay(struct drm_atomic_state *state) { int i; struct drm_plane *plane; - struct drm_plane_state *old_plane_state, *new_plane_state; + struct drm_plane_state *new_plane_state; struct drm_plane_state *primary_state, *cursor_state, *overlay_state = NULL; /* Check if primary plane is contained inside overlay */ - for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { + for_each_new_plane_in_state_reverse(state, plane, new_plane_state, i) { if (plane->type == DRM_PLANE_TYPE_OVERLAY) { if (drm_atomic_plane_disabling(plane->state, new_plane_state)) return 0; @@ -10031,6 +10258,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dm_old_crtc_state->dsc_force_changed == false) continue; + ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); + if (ret) + goto fail; + if (!new_crtc_state->enable) continue; @@ -10511,136 +10742,6 @@ update: freesync_capable); } -static void amdgpu_dm_set_psr_caps(struct dc_link *link) -{ - uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; - - if (!(link->connector_signal & SIGNAL_TYPE_EDP)) - return; - if (link->type == dc_connection_none) - return; - if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, - dpcd_data, sizeof(dpcd_data))) { - link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; - - if (dpcd_data[0] == 0) { - link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - link->psr_settings.psr_feature_enabled = false; - } else { - link->psr_settings.psr_version = DC_PSR_VERSION_1; - link->psr_settings.psr_feature_enabled = true; - } - - DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled); - } -} - -/* - * amdgpu_dm_link_setup_psr() - configure psr link - * @stream: stream state - * - * Return: true if success - */ -static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) -{ - struct dc_link *link = NULL; - struct psr_config psr_config = {0}; - struct psr_context psr_context = {0}; - bool ret = false; - - if (stream == NULL) - return false; - - link = stream->link; - - psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version; - - if (psr_config.psr_version > 0) { - psr_config.psr_exit_link_training_required = 0x1; - psr_config.psr_frame_capture_indication_req = 0; - psr_config.psr_rfb_setup_time = 0x37; - psr_config.psr_sdp_transmit_line_num_deadline = 0x20; - psr_config.allow_smu_optimizations = 0x0; - - ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); - - } - DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); - - return ret; -} - -/* - * amdgpu_dm_psr_enable() - enable psr f/w - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) -{ - struct dc_link *link = stream->link; - unsigned int vsync_rate_hz = 0; - struct dc_static_screen_params params = {0}; - /* Calculate number of static frames before generating interrupt to - * enter PSR. - */ - // Init fail safe of 2 frames static - unsigned int num_frames_static = 2; - - DRM_DEBUG_DRIVER("Enabling psr...\n"); - - vsync_rate_hz = div64_u64(div64_u64(( - stream->timing.pix_clk_100hz * 100), - stream->timing.v_total), - stream->timing.h_total); - - /* Round up - * Calculate number of frames such that at least 30 ms of time has - * passed. - */ - if (vsync_rate_hz != 0) { - unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; - num_frames_static = (30000 / frame_time_microsec) + 1; - } - - params.triggers.cursor_update = true; - params.triggers.overlay_update = true; - params.triggers.surface_update = true; - params.num_frames = num_frames_static; - - dc_stream_set_static_screen_params(link->ctx->dc, - &stream, 1, - ¶ms); - - return dc_link_set_psr_allow_active(link, true, false, false); -} - -/* - * amdgpu_dm_psr_disable() - disable psr f/w - * @stream: stream state - * - * Return: true if success - */ -static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) -{ - - DRM_DEBUG_DRIVER("Disabling psr...\n"); - - return dc_link_set_psr_allow_active(stream->link, false, true, false); -} - -/* - * amdgpu_dm_psr_disable() - disable psr f/w - * if psr is enabled on any stream - * - * Return: true if success - */ -static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) -{ - DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); - return dc_set_psr_allow_active(dm->dc, false); -} - void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -10697,3 +10798,30 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, return value; } + +int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex, + struct aux_payload *payload, enum aux_return_code_type *operation_result) +{ + struct amdgpu_device *adev = ctx->driver_context; + int ret = 0; + + dc_process_dmub_aux_transfer_async(ctx->dc, linkIndex, payload); + ret = wait_for_completion_interruptible_timeout(&adev->dm.dmub_aux_transfer_done, 10*HZ); + if (ret == 0) { + *operation_result = AUX_RET_ERROR_TIMEOUT; + return -1; + } + *operation_result = (enum aux_return_code_type)adev->dm.dmub_notify->result; + + if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) { + (*payload->reply) = adev->dm.dmub_notify->aux_reply.command; + + // For read case, Copy data to payload + if (!payload->write && adev->dm.dmub_notify->aux_reply.length && + (*payload->reply == AUX_TRANSACTION_REPLY_AUX_ACK)) + memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data, + adev->dm.dmub_notify->aux_reply.length); + } + + return adev->dm.dmub_notify->aux_reply.length; +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b2f2ccfc20bb..9522d4ca299e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -46,6 +46,7 @@ #define AMDGPU_DM_MAX_CRTC 6 +#define AMDGPU_DM_MAX_NUM_EDP 2 /* #include "include/amdgpu_dal_power_if.h" #include "amdgpu_dm_irq.h" @@ -54,6 +55,8 @@ #include "irq_types.h" #include "signal_types.h" #include "amdgpu_dm_crc.h" +struct aux_payload; +enum aux_return_code_type; /* Forward declarations */ struct amdgpu_device; @@ -62,6 +65,7 @@ struct dc; struct amdgpu_bo; struct dmub_srv; struct dc_plane_state; +struct dmub_notification; struct common_irq_params { struct amdgpu_device *adev; @@ -135,6 +139,10 @@ struct amdgpu_dm_backlight_caps { /** * struct dal_allocation - Tracks mapped FB memory for SMU communication + * @list: list of dal allocations + * @bo: GPU buffer object + * @cpu_ptr: CPU virtual address of the GPU buffer object + * @gpu_addr: GPU virtual address of the GPU buffer object */ struct dal_allocation { struct list_head list; @@ -164,6 +172,7 @@ struct dal_allocation { * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info * @force_timing_sync: set via debugfs. When set, indicates that all connected * displays will be forced to synchronize. + * @dmcub_trace_event_en: enable dmcub trace events */ struct amdgpu_display_manager { @@ -178,6 +187,8 @@ struct amdgpu_display_manager { */ struct dmub_srv *dmub_srv; + struct dmub_notification *dmub_notify; + /** * @dmub_fb_info: * @@ -349,11 +360,17 @@ struct amdgpu_display_manager { struct common_irq_params dmub_trace_params[1]; + struct common_irq_params + dmub_outbox_params[1]; + spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev; - const struct dc_link *backlight_link; + const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; + + uint8_t num_of_edps; + struct amdgpu_dm_backlight_caps backlight_caps; struct mod_freesync *freesync_module; @@ -418,6 +435,14 @@ struct amdgpu_display_manager { * DAL fb memory allocation list, for communication with SMU. */ struct list_head da_list; + struct completion dmub_aux_transfer_done; + + /** + * @brightness: + * + * cached backlight values. + */ + u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; }; enum dsc_clock_force_state { @@ -431,6 +456,7 @@ struct dsc_preferred_settings { uint32_t dsc_num_slices_v; uint32_t dsc_num_slices_h; uint32_t dsc_bits_per_pixel; + bool dsc_force_disable_passthrough; }; struct amdgpu_dm_connector { @@ -483,6 +509,8 @@ struct amdgpu_dm_connector { struct dsc_preferred_settings dsc_settings; /* Cached display modes */ struct drm_display_mode freesync_vid_base; + + int psr_skip_count; }; #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) @@ -591,6 +619,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 void amdgpu_dm_init_color_mod(void); +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); @@ -600,4 +629,6 @@ void amdgpu_dm_update_connector_after_detect( extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; +int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex, + struct aux_payload *payload, enum aux_return_code_type *operation_result); #endif /* __AMDGPU_DM_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 157fe4efbb59..a022e5bb30a5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -284,6 +284,37 @@ static int __set_input_tf(struct dc_transfer_func *func, return res ? 0 : -ENOMEM; } +/** + * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of + * the expected size. + * Returns 0 on success. + */ +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) +{ + const struct drm_color_lut *lut = NULL; + uint32_t size = 0; + + lut = __extract_blob_lut(crtc_state->degamma_lut, &size); + if (lut && size != MAX_COLOR_LUT_ENTRIES) { + DRM_DEBUG_DRIVER( + "Invalid Degamma LUT size. Should be %u but got %u.\n", + MAX_COLOR_LUT_ENTRIES, size); + return -EINVAL; + } + + lut = __extract_blob_lut(crtc_state->gamma_lut, &size); + if (lut && size != MAX_COLOR_LUT_ENTRIES && + size != MAX_COLOR_LEGACY_LUT_ENTRIES) { + DRM_DEBUG_DRIVER( + "Invalid Gamma LUT size. Should be %u (or %u for legacy) but got %u.\n", + MAX_COLOR_LUT_ENTRIES, MAX_COLOR_LEGACY_LUT_ENTRIES, + size); + return -EINVAL; + } + + return 0; +} + /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state @@ -317,14 +348,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) bool is_legacy; int r; - degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); - if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES) - return -EINVAL; + r = amdgpu_dm_verify_lut_sizes(&crtc->base); + if (r) + return r; + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); - if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES && - regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES) - return -EINVAL; has_degamma = degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 5cd788b20c21..cce062adc439 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -176,7 +176,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, /* Configuration will be deferred to stream enable. */ if (!stream_state) - return 0; + return -EINVAL; mutex_lock(&adev->dm.dc_lock); @@ -525,67 +525,6 @@ cleanup: spin_unlock_irqrestore(&drm_dev->event_lock, flags1); } -void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev) -{ - struct drm_crtc *crtc; - enum amdgpu_dm_pipe_crc_source cur_crc_src; - struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; - struct crc_window_parm cur_crc_window; - struct amdgpu_crtc *acrtc = NULL; - - drm_for_each_crtc(crtc, &adev->ddev) { - acrtc = to_amdgpu_crtc(crtc); - - spin_lock_irq(&adev_to_drm(adev)->event_lock); - cur_crc_src = acrtc->dm_irq_params.crc_src; - cur_crc_window = acrtc->dm_irq_params.crc_window; - spin_unlock_irq(&adev_to_drm(adev)->event_lock); - - if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { - amdgpu_dm_crtc_set_crc_source(crtc, - pipe_crc_sources[cur_crc_src]); - spin_lock_irq(&adev_to_drm(adev)->event_lock); - acrtc->dm_irq_params.crc_window = cur_crc_window; - if (acrtc->dm_irq_params.crc_window.activated) { - acrtc->dm_irq_params.crc_window.update_win = true; - acrtc->dm_irq_params.crc_window.skip_frame_cnt = 1; - spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); - crc_rd_wrk->crtc = crtc; - spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); - } - spin_unlock_irq(&adev_to_drm(adev)->event_lock); - } - } -} - -void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev) -{ - struct drm_crtc *crtc; - struct crc_window_parm cur_crc_window; - enum amdgpu_dm_pipe_crc_source cur_crc_src; - struct amdgpu_crtc *acrtc = NULL; - - drm_for_each_crtc(crtc, &adev->ddev) { - acrtc = to_amdgpu_crtc(crtc); - - spin_lock_irq(&adev_to_drm(adev)->event_lock); - cur_crc_src = acrtc->dm_irq_params.crc_src; - cur_crc_window = acrtc->dm_irq_params.crc_window; - cur_crc_window.update_win = false; - spin_unlock_irq(&adev_to_drm(adev)->event_lock); - - if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { - amdgpu_dm_crtc_set_crc_source(crtc, NULL); - spin_lock_irq(&adev_to_drm(adev)->event_lock); - /* For resume to set back crc source*/ - acrtc->dm_irq_params.crc_src = cur_crc_src; - acrtc->dm_irq_params.crc_window = cur_crc_window; - spin_unlock_irq(&adev_to_drm(adev)->event_lock); - } - } - -} - struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void) { struct crc_rd_work *crc_rd_wrk = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 737e701fb0f0..f07850db60a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -91,14 +91,10 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void); -void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev); -void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev); #else #define amdgpu_dm_crc_window_is_activated(x) #define amdgpu_dm_crtc_handle_crc_window_irq(x) #define amdgpu_dm_crtc_secure_display_create_work() -#define amdgpu_dm_crtc_secure_display_resume(x) -#define amdgpu_dm_crtc_secure_display_suspend(x) #endif #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1b6b15708b96..f1145086a468 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -887,6 +887,47 @@ unlock: return res; } +/* + * Example usage: + * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX + * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough + * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX + * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough + */ +static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; + char *wr_buf = NULL; + uint32_t wr_buf_size = 42; + int max_param_num = 1; + long param; + uint8_t param_nums = 0; + + if (size == 0) + return -EINVAL; + + wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); + + if (!wr_buf) { + DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); + return -ENOSPC; + } + + if (parse_write_buffer_into_params(wr_buf, size, + ¶m, buf, + max_param_num, + ¶m_nums)) { + kfree(wr_buf); + return -EINVAL; + } + + aconnector->dsc_settings.dsc_force_disable_passthrough = param; + + kfree(wr_buf); + return 0; +} + #ifdef CONFIG_DRM_AMD_DC_HDCP /* * Returns the HDCP capability of the Display (1.4 for now). @@ -925,6 +966,22 @@ static int hdcp_sink_capability_show(struct seq_file *m, void *data) return 0; } #endif + +/* + * Returns whether the connected display is internal and not hotpluggable. + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display + */ +static int internal_display_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct dc_link *link = aconnector->dc_link; + + seq_printf(m, "Internal: %u\n", link->is_internal_display); + + return 0; +} + /* function description * * generic SDP message access for testing @@ -2361,6 +2418,44 @@ unlock: return size; } +/* + * Backlight at this moment. Read only. + * As written to display, taking ABM and backlight lut into account. + * Ranges from 0x0 to 0x10000 (= 100% PWM) + * + * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight + */ +static int current_backlight_show(struct seq_file *m, void *unused) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); + struct dc_link *link = aconnector->dc_link; + unsigned int backlight; + + backlight = dc_link_get_backlight_level(link); + seq_printf(m, "0x%x\n", backlight); + + return 0; +} + +/* + * Backlight value that is being approached. Read only. + * As written to display, taking ABM and backlight lut into account. + * Ranges from 0x0 to 0x10000 (= 100% PWM) + * + * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight + */ +static int target_backlight_show(struct seq_file *m, void *unused) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); + struct dc_link *link = aconnector->dc_link; + unsigned int backlight; + + backlight = dc_link_get_target_backlight_pwm(link); + seq_printf(m, "0x%x\n", backlight); + + return 0; +} + DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); @@ -2369,6 +2464,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); #ifdef CONFIG_DRM_AMD_DC_HDCP DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); #endif +DEFINE_SHOW_ATTRIBUTE(internal_display); static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, @@ -2480,6 +2576,12 @@ static const struct file_operations dp_max_bpc_debugfs_fops = { .llseek = default_llseek }; +static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { + .owner = THIS_MODULE, + .write = dp_dsc_passthrough_set, + .llseek = default_llseek +}; + static const struct { char *name; const struct file_operations *fops; @@ -2504,7 +2606,8 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, - {"max_bpc", &dp_max_bpc_debugfs_fops} + {"max_bpc", &dp_max_bpc_debugfs_fops}, + {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, }; #ifdef CONFIG_DRM_AMD_DC_HDCP @@ -2594,13 +2697,17 @@ DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_g DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); +DEFINE_SHOW_ATTRIBUTE(current_backlight); +DEFINE_SHOW_ATTRIBUTE(target_backlight); + static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { {"force_yuv420_output", &force_yuv420_output_fops}, {"output_bpc", &output_bpc_fops}, - {"trigger_hotplug", &trigger_hotplug_debugfs_fops} + {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, + {"internal_display", &internal_display_fops} }; void connector_debugfs_init(struct amdgpu_dm_connector *connector) @@ -2616,8 +2723,13 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) dp_debugfs_entries[i].fops); } } - if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) + if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); + debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, + ¤t_backlight_fops); + debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, + &target_backlight_fops); + } for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -2920,38 +3032,6 @@ static ssize_t dtn_log_write( return size; } -/* - * Backlight at this moment. Read only. - * As written to display, taking ABM and backlight lut into account. - * Ranges from 0x0 to 0x10000 (= 100% PWM) - */ -static int current_backlight_show(struct seq_file *m, void *unused) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)m->private; - struct amdgpu_display_manager *dm = &adev->dm; - - unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link); - - seq_printf(m, "0x%x\n", backlight); - return 0; -} - -/* - * Backlight value that is being approached. Read only. - * As written to display, taking ABM and backlight lut into account. - * Ranges from 0x0 to 0x10000 (= 100% PWM) - */ -static int target_backlight_show(struct seq_file *m, void *unused) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)m->private; - struct amdgpu_display_manager *dm = &adev->dm; - - unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link); - - seq_printf(m, "0x%x\n", backlight); - return 0; -} - static int mst_topo_show(struct seq_file *m, void *unused) { struct amdgpu_device *adev = (struct amdgpu_device *)m->private; @@ -3134,8 +3214,6 @@ static int visual_confirm_get(void *data, u64 *val) return 0; } -DEFINE_SHOW_ATTRIBUTE(current_backlight); -DEFINE_SHOW_ATTRIBUTE(target_backlight); DEFINE_SHOW_ATTRIBUTE(mst_topo); DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); @@ -3215,10 +3293,6 @@ void dtn_debugfs_init(struct amdgpu_device *adev) struct drm_minor *minor = adev_to_drm(adev)->primary; struct dentry *root = minor->debugfs_root; - debugfs_create_file("amdgpu_current_backlight_pwm", 0444, - root, adev, ¤t_backlight_fops); - debugfs_create_file("amdgpu_target_backlight_pwm", 0444, - root, adev, &target_backlight_fops); debugfs_create_file("amdgpu_mst_topology", 0444, root, adev, &mst_topo_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 666796a0067c..e63c6885c757 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -222,10 +222,23 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, struct amdgpu_dm_connector *aconnector) { struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; + struct drm_connector_state *conn_state = aconnector->base.state; mutex_lock(&hdcp_w->mutex); hdcp_w->aconnector = aconnector; + /* the removal of display will invoke auth reset -> hdcp destroy and + * we'd expect the Content Protection (CP) property changed back to + * DESIRED if at the time ENABLED. CP property change should occur + * before the element removed from linked list. + */ + if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { + conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; + + DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", + aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); + } + mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); process_output(hdcp_w); @@ -454,6 +467,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) display->dig_fe = config->dig_fe; link->dig_be = config->dig_be; link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; + display->stream_enc_idx = config->stream_enc_idx; + link->link_enc_idx = config->link_enc_idx; + link->phy_idx = config->phy_idx; + link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link, + aconnector->dc_sink->sink_signal) ? 1 : 0; link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.assr_enabled = config->assr_enabled; link->dp.mst_enabled = config->mst_enabled; @@ -462,7 +480,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.hdcp1.disable = 0; conn_state = aconnector->base.state; - pr_debug("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, + DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, (!!aconnector->base.state) ? aconnector->base.state->hdcp_content_type : -1); @@ -637,6 +655,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); hdcp_work[i].hdcp.config.psp.handle = &adev->psp; + if (dc->ctx->dce_version == DCN_VERSION_3_1) { + hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1; + hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false; + } hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index e8b325a828c1..6fee12c91ef5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -544,8 +544,10 @@ bool dm_helpers_dp_write_dsc_enable( ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); } - if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) - return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { + ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); + DC_LOG_DC("Send DSC %s to sst display\n", enable_dsc ? "enable" : "disable"); + } return (ret > 0); } @@ -640,12 +642,25 @@ enum dc_edid_status dm_helpers_read_local_edid( return edid_status; } - +int dm_helper_dmub_aux_transfer_sync( + struct dc_context *ctx, + const struct dc_link *link, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) +{ + return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, operation_result); +} void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) { /* TODO: something */ } +void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) +{ + // TODO: + //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); +} + void *dm_helpers_allocate_gpu_mem( struct dc_context *ctx, enum dc_gpu_mem_alloc_type type, @@ -698,12 +713,12 @@ void dm_helpers_free_gpu_mem( } } -bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable) +bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) { enum dc_irq_source irq_source; bool ret; - irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0; + irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; ret = dc_interrupt_set(ctx->dc, irq_source, enable); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index b3ed7e777720..40f617bbb86f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -769,6 +769,18 @@ static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev, __func__); } +static int amdgpu_dm_set_dmub_outbox_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int crtc_id, + enum amdgpu_interrupt_state state) +{ + enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; + bool st = (state == AMDGPU_IRQ_STATE_ENABLE); + + dc_interrupt_set(adev->dm.dc, irq_source, st); + return 0; +} + static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int crtc_id, @@ -805,6 +817,11 @@ static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = { .process = amdgpu_dm_irq_handler, }; +static const struct amdgpu_irq_src_funcs dm_dmub_outbox_irq_funcs = { + .set = amdgpu_dm_set_dmub_outbox_irq_state, + .process = amdgpu_dm_irq_handler, +}; + static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = { .set = amdgpu_dm_set_vupdate_irq_state, .process = amdgpu_dm_irq_handler, @@ -827,13 +844,15 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = { void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = adev->mode_info.num_crtc; adev->crtc_irq.funcs = &dm_crtc_irq_funcs; adev->vline0_irq.num_types = adev->mode_info.num_crtc; adev->vline0_irq.funcs = &dm_vline0_irq_funcs; + adev->dmub_outbox_irq.num_types = 1; + adev->dmub_outbox_irq.funcs = &dm_dmub_outbox_irq_funcs; + adev->vupdate_irq.num_types = adev->mode_info.num_crtc; adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs; @@ -846,6 +865,12 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dm_hpd_irq_funcs; } +void amdgpu_dm_outbox_init(struct amdgpu_device *adev) +{ + dc_interrupt_set(adev->dm.dc, + DC_IRQ_SOURCE_DMCUB_OUTBOX, + true); +} /** * amdgpu_dm_hpd_init - hpd setup callback. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h index 82f8e761beca..2349238a626b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h @@ -82,6 +82,7 @@ void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev); +void amdgpu_dm_outbox_init(struct amdgpu_device *adev); void amdgpu_dm_hpd_init(struct amdgpu_device *adev); void amdgpu_dm_hpd_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9b221db526dc..5568d4e518e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -160,6 +160,8 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto struct dc_sink *dc_sink = aconnector->dc_sink; struct drm_dp_mst_port *port = aconnector->port; u8 dsc_caps[16] = { 0 }; + u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 + u8 *dsc_branch_dec_caps = NULL; aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); #if defined(CONFIG_HP_HOOK_WORKAROUND) @@ -182,9 +184,13 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) return false; + if (drm_dp_dpcd_read(aconnector->dsc_aux, + DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) + dsc_branch_dec_caps = dsc_branch_dec_caps_raw; + if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, - dsc_caps, NULL, - &dc_sink->dsc_caps.dsc_dec_caps)) + dsc_caps, dsc_branch_dec_caps, + &dc_sink->dsc_caps.dsc_dec_caps)) return false; return true; @@ -278,6 +284,9 @@ dm_dp_mst_detect(struct drm_connector *connector, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct amdgpu_dm_connector *master = aconnector->mst_port; + if (drm_connector_is_unregistered(connector)) + return connector_status_disconnected; + return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, aconnector->port); } @@ -434,10 +443,13 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, int link_index) { + struct dc_link_settings max_link_enc_cap = {0}; + aconnector->dm_dp_aux.aux.name = kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", link_index); aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; + aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_init(&aconnector->dm_dp_aux.aux); @@ -447,6 +459,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) return; + dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; drm_dp_mst_topology_mgr_init( &aconnector->mst_mgr, @@ -454,6 +467,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c new file mode 100644 index 000000000000..70a554f1e725 --- /dev/null +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -0,0 +1,164 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "amdgpu_dm_psr.h" +#include "dc.h" +#include "dm_helpers.h" + +/* + * amdgpu_dm_set_psr_caps() - set link psr capabilities + * @link: link + * + */ +void amdgpu_dm_set_psr_caps(struct dc_link *link) +{ + uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; + + if (!(link->connector_signal & SIGNAL_TYPE_EDP)) + return; + if (link->type == dc_connection_none) + return; + if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, + dpcd_data, sizeof(dpcd_data))) { + link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; + + if (dpcd_data[0] == 0) { + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->psr_settings.psr_feature_enabled = false; + } else { + link->psr_settings.psr_version = DC_PSR_VERSION_1; + link->psr_settings.psr_feature_enabled = true; + } + + DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled); + } +} + +/* + * amdgpu_dm_link_setup_psr() - configure psr link + * @stream: stream state + * + * Return: true if success + */ +bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) +{ + struct dc_link *link = NULL; + struct psr_config psr_config = {0}; + struct psr_context psr_context = {0}; + bool ret = false; + + if (stream == NULL) + return false; + + link = stream->link; + + psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version; + + if (psr_config.psr_version > 0) { + psr_config.psr_exit_link_training_required = 0x1; + psr_config.psr_frame_capture_indication_req = 0; + psr_config.psr_rfb_setup_time = 0x37; + psr_config.psr_sdp_transmit_line_num_deadline = 0x20; + psr_config.allow_smu_optimizations = 0x0; + + ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); + + } + DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); + + return ret; +} + +/* + * amdgpu_dm_psr_enable() - enable psr f/w + * @stream: stream state + * + * Return: true if success + */ +bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) +{ + struct dc_link *link = stream->link; + unsigned int vsync_rate_hz = 0; + struct dc_static_screen_params params = {0}; + /* Calculate number of static frames before generating interrupt to + * enter PSR. + */ + // Init fail safe of 2 frames static + unsigned int num_frames_static = 2; + + DRM_DEBUG_DRIVER("Enabling psr...\n"); + + vsync_rate_hz = div64_u64(div64_u64(( + stream->timing.pix_clk_100hz * 100), + stream->timing.v_total), + stream->timing.h_total); + + /* Round up + * Calculate number of frames such that at least 30 ms of time has + * passed. + */ + if (vsync_rate_hz != 0) { + unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; + num_frames_static = (30000 / frame_time_microsec) + 1; + } + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = num_frames_static; + + dc_stream_set_static_screen_params(link->ctx->dc, + &stream, 1, + ¶ms); + + return dc_link_set_psr_allow_active(link, true, false, false); +} + +/* + * amdgpu_dm_psr_disable() - disable psr f/w + * @stream: stream state + * + * Return: true if success + */ +bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) +{ + + DRM_DEBUG_DRIVER("Disabling psr...\n"); + + return dc_link_set_psr_allow_active(stream->link, false, true, false); +} + +/* + * amdgpu_dm_psr_disable() - disable psr f/w + * if psr is enabled on any stream + * + * Return: true if success + */ +bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) +{ + DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); + return dc_set_psr_allow_active(dm->dc, false); +} + diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h new file mode 100644 index 000000000000..6806b3c9c84b --- /dev/null +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h @@ -0,0 +1,40 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef AMDGPU_DM_AMDGPU_DM_PSR_H_ +#define AMDGPU_DM_AMDGPU_DM_PSR_H_ + +#include "amdgpu.h" + +/* the number of pageflips before enabling psr */ +#define AMDGPU_DM_PSR_ENTRY_DELAY 5 + +void amdgpu_dm_set_psr_caps(struct dc_link *link); +bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); +bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); +bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); +bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); + +#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index f33847299bca..943fcb164876 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -33,6 +33,8 @@ DC_LIBS += dcn21 DC_LIBS += dcn30 DC_LIBS += dcn301 DC_LIBS += dcn302 +DC_LIBS += dcn303 +DC_LIBS += dcn31 endif DC_LIBS += dce120 @@ -54,9 +56,9 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI include $(AMD_DC) -DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ +DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \ -dc_link_enc_cfg.o +dc_link_enc_cfg.o dc_link_dpcd.o ifdef CONFIG_DRM_AMD_DC_DCN DISPLAY_CORE += dc_vm_helper.o diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index c67d21a5ee52..9b8ea6e9a2b9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -979,7 +979,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1( struct spread_spectrum_info *info); /** - * get_ss_info_from_table + * get_ss_info_from_tbl * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or * SS_Info table from the VBIOS * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or @@ -1548,7 +1548,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl( uint32_t id); /** - * BiosParserObject::GetNumberofSpreadSpectrumEntry + * bios_parser_get_ss_entry_number * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from * the VBIOS that match the SSid (to be converted from signal) * @@ -1725,7 +1725,7 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( return 0; } /** - * get_ss_entry_number_from_internal_ss_info_table_V3_1 + * get_ss_entry_number_from_internal_ss_info_tbl_V3_1 * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of * the VBIOS that matches id * diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index d79f4fe06c47..6dbde74c1e06 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -577,6 +577,11 @@ static struct device_id device_type_from_device_id(uint16_t device_id) result_device_id.enum_id = 1; break; + case ATOM_DISPLAY_LCD2_SUPPORT: + result_device_id.device_type = DEVICE_TYPE_LCD; + result_device_id.enum_id = 2; + break; + case ATOM_DISPLAY_DFP1_SUPPORT: result_device_id.device_type = DEVICE_TYPE_DFP; result_device_id.enum_id = 1; @@ -836,8 +841,10 @@ static enum bp_result bios_parser_get_spread_spectrum_info( return get_ss_info_v4_1(bp, signal, index, ss_info); case 2: case 3: + case 4: return get_ss_info_v4_2(bp, signal, index, ss_info); default: + ASSERT(0); break; } break; @@ -2131,7 +2138,7 @@ static enum bp_result get_integrated_info_v2_1( info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; info->edp1_info.edp_panel_bpc = info_v2_1->edp1_info.edp_panel_bpc; - info->edp1_info.edp_bootup_bl_level = + info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; info->edp2_info.edp_backlight_pwm_hz = le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); @@ -2153,6 +2160,106 @@ static enum bp_result get_integrated_info_v2_1( return BP_RESULT_OK; } +static enum bp_result get_integrated_info_v2_2( + struct bios_parser *bp, + struct integrated_info *info) +{ + struct atom_integrated_system_info_v2_2 *info_v2_2; + uint32_t i; + + info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, + DATA_TABLES(integratedsysteminfo)); + + if (info_v2_2 == NULL) + return BP_RESULT_BADBIOSTABLE; + + info->gpu_cap_info = + le32_to_cpu(info_v2_2->gpucapinfo); + /* + * system_config: Bit[0] = 0 : PCIE power gating disabled + * = 1 : PCIE power gating enabled + * Bit[1] = 0 : DDR-PLL shut down disabled + * = 1 : DDR-PLL shut down enabled + * Bit[2] = 0 : DDR-PLL power down disabled + * = 1 : DDR-PLL power down enabled + */ + info->system_config = le32_to_cpu(info_v2_2->system_config); + info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); + info->memory_type = info_v2_2->memorytype; + info->ma_channel_number = info_v2_2->umachannelnumber; + info->dp_ss_control = + le16_to_cpu(info_v2_2->reserved1); + + for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { + info->ext_disp_conn_info.gu_id[i] = + info_v2_2->extdispconninfo.guid[i]; + } + + for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { + info->ext_disp_conn_info.path[i].device_connector_id = + object_id_from_bios_object_id( + le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); + + info->ext_disp_conn_info.path[i].ext_encoder_obj_id = + object_id_from_bios_object_id( + le16_to_cpu( + info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); + + info->ext_disp_conn_info.path[i].device_tag = + le16_to_cpu( + info_v2_2->extdispconninfo.path[i].device_tag); + info->ext_disp_conn_info.path[i].device_acpi_enum = + le16_to_cpu( + info_v2_2->extdispconninfo.path[i].device_acpi_enum); + info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = + info_v2_2->extdispconninfo.path[i].auxddclut_index; + info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = + info_v2_2->extdispconninfo.path[i].hpdlut_index; + info->ext_disp_conn_info.path[i].channel_mapping.raw = + info_v2_2->extdispconninfo.path[i].channelmapping; + info->ext_disp_conn_info.path[i].caps = + le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); + } + + info->ext_disp_conn_info.checksum = + info_v2_2->extdispconninfo.checksum; + + info->edp1_info.edp_backlight_pwm_hz = + le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); + info->edp1_info.edp_ss_percentage = + le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); + info->edp1_info.edp_ss_rate_10hz = + le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); + info->edp1_info.edp_pwr_on_off_delay = + info_v2_2->edp1_info.edp_pwr_on_off_delay; + info->edp1_info.edp_pwr_on_vary_bl_to_blon = + info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; + info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = + info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; + info->edp1_info.edp_panel_bpc = + info_v2_2->edp1_info.edp_panel_bpc; + info->edp1_info.edp_bootup_bl_level = + + info->edp2_info.edp_backlight_pwm_hz = + le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); + info->edp2_info.edp_ss_percentage = + le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); + info->edp2_info.edp_ss_rate_10hz = + le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); + info->edp2_info.edp_pwr_on_off_delay = + info_v2_2->edp2_info.edp_pwr_on_off_delay; + info->edp2_info.edp_pwr_on_vary_bl_to_blon = + info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; + info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = + info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; + info->edp2_info.edp_panel_bpc = + info_v2_2->edp2_info.edp_panel_bpc; + info->edp2_info.edp_bootup_bl_level = + info_v2_2->edp2_info.edp_bootup_bl_level; + + return BP_RESULT_OK; +} + /* * construct_integrated_info * @@ -2200,6 +2307,9 @@ static enum bp_result construct_integrated_info( case 1: result = get_integrated_info_v2_1(bp, info); break; + case 2: + result = get_integrated_info_v2_2(bp, info); + break; default: return result; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c index 53d7513b5083..adc710fe4a45 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c @@ -82,9 +82,6 @@ void bios_set_scratch_critical_state( uint32_t bios_get_vga_enabled_displays( struct dc_bios *bios) { - uint32_t active_disp = 1; - - active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF; - return active_disp; + return REG_READ(BIOS_SCRATCH_3) & 0XFFFF; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c index 5b77251e0590..e317a3615147 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c @@ -114,7 +114,7 @@ bool dal_cmd_table_helper_controller_id_to_atom( } /** - * translate_transmitter_bp_to_atom - Translate the Transmitter to the + * dal_cmd_table_helper_transmitter_bp_to_atom - Translate the Transmitter to the * corresponding ATOM BIOS value * @t: transmitter * returns: output digitalTransmitter diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 455ee2be15a3..cb3fd44cb1ed 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -73,6 +73,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCN_VERSION_3_0: case DCN_VERSION_3_01: case DCN_VERSION_3_02: + case DCN_VERSION_3_03: + case DCN_VERSION_3_1: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; #endif @@ -128,7 +130,7 @@ bool dal_cmd_table_helper_controller_id_to_atom2( } /** - * translate_transmitter_bp_to_atom2 - Translate the Transmitter to the + * dal_cmd_table_helper_transmitter_bp_to_atom2 - Translate the Transmitter to the * corresponding ATOM BIOS value * @t: transmitter * returns: digitalTransmitter diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 1244fcb0f446..ff5bb152ef49 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2863,6 +2863,7 @@ static void populate_initial_data( data->bytes_per_pixel[num_displays + 4] = 4; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: data->bytes_per_pixel[num_displays + 4] = 8; break; @@ -2966,6 +2967,7 @@ static void populate_initial_data( data->bytes_per_pixel[num_displays + 4] = 4; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: data->bytes_per_pixel[num_displays + 4] = 8; break; diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index d4df4da5b81a..0e18df1283b6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -236,6 +236,7 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format for case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: return dcn_bw_rgb_sub_32; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: return dcn_bw_rgb_sub_64; @@ -375,6 +376,7 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.viewport_height_c = input->src.viewport_height / 2; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: input->src.source_format = dm_444_64; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index ff96bee57bfc..7fa0b007a7ea 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -135,4 +135,13 @@ endif AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301) + +############################################################################### +# DCN31 +############################################################################### +CLK_MGR_DCN31 = dcn31_smu.o dcn31_clk_mgr.o + +AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DCN31)) + +AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31) endif diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 7d6c68c5dea9..bb31541f8072 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -41,6 +41,7 @@ #include "dcn21/rn_clk_mgr.h" #include "dcn30/dcn30_clk_mgr.h" #include "dcn301/vg_clk_mgr.h" +#include "dcn31/dcn31_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( @@ -90,15 +91,20 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m struct dc_link *edp_links[MAX_NUM_EDP]; struct dc_link *edp_link = NULL; int edp_num; + unsigned int panel_inst; get_edp_links(dc, edp_links, &edp_num); if (dc->hwss.exit_optimized_pwr_state) dc->hwss.exit_optimized_pwr_state(dc, dc->current_state); if (edp_num) { - edp_link = edp_links[0]; - clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; - dc_link_set_psr_allow_active(edp_link, false, false, false); + for (panel_inst = 0; panel_inst < edp_num; panel_inst++) { + edp_link = edp_links[panel_inst]; + if (!edp_link->psr_settings.psr_feature_enabled) + continue; + clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; + dc_link_set_psr_allow_active(edp_link, false, false, false); + } } } @@ -108,12 +114,17 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) struct dc_link *edp_links[MAX_NUM_EDP]; struct dc_link *edp_link = NULL; int edp_num; + unsigned int panel_inst; get_edp_links(dc, edp_links, &edp_num); if (edp_num) { - edp_link = edp_links[0]; - dc_link_set_psr_allow_active(edp_link, - clk_mgr->psr_allow_active_cache, false, false); + for (panel_inst = 0; panel_inst < edp_num; panel_inst++) { + edp_link = edp_links[panel_inst]; + if (!edp_link->psr_settings.psr_feature_enabled) + continue; + dc_link_set_psr_allow_active(edp_link, + clk_mgr->psr_allow_active_cache, false, false); + } } if (dc->hwss.optimize_pwr_state) @@ -241,6 +252,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } + if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) { + dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base; + } dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } @@ -256,7 +271,24 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return &clk_mgr->base.base; } break; + case FAMILY_YELLOW_CARP: { + struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) { + /* TODO: to add DCN31 clk_mgr support, once CLK IP header files are available, + * for now use DCN3.0 clk mgr. + */ + dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base.base; + } + return &clk_mgr->base.base; + } #endif + default: ASSERT(0); /* Unknown Asic */ break; @@ -278,6 +310,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { dcn3_clk_mgr_destroy(clk_mgr); } + if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { + dcn3_clk_mgr_destroy(clk_mgr); + } break; case FAMILY_VGH: @@ -285,6 +320,11 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) vg_clk_mgr_destroy(clk_mgr); break; + case FAMILY_YELLOW_CARP: + if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + dcn31_clk_mgr_destroy(clk_mgr); + break; + default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 372d53b5a34d..6e0c5c664fdc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -123,7 +123,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, } } -void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) +void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context) { int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; @@ -132,6 +132,68 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); + uint32_t current_dispclk_wdivider; + uint32_t i; + + REG_GET(DENTIST_DISPCLK_CNTL, + DENTIST_DISPCLK_WDIVIDER, ¤t_dispclk_wdivider); + + /* When changing divider to or from 127, some extra programming is required to prevent corruption */ + if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) { + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + uint32_t fifo_level; + struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; + struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; + int32_t N; + int32_t j; + + if (!pipe_ctx->stream) + continue; + /* Virtual encoders don't have this function */ + if (!stream_enc->funcs->get_fifo_cal_average_level) + continue; + fifo_level = stream_enc->funcs->get_fifo_cal_average_level( + stream_enc); + N = fifo_level / 4; + dccg->funcs->set_fifo_errdet_ovr_en( + dccg, + true); + for (j = 0; j < N - 4; j++) + dccg->funcs->otg_drop_pixel( + dccg, + pipe_ctx->stream_res.tg->inst); + dccg->funcs->set_fifo_errdet_ovr_en( + dccg, + false); + } + } else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) { + REG_UPDATE(DENTIST_DISPCLK_CNTL, + DENTIST_DISPCLK_WDIVIDER, 126); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100); + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; + struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; + uint32_t fifo_level; + int32_t N; + int32_t j; + + if (!pipe_ctx->stream) + continue; + /* Virtual encoders don't have this function */ + if (!stream_enc->funcs->get_fifo_cal_average_level) + continue; + fifo_level = stream_enc->funcs->get_fifo_cal_average_level( + stream_enc); + N = fifo_level / 4; + dccg->funcs->set_fifo_errdet_ovr_en(dccg, true); + for (j = 0; j < 12 - N; j++) + dccg->funcs->otg_add_pixel(dccg, + pipe_ctx->stream_res.tg->inst); + dccg->funcs->set_fifo_errdet_ovr_en(dccg, false); + } + } REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); @@ -251,11 +313,11 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, if (dpp_clock_lowered) { // if clock is being lowered, increase DTO before lowering refclk dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); - dcn20_update_clocks_update_dentist(clk_mgr); + dcn20_update_clocks_update_dentist(clk_mgr, context); } else { // if clock is being raised, increase refclk before lowering DTO if (update_dppclk || update_dispclk) - dcn20_update_clocks_update_dentist(clk_mgr); + dcn20_update_clocks_update_dentist(clk_mgr, context); // always update dtos unless clock is lowered and not safe to lower dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); } @@ -324,6 +386,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, // Both fclk and ref_dppclk run on the same scemi clock. clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; + /* TODO: set dtbclk in correct place */ + clk_mgr->clks.dtbclk_en = false; dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h index 0b9c045b0c8e..d254d0b6fba1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h @@ -50,7 +50,8 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); -void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr); +void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, + struct dc_state *context); void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index a06e86853bb9..c6f494f0dcea 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -106,10 +106,10 @@ static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { int dpp_inst, dppclk_khz, prev_dppclk_khz; - /* Loop index will match dpp->inst if resource exists, - * and we want to avoid dependency on dpp object + /* Loop index may not match dpp->inst if some pipes disabled, + * so select correct inst from res_pool */ - dpp_inst = i; + dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; @@ -128,7 +128,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; struct dc *dc = clk_mgr_base->ctx->dc; - int display_count, i; + int display_count; bool update_dppclk = false; bool update_dispclk = false; bool dpp_clock_lowered = false; @@ -210,14 +210,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dppclk_khz, safe_to_lower); - for (i = 0; i < context->stream_count; i++) { - if (context->streams[i]->signal == SIGNAL_TYPE_EDP && - context->streams[i]->apply_seamless_boot_optimization) { - dc_wait_for_vblank(dc, context->streams[i]); - break; - } - } - clk_mgr_base->clks.actual_dppclk_khz = rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); @@ -842,6 +834,7 @@ static struct wm_table lpddr4_wm_table_rn = { }, } }; + static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) { int i; @@ -854,6 +847,7 @@ static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsi ASSERT(0); return 0; } + static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index 652fa89fae5f..513676a6f52b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -334,11 +334,11 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, if (dpp_clock_lowered) { /* if clock is being lowered, increase DTO before lowering refclk */ dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); - dcn20_update_clocks_update_dentist(clk_mgr); + dcn20_update_clocks_update_dentist(clk_mgr, context); } else { /* if clock is being raised, increase refclk before lowering DTO */ if (update_dppclk || update_dispclk) - dcn20_update_clocks_update_dentist(clk_mgr); + dcn20_update_clocks_update_dentist(clk_mgr, context); /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures * that we do not lower dto when it is not safe to lower. We do not need to * compare the current and new dppclk before calling this function.*/ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c new file mode 100644 index 000000000000..7b7d884d58be --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -0,0 +1,673 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + + +#include "dccg.h" +#include "clk_mgr_internal.h" + +// For dce12_get_dp_ref_freq_khz +#include "dce100/dce_clk_mgr.h" + +// For dcn20_update_clocks_update_dpp_dto +#include "dcn20/dcn20_clk_mgr.h" + + + +#include "dcn31_clk_mgr.h" + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn31_smu.h" +#include "dm_helpers.h" + +/* TODO: remove this include once we ported over remaining clk mgr functions*/ +#include "dcn30/dcn30_clk_mgr.h" + +#include "dc_dmub_srv.h" + +#define TO_CLK_MGR_DCN31(clk_mgr)\ + container_of(clk_mgr, struct clk_mgr_dcn31, base) + +int dcn31_get_active_display_cnt_wa( + struct dc *dc, + struct dc_state *context) +{ + int i, display_count; + bool tmds_present = false; + + display_count = 0; + for (i = 0; i < context->stream_count; i++) { + const struct dc_stream_state *stream = context->streams[i]; + + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || + stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || + stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) + tmds_present = true; + } + + for (i = 0; i < dc->link_count; i++) { + const struct dc_link *link = dc->links[i]; + + /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) + display_count++; + } + + /* WA for hang on HDMI after display off back back on*/ + if (display_count == 0 && tmds_present) + display_count = 1; + + return display_count; +} + +static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) +{ + struct dc *dc = clk_mgr_base->ctx->dc; + int i; + + for (i = 0; i < dc->res_pool->pipe_count; ++i) { + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->top_pipe || pipe->prev_odm_pipe) + continue; + if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { + if (disable) + pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); + else + pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); + } + } +} + +static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower) +{ + union dmub_rb_cmd cmd; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + struct dc *dc = clk_mgr_base->ctx->dc; + int display_count; + bool update_dppclk = false; + bool update_dispclk = false; + bool dpp_clock_lowered = false; + + if (dc->work_arounds.skip_clock_update) + return; + + /* + * if it is safe to lower, but we are already in the lower state, we don't have to do anything + * also if safe to lower is false, we just go in the higher state + */ + if (safe_to_lower) { + if (new_clocks->z9_support == DCN_Z9_SUPPORT_ALLOW && + new_clocks->z9_support != clk_mgr_base->clks.z9_support) { + dcn31_smu_set_Z9_support(clk_mgr, true); + clk_mgr_base->clks.z9_support = new_clocks->z9_support; + } + + if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { + dcn31_smu_set_dtbclk(clk_mgr, false); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + /* check that we're not already in lower */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { + display_count = dcn31_get_active_display_cnt_wa(dc, context); + /* if we can go lower, go lower */ + if (display_count == 0) { + union display_idle_optimization_u idle_info = { 0 }; + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + /* update power state */ + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; + } + } + } else { + if (new_clocks->z9_support == DCN_Z9_SUPPORT_DISALLOW && + new_clocks->z9_support != clk_mgr_base->clks.z9_support) { + dcn31_smu_set_Z9_support(clk_mgr, false); + clk_mgr_base->clks.z9_support = new_clocks->z9_support; + } + + if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { + dcn31_smu_set_dtbclk(clk_mgr, true); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + + /* check that we're not already in D0 */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { + union display_idle_optimization_u idle_info = { 0 }; + dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + /* update power state */ + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; + } + } + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); + } + + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { + clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); + } + + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; + } + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { + if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) + dpp_clock_lowered = true; + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; + update_dppclk = true; + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { + dcn31_disable_otg_wa(clk_mgr_base, true); + + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); + dcn31_disable_otg_wa(clk_mgr_base, false); + + update_dispclk = true; + } + + /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/ + if (dpp_clock_lowered) { + // increase per DPP DTO before lowering global dppclk + dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + } else { + // increase global DPPCLK before lowering per DPP DTO + if (update_dppclk || update_dispclk) + dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + } + + // notify DMCUB of latest clocks + memset(&cmd, 0, sizeof(cmd)); + cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; + cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; + cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; + cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = + clk_mgr_base->clks.dcfclk_deep_sleep_khz; + cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; + cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; + + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); +} + +static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) +{ + return 0; +} + +static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + dcn31_smu_enable_pme_wa(clk_mgr); +} + +static void dcn31_init_clocks(struct clk_mgr *clk_mgr) +{ + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); + // Assumption is that boot state always supports pstate + clk_mgr->clks.p_state_change_support = true; + clk_mgr->clks.prev_p_state_change_support = true; + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; + clk_mgr->clks.z9_support = DCN_Z9_SUPPORT_UNKNOWN; +} + +static bool dcn31_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b) +{ + if (a->dispclk_khz != b->dispclk_khz) + return false; + else if (a->dppclk_khz != b->dppclk_khz) + return false; + else if (a->dcfclk_khz != b->dcfclk_khz) + return false; + else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) + return false; + else if (a->z9_support != b->z9_support) + return false; + else if (a->dtbclk_en != b->dtbclk_en) + return false; + + return true; +} + +static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) +{ + return; +} + +static struct clk_bw_params dcn31_bw_params = { + .vram_type = Ddr4MemType, + .num_channels = 1, + .clk_table = { + .num_entries = 4, + }, + +}; + +static struct wm_table ddr4_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 6.09, + .sr_enter_plus_exit_time_us = 7.14, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 10.12, + .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 10.12, + .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 10.12, + .sr_enter_plus_exit_time_us = 11.48, + .valid = true, + }, + } +}; + +static struct wm_table lpddr5_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 5.32, + .sr_enter_plus_exit_time_us = 6.38, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 9.82, + .sr_enter_plus_exit_time_us = 11.196, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 9.89, + .sr_enter_plus_exit_time_us = 11.24, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 9.748, + .sr_enter_plus_exit_time_us = 11.102, + .valid = true, + }, + } +}; + +static DpmClocks_t dummy_clocks; + +static struct dcn31_watermarks dummy_wms = { 0 }; + +static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) +{ + int i, num_valid_sets; + + num_valid_sets = 0; + + for (i = 0; i < WM_SET_COUNT; i++) { + /* skip empty entries, the smu array has no holes*/ + if (!bw_params->wm_table.entries[i].valid) + continue; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + /* We will not select WM based on fclk, so leave it as unconstrained */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { + if (i == 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; + else { + /* add 1 to make it non-overlapping with next lvl */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = + bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + } + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = + bw_params->clk_table.entries[i].dcfclk_mhz; + + } else { + /* unconstrained for memory retraining */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + /* Modify previous watermark range to cover up to max */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + } + num_valid_sets++; + } + + ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ + + /* modify the min and max to make sure we cover the whole range*/ + table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; + table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + + /* This is for writeback only, does not matter currently as no writeback support*/ + table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; + table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; + table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; +} + +static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr); + struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; + + if (!clk_mgr->smu_ver) + return; + + if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + + dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); + + dcn31_smu_set_dram_addr_high(clk_mgr, + clk_mgr_dcn31->smu_wm_set.mc_address.high_part); + dcn31_smu_set_dram_addr_low(clk_mgr, + clk_mgr_dcn31->smu_wm_set.mc_address.low_part); + dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr); +} + +static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, + struct dcn31_smu_dpm_clks *smu_dpm_clks) +{ + DpmClocks_t *table = smu_dpm_clks->dpm_clks; + + if (!clk_mgr->smu_ver) + return; + + if (!table || smu_dpm_clks->mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + + dcn31_smu_set_dram_addr_high(clk_mgr, + smu_dpm_clks->mc_address.high_part); + dcn31_smu_set_dram_addr_low(clk_mgr, + smu_dpm_clks->mc_address.low_part); + dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr); +} + +static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) +{ + uint32_t max = 0; + int i; + + for (i = 0; i < num_clocks; ++i) { + if (clocks[i] > max) + max = clocks[i]; + } + + return max; +} + +static unsigned int find_clk_for_voltage( + const DpmClocks_t *clock_table, + const uint32_t clocks[], + unsigned int voltage) +{ + int i; + + for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { + if (clock_table->SocVoltage[i] == voltage) + return clocks[i]; + } + + ASSERT(0); + return 0; +} + +void dcn31_clk_mgr_helper_populate_bw_params( + struct clk_mgr_internal *clk_mgr, + struct integrated_info *bios_info, + const DpmClocks_t *clock_table) +{ + int i, j; + struct clk_bw_params *bw_params = clk_mgr->base.bw_params; + uint32_t max_dispclk = 0, max_dppclk = 0; + + j = -1; + + ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); + + /* Find lowest DPM, FCLK is filled in reverse order*/ + + for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) { + if (clock_table->DfPstateTable[i].FClk != 0) { + j = i; + break; + } + } + + if (j == -1) { + /* clock table is all 0s, just use our own hardcode */ + ASSERT(0); + return; + } + + bw_params->clk_table.num_entries = j + 1; + + /* dispclk and dppclk can be max at any voltage, same number of levels for both */ + if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && + clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { + max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); + max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); + } else { + ASSERT(0); + } + + for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { + bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; + bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; + bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; + switch (clock_table->DfPstateTable[j].WckRatio) { + case WCK_RATIO_1_2: + bw_params->clk_table.entries[i].wck_ratio = 2; + break; + case WCK_RATIO_1_4: + bw_params->clk_table.entries[i].wck_ratio = 4; + break; + default: + bw_params->clk_table.entries[i].wck_ratio = 1; + } + bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + } + + bw_params->vram_type = bios_info->memory_type; + bw_params->num_channels = bios_info->ma_channel_number; + + for (i = 0; i < WM_SET_COUNT; i++) { + bw_params->wm_table.entries[i].wm_inst = i; + + if (i >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[i].valid = false; + continue; + } + + bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[i].valid = true; + } +} + +static struct clk_mgr_funcs dcn31_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .update_clocks = dcn31_update_clocks, + .init_clocks = dcn31_init_clocks, + .enable_pme_wa = dcn31_enable_pme_wa, + .are_clock_states_equal = dcn31_are_clock_states_equal, + .notify_wm_ranges = dcn31_notify_wm_ranges +}; +extern struct clk_mgr_funcs dcn3_fpga_funcs; + +void dcn31_clk_mgr_construct( + struct dc_context *ctx, + struct clk_mgr_dcn31 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg) +{ + struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 }; + + clk_mgr->base.base.ctx = ctx; + clk_mgr->base.base.funcs = &dcn31_funcs; + + clk_mgr->base.pp_smu = pp_smu; + + clk_mgr->base.dccg = dccg; + clk_mgr->base.dfs_bypass_disp_clk = 0; + + clk_mgr->base.dprefclk_ss_percentage = 0; + clk_mgr->base.dprefclk_ss_divider = 1000; + clk_mgr->base.ss_on_dprefclk = false; + + clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( + clk_mgr->base.base.ctx, + DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + sizeof(struct dcn31_watermarks), + &clk_mgr->smu_wm_set.mc_address.quad_part); + + if (clk_mgr->smu_wm_set.wm_set == 0) { + clk_mgr->smu_wm_set.wm_set = &dummy_wms; + clk_mgr->smu_wm_set.mc_address.quad_part = 0; + } + ASSERT(clk_mgr->smu_wm_set.wm_set); + + smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem( + clk_mgr->base.base.ctx, + DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + sizeof(DpmClocks_t), + &smu_dpm_clks.mc_address.quad_part); + + if (smu_dpm_clks.dpm_clks == NULL) { + smu_dpm_clks.dpm_clks = &dummy_clocks; + smu_dpm_clks.mc_address.quad_part = 0; + } + + ASSERT(smu_dpm_clks.dpm_clks); + + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { + clk_mgr->base.base.funcs = &dcn3_fpga_funcs; + } else { + struct clk_log_info log_info = {0}; + + clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base); + + if (clk_mgr->base.smu_ver) + clk_mgr->base.smu_present = true; + + /* TODO: Check we get what we expect during bringup */ + clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); + + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + dcn31_bw_params.wm_table = lpddr5_wm_table; + } else { + dcn31_bw_params.wm_table = ddr4_wm_table; + } + /* Saved clocks configured at boot for debug purposes */ + dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + + } + + clk_mgr->base.base.dprefclk_khz = 600000; + clk_mgr->base.dccg->ref_dtbclk_khz = 600000; + dce_clock_read_ss_info(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn31_bw_params; + + if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { + dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); + + if (ctx->dc_bios && ctx->dc_bios->integrated_info) { + dcn31_clk_mgr_helper_populate_bw_params( + &clk_mgr->base, + ctx->dc_bios->integrated_info, + smu_dpm_clks.dpm_clks); + } + } + + if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + smu_dpm_clks.dpm_clks); +} + +void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) +{ + struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int); + + if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + clk_mgr->smu_wm_set.wm_set); +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h new file mode 100644 index 000000000000..cc21cf75eafd --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h @@ -0,0 +1,103 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN31_CLK_MGR_H__ +#define __DCN31_CLK_MGR_H__ +#include "clk_mgr_internal.h" + +//CLK1_CLK_PLL_REQ +#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L +//CLK1_CLK0_DFS_CNTL +#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0 +#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL +/*DPREF clock related*/ +#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL +#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 +#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL + +//CLK3_0_CLK3_CLK_PLL_REQ +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L + +#define mmCLK0_CLK3_DFS_CNTL 0x16C60 +#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60 +#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60 +#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060 +#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260 + +#define mmCLK0_CLK_PLL_REQ 0x16C10 +#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10 +#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10 +#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010 +#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210 + +#define mmCLK1_CLK_PLL_REQ 0x1B00D +#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D +#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D +#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D +#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D + +#define mmCLK2_CLK_PLL_REQ 0x17E0D + +/*AMCLK*/ +#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F +#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D +#endif + +struct dcn31_watermarks; + +struct dcn31_smu_watermark_set { + struct dcn31_watermarks *wm_set; + union large_integer mc_address; +}; + +struct clk_mgr_dcn31 { + struct clk_mgr_internal base; + struct dcn31_smu_watermark_set smu_wm_set; +}; + +void dcn31_clk_mgr_construct(struct dc_context *ctx, + struct clk_mgr_dcn31 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg); + +void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); + +#endif //__DCN31_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c new file mode 100644 index 000000000000..66db5e988bc1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c @@ -0,0 +1,333 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "core_types.h" +#include "clk_mgr_internal.h" +#include "reg_helper.h" +#include "dm_helpers.h" +#include "dcn31_smu.h" + +#include "yellow_carp_offset.h" +#include "mp/mp_13_0_1_offset.h" +#include "mp/mp_13_0_1_sh_mask.h" + +#define REG(reg_name) \ + (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) + +#define FN(reg_name, field) \ + FD(reg_name##__##field) + +#define VBIOSSMC_MSG_TestMessage 0x1 +#define VBIOSSMC_MSG_GetSmuVersion 0x2 +#define VBIOSSMC_MSG_PowerUpGfx 0x3 +#define VBIOSSMC_MSG_SetDispclkFreq 0x4 +#define VBIOSSMC_MSG_SetDprefclkFreq 0x5 //Not used. DPRef is constant +#define VBIOSSMC_MSG_SetDppclkFreq 0x6 +#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7 +#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8 +#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x9 //Keep it in case VMIN dees not support phy clk +#define VBIOSSMC_MSG_GetFclkFrequency 0xA +#define VBIOSSMC_MSG_SetDisplayCount 0xB //Not used anymore +#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //Not used anymore +#define VBIOSSMC_MSG_UpdatePmeRestore 0xD +#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr +#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF +#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 +#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 +#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 +#define VBIOSSMC_MSG_GetDprefclkFreq 0x13 +#define VBIOSSMC_MSG_GetDtbclkFreq 0x14 +#define VBIOSSMC_MSG_AllowZstatesEntry 0x15 +#define VBIOSSMC_MSG_DisallowZstatesEntry 0x16 +#define VBIOSSMC_MSG_SetDtbClk 0x17 +#define VBIOSSMC_Message_Count 0x18 + +#define VBIOSSMC_Status_BUSY 0x0 +#define VBIOSSMC_Result_OK 0x1 +#define VBIOSSMC_Result_Failed 0xFF +#define VBIOSSMC_Result_UnknownCmd 0xFE +#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD +#define VBIOSSMC_Result_CmdRejectedBusy 0xFC + +/* + * Function to be used instead of REG_WAIT macro because the wait ends when + * the register is NOT EQUAL to zero, and because the translation in msg_if.h + * won't work with REG_WAIT. + */ +static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) +{ + uint32_t res_val = VBIOSSMC_Status_BUSY; + + do { + res_val = REG_READ(MP1_SMN_C2PMSG_91); + if (res_val != VBIOSSMC_Status_BUSY) + break; + + if (delay_us >= 1000) + msleep(delay_us/1000); + else if (delay_us > 0) + udelay(delay_us); + } while (max_retries--); + + return res_val; +} + +int dcn31_smu_send_msg_with_param( + struct clk_mgr_internal *clk_mgr, + unsigned int msg_id, unsigned int param) +{ + uint32_t result; + + result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); + ASSERT(result == VBIOSSMC_Result_OK); + + if (result == VBIOSSMC_Status_BUSY) { + return -1; + } + + /* First clear response register */ + REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); + + /* Set the parameter register for the SMU message, unit is Mhz */ + REG_WRITE(MP1_SMN_C2PMSG_83, param); + + /* Trigger the message transaction by writing the message ID */ + REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); + + result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); + + if (IS_SMU_TIMEOUT(result)) { + ASSERT(0); + dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); + } + + return REG_READ(MP1_SMN_C2PMSG_83); +} + +int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) +{ + return dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_GetSmuVersion, + 0); +} + + +int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) +{ + int actual_dispclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_dispclk_khz; + + /* Unit of SMU msg parameter is Mhz */ + actual_dispclk_set_mhz = dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDispclkFreq, + (requested_dispclk_khz + 999) / 1000); + + return actual_dispclk_set_mhz * 1000; +} + +int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) +{ + int actual_dprefclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return clk_mgr->base.dprefclk_khz; + + actual_dprefclk_set_mhz = dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDprefclkFreq, + (clk_mgr->base.dprefclk_khz + 999) / 1000); + + /* TODO: add code for programing DP DTO, currently this is down by command table */ + + return actual_dprefclk_set_mhz * 1000; +} + +int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) +{ + int actual_dcfclk_set_mhz = -1; + + if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) + return -1; + + if (!clk_mgr->smu_present) + return requested_dcfclk_khz; + + actual_dcfclk_set_mhz = dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetHardMinDcfclkByFreq, + (requested_dcfclk_khz + 999) / 1000); + + return actual_dcfclk_set_mhz * 1000; +} + +int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) +{ + int actual_min_ds_dcfclk_mhz = -1; + + if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) + return -1; + + if (!clk_mgr->smu_present) + return requested_min_ds_dcfclk_khz; + + actual_min_ds_dcfclk_mhz = dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetMinDeepSleepDcfclk, + (requested_min_ds_dcfclk_khz + 999) / 1000); + + return actual_min_ds_dcfclk_mhz * 1000; +} + +int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) +{ + int actual_dppclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_dpp_khz; + + actual_dppclk_set_mhz = dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDppclkFreq, + (requested_dpp_khz + 999) / 1000); + + return actual_dppclk_set_mhz * 1000; +} + +void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) +{ + if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) + return; + + if (!clk_mgr->smu_present) + return; + + //TODO: Work with smu team to define optimization options. + dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDisplayIdleOptimizations, + idle_info); +} + +void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) +{ + union display_idle_optimization_u idle_info = { 0 }; + + if (!clk_mgr->smu_present) + return; + + if (enable) { + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + } + + dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDisplayIdleOptimizations, + idle_info.data); +} + +void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_UpdatePmeRestore, + 0); +} + +void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param(clk_mgr, + VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high); +} + +void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param(clk_mgr, + VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low); +} + +void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param(clk_mgr, + VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS); +} + +void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param(clk_mgr, + VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS); +} + +void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support) +{ + //TODO: Work with smu team to define optimization options. + unsigned int msg_id; + + if (!clk_mgr->smu_present) + return; + + if (support) + msg_id = VBIOSSMC_MSG_AllowZstatesEntry; + else + msg_id = VBIOSSMC_MSG_DisallowZstatesEntry; + + dcn31_smu_send_msg_with_param( + clk_mgr, + msg_id, + 0); + +} + +/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ +void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) +{ + if (!clk_mgr->smu_present) + return; + + dcn31_smu_send_msg_with_param( + clk_mgr, + VBIOSSMC_MSG_SetDtbClk, + enable); +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h new file mode 100644 index 000000000000..cd0b7e1e685f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h @@ -0,0 +1,271 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DAL_DC_31_SMU_H_ +#define DAL_DC_31_SMU_H_ + +#ifndef PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_VERSION 4 + +typedef struct { + int32_t value; + uint32_t numFractionalBits; +} FloatInIntFormat_t; + +typedef enum { + DSPCLK_DCFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; // in MHz + uint16_t Vid; // min voltage in SVI3 VID +} DisplayClockTable_t; + +typedef struct { + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t WmType; // Used for normal pstate change or memory retraining + uint8_t Padding[2]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 +#define WM_PSTATE_CHG 0 +#define WM_RETRAINING 1 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +} Watermarks_t; + +typedef enum { + CUSTOM_DPM_SETTING_GFXCLK, + CUSTOM_DPM_SETTING_CCLK, + CUSTOM_DPM_SETTING_FCLK_CCX, + CUSTOM_DPM_SETTING_FCLK_GFX, + CUSTOM_DPM_SETTING_FCLK_STALLS, + CUSTOM_DPM_SETTING_LCLK, + CUSTOM_DPM_SETTING_COUNT, +} CUSTOM_DPM_SETTING_e; + +typedef struct { + uint8_t ActiveHystLimit; + uint8_t IdleHystLimit; + uint8_t FPS; + uint8_t MinActiveFreqType; + FloatInIntFormat_t MinActiveFreq; + FloatInIntFormat_t PD_Data_limit; + FloatInIntFormat_t PD_Data_time_constant; + FloatInIntFormat_t PD_Data_error_coeff; + FloatInIntFormat_t PD_Data_error_rate_coeff; +} DpmActivityMonitorCoeffExt_t; + +typedef struct { + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; +} CustomDpmSettings_t; + +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_VCN_DPM_LEVELS 8 +#define NUM_SOC_VOLTAGE_LEVELS 8 +#define NUM_DF_PSTATE_LEVELS 4 + +typedef enum{ + WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; + WCK_RATIO_1_2, + WCK_RATIO_1_4, + WCK_RATIO_MAX +} WCK_RATIO_e; + +typedef struct { + uint32_t FClk; + uint32_t MemClk; + uint32_t Voltage; + uint8_t WckRatio; + uint8_t Spare[3]; +} DfPstateTable_t; + +//Freq in MHz +//Voltage in milli volts with 2 fractional bits +typedef struct { + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + uint32_t VClocks[NUM_VCN_DPM_LEVELS]; + uint32_t DClocks[NUM_VCN_DPM_LEVELS]; + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; + DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS]; + + uint8_t NumDcfClkLevelsEnabled; + uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk + uint8_t NumSocClkLevelsEnabled; + uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk + uint8_t NumDfPstatesEnabled; + uint8_t spare[3]; + + uint32_t MinGfxClk; + uint32_t MaxGfxClk; +} DpmClocks_t; + + +// Throttler Status Bitmask +#define THROTTLER_STATUS_BIT_SPL 0 +#define THROTTLER_STATUS_BIT_FPPT 1 +#define THROTTLER_STATUS_BIT_SPPT 2 +#define THROTTLER_STATUS_BIT_SPPT_APU 3 +#define THROTTLER_STATUS_BIT_THM_CORE 4 +#define THROTTLER_STATUS_BIT_THM_GFX 5 +#define THROTTLER_STATUS_BIT_THM_SOC 6 +#define THROTTLER_STATUS_BIT_TDC_VDD 7 +#define THROTTLER_STATUS_BIT_TDC_SOC 8 +#define THROTTLER_STATUS_BIT_PROCHOT_CPU 9 +#define THROTTLER_STATUS_BIT_PROCHOT_GFX 10 +#define THROTTLER_STATUS_BIT_EDC_CPU 11 +#define THROTTLER_STATUS_BIT_EDC_GFX 12 + +typedef struct { + uint16_t GfxclkFrequency; //[MHz] + uint16_t SocclkFrequency; //[MHz] + uint16_t VclkFrequency; //[MHz] + uint16_t DclkFrequency; //[MHz] + uint16_t MemclkFrequency; //[MHz] + uint16_t spare; + + uint16_t GfxActivity; //[centi] + uint16_t UvdActivity; //[centi] + + uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC + uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC + uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC + + //3rd party tools in Windows need this info in the case of APUs + uint16_t CoreFrequency[8]; //[MHz] + uint16_t CorePower[8]; //[mW] + uint16_t CoreTemperature[8]; //[centi-Celsius] + uint16_t L3Frequency; //[MHz] + uint16_t L3Temperature; //[centi-Celsius] + + uint16_t GfxTemperature; //[centi-Celsius] + uint16_t SocTemperature; //[centi-Celsius] + uint16_t ThrottlerStatus; + + uint16_t CurrentSocketPower; //[mW] + uint16_t StapmOriginalLimit; //[W] + uint16_t StapmCurrentLimit; //[W] + uint16_t ApuPower; //[W] + uint16_t dGpuPower; //[W] + + uint16_t VddTdcValue; //[mA] + uint16_t SocTdcValue; //[mA] + uint16_t VddEdcValue; //[mA] + uint16_t SocEdcValue; //[mA] + + uint16_t InfrastructureCpuMaxFreq; //[MHz] + uint16_t InfrastructureGfxMaxFreq; //[MHz] +} SmuMetrics_t; + + +// Workload bits +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 +#define WORKLOAD_PPLIB_VIDEO_BIT 2 +#define WORKLOAD_PPLIB_VR_BIT 3 +#define WORKLOAD_PPLIB_COMPUTE_BIT 4 +#define WORKLOAD_PPLIB_CUSTOM_BIT 5 +#define WORKLOAD_PPLIB_COUNT 6 + +#define TABLE_BIOS_IF 0 // Called by BIOS +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS +#define TABLE_CUSTOM_DPM 2 // Called by Driver +#define TABLE_SPARE1 3 +#define TABLE_DPMCLOCKS 4 // Called by Driver +#define TABLE_MOMENTARY_PM 5 // Called by Tools +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log +#define TABLE_SMU_METRICS 7 // Called by Driver +#define TABLE_COUNT 8 + +#endif + +struct dcn31_watermarks { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +}; + +struct dcn31_smu_dpm_clks { + DpmClocks_t *dpm_clks; + union large_integer mc_address; +}; + +/* TODO: taken from vgh, may not be correct */ +struct display_idle_optimization { + unsigned int df_request_disabled : 1; + unsigned int phy_ref_clk_off : 1; + unsigned int s0i2_rdy : 1; + unsigned int reserved : 29; +}; + +union display_idle_optimization_u { + struct display_idle_optimization idle_info; + uint32_t data; +}; + +int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); +int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); +int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); +int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); +int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); +int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); +void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); +void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); +void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); +void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); +void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); +void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); +void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); + +void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support); +void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); + +#endif /* DAL_DC_31_SMU_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4713f09bcbf1..605e297b7a59 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -59,7 +59,6 @@ #include "dc_link_ddc.h" #include "dm_helpers.h" #include "mem_input.h" -#include "hubp.h" #include "dc_link_dp.h" #include "dc_dmub_srv.h" @@ -304,7 +303,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust) { - int i = 0; + int i; bool ret = false; stream->adjust.v_total_max = adjust->v_total_max; @@ -326,13 +325,55 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, return ret; } +/** + ***************************************************************************** + * Function: dc_stream_get_last_vrr_vtotal + * + * @brief + * Looks up the pipe context of dc_stream_state and gets the + * last VTOTAL used by DRR (Dynamic Refresh Rate) + * + * @param [in] dc: dc reference + * @param [in] stream: Initial dc stream state + * @param [in] adjust: Updated parameters for vertical_total_min and + * vertical_total_max + ***************************************************************************** + */ +bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, + struct dc_stream_state *stream, + uint32_t *refresh_rate) +{ + bool status = false; + + int i = 0; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream == stream && pipe->stream_res.tg) { + /* Only execute if a function pointer has been defined for + * the DC version in question + */ + if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { + pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); + + status = true; + + break; + } + } + } + + return status; +} + bool dc_stream_get_crtc_position(struct dc *dc, struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ const struct dc_stream_state *stream = streams[0]; - int i = 0; + int i; bool ret = false; struct crtc_position position; @@ -539,7 +580,7 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, enum dc_dynamic_expansion option) { /* OPP FMT dyn expansion updates*/ - int i = 0; + int i; struct pipe_ctx *pipe_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -597,7 +638,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream, bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { - int i = 0; + int i; bool ret = false; struct pipe_ctx *pipes; @@ -614,7 +655,7 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stre bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { - int i = 0; + int i; bool ret = false; struct pipe_ctx *pipes; @@ -640,8 +681,7 @@ void dc_stream_set_static_screen_params(struct dc *dc, int num_streams, const struct dc_static_screen_params *params) { - int i = 0; - int j = 0; + int i, j; struct pipe_ctx *pipes_affected[MAX_PIPES]; int num_pipes_affected = 0; @@ -896,7 +936,7 @@ static void disable_all_writeback_pipes_for_stream( static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock) { - int i = 0; + int i; /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ if (dc->hwss.interdependent_update_lock) @@ -1156,7 +1196,7 @@ static void enable_timing_multisync( struct dc *dc, struct dc_state *ctx) { - int i = 0, multisync_count = 0; + int i, multisync_count = 0; int pipe_count = dc->res_pool->pipe_count; struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; @@ -1484,6 +1524,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) return stream_mask; } +#if defined(CONFIG_DRM_AMD_DC_DCN) +void dc_z10_restore(struct dc *dc) +{ + if (dc->hwss.z10_restore) + dc->hwss.z10_restore(dc); +} +#endif /* * Applies given context to HW and copy it into current context. * It's up to the user to release the src context afterwards. @@ -1497,6 +1544,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; #if defined(CONFIG_DRM_AMD_DC_DCN) + dc_z10_restore(dc); dc_allow_idle_optimizations(dc, false); #endif @@ -1919,8 +1967,13 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa if (u->plane_info->dcc.enable != u->surface->dcc.enable || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) { + /* During DCC on/off, stutter period is calculated before + * DCC has fully transitioned. This results in incorrect + * stutter period calculation. Triggering a full update will + * recalculate stutter period. + */ update_flags->bits.dcc_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_FULL); } if (resource_pixel_format_to_bpp(u->plane_info->format) != @@ -2571,6 +2624,10 @@ static void commit_planes_for_stream(struct dc *dc, int i, j; struct pipe_ctx *top_pipe_to_program = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCN) + dc_z10_restore(dc); +#endif + if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower @@ -2664,7 +2721,6 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.interdependent_update_lock(dc, context, false); else dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); - dc->hwss.post_unlock_program_front_end(dc, context); return; } @@ -2765,6 +2821,7 @@ static void commit_planes_for_stream(struct dc *dc, plane_state->flip_immediate); } } + /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; @@ -2787,6 +2844,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.update_plane_addr(dc, pipe_ctx); } } + } if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) @@ -3025,6 +3083,9 @@ void dc_set_power_state( case DC_ACPI_CM_POWER_STATE_D0: dc_resource_state_construct(dc, dc->current_state); +#if defined(CONFIG_DRM_AMD_DC_DCN) + dc_z10_restore(dc); +#endif if (dc->ctx->dmub_srv) dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv); @@ -3219,19 +3280,6 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) } } -void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream) -{ - int i; - - for (i = 0; i < dc->res_pool->pipe_count; i++) - if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - struct timing_generator *tg = - dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; - tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); - break; - } -} - void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info) { info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz; @@ -3270,10 +3318,13 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable) continue; if (link->psr_settings.psr_feature_enabled) { - if (enable && !link->psr_settings.psr_allow_active) - return dc_link_set_psr_allow_active(link, true, false, false); - else if (!enable && link->psr_settings.psr_allow_active) - return dc_link_set_psr_allow_active(link, false, true, false); + if (enable && !link->psr_settings.psr_allow_active) { + if (!dc_link_set_psr_allow_active(link, true, false, false)) + return false; + } else if (!enable && link->psr_settings.psr_allow_active) { + if (!dc_link_set_psr_allow_active(link, false, true, false)) + return false; + } } } @@ -3287,7 +3338,7 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow) if (dc->debug.disable_idle_power_optimizations) return; - if (dc->clk_mgr->funcs->is_smu_present) + if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present) if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) return; @@ -3348,18 +3399,10 @@ void dc_hardware_release(struct dc *dc) #endif /** - ***************************************************************************** - * Function: dc_enable_dmub_notifications + * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled + * @dc: dc structure * - * @brief - * Returns whether dmub notification can be enabled - * - * @param - * [in] dc: dc structure - * - * @return - * True to enable dmub notifications, False otherwise - ***************************************************************************** + * Returns: True to enable dmub notifications, False otherwise */ bool dc_enable_dmub_notifications(struct dc *dc) { @@ -3368,21 +3411,13 @@ bool dc_enable_dmub_notifications(struct dc *dc) } /** - ***************************************************************************** - * Function: dc_process_dmub_aux_transfer_async + * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message + * Sets port index appropriately for legacy DDC + * @dc: dc structure + * @link_index: link index + * @payload: aux payload * - * @brief - * Submits aux command to dmub via inbox message - * Sets port index appropriately for legacy DDC - * - * @param - * [in] dc: dc structure - * [in] link_index: link index - * [in] payload: aux payload - * - * @return - * True if successful, False if failure - ***************************************************************************** + * Returns: True if successful, False if failure */ bool dc_process_dmub_aux_transfer_async(struct dc *dc, uint32_t link_index, @@ -3441,16 +3476,8 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, } /** - ***************************************************************************** - * Function: dc_disable_accelerated_mode - * - * @brief - * disable accelerated mode - * - * @param - * [in] dc: dc structure - * - ***************************************************************************** + * dc_disable_accelerated_mode - disable accelerated mode + * @dc: dc structure */ void dc_disable_accelerated_mode(struct dc *dc) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 2a9080400bdd..9039fb134db5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -291,3 +291,136 @@ bool hwss_wait_for_blank_complete( return true; } + +void get_mpctree_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + const struct tg_color pipe_colors[6] = { + {MAX_TG_COLOR_VALUE, 0, 0}, /* red */ + {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */ + {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */ + {0, MAX_TG_COLOR_VALUE, 0}, /* green */ + {0, 0, MAX_TG_COLOR_VALUE}, /* blue */ + {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */ + }; + + struct pipe_ctx *top_pipe = pipe_ctx; + + while (top_pipe->top_pipe) + top_pipe = top_pipe->top_pipe; + + *color = pipe_colors[top_pipe->pipe_idx]; +} + +void get_surface_visual_confirm_color( + const struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + + switch (pipe_ctx->plane_res.scl_data.format) { + case PIXEL_FORMAT_ARGB8888: + /* set border color to red */ + color->color_r_cr = color_value; + if (pipe_ctx->plane_state->layer_index > 0) { + /* set border color to pink */ + color->color_b_cb = color_value; + color->color_g_y = color_value * 0.5; + } + break; + + case PIXEL_FORMAT_ARGB2101010: + /* set border color to blue */ + color->color_b_cb = color_value; + if (pipe_ctx->plane_state->layer_index > 0) { + /* set border color to cyan */ + color->color_g_y = color_value; + } + break; + case PIXEL_FORMAT_420BPP8: + /* set border color to green */ + color->color_g_y = color_value; + break; + case PIXEL_FORMAT_420BPP10: + /* set border color to yellow */ + color->color_g_y = color_value; + color->color_r_cr = color_value; + break; + case PIXEL_FORMAT_FP16: + /* set border color to white */ + color->color_r_cr = color_value; + color->color_b_cb = color_value; + color->color_g_y = color_value; + if (pipe_ctx->plane_state->layer_index > 0) { + /* set border color to orange */ + color->color_g_y = 0.22 * color_value; + color->color_b_cb = 0; + } + break; + default: + break; + } +} + +void get_hdr_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + + /* Determine the overscan color based on the top-most (desktop) plane's context */ + struct pipe_ctx *top_pipe_ctx = pipe_ctx; + + while (top_pipe_ctx->top_pipe != NULL) + top_pipe_ctx = top_pipe_ctx->top_pipe; + + switch (top_pipe_ctx->plane_res.scl_data.format) { + case PIXEL_FORMAT_ARGB2101010: + if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { + /* HDR10, ARGB2101010 - set border color to red */ + color->color_r_cr = color_value; + } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { + /* FreeSync 2 ARGB2101010 - set border color to pink */ + color->color_r_cr = color_value; + color->color_b_cb = color_value; + } + break; + case PIXEL_FORMAT_FP16: + if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { + /* HDR10, FP16 - set border color to blue */ + color->color_b_cb = color_value; + } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { + /* FreeSync 2 HDR - set border color to green */ + color->color_g_y = color_value; + } + break; + default: + /* SDR - set border color to Gray */ + color->color_r_cr = color_value/2; + color->color_b_cb = color_value/2; + color->color_g_y = color_value/2; + break; + } +} + +void get_surface_tile_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + /* Determine the overscan color based on the bottom-most plane's context */ + struct pipe_ctx *bottom_pipe_ctx = pipe_ctx; + + while (bottom_pipe_ctx->bottom_pipe != NULL) + bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; + + switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { + case DC_SW_LINEAR: + /* LINEAR Surface - set border color to red */ + color->color_r_cr = color_value; + break; + default: + break; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c1f5474c205a..6132b645bfd1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -48,6 +48,8 @@ #include "dce/dmub_psr.h" #include "dmub/dmub_srv.h" #include "inc/hw/panel_cntl.h" +#include "inc/link_enc_cfg.h" +#include "inc/link_dpcd.h" #define DC_LOGGER_INIT(logger) @@ -58,20 +60,6 @@ #define RETIMER_REDRIVER_INFO(...) \ DC_LOG_RETIMER_REDRIVER( \ __VA_ARGS__) -/******************************************************************************* - * Private structures - ******************************************************************************/ - -enum { - PEAK_FACTOR_X1000 = 1006, - /* - * Some receivers fail to train on first try and are good - * on subsequent tries. 2 retries should be plenty. If we - * don't have a successful training then we don't expect to - * ever get one. - */ - LINK_TRAINING_MAX_VERIFY_RETRY = 2 -}; /******************************************************************************* * Private functions @@ -247,6 +235,16 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type) link->dc->hwss.edp_wait_for_hpd_ready(link, true); } + /* Link may not have physical HPD pin. */ + if (link->ep_type != DISPLAY_ENDPOINT_PHY) { + if (link->hpd_status) + *type = dc_connection_single; + else + *type = dc_connection_none; + + return true; + } + /* todo: may need to lock gpio access */ hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); @@ -432,8 +430,18 @@ bool dc_link_is_dp_sink_present(struct dc_link *link) static enum signal_type link_detect_sink(struct dc_link *link, enum dc_detect_reason reason) { - enum signal_type result = get_basic_signal_type(link->link_enc->id, - link->link_id); + enum signal_type result; + struct graphics_object_id enc_id; + + if (link->is_dig_mapping_flexible) + enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; + else + enc_id = link->link_enc->id; + result = get_basic_signal_type(enc_id, link->link_id); + + /* Use basic signal type for link without physical connector. */ + if (link->ep_type != DISPLAY_ENDPOINT_PHY) + return result; /* Internal digital encoder will detect only dongles * that require digital signal @@ -697,11 +705,9 @@ static void read_current_link_settings_on_detect(struct dc_link *link) static bool detect_dp(struct dc_link *link, struct display_sink_capability *sink_caps, - bool *converter_disable_audio, - struct audio_support *audio_support, enum dc_detect_reason reason) { - bool boot = false; + struct audio_support *audio_support = &link->dc->res_pool->audio_support; sink_caps->signal = link_detect_sink(link, reason); sink_caps->transaction_type = @@ -724,59 +730,12 @@ static bool detect_dp(struct dc_link *link, * of this function). */ query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link); #endif - /* - * This call will initiate MST topology discovery. Which - * will detect MST ports and add new DRM connector DRM - * framework. Then read EDID via remote i2c over aux. In - * the end, will notify DRM detect result and save EDID - * into DRM framework. - * - * .detect is called by .fill_modes. - * .fill_modes is called by user mode ioctl - * DRM_IOCTL_MODE_GETCONNECTOR. - * - * .get_modes is called by .fill_modes. - * - * call .get_modes, AMDGPU DM implementation will create - * new dc_sink and add to dc_link. For long HPD plug - * in/out, MST has its own handle. - * - * Therefore, just after dc_create, link->sink is not - * created for MST until user mode app calls - * DRM_IOCTL_MODE_GETCONNECTOR. - * - * Need check ->sink usages in case ->sink = NULL - * TODO: s3 resume check - */ - if (reason == DETECT_REASON_BOOT) - boot = true; - - dm_helpers_dp_update_branch_info(link->ctx, link); - - if (!dm_helpers_dp_mst_start_top_mgr(link->ctx, - link, boot)) { - /* MST not supported */ - link->type = dc_connection_single; - sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; - } } if (link->type != dc_connection_mst_branch && - is_dp_active_dongle(link)) { - /* DP active dongles */ - link->type = dc_connection_active_dongle; - if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) { - /* - * active dongle unplug processing for short irq - */ - link_disconnect_sink(link); - return true; - } - - if (link->dpcd_caps.dongle_type != - DISPLAY_DONGLE_DP_HDMI_CONVERTER) - *converter_disable_audio = true; - } + is_dp_branch_device(link)) + /* DP SST branch */ + link->type = dc_connection_sst_branch; } else { /* DP passive dongles */ sink_caps->signal = dp_passive_dongle_detection(link->ddc, @@ -862,7 +821,7 @@ static bool dc_link_detect_helper(struct dc_link *link, { struct dc_sink_init_data sink_init_data = { 0 }; struct display_sink_capability sink_caps = { 0 }; - uint8_t i; + uint32_t i; bool converter_disable_audio = false; struct audio_support *aud_support = &link->dc->res_pool->audio_support; bool same_edid = false; @@ -871,7 +830,6 @@ static bool dc_link_detect_helper(struct dc_link *link, struct dc_sink *sink = NULL; struct dc_sink *prev_sink = NULL; struct dpcd_caps prev_dpcd_caps; - bool same_dpcd = true; enum dc_connection_type new_connection_type = dc_connection_none; enum dc_connection_type pre_connection_type = dc_connection_none; bool perform_dp_seamless_boot = false; @@ -882,9 +840,10 @@ static bool dc_link_detect_helper(struct dc_link *link, if (dc_is_virtual_signal(link->connector_signal)) return false; - if ((link->connector_signal == SIGNAL_TYPE_LVDS || - link->connector_signal == SIGNAL_TYPE_EDP) && - link->local_sink) { + if (((link->connector_signal == SIGNAL_TYPE_LVDS || + link->connector_signal == SIGNAL_TYPE_EDP) && + (!link->dc->config.allow_edp_hotplug_detection)) && + link->local_sink) { // need to re-write OUI and brightness in resume case if (link->connector_signal == SIGNAL_TYPE_EDP) { dpcd_set_source_specific_data(link); @@ -954,41 +913,19 @@ static bool dc_link_detect_helper(struct dc_link *link, case SIGNAL_TYPE_DISPLAY_PORT: { /* wa HPD high coming too early*/ - if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { + if (link->ep_type == DISPLAY_ENDPOINT_PHY && + link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { /* if alt mode times out, return false */ if (!wait_for_entering_dp_alt_mode(link)) return false; } - if (!detect_dp(link, &sink_caps, - &converter_disable_audio, - aud_support, reason)) { + if (!detect_dp(link, &sink_caps, reason)) { if (prev_sink) dc_sink_release(prev_sink); return false; } - // Check if dpcp block is the same - if (prev_sink) { - if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, - sizeof(struct dpcd_caps))) - same_dpcd = false; - } - /* Active dongle downstream unplug*/ - if (link->type == dc_connection_active_dongle && - link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { - if (prev_sink) - /* Downstream unplug */ - dc_sink_release(prev_sink); - return true; - } - - // link switch from MST to non-MST stop topology manager - if (pre_connection_type == dc_connection_mst_branch && - link->type != dc_connection_mst_branch) { - dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); - } - if (link->type == dc_connection_mst_branch) { LINK_INFO("link=%d, mst branch is now Connected\n", link->link_index); @@ -999,15 +936,69 @@ static bool dc_link_detect_helper(struct dc_link *link, */ dp_verify_mst_link_cap(link); - if (prev_sink) - dc_sink_release(prev_sink); - return false; + /* + * This call will initiate MST topology discovery. Which + * will detect MST ports and add new DRM connector DRM + * framework. Then read EDID via remote i2c over aux. In + * the end, will notify DRM detect result and save EDID + * into DRM framework. + * + * .detect is called by .fill_modes. + * .fill_modes is called by user mode ioctl + * DRM_IOCTL_MODE_GETCONNECTOR. + * + * .get_modes is called by .fill_modes. + * + * call .get_modes, AMDGPU DM implementation will create + * new dc_sink and add to dc_link. For long HPD plug + * in/out, MST has its own handle. + * + * Therefore, just after dc_create, link->sink is not + * created for MST until user mode app calls + * DRM_IOCTL_MODE_GETCONNECTOR. + * + * Need check ->sink usages in case ->sink = NULL + * TODO: s3 resume check + */ + + dm_helpers_dp_update_branch_info(link->ctx, link); + if (dm_helpers_dp_mst_start_top_mgr(link->ctx, + link, reason == DETECT_REASON_BOOT)) { + if (prev_sink) + dc_sink_release(prev_sink); + return false; + } else { + link->type = dc_connection_sst_branch; + sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT; + } } + /* Active SST downstream branch device unplug*/ + if (link->type == dc_connection_sst_branch && + link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { + if (prev_sink) + /* Downstream unplug */ + dc_sink_release(prev_sink); + return true; + } + + /* disable audio for non DP to HDMI active sst converter */ + if (link->type == dc_connection_sst_branch && + is_dp_active_dongle(link) && + (link->dpcd_caps.dongle_type != + DISPLAY_DONGLE_DP_HDMI_CONVERTER)) + converter_disable_audio = true; + + // link switch from MST to non-MST stop topology manager + if (pre_connection_type == dc_connection_mst_branch && + link->type != dc_connection_mst_branch) + dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); + + // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified. if (reason == DETECT_REASON_BOOT && - !dc_ctx->dc->config.power_down_display_on_boot && - link->link_status.link_active) + !dc_ctx->dc->config.power_down_display_on_boot && + link->link_status.link_active) perform_dp_seamless_boot = true; if (perform_dp_seamless_boot) { @@ -1076,24 +1067,6 @@ static bool dc_link_detect_helper(struct dc_link *link, dc_is_dvi_signal(link->connector_signal)) { if (prev_sink) dc_sink_release(prev_sink); - link_disconnect_sink(link); - - return false; - } - /* - * Abort detection for DP connectors if we have - * no EDID and connector is active converter - * as there are no display downstream - * - */ - if (dc_is_dp_sst_signal(link->connector_signal) && - (link->dpcd_caps.dongle_type == - DISPLAY_DONGLE_DP_VGA_CONVERTER || - link->dpcd_caps.dongle_type == - DISPLAY_DONGLE_DP_DVI_CONVERTER)) { - if (prev_sink) - dc_sink_release(prev_sink); - link_disconnect_sink(link); return false; } @@ -1208,11 +1181,11 @@ static bool dc_link_detect_helper(struct dc_link *link, link->dongle_max_pix_clk = 0; } - LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n", + LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), - prev_sink, same_dpcd, same_edid); + prev_sink, same_edid); if (prev_sink) dc_sink_release(prev_sink); @@ -1224,14 +1197,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) { const struct dc *dc = link->dc; bool ret; + bool can_apply_seamless_boot = false; + int i; + + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { + can_apply_seamless_boot = true; + break; + } + } /* get out of low power state */ - clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); + if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT) + clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); ret = dc_link_detect_helper(link, reason); /* Go back to power optimized state */ - clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); + if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT) + clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); return ret; } @@ -1485,7 +1469,8 @@ static bool dc_link_construct(struct dc_link *link, link->connector_signal = SIGNAL_TYPE_EDP; if (link->hpd_gpio) { - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + if (!link->dc->config.allow_edp_hotplug_detection) + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; link->irq_source_hpd_rx = dal_irq_get_rx_source(link->hpd_gpio); } @@ -1734,6 +1719,8 @@ static enum dc_status enable_link_dp(struct dc_state *state, bool apply_seamless_boot_optimization = false; uint32_t bl_oled_enable_delay = 50; // in ms const uint32_t post_oui_delay = 30; // 30ms + /* Reduce link bandwidth between failed link training attempts. */ + bool do_fallback = false; // check for seamless boot for (i = 0; i < state->stream_count; i++) { @@ -1772,7 +1759,8 @@ static enum dc_status enable_link_dp(struct dc_state *state, skip_video_pattern, LINK_TRAINING_ATTEMPTS, pipe_ctx, - pipe_ctx->stream->signal)) { + pipe_ctx->stream->signal, + do_fallback)) { link->cur_link_settings = link_settings; status = DC_OK; } else { @@ -2664,16 +2652,24 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, struct dc *dc = link->ctx->dc; struct dmcu *dmcu = dc->res_pool->dmcu; struct dmub_psr *psr = dc->res_pool->psr; + unsigned int panel_inst; if (psr == NULL && force_static) return false; + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return false; + link->psr_settings.psr_allow_active = allow_active; +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (!allow_active) + dc_z10_restore(dc); +#endif if (psr != NULL && link->psr_settings.psr_feature_enabled) { if (force_static && psr->funcs->psr_force_static) - psr->funcs->psr_force_static(psr); - psr->funcs->psr_enable(psr, allow_active, wait); + psr->funcs->psr_force_static(psr, panel_inst); + psr->funcs->psr_enable(psr, allow_active, wait, panel_inst); } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled) dmcu->funcs->set_psr_enable(dmcu, allow_active, wait); else @@ -2687,9 +2683,13 @@ bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) struct dc *dc = link->ctx->dc; struct dmcu *dmcu = dc->res_pool->dmcu; struct dmub_psr *psr = dc->res_pool->psr; + unsigned int panel_inst; + + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return false; if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_state(psr, state); + psr->funcs->psr_get_state(psr, state, panel_inst); else if (dmcu != NULL && link->psr_settings.psr_feature_enabled) dmcu->funcs->get_psr_state(dmcu, state); @@ -2739,6 +2739,7 @@ bool dc_link_setup_psr(struct dc_link *link, struct dmcu *dmcu; struct dmub_psr *psr; int i; + unsigned int panel_inst; /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; @@ -2754,6 +2755,9 @@ bool dc_link_setup_psr(struct dc_link *link, if (!dmcu && !psr) return false; + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return false; + memset(&psr_configuration, 0, sizeof(psr_configuration)); @@ -2838,8 +2842,16 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->psr_level.u32all = 0; /*skip power down the single pipe since it blocks the cstate*/ +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (link->ctx->asic_id.chip_family >= FAMILY_RV) { + psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; + if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10) + psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false; + } +#else if (link->ctx->asic_id.chip_family >= FAMILY_RV) psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; +#endif /* SMU will perform additional powerdown sequence. * For unsupported ASICs, set psr_level flag to skip PSR @@ -2860,7 +2872,8 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->frame_delay = 0; if (psr) - link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context); + link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, + link, psr_context, panel_inst); else link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context); @@ -2878,10 +2891,14 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency) { struct dc *dc = link->ctx->dc; struct dmub_psr *psr = dc->res_pool->psr; + unsigned int panel_inst; - // PSR residency measurements only supported on DMCUB + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return; + + /* PSR residency measurements only supported on DMCUB */ if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_residency(psr, residency); + psr->funcs->psr_get_residency(psr, residency, panel_inst); else *residency = 0; } @@ -3171,8 +3188,14 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) dp_get_panel_mode(pipe_ctx->stream->link); config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; + /*stream_enc_inst*/ config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; +#if defined(CONFIG_DRM_AMD_DC_DCN) + config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; + config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; + config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; +#endif config.dpms_off = dpms_off; config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP); @@ -3493,9 +3516,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing( uint32_t kbps; #if defined(CONFIG_DRM_AMD_DC_DCN) - if (timing->flags.DSC) { - return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel); - } + if (timing->flags.DSC) + return dc_dsc_stream_bandwidth_in_kbps(timing, + timing->dsc_cfg.bits_per_pixel, + timing->dsc_cfg.num_slices_h, + timing->dsc_cfg.is_dp); #endif switch (timing->display_color_depth) { @@ -3557,19 +3582,6 @@ void dc_link_set_drive_settings(struct dc *dc, dc_link_dp_set_drive_settings(dc->links[i], lt_settings); } -void dc_link_perform_link_training(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern) -{ - int i; - - for (i = 0; i < dc->link_count; i++) - dc_link_dp_perform_link_training( - dc->links[i], - link_setting, - skip_video_pattern); -} - void dc_link_set_preferred_link_settings(struct dc *dc, struct dc_link_settings *link_setting, struct dc_link *link) @@ -3720,8 +3732,22 @@ void dc_link_overwrite_extended_receiver_cap( bool dc_link_is_fec_supported(const struct dc_link *link) { + struct link_encoder *link_enc = NULL; + + /* Links supporting dynamically assigned link encoder will be assigned next + * available encoder if one not already assigned. + */ + if (link->is_dig_mapping_flexible && + link->dc->res_pool->funcs->link_encs_assign) { + link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); + if (link_enc == NULL) + link_enc = link_enc_cfg_get_next_avail_link_enc(link->dc, link->dc->current_state); + } else + link_enc = link->link_enc; + ASSERT(link_enc); + return (dc_is_dp_signal(link->connector_signal) && - link->link_enc->features.fec_supported && + link_enc->features.fec_supported && link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index 64414c51312d..ba6b56f20269 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -658,7 +658,10 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result) { - return dce_aux_transfer_raw(ddc, payload, operation_result); + if (dc_enable_dmub_notifications(ddc->ctx->dc)) + return dce_aux_transfer_dmub_raw(ddc, payload, operation_result); + else + return dce_aux_transfer_raw(ddc, payload, operation_result); } /* dc_link_aux_transfer_with_retries() - Attempt to submit an @@ -682,6 +685,10 @@ bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc, bool result = false; struct ddc *ddc_pin = ddc->ddc_pin; + /* Do not try to access nonexistent DDC pin. */ + if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY) + return true; + if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) { ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout); result = true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 3ff3d9e90983..b8832bdde2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -14,6 +14,7 @@ #include "dpcd_defs.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" +#include "inc/link_enc_cfg.h" /*Travis*/ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; @@ -24,7 +25,7 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; link->ctx->logger #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ -#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 +#include "link_dpcd.h" /* maximum pre emphasis level allowed for each voltage swing level*/ static const enum dc_pre_emphasis @@ -38,14 +39,6 @@ enum { POST_LT_ADJ_REQ_TIMEOUT = 200 }; -enum { - LINK_TRAINING_MAX_RETRY_COUNT = 5, - /* to avoid infinite loop where-in the receiver - * switches between different VS - */ - LINK_TRAINING_MAX_CR_RETRY = 100 -}; - static bool decide_fallback_link_setting( struct dc_link_settings initial_link_settings, struct dc_link_settings *current_link_setting, @@ -96,7 +89,7 @@ static uint32_t get_eq_training_aux_rd_interval( return wait_in_micro_secs; } -static void wait_for_training_aux_rd_interval( +void dp_wait_for_training_aux_rd_interval( struct dc_link *link, uint32_t wait_in_micro_secs) { @@ -107,10 +100,50 @@ static void wait_for_training_aux_rd_interval( wait_in_micro_secs); } +enum dpcd_training_patterns + dc_dp_training_pattern_to_dpcd_training_pattern( + struct dc_link *link, + enum dc_dp_training_pattern pattern) +{ + enum dpcd_training_patterns dpcd_tr_pattern = + DPCD_TRAINING_PATTERN_VIDEOIDLE; + + switch (pattern) { + case DP_TRAINING_PATTERN_SEQUENCE_1: + dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1; + break; + case DP_TRAINING_PATTERN_SEQUENCE_2: + dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2; + break; + case DP_TRAINING_PATTERN_SEQUENCE_3: + dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; + break; + case DP_TRAINING_PATTERN_SEQUENCE_4: + dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; + break; + case DP_TRAINING_PATTERN_VIDEOIDLE: + dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE; + break; + default: + ASSERT(0); + DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", + __func__, pattern); + break; + } + + return dpcd_tr_pattern; +} + static void dpcd_set_training_pattern( struct dc_link *link, - union dpcd_training_pattern dpcd_pattern) + enum dc_dp_training_pattern training_pattern) { + union dpcd_training_pattern dpcd_pattern = { {0} }; + + dpcd_pattern.v1_4.TRAINING_PATTERN_SET = + dc_dp_training_pattern_to_dpcd_training_pattern( + link, training_pattern); + core_link_write_dpcd( link, DP_TRAINING_PATTERN_SET, @@ -132,10 +165,22 @@ static enum dc_dp_training_pattern decide_cr_training_pattern( static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link, const struct dc_link_settings *link_settings) { + struct link_encoder *link_enc; enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2; - struct encoder_feature_support *features = &link->link_enc->features; + struct encoder_feature_support *features; struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + /* Access link encoder capability based on whether it is statically + * or dynamically assigned to a link. + */ + if (link->is_dig_mapping_flexible && + link->dc->res_pool->funcs->link_encs_assign) + link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); + else + link_enc = link->link_enc; + ASSERT(link_enc); + features = &link_enc->features; + if (features->flags.bits.IS_TPS3_CAPABLE) highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3; @@ -153,11 +198,12 @@ static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *li return DP_TRAINING_PATTERN_SEQUENCE_2; } -static void dpcd_set_link_settings( +enum dc_status dpcd_set_link_settings( struct dc_link *link, const struct link_training_settings *lt_settings) { uint8_t rate; + enum dc_status status; union down_spread_ctrl downspread = { {0} }; union lane_count_set lane_count_set = { {0} }; @@ -172,15 +218,16 @@ static void dpcd_set_link_settings( lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; - if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) { + if (link->ep_type == DISPLAY_ENDPOINT_PHY && + lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) { lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED; } - core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, + status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, &downspread.raw, sizeof(downspread)); - core_link_write_dpcd(link, DP_LANE_COUNT_SET, + status = core_link_write_dpcd(link, DP_LANE_COUNT_SET, &lane_count_set.raw, 1); if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && @@ -196,12 +243,12 @@ static void dpcd_set_link_settings( core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, supported_link_rates, sizeof(supported_link_rates)); } - core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); - core_link_write_dpcd(link, DP_LINK_RATE_SET, + status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); + status = core_link_write_dpcd(link, DP_LINK_RATE_SET, <_settings->link_settings.link_rate_set, 1); } else { rate = (uint8_t) (lt_settings->link_settings.link_rate); - core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); + status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); } if (rate) { @@ -225,40 +272,11 @@ static void dpcd_set_link_settings( DP_DOWNSPREAD_CTRL, lt_settings->link_settings.link_spread); } + + return status; } -static enum dpcd_training_patterns - dc_dp_training_pattern_to_dpcd_training_pattern( - struct dc_link *link, - enum dc_dp_training_pattern pattern) -{ - enum dpcd_training_patterns dpcd_tr_pattern = - DPCD_TRAINING_PATTERN_VIDEOIDLE; - - switch (pattern) { - case DP_TRAINING_PATTERN_SEQUENCE_1: - dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1; - break; - case DP_TRAINING_PATTERN_SEQUENCE_2: - dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2; - break; - case DP_TRAINING_PATTERN_SEQUENCE_3: - dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; - break; - case DP_TRAINING_PATTERN_SEQUENCE_4: - dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; - break; - default: - ASSERT(0); - DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", - __func__, pattern); - break; - } - - return dpcd_tr_pattern; -} - -static uint8_t dc_dp_initialize_scrambling_data_symbols( +uint8_t dc_dp_initialize_scrambling_data_symbols( struct dc_link *link, enum dc_dp_training_pattern pattern) { @@ -407,7 +425,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( link->cur_lane_setting = lt_settings->lane_settings[0]; } -static bool is_cr_done(enum dc_lane_count ln_count, +bool dp_is_cr_done(enum dc_lane_count ln_count, union lane_status *dpcd_lane_status) { uint32_t lane; @@ -419,24 +437,34 @@ static bool is_cr_done(enum dc_lane_count ln_count, return true; } -static bool is_ch_eq_done(enum dc_lane_count ln_count, - union lane_status *dpcd_lane_status, - union lane_align_status_updated *lane_status_updated) +bool dp_is_ch_eq_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status) { + bool done = true; uint32_t lane; - if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE) - return false; - else { - for (lane = 0; lane < (uint32_t)(ln_count); lane++) { - if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 || - !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0) - return false; - } - } - return true; + for (lane = 0; lane < (uint32_t)(ln_count); lane++) + if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0) + done = false; + return done; } -static void update_drive_settings( +bool dp_is_symbol_locked(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status) +{ + bool locked = true; + uint32_t lane; + for (lane = 0; lane < (uint32_t)(ln_count); lane++) + if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0) + locked = false; + return locked; +} + +bool dp_is_interlane_aligned(union lane_align_status_updated align_status) +{ + return align_status.bits.INTERLANE_ALIGN_DONE == 1; +} + +void dp_update_drive_settings( struct link_training_settings *dest, struct link_training_settings src) { @@ -580,7 +608,7 @@ static void find_max_drive_settings( } -static void get_lane_status_and_drive_settings( +enum dc_status dp_get_lane_status_and_drive_settings( struct dc_link *link, const struct link_training_settings *link_training_setting, union lane_status *ln_status, @@ -595,6 +623,7 @@ static void get_lane_status_and_drive_settings( union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; struct link_training_settings request_settings = { {0} }; uint32_t lane; + enum dc_status status; memset(req_settings, '\0', sizeof(struct link_training_settings)); @@ -605,7 +634,7 @@ static void get_lane_status_and_drive_settings( lane_adjust_offset = 3; } - core_link_read_dpcd( + status = core_link_read_dpcd( link, lane01_status_address, (uint8_t *)(dpcd_buf), @@ -693,9 +722,10 @@ static void get_lane_status_and_drive_settings( * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C */ + return status; } -static void dpcd_set_lane_settings( +enum dc_status dpcd_set_lane_settings( struct dc_link *link, const struct link_training_settings *link_training_setting, uint32_t offset) @@ -703,6 +733,7 @@ static void dpcd_set_lane_settings( union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; uint32_t lane; unsigned int lane0_set_address; + enum dc_status status; lane0_set_address = DP_TRAINING_LANE0_SET; @@ -730,7 +761,7 @@ static void dpcd_set_lane_settings( PRE_EMPHASIS_MAX_LEVEL ? 1 : 0); } - core_link_write_dpcd(link, + status = core_link_write_dpcd(link, lane0_set_address, (uint8_t *)(dpcd_lane), link_training_setting->link_settings.lane_count); @@ -776,9 +807,10 @@ static void dpcd_set_lane_settings( } link->cur_lane_setting = link_training_setting->lane_settings[0]; + return status; } -static bool is_max_vs_reached( +bool dp_is_max_vs_reached( const struct link_training_settings *lt_settings) { uint32_t lane; @@ -820,25 +852,24 @@ static bool perform_post_lt_adj_req_sequence( union lane_align_status_updated dpcd_lane_status_updated; - get_lane_status_and_drive_settings( - link, - lt_settings, - dpcd_lane_status, - &dpcd_lane_status_updated, - &req_settings, - DPRX); + dp_get_lane_status_and_drive_settings( + link, + lt_settings, + dpcd_lane_status, + &dpcd_lane_status_updated, + &req_settings, + DPRX); if (dpcd_lane_status_updated.bits. POST_LT_ADJ_REQ_IN_PROGRESS == 0) return true; - if (!is_cr_done(lane_count, dpcd_lane_status)) + if (!dp_is_cr_done(lane_count, dpcd_lane_status)) return false; - if (!is_ch_eq_done( - lane_count, - dpcd_lane_status, - &dpcd_lane_status_updated)) + if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) || + !dp_is_symbol_locked(lane_count, dpcd_lane_status) || + !dp_is_interlane_aligned(dpcd_lane_status_updated)) return false; for (lane = 0; lane < (uint32_t)(lane_count); lane++) { @@ -856,7 +887,7 @@ static bool perform_post_lt_adj_req_sequence( } if (req_drv_setting_changed) { - update_drive_settings( + dp_update_drive_settings( lt_settings, req_settings); dc_link_dp_set_drive_settings(link, @@ -884,7 +915,7 @@ static bool perform_post_lt_adj_req_sequence( } /* Only used for channel equalization */ -static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) +uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) { unsigned int aux_rd_interval_us = 400; @@ -908,7 +939,7 @@ static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_inte return aux_rd_interval_us; } -static enum link_training_result get_cr_failure(enum dc_lane_count ln_count, +enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, union lane_status *dpcd_lane_status) { enum link_training_result result = LINK_TRAINING_SUCCESS; @@ -969,17 +1000,17 @@ static enum link_training_result perform_channel_equalization_sequence( if (is_repeater(link, offset)) wait_time_microsec = - translate_training_aux_read_interval( + dp_translate_training_aux_read_interval( link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); - wait_for_training_aux_rd_interval( + dp_wait_for_training_aux_rd_interval( link, wait_time_microsec); /* 4. Read lane status and requested * drive settings as set by the sink*/ - get_lane_status_and_drive_settings( + dp_get_lane_status_and_drive_settings( link, lt_settings, dpcd_lane_status, @@ -988,23 +1019,22 @@ static enum link_training_result perform_channel_equalization_sequence( offset); /* 5. check CR done*/ - if (!is_cr_done(lane_count, dpcd_lane_status)) + if (!dp_is_cr_done(lane_count, dpcd_lane_status)) return LINK_TRAINING_EQ_FAIL_CR; /* 6. check CHEQ done*/ - if (is_ch_eq_done(lane_count, - dpcd_lane_status, - &dpcd_lane_status_updated)) + if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && + dp_is_symbol_locked(lane_count, dpcd_lane_status) && + dp_is_interlane_aligned(dpcd_lane_status_updated)) return LINK_TRAINING_SUCCESS; /* 7. update VS/PE/PC2 in lt_settings*/ - update_drive_settings(lt_settings, req_settings); + dp_update_drive_settings(lt_settings, req_settings); } return LINK_TRAINING_EQ_FAIL_EQ; } -#define TRAINING_AUX_RD_INTERVAL 100 //us static void start_clock_recovery_pattern_early(struct dc_link *link, struct link_training_settings *lt_settings, @@ -1075,14 +1105,14 @@ static enum link_training_result perform_clock_recovery_sequence( if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) wait_time_microsec = TRAINING_AUX_RD_INTERVAL; - wait_for_training_aux_rd_interval( + dp_wait_for_training_aux_rd_interval( link, wait_time_microsec); /* 4. Read lane status and requested drive * settings as set by the sink */ - get_lane_status_and_drive_settings( + dp_get_lane_status_and_drive_settings( link, lt_settings, dpcd_lane_status, @@ -1091,11 +1121,11 @@ static enum link_training_result perform_clock_recovery_sequence( offset); /* 5. check CR done*/ - if (is_cr_done(lane_count, dpcd_lane_status)) + if (dp_is_cr_done(lane_count, dpcd_lane_status)) return LINK_TRAINING_SUCCESS; /* 6. max VS reached*/ - if (is_max_vs_reached(lt_settings)) + if (dp_is_max_vs_reached(lt_settings)) break; /* 7. same lane settings*/ @@ -1110,7 +1140,7 @@ static enum link_training_result perform_clock_recovery_sequence( retries_cr = 0; /* 8. update VS/PE/PC2 in lt_settings*/ - update_drive_settings(lt_settings, req_settings); + dp_update_drive_settings(lt_settings, req_settings); retry_count++; } @@ -1123,10 +1153,10 @@ static enum link_training_result perform_clock_recovery_sequence( } - return get_cr_failure(lane_count, dpcd_lane_status); + return dp_get_cr_failure(lane_count, dpcd_lane_status); } -static inline enum link_training_result perform_link_training_int( +static inline enum link_training_result dp_transition_to_video_idle( struct dc_link *link, struct link_training_settings *lt_settings, enum link_training_result status) @@ -1142,8 +1172,16 @@ static inline enum link_training_result perform_link_training_int( * TPS4 must be used instead of POST_LT_ADJ_REQ. */ if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 || - lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) + lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) { + /* delay 5ms after Main Link output idle pattern and then check + * DPCD 0202h. + */ + if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) { + msleep(5); + status = dp_check_link_loss_status(link, lt_settings); + } return status; + } if (status == LINK_TRAINING_SUCCESS && perform_post_lt_adj_req_sequence(link, lt_settings) == false) @@ -1162,7 +1200,7 @@ static inline enum link_training_result perform_link_training_int( return status; } -static enum link_training_result check_link_loss_status( +enum link_training_result dp_check_link_loss_status( struct dc_link *link, const struct link_training_settings *link_training_setting) { @@ -1200,7 +1238,7 @@ static enum link_training_result check_link_loss_status( return status; } -static void initialize_training_settings( +static inline void decide_8b_10b_training_settings( struct dc_link *link, const struct dc_link_settings *link_setting, const struct dc_link_training_overrides *overrides, @@ -1244,6 +1282,8 @@ static void initialize_training_settings( else lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; + lt_settings->lttpr_mode = link->lttpr_mode; + /* Initialize lane settings overrides */ if (overrides->voltage_swing != NULL) lt_settings->voltage_swing = overrides->voltage_swing; @@ -1294,9 +1334,25 @@ static void initialize_training_settings( lt_settings->enhanced_framing = *overrides->enhanced_framing; else lt_settings->enhanced_framing = 1; + + if (link->preferred_training_settings.fec_enable != NULL) + lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; + else + lt_settings->should_set_fec_ready = true; } -static uint8_t convert_to_count(uint8_t lttpr_repeater_count) +void dp_decide_training_settings( + struct dc_link *link, + const struct dc_link_settings *link_settings, + const struct dc_link_training_overrides *overrides, + struct link_training_settings *lt_settings) +{ + if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) + decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings); +} + + +uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count) { switch (lttpr_repeater_count) { case 0x80: // 1 lttpr repeater @@ -1321,17 +1377,20 @@ static uint8_t convert_to_count(uint8_t lttpr_repeater_count) return 0; // invalid value } -static void configure_lttpr_mode_transparent(struct dc_link *link) +enum dc_status configure_lttpr_mode_transparent(struct dc_link *link) { uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT; - core_link_write_dpcd(link, + DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); + return core_link_write_dpcd(link, DP_PHY_REPEATER_MODE, (uint8_t *)&repeater_mode, sizeof(repeater_mode)); } -static void configure_lttpr_mode_non_transparent(struct dc_link *link) +enum dc_status configure_lttpr_mode_non_transparent( + struct dc_link *link, + const struct link_training_settings *lt_settings) { /* aux timeout is already set to extended */ /* RESET/SET lttpr mode to enable non transparent mode */ @@ -1341,11 +1400,16 @@ static void configure_lttpr_mode_non_transparent(struct dc_link *link) enum dc_status result = DC_ERROR_UNEXPECTED; uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT; - DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); - result = core_link_write_dpcd(link, - DP_PHY_REPEATER_MODE, - (uint8_t *)&repeater_mode, - sizeof(repeater_mode)); + enum dp_link_encoding encoding = dp_get_link_encoding_format(<_settings->link_settings); + + if (encoding == DP_8b_10b_ENCODING) { + DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); + result = core_link_write_dpcd(link, + DP_PHY_REPEATER_MODE, + (uint8_t *)&repeater_mode, + sizeof(repeater_mode)); + + } if (result == DC_OK) { link->dpcd_caps.lttpr_caps.mode = repeater_mode; @@ -1365,18 +1429,22 @@ static void configure_lttpr_mode_non_transparent(struct dc_link *link) link->dpcd_caps.lttpr_caps.mode = repeater_mode; } - repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); - for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) { - aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 + - ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1)); - core_link_read_dpcd( - link, - aux_interval_address, - (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1], - sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1])); - link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F; + if (encoding == DP_8b_10b_ENCODING) { + repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) { + aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 + + ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1)); + core_link_read_dpcd( + link, + aux_interval_address, + (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1], + sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1])); + link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F; + } } } + + return result; } static void repeater_training_done(struct dc_link *link, uint32_t offset) @@ -1510,7 +1578,7 @@ bool dc_link_dp_perform_link_training_skip_aux( { struct link_training_settings lt_settings; - initialize_training_settings( + dp_decide_training_settings( link, link_setting, &link->preferred_training_settings, @@ -1525,7 +1593,7 @@ bool dc_link_dp_perform_link_training_skip_aux( dp_set_hw_lane_settings(link, <_settings, DPRX); /* wait receiver to lock-on*/ - wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time); + dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time); /* 2. Perform_channel_equalization_sequence. */ @@ -1536,7 +1604,7 @@ bool dc_link_dp_perform_link_training_skip_aux( dp_set_hw_lane_settings(link, <_settings, DPRX); /* wait receiver to lock-on. */ - wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time); + dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time); /* 3. Perform_link_training_int. */ @@ -1548,60 +1616,78 @@ bool dc_link_dp_perform_link_training_skip_aux( return true; } -enum link_training_result dc_link_dp_perform_link_training( - struct dc_link *link, - const struct dc_link_settings *link_setting, - bool skip_video_pattern) +enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings) +{ + enum dc_status status = DC_OK; + + if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) + status = configure_lttpr_mode_non_transparent(link, lt_settings); + else + status = configure_lttpr_mode_transparent(link); + + return status; +} + +static void dpcd_exit_training_mode(struct dc_link *link) +{ + + /* clear training pattern set */ + dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); +} + +enum dc_status dpcd_configure_channel_coding(struct dc_link *link, + struct link_training_settings *lt_settings) +{ + enum dp_link_encoding encoding = + dp_get_link_encoding_format( + <_settings->link_settings); + enum dc_status status; + + status = core_link_write_dpcd( + link, + DP_MAIN_LINK_CHANNEL_CODING_SET, + (uint8_t *) &encoding, + 1); + DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n", + __func__, + DP_MAIN_LINK_CHANNEL_CODING_SET, + encoding); + + return status; +} + +static enum link_training_result dp_perform_8b_10b_link_training( + struct dc_link *link, + struct link_training_settings *lt_settings) { enum link_training_result status = LINK_TRAINING_SUCCESS; - struct link_training_settings lt_settings; - union dpcd_training_pattern dpcd_pattern = { { 0 } }; - bool fec_enable; uint8_t repeater_cnt; uint8_t repeater_id; - - initialize_training_settings( - link, - link_setting, - &link->preferred_training_settings, - <_settings); - - /* Configure lttpr mode */ - if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) - configure_lttpr_mode_non_transparent(link); - else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT) - configure_lttpr_mode_transparent(link); + uint8_t lane = 0; if (link->ctx->dc->work_arounds.lt_early_cr_pattern) - start_clock_recovery_pattern_early(link, <_settings, DPRX); + start_clock_recovery_pattern_early(link, lt_settings, DPRX); /* 1. set link rate, lane count and spread. */ - dpcd_set_link_settings(link, <_settings); - - if (link->preferred_training_settings.fec_enable != NULL) - fec_enable = *link->preferred_training_settings.fec_enable; - else - fec_enable = true; - - dp_set_fec_ready(link, fec_enable); + dpcd_set_link_settings(link, lt_settings); if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) { /* 2. perform link training (set link training done * to false is done as well) */ - repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS); repeater_id--) { - status = perform_clock_recovery_sequence(link, <_settings, repeater_id); + status = perform_clock_recovery_sequence(link, lt_settings, repeater_id); if (status != LINK_TRAINING_SUCCESS) break; status = perform_channel_equalization_sequence(link, - <_settings, + lt_settings, repeater_id); if (status != LINK_TRAINING_SUCCESS) @@ -1609,77 +1695,69 @@ enum link_training_result dc_link_dp_perform_link_training( repeater_training_done(link, repeater_id); } + + for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++) + lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0; } if (status == LINK_TRAINING_SUCCESS) { - status = perform_clock_recovery_sequence(link, <_settings, DPRX); + status = perform_clock_recovery_sequence(link, lt_settings, DPRX); if (status == LINK_TRAINING_SUCCESS) { status = perform_channel_equalization_sequence(link, - <_settings, + lt_settings, DPRX); } } - /* 3. set training not in progress*/ - dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE; - dpcd_set_training_pattern(link, dpcd_pattern); - if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { - status = perform_link_training_int(link, - <_settings, - status); - } - - /* delay 5ms after Main Link output idle pattern and then check - * DPCD 0202h. - */ - if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) { - msleep(5); - status = check_link_loss_status(link, <_settings); - } - - /* 6. print status message*/ - print_status_message(link, <_settings, status); - - if (status != LINK_TRAINING_SUCCESS) - link->ctx->dc->debug_data.ltFailCount++; - return status; } -static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream) +enum link_training_result dc_link_dp_perform_link_training( + struct dc_link *link, + const struct dc_link_settings *link_settings, + bool skip_video_pattern) { - struct dc_link *link = stream->link; - enum dp_panel_mode panel_mode = dp_get_panel_mode(link); -#ifdef CONFIG_DRM_AMD_DC_HDCP - struct cp_psp *cp_psp = &stream->ctx->cp_psp; -#endif + enum link_training_result status = LINK_TRAINING_SUCCESS; + struct link_training_settings lt_settings; + enum dp_link_encoding encoding = + dp_get_link_encoding_format(link_settings); - /* ASSR must be supported on the panel */ - if (panel_mode == DP_PANEL_MODE_DEFAULT) - return panel_mode; + /* decide training settings */ + dp_decide_training_settings( + link, + link_settings, + &link->preferred_training_settings, + <_settings); - /* eDP or internal DP only */ - if (link->connector_signal != SIGNAL_TYPE_EDP && - !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && - link->is_internal_display)) - return DP_PANEL_MODE_DEFAULT; + /* reset previous training states */ + dpcd_exit_training_mode(link); -#ifdef CONFIG_DRM_AMD_DC_HDCP - if (cp_psp && cp_psp->funcs.enable_assr) { - if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) { - /* since eDP implies ASSR on, change panel - * mode to disable ASSR - */ - panel_mode = DP_PANEL_MODE_DEFAULT; - } - } else - panel_mode = DP_PANEL_MODE_DEFAULT; + /* configure link prior to entering training mode */ + dpcd_configure_lttpr_mode(link, <_settings); + dp_set_fec_ready(link, lt_settings.should_set_fec_ready); + dpcd_configure_channel_coding(link, <_settings); -#else - /* turn off ASSR if the implementation is not compiled in */ - panel_mode = DP_PANEL_MODE_DEFAULT; -#endif - return panel_mode; + /* enter training mode: + * Per DP specs starting from here, DPTX device shall not issue + * Non-LT AUX transactions inside training mode. + */ + if (encoding == DP_8b_10b_ENCODING) + status = dp_perform_8b_10b_link_training(link, <_settings); + else + ASSERT(0); + + /* exit training mode and switch to video idle */ + dpcd_exit_training_mode(link); + if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) + status = dp_transition_to_video_idle(link, + <_settings, + status); + + /* dump debug data */ + print_status_message(link, <_settings, status); + if (status != LINK_TRAINING_SUCCESS) + link->ctx->dc->debug_data.ltFailCount++; + return status; } bool perform_link_training_with_retries( @@ -1687,18 +1765,31 @@ bool perform_link_training_with_retries( bool skip_video_pattern, int attempts, struct pipe_ctx *pipe_ctx, - enum signal_type signal) + enum signal_type signal, + bool do_fallback) { - uint8_t j; + int j; uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY; struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->link; - enum dp_panel_mode panel_mode; + enum dp_panel_mode panel_mode = dp_get_panel_mode(link); + struct link_encoder *link_enc; + enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0; + struct dc_link_settings current_setting = *link_setting; + + /* Dynamically assigned link encoders associated with stream rather than + * link. + */ + if (link->dc->res_pool->funcs->link_encs_assign) + link_enc = stream->link_enc; + else + link_enc = link->link_enc; + ASSERT(link_enc); /* We need to do this before the link training to ensure the idle pattern in SST * mode will be sent right after the link training */ - link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + link_enc->funcs->connect_dig_be_to_fe(link_enc, pipe_ctx->stream_res.stream_enc->id, true); for (j = 0; j < attempts; ++j) { @@ -1710,7 +1801,7 @@ bool perform_link_training_with_retries( link, signal, pipe_ctx->clock_source->id, - link_setting); + ¤t_setting); if (stream->sink_patches.dppowerup_delay > 0) { int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay; @@ -1718,21 +1809,31 @@ bool perform_link_training_with_retries( msleep(delay_dp_power_up_in_ms); } - panel_mode = try_enable_assr(stream); +#ifdef CONFIG_DRM_AMD_DC_HDCP + if (panel_mode == DP_PANEL_MODE_EDP) { + struct cp_psp *cp_psp = &stream->ctx->cp_psp; + + if (cp_psp && cp_psp->funcs.enable_assr) { + if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) { + /* since eDP implies ASSR on, change panel + * mode to disable ASSR + */ + panel_mode = DP_PANEL_MODE_DEFAULT; + } + } else + panel_mode = DP_PANEL_MODE_DEFAULT; + } +#endif + dp_set_panel_mode(link, panel_mode); - DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n", - link->link_index, - panel_mode != DP_PANEL_MODE_DEFAULT); if (link->aux_access_disabled) { - dc_link_dp_perform_link_training_skip_aux(link, link_setting); + dc_link_dp_perform_link_training_skip_aux(link, ¤t_setting); return true; } else { - enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0; - status = dc_link_dp_perform_link_training( link, - link_setting, + ¤t_setting, skip_video_pattern); if (status == LINK_TRAINING_SUCCESS) return true; @@ -1740,7 +1841,7 @@ bool perform_link_training_with_retries( /* latest link training still fail, skip delay and keep PHY on */ - if (j == (attempts - 1)) + if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY) break; DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n", @@ -1748,6 +1849,19 @@ bool perform_link_training_with_retries( dp_disable_link_phy(link, signal); + /* Abort link training if failure due to sink being unplugged. */ + if (status == LINK_TRAINING_ABORT) + break; + else if (do_fallback) { + decide_fallback_link_setting(*link_setting, ¤t_setting, status); + /* Fail link training if reduced link bandwidth no longer meets + * stream requirements. + */ + if (dc_bandwidth_in_kbps_from_timing(&stream->timing) < + dc_link_bandwidth_kbps(link, ¤t_setting)) + break; + } + msleep(delay_between_attempts); delay_between_attempts += LINK_TRAINING_RETRY_DELAY; @@ -1784,6 +1898,8 @@ static void set_dp_mst_mode(struct dc_link *link, bool mst_enable) link->type = dc_connection_single; link->local_sink = link->remote_sinks[0]; link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT; + dc_sink_retain(link->local_sink); + dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); } else if (mst_enable == true && link->type == dc_connection_single && link->remote_sinks[0] != NULL) { @@ -1823,7 +1939,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt( enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; bool fec_enable = false; - initialize_training_settings( + dp_decide_training_settings( link, link_settings, lt_overrides, @@ -1893,6 +2009,24 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) return true; } +bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) +{ + if (!max_link_enc_cap) { + DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__); + return false; + } + + if (link->link_enc->funcs->get_max_link_cap) { + link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap); + return true; + } + + DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__); + max_link_enc_cap->lane_count = 1; + max_link_enc_cap->link_rate = 6; + return false; +} + static struct dc_link_settings get_max_link_cap(struct dc_link *link) { struct dc_link_settings max_link_cap = {0}; @@ -1976,7 +2110,7 @@ enum dc_status read_hpd_rx_irq_data( return retval; } -static bool hpd_rx_irq_check_link_loss_status( +bool hpd_rx_irq_check_link_loss_status( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data) { @@ -2173,7 +2307,7 @@ bool dp_verify_link_cap_with_retries( struct dc_link_settings *known_limit_link_setting, int attempts) { - uint8_t i = 0; + int i = 0; bool success = false; for (i = 0; i < attempts; i++) { @@ -2411,6 +2545,12 @@ bool dp_validate_mode_timing( const struct dc_link_settings *link_setting; + /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */ + if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && + !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && + dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL) + return false; + /*always DP fail safe mode*/ if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && timing->h_addressable == (uint32_t) 640 && @@ -2495,7 +2635,11 @@ bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *lin struct dc_link_settings current_link_setting; uint32_t link_bw; - if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 || + /* + * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. + * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" + */ + if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 || link->dpcd_caps.edp_supported_link_rates_count == 0) { *link_setting = link->verified_link_cap; return true; @@ -2593,13 +2737,11 @@ static bool allow_hpd_rx_irq(const struct dc_link *link) /* * Don't handle RX IRQ unless one of following is met: * 1) The link is established (cur_link_settings != unknown) - * 2) We kicked off MST detection - * 3) We know we're dealing with an active dongle + * 2) We know we're dealing with a branch device, SST or MST */ if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || - (link->type == dc_connection_mst_branch) || - is_dp_active_dongle(link)) + is_dp_branch_device(link)) return true; return false; @@ -2697,9 +2839,10 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) union phy_test_pattern dpcd_test_pattern; union lane_adjust dpcd_lane_adjustment[2]; unsigned char dpcd_post_cursor_2_adjustment = 0; - unsigned char test_80_bit_pattern[ + unsigned char test_pattern_buffer[ (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0}; + unsigned int test_pattern_size = 0; enum dp_test_pattern test_pattern; struct dc_link_training_settings link_settings; union lane_adjust dpcd_lane_adjust; @@ -2769,12 +2912,15 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) break; } - if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) + if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { + test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - + DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1; core_link_read_dpcd( link, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, - test_80_bit_pattern, - sizeof(test_80_bit_pattern)); + test_pattern_buffer, + test_pattern_size); + } /* prepare link training settings */ link_settings.link = link->cur_link_settings; @@ -2812,9 +2958,8 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) test_pattern, DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED, &link_training_settings, - test_80_bit_pattern, - (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - - DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1); + test_pattern_buffer, + test_pattern_size); } static void dp_test_send_link_test_pattern(struct dc_link *link) @@ -2899,6 +3044,22 @@ static void dp_test_send_link_test_pattern(struct dc_link *link) break; } + switch (dpcd_test_params.bits.CLR_FORMAT) { + case 0: + pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB; + break; + case 1: + pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422; + break; + case 2: + pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444; + break; + default: + pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB; + break; + } + + if (requestColorDepth != COLOR_DEPTH_UNDEFINED && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) { DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n", @@ -2906,9 +3067,10 @@ static void dp_test_send_link_test_pattern(struct dc_link *link) pipe_ctx->stream->timing.display_color_depth, requestColorDepth); pipe_ctx->stream->timing.display_color_depth = requestColorDepth; - dp_update_dsc_config(pipe_ctx); } + dp_update_dsc_config(pipe_ctx); + dc_link_dp_set_test_pattern( link, test_pattern, @@ -3164,7 +3326,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd *out_link_loss = true; } - if (link->type == dc_connection_active_dongle && + if (link->type == dc_connection_sst_branch && hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT != link->dpcd_sink_count) status = true; @@ -3214,6 +3376,12 @@ bool is_mst_supported(struct dc_link *link) } bool is_dp_active_dongle(const struct dc_link *link) +{ + return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && + (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); +} + +bool is_dp_branch_device(const struct dc_link *link) { return link->dpcd_caps.is_branch_dev; } @@ -3432,79 +3600,16 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link) return true; } -static bool retrieve_link_cap(struct dc_link *link) +bool dp_retrieve_lttpr_cap(struct dc_link *link) { - /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, - * which means size 16 will be good for both of those DPCD register block reads - */ - uint8_t dpcd_data[16]; uint8_t lttpr_dpcd_data[6]; - - /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. - */ - uint8_t dpcd_dprx_data = '\0'; - uint8_t dpcd_power_state = '\0'; - - struct dp_device_vendor_id sink_id; - union down_stream_port_count down_strm_port_count; - union edp_configuration_cap edp_config_cap; - union dp_downstream_port_present ds_port = { 0 }; - enum dc_status status = DC_ERROR_UNEXPECTED; - uint32_t read_dpcd_retry_cnt = 3; - int i; - struct dp_sink_hw_fw_revision dp_hw_fw_revision; - bool is_lttpr_present = false; - const uint32_t post_oui_delay = 30; // 30ms bool vbios_lttpr_enable = false; bool vbios_lttpr_interop = false; struct dc_bios *bios = link->dc->ctx->dc_bios; + enum dc_status status = DC_ERROR_UNEXPECTED; + bool is_lttpr_present = false; - memset(dpcd_data, '\0', sizeof(dpcd_data)); memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); - memset(&down_strm_port_count, - '\0', sizeof(union down_stream_port_count)); - memset(&edp_config_cap, '\0', - sizeof(union edp_configuration_cap)); - - /* if extended timeout is supported in hardware, - * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer - * CTS 4.2.1.1 regression introduced by CTS specs requirement update. - */ - dc_link_aux_try_to_configure_timeout(link->ddc, - LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); - - status = core_link_read_dpcd(link, DP_SET_POWER, - &dpcd_power_state, sizeof(dpcd_power_state)); - - /* Delay 1 ms if AUX CH is in power down state. Based on spec - * section 2.3.1.2, if AUX CH may be powered down due to - * write to DPCD 600h = 2. Sink AUX CH is monitoring differential - * signal and may need up to 1 ms before being able to reply. - */ - if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) - udelay(1000); - - dpcd_set_source_specific_data(link); - /* Sink may need to configure internals based on vendor, so allow some - * time before proceeding with possibly vendor specific transactions - */ - msleep(post_oui_delay); - - for (i = 0; i < read_dpcd_retry_cnt; i++) { - status = core_link_read_dpcd( - link, - DP_DPCD_REV, - dpcd_data, - sizeof(dpcd_data)); - if (status == DC_OK) - break; - } - - if (status != DC_OK) { - dm_error("%s: Read dpcd data failed.\n", __func__); - return false; - } - /* Query BIOS to determine if LTTPR functionality is forced on by system */ if (bios->funcs->get_lttpr_caps) { enum bp_result bp_query_result; @@ -3550,6 +3655,10 @@ static bool retrieve_link_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, lttpr_dpcd_data, sizeof(lttpr_dpcd_data)); + if (status != DC_OK) { + dm_error("%s: Read LTTPR caps data failed.\n", __func__); + return false; + } link->dpcd_caps.lttpr_caps.revision.raw = lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - @@ -3575,20 +3684,92 @@ static bool retrieve_link_cap(struct dc_link *link) lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; - is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && + /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ + is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 && link->dpcd_caps.lttpr_caps.max_lane_count > 0 && link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); - if (is_lttpr_present) + if (is_lttpr_present) { CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); - else + configure_lttpr_mode_transparent(link); + } else link->lttpr_mode = LTTPR_MODE_NON_LTTPR; } + return is_lttpr_present; +} + +static bool retrieve_link_cap(struct dc_link *link) +{ + /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, + * which means size 16 will be good for both of those DPCD register block reads + */ + uint8_t dpcd_data[16]; + /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. + */ + uint8_t dpcd_dprx_data = '\0'; + uint8_t dpcd_power_state = '\0'; + + struct dp_device_vendor_id sink_id; + union down_stream_port_count down_strm_port_count; + union edp_configuration_cap edp_config_cap; + union dp_downstream_port_present ds_port = { 0 }; + enum dc_status status = DC_ERROR_UNEXPECTED; + uint32_t read_dpcd_retry_cnt = 3; + int i; + struct dp_sink_hw_fw_revision dp_hw_fw_revision; + const uint32_t post_oui_delay = 30; // 30ms + bool is_lttpr_present = false; + + memset(dpcd_data, '\0', sizeof(dpcd_data)); + memset(&down_strm_port_count, + '\0', sizeof(union down_stream_port_count)); + memset(&edp_config_cap, '\0', + sizeof(union edp_configuration_cap)); + + /* if extended timeout is supported in hardware, + * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer + * CTS 4.2.1.1 regression introduced by CTS specs requirement update. + */ + dc_link_aux_try_to_configure_timeout(link->ddc, + LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); + + is_lttpr_present = dp_retrieve_lttpr_cap(link); + + status = core_link_read_dpcd(link, DP_SET_POWER, + &dpcd_power_state, sizeof(dpcd_power_state)); + + /* Delay 1 ms if AUX CH is in power down state. Based on spec + * section 2.3.1.2, if AUX CH may be powered down due to + * write to DPCD 600h = 2. Sink AUX CH is monitoring differential + * signal and may need up to 1 ms before being able to reply. + */ + if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) + udelay(1000); + + dpcd_set_source_specific_data(link); + /* Sink may need to configure internals based on vendor, so allow some + * time before proceeding with possibly vendor specific transactions + */ + msleep(post_oui_delay); + + for (i = 0; i < read_dpcd_retry_cnt; i++) { + status = core_link_read_dpcd( + link, + DP_DPCD_REV, + dpcd_data, + sizeof(dpcd_data)); + if (status == DC_OK) + break; + } + + if (status != DC_OK) { + dm_error("%s: Read receiver caps dpcd data failed.\n", __func__); + return false; + } if (!is_lttpr_present) dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); - { union training_aux_rd_interval aux_rd_interval; @@ -3892,7 +4073,11 @@ void detect_edp_sink_caps(struct dc_link *link) link->dpcd_caps.edp_supported_link_rates_count = 0; memset(supported_link_rates, 0, sizeof(supported_link_rates)); - if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && + /* + * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. + * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" + */ + if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 && (link->dc->debug.optimize_edp_link_rate || link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) { // Read DPCD 00010h - 0001Fh 16 bytes at one shot @@ -4472,50 +4657,74 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) return DP_PANEL_MODE_DEFAULT; } -void dp_set_fec_ready(struct dc_link *link, bool ready) +enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready) { /* FEC has to be "set ready" before the link training. * The policy is to always train with FEC * if the sink supports it and leave it enabled on link. * If FEC is not supported, disable it. */ - struct link_encoder *link_enc = link->link_enc; + struct link_encoder *link_enc = NULL; + enum dc_status status = DC_OK; uint8_t fec_config = 0; + /* Access link encoder based on whether it is statically + * or dynamically assigned to a link. + */ + if (link->is_dig_mapping_flexible && + link->dc->res_pool->funcs->link_encs_assign) + link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); + else + link_enc = link->link_enc; + ASSERT(link_enc); + if (!dc_link_should_enable_fec(link)) - return; + return status; if (link_enc->funcs->fec_set_ready && link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { if (ready) { fec_config = 1; - if (core_link_write_dpcd(link, + status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION, &fec_config, - sizeof(fec_config)) == DC_OK) { + sizeof(fec_config)); + if (status == DC_OK) { link_enc->funcs->fec_set_ready(link_enc, true); link->fec_state = dc_link_fec_ready; } else { - link->link_enc->funcs->fec_set_ready(link->link_enc, false); + link_enc->funcs->fec_set_ready(link->link_enc, false); link->fec_state = dc_link_fec_not_ready; dm_error("dpcd write failed to set fec_ready"); } } else if (link->fec_state == dc_link_fec_ready) { fec_config = 0; - core_link_write_dpcd(link, + status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION, &fec_config, sizeof(fec_config)); - link->link_enc->funcs->fec_set_ready( - link->link_enc, false); + link_enc->funcs->fec_set_ready(link_enc, false); link->fec_state = dc_link_fec_not_ready; } } + + return status; } void dp_set_fec_enable(struct dc_link *link, bool enable) { - struct link_encoder *link_enc = link->link_enc; + struct link_encoder *link_enc = NULL; + + /* Access link encoder based on whether it is statically + * or dynamically assigned to a link. + */ + if (link->is_dig_mapping_flexible && + link->dc->res_pool->funcs->link_encs_assign) + link_enc = link_enc_cfg_get_link_enc_used_by_link( + link->dc->current_state, link); + else + link_enc = link->link_enc; + ASSERT(link_enc); if (!dc_link_should_enable_fec(link)) return; @@ -4766,4 +4975,11 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin return false; } +enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings) +{ + if ((link_settings->link_rate >= LINK_RATE_LOW) && + (link_settings->link_rate <= LINK_RATE_HIGH3)) + return DP_8b_10b_ENCODING; + return DP_UNKNOWN_ENCODING; +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c new file mode 100644 index 000000000000..fe234760a0f5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c @@ -0,0 +1,218 @@ +#include +#include +#include +#include +#include "drm/drm_dp_helper.h" +#include +#include "dm_helpers.h" + +#define END_ADDRESS(start, size) (start + size - 1) +#define ADDRESS_RANGE_SIZE(start, end) (end - start + 1) +struct dpcd_address_range { + uint32_t start; + uint32_t end; +}; + +static enum dc_status internal_link_read_dpcd( + struct dc_link *link, + uint32_t address, + uint8_t *data, + uint32_t size) +{ + if (!link->aux_access_disabled && + !dm_helpers_dp_read_dpcd(link->ctx, + link, address, data, size)) { + return DC_ERROR_UNEXPECTED; + } + + return DC_OK; +} + +static enum dc_status internal_link_write_dpcd( + struct dc_link *link, + uint32_t address, + const uint8_t *data, + uint32_t size) +{ + if (!link->aux_access_disabled && + !dm_helpers_dp_write_dpcd(link->ctx, + link, address, data, size)) { + return DC_ERROR_UNEXPECTED; + } + + return DC_OK; +} + +/* + * Partition the entire DPCD address space + * XXX: This partitioning must cover the entire DPCD address space, + * and must contain no gaps or overlapping address ranges. + */ +static const struct dpcd_address_range mandatory_dpcd_partitions[] = { + { 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1}, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 }, + { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 }, + /* + * The FEC registers are contiguous + */ + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 }, + { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD }, + /* all remaining DPCD addresses */ + { DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } }; + +static inline bool do_addresses_intersect_with_range( + const struct dpcd_address_range *range, + const uint32_t start_address, + const uint32_t end_address) +{ + return start_address <= range->end && end_address >= range->start; +} + +static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size) +{ + const uint32_t end_address = END_ADDRESS(address, size); + uint32_t partition_iterator = 0; + + /* + * find current partition + * this loop spins forever if partition map above is not surjective + */ + while (!do_addresses_intersect_with_range(&mandatory_dpcd_partitions[partition_iterator], + address, end_address)) + partition_iterator++; + if (end_address < mandatory_dpcd_partitions[partition_iterator].end) + return size; + return ADDRESS_RANGE_SIZE(address, mandatory_dpcd_partitions[partition_iterator].end); +} + +/* + * Ranges of DPCD addresses that must be read in a single transaction + * XXX: Do not allow any two address ranges in this array to overlap + */ +static const struct dpcd_address_range mandatory_dpcd_blocks[] = { + { DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }}; + +/* + * extend addresses to read all mandatory blocks together + */ +static void dpcd_extend_address_range( + const uint32_t in_address, + uint8_t * const in_data, + const uint32_t in_size, + uint32_t *out_address, + uint8_t **out_data, + uint32_t *out_size) +{ + const uint32_t end_address = END_ADDRESS(in_address, in_size); + const struct dpcd_address_range *addr_range; + struct dpcd_address_range new_addr_range; + uint32_t i; + + new_addr_range.start = in_address; + new_addr_range.end = end_address; + for (i = 0; i < ARRAY_SIZE(mandatory_dpcd_blocks); i++) { + addr_range = &mandatory_dpcd_blocks[i]; + if (addr_range->start <= in_address && addr_range->end >= in_address) + new_addr_range.start = addr_range->start; + + if (addr_range->start <= end_address && addr_range->end >= end_address) + new_addr_range.end = addr_range->end; + } + *out_address = in_address; + *out_size = in_size; + *out_data = in_data; + if (new_addr_range.start != in_address || new_addr_range.end != end_address) { + *out_address = new_addr_range.start; + *out_size = ADDRESS_RANGE_SIZE(new_addr_range.start, new_addr_range.end); + *out_data = kzalloc(*out_size * sizeof(**out_data), GFP_KERNEL); + } +} + +/* + * Reduce the AUX reply down to the values the caller requested + */ +static void dpcd_reduce_address_range( + const uint32_t extended_address, + uint8_t * const extended_data, + const uint32_t extended_size, + const uint32_t reduced_address, + uint8_t * const reduced_data, + const uint32_t reduced_size) +{ + const uint32_t reduced_end_address = END_ADDRESS(reduced_address, reduced_size); + const uint32_t extended_end_address = END_ADDRESS(extended_address, extended_size); + const uint32_t offset = reduced_address - extended_address; + + if (extended_end_address == reduced_end_address && extended_address == reduced_address) + return; /* extended and reduced address ranges point to the same data */ + + memcpy(&extended_data[offset], reduced_data, reduced_size); + kfree(extended_data); +} + +enum dc_status core_link_read_dpcd( + struct dc_link *link, + uint32_t address, + uint8_t *data, + uint32_t size) +{ + uint32_t extended_address; + uint32_t partitioned_address; + uint8_t *extended_data; + uint32_t extended_size; + /* size of the remaining partitioned address space */ + uint32_t size_left_to_read; + enum dc_status status; + /* size of the next partition to be read from */ + uint32_t partition_size; + uint32_t data_index = 0; + + dpcd_extend_address_range(address, data, size, &extended_address, &extended_data, &extended_size); + partitioned_address = extended_address; + size_left_to_read = extended_size; + while (size_left_to_read) { + partition_size = dpcd_get_next_partition_size(partitioned_address, size_left_to_read); + status = internal_link_read_dpcd(link, partitioned_address, &extended_data[data_index], partition_size); + if (status != DC_OK) + break; + partitioned_address += partition_size; + data_index += partition_size; + size_left_to_read -= partition_size; + } + dpcd_reduce_address_range(extended_address, extended_data, extended_size, address, data, size); + return status; +} + +enum dc_status core_link_write_dpcd( + struct dc_link *link, + uint32_t address, + const uint8_t *data, + uint32_t size) +{ + uint32_t partition_size; + uint32_t data_index = 0; + enum dc_status status; + + while (size) { + partition_size = dpcd_get_next_partition_size(address, size); + status = internal_link_write_dpcd(link, address, &data[data_index], partition_size); + if (status != DC_OK) + break; + address += partition_size; + data_index += partition_size; + size -= partition_size; + } + return status; +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index 1361b87d86d7..1a89d565c92e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -112,8 +112,8 @@ static void update_link_enc_assignment( /* Return first available DIG link encoder. */ static enum engine_id find_first_avail_link_enc( - struct dc_context *ctx, - struct dc_state *state) + const struct dc_context *ctx, + const struct dc_state *state) { enum engine_id eng_id = ENGINE_ID_UNKNOWN; int i; @@ -270,7 +270,7 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc( struct link_encoder *link_enc_cfg_get_link_enc_used_by_link( struct dc_state *state, - struct dc_link *link) + const struct dc_link *link) { struct link_encoder *link_enc = NULL; struct display_endpoint_id ep_id; @@ -296,8 +296,20 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link( if (stream_idx != -1) link_enc = state->streams[stream_idx]->link_enc; - else - dm_output_to_console("%s: No link encoder used by link(%d).\n", __func__, link->link_index); + + return link_enc; +} + +struct link_encoder *link_enc_cfg_get_next_avail_link_enc( + const struct dc *dc, + const struct dc_state *state) +{ + struct link_encoder *link_enc = NULL; + enum engine_id eng_id = ENGINE_ID_UNKNOWN; + + eng_id = find_first_avail_link_enc(dc->ctx, state); + if (eng_id != ENGINE_ID_UNKNOWN) + link_enc = dc->res_pool->link_encoders[eng_id - ENGINE_ID_DIGA]; return link_enc; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index b426f878fb99..9c51cd09dcf1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -16,6 +16,7 @@ #include "resource.h" #include "link_enc_cfg.h" #include "clk_mgr.h" +#include "inc/link_dpcd.h" static uint8_t convert_to_count(uint8_t lttpr_repeater_count) { @@ -47,36 +48,6 @@ static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset); } -enum dc_status core_link_read_dpcd( - struct dc_link *link, - uint32_t address, - uint8_t *data, - uint32_t size) -{ - if (!link->aux_access_disabled && - !dm_helpers_dp_read_dpcd(link->ctx, - link, address, data, size)) { - return DC_ERROR_UNEXPECTED; - } - - return DC_OK; -} - -enum dc_status core_link_write_dpcd( - struct dc_link *link, - uint32_t address, - const uint8_t *data, - uint32_t size) -{ - if (!link->aux_access_disabled && - !dm_helpers_dp_write_dpcd(link->ctx, - link, address, data, size)) { - return DC_ERROR_UNEXPECTED; - } - - return DC_OK; -} - void dp_receiver_power_ctrl(struct dc_link *link, bool on) { uint8_t state; @@ -332,7 +303,16 @@ void dp_set_hw_test_pattern( uint32_t custom_pattern_size) { struct encoder_set_dp_phy_pattern_param pattern_param = {0}; - struct link_encoder *encoder = link->link_enc; + struct link_encoder *encoder; + + /* Access link encoder based on whether it is statically + * or dynamically assigned to a link. + */ + if (link->is_dig_mapping_flexible && + link->dc->res_pool->funcs->link_encs_assign) + encoder = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); + else + encoder = link->link_enc; pattern_param.dp_phy_pattern = test_pattern; pattern_param.custom_pattern = custom_pattern; @@ -384,7 +364,8 @@ void dp_retrain_link_dp_test(struct dc_link *link, skip_video_pattern, LINK_TRAINING_ATTEMPTS, &pipes[i], - SIGNAL_TYPE_DISPLAY_PORT); + SIGNAL_TYPE_DISPLAY_PORT, + false); link->dc->hwss.enable_stream(&pipes[i]); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 8cb937c046aa..a6a67244a322 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -57,6 +57,8 @@ #include "dcn30/dcn30_resource.h" #include "dcn301/dcn301_resource.h" #include "dcn302/dcn302_resource.h" +#include "dcn303/dcn303_resource.h" +#include "dcn31/dcn31_resource.h" #endif #define DC_LOGGER_INIT(logger) @@ -130,12 +132,20 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) dc_version = DCN_VERSION_3_0; if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_3_02; + if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_03; break; case FAMILY_VGH: dc_version = DCN_VERSION_3_01; break; + + case FAMILY_YELLOW_CARP: + if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_1; + break; #endif + default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -216,6 +226,12 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_3_02: res_pool = dcn302_create_resource_pool(init_data, dc); break; + case DCN_VERSION_3_03: + res_pool = dcn303_create_resource_pool(init_data, dc); + break; + case DCN_VERSION_3_1: + res_pool = dcn31_create_resource_pool(init_data, dc); + break; #endif default: break; @@ -423,7 +439,7 @@ bool resource_are_vblanks_synchronizable( { uint32_t base60_refresh_rates[] = {10, 20, 5}; uint8_t i; - uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]); + uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); uint64_t frame_time_diff; if (stream1->ctx->dc->config.vblank_alignment_dto_params && @@ -605,6 +621,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface( dal_pixel_format = PIXEL_FORMAT_420BPP10; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: default: dal_pixel_format = PIXEL_FORMAT_UNKNOWN; break; @@ -695,124 +712,23 @@ static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *spli } } -static void calculate_viewport(struct pipe_ctx *pipe_ctx) +/* + * This is a preliminary vp size calculation to allow us to check taps support. + * The result is completely overridden afterwards. + */ +static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *plane_state = pipe_ctx->plane_state; - const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->plane_res.scl_data; - struct rect surf_src = plane_state->src_rect; - struct rect clip, dest; - int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 - || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - int split_count = 0; - int split_idx = 0; - bool orthogonal_rotation, flip_y_start, flip_x_start; - calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); - - if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || - stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { - split_count = 0; - split_idx = 0; + data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); + data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); + data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); + data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { + swap(data->viewport.width, data->viewport.height); + swap(data->viewport_c.width, data->viewport_c.height); } - - /* The actual clip is an intersection between stream - * source and surface clip - */ - dest = plane_state->dst_rect; - clip.x = stream->src.x > plane_state->clip_rect.x ? - stream->src.x : plane_state->clip_rect.x; - - clip.width = stream->src.x + stream->src.width < - plane_state->clip_rect.x + plane_state->clip_rect.width ? - stream->src.x + stream->src.width - clip.x : - plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; - - clip.y = stream->src.y > plane_state->clip_rect.y ? - stream->src.y : plane_state->clip_rect.y; - - clip.height = stream->src.y + stream->src.height < - plane_state->clip_rect.y + plane_state->clip_rect.height ? - stream->src.y + stream->src.height - clip.y : - plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; - - /* - * Need to calculate how scan origin is shifted in vp space - * to correctly rotate clip and dst - */ - get_vp_scan_direction( - plane_state->rotation, - plane_state->horizontal_mirror, - &orthogonal_rotation, - &flip_y_start, - &flip_x_start); - - if (orthogonal_rotation) { - swap(clip.x, clip.y); - swap(clip.width, clip.height); - swap(dest.x, dest.y); - swap(dest.width, dest.height); - } - if (flip_x_start) { - clip.x = dest.x + dest.width - clip.x - clip.width; - dest.x = 0; - } - if (flip_y_start) { - clip.y = dest.y + dest.height - clip.y - clip.height; - dest.y = 0; - } - - /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio - * num_pixels = clip.num_pix * scl_ratio - */ - data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width; - data->viewport.width = clip.width * surf_src.width / dest.width; - - data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height; - data->viewport.height = clip.height * surf_src.height / dest.height; - - /* Handle split */ - if (split_count) { - /* extra pixels in the division remainder need to go to pipes after - * the extra pixel index minus one(epimo) defined here as: - */ - int epimo = 0; - - if (orthogonal_rotation) { - if (flip_y_start) - split_idx = split_count - split_idx; - - epimo = split_count - data->viewport.height % (split_count + 1); - - data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx; - if (split_idx > epimo) - data->viewport.y += split_idx - epimo - 1; - data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0); - } else { - if (flip_x_start) - split_idx = split_count - split_idx; - - epimo = split_count - data->viewport.width % (split_count + 1); - - data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx; - if (split_idx > epimo) - data->viewport.x += split_idx - epimo - 1; - data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); - } - } - - /* Round down, compensate in init */ - data->viewport_c.x = data->viewport.x / vpc_div; - data->viewport_c.y = data->viewport.y / vpc_div; - data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero; - data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero; - - /* Round up, assume original video size always even dimensions */ - data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; - data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; - - data->viewport_unadjusted = data->viewport; - data->viewport_c_unadjusted = data->viewport_c; } static void calculate_recout(struct pipe_ctx *pipe_ctx) @@ -821,26 +737,21 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->plane_res.scl_data; struct rect surf_clip = plane_state->clip_rect; - bool pri_split_tb = pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state && - stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; - bool sec_split_tb = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state && - stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; - int split_count = 0; - int split_idx = 0; + bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; + int split_count, split_idx; calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) + split_idx = 0; /* * Only the leftmost ODM pipe should be offset by a nonzero distance */ - if (!pipe_ctx->prev_odm_pipe) { + if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { data->recout.x = stream->dst.x; if (stream->src.x < surf_clip.x) data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width / stream->src.width; - } else data->recout.x = 0; @@ -861,26 +772,36 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; - /* Handle h & v split, handle rotation using viewport */ - if (sec_split_tb) { - data->recout.y += data->recout.height / 2; - /* Floor primary pipe, ceil 2ndary pipe */ - data->recout.height = (data->recout.height + 1) / 2; - } else if (pri_split_tb) + /* Handle h & v split */ + if (split_tb) { + ASSERT(data->recout.height % 2 == 0); data->recout.height /= 2; - else if (split_count) { - /* extra pixels in the division remainder need to go to pipes after - * the extra pixel index minus one(epimo) defined here as: - */ - int epimo = split_count - data->recout.width % (split_count + 1); - - /*no recout offset due to odm */ + } else if (split_count) { if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { + /* extra pixels in the division remainder need to go to pipes after + * the extra pixel index minus one(epimo) defined here as: + */ + int epimo = split_count - data->recout.width % (split_count + 1); + data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; if (split_idx > epimo) data->recout.x += split_idx - epimo - 1; + ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); + data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); + } else { + /* odm */ + if (split_idx == split_count) { + /* rightmost pipe is the remainder recout */ + data->recout.width -= data->h_active * split_count - data->recout.x; + + /* ODM combine cases with MPO we can get negative widths */ + if (data->recout.width < 0) + data->recout.width = 0; + + data->recout.x = 0; + } else + data->recout.width = data->h_active - data->recout.x; } - data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); } } @@ -934,9 +855,15 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); } -static inline void adjust_vp_and_init_for_seamless_clip( + +/* + * We completely calculate vp offset, size and inits here based entirely on scaling + * ratios and recout for pixel perfect pipe combine. + */ +static void calculate_init_and_vp( bool flip_scan_dir, - int recout_skip, + int recout_offset_within_recout_full, + int recout_size, int src_size, int taps, struct fixed31_32 ratio, @@ -944,91 +871,87 @@ static inline void adjust_vp_and_init_for_seamless_clip( int *vp_offset, int *vp_size) { - if (!flip_scan_dir) { - /* Adjust for viewport end clip-off */ - if ((*vp_offset + *vp_size) < src_size) { - int vp_clip = src_size - *vp_size - *vp_offset; - int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio)); + struct fixed31_32 temp; + int int_part; - int_part = int_part > 0 ? int_part : 0; - *vp_size += int_part < vp_clip ? int_part : vp_clip; - } - - /* Adjust for non-0 viewport offset */ - if (*vp_offset) { - int int_part; - - *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip)); - int_part = dc_fixpt_floor(*init) - *vp_offset; - if (int_part < taps) { - int int_adj = *vp_offset >= (taps - int_part) ? - (taps - int_part) : *vp_offset; - *vp_offset -= int_adj; - *vp_size += int_adj; - int_part += int_adj; - } else if (int_part > taps) { - *vp_offset += int_part - taps; - *vp_size -= int_part - taps; - int_part = taps; - } - init->value &= 0xffffffff; - *init = dc_fixpt_add_int(*init, int_part); - } - } else { - /* Adjust for non-0 viewport offset */ - if (*vp_offset) { - int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio)); - - int_part = int_part > 0 ? int_part : 0; - *vp_size += int_part < *vp_offset ? int_part : *vp_offset; - *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset; - } - - /* Adjust for viewport end clip-off */ - if ((*vp_offset + *vp_size) < src_size) { - int int_part; - int end_offset = src_size - *vp_offset - *vp_size; - - /* - * this is init if vp had no offset, keep in mind this is from the - * right side of vp due to scan direction - */ - *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip)); - /* - * this is the difference between first pixel of viewport available to read - * and init position, takning into account scan direction - */ - int_part = dc_fixpt_floor(*init) - end_offset; - if (int_part < taps) { - int int_adj = end_offset >= (taps - int_part) ? - (taps - int_part) : end_offset; - *vp_size += int_adj; - int_part += int_adj; - } else if (int_part > taps) { - *vp_size += int_part - taps; - int_part = taps; - } - init->value &= 0xffffffff; - *init = dc_fixpt_add_int(*init, int_part); - } + /* + * First of the taps starts sampling pixel number corresponding to recout + * pixel 1. Next recout pixel samples int part of and so on. + * All following calculations are based on this logic. + * + * Init calculated according to formula: + * init = (scaling_ratio + number_of_taps + 1) / 2 + * init_bot = init + scaling_ratio + * to get pixel perfect combine add the fraction from calculating vp offset + */ + temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); + *vp_offset = dc_fixpt_floor(temp); + temp.value &= 0xffffffff; + *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( + dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); + /* + * If viewport has non 0 offset and there are more taps than covered by init then + * we should decrease the offset and increase init so we are never sampling + * outside of viewport. + */ + int_part = dc_fixpt_floor(*init); + if (int_part < taps) { + int_part = taps - int_part; + if (int_part > *vp_offset) + int_part = *vp_offset; + *vp_offset -= int_part; + *init = dc_fixpt_add_int(*init, int_part); } + /* + * If taps are sampling outside of viewport at end of recout and there are more pixels + * available in the surface we should increase the viewport size, regardless set vp to + * only what is used. + */ + temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); + *vp_size = dc_fixpt_floor(temp); + if (*vp_size + *vp_offset > src_size) + *vp_size = src_size - *vp_offset; + + /* We did all the math assuming we are scanning same direction as display does, + * however mirror/rotation changes how vp scans vs how it is offset. If scan direction + * is flipped we simply need to calculate offset from the other side of plane. + * Note that outside of viewport all scaling hardware works in recout space. + */ + if (flip_scan_dir) + *vp_offset = src_size - *vp_offset - *vp_size; } -static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) +static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *odm_pipe = pipe_ctx; struct scaler_data *data = &pipe_ctx->plane_res.scl_data; - struct rect src = pipe_ctx->plane_state->src_rect; - int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v; + struct rect src = plane_state->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 - || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; + || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; + int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; - int odm_idx = 0; + + calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); + /* + * recout full is what the recout would have been if we didnt clip + * the source plane at all. We only care about left(ro_lb) and top(ro_tb) + * offsets of recout within recout full because those are the directions + * we scan from and therefore the only ones that affect inits. + */ + recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) + * stream->dst.width / stream->src.width; + recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) + * stream->dst.height / stream->src.height; + if (pipe_ctx->prev_odm_pipe && split_idx) + ro_lb = data->h_active * split_idx - recout_full_x; + else + ro_lb = data->recout.x - recout_full_x; + ro_tb = data->recout.y - recout_full_y; + ASSERT(ro_lb >= 0 && ro_tb >= 0); /* - * Need to calculate the scan direction for viewport to make adjustments + * Work in recout rotation since that requires less transformations */ get_vp_scan_direction( plane_state->rotation, @@ -1037,145 +960,62 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) &flip_vert_scan_dir, &flip_horz_scan_dir); - /* Calculate src rect rotation adjusted to recout space */ - surf_size_h = src.x + src.width; - surf_size_v = src.y + src.height; - if (flip_horz_scan_dir) - src.x = 0; - if (flip_vert_scan_dir) - src.y = 0; if (orthogonal_rotation) { - swap(src.x, src.y); swap(src.width, src.height); + swap(flip_vert_scan_dir, flip_horz_scan_dir); } - /*modified recout_skip_h calculation due to odm having no recout offset*/ - while (odm_pipe->prev_odm_pipe) { - odm_idx++; - odm_pipe = odm_pipe->prev_odm_pipe; - } - /*odm_pipe is the leftmost pipe in the ODM group*/ - recout_skip_h = odm_idx * data->recout.width; - - /* Recout matching initial vp offset = recout_offset - (stream dst offset + - * ((surf dst offset - stream src offset) * 1/ stream scaling ratio) - * - (surf surf_src offset * 1/ full scl ratio)) - */ - recout_skip_h += odm_pipe->plane_res.scl_data.recout.x - - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x) - * stream->dst.width / stream->src.width - - src.x * plane_state->dst_rect.width / src.width - * stream->dst.width / stream->src.width); - - - recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y) - * stream->dst.height / stream->src.height - - src.y * plane_state->dst_rect.height / src.height - * stream->dst.height / stream->src.height); - if (orthogonal_rotation) - swap(recout_skip_h, recout_skip_v); - /* - * Init calculated according to formula: - * init = (scaling_ratio + number_of_taps + 1) / 2 - * init_bot = init + scaling_ratio - * init_c = init + truncated_vp_c_offset(from calculate viewport) - */ - data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int( - dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19); - - data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int( - dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19); - - data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int( - dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19); - - data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int( - dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19); - - /* - * Taps, inits and scaling ratios are in recout space need to rotate - * to viewport rotation before adjustment - */ - adjust_vp_and_init_for_seamless_clip( + calculate_init_and_vp( flip_horz_scan_dir, - recout_skip_h, - surf_size_h, - orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, - orthogonal_rotation ? data->ratios.vert : data->ratios.horz, - orthogonal_rotation ? &data->inits.v : &data->inits.h, + ro_lb, + data->recout.width, + src.width, + data->taps.h_taps, + data->ratios.horz, + &data->inits.h, &data->viewport.x, &data->viewport.width); - adjust_vp_and_init_for_seamless_clip( + calculate_init_and_vp( flip_horz_scan_dir, - recout_skip_h, - surf_size_h / vpc_div, - orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c, - orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c, - orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c, + ro_lb, + data->recout.width, + src.width / vpc_div, + data->taps.h_taps_c, + data->ratios.horz_c, + &data->inits.h_c, &data->viewport_c.x, &data->viewport_c.width); - adjust_vp_and_init_for_seamless_clip( + calculate_init_and_vp( flip_vert_scan_dir, - recout_skip_v, - surf_size_v, - orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps, - orthogonal_rotation ? data->ratios.horz : data->ratios.vert, - orthogonal_rotation ? &data->inits.h : &data->inits.v, + ro_tb, + data->recout.height, + src.height, + data->taps.v_taps, + data->ratios.vert, + &data->inits.v, &data->viewport.y, &data->viewport.height); - adjust_vp_and_init_for_seamless_clip( + calculate_init_and_vp( flip_vert_scan_dir, - recout_skip_v, - surf_size_v / vpc_div, - orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c, - orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c, - orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c, + ro_tb, + data->recout.height, + src.height / vpc_div, + data->taps.v_taps_c, + data->ratios.vert_c, + &data->inits.v_c, &data->viewport_c.y, &data->viewport_c.height); - - /* Interlaced inits based on final vert inits */ - data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert); - data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c); - -} - -/* - * When handling 270 rotation in mixed SLS mode, we have - * stream->timing.h_border_left that is non zero. If we are doing - * pipe-splitting, this h_border_left value gets added to recout.x and when it - * calls calculate_inits_and_adj_vp() and - * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a - * pipe to be incorrect. - * - * To fix this, instead of using stream->timing.h_border_left, we can use - * stream->dst.x to represent the border instead. So we will set h_border_left - * to 0 and shift the appropriate amount in stream->dst.x. We will then - * perform all calculations in resource_build_scaling_params() based on this - * and then restore the h_border_left and stream->dst.x to their original - * values. - * - * shift_border_left_to_dst() will shift the amount of h_border_left to - * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst() - * will restore h_border_left and stream->dst.x back to their original values - * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the - * original h_border_left value in its calculation. - */ -static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx) -{ - int store_h_border_left = pipe_ctx->stream->timing.h_border_left; - - if (store_h_border_left) { - pipe_ctx->stream->timing.h_border_left = 0; - pipe_ctx->stream->dst.x += store_h_border_left; + if (orthogonal_rotation) { + swap(data->viewport.x, data->viewport.y); + swap(data->viewport.width, data->viewport.height); + swap(data->viewport_c.x, data->viewport_c.y); + swap(data->viewport_c.width, data->viewport_c.height); } - return store_h_border_left; -} - -static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx, - int store_h_border_left) -{ - pipe_ctx->stream->dst.x -= store_h_border_left; - pipe_ctx->stream->timing.h_border_left = store_h_border_left; + data->viewport.x += src.x; + data->viewport.y += src.y; + ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); + data->viewport_c.x += src.x / vpc_div; + data->viewport_c.y += src.y / vpc_div; } bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) @@ -1183,48 +1023,52 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) const struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; bool res = false; - int store_h_border_left = shift_border_left_to_dst(pipe_ctx); DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); - /* Important: scaling ratio calculation requires pixel format, - * lb depth calculation requires recout and taps require scaling ratios. - * Inits require viewport, taps, ratios and recout of split pipe - */ + pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( pipe_ctx->plane_state->format); - calculate_scaling_ratios(pipe_ctx); - - calculate_viewport(pipe_ctx); - - if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || - pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) { - if (store_h_border_left) { - restore_border_left_from_dst(pipe_ctx, - store_h_border_left); - } - return false; - } - - calculate_recout(pipe_ctx); - - /** - * Setting line buffer pixel depth to 24bpp yields banding - * on certain displays, such as the Sharp 4k + /* Timing borders are part of vactive that we are also supposed to skip in addition + * to any stream dst offset. Since dm logic assumes dst is in addressable + * space we need to add the the left and top borders to dst offsets temporarily. + * TODO: fix in DM, stream dst is supposed to be in vactive */ - pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; - pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; - - pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; - pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; + pipe_ctx->stream->dst.x += timing->h_border_left; + pipe_ctx->stream->dst.y += timing->v_border_top; + /* Calculate H and V active size */ pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + - store_h_border_left + timing->h_border_right; + timing->h_border_left + timing->h_border_right; pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; - /* Taps calculations */ + /* depends on h_active */ + calculate_recout(pipe_ctx); + /* depends on pixel format */ + calculate_scaling_ratios(pipe_ctx); + /* depends on scaling ratios and recout, does not calculate offset yet */ + calculate_viewport_size(pipe_ctx); + + /* + * LB calculations depend on vp size, h/v_active and scaling ratios + * Setting line buffer pixel depth to 24bpp yields banding + * on certain displays, such as the Sharp 4k. 36bpp is needed + * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and + * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc + * precision on at least DCN display engines. However, at least + * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, + * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 + * did not show such problems, so this seems to be the exception. + */ + if (plane_state->ctx->dce_version != DCE_VERSION_11_0) + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; + else + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; + + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; + if (pipe_ctx->plane_res.xfm != NULL) res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); @@ -1251,9 +1095,31 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) &plane_state->scaling_quality); } + /* + * Depends on recout, scaling ratios, h_active and taps + * May need to re-check lb size after this in some obscure scenario + */ if (res) - /* May need to re-check lb size after this in some obscure scenario */ - calculate_inits_and_adj_vp(pipe_ctx); + calculate_inits_and_viewports(pipe_ctx); + + /* + * Handle side by side and top bottom 3d recout offsets after vp calculation + * since 3d is special and needs to calculate vp as if there is no recout offset + * This may break with rotation, good thing we aren't mixing hw rotation and 3d + */ + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { + ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || + (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && + pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); + if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; + else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) + pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; + } + + if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || + pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) + res = false; DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", @@ -1282,8 +1148,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) plane_state->clip_rect.x, plane_state->clip_rect.y); - if (store_h_border_left) - restore_border_left_from_dst(pipe_ctx, store_h_border_left); + pipe_ctx->stream->dst.x -= timing->h_border_left; + pipe_ctx->stream->dst.y -= timing->v_border_top; return res; } @@ -1706,12 +1572,6 @@ static bool is_timing_changed(struct dc_stream_state *cur_stream, if (cur_stream == NULL) return true; - /* If sink pointer changed, it means this is a hotplug, we should do - * full hw setting. - */ - if (cur_stream->sink != new_stream->sink) - return true; - /* If output color space is changed, need to reprogram info frames */ if (cur_stream->output_color_space != new_stream->output_color_space) return true; @@ -2276,6 +2136,16 @@ enum dc_status dc_validate_global_state( if (!new_ctx) return DC_ERROR_UNEXPECTED; +#if defined(CONFIG_DRM_AMD_DC_DCN) + + /* + * Update link encoder to stream assignment. + * TODO: Split out reason allocation from validation. + */ + if (dc->res_pool->funcs->link_encs_assign) + dc->res_pool->funcs->link_encs_assign( + dc, new_ctx, new_ctx->streams, new_ctx->stream_count); +#endif if (dc->res_pool->funcs->validate_global) { result = dc->res_pool->funcs->validate_global(dc, new_ctx); @@ -2679,6 +2549,7 @@ void dc_resource_state_destruct(struct dc_state *context) dc_stream_release(context->streams[i]); context->streams[i] = NULL; } + context->stream_count = 0; } void dc_resource_state_copy_construct( @@ -3045,6 +2916,7 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) #endif return 32; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: return 64; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 25fa712a7847..45931ee14a6e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -294,6 +294,7 @@ bool dc_stream_set_cursor_attributes( stream->cursor_attributes = *attributes; #if defined(CONFIG_DRM_AMD_DC_DCN) + dc_z10_restore(dc); /* disable idle optimizations while updating cursor */ if (dc->idle_optimizations_allowed) { dc_allow_idle_optimizations(dc, false); @@ -355,6 +356,7 @@ bool dc_stream_set_cursor_position( dc = stream->ctx->dc; res_ctx = &dc->current_state->res_ctx; #if defined(CONFIG_DRM_AMD_DC_DCN) + dc_z10_restore(dc); /* disable idle optimizations if enabling cursor */ if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 100d434f7a03..5101a4f8f69f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.132" +#define DC_VER "3.2.141" #define MAX_SURFACES 3 #define MAX_PLANES 6 @@ -303,6 +303,7 @@ struct dc_config { bool multi_mon_pp_mclk_switch; bool disable_dmcu; bool enable_4to1MPC; + bool allow_edp_hotplug_detection; #if defined(CONFIG_DRM_AMD_DC_DCN) bool clamp_min_dcfclk; #endif @@ -318,6 +319,7 @@ enum visual_confirm { VISUAL_CONFIRM_HDR = 2, VISUAL_CONFIRM_MPCTREE = 4, VISUAL_CONFIRM_PSR = 5, + VISUAL_CONFIRM_SWIZZLE = 9, }; enum dcc_option { @@ -350,6 +352,13 @@ enum dcn_pwr_state { DCN_PWR_STATE_LOW_POWER = 3, }; +#if defined(CONFIG_DRM_AMD_DC_DCN) +enum dcn_z9_support_state { + DCN_Z9_SUPPORT_UNKNOWN, + DCN_Z9_SUPPORT_ALLOW, + DCN_Z9_SUPPORT_DISALLOW, +}; +#endif /* * For any clocks that may differ per pipe * only the max is stored in this structure @@ -367,6 +376,10 @@ struct dc_clocks { int phyclk_khz; int dramclk_khz; bool p_state_change_support; +#if defined(CONFIG_DRM_AMD_DC_DCN) + enum dcn_z9_support_state z9_support; + bool dtbclk_en; +#endif enum dcn_pwr_state pwr_state; /* * Elements below are not compared for the purposes of @@ -433,6 +446,7 @@ struct dc_bw_validation_profile { union mem_low_power_enable_options { struct { + bool vga: 1; bool i2c: 1; bool dmcu: 1; bool dscl: 1; @@ -487,6 +501,9 @@ struct dc_debug_options { bool disable_pplib_clock_request; bool disable_clock_gate; bool disable_mem_low_power; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool pstate_enabled; +#endif bool disable_dmcu; bool disable_psr; bool force_abm_enable; @@ -505,6 +522,7 @@ struct dc_debug_options { unsigned int force_odm_combine; //bit vector based on otg inst #if defined(CONFIG_DRM_AMD_DC_DCN) unsigned int force_odm_combine_4to1; //bit vector based on otg inst + bool disable_z9_mpc; #endif unsigned int force_fclk_khz; bool enable_tri_buf; @@ -547,6 +565,10 @@ struct dc_debug_options { bool force_enable_edp_fec; /* FEC/PSR1 sequence enable delay in 100us */ uint8_t fec_enable_delay_in100us; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool disable_z10; + bool enable_sw_cntl_psr; +#endif }; struct dc_debug_data { @@ -571,6 +593,9 @@ struct dc_phy_addr_space_config { uint64_t page_table_start_addr; uint64_t page_table_end_addr; uint64_t page_table_base_addr; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool base_addr_is_mc_addr; +#endif } gart_config; bool valid; @@ -600,7 +625,6 @@ struct dc_bounding_box_overrides { int min_dcfclk_mhz; }; -struct dc_state; struct resource_pool; struct dce_hwseq; struct gpu_info_soc_bounding_box_v1_0; @@ -719,7 +743,6 @@ void dc_init_callbacks(struct dc *dc, void dc_deinit_callbacks(struct dc *dc); void dc_destroy(struct dc **dc); -void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream); /******************************************************************************* * Surface Interfaces ******************************************************************************/ @@ -1071,8 +1094,6 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); */ bool dc_commit_state(struct dc *dc, struct dc_state *context); -void dc_power_down_on_boot(struct dc *dc); - struct dc_state *dc_create_state(struct dc *dc); struct dc_state *dc_copy_state(struct dc_state *src_ctx); void dc_retain_state(struct dc_state *context); @@ -1312,6 +1333,9 @@ void dc_hardware_release(struct dc *dc); #endif bool dc_set_psr_allow_active(struct dc *dc, bool enable); +#if defined(CONFIG_DRM_AMD_DC_DCN) +void dc_z10_restore(struct dc *dc); +#endif bool dc_enable_dmub_notifications(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 6b72af2b3f4c..360f3199ea6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -86,6 +86,7 @@ void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, error: DC_ERROR("Error queuing DMUB command: status=%d\n", status); + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); } void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) @@ -95,8 +96,10 @@ void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) enum dmub_status status; status = dmub_srv_cmd_execute(dmub); - if (status != DMUB_STATUS_OK) + if (status != DMUB_STATUS_OK) { DC_ERROR("Error starting DMUB execution: status=%d\n", status); + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + } } void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) @@ -106,8 +109,19 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) enum dmub_status status; status = dmub_srv_wait_for_idle(dmub, 100000); - if (status != DMUB_STATUS_OK) + if (status != DMUB_STATUS_OK) { DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + } +} + +void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, + union dmub_inbox0_data_register data) +{ + struct dmub_srv *dmub = dmub_srv->dmub; + if (dmub->hw_funcs.send_inbox0_cmd) + dmub->hw_funcs.send_inbox0_cmd(dmub, data); + // TODO: Add wait command -- poll register for ACK } bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) @@ -172,6 +186,28 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, stream_mask, timeout) == DMUB_STATUS_OK; } +bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) +{ + struct dmub_srv *dmub; + struct dc_context *dc_ctx; + union dmub_fw_boot_status boot_status; + enum dmub_status status; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return false; + + dmub = dc_dmub_srv->dmub; + dc_ctx = dc_dmub_srv->ctx; + + status = dmub_srv_get_fw_boot_status(dmub, &boot_status); + if (status != DMUB_STATUS_OK) { + DC_ERROR("Error querying DMUB boot status: error=%d\n", status); + return false; + } + + return boot_status.bits.restore_required; +} + bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) { struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; @@ -180,5 +216,96 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu void dc_dmub_trace_event_control(struct dc *dc, bool enable) { - dm_helpers_dmub_outbox0_interrupt_control(dc->ctx, enable); + dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); +} + +bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) +{ + if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) + return false; + return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); +} + +void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) +{ + struct dmub_diagnostic_data diag_data = {0}; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) { + DC_LOG_ERROR("%s: invalid parameters.", __func__); + return; + } + + if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { + DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); + return; + } + + DC_LOG_DEBUG( + "DMCUB STATE\n" + " dmcub_version : %08x\n" + " scratch [0] : %08x\n" + " scratch [1] : %08x\n" + " scratch [2] : %08x\n" + " scratch [3] : %08x\n" + " scratch [4] : %08x\n" + " scratch [5] : %08x\n" + " scratch [6] : %08x\n" + " scratch [7] : %08x\n" + " scratch [8] : %08x\n" + " scratch [9] : %08x\n" + " scratch [10] : %08x\n" + " scratch [11] : %08x\n" + " scratch [12] : %08x\n" + " scratch [13] : %08x\n" + " scratch [14] : %08x\n" + " scratch [15] : %08x\n" + " pc : %08x\n" + " unk_fault_addr : %08x\n" + " inst_fault_addr : %08x\n" + " data_fault_addr : %08x\n" + " inbox1_rptr : %08x\n" + " inbox1_wptr : %08x\n" + " inbox1_size : %08x\n" + " inbox0_rptr : %08x\n" + " inbox0_wptr : %08x\n" + " inbox0_size : %08x\n" + " is_enabled : %d\n" + " is_soft_reset : %d\n" + " is_secure_reset : %d\n" + " is_traceport_en : %d\n" + " is_cw0_en : %d\n" + " is_cw6_en : %d\n", + diag_data.dmcub_version, + diag_data.scratch[0], + diag_data.scratch[1], + diag_data.scratch[2], + diag_data.scratch[3], + diag_data.scratch[4], + diag_data.scratch[5], + diag_data.scratch[6], + diag_data.scratch[7], + diag_data.scratch[8], + diag_data.scratch[9], + diag_data.scratch[10], + diag_data.scratch[11], + diag_data.scratch[12], + diag_data.scratch[13], + diag_data.scratch[14], + diag_data.scratch[15], + diag_data.pc, + diag_data.undefined_address_fault_addr, + diag_data.inst_fetch_fault_addr, + diag_data.data_write_fault_addr, + diag_data.inbox1_rptr, + diag_data.inbox1_wptr, + diag_data.inbox1_size, + diag_data.inbox0_rptr, + diag_data.inbox0_wptr, + diag_data.inbox0_size, + diag_data.is_dmcub_enabled, + diag_data.is_dmcub_soft_reset, + diag_data.is_dmcub_secure_reset, + diag_data.is_traceport_en, + diag_data.is_cw0_enabled, + diag_data.is_cw6_enabled); } diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 338f776990db..3e35eee7188c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -62,8 +62,16 @@ bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, unsigned int stream_mask); +bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv); + bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry); void dc_dmub_trace_event_control(struct dc *dc, bool enable); +void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); + +bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *dmub_oca); + +void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); + #endif /* _DMUB_DC_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index cc6fb838420e..1948cd9427d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -95,6 +95,12 @@ enum dc_dp_training_pattern { DP_TRAINING_PATTERN_SEQUENCE_2, DP_TRAINING_PATTERN_SEQUENCE_3, DP_TRAINING_PATTERN_SEQUENCE_4, + DP_TRAINING_PATTERN_VIDEOIDLE, +}; + +enum dp_link_encoding { + DP_UNKNOWN_ENCODING = 0, + DP_8b_10b_ENCODING = 1, }; struct dc_link_settings { diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index c51d2d961b7a..16cc76ce3739 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -78,7 +78,8 @@ bool dc_dsc_compute_config( const struct dc_crtc_timing *timing, struct dc_dsc_config *dsc_cfg); -uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16); +uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, + uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp); void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, @@ -88,6 +89,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable); -uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16); +void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index bcec019efa6f..52355fe6994c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -182,6 +182,8 @@ enum surface_pixel_format { SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, /*64 bpp */ SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, + /*swapped*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, /*float*/ SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, /*swaped & float*/ @@ -739,6 +741,7 @@ struct dc_dsc_config { uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ + bool is_dp; /* indicate if DSC is applied based on DP's capability */ }; struct dc_crtc_timing { uint32_t h_total; diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index 054bab45ee17..83845d006c54 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -36,12 +36,6 @@ enum dc_link_fec_state { dc_link_fec_enabled }; -enum lttpr_mode { - LTTPR_MODE_NON_LTTPR, - LTTPR_MODE_TRANSPARENT, - LTTPR_MODE_NON_TRANSPARENT, -}; - struct dc_link_status { bool link_active; struct dpcd_caps *dpcd_caps; @@ -113,6 +107,7 @@ struct dc_link { /* TODO: Rename. Flag an endpoint as having a programmable mapping to a * DIG encoder. */ bool is_dig_mapping_flexible; + bool hpd_status; /* HPD status of link without physical HPD pin. */ bool edp_sink_present; @@ -221,6 +216,23 @@ static inline void get_edp_links(const struct dc *dc, } } +static inline bool dc_get_edp_link_panel_inst(const struct dc *dc, + const struct dc_link *link, + unsigned int *inst_out) +{ + struct dc_link *edp_links[MAX_NUM_EDP]; + int edp_num; + + if (link->connector_signal != SIGNAL_TYPE_EDP) + return false; + get_edp_links(dc, edp_links, &edp_num); + if ((edp_num > 1) && (link->link_index > edp_links[0]->link_index)) + *inst_out = 1; + else + *inst_out = 0; + return true; +} + /* Set backlight level of an embedded panel (eDP, LVDS). * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer * and 16 bit fractional, where 1.0 is max backlight value. @@ -321,7 +333,7 @@ bool dc_link_dp_perform_link_training_skip_aux( enum link_training_result dc_link_dp_perform_link_training( struct dc_link *link, - const struct dc_link_settings *link_setting, + const struct dc_link_settings *link_settings, bool skip_video_pattern); bool dc_link_dp_sync_lt_begin(struct dc_link *link); @@ -345,6 +357,8 @@ bool dc_link_dp_set_test_pattern( const unsigned char *p_custom_pattern, unsigned int cust_pattern_size); +bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap); + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); bool dc_link_is_dp_sink_present(struct dc_link *link); @@ -361,9 +375,6 @@ bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); void dc_link_set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link); -void dc_link_perform_link_training(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern); void dc_link_set_preferred_link_settings(struct dc *dc, struct dc_link_settings *link_setting, struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 13dae7238a58..b8ebc1f09538 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -179,6 +179,9 @@ struct dc_stream_state { bool use_vsc_sdp_for_colorimetry; bool ignore_msa_timing_param; + + bool freesync_on_desktop; + bool converter_disable_audio; uint8_t qs_bit; uint8_t qy_bit; @@ -462,6 +465,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust); +bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, + struct dc_stream_state *stream, + uint32_t *refresh_rate); + bool dc_stream_get_crtc_position(struct dc *dc, struct dc_stream_state **stream, int num_streams, diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 432754eaf10b..8016e22114ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -271,11 +271,6 @@ struct dc_edid_caps { struct dc_panel_patch panel_patch; }; -struct view { - uint32_t width; - uint32_t height; -}; - struct dc_mode_flags { /* note: part of refresh rate flag*/ uint32_t INTERLACE :1; @@ -404,7 +399,7 @@ enum dc_connection_type { dc_connection_none, dc_connection_single, dc_connection_mst_branch, - dc_connection_active_dongle + dc_connection_sst_branch }; struct dc_csc_adjustments { @@ -909,6 +904,7 @@ struct dsc_dec_dpcd_caps { uint32_t branch_overall_throughput_0_mps; /* In MPs */ uint32_t branch_overall_throughput_1_mps; /* In MPs */ uint32_t branch_max_line_width; + bool is_dp; }; struct dc_golden_table { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index 87d57e81de12..2fb88e54a4bf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -595,8 +595,28 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, return res; } +int dce_aux_transfer_dmub_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) +{ + struct ddc *ddc_pin = ddc->ddc_pin; + + if (ddc_pin != NULL) { + struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; + /* XXX: Workaround to configure ddc channels for aux transactions */ + if (!acquire(aux_engine, ddc_pin)) { + *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; + return -1; + } + release_engine(aux_engine); + } + + return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result); +} + #define AUX_MAX_RETRIES 7 -#define AUX_MAX_DEFER_RETRIES 7 +#define AUX_MIN_DEFER_RETRIES 7 +#define AUX_MAX_DEFER_TIMEOUT_MS 50 #define AUX_MAX_I2C_DEFER_RETRIES 7 #define AUX_MAX_INVALID_REPLY_RETRIES 2 #define AUX_MAX_TIMEOUT_RETRIES 3 @@ -609,6 +629,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, bool payload_reply = true; enum aux_return_code_type operation_result; bool retry_on_defer = false; + struct ddc *ddc_pin = ddc->ddc_pin; + struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; + struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine); + uint32_t defer_time_in_ms = 0; int aux_ack_retries = 0, aux_defer_retries = 0, @@ -641,19 +665,27 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, break; case AUX_TRANSACTION_REPLY_AUX_DEFER: + /* polling_timeout_period is in us */ + defer_time_in_ms += aux110->polling_timeout_period / 1000; + ++aux_defer_retries; + fallthrough; case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: retry_on_defer = true; fallthrough; case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK: - if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) { + if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES + && defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) { goto fail; } else { if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) || (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) { - if (payload->defer_delay > 1) + if (payload->defer_delay > 1) { msleep(payload->defer_delay); - else if (payload->defer_delay <= 1) + defer_time_in_ms += payload->defer_delay; + } else if (payload->defer_delay <= 1) { udelay(payload->defer_delay * 1000); + defer_time_in_ms += payload->defer_delay; + } } } break; @@ -682,7 +714,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, // Check whether a DEFER had occurred before the timeout. // If so, treat timeout as a DEFER. if (retry_on_defer) { - if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) + if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES) goto fail; else if (payload->defer_delay > 0) msleep(payload->defer_delay); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h index 566b1bddd8cc..e69f1899fbf0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h @@ -304,6 +304,9 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *cmd, enum aux_return_code_type *operation_result); +int dce_aux_transfer_dmub_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result); bool dce_aux_transfer_with_retries(struct ddc_service *ddc, struct aux_payload *cmd); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 7fe5a07e2233..3139285bd403 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -142,6 +142,15 @@ SRII(PIXEL_RATE_CNTL, OTG, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 4) +#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PIXEL_RATE_CNTL, OTG, 1) + #endif #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index fe31abfa6c85..df6539e4c730 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -480,6 +480,35 @@ SR(AZALIA_AUDIO_DTO), \ SR(AZALIA_CONTROLLER_CLOCK_GATING) +#define HWSEQ_DCN303_REG_LIST() \ + HWSEQ_DCN_REG_LIST(), \ + HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ + HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ + SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_GB), \ + SR(MPC_CRC_RESULT_C), \ + SR(MPC_CRC_RESULT_AR), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL), \ + SR(D5VGA_CONTROL), \ + SR(D6VGA_CONTROL), \ + HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \ + HWSEQ_PHYPLL_REG_LIST_303(OTG), \ + SR(AZALIA_AUDIO_DTO), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING), \ + SR(HPO_TOP_CLOCK_CONTROL) + #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \ SRII(PIXEL_RATE_CNTL, blk, 0), \ SRII(PIXEL_RATE_CNTL, blk, 1),\ @@ -494,6 +523,14 @@ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4) +#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \ + SRII(PIXEL_RATE_CNTL, blk, 0), \ + SRII(PIXEL_RATE_CNTL, blk, 1) + +#define HWSEQ_PHYPLL_REG_LIST_303(blk) \ + SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) + struct dce_hwseq_registers { uint32_t DCFE_CLOCK_CONTROL[6]; uint32_t DCFEV_CLOCK_CONTROL; @@ -598,6 +635,7 @@ struct dce_hwseq_registers { uint32_t HPO_TOP_CLOCK_CONTROL; uint32_t ODM_MEM_PWR_CTRL3; uint32_t DMU_MEM_PWR_CNTL; + uint32_t MMHUBBUB_MEM_PWR_CNTL; }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ @@ -838,7 +876,8 @@ struct dce_hwseq_registers { HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ - HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh) + HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ + HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ @@ -934,6 +973,12 @@ struct dce_hwseq_registers { HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) +#define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh) + #define HWSEQ_REG_FIELD_LIST(type) \ type DCFE_CLOCK_ENABLE; \ type DCFEV_CLOCK_ENABLE; \ @@ -1049,7 +1094,8 @@ struct dce_hwseq_registers { type AZALIA_AUDIO_DTO_MODULE; \ type ODM_MEM_UNASSIGNED_PWR_MODE; \ type ODM_MEM_VBLANK_PWR_MODE; \ - type DMCU_ERAM_MEM_PWR_FORCE; + type DMCU_ERAM_MEM_PWR_FORCE; \ + type VGA_MEM_PWR_FORCE; #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ type HPO_HDMISTREAMCLK_GATE_DIS; @@ -1060,11 +1106,18 @@ struct dce_hwseq_registers { type PANEL_DIGON_OVRD;\ type PANEL_PWRSEQ_TARGET_STATE_R; +#define HWSEQ_DCN31_REG_FIELD_LIST(type) \ + type DOMAIN_POWER_FORCEON;\ + type DOMAIN_POWER_GATE;\ + type DOMAIN_PGFSM_PWR_STATUS;\ + type HPO_HDMISTREAMCLK_G_GATE_DIS; + struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) HWSEQ_DCN_REG_FIELD_LIST(uint8_t) HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) + HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) }; struct dce_hwseq_mask { @@ -1072,6 +1125,7 @@ struct dce_hwseq_mask { HWSEQ_DCN_REG_FIELD_LIST(uint32_t) HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) + HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index a524f471e0d7..6d1b01c267b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -264,18 +264,25 @@ static void set_speed( struct dce_i2c_hw *dce_i2c_hw, uint32_t speed) { - uint32_t xtal_ref_div = 0; + uint32_t xtal_ref_div = 0, ref_base_div = 0; uint32_t prescale = 0; + uint32_t i2c_ref_clock = 0; if (speed == 0) return; - REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); + REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div, + XTAL_REF_DIV, &xtal_ref_div); if (xtal_ref_div == 0) xtal_ref_div = 2; - prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / speed; + if (ref_base_div == 0) + i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2); + else + i2c_ref_clock = ref_base_div * 1000; + + prescale = (i2c_ref_clock / xtal_ref_div) / speed; if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) REG_UPDATE_N(SPEED, 3, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h index 2309f2bb162c..3f45ecd189a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h @@ -139,6 +139,7 @@ enum { I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\ I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\ I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\ + I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\ I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh) #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ @@ -182,6 +183,7 @@ struct dce_i2c_shift { uint8_t DC_I2C_INDEX; uint8_t DC_I2C_INDEX_WRITE; uint8_t XTAL_REF_DIV; + uint8_t MICROSECOND_TIME_BASE_DIV; uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH; uint8_t DC_I2C_REG_RW_CNTL_STATUS; uint8_t I2C_LIGHT_SLEEP_FORCE; @@ -225,6 +227,7 @@ struct dce_i2c_mask { uint32_t DC_I2C_INDEX; uint32_t DC_I2C_INDEX_WRITE; uint32_t XTAL_REF_DIV; + uint32_t MICROSECOND_TIME_BASE_DIV; uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; uint32_t DC_I2C_REG_RW_CNTL_STATUS; uint32_t I2C_LIGHT_SLEEP_FORCE; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 79a6f261a0da..4cdd4dacb761 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -566,6 +566,7 @@ static void program_grph_pixel_format( * should problem swap endian*/ format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS || + format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { /* ABGR formats */ red_xbar = 2; @@ -606,6 +607,7 @@ static void program_grph_pixel_format( fallthrough; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: grph_depth = 3; grph_format = 0; break; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 23db5c72f07e..f98400efdd9b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -181,7 +181,6 @@ struct dce_mem_input_registers { SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ - SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ @@ -207,7 +206,6 @@ struct dce_mem_input_registers { SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ - SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ @@ -299,6 +297,7 @@ struct dce_mem_input_registers { MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 151dc7bf6d23..d9fd4ec60588 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -794,7 +794,7 @@ static void program_bit_depth_reduction( enum dcp_out_trunc_round_mode trunc_mode; bool spatial_dither_enable; - ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */ + ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; /* Default to 12 bit truncation without rounding */ @@ -854,7 +854,7 @@ static void dce60_program_bit_depth_reduction( enum dcp_out_trunc_round_mode trunc_mode; bool spatial_dither_enable; - ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */ + ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; /* Default to 12 bit truncation without rounding */ @@ -1647,7 +1647,8 @@ void dce_transform_construct( xfm_dce->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ @@ -1675,7 +1676,8 @@ void dce60_transform_construct( xfm_dce->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c index eb1698d54a48..54a1408c8015 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c @@ -56,11 +56,19 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) { union dmub_rb_cmd cmd; uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; + uint32_t edp_id_count = dc->dc_edp_id_count; + int i; + uint8_t panel_mask = 0; + + for (i = 0; i < edp_id_count; i++) + panel_mask |= 0x01 << i; memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM; cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC; cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm; + cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; + cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask; cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pwm_frac_data); dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); @@ -135,11 +143,24 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level) { union dmub_rb_cmd cmd; struct dc_context *dc = abm->ctx; + struct dc_link *edp_links[MAX_NUM_EDP]; + int i; + int edp_num; + uint8_t panel_mask = 0; + + get_edp_links(dc->dc, edp_links, &edp_num); + + for (i = 0; i < edp_num; i++) { + if (edp_links[i]->link_status.link_active) + panel_mask |= (0x01 << i); + } memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_level.header.type = DMUB_CMD__ABM; cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL; cmd.abm_set_level.abm_set_level_data.level = level; + cmd.abm_set_level.abm_set_level_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; + cmd.abm_set_level.abm_set_level_data.panel_mask = panel_mask; cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_level_data); dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); @@ -151,10 +172,12 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level) static bool dmub_abm_init_config(struct abm *abm, const char *src, - unsigned int bytes) + unsigned int bytes, + unsigned int inst) { union dmub_rb_cmd cmd; struct dc_context *dc = abm->ctx; + uint8_t panel_mask = 0x01 << inst; // TODO: Optimize by only reading back final 4 bytes dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb); @@ -168,6 +191,9 @@ static bool dmub_abm_init_config(struct abm *abm, cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; cmd.abm_init_config.abm_init_config_data.bytes = bytes; + cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; + cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask; + cmd.abm_init_config.header.payload_bytes = sizeof(struct dmub_cmd_abm_init_config_data); dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index c97ee5abc0ef..9baf8ca0a920 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -52,6 +52,14 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, dc_dmub_srv_wait_idle(dmub_srv); } +void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, + union dmub_inbox0_cmd_lock_hw hw_lock_cmd) +{ + union dmub_inbox0_data_register data = { 0 }; + data.inbox0_cmd_lock_hw = hw_lock_cmd; + dc_dmub_srv_send_inbox0_cmd(dmub_srv, data); +} + bool should_use_dmub_lock(struct dc_link *link) { return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index bc5906347493..5a72b168fb4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -34,6 +34,9 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, union dmub_hw_lock_flags *hw_locks, struct dmub_hw_lock_inst_flags *inst_flags); +void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, + union dmub_inbox0_cmd_lock_hw hw_lock_cmd); + bool should_use_dmub_lock(struct dc_link *link); #endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c index 295596d1f47f..faad8555ddbb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c @@ -27,19 +27,10 @@ #include "dmub/inc/dmub_cmd.h" /** - ***************************************************************************** - * Function: dmub_enable_outbox_notification - * - * @brief - * Sends inbox cmd to dmub to enable outbox1 messages with interrupt. - * Dmub sends outbox1 message and triggers outbox1 interrupt. - * - * @param - * [in] dc: dc structure - * - * @return - * None - ***************************************************************************** + * dmub_enable_outbox_notification - Sends inbox cmd to dmub to enable outbox1 + * messages with interrupt. Dmub sends outbox1 + * message and triggers outbox1 interrupt. + * @dc: dc structure */ void dmub_enable_outbox_notification(struct dc *dc) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 5e99553fcdd4..10d42ae0cffe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -77,7 +77,7 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state) /* * Get PSR state from firmware. */ -static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state) +static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst) { struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; uint32_t raw_state = 0; @@ -86,7 +86,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state) do { // Send gpint command and wait for ack - status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30); + status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30); if (status == DMUB_STATUS_OK) { // GPINT was executed, get response @@ -105,7 +105,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state) /* * Set PSR version. */ -static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream) +static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -125,6 +125,8 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state * cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED; break; } + cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst; cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); @@ -137,7 +139,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state * /* * Enable/Disable PSR. */ -static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) +static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -147,6 +149,9 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) memset(&cmd, 0, sizeof(cmd)); cmd.psr_enable.header.type = DMUB_CMD__PSR; + cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + cmd.psr_enable.data.panel_inst = panel_inst; + if (enable) cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; else @@ -164,7 +169,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) */ if (wait) { for (retry_count = 0; retry_count <= 1000; retry_count++) { - dmub_psr_get_state(dmub, &state); + dmub_psr_get_state(dmub, &state, panel_inst); if (enable) { if (state != PSR_STATE0) @@ -186,13 +191,13 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) /* * Set PSR level. */ -static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) +static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst) { union dmub_rb_cmd cmd; enum dc_psr_state state = PSR_STATE0; struct dc_context *dc = dmub->ctx; - dmub_psr_get_state(dmub, &state); + dmub_psr_get_state(dmub, &state, panel_inst); if (state == PSR_STATE0) return; @@ -202,7 +207,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; - + cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1; + cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); dc_dmub_srv_cmd_execute(dc->dmub_srv); dc_dmub_srv_wait_idle(dc->dmub_srv); @@ -213,7 +219,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) */ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, struct dc_link *link, - struct psr_context *psr_context) + struct psr_context *psr_context, + uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -237,7 +244,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, return false; // First, set the psr version - if (!dmub_psr_set_version(dmub, pipe_ctx->stream)) + if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst)) return false; // Program DP DPHY fast training registers @@ -286,6 +293,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; + copy_settings_data->cmd_version = PSR_VERSION_1; + copy_settings_data->panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); dc_dmub_srv_cmd_execute(dc->dmub_srv); @@ -297,12 +306,15 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, /* * Send command to PSR to force static ENTER and ignore all state changes until exit */ -static void dmub_psr_force_static(struct dmub_psr *dmub) +static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; memset(&cmd, 0, sizeof(cmd)); + + cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst; + cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; cmd.psr_force_static.header.type = DMUB_CMD__PSR; cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC; cmd.psr_enable.header.payload_bytes = 0; @@ -315,12 +327,13 @@ static void dmub_psr_force_static(struct dmub_psr *dmub) /* * Get PSR residency from firmware. */ -static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency) +static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst) { struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; + uint16_t param = (uint16_t)(panel_inst << 8); - // Send gpint command and wait for ack - dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30); + /* Send gpint command and wait for ack */ + dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30); dmub_srv_get_gpint_response(srv, residency); } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h index fe747c20a0d2..9675c269e649 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h @@ -35,12 +35,17 @@ struct dmub_psr { }; struct dmub_psr_funcs { - bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context); - void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait); - void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state); - void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level); - void (*psr_force_static)(struct dmub_psr *dmub); - void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency); + bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, + struct psr_context *psr_context, uint8_t panel_inst); + void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait, + uint8_t panel_inst); + void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state, + uint8_t panel_inst); + void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level, + uint8_t panel_inst); + void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst); + void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency, + uint8_t panel_inst); }; struct dmub_psr *dmub_psr_create(struct dc_context *ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5ddeee96bf23..2938caaa2299 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -32,7 +32,6 @@ #include "core_status.h" #include "resource.h" #include "dm_helpers.h" -#include "dce110_hw_sequencer.h" #include "dce110_timing_generator.h" #include "dce/dce_hwseq.h" #include "gpio_service_interface.h" @@ -49,6 +48,9 @@ #include "link_encoder.h" #include "link_hwss.h" #include "dc_link_dp.h" +#if defined(CONFIG_DRM_AMD_DC_DCN) +#include "dccg.h" +#endif #include "clock_source.h" #include "clk_mgr.h" #include "abm.h" @@ -63,6 +65,8 @@ #include "atomfirmware.h" +#include "dcn10/dcn10_hw_sequencer.h" + #define GAMMA_HW_POINTS_NUM 256 /* @@ -264,6 +268,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, prescale_params->scale = 0x2008; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: prescale_params->scale = 0x2000; break; @@ -1306,41 +1311,6 @@ static void build_audio_output( pipe_ctx->pll_settings.ss_percentage; } -static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, - struct tg_color *color) -{ - uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; - - switch (pipe_ctx->plane_res.scl_data.format) { - case PIXEL_FORMAT_ARGB8888: - /* set boarder color to red */ - color->color_r_cr = color_value; - break; - - case PIXEL_FORMAT_ARGB2101010: - /* set boarder color to blue */ - color->color_b_cb = color_value; - break; - case PIXEL_FORMAT_420BPP8: - /* set boarder color to green */ - color->color_g_y = color_value; - break; - case PIXEL_FORMAT_420BPP10: - /* set boarder color to yellow */ - color->color_g_y = color_value; - color->color_r_cr = color_value; - break; - case PIXEL_FORMAT_FP16: - /* set boarder color to white */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; - color->color_g_y = color_value; - break; - default: - break; - } -} - static void program_scaler(const struct dc *dc, const struct pipe_ctx *pipe_ctx) { @@ -2120,11 +2090,31 @@ static void dce110_setup_audio_dto( build_audio_output(context, pipe_ctx, &audio_output); +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { + /* disable audio DTBCLK DTO */ + dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( + dc->res_pool->dccg, 0); + + pipe_ctx->stream_res.audio->funcs->wall_dto_setup( + pipe_ctx->stream_res.audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &audio_output.pll_info); + } else + pipe_ctx->stream_res.audio->funcs->wall_dto_setup( + pipe_ctx->stream_res.audio, + pipe_ctx->stream->signal, + &audio_output.crtc_info, + &audio_output.pll_info); +#else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, &audio_output.crtc_info, &audio_output.pll_info); +#endif break; } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 8bbb499067f7..db7557a1c613 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -393,6 +393,7 @@ static void program_pixel_format( grph_format = 1; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: grph_depth = 3; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index d88a74559edd..27cbb5b42c7e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -2231,6 +2231,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { dce110_timing_generator_enable_advanced_request, .set_drr = dce110_timing_generator_set_drr, + .get_last_used_drr_vtotal = NULL, .set_static_screen_control = dce110_timing_generator_set_static_screen_control, .set_test_pattern = dce110_timing_generator_set_test_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index 29438c6050db..45bca0db5e5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -708,7 +708,8 @@ bool dce110_transform_v_construct( xfm_dce->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; xfm_dce->prescaler_on = true; xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index b57c466124e7..4af0c70098c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -1190,6 +1190,7 @@ static const struct timing_generator_funcs dce120_tg_funcs = { .tear_down_global_swap_lock = dce120_timing_generator_tear_down_global_swap_lock, .enable_advanced_request = dce120_timing_generator_enable_advanced_request, .set_drr = dce120_timing_generator_set_drr, + .get_last_used_drr_vtotal = NULL, .set_static_screen_control = dce120_timing_generator_set_static_screen_control, .set_test_pattern = dce120_timing_generator_set_test_pattern, .arm_vert_intr = dce120_arm_vert_intr, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index 397e7f94e1e8..b8fd43dc010b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -209,6 +209,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = { .tear_down_global_swap_lock = dce110_timing_generator_tear_down_global_swap_lock, .set_drr = dce110_timing_generator_set_drr, + .get_last_used_drr_vtotal = NULL, .set_static_screen_control = dce110_timing_generator_set_static_screen_control, .set_test_pattern = dce110_timing_generator_set_test_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 7f8456b9988b..91fdfcd8a14e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -257,7 +257,8 @@ static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) *fmt = PIXEL_FORMAT_FLOAT; - else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) + else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 || + input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616) *fmt = PIXEL_FORMAT_FIXED16; else *fmt = PIXEL_FORMAT_FIXED; @@ -368,7 +369,8 @@ void dpp1_cnv_setup ( select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - pixel_format = 22; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + pixel_format = 26; /* ARGB16161616_UNORM */ break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: pixel_format = 24; @@ -566,7 +568,8 @@ void dpp1_construct( dpp->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 9a1f40eb5c47..71b3a6949001 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -1497,8 +1497,6 @@ void dpp1_cnv_setup ( enum dc_color_space input_color_space, struct cnv_alpha_2bit_lut *alpha_2bit_lut); -void dpp1_full_bypass(struct dpp *dpp_base); - void dpp1_dppclk_control( struct dpp *dpp_base, bool dppclk_div, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index efa86d5c6847..673b93f4fea5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -496,10 +496,13 @@ static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *d int vtaps_c = scl_data->taps.v_taps_c; int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c); - enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0; - if (dpp->base.ctx->dc->debug.use_max_lb) - return mem_cfg; + if (dpp->base.ctx->dc->debug.use_max_lb) { + if (scl_data->format == PIXEL_FORMAT_420BPP8 + || scl_data->format == PIXEL_FORMAT_420BPP10) + return LB_MEMORY_CONFIG_3; + return LB_MEMORY_CONFIG_0; + } dpp->base.caps->dscl_calc_lb_num_partitions( scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); @@ -628,8 +631,10 @@ static void dpp1_dscl_set_manual_ratio_init( SCL_V_INIT_INT, init_int); if (REG(SCL_VERT_FILTER_INIT_BOT)) { - init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5; - init_int = dc_fixpt_floor(data->inits.v_bot); + struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert); + + init_frac = dc_fixpt_u0d19(bot) << 5; + init_int = dc_fixpt_floor(bot); REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, SCL_V_INIT_FRAC_BOT, init_frac, SCL_V_INIT_INT_BOT, init_int); @@ -642,41 +647,60 @@ static void dpp1_dscl_set_manual_ratio_init( SCL_V_INIT_INT_C, init_int); if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { - init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5; - init_int = dc_fixpt_floor(data->inits.v_c_bot); + struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c); + + init_frac = dc_fixpt_u0d19(bot) << 5; + init_int = dc_fixpt_floor(bot); REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, SCL_V_INIT_FRAC_BOT_C, init_frac, SCL_V_INIT_INT_BOT_C, init_int); } } - - -static void dpp1_dscl_set_recout( - struct dcn10_dpp *dpp, const struct rect *recout) +/** + * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area + * + * @dpp: DPP data struct + * @recount: Rectangle information + * + * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on + * the values specified in the recount parameter. + * + * Note: This function only have effect if AutoCal is disabled. + */ +static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp, + const struct rect *recout) { int visual_confirm_on = 0; if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) visual_confirm_on = 1; REG_SET_2(RECOUT_START, 0, - /* First pixel of RECOUT */ - RECOUT_START_X, recout->x, - /* First line of RECOUT */ - RECOUT_START_Y, recout->y); + /* First pixel of RECOUT in the active OTG area */ + RECOUT_START_X, recout->x, + /* First line of RECOUT in the active OTG area */ + RECOUT_START_Y, recout->y); REG_SET_2(RECOUT_SIZE, 0, - /* Number of RECOUT horizontal pixels */ - RECOUT_WIDTH, recout->width, - /* Number of RECOUT vertical lines */ - RECOUT_HEIGHT, recout->height + /* Number of RECOUT horizontal pixels */ + RECOUT_WIDTH, recout->width, + /* Number of RECOUT vertical lines */ + RECOUT_HEIGHT, recout->height - visual_confirm_on * 2 * (dpp->base.inst + 1)); } -/* Main function to program scaler and line buffer in manual scaling mode */ -void dpp1_dscl_set_scaler_manual_scale( - struct dpp *dpp_base, - const struct scaler_data *scl_data) +/** + * dpp1_dscl_set_scaler_manual_scale - Manually program scaler and line buffer + * + * @dpp_base: High level DPP struct + * @scl_data: scalaer_data info + * + * This is the primary function to program scaler and line buffer in manual + * scaling mode. To execute the required operations for manual scale, we need + * to disable AutoCal first. + */ +void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, + const struct scaler_data *scl_data) { enum lb_memory_config lb_config; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index 6f42d10dd772..f4f423d0b8c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -785,6 +785,7 @@ static bool hubbub1_dcc_support_pixel_format( *bytes_per_element = 4; return true; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: *bytes_per_element = 8; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h index 343a537172c7..8d7e92d5d3e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -139,6 +139,21 @@ struct dcn_hubbub_registers { uint32_t DCHVM_CLK_CTRL; uint32_t DCHVM_RIOMMU_CTRL0; uint32_t DCHVM_RIOMMU_STAT0; + uint32_t DCHUBBUB_DET0_CTRL; + uint32_t DCHUBBUB_DET1_CTRL; + uint32_t DCHUBBUB_DET2_CTRL; + uint32_t DCHUBBUB_DET3_CTRL; + uint32_t DCHUBBUB_COMPBUF_CTRL; + uint32_t COMPBUF_RESERVED_SPACE; + uint32_t DCHUBBUB_DEBUG_CTRL_0; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; }; /* set field name */ @@ -276,16 +291,42 @@ struct dcn_hubbub_registers { type RIOMMU_ACTIVE; \ type HOSTVM_PREFETCH_DONE +#define HUBBUB_RET_REG_FIELD_LIST(type) \ + type DET_DEPTH;\ + type DET0_SIZE;\ + type DET1_SIZE;\ + type DET2_SIZE;\ + type DET3_SIZE;\ + type DET0_SIZE_CURRENT;\ + type DET1_SIZE_CURRENT;\ + type DET2_SIZE_CURRENT;\ + type DET3_SIZE_CURRENT;\ + type COMPBUF_SIZE;\ + type COMPBUF_SIZE_CURRENT;\ + type COMPBUF_RESERVED_SPACE_64B;\ + type COMPBUF_RESERVED_SPACE_ZS;\ + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\ + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\ + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\ + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\ + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\ + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\ + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\ + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D + + struct dcn_hubbub_shift { DCN_HUBBUB_REG_FIELD_LIST(uint8_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); HUBBUB_HVM_REG_FIELD_LIST(uint8_t); + HUBBUB_RET_REG_FIELD_LIST(uint8_t); }; struct dcn_hubbub_mask { DCN_HUBBUB_REG_FIELD_LIST(uint32_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); HUBBUB_HVM_REG_FIELD_LIST(uint32_t); + HUBBUB_RET_REG_FIELD_LIST(uint32_t); }; struct dc; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 714c71a5fbde..04303fe9c659 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -245,6 +245,7 @@ void hubp1_program_pixel_format( if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { red_bar = 2; blue_bar = 3; @@ -277,8 +278,9 @@ void hubp1_program_pixel_format( SURFACE_PIXEL_FORMAT, 10); break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 22); + SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ @@ -1226,6 +1228,14 @@ void hubp1_cursor_set_position( /* TODO Handle surface pixel formats other than 4:4:4 */ } +/** + * hubp1_clk_cntl - Disable or enable clocks for DCHUBP + * + * @hubp: hubp struct reference. + * @enable: Set true for enabling gate clock. + * + * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk. + */ void hubp1_clk_cntl(struct hubp *hubp, bool enable) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); @@ -1257,6 +1267,11 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset) REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); } +/** + * hubp1_set_flip_int - Enable surface flip interrupt + * + * @hubp: hubp struct reference. + */ void hubp1_set_flip_int(struct hubp *hubp) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7c939c0a977b..c545eddabdcc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -54,6 +54,8 @@ #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" #include "dce/dmub_outbox.h" +#include "inc/dc_link_dp.h" +#include "inc/link_dpcd.h" #define DC_LOGGER_INIT(logger) @@ -72,6 +74,9 @@ #define GAMMA_HW_POINTS_NUM 256 +#define PGFSM_POWER_ON 0 +#define PGFSM_POWER_OFF 2 + void print_microsec(struct dc_context *dc_ctx, struct dc_log_buffer_ctx *log_ctx, uint32_t ref_cycle) @@ -536,13 +541,22 @@ void dcn10_disable_vga( REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1); } +/** + * dcn10_dpp_pg_control - DPP power gate control. + * + * @hws: dce_hwseq reference. + * @dpp_inst: DPP instance reference. + * @power_on: true if we want to enable power gate, false otherwise. + * + * Enable or disable power gate in the specific DPP instance. + */ void dcn10_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; + uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF; if (hws->ctx->dc->debug.disable_dpp_power_gate) return; @@ -588,13 +602,22 @@ void dcn10_dpp_pg_control( } } +/** + * dcn10_hubp_pg_control - HUBP power gate control. + * + * @hws: dce_hwseq reference. + * @hubp_inst: DPP instance reference. + * @power_on: true if we want to enable power gate, false otherwise. + * + * Enable or disable power gate in the specific HUBP instance. + */ void dcn10_hubp_pg_control( struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; + uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF; if (hws->ctx->dc->debug.disable_hubp_power_gate) return; @@ -1078,6 +1101,19 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) hws->funcs.verify_allow_pstate_change_high(dc); } +/** + * dcn10_plane_atomic_power_down - Power down plane components. + * + * @dc: dc struct reference. used for grab hwseq. + * @dpp: dpp struct reference. + * @hubp: hubp struct reference. + * + * Keep in mind that this operation requires a power gate configuration; + * however, requests for switch power gate are precisely controlled to avoid + * problems. For this reason, power gate request is usually disabled. This + * function first needs to enable the power gate request before disabling DPP + * and HUBP. Finally, it disables the power gate request again. + */ void dcn10_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp) @@ -1369,6 +1405,9 @@ void dcn10_init_hw(struct dc *dc) if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) continue; + /* DP 2.0 requires that LTTPR Caps be read first */ + dp_retrieve_lttpr_cap(dc->links[i]); + /* * If any of the displays are lit up turn them off. * The reason is that some MST hubs cannot be turned off @@ -2165,129 +2204,6 @@ void dcn10_enable_per_frame_crtc_position_reset( DC_SYNC_INFO("Multi-display sync is complete\n"); } -/*static void print_rq_dlg_ttu( - struct dc *dc, - struct pipe_ctx *pipe_ctx) -{ - DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger, - "\n============== DML TTU Output parameters [%d] ==============\n" - "qos_level_low_wm: %d, \n" - "qos_level_high_wm: %d, \n" - "min_ttu_vblank: %d, \n" - "qos_level_flip: %d, \n" - "refcyc_per_req_delivery_l: %d, \n" - "qos_level_fixed_l: %d, \n" - "qos_ramp_disable_l: %d, \n" - "refcyc_per_req_delivery_pre_l: %d, \n" - "refcyc_per_req_delivery_c: %d, \n" - "qos_level_fixed_c: %d, \n" - "qos_ramp_disable_c: %d, \n" - "refcyc_per_req_delivery_pre_c: %d\n" - "=============================================================\n", - pipe_ctx->pipe_idx, - pipe_ctx->ttu_regs.qos_level_low_wm, - pipe_ctx->ttu_regs.qos_level_high_wm, - pipe_ctx->ttu_regs.min_ttu_vblank, - pipe_ctx->ttu_regs.qos_level_flip, - pipe_ctx->ttu_regs.refcyc_per_req_delivery_l, - pipe_ctx->ttu_regs.qos_level_fixed_l, - pipe_ctx->ttu_regs.qos_ramp_disable_l, - pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l, - pipe_ctx->ttu_regs.refcyc_per_req_delivery_c, - pipe_ctx->ttu_regs.qos_level_fixed_c, - pipe_ctx->ttu_regs.qos_ramp_disable_c, - pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c - ); - - DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger, - "\n============== DML DLG Output parameters [%d] ==============\n" - "refcyc_h_blank_end: %d, \n" - "dlg_vblank_end: %d, \n" - "min_dst_y_next_start: %d, \n" - "refcyc_per_htotal: %d, \n" - "refcyc_x_after_scaler: %d, \n" - "dst_y_after_scaler: %d, \n" - "dst_y_prefetch: %d, \n" - "dst_y_per_vm_vblank: %d, \n" - "dst_y_per_row_vblank: %d, \n" - "ref_freq_to_pix_freq: %d, \n" - "vratio_prefetch: %d, \n" - "refcyc_per_pte_group_vblank_l: %d, \n" - "refcyc_per_meta_chunk_vblank_l: %d, \n" - "dst_y_per_pte_row_nom_l: %d, \n" - "refcyc_per_pte_group_nom_l: %d, \n", - pipe_ctx->pipe_idx, - pipe_ctx->dlg_regs.refcyc_h_blank_end, - pipe_ctx->dlg_regs.dlg_vblank_end, - pipe_ctx->dlg_regs.min_dst_y_next_start, - pipe_ctx->dlg_regs.refcyc_per_htotal, - pipe_ctx->dlg_regs.refcyc_x_after_scaler, - pipe_ctx->dlg_regs.dst_y_after_scaler, - pipe_ctx->dlg_regs.dst_y_prefetch, - pipe_ctx->dlg_regs.dst_y_per_vm_vblank, - pipe_ctx->dlg_regs.dst_y_per_row_vblank, - pipe_ctx->dlg_regs.ref_freq_to_pix_freq, - pipe_ctx->dlg_regs.vratio_prefetch, - pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l, - pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l, - pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l, - pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l - ); - - DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger, - "\ndst_y_per_meta_row_nom_l: %d, \n" - "refcyc_per_meta_chunk_nom_l: %d, \n" - "refcyc_per_line_delivery_pre_l: %d, \n" - "refcyc_per_line_delivery_l: %d, \n" - "vratio_prefetch_c: %d, \n" - "refcyc_per_pte_group_vblank_c: %d, \n" - "refcyc_per_meta_chunk_vblank_c: %d, \n" - "dst_y_per_pte_row_nom_c: %d, \n" - "refcyc_per_pte_group_nom_c: %d, \n" - "dst_y_per_meta_row_nom_c: %d, \n" - "refcyc_per_meta_chunk_nom_c: %d, \n" - "refcyc_per_line_delivery_pre_c: %d, \n" - "refcyc_per_line_delivery_c: %d \n" - "========================================================\n", - pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l, - pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l, - pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l, - pipe_ctx->dlg_regs.refcyc_per_line_delivery_l, - pipe_ctx->dlg_regs.vratio_prefetch_c, - pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c, - pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c, - pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c, - pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c, - pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c, - pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c, - pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c, - pipe_ctx->dlg_regs.refcyc_per_line_delivery_c - ); - - DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger, - "\n============== DML RQ Output parameters [%d] ==============\n" - "chunk_size: %d \n" - "min_chunk_size: %d \n" - "meta_chunk_size: %d \n" - "min_meta_chunk_size: %d \n" - "dpte_group_size: %d \n" - "mpte_group_size: %d \n" - "swath_height: %d \n" - "pte_row_height_linear: %d \n" - "========================================================\n", - pipe_ctx->pipe_idx, - pipe_ctx->rq_regs.rq_regs_l.chunk_size, - pipe_ctx->rq_regs.rq_regs_l.min_chunk_size, - pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size, - pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size, - pipe_ctx->rq_regs.rq_regs_l.dpte_group_size, - pipe_ctx->rq_regs.rq_regs_l.mpte_group_size, - pipe_ctx->rq_regs.rq_regs_l.swath_height, - pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear - ); -} -*/ - static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, struct vm_system_aperture_param *apt, struct dce_hwseq *hws) @@ -2395,43 +2311,6 @@ static void dcn10_enable_plane( pipe_ctx->stream_res.opp, true); -/* TODO: enable/disable in dm as per update type. - if (plane_state) { - DC_LOG_DC(dc->ctx->logger, - "Pipe:%d 0x%x: addr hi:0x%x, " - "addr low:0x%x, " - "src: %d, %d, %d," - " %d; dst: %d, %d, %d, %d;\n", - pipe_ctx->pipe_idx, - plane_state, - plane_state->address.grph.addr.high_part, - plane_state->address.grph.addr.low_part, - plane_state->src_rect.x, - plane_state->src_rect.y, - plane_state->src_rect.width, - plane_state->src_rect.height, - plane_state->dst_rect.x, - plane_state->dst_rect.y, - plane_state->dst_rect.width, - plane_state->dst_rect.height); - - DC_LOG_DC(dc->ctx->logger, - "Pipe %d: width, height, x, y format:%d\n" - "viewport:%d, %d, %d, %d\n" - "recout: %d, %d, %d, %d\n", - pipe_ctx->pipe_idx, - plane_state->format, - pipe_ctx->plane_res.scl_data.viewport.width, - pipe_ctx->plane_res.scl_data.viewport.height, - pipe_ctx->plane_res.scl_data.viewport.x, - pipe_ctx->plane_res.scl_data.viewport.y, - pipe_ctx->plane_res.scl_data.recout.width, - pipe_ctx->plane_res.scl_data.recout.height, - pipe_ctx->plane_res.scl_data.recout.x, - pipe_ctx->plane_res.scl_data.recout.y); - print_rq_dlg_ttu(dc, pipe_ctx); - } -*/ if (dc->config.gpu_vm_support) dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); @@ -2533,83 +2412,6 @@ void dcn10_program_output_csc(struct dc *dc, } } -void dcn10_get_surface_visual_confirm_color( - const struct pipe_ctx *pipe_ctx, - struct tg_color *color) -{ - uint32_t color_value = MAX_TG_COLOR_VALUE; - - switch (pipe_ctx->plane_res.scl_data.format) { - case PIXEL_FORMAT_ARGB8888: - /* set border color to red */ - color->color_r_cr = color_value; - break; - - case PIXEL_FORMAT_ARGB2101010: - /* set border color to blue */ - color->color_b_cb = color_value; - break; - case PIXEL_FORMAT_420BPP8: - /* set border color to green */ - color->color_g_y = color_value; - break; - case PIXEL_FORMAT_420BPP10: - /* set border color to yellow */ - color->color_g_y = color_value; - color->color_r_cr = color_value; - break; - case PIXEL_FORMAT_FP16: - /* set border color to white */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; - color->color_g_y = color_value; - break; - default: - break; - } -} - -void dcn10_get_hdr_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color) -{ - uint32_t color_value = MAX_TG_COLOR_VALUE; - - // Determine the overscan color based on the top-most (desktop) plane's context - struct pipe_ctx *top_pipe_ctx = pipe_ctx; - - while (top_pipe_ctx->top_pipe != NULL) - top_pipe_ctx = top_pipe_ctx->top_pipe; - - switch (top_pipe_ctx->plane_res.scl_data.format) { - case PIXEL_FORMAT_ARGB2101010: - if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { - /* HDR10, ARGB2101010 - set border color to red */ - color->color_r_cr = color_value; - } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { - /* FreeSync 2 ARGB2101010 - set border color to pink */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; - } - break; - case PIXEL_FORMAT_FP16: - if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { - /* HDR10, FP16 - set border color to blue */ - color->color_b_cb = color_value; - } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { - /* FreeSync 2 HDR - set border color to green */ - color->color_g_y = color_value; - } - break; - default: - /* SDR - set border color to Gray */ - color->color_r_cr = color_value/2; - color->color_b_cb = color_value/2; - color->color_g_y = color_value/2; - break; - } -} - static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) { struct dc_bias_and_scale bns_params = {0}; @@ -2628,9 +2430,26 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); } +void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) +{ + struct mpc *mpc = dc->res_pool->mpc; + + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) + get_hdr_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) + get_surface_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) + get_surface_tile_visual_confirm_color(pipe_ctx, color); + else + color_space_to_black_color( + dc, pipe_ctx->stream->output_color_space, color); + + if (mpc->funcs->set_bg_color) + mpc->funcs->set_bg_color(mpc, color, mpcc_id); +} + void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) { - struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = pipe_ctx->plane_res.hubp; struct mpcc_blnd_cfg blnd_cfg = {{0}}; bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; @@ -2639,18 +2458,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) struct mpc *mpc = dc->res_pool->mpc; struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); - if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { - hws->funcs.get_hdr_visual_confirm_color( - pipe_ctx, &blnd_cfg.black_color); - } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { - hws->funcs.get_surface_visual_confirm_color( - pipe_ctx, &blnd_cfg.black_color); - } else { - color_space_to_black_color( - dc, pipe_ctx->stream->output_color_space, - &blnd_cfg.black_color); - } - if (per_pixel_alpha) blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; else @@ -2685,6 +2492,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) /* If there is no full update, don't need to touch MPC tree*/ if (!pipe_ctx->plane_state->update_flags.bits.full_update) { mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); return; } @@ -2706,6 +2514,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) NULL, hubp->inst, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); ASSERT(new_mpcc != NULL); @@ -2719,7 +2528,7 @@ static void update_scaler(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; - pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; /* scaler configuration */ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); @@ -2956,6 +2765,25 @@ void dcn10_program_pipe( { struct dce_hwseq *hws = dc->hwseq; + if (pipe_ctx->top_pipe == NULL) { + bool blank = !is_pipe_tree_visible(pipe_ctx); + + pipe_ctx->stream_res.tg->funcs->program_global_sync( + pipe_ctx->stream_res.tg, + pipe_ctx->pipe_dlg_param.vready_offset, + pipe_ctx->pipe_dlg_param.vstartup_start, + pipe_ctx->pipe_dlg_param.vupdate_offset, + pipe_ctx->pipe_dlg_param.vupdate_width); + + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); + + if (hws->funcs.setup_vupdate_interrupt) + hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); + + hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); + } + if (pipe_ctx->plane_state->update_flags.bits.full_update) dcn10_enable_plane(dc, pipe_ctx, context); @@ -2978,63 +2806,6 @@ void dcn10_program_pipe( hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); } -static void dcn10_program_all_pipe_in_tree( - struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_state *context) -{ - struct dce_hwseq *hws = dc->hwseq; - - if (pipe_ctx->top_pipe == NULL) { - bool blank = !is_pipe_tree_visible(pipe_ctx); - - pipe_ctx->stream_res.tg->funcs->program_global_sync( - pipe_ctx->stream_res.tg, - pipe_ctx->pipe_dlg_param.vready_offset, - pipe_ctx->pipe_dlg_param.vstartup_start, - pipe_ctx->pipe_dlg_param.vupdate_offset, - pipe_ctx->pipe_dlg_param.vupdate_width); - - pipe_ctx->stream_res.tg->funcs->set_vtg_params( - pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); - - if (hws->funcs.setup_vupdate_interrupt) - hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); - - hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); - } - - if (pipe_ctx->plane_state != NULL) - hws->funcs.program_pipe(dc, pipe_ctx, context); - - if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) - dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); -} - -static struct pipe_ctx *dcn10_find_top_pipe_for_stream( - struct dc *dc, - struct dc_state *context, - const struct dc_stream_state *stream) -{ - int i; - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[i]; - - if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) - continue; - - if (pipe_ctx->stream != stream) - continue; - - if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) - return pipe_ctx; - } - return NULL; -} - void dcn10_wait_for_pending_cleared(struct dc *dc, struct dc_state *context) { @@ -3067,91 +2838,6 @@ void dcn10_wait_for_pending_cleared(struct dc *dc, } } -void dcn10_apply_ctx_for_surface( - struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, - struct dc_state *context) -{ - struct dce_hwseq *hws = dc->hwseq; - int i; - struct timing_generator *tg; - uint32_t underflow_check_delay_us; - bool interdependent_update = false; - struct pipe_ctx *top_pipe_to_program = - dcn10_find_top_pipe_for_stream(dc, context, stream); - DC_LOGGER_INIT(dc->ctx->logger); - - // Clear pipe_ctx flag - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - pipe_ctx->update_flags.raw = 0; - } - - if (!top_pipe_to_program) - return; - - tg = top_pipe_to_program->stream_res.tg; - - interdependent_update = top_pipe_to_program->plane_state && - top_pipe_to_program->plane_state->update_flags.bits.full_update; - - underflow_check_delay_us = dc->debug.underflow_assert_delay_us; - - if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur) - ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program)); - - if (underflow_check_delay_us != 0xFFFFFFFF) - udelay(underflow_check_delay_us); - - if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur) - ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program)); - - if (num_planes == 0) { - /* OTG blank before remove all front end */ - hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true); - } - - /* Disconnect unused mpcc */ - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[i]; - - if ((!pipe_ctx->plane_state || - pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && - old_pipe_ctx->plane_state && - old_pipe_ctx->stream_res.tg == tg) { - - hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx); - pipe_ctx->update_flags.bits.disable = 1; - - DC_LOG_DC("Reset mpcc for pipe %d\n", - old_pipe_ctx->pipe_idx); - } - } - - if (num_planes > 0) - dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context); - - /* Program secondary blending tree and writeback pipes */ - if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree)) - hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context); - if (interdependent_update) - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - /* Skip inactive pipes and ones already updated */ - if (!pipe_ctx->stream || pipe_ctx->stream == stream || - !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) - continue; - - pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( - pipe_ctx->plane_res.hubp, - &pipe_ctx->dlg_regs, - &pipe_ctx->ttu_regs); - } -} - void dcn10_post_unlock_program_front_end( struct dc *dc, struct dc_state *context) @@ -3559,10 +3245,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) * about the actual size being incorrect, that's a limitation of * the hardware. */ - x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width / - pipe_ctx->plane_state->dst_rect.width; - y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height / - pipe_ctx->plane_state->dst_rect.height; + if (param.rotation == ROTATION_ANGLE_90 || param.rotation == ROTATION_ANGLE_270) { + x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height / + pipe_ctx->plane_state->dst_rect.width; + y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width / + pipe_ctx->plane_state->dst_rect.height; + } else { + x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width / + pipe_ctx->plane_state->dst_rect.width; + y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height / + pipe_ctx->plane_state->dst_rect.height; + } /** * If the cursor's source viewport is clipped then we need to diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 37bec421fde8..9ae07c77fdc0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -80,11 +80,6 @@ void dcn10_lock_all_pipes( struct dc *dc, struct dc_state *context, bool lock); -void dcn10_apply_ctx_for_surface( - struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, - struct dc_state *context); void dcn10_post_unlock_program_front_end( struct dc *dc, struct dc_state *context); @@ -194,12 +189,6 @@ void dcn10_bios_golden_init(struct dc *dc); void dcn10_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp); -void dcn10_get_surface_visual_confirm_color( - const struct pipe_ctx *pipe_ctx, - struct tg_color *color); -void dcn10_get_hdr_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color); bool dcn10_disconnect_pipes( struct dc *dc, struct dc_state *context); @@ -211,4 +200,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc); void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits); +void dcn10_update_visual_confirm_color( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct tg_color *color, + int mpcc_id); + #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c index d532c78ee764..34001a30d449 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c @@ -26,13 +26,15 @@ #include "hw_sequencer_private.h" #include "dce110/dce110_hw_sequencer.h" #include "dcn10_hw_sequencer.h" +#include "dcn20/dcn20_hwseq.h" static const struct hw_sequencer_funcs dcn10_funcs = { .program_gamut_remap = dcn10_program_gamut_remap, .init_hw = dcn10_init_hw, .power_down_on_boot = dcn10_power_down_on_boot, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, - .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, .post_unlock_program_front_end = dcn10_post_unlock_program_front_end, .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, .update_plane_addr = dcn10_update_plane_addr, @@ -80,6 +82,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_abm_immediate_disable = dce110_set_abm_immediate_disable, .set_pipe = dce110_set_pipe, .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .update_visual_confirm_color = dcn10_update_visual_confirm_color, }; static const struct hwseq_private_funcs dcn10_private_funcs = { @@ -109,8 +112,6 @@ static const struct hwseq_private_funcs dcn10_private_funcs = { .dpp_pg_control = dcn10_dpp_pg_control, .hubp_pg_control = dcn10_hubp_pg_control, .dsc_pg_control = NULL, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h index 3e1a582e4b88..d8b22618b79e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h @@ -160,6 +160,12 @@ struct dcn10_link_enc_registers { uint32_t PHYA_LINK_CNTL2; uint32_t PHYB_LINK_CNTL2; uint32_t PHYC_LINK_CNTL2; + uint32_t DIO_LINKA_CNTL; + uint32_t DIO_LINKB_CNTL; + uint32_t DIO_LINKC_CNTL; + uint32_t DIO_LINKD_CNTL; + uint32_t DIO_LINKE_CNTL; + uint32_t DIO_LINKF_CNTL; }; #define LE_SF(reg_name, field_name, post_fix)\ @@ -460,16 +466,23 @@ struct dcn10_link_enc_registers { type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\ type RDPCS_TX_CLK_EN +#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \ + type ENC_TYPE_SEL;\ + type HPO_DP_ENC_SEL;\ + type HPO_HDMI_ENC_SEL + struct dcn10_link_enc_shift { DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); + DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t); }; struct dcn10_link_enc_mask { DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); + DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t); }; struct dcn10_link_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index b096011acb49..11019c2c62cc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -45,6 +45,8 @@ void mpc1_set_bg_color(struct mpc *mpc, struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); uint32_t bg_r_cr, bg_g_y, bg_b_cb; + bottommost_mpcc->blnd_cfg.black_color = *bg_color; + /* find bottommost mpcc. */ while (bottommost_mpcc->mpcc_bot) { bottommost_mpcc = bottommost_mpcc->mpcc_bot; @@ -81,7 +83,6 @@ static void mpc1_update_blending( MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); - mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); mpcc->blnd_cfg = *blnd_cfg; } @@ -495,6 +496,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = { .set_output_csc = NULL, .set_output_gamma = NULL, .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .set_bg_color = mpc1_set_bg_color, }; void dcn10_mpc_construct(struct dcn10_mpc *mpc10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index 677663cc7bff..3696faf12d86 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -968,6 +968,17 @@ void optc1_set_drr( } } +void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_SET(OTG_V_TOTAL_MAX, 0, + OTG_V_TOTAL_MAX, vtotal_max); + + REG_SET(OTG_V_TOTAL_MIN, 0, + OTG_V_TOTAL_MIN, vtotal_min); +} + static void optc1_set_test_pattern( struct timing_generator *optc, /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' @@ -1543,6 +1554,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .unlock = optc1_unlock, .enable_optc_clock = optc1_enable_optc_clock, .set_drr = optc1_set_drr, + .get_last_used_drr_vtotal = NULL, .set_static_screen_control = optc1_set_static_screen_control, .set_test_pattern = optc1_set_test_pattern, .program_stereo = optc1_program_stereo, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index cabfe83fd634..29d6fbe0093a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -171,6 +171,7 @@ struct dcn_optc_registers { uint32_t OPTC_DATA_FORMAT_CONTROL; uint32_t OPTC_BYTES_PER_PIXEL; uint32_t OPTC_WIDTH_CONTROL; + uint32_t OTG_DRR_CONTROL; uint32_t OTG_BLANK_DATA_COLOR; uint32_t OTG_BLANK_DATA_COLOR_EXT; uint32_t OTG_DRR_TRIGGER_WINDOW; @@ -517,7 +518,8 @@ struct dcn_optc_registers { type OTG_CRC_DSC_MODE;\ type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ - type OTG_CRC_DATA_FORMAT; + type OTG_CRC_DATA_FORMAT;\ + type OTG_V_TOTAL_LAST_USED_BY_DRR; struct dcn_optc_shift { @@ -666,6 +668,8 @@ void optc1_set_drr( struct timing_generator *optc, const struct drr_params *params); +void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); + void optc1_set_static_screen_control( struct timing_generator *optc, uint32_t event_triggers, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index f962b905e79e..7daadb6a5233 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1266,8 +1266,6 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) { - enum dc_status result = DC_OK; - enum surface_pixel_format surf_pix_format = plane_state->format; unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); @@ -1279,7 +1277,7 @@ static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *pla swizzle = DC_SW_64KB_S; plane_state->tiling_info.gfx9.swizzle = swizzle; - return result; + return DC_OK; } struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index 76b334644f9e..0d86df97878c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -52,6 +52,7 @@ SRI(AFMT_60958_1, DIG, id), \ SRI(AFMT_60958_2, DIG, id), \ SRI(DIG_FE_CNTL, DIG, id), \ + SRI(DIG_FIFO_STATUS, DIG, id), \ SRI(HDMI_CONTROL, DIG, id), \ SRI(HDMI_DB_CONTROL, DIG, id), \ SRI(HDMI_GC, DIG, id), \ @@ -124,6 +125,7 @@ struct dcn10_stream_enc_registers { uint32_t AFMT_60958_2; uint32_t DIG_FE_CNTL; uint32_t DIG_FE_CNTL2; + uint32_t DIG_FIFO_STATUS; uint32_t DP_MSE_RATE_CNTL; uint32_t DP_MSE_RATE_UPDATE; uint32_t DP_PIXEL_FORMAT; @@ -266,6 +268,17 @@ struct dcn10_stream_enc_registers { SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ @@ -488,6 +501,17 @@ struct dcn10_stream_enc_registers { type DP_VID_N_MUL;\ type DP_VID_M_DOUBLE_VALUE_EN;\ type DIG_SOURCE_SELECT;\ + type DIG_FIFO_LEVEL_ERROR;\ + type DIG_FIFO_USE_OVERWRITE_LEVEL;\ + type DIG_FIFO_OVERWRITE_LEVEL;\ + type DIG_FIFO_ERROR_ACK;\ + type DIG_FIFO_CAL_AVERAGE_LEVEL;\ + type DIG_FIFO_MAXIMUM_LEVEL;\ + type DIG_FIFO_MINIMUM_LEVEL;\ + type DIG_FIFO_READ_CLOCK_SRC;\ + type DIG_FIFO_CALIBRATED;\ + type DIG_FIFO_FORCE_RECAL_AVERAGE;\ + type DIG_FIFO_FORCE_RECOMP_MINMAX;\ type DIG_CLOCK_PATTERN #define SE_REG_FIELD_LIST_DCN2_0(type) \ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c index 8774406120fc..5999b2da3a01 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c @@ -96,6 +96,39 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, return; } +void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, + bool en) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, + DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); +} + +void dccg2_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 0, + OTG_DROP_PIXEL[otg_inst], 0); + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 1); +} + +void dccg2_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 0, + OTG_DROP_PIXEL[otg_inst], 0); + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_DROP_PIXEL[otg_inst], 1); +} + void dccg2_init(struct dccg *dccg) { } @@ -103,6 +136,9 @@ void dccg2_init(struct dccg *dccg) static const struct dccg_funcs dccg2_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index d407f33308b9..ede65100a050 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -34,12 +34,19 @@ DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ - SR(REFCLK_CNTL) + SR(REFCLK_CNTL),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SR(DISPCLK_FREQ_CHANGE_CNTL) #define DCCG_REG_LIST_DCN2() \ DCCG_COMMON_REG_LIST_DCN_BASE(),\ DCCG_SRII(DTO_PARAM, DPPCLK, 4),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 5) + DCCG_SRII(DTO_PARAM, DPPCLK, 5),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) #define DCCG_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -47,6 +54,9 @@ #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix +#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ + .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix + #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ @@ -59,14 +69,49 @@ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ - DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) + DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) + + + #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh) + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh) + +#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \ + DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh) + #define DCCG_REG_FIELD_LIST(type) \ type DPPCLK0_DTO_PHASE;\ @@ -74,7 +119,18 @@ type DPPCLK_DTO_ENABLE[6];\ type DPPCLK_DTO_DB_EN[6];\ type REFCLK_CLOCK_EN;\ - type REFCLK_SRC_SEL; + type REFCLK_SRC_SEL;\ + type DISPCLK_STEP_DELAY;\ + type DISPCLK_STEP_SIZE;\ + type DISPCLK_FREQ_RAMP_DONE;\ + type DISPCLK_MAX_ERRDET_CYCLES;\ + type DCCG_FIFO_ERRDET_RESET;\ + type DCCG_FIFO_ERRDET_STATE;\ + type DCCG_FIFO_ERRDET_OVR_EN;\ + type DISPCLK_CHG_FWD_CORR_DISABLE;\ + type DISPCLK_FREQ_CHANGE_CNTL;\ + type OTG_ADD_PIXEL[MAX_PIPES];\ + type OTG_DROP_PIXEL[MAX_PIPES]; #define DCCG3_REG_FIELD_LIST(type) \ type PHYASYMCLK_FORCE_EN;\ @@ -84,24 +140,71 @@ type PHYCSYMCLK_FORCE_EN;\ type PHYCSYMCLK_FORCE_SRC_SEL; +#define DCCG31_REG_FIELD_LIST(type) \ + type PHYDSYMCLK_FORCE_EN;\ + type PHYDSYMCLK_FORCE_SRC_SEL;\ + type PHYESYMCLK_FORCE_EN;\ + type PHYESYMCLK_FORCE_SRC_SEL;\ + type DPSTREAMCLK_PIPE0_EN;\ + type DPSTREAMCLK_PIPE1_EN;\ + type DPSTREAMCLK_PIPE2_EN;\ + type DPSTREAMCLK_PIPE3_EN;\ + type HDMISTREAMCLK0_SRC_SEL;\ + type HDMISTREAMCLK0_DTO_FORCE_DIS;\ + type SYMCLK32_SE0_SRC_SEL;\ + type SYMCLK32_SE1_SRC_SEL;\ + type SYMCLK32_SE2_SRC_SEL;\ + type SYMCLK32_SE3_SRC_SEL;\ + type SYMCLK32_SE0_EN;\ + type SYMCLK32_SE1_EN;\ + type SYMCLK32_SE2_EN;\ + type SYMCLK32_SE3_EN;\ + type SYMCLK32_LE0_SRC_SEL;\ + type SYMCLK32_LE1_SRC_SEL;\ + type SYMCLK32_LE0_EN;\ + type SYMCLK32_LE1_EN;\ + type DTBCLK_DTO_ENABLE[MAX_PIPES];\ + type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ + type PIPE_DTO_SRC_SEL[MAX_PIPES];\ + type DTBCLK_DTO_DIV[MAX_PIPES];\ + type DCCG_AUDIO_DTO_SEL;\ + type DCCG_AUDIO_DTO0_SOURCE_SEL;\ + type DENTIST_DISPCLK_CHG_MODE; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) + DCCG31_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { DCCG_REG_FIELD_LIST(uint32_t) DCCG3_REG_FIELD_LIST(uint32_t) + DCCG31_REG_FIELD_LIST(uint32_t) }; struct dccg_registers { uint32_t DPPCLK_DTO_CTRL; uint32_t DPPCLK_DTO_PARAM[6]; uint32_t REFCLK_CNTL; + uint32_t DISPCLK_FREQ_CHANGE_CNTL; + uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; uint32_t HDMICHARCLK_CLOCK_CNTL[6]; uint32_t PHYASYMCLK_CLOCK_CNTL; uint32_t PHYBSYMCLK_CLOCK_CNTL; uint32_t PHYCSYMCLK_CLOCK_CNTL; + uint32_t PHYDSYMCLK_CLOCK_CNTL; + uint32_t PHYESYMCLK_CLOCK_CNTL; + uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; + uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; + uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; + uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; + uint32_t DCCG_AUDIO_DTO_SOURCE; + uint32_t DPSTREAMCLK_CNTL; + uint32_t HDMISTREAMCLK_CNTL; + uint32_t SYMCLK32_SE_CNTL; + uint32_t SYMCLK32_LE_CNTL; + uint32_t DENTIST_DISPCLK_CNTL; }; struct dcn_dccg { @@ -117,6 +220,14 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz); +void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, + bool en); +void dccg2_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst); +void dccg2_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst); + + void dccg2_init(struct dccg *dccg); struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c index 4af96cc5d9d6..a9e420c7d75a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c @@ -166,7 +166,8 @@ static void dpp2_cnv_setup ( select = DCN2_ICSC_SELECT_ICSC_A; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - pixel_format = 22; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + pixel_format = 26; /* ARGB16161616_UNORM */ break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: pixel_format = 24; @@ -431,7 +432,8 @@ bool dpp2_construct( dpp->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c index 8dc3d1f73984..2feb051a2002 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c @@ -482,7 +482,7 @@ bool dpp20_program_blnd_lut( next_mode = LUT_RAM_A; dpp20_power_on_blnd_lut(dpp_base, true); - dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); + dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) dpp20_program_blnd_luta_settings(dpp_base, params); @@ -893,7 +893,7 @@ bool dpp20_program_shaper( else next_mode = LUT_RAM_A; - dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); + dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) dpp20_program_shaper_luta_settings(dpp_base, params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c index 6d03d98fca22..91a9305d42e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c @@ -158,6 +158,7 @@ bool hubbub2_dcc_support_pixel_format( *bytes_per_element = 4; return true; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: *bytes_per_element = 8; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h index c478213ba7ad..10af257d90ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h @@ -83,6 +83,13 @@ struct dcn20_hubbub { int num_vmid; struct dcn20_vmid vmid[16]; unsigned int detile_buf_size; + unsigned int crb_size_segs; + unsigned int compbuf_size_segments; + unsigned int pixel_chunk_size; + unsigned int det0_size; + unsigned int det1_size; + unsigned int det2_size; + unsigned int det3_size; }; void hubbub2_construct(struct dcn20_hubbub *hubbub, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index a1318c31bcfa..7e54058715aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -431,6 +431,7 @@ void hubp2_program_pixel_format( if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { red_bar = 2; blue_bar = 3; @@ -463,8 +464,9 @@ void hubp2_program_pixel_format( SURFACE_PIXEL_FORMAT, 10); break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 22); + SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index f501c02c244b..eea2254b15e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -216,16 +216,22 @@ type ROW_TTU_MODE; \ type NUM_PKRS +#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\ + type HUBP_UNBOUNDED_REQ_MODE;\ + type CURSOR_REQ_MODE;\ + type HUBP_SOFT_RESET + struct dcn_hubp2_registers { DCN30_HUBP_REG_COMMON_VARIABLE_LIST; }; struct dcn_hubp2_shift { - DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); + DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); }; struct dcn_hubp2_mask { - DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); + DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); }; struct dcn20_hubp { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 6a10daec15cc..5c2853654cca 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -51,6 +51,7 @@ #include "dccg.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" +#include "hw_sequencer.h" #define DC_LOGGER_INIT(logger) @@ -243,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws) REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); /* This value is dependent on the hardware pipeline delay so set once per SOC */ - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); } void dcn20_disable_vga( @@ -1269,6 +1270,7 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx new_pipe->update_flags.bits.gamut_remap = 1; new_pipe->update_flags.bits.scaler = 1; new_pipe->update_flags.bits.viewport = 1; + new_pipe->update_flags.bits.det_size = 1; if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { new_pipe->update_flags.bits.odm = 1; new_pipe->update_flags.bits.global_sync = 1; @@ -1303,6 +1305,9 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx new_pipe->update_flags.bits.global_sync = 1; } + if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) + new_pipe->update_flags.bits.det_size = 1; + /* * Detect opp / tg change, only set on change, not on enable * Assume mpcc inst = pipe index, if not this code needs to be updated @@ -1418,6 +1423,9 @@ static void dcn20_update_dchubp_dpp( &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); + + if (hubp->funcs->set_unbounded_requesting) + hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); } if (pipe_ctx->update_flags.bits.hubp_interdependent) hubp->funcs->hubp_setup_interdependent( @@ -1473,7 +1481,7 @@ static void dcn20_update_dchubp_dpp( plane_state->update_flags.bits.per_pixel_alpha_change || pipe_ctx->stream->update_flags.bits.scaling) { pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; - ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); + ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); /* scaler configuration */ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); @@ -1597,6 +1605,10 @@ static void dcn20_program_pipe( dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); } + if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) + dc->res_pool->hubbub->funcs->program_det_size( + dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); + if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) dcn20_update_dchubp_dpp(dc, pipe_ctx, context); @@ -1687,6 +1699,10 @@ void dcn20_program_front_end_for_ctx( for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { + struct hubbub *hubbub = dc->res_pool->hubbub; + + if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) + hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); } @@ -1700,7 +1716,11 @@ void dcn20_program_front_end_for_ctx( if (pipe->plane_state && !pipe->top_pipe) { while (pipe) { - dcn20_program_pipe(dc, pipe, context); + if (hws->funcs.program_pipe) + hws->funcs.program_pipe(dc, pipe, context); + else + dcn20_program_pipe(dc, pipe, context); + pipe = pipe->bottom_pipe; } /* Program secondary blending tree and writeback pipes */ @@ -1800,6 +1820,9 @@ void dcn20_prepare_bandwidth( &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, false); + /* decrease compbuf size */ + if (hubbub->funcs->program_compbuf_size) + hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false); } void dcn20_optimize_bandwidth( @@ -1818,6 +1841,9 @@ void dcn20_optimize_bandwidth( dc->clk_mgr, context, true); + /* increase compbuf size */ + if (hubbub->funcs->program_compbuf_size) + hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); } bool dcn20_update_bandwidth( @@ -2241,31 +2267,26 @@ void dcn20_reset_hw_ctx_wrap( } } -void dcn20_get_mpctree_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color) +void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) { - const struct tg_color pipe_colors[6] = { - {MAX_TG_COLOR_VALUE, 0, 0}, // red - {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange - {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow - {0, MAX_TG_COLOR_VALUE, 0}, // green - {0, 0, MAX_TG_COLOR_VALUE}, // blue - {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple - }; + struct mpc *mpc = dc->res_pool->mpc; - struct pipe_ctx *top_pipe = pipe_ctx; + // input to MPCC is always RGB, by default leave black_color at 0 + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) + get_hdr_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) + get_surface_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) + get_mpctree_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) + get_surface_tile_visual_confirm_color(pipe_ctx, color); - while (top_pipe->top_pipe) { - top_pipe = top_pipe->top_pipe; - } - - *color = pipe_colors[top_pipe->pipe_idx]; + if (mpc->funcs->set_bg_color) + mpc->funcs->set_bg_color(mpc, color, mpcc_id); } void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) { - struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = pipe_ctx->plane_res.hubp; struct mpcc_blnd_cfg blnd_cfg = { {0} }; bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; @@ -2274,15 +2295,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) struct mpc *mpc = dc->res_pool->mpc; struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); - // input to MPCC is always RGB, by default leave black_color at 0 - if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { - hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); - } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { - hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); - } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { - dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); - } - if (per_pixel_alpha) blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; else @@ -2320,6 +2332,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) if (!pipe_ctx->plane_state->update_flags.bits.full_update && !pipe_ctx->update_flags.bits.mpcc) { mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); return; } @@ -2341,6 +2354,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) NULL, hubp->inst, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); ASSERT(new_mpcc != NULL); hubp->opp_id = pipe_ctx->stream_res.opp->inst; @@ -2535,6 +2549,9 @@ void dcn20_fpga_init_hw(struct dc *dc) tg->funcs->tg_init(tg); } + + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); } #ifndef TRIM_FSFT bool dcn20_optimize_timing_for_fsft(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h index c69f766a40ce..6bba191cd33e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h @@ -146,5 +146,10 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc, const struct tg_color *solid_color, int width, int height, int offset); +void dcn20_update_visual_confirm_color(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct tg_color *color, + int mpcc_id); + #endif /* __DC_HWSS_DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c index b5bb613eed4d..5cfd4b0afea5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c @@ -96,6 +96,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = { #endif .set_disp_pattern_generator = dcn20_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .update_visual_confirm_color = dcn20_update_visual_confirm_color }; static const struct hwseq_private_funcs dcn20_private_funcs = { @@ -125,8 +126,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, .dsc_pg_control = dcn20_dsc_pg_control, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c index 6a99fdd55e8c..947eb0df3f12 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c @@ -67,7 +67,6 @@ void mpc2_update_blending( REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); - mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); mpcc->blnd_cfg = *blnd_cfg; } @@ -557,6 +556,7 @@ const struct mpc_funcs dcn20_mpc_funcs = { .set_output_gamma = mpc2_set_output_gamma, .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .set_bg_color = mpc1_set_bg_color, }; void dcn20_mpc_construct(struct dcn20_mpc *mpc20, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index 3139d90017ee..7fa9fc656b0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -520,6 +520,14 @@ bool optc2_configure_crc(struct timing_generator *optc, return optc1_configure_crc(optc, params); } + +void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); +} + static struct timing_generator_funcs dcn20_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -553,6 +561,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = { .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, .enable_optc_clock = optc1_enable_optc_clock, .set_drr = optc1_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, .set_static_screen_control = optc1_set_static_screen_control, .program_stereo = optc1_program_stereo, .is_stereo_left_eye = optc1_is_stereo_left_eye, @@ -591,4 +600,3 @@ void dcn20_timing_generator_init(struct optc *optc1) optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. optc1->min_v_sync_width = 1; } - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h index 3dee2ec2a1bb..be19a6885fbf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h @@ -42,7 +42,8 @@ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SR(DWB_SOURCE_SELECT),\ - SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) + SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \ + SRI(OTG_DRR_CONTROL, OTG, inst) #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -75,10 +76,14 @@ SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ - SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh) + SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) void dcn20_timing_generator_init(struct optc *optc); +void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, + uint32_t *refresh_rate); + bool optc2_enable_crtc(struct timing_generator *optc); void optc2_set_gsl(struct timing_generator *optc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 8357aa3c41d5..1b05a37b674d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1065,7 +1065,7 @@ static const struct dc_debug_options debug_defaults_drv = { .timing_trace = false, .clock_trace = true, .disable_pplib_clock_request = true, - .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, .vsr_support = true, @@ -2289,12 +2289,14 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; - pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y; - pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y; - pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width; - pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width; - pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height; - pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height; + pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; + pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; + pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; + pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; + pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; + pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; + pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width; + pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height; pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; @@ -2363,6 +2365,7 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.src.source_format = dm_420_10; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: pipes[pipe_cnt].pipe.src.source_format = dm_444_64; @@ -2786,7 +2789,6 @@ int dcn20_validate_apply_pipe_split_flags( split[i] = 0; } else if (get_num_odm_splits(pipe)) { /* ODM -> MPC transition */ - ASSERT(0); /* NOT expected yet */ if (pipe->prev_odm_pipe) { split[i] = 0; merge[i] = true; @@ -3067,6 +3069,16 @@ static void dcn20_calculate_wm( context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; } +static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) +{ + int i; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + } + return false; +} + void dcn20_calculate_dlg_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, @@ -3074,6 +3086,7 @@ void dcn20_calculate_dlg_params( int vlevel) { int i, pipe_idx; + int plane_count; /* Writeback MCIF_WB arbitration parameters */ dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); @@ -3089,6 +3102,20 @@ void dcn20_calculate_dlg_params( != dm_dram_clock_change_unsupported; context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; + context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ? + DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW; + + plane_count = 0; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (context->res_ctx.pipe_ctx[i].plane_state) + plane_count++; + } + + if (plane_count == 0) + context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW; + + context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); + if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; @@ -3099,6 +3126,9 @@ void dcn20_calculate_dlg_params( pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; + context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; + if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = @@ -3112,6 +3142,9 @@ void dcn20_calculate_dlg_params( context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; + context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes + - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; @@ -3667,7 +3700,7 @@ static bool dcn20_resource_construct( int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; - struct ddc_service_init_data ddc_init_data; + struct ddc_service_init_data ddc_init_data = {0}; struct _vcs_dpi_soc_bounding_box_st *loaded_bb = get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); struct _vcs_dpi_ip_params_st *loaded_ip = diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index 4075ae111530..e6307397e0d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -552,6 +552,17 @@ void enc2_stream_encoder_dp_set_stream_attribute( DP_SST_SDP_SPLITTING, enable_sdp_splitting); } +uint32_t enc2_get_fifo_cal_average_level( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t fifo_level; + + REG_GET(DIG_FIFO_STATUS, + DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level); + return fifo_level; +} + static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_set_odm_combine = enc2_dp_set_odm_combine, @@ -598,6 +609,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, + .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, }; void dcn20_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h index 9a881e639709..f3d1a0237bda 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h @@ -112,4 +112,7 @@ void enc2_set_dynamic_metadata(struct stream_encoder *enc, uint32_t hubp_requestor_id, enum dynamic_metadata_mode dmdata_mode); +uint32_t enc2_get_fifo_cal_average_level( + struct stream_encoder *enc); + #endif /* __DC_STREAM_ENCODER_DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c index 60cf3ff68cb0..33fc9aa8621b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c @@ -100,6 +100,9 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) static const struct dccg_funcs dccg21_funcs = { .update_dpp_dto = dccg21_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c index 8fccee5a3036..69cc192a7e71 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c @@ -218,7 +218,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT; cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp; cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16; - cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1; + cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_cntl->inst); cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data); diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c index 4f20a85ff396..54c11ba550ae 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c @@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = { .is_abm_supported = dcn21_is_abm_supported, .set_disp_pattern_generator = dcn20_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; static const struct hwseq_private_funcs dcn21_private_funcs = { @@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, .dsc_pg_control = dcn20_dsc_pg_control, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 8e3f1d0b4cc3..f3d98e3ba624 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -448,11 +448,11 @@ static const struct dccg_registers dccg_regs = { }; static const struct dccg_shift dccg_shift = { - DCCG_MASK_SH_LIST_DCN2(__SHIFT) + DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) }; static const struct dccg_mask dccg_mask = { - DCCG_MASK_SH_LIST_DCN2(_MASK) + DCCG_MASK_SH_LIST_DCN2_1(_MASK) }; #define opp_regs(id)\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c index b822a13e40ce..d445dfefc047 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c @@ -46,6 +46,9 @@ static const struct dccg_funcs dccg3_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h index 029dda13a464..35a613bb08bf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h @@ -38,10 +38,25 @@ #define DCCG_REG_LIST_DCN30() \ DCCG_REG_LIST_DCN2(),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\ SR(PHYASYMCLK_CLOCK_CNTL),\ SR(PHYBSYMCLK_CLOCK_CNTL),\ SR(PHYCSYMCLK_CLOCK_CNTL) +#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \ + DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh) + #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \ DCCG_MASK_SH_LIST_DCN2(mask_sh),\ DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ @@ -49,7 +64,7 @@ DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh) + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\ struct dccg *dccg3_create( struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index 72bee637c1e4..8487516819ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -823,6 +823,8 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, + + .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, }; void dcn30_dio_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h index 0b1755f1dea8..e2c264ecb20f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h @@ -85,7 +85,9 @@ SRI(DP_MSE_RATE_UPDATE, DP, id), \ SRI(DP_PIXEL_FORMAT, DP, id), \ SRI(DP_SEC_CNTL, DP, id), \ + SRI(DP_SEC_CNTL1, DP, id), \ SRI(DP_SEC_CNTL2, DP, id), \ + SRI(DP_SEC_CNTL5, DP, id), \ SRI(DP_SEC_CNTL6, DP, id), \ SRI(DP_STEER_FIFO, DP, id), \ SRI(DP_VID_M, DP, id), \ @@ -104,6 +106,7 @@ SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ SRI(DIG_FE_CNTL, DIG, id), \ + SRI(DIG_FIFO_STATUS, DIG, id), \ SRI(DIG_CLOCK_PATTERN, DIG, id) @@ -165,11 +168,24 @@ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\ SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index 434d3c46cad4..2140b75540cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -245,7 +245,8 @@ static void dpp3_cnv_setup ( select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - pixel_format = 22; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + pixel_format = 26; /* ARGB16161616_UNORM */ break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: pixel_format = 24; @@ -1442,7 +1443,8 @@ bool dpp3_construct( dpp->lb_pixel_depth_supported = LB_PIXEL_DEPTH_18BPP | LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP; + LB_PIXEL_DEPTH_30BPP | + LB_PIXEL_DEPTH_36BPP; dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index d53f8b39699b..c68e3a708a33 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -48,6 +48,8 @@ #include "dc_dmub_srv.h" #include "link_hwss.h" #include "dpcd_defs.h" +#include "inc/dc_link_dp.h" +#include "inc/link_dpcd.h" @@ -529,6 +531,8 @@ void dcn30_init_hw(struct dc *dc) for (i = 0; i < dc->link_count; i++) { if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) continue; + /* DP 2.0 states that LTTPR regs must be read first */ + dp_retrieve_lttpr_cap(dc->links[i]); /* if any of the displays are lit up turn them off */ status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, @@ -651,6 +655,9 @@ void dcn30_init_hw(struct dc *dc) if (dc->res_pool->hubbub->funcs->force_pstate_change_control) dc->res_pool->hubbub->funcs->force_pstate_change_control( dc->res_pool->hubbub, false, false); + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); + } void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) @@ -813,6 +820,15 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), denom) - 64LL; + /* In some cases the stutter period is really big (tiny modes) in these + * cases MALL cant be enabled, So skip these cases to avoid a ASSERT() + * + * We can check if stutter_period is more than 1/10th the frame time to + * consider if we can actually meet the range of hysteresis timer + */ + if (stutter_period > 100000/refresh_hz) + return false; + /* scale should be increased until it fits into 6 bits */ while (tmr_delay & ~0x3F) { tmr_scale++; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index bf7fa98b39eb..3a5b53dd2f6d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .set_pipe = dcn21_set_pipe, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; static const struct hwseq_private_funcs dcn30_private_funcs = { @@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, .dsc_pg_control = dcn20_dsc_pg_control, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c index 910c17fd4278..a82319f4d081 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c @@ -874,7 +874,7 @@ bool mpc3_program_shaper( else next_mode = LUT_RAM_A; - mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, rmu_idx); + mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx); if (next_mode == LUT_RAM_A) mpc3_program_shaper_luta_settings(mpc, params, rmu_idx); @@ -1431,7 +1431,7 @@ const struct mpc_funcs dcn30_mpc_funcs = { .release_rmu = mpcc3_release_rmu, .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, - + .set_bg_color = mpc1_set_bg_color, }; void dcn30_mpc_construct(struct dcn30_mpc *mpc30, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h index d1fd0b9aa0f9..b7dc78624963 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h @@ -585,6 +585,181 @@ type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ type MPC_RMU_SHAPER_MODE_CURRENT +#define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \ + MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ + SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ + SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ + SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ + SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ + /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ + SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ + SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ + /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\ + SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ + SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ + /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\ + SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ + SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ + SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ + SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ + SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ + /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\ + SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ + SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ + SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ + SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ + SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ + SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ + /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\ + SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ + SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ + SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\ + SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) + +#define MPC_REG_FIELD_LIST_DCN3_03(type) \ + MPC_REG_FIELD_LIST_DCN2_0(type) \ + type MPC_DWB0_MUX;\ + type MPC_DWB0_MUX_STATUS;\ + type MPC_OUT_RATE_CONTROL;\ + type MPC_OUT_RATE_CONTROL_DISABLE;\ + type MPC_OUT_FLOW_CONTROL_MODE;\ + type MPC_OUT_FLOW_CONTROL_COUNT; \ + type MPCC_GAMUT_REMAP_MODE; \ + type MPCC_GAMUT_REMAP_MODE_CURRENT;\ + type MPCC_GAMUT_REMAP_COEF_FORMAT; \ + type MPCC_GAMUT_REMAP_C11_A; \ + type MPCC_GAMUT_REMAP_C12_A; \ + type MPC_RMU0_MUX; \ + type MPC_RMU0_MUX_STATUS; \ + type MPC_RMU0_MEM_PWR_FORCE;\ + type MPC_RMU0_MEM_PWR_DIS;\ + type MPC_RMU0_MEM_LOW_PWR_MODE;\ + type MPC_RMU0_SHAPER_MEM_PWR_STATE;\ + type MPC_RMU0_3DLUT_MEM_PWR_STATE;\ + type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ + type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\ + type MPCC_OGAM_RAMA_OFFSET_B;\ + type MPCC_OGAM_RAMA_OFFSET_G;\ + type MPCC_OGAM_RAMA_OFFSET_R;\ + type MPCC_OGAM_SELECT; \ + type MPCC_OGAM_PWL_DISABLE; \ + type MPCC_OGAM_MODE_CURRENT; \ + type MPCC_OGAM_SELECT_CURRENT; \ + type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \ + type MPCC_OGAM_LUT_READ_COLOR_SEL; \ + type MPCC_OGAM_LUT_READ_DBG; \ + type MPCC_OGAM_LUT_HOST_SEL; \ + type MPCC_OGAM_LUT_CONFIG_MODE; \ + type MPCC_OGAM_LUT_STATUS; \ + type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\ + type MPCC_OGAM_MEM_LOW_PWR_MODE;\ + type MPCC_OGAM_MEM_PWR_STATE;\ + type MPC_RMU_3DLUT_MODE; \ + type MPC_RMU_3DLUT_SIZE; \ + type MPC_RMU_3DLUT_MODE_CURRENT; \ + type MPC_RMU_3DLUT_WRITE_EN_MASK;\ + type MPC_RMU_3DLUT_RAM_SEL;\ + type MPC_RMU_3DLUT_30BIT_EN;\ + type MPC_RMU_3DLUT_CONFIG_STATUS;\ + type MPC_RMU_3DLUT_READ_SEL;\ + type MPC_RMU_3DLUT_INDEX;\ + type MPC_RMU_3DLUT_DATA0;\ + type MPC_RMU_3DLUT_DATA1;\ + type MPC_RMU_3DLUT_DATA_30BIT;\ + type MPC_RMU_SHAPER_LUT_MODE;\ + type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\ + type MPC_RMU_SHAPER_OFFSET_R;\ + type MPC_RMU_SHAPER_OFFSET_G;\ + type MPC_RMU_SHAPER_OFFSET_B;\ + type MPC_RMU_SHAPER_SCALE_R;\ + type MPC_RMU_SHAPER_SCALE_G;\ + type MPC_RMU_SHAPER_SCALE_B;\ + type MPC_RMU_SHAPER_LUT_INDEX;\ + type MPC_RMU_SHAPER_LUT_DATA;\ + type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\ + type MPC_RMU_SHAPER_LUT_WRITE_SEL;\ + type MPC_RMU_SHAPER_CONFIG_STATUS;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ + type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ + type MPC_RMU_SHAPER_MODE_CURRENT struct dcn30_mpc_registers { MPC_REG_VARIABLE_LIST_DCN3_0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c index 8980c90b2277..f37e8254df21 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c @@ -97,7 +97,7 @@ void optc3_lock_doublebuffer_disable(struct timing_generator *optc) MASTER_UPDATE_LOCK_DB_END_Y, 0); REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0); - REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 1); + REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0); } void optc3_lock(struct timing_generator *optc) @@ -315,6 +315,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, .enable_optc_clock = optc1_enable_optc_clock, .set_drr = optc1_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, .set_static_screen_control = optc1_set_static_screen_control, .program_stereo = optc1_program_stereo, .is_stereo_left_eye = optc1_is_stereo_left_eye, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h index 379616831636..736e63bc80c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h @@ -87,7 +87,8 @@ SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ SR(GSL_SOURCE_SELECT),\ - SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) + SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\ + SRI(OTG_DRR_CONTROL, OTG, inst) #define OPTC_COMMON_REG_LIST_DCN3_0(inst) \ @@ -233,7 +234,8 @@ SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ - SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) #define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\ OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 5fcc2e64305d..596c97dce67e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = { .timing_trace = false, .clock_trace = true, .disable_pplib_clock_request = true, - .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, .vsr_support = true, @@ -1725,7 +1725,7 @@ static bool init_soc_bounding_box(struct dc *dc, DC_LOGGER_INIT(dc->ctx->logger); if (!is_soc_bounding_box_valid(dc)) { - DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); + DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); return false; } @@ -2539,7 +2539,7 @@ static bool dcn30_resource_construct( int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; - struct ddc_service_init_data ddc_init_data; + struct ddc_service_init_data ddc_init_data = {0}; uint32_t pipe_fuses = read_pipe_fuses(ctx); uint32_t num_pipes = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c index 420da414929c..97e9be87afd9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c @@ -45,6 +45,9 @@ static const struct dccg_funcs dccg301_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c index 70b053d9ba40..e85b695f2351 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c @@ -101,6 +101,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .get_dcc_en_bits = dcn10_get_dcc_en_bits, .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; static const struct hwseq_private_funcs dcn301_private_funcs = { @@ -131,8 +132,6 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, .dsc_pg_control = dcn20_dsc_pg_control, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index 472696f949ac..9776d1737818 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -1498,7 +1498,7 @@ static bool init_soc_bounding_box(struct dc *dc, DC_LOGGER_INIT(dc->ctx->logger); if (!is_soc_bounding_box_valid(dc)) { - DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); + DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c index e8580cccbebf..0a6d58dd8f6d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c @@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po 1, 1000); break; case 4: /* DPP4 */ - /* - * Do not power gate DPP4, should be left at HW default, power on permanently. - * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard - * reset. - * REG_UPDATE(DOMAIN9_PG_CONFIG, - * DOMAIN9_POWER_GATE, power_gate); - * - * REG_WAIT(DOMAIN9_PG_STATUS, - * DOMAIN9_PGFSM_PWR_STATUS, pwr_status, - * 1, 1000); - */ + REG_UPDATE(DOMAIN9_PG_CONFIG, + DOMAIN9_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN9_PG_STATUS, + DOMAIN9_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); @@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool 1, 1000); break; case 4: /* DCHUBP4 */ - /* - * Do not power gate DCHUB4, should be left at HW default, power on permanently. - * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard - * reset. - * REG_UPDATE(DOMAIN8_PG_CONFIG, - * DOMAIN8_POWER_GATE, power_gate); - * - * REG_WAIT(DOMAIN8_PG_STATUS, - * DOMAIN8_PGFSM_PWR_STATUS, pwr_status, - * 1, 1000); - */ + REG_UPDATE(DOMAIN8_PG_CONFIG, + DOMAIN8_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN8_PG_STATUS, + DOMAIN8_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c index a33f0365329b..16a75ba0ca82 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c @@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ .num_states = 1, - .sr_exit_time_us = 15.5, - .sr_enter_plus_exit_time_us = 20, + .sr_exit_time_us = 26.5, + .sr_enter_plus_exit_time_us = 31, .urgent_latency_us = 4.0, .urgent_latency_pixel_data_only_us = 4.0, .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, @@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = { .timing_trace = false, .clock_trace = true, .disable_pplib_clock_request = true, - .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, .vsr_support = true, @@ -1094,7 +1094,7 @@ static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) DC_LOGGER_INIT(dc->ctx->logger); if (!is_soc_bounding_box_valid(dc)) { - DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); + DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); return false; } @@ -1102,6 +1102,26 @@ static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) loaded_ip->max_num_dpp = pool->pipe_count; loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; dcn20_patch_bounding_box(dc, loaded_bb); + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { + struct bp_soc_bb_info bb_info = { 0 }; + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info( + dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { + if (bb_info.dram_clock_change_latency_100ns > 0) + dcn3_02_soc.dram_clock_change_latency_us = + bb_info.dram_clock_change_latency_100ns * 10; + + if (bb_info.dram_sr_enter_exit_latency_100ns > 0) + dcn3_02_soc.sr_enter_plus_exit_time_us = + bb_info.dram_sr_enter_exit_latency_100ns * 10; + + if (bb_info.dram_sr_exit_latency_100ns > 0) + dcn3_02_soc.sr_exit_time_us = + bb_info.dram_sr_exit_latency_100ns * 10; + } + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/Makefile b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile new file mode 100644 index 000000000000..6f7a1f2b49f0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (C) 2021 Advanced Micro Devices, Inc. All the rights reserved +# +# Authors: AMD +# +# Makefile for dcn303. + +DCN3_03 = dcn303_init.o dcn303_hwseq.o dcn303_resource.o + +ifdef CONFIG_X86 +CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o := -msse +endif + +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o := -mhard-float -maltivec +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -mhard-float +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -mpreferred-stack-boundary=4 +else +CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -msse2 +endif +endif + +AMD_DAL_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/dcn303/,$(DCN3_03)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_03) diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h new file mode 100644 index 000000000000..a79c54bbc899 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef __DCN303_DCCG_H__ +#define __DCN303_DCCG_H__ + +#include "dcn30/dcn30_dccg.h" + + +#define DCCG_REG_LIST_DCN3_03() \ + SR(DPPCLK_DTO_CTRL),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ + SR(REFCLK_CNTL) + +#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ + DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) + +#endif //__DCN303_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c new file mode 100644 index 000000000000..b48b732aa647 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#include "dcn303_hwseq.h" + +#include "dce/dce_hwseq.h" + +#include "reg_helper.h" +#include "dc.h" + +#define DC_LOGGER_INIT(logger) + +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + + +void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) +{ + /*DCN303 removes PG registers*/ +} + +void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) +{ + /*DCN303 removes PG registers*/ +} + +void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) +{ + /*DCN303 removes PG registers*/ +} + +void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) +{ + /*DCN303 removes PG registers*/ +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h new file mode 100644 index 000000000000..8b69a3b76c11 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef __DC_HWSS_DCN303_H__ +#define __DC_HWSS_DCN303_H__ + +#include "hw_sequencer_private.h" + +void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); +void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); +void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable); + +#endif /* __DC_HWSS_DCN303_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c new file mode 100644 index 000000000000..aa5dbbade2bd --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#include "dcn303_hwseq.h" +#include "dcn30/dcn30_init.h" +#include "dc.h" + +void dcn303_hw_sequencer_construct(struct dc *dc) +{ + dcn30_hw_sequencer_construct(dc); + + dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control; + dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control; + dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control; + dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h new file mode 100644 index 000000000000..66b1e3604f07 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef __DC_DCN303_INIT_H__ +#define __DC_DCN303_INIT_H__ + +struct dc; + +void dcn303_hw_sequencer_construct(struct dc *dc); + +#endif /* __DC_DCN303_INIT_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c new file mode 100644 index 000000000000..34b89464ae02 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c @@ -0,0 +1,1695 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#include "dcn303_init.h" +#include "dcn303_resource.h" +#include "dcn303_dccg.h" +#include "irq/dcn303/irq_service_dcn303.h" + +#include "dcn30/dcn30_dio_link_encoder.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn30/dcn30_dpp.h" +#include "dcn30/dcn30_dwb.h" +#include "dcn30/dcn30_hubbub.h" +#include "dcn30/dcn30_hubp.h" +#include "dcn30/dcn30_mmhubbub.h" +#include "dcn30/dcn30_mpc.h" +#include "dcn30/dcn30_opp.h" +#include "dcn30/dcn30_optc.h" +#include "dcn30/dcn30_resource.h" + +#include "dcn20/dcn20_dsc.h" +#include "dcn20/dcn20_resource.h" + +#include "dcn10/dcn10_resource.h" + +#include "dc_link_ddc.h" + +#include "dce/dce_abm.h" +#include "dce/dce_audio.h" +#include "dce/dce_aux.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_hwseq.h" +#include "dce/dce_i2c_hw.h" +#include "dce/dce_panel_cntl.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "clk_mgr.h" + +#include "hw_sequencer_private.h" +#include "reg_helper.h" +#include "resource.h" +#include "vm_helper.h" + +#include "sienna_cichlid_ip_offset.h" +#include "dcn/dcn_3_0_3_offset.h" +#include "dcn/dcn_3_0_3_sh_mask.h" +#include "dcn/dpcs_3_0_3_offset.h" +#include "dcn/dpcs_3_0_3_sh_mask.h" +#include "nbio/nbio_2_3_offset.h" + +#define DC_LOGGER_INIT(logger) + +struct _vcs_dpi_ip_params_st dcn3_03_ip = { + .use_min_dcfclk = 0, + .clamp_min_dcfclk = 0, + .odm_capable = 1, + .gpuvm_enable = 1, + .hostvm_enable = 0, + .gpuvm_max_page_table_levels = 4, + .hostvm_max_page_table_levels = 4, + .hostvm_cached_page_table_levels = 0, + .pte_group_size_bytes = 2048, + .num_dsc = 2, + .rob_buffer_size_kbytes = 184, + .det_buffer_size_kbytes = 184, + .dpte_buffer_size_in_pte_reqs_luma = 64, + .dpte_buffer_size_in_pte_reqs_chroma = 34, + .pde_proc_buffer_size_64k_reqs = 48, + .dpp_output_buffer_pixels = 2560, + .opp_output_buffer_lines = 1, + .pixel_chunk_size_kbytes = 8, + .pte_enable = 1, + .max_page_table_levels = 2, + .pte_chunk_size_kbytes = 2, // ? + .meta_chunk_size_kbytes = 2, + .writeback_chunk_size_kbytes = 8, + .line_buffer_size_bits = 789504, + .is_line_buffer_bpp_fixed = 0, // ? + .line_buffer_fixed_bpp = 0, // ? + .dcc_supported = true, + .writeback_interface_buffer_size_kbytes = 90, + .writeback_line_buffer_buffer_size = 0, + .max_line_buffer_lines = 12, + .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 + .writeback_chroma_buffer_size_kbytes = 8, + .writeback_chroma_line_buffer_width_pixels = 4, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .writeback_line_buffer_luma_buffer_size = 0, + .writeback_line_buffer_chroma_buffer_size = 14643, + .cursor_buffer_size = 8, + .cursor_chunk_size = 2, + .max_num_otg = 2, + .max_num_dpp = 2, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .hscl_mults = 4, + .vscl_mults = 4, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dispclk_ramp_margin_percent = 1, + .underscan_factor = 1.11, + .min_vblank_lines = 32, + .dppclk_delay_subtotal = 46, + .dynamic_metadata_vm_enabled = true, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_scl = 50, + .dppclk_delay_cnvc_formatter = 27, + .dppclk_delay_cnvc_cursor = 6, + .dispclk_delay_subtotal = 119, + .dcfclk_cstate_latency = 5.2, // SRExitTime + .max_inter_dcn_tile_repeaters = 8, + .max_num_hdmi_frl_outputs = 1, + .odm_combine_4to1_supported = false, + .xfc_supported = false, + .xfc_fill_bw_overhead_percent = 10.0, + .xfc_fill_constant_bytes = 0, + .gfx7_compat_tiling_supported = 0, + .number_of_cursors = 1, +}; + +struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { + .clock_limits = { + { + .state = 0, + .dispclk_mhz = 1217.0, + .dppclk_mhz = 1217.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 405.6, + }, + }, + + .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ + .num_states = 1, + .sr_exit_time_us = 26.5, + .sr_enter_plus_exit_time_us = 31, + .urgent_latency_us = 4.0, + .urgent_latency_pixel_data_only_us = 4.0, + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, + .urgent_latency_vm_data_only_us = 4.0, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, + .max_avg_sdp_bw_use_normal_percent = 60.0, + .max_avg_dram_bw_use_normal_percent = 40.0, + .writeback_latency_us = 12.0, + .max_request_size_bytes = 256, + .fabric_datapath_to_dcn_data_return_bytes = 64, + .dcn_downspread_percent = 0.5, + .downspread_percent = 0.38, + .dram_page_open_time_ns = 50.0, + .dram_rw_turnaround_time_ns = 17.5, + .dram_return_buffer_per_channel_bytes = 8192, + .round_trip_ping_latency_dcfclk_cycles = 156, + .urgent_out_of_order_return_per_channel_bytes = 4096, + .channel_interleave_bytes = 256, + .num_banks = 8, + .gpuvm_min_page_size_bytes = 4096, + .hostvm_min_page_size_bytes = 4096, + .dram_clock_change_latency_us = 404, + .dummy_pstate_latency_us = 5, + .writeback_dram_clock_change_latency_us = 23.0, + .return_bus_width_bytes = 64, + .dispclk_dppclk_vco_speed_mhz = 3650, + .xfc_bus_transport_time_us = 20, // ? + .xfc_xbuf_latency_tolerance_us = 4, // ? + .use_urgent_burst_bw = 1, // ? + .do_urgent_latency_adjustment = true, + .urgent_latency_adjustment_fabric_clock_component_us = 1.0, + .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, +}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, + .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 7680,/*upto 8K*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .disable_idle_power_optimizations = false, +}; + +static const struct dc_debug_options debug_defaults_diags = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = true, + .clock_trace = true, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_clock_gate = true, + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = true, + .disable_stutter = false, + .scl_reset_length10 = true, + .dwb_fi_phase = -1, // -1 = disable + .dmub_command_table = true, + .enable_tri_buf = true, + .disable_psr = true, +}; + +enum dcn303_clk_src_array_id { + DCN303_CLK_SRC_PLL0, + DCN303_CLK_SRC_PLL1, + DCN303_CLK_SRC_TOTAL +}; + +static const struct resource_caps res_cap_dcn303 = { + .num_timing_generator = 2, + .num_opp = 2, + .num_video_plane = 2, + .num_audio = 2, + .num_stream_encoder = 2, + .num_dwb = 1, + .num_ddc = 2, + .num_vmid = 16, + .num_mpc_3dlut = 1, + .num_dsc = 2, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .blends_with_above = true, + .blends_with_below = true, + .per_pixel_alpha = true, + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = false, + .ayuv = false, + }, + .max_upscale_factor = { + .argb8888 = 16000, + .nv12 = 16000, + .fp16 = 16000 + }, + .max_downscale_factor = { + .argb8888 = 600, + .nv12 = 600, + .fp16 = 600 + }, + 16, + 16 +}; + +/* NBIO */ +#define NBIO_BASE_INNER(seg) \ + NBIO_BASE__INST0_SEG ## seg + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name)\ + .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ + mm ## reg_name + +/* DCN */ +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name + +#define SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define SRI(reg_name, block, id)\ + .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name + +#define SRI2(reg_name, block, id)\ + .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name + +#define SRII(reg_name, block, id)\ + .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + mm ## block ## id ## _ ## reg_name + +#define DCCG_SRII(reg_name, block, id)\ + .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + mm ## block ## id ## _ ## reg_name + +#define VUPDATE_SRII(reg_name, block, id)\ + .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ + mm ## reg_name ## _ ## block ## id + +#define SRII_DWB(reg_name, temp_name, block, id)\ + .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ + mm ## block ## id ## _ ## temp_name + +#define SRII_MPC_RMU(reg_name, block, id)\ + .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + mm ## block ## id ## _ ## reg_name + +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN30(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN30(_MASK) +}; + +#define vmid_regs(id)\ + [id] = { DCN20_VMID_REG_LIST(id) } + +static const struct dcn_vmid_registers vmid_regs[] = { + vmid_regs(0), + vmid_regs(1), + vmid_regs(2), + vmid_regs(3), + vmid_regs(4), + vmid_regs(5), + vmid_regs(6), + vmid_regs(7), + vmid_regs(8), + vmid_regs(9), + vmid_regs(10), + vmid_regs(11), + vmid_regs(12), + vmid_regs(13), + vmid_regs(14), + vmid_regs(15) +}; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) +}; + +static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); + + if (!hubbub3) + return NULL; + + hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); + + for (i = 0; i < res_cap_dcn303.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub3->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub3->base; +} + +#define vpg_regs(id)\ + [id] = { VPG_DCN3_REG_LIST(id) } + +static const struct dcn30_vpg_registers vpg_regs[] = { + vpg_regs(0), + vpg_regs(1), + vpg_regs(2) +}; + +static const struct dcn30_vpg_shift vpg_shift = { + DCN3_VPG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_vpg_mask vpg_mask = { + DCN3_VPG_MASK_SH_LIST(_MASK) +}; + +static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); + + if (!vpg3) + return NULL; + + vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); + + return &vpg3->base; +} + +#define afmt_regs(id)\ + [id] = { AFMT_DCN3_REG_LIST(id) } + +static const struct dcn30_afmt_registers afmt_regs[] = { + afmt_regs(0), + afmt_regs(1), + afmt_regs(2) +}; + +static const struct dcn30_afmt_shift afmt_shift = { + DCN3_AFMT_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_afmt_mask afmt_mask = { + DCN3_AFMT_MASK_SH_LIST(_MASK) +}; + +static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); + + if (!afmt3) + return NULL; + + afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); + + return &afmt3->base; +} + +#define audio_regs(id)\ + [id] = { AUD_COMMON_REG_LIST(id) } + +static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), + audio_regs(3), + audio_regs(4), + audio_regs(5), + audio_regs(6) +}; + +#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) + +static const struct dce_audio_shift audio_shift = { + DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) +{ + return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); +} + +#define stream_enc_regs(id)\ + [id] = { SE_DCN3_REG_LIST(id) } + +static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(0), + stream_enc_regs(1) +}; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct afmt *afmt; + int vpg_inst; + int afmt_inst; + + /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGE) { + vpg_inst = eng_id; + afmt_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn303_vpg_create(ctx, vpg_inst); + afmt = dcn303_afmt_create(ctx, afmt_inst); + + if (!enc1 || !vpg || !afmt) + return NULL; + + dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], + &se_shift, &se_mask); + + return &enc1->base; +} + +#define clk_src_regs(index, pllid)\ + [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } + +static const struct dce110_clk_src_regs clk_src_regs[] = { + clk_src_regs(0, A), + clk_src_regs(1, B) +}; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) +}; + +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) +}; + +static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, + enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +static const struct dce_hwseq_registers hwseq_reg = { + HWSEQ_DCN303_REG_LIST() +}; + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN303_MASK_SH_LIST(_MASK) +}; + +static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + return hws; +} + +#define hubp_regs(id)\ + [id] = { HUBP_REG_LIST_DCN30(id) } + +static const struct dcn_hubp2_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1) +}; + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + + if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} + +#define dpp_regs(id)\ + [id] = { DPP_REG_LIST_DCN30(id) } + +static const struct dcn3_dpp_registers dpp_regs[] = { + dpp_regs(0), + dpp_regs(1) +}; + +static const struct dcn3_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) +}; + +static const struct dcn3_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN30(_MASK) +}; + +static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); + + if (!dpp) + return NULL; + + if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp); + return NULL; +} + +#define opp_regs(id)\ + [id] = { OPP_REG_LIST_DCN30(id) } + +static const struct dcn20_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1) +}; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT) +}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK) +}; + +static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; +} + +#define optc_regs(id)\ + [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } + +static const struct dcn_optc_registers optc_regs[] = { + optc_regs(0), + optc_regs(1) +}; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) +{ + struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; + + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn30_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct dcn30_mpc_registers mpc_regs = { + MPC_REG_LIST_DCN3_0(0), + MPC_REG_LIST_DCN3_0(1), + MPC_OUT_MUX_REG_LIST_DCN3_0(0), + MPC_OUT_MUX_REG_LIST_DCN3_0(1), + MPC_RMU_GLOBAL_REG_LIST_DCN3AG, + MPC_RMU_REG_LIST_DCN3AG(0), + MPC_DWB_MUX_REG_LIST_DCN3_0(0), +}; + +static const struct dcn30_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) +}; + +static const struct dcn30_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) +}; + +static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) +{ + struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); + + if (!mpc30) + return NULL; + + dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); + + return &mpc30->base; +} + +#define dsc_regsDCN20(id)\ +[id] = { DSC_REG_LIST_DCN20(id) } + +static const struct dcn20_dsc_registers dsc_regs[] = { + dsc_regsDCN20(0), + dsc_regsDCN20(1) +}; + +static const struct dcn20_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) +}; + +static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) +}; + +static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + return &dsc->base; +} + +#define dwbc_regs_dcn3(id)\ +[id] = { DWBC_COMMON_REG_LIST_DCN30(id) } + +static const struct dcn30_dwbc_registers dwbc30_regs[] = { + dwbc_regs_dcn3(0) +}; + +static const struct dcn30_dwbc_shift dwbc30_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_dwbc_mask dwbc30_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); + + if (!dwbc30) { + dm_error("DC: failed to create dwbc30!\n"); + return false; + } + + dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); + + pool->dwbc[i] = &dwbc30->base; + } + return true; +} + +#define mcif_wb_regs_dcn3(id)\ +[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } + +static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { + mcif_wb_regs_dcn3(0) +}; + +static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + + dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +#define aux_engine_regs(id)\ +[id] = {\ + AUX_COMMON_REG_LIST0(id), \ + .AUXN_IMPCAL = 0, \ + .AUXP_IMPCAL = 0, \ + .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ +} + +static const struct dce110_aux_registers aux_engine_regs[] = { + aux_engine_regs(0), + aux_engine_regs(1) +}; + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK) +}; + +static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + + dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} + +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } + +static const struct dce_i2c_registers i2c_hw_regs[] = { + i2c_inst_regs(1), + i2c_inst_regs(2) +}; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) +}; + +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) +}; + +static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true +}; + +#define link_regs(id, phyid)\ + [id] = {\ + LE_DCN3_REG_LIST(id), \ + UNIPHY_DCN2_REG_LIST(phyid), \ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ + } + +static const struct dcn10_link_enc_registers link_enc_regs[] = { + link_regs(0, A), + link_regs(1, B) +}; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), + DPCS_DCN2_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), + DPCS_DCN2_MASK_SH_LIST(_MASK) +}; + +#define aux_regs(id)\ + [id] = { DCN2_AUX_REG_LIST(id) } + +static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { + aux_regs(0), + aux_regs(1) +}; + +#define hpd_regs(id)\ + [id] = { HPD_REG_LIST(id) } + +static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { + hpd_regs(0), + hpd_regs(1) +}; + +static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20) + return NULL; + + dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); + + return &enc20->enc10.base; +} + +static const struct dce_panel_cntl_registers panel_cntl_regs[] = { + { DCN_PANEL_CNTL_REG_LIST() } +}; + +static const struct dce_panel_cntl_shift panel_cntl_shift = { + DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_panel_cntl_mask panel_cntl_mask = { + DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) +}; + +static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) +{ + struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); + + if (!panel_cntl) + return NULL; + + dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], + &panel_cntl_shift, &panel_cntl_mask); + + return &panel_cntl->base; +} + +static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) +{ + generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); +} + +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn303_create_audio, + .create_stream_encoder = dcn303_stream_encoder_create, + .create_hwseq = dcn303_hwseq_create, +}; + +static const struct resource_create_funcs res_create_maximus_funcs = { + .read_dce_straps = NULL, + .create_audio = NULL, + .create_stream_encoder = NULL, + .create_hwseq = dcn303_hwseq_create, +}; + +static bool is_soc_bounding_box_valid(struct dc *dc) +{ + uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; + + if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) + return true; + + return false; +} + +static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) +{ + struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; + struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; + + DC_LOGGER_INIT(dc->ctx->logger); + + if (!is_soc_bounding_box_valid(dc)) { + DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); + return false; + } + + loaded_ip->max_num_otg = pool->pipe_count; + loaded_ip->max_num_dpp = pool->pipe_count; + loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; + dcn20_patch_bounding_box(dc, loaded_bb); + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { + struct bp_soc_bb_info bb_info = { 0 }; + + if (dc->ctx->dc_bios->funcs->get_soc_bb_info( + dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { + if (bb_info.dram_clock_change_latency_100ns > 0) + dcn3_03_soc.dram_clock_change_latency_us = + bb_info.dram_clock_change_latency_100ns * 10; + + if (bb_info.dram_sr_enter_exit_latency_100ns > 0) + dcn3_03_soc.sr_enter_plus_exit_time_us = + bb_info.dram_sr_enter_exit_latency_100ns * 10; + + if (bb_info.dram_sr_exit_latency_100ns > 0) + dcn3_03_soc.sr_exit_time_us = + bb_info.dram_sr_exit_latency_100ns * 10; + } + } + + return true; +} + +static void dcn303_resource_destruct(struct resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->stream_enc_count; i++) { + if (pool->stream_enc[i] != NULL) { + if (pool->stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); + pool->stream_enc[i]->vpg = NULL; + } + if (pool->stream_enc[i]->afmt != NULL) { + kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); + pool->stream_enc[i]->afmt = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); + pool->stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->res_cap->num_dsc; i++) { + if (pool->dscs[i] != NULL) + dcn20_dsc_destroy(&pool->dscs[i]); + } + + if (pool->mpc != NULL) { + kfree(TO_DCN20_MPC(pool->mpc)); + pool->mpc = NULL; + } + + if (pool->hubbub != NULL) { + kfree(pool->hubbub); + pool->hubbub = NULL; + } + + for (i = 0; i < pool->pipe_count; i++) { + if (pool->dpps[i] != NULL) { + kfree(TO_DCN20_DPP(pool->dpps[i])); + pool->dpps[i] = NULL; + } + + if (pool->hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->hubps[i])); + pool->hubps[i] = NULL; + } + + if (pool->irqs != NULL) + dal_irq_service_destroy(&pool->irqs); + } + + for (i = 0; i < pool->res_cap->num_ddc; i++) { + if (pool->engines[i] != NULL) + dce110_engine_destroy(&pool->engines[i]); + if (pool->hw_i2cs[i] != NULL) { + kfree(pool->hw_i2cs[i]); + pool->hw_i2cs[i] = NULL; + } + if (pool->sw_i2cs[i] != NULL) { + kfree(pool->sw_i2cs[i]); + pool->sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->res_cap->num_opp; i++) { + if (pool->opps[i] != NULL) + pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); + } + + for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + if (pool->timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); + pool->timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->res_cap->num_dwb; i++) { + if (pool->dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->dwbc[i])); + pool->dwbc[i] = NULL; + } + if (pool->mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); + pool->mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->audio_count; i++) { + if (pool->audios[i]) + dce_aud_destroy(&pool->audios[i]); + } + + for (i = 0; i < pool->clk_src_count; i++) { + if (pool->clock_sources[i] != NULL) + dcn20_clock_source_destroy(&pool->clock_sources[i]); + } + + if (pool->dp_clock_source != NULL) + dcn20_clock_source_destroy(&pool->dp_clock_source); + + for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + if (pool->mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->mpc_lut[i]); + pool->mpc_lut[i] = NULL; + } + if (pool->mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->mpc_shaper[i]); + pool->mpc_shaper[i] = NULL; + } + } + + for (i = 0; i < pool->pipe_count; i++) { + if (pool->multiple_abms[i] != NULL) + dce_abm_destroy(&pool->multiple_abms[i]); + } + + if (pool->psr != NULL) + dmub_psr_destroy(&pool->psr); + + if (pool->dccg != NULL) + dcn_dccg_destroy(&pool->dccg); + + if (pool->oem_device != NULL) + dal_ddc_service_destroy(&pool->oem_device); +} + +static void dcn303_destroy_resource_pool(struct resource_pool **pool) +{ + dcn303_resource_destruct(*pool); + kfree(*pool); + *pool = NULL; +} + +static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, + unsigned int *optimal_dcfclk, + unsigned int *optimal_fclk) +{ + double bw_from_dram, bw_from_dram1, bw_from_dram2; + + bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * + dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); + bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * + dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); + + bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; + + if (optimal_fclk) + *optimal_fclk = bw_from_dram / + (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * + (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); + + if (optimal_dcfclk) + *optimal_dcfclk = bw_from_dram / + (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); +} + +void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + unsigned int i, j; + unsigned int num_states = 0; + + unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; + unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; + unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; + + unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; + unsigned int num_dcfclk_sta_targets = 4; + unsigned int num_uclk_states; + + + if (dc->ctx->dc_bios->vram_info.num_chans) + dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; + + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) + dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + + if (bw_params->clk_table.entries[0].memclk_mhz) { + int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + + for (i = 0; i < MAX_NUM_DPM_LVL; i++) { + if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) + max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; + if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; + if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) + max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; + } + if (!max_dcfclk_mhz) + max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; + if (!max_dispclk_mhz) + max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; + if (!max_dppclk_mhz) + max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; + if (!max_phyclk_mhz) + max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; + + if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; + num_dcfclk_sta_targets++; + } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + for (i = 0; i < num_dcfclk_sta_targets; i++) { + if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { + dcfclk_sta_targets[i] = max_dcfclk_mhz; + break; + } + } + /* Update size of array since we "removed" duplicates */ + num_dcfclk_sta_targets = i + 1; + } + + num_uclk_states = bw_params->clk_table.num_entries; + + /* Calculate optimal dcfclk for each uclk */ + for (i = 0; i < num_uclk_states; i++) { + dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, + &optimal_dcfclk_for_uclk[i], NULL); + if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) + optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; + } + + /* Calculate optimal uclk for each dcfclk sta target */ + for (i = 0; i < num_dcfclk_sta_targets; i++) { + for (j = 0; j < num_uclk_states; j++) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { + optimal_uclk_for_dcfclk_sta_targets[i] = + bw_params->clk_table.entries[j].memclk_mhz * 16; + break; + } + } + } + + i = 0; + j = 0; + /* create the final dcfclk and uclk table */ + while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } else { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = + bw_params->clk_table.entries[j++].memclk_mhz * 16; + } else { + j = num_uclk_states; + } + } + } + + while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { + dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; + dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; + } + + while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && + optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { + dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; + dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; + } + + dcn3_03_soc.num_states = num_states; + for (i = 0; i < dcn3_03_soc.num_states; i++) { + dcn3_03_soc.clock_limits[i].state = i; + dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; + dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; + dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; + + /* Fill all states with max values of all other clocks */ + dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; + dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; + dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; + dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; + /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */ + /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ + dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; + dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz; + dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; + } + /* re-init DML with updated bb */ + dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); + if (dc->current_state) + dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); + } +} + +static struct resource_funcs dcn303_res_pool_funcs = { + .destroy = dcn303_destroy_resource_pool, + .link_enc_create = dcn303_link_encoder_create, + .panel_cntl_create = dcn303_panel_cntl_create, + .validate_bandwidth = dcn30_validate_bandwidth, + .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, + .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, + .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn303_update_bw_bounding_box, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, +}; + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap +}; + +static const struct bios_registers bios_regs = { + NBIO_SR(BIOS_SCRATCH_3), + NBIO_SR(BIOS_SCRATCH_6) +}; + +static const struct dccg_registers dccg_regs = { + DCCG_REG_LIST_DCN3_03() +}; + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) +}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN3_03(_MASK) +}; + +#define abm_regs(id)\ + [id] = { ABM_DCN301_REG_LIST(id) } + +static const struct dce_abm_registers abm_regs[] = { + abm_regs(0), + abm_regs(1) +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN30(_MASK) +}; + +static bool dcn303_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct resource_pool *pool) +{ + int i; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + struct ddc_service_init_data ddc_init_data; + + ctx->dc_bios->regs = &bios_regs; + + pool->res_cap = &res_cap_dcn303; + + pool->funcs = &dcn303_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->pipe_count = pool->res_cap->num_timing_generator; + pool->mpcc_count = pool->res_cap->num_timing_generator; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ + dc->caps.max_cursor_size = 256; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; +#if defined(CONFIG_DRM_AMD_DC_DCN) + dc->caps.mall_size_per_mem_channel = 4; + /* total size = mall per channel * num channels * 1024 * 1024 */ + dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * + dc->ctx->dc_bios->vram_info.num_chans * + 1024 * 1024; + dc->caps.cursor_cache_size = + dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; +#endif + dc->caps.max_slave_planes = 1; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 1; + dc->caps.color.dpp.ogam_ram = 1; + // no OGAM ROM on DCN3 + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + else + dc->debug = debug_defaults_diags; + + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->clock_sources[DCN303_CLK_SRC_PLL0] = + dcn303_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->clock_sources[DCN303_CLK_SRC_PLL1] = + dcn303_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + + pool->clk_src_count = DCN303_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->dp_clock_source = + dcn303_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->clk_src_count; i++) { + if (pool->clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* DCCG */ + pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* PP Lib and SMU interfaces */ + init_soc_bounding_box(dc, pool); + + /* DML */ + dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); + + /* IRQ */ + init_data.ctx = dc->ctx; + pool->irqs = dal_irq_service_dcn303_create(&init_data); + if (!pool->irqs) + goto create_fail; + + /* HUBBUB */ + pool->hubbub = dcn303_hubbub_create(ctx); + if (pool->hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs and TGs */ + for (i = 0; i < pool->pipe_count; i++) { + pool->hubps[i] = dcn303_hubp_create(ctx, i); + if (pool->hubps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubps!\n"); + goto create_fail; + } + + pool->dpps[i] = dcn303_dpp_create(ctx, i); + if (pool->dpps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dpps!\n"); + goto create_fail; + } + } + + for (i = 0; i < pool->res_cap->num_opp; i++) { + pool->opps[i] = dcn303_opp_create(ctx, i); + if (pool->opps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create output pixel processor!\n"); + goto create_fail; + } + } + + for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); + if (pool->timing_generators[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + } + pool->timing_generator_count = i; + + /* PSR */ + pool->psr = dmub_psr_create(ctx); + if (pool->psr == NULL) { + dm_error("DC: failed to create psr!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* ABM */ + for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); + if (pool->multiple_abms[i] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* MPC and DSC */ + pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); + if (pool->mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + for (i = 0; i < pool->res_cap->num_dsc; i++) { + pool->dscs[i] = dcn303_dsc_create(ctx, i); + if (pool->dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB and MMHUBBUB */ + if (!dcn303_dwbc_create(ctx, pool)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + if (!dcn303_mmhubbub_create(ctx, pool)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->res_cap->num_ddc; i++) { + pool->engines[i] = dcn303_aux_engine_create(ctx, i); + if (pool->engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); + if (pool->hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->sw_i2cs[i] = NULL; + } + + /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, pool, + (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? + &res_create_funcs : &res_create_maximus_funcs))) + goto create_fail; + + /* HW Sequencer and Plane caps */ + dcn303_hw_sequencer_construct(dc); + + dc->caps.max_planes = pool->pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->cap_funcs = cap_funcs; + + if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { + ddc_init_data.ctx = dc->ctx; + ddc_init_data.link = NULL; + ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; + ddc_init_data.id.enum_id = 0; + ddc_init_data.id.type = OBJECT_TYPE_GENERIC; + pool->oem_device = dal_ddc_service_create(&ddc_init_data); + } else { + pool->oem_device = NULL; + } + + return true; + +create_fail: + + dcn303_resource_destruct(pool); + + return false; +} + +struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) +{ + struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) + return pool; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h new file mode 100644 index 000000000000..5b590c169763 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _DCN303_RESOURCE_H_ +#define _DCN303_RESOURCE_H_ + +#include "core_types.h" + +struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc); + +void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); + +#endif /* _DCN303_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile new file mode 100644 index 000000000000..5dcdc5a858fe --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile @@ -0,0 +1,42 @@ +# +# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved +# +# All rights reserved. This notice is intended as a precaution against +# inadvertent publication and does not imply publication or any waiver +# of confidentiality. The year included in the foregoing notice is the +# year of creation of the work. +# +# Authors: AMD +# +# Makefile for dcn31. + +DCN31 = dcn31_resource.o dcn31_hubbub.o dcn31_hwseq.o dcn31_init.o dcn31_hubp.o \ + dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o + +ifdef CONFIG_X86 +CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -msse +endif + +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -mhard-float -maltivec +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mhard-float +endif + +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mpreferred-stack-boundary=4 +else +CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -msse2 +endif + +AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCN31) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c new file mode 100644 index 000000000000..696c9307715d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -0,0 +1,279 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn31_dccg.h" + +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) + +#define REG(reg) \ + (dccg_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name + +#define CTX \ + dccg_dcn->base.ctx +#define DC_LOGGER \ + dccg->ctx->logger + +void dccg31_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */ + switch (phy_inst) { + case 0: + if (force_enable) + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_FORCE_EN, 1, + PHYASYMCLK_FORCE_SRC_SEL, clk_src); + else + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_FORCE_EN, 0, + PHYASYMCLK_FORCE_SRC_SEL, 0); + break; + case 1: + if (force_enable) + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_FORCE_EN, 1, + PHYBSYMCLK_FORCE_SRC_SEL, clk_src); + else + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_FORCE_EN, 0, + PHYBSYMCLK_FORCE_SRC_SEL, 0); + break; + case 2: + if (force_enable) + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_FORCE_EN, 1, + PHYCSYMCLK_FORCE_SRC_SEL, clk_src); + else + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_FORCE_EN, 0, + PHYCSYMCLK_FORCE_SRC_SEL, 0); + break; + case 3: + if (force_enable) + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_FORCE_EN, 1, + PHYDSYMCLK_FORCE_SRC_SEL, clk_src); + else + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_FORCE_EN, 0, + PHYDSYMCLK_FORCE_SRC_SEL, 0); + break; + case 4: + if (force_enable) + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_FORCE_EN, 1, + PHYESYMCLK_FORCE_SRC_SEL, clk_src); + else + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_FORCE_EN, 0, + PHYESYMCLK_FORCE_SRC_SEL, 0); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ +void dccg31_set_dtbclk_dto( + struct dccg *dccg, + int dtbclk_inst, + int req_dtbclk_khz, + int num_odm_segments, + const struct dc_crtc_timing *timing) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + uint32_t dtbdto_div; + + /* Mode DTBDTO Rate DTBCLK_DTO_DIV Register + * ODM 4:1 combine pixel rate/4 2 + * ODM 2:1 combine pixel rate/2 4 + * non-DSC 4:2:0 mode pixel rate/2 4 + * DSC native 4:2:0 pixel rate/2 4 + * DSC native 4:2:2 pixel rate/2 4 + * Other modes pixel rate 8 + */ + if (num_odm_segments == 4) { + dtbdto_div = 2; + req_dtbclk_khz = req_dtbclk_khz / 4; + } else if ((num_odm_segments == 2) || + (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || + (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 + && !timing->dsc_cfg.ycbcr422_simple)) { + dtbdto_div = 4; + req_dtbclk_khz = req_dtbclk_khz / 2; + } else + dtbdto_div = 8; + + if (dccg->ref_dtbclk_khz && req_dtbclk_khz) { + uint32_t modulo, phase; + + // phase / modulo = dtbclk / dtbclk ref + modulo = dccg->ref_dtbclk_khz * 1000; + phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1), + dccg->ref_dtbclk_khz); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst], + DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div); + + REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], modulo); + REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], phase); + + REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst], + DTBCLK_DTO_ENABLE[dtbclk_inst], 1); + + REG_WAIT(OTG_PIXEL_RATE_CNTL[dtbclk_inst], + DTBCLKDTO_ENABLE_STATUS[dtbclk_inst], 1, + 1, 100); + + /* The recommended programming sequence to enable DTBCLK DTO to generate + * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should + * be set only after DTO is enabled + */ + REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst], + PIPE_DTO_SRC_SEL[dtbclk_inst], 1); + + dccg->dtbclk_khz[dtbclk_inst] = req_dtbclk_khz; + } else { + REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[dtbclk_inst], + DTBCLK_DTO_ENABLE[dtbclk_inst], 0, + PIPE_DTO_SRC_SEL[dtbclk_inst], 0, + DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div); + + REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], 0); + REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], 0); + + dccg->dtbclk_khz[dtbclk_inst] = 0; + } +} + +void dccg31_set_audio_dtbclk_dto( + struct dccg *dccg, + uint32_t req_audio_dtbclk_khz) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) { + uint32_t modulo, phase; + + // phase / modulo = dtbclk / dtbclk ref + modulo = dccg->ref_dtbclk_khz * 1000; + phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1), + dccg->ref_dtbclk_khz); + + + REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); + REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); + + //REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, + // DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1); + + REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO_SEL, 4); // 04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK + + dccg->audio_dtbclk_khz = req_audio_dtbclk_khz; + } else { + REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); + REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); + + REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO_SEL, 3); // 03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO + + dccg->audio_dtbclk_khz = 0; + } +} + +static void dccg31_get_dccg_ref_freq(struct dccg *dccg, + unsigned int xtalin_freq_inKhz, + unsigned int *dccg_ref_freq_inKhz) +{ + /* + * Assume refclk is sourced from xtalin + * expect 24MHz + */ + *dccg_ref_freq_inKhz = xtalin_freq_inKhz; + return; +} + +static void dccg31_set_dispclk_change_mode( + struct dccg *dccg, + enum dentist_dispclk_change_mode change_mode) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, + change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0); +} + +void dccg31_init(struct dccg *dccg) +{ +} + +static const struct dccg_funcs dccg31_funcs = { + .update_dpp_dto = dccg2_update_dpp_dto, + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg31_init, + .set_physymclk = dccg31_set_physymclk, + .set_dtbclk_dto = dccg31_set_dtbclk_dto, + .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, + .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, +}; + +struct dccg *dccg31_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg31_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h new file mode 100644 index 000000000000..706ad80ba873 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h @@ -0,0 +1,147 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN31_DCCG_H__ +#define __DCN31_DCCG_H__ + +#include "dcn30/dcn30_dccg.h" + +#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ + .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix + + +#define DCCG_REG_LIST_DCN31() \ + SR(DPPCLK_DTO_CTRL),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ + DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ + SR(PHYASYMCLK_CLOCK_CNTL),\ + SR(PHYBSYMCLK_CLOCK_CNTL),\ + SR(PHYCSYMCLK_CLOCK_CNTL),\ + SR(PHYDSYMCLK_CLOCK_CNTL),\ + SR(PHYESYMCLK_CLOCK_CNTL),\ + SR(DPSTREAMCLK_CNTL),\ + SR(SYMCLK32_SE_CNTL),\ + SR(SYMCLK32_LE_CNTL),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 0),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 1),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 2),\ + DCCG_SRII(MODULO, DTBCLK_DTO, 3),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 0),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 1),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 2),\ + DCCG_SRII(PHASE, DTBCLK_DTO, 3),\ + SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\ + SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\ + SR(DCCG_AUDIO_DTO_SOURCE),\ + SR(DENTIST_DISPCLK_CNTL) + + +#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh) + + +struct dccg *dccg31_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +void dccg31_init(struct dccg *dccg); + +void dccg31_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable); + +void dccg31_set_audio_dtbclk_dto( + struct dccg *dccg, + uint32_t req_audio_dtbclk_khz); + +void dccg31_set_hdmistreamclk( + struct dccg *dccg, + enum hdmistreamclk_source src); + +#endif //__DCN31_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c new file mode 100644 index 000000000000..90127c1f9e35 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c @@ -0,0 +1,406 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "reg_helper.h" + +#include "core_types.h" +#include "link_encoder.h" +#include "dcn31_dio_link_encoder.h" +#include "stream_encoder.h" +#include "i2caux_interface.h" +#include "dc_bios_types.h" + +#include "gpio_service_interface.h" + +#include "link_enc_cfg.h" +#include "dc_dmub_srv.h" + +#define CTX \ + enc10->base.ctx +#define DC_LOGGER \ + enc10->base.ctx->logger + +#define REG(reg)\ + (enc10->link_regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc10->link_shift->field_name, enc10->link_mask->field_name + +#define IND_REG(index) \ + (enc10->link_regs->index) + +#define AUX_REG(reg)\ + (enc10->aux_regs->reg) + +#define AUX_REG_READ(reg_name) \ + dm_read_reg(CTX, AUX_REG(reg_name)) + +#define AUX_REG_WRITE(reg_name, val) \ + dm_write_reg(CTX, AUX_REG(reg_name), val) + +void dcn31_link_encoder_set_dio_phy_mux( + struct link_encoder *enc, + enum encoder_type_select sel, + uint32_t hpo_inst) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + + switch (enc->transmitter) { + case TRANSMITTER_UNIPHY_A: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKA_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKA_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKA_CNTL, + ENC_TYPE_SEL, sel); + break; + case TRANSMITTER_UNIPHY_B: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKB_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKB_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKB_CNTL, + ENC_TYPE_SEL, sel); + break; + case TRANSMITTER_UNIPHY_C: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKC_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKC_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKC_CNTL, + ENC_TYPE_SEL, sel); + break; + case TRANSMITTER_UNIPHY_D: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKD_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKD_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKD_CNTL, + ENC_TYPE_SEL, sel); + break; + case TRANSMITTER_UNIPHY_E: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKE_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKE_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKE_CNTL, + ENC_TYPE_SEL, sel); + break; + case TRANSMITTER_UNIPHY_F: + if (sel == ENCODER_TYPE_HDMI_FRL) + REG_UPDATE(DIO_LINKF_CNTL, + HPO_HDMI_ENC_SEL, hpo_inst); + else if (sel == ENCODER_TYPE_DP_128B132B) + REG_UPDATE(DIO_LINKF_CNTL, + HPO_DP_ENC_SEL, hpo_inst); + REG_UPDATE(DIO_LINKF_CNTL, + ENC_TYPE_SEL, sel); + break; + default: + /* Do nothing */ + break; + } +} + +void enc31_hw_init(struct link_encoder *enc) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + +/* + 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 + 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 + 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 + 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 + 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 + 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 + 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 + 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 +*/ + +/* + AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, + AUX_RX_START_WINDOW = 1 [6:4] + AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] + AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 + AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 + AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 + AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 + AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 + AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 + AUX_RX_DETECTION_THRESHOLD [30:28] = 1 +*/ + AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); + + AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); + + //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; + // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk + // 27MHz -> 0xd + // 100MHz -> 0x32 + // 48MHz -> 0x18 + +#ifdef CLEANUP_FIXME + /*from display_init*/ + REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0); +#endif + + // Set TMDS_CTL0 to 1. This is a legacy setting. + REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); + + /*HW default is 5*/ + REG_UPDATE(RDPCSTX_CNTL, + RDPCS_TX_FIFO_RD_START_DELAY, 4); + + dcn10_aux_initialize(enc10); +} + +static const struct link_encoder_funcs dcn31_link_enc_funcs = { + .read_state = link_enc2_read_state, + .validate_output_with_stream = + dcn30_link_encoder_validate_output_with_stream, + .hw_init = enc31_hw_init, + .setup = dcn10_link_encoder_setup, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_dp_output = dcn31_link_encoder_enable_dp_output, + .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output, + .disable_output = dcn31_link_encoder_disable_output, + .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dcn10_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dcn10_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, + .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, + .enable_hpd = dcn10_link_encoder_enable_hpd, + .disable_hpd = dcn10_link_encoder_disable_hpd, + .is_dig_enabled = dcn10_is_dig_enabled, + .destroy = dcn10_link_encoder_destroy, + .fec_set_enable = enc2_fec_set_enable, + .fec_set_ready = enc2_fec_set_ready, + .fec_is_active = enc2_fec_is_active, + .get_dig_frontend = dcn10_get_dig_frontend, + .get_dig_mode = dcn10_get_dig_mode, + .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, + .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, +}; + +void dcn31_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask) +{ + struct bp_encoder_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enum bp_result result = BP_RESULT_OK; + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn31_link_enc_funcs; + enc10->base.ctx = init_data->ctx; + enc10->base.id = init_data->encoder; + + enc10->base.hpd_source = init_data->hpd_source; + enc10->base.connector = init_data->connector; + + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + + enc10->base.features = *enc_features; + + enc10->base.transmitter = init_data->transmitter; + + /* set the flag to indicate whether driver poll the I2C data pin + * while doing the DP sink detect + */ + +/* if (dal_adapter_service_is_feature_supported(as, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) + enc10->base.features.flags.bits. + DP_SINK_DETECT_POLL_DATA_PIN = true;*/ + + enc10->base.output_signals = + SIGNAL_TYPE_DVI_SINGLE_LINK | + SIGNAL_TYPE_DVI_DUAL_LINK | + SIGNAL_TYPE_LVDS | + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP | + SIGNAL_TYPE_HDMI_TYPE_A; + + /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. + * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. + * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer + * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. + * Prefer DIG assignment is decided by board design. + * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design + * and VBIOS will filter out 7 UNIPHY for DCE 8.0. + * By this, adding DIGG should not hurt DCE 8.0. + * This will let DCE 8.1 share DCE 8.0 as much as possible + */ + + enc10->link_regs = link_regs; + enc10->aux_regs = aux_regs; + enc10->hpd_regs = hpd_regs; + enc10->link_shift = link_shift; + enc10->link_mask = link_mask; + + switch (enc10->base.transmitter) { + case TRANSMITTER_UNIPHY_A: + enc10->base.preferred_engine = ENGINE_ID_DIGA; + break; + case TRANSMITTER_UNIPHY_B: + enc10->base.preferred_engine = ENGINE_ID_DIGB; + break; + case TRANSMITTER_UNIPHY_C: + enc10->base.preferred_engine = ENGINE_ID_DIGC; + break; + case TRANSMITTER_UNIPHY_D: + enc10->base.preferred_engine = ENGINE_ID_DIGD; + break; + case TRANSMITTER_UNIPHY_E: + enc10->base.preferred_engine = ENGINE_ID_DIGE; + break; + case TRANSMITTER_UNIPHY_F: + enc10->base.preferred_engine = ENGINE_ID_DIGF; + break; + default: + ASSERT_CRITICAL(false); + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + } + + /* default to one to mirror Windows behavior */ + enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + + result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, + enc10->base.id, &bp_cap_info); + + /* Override features with DCE-specific values */ + if (result == BP_RESULT_OK) { + enc10->base.features.flags.bits.IS_HBR2_CAPABLE = + bp_cap_info.DP_HBR2_EN; + enc10->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; + enc10->base.features.flags.bits.DP_IS_USB_C = + bp_cap_info.DP_IS_USB_C; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, + result); + } + if (enc10->base.ctx->dc->debug.hdmi20_disable) { + enc10->base.features.flags.bits.HDMI_6GB_EN = 0; + } +} + +void dcn31_link_encoder_construct_minimal( + struct dcn20_link_encoder *enc20, + struct dc_context *ctx, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + enum engine_id eng_id) +{ + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn31_link_enc_funcs; + enc10->base.ctx = ctx; + enc10->base.id.type = OBJECT_TYPE_ENCODER; + enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN; + enc10->base.connector.type = OBJECT_TYPE_CONNECTOR; + enc10->base.preferred_engine = eng_id; + enc10->base.features = *enc_features; + enc10->base.transmitter = TRANSMITTER_UNKNOWN; + enc10->link_regs = link_regs; + + enc10->base.output_signals = + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP; +} + +void dcn31_link_encoder_enable_dp_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) +{ + /* Enable transmitter and encoder. */ + if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) { + + dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source); + + } else { + + /** @todo Handle transmitter with programmable mapping to link encoder. */ + } +} + +void dcn31_link_encoder_enable_dp_mst_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) +{ + /* Enable transmitter and encoder. */ + if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) { + + dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); + + } else { + + /** @todo Handle transmitter with programmable mapping to link encoder. */ + } +} + +void dcn31_link_encoder_disable_output( + struct link_encoder *enc, + enum signal_type signal) +{ + /* Disable transmitter and encoder. */ + if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) { + + dcn10_link_encoder_disable_output(enc, signal); + + } else { + + /** @todo Handle transmitter with programmable mapping to link encoder. */ + } +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h new file mode 100644 index 000000000000..32d146312838 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h @@ -0,0 +1,246 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_ENCODER__DCN31_H__ +#define __DC_LINK_ENCODER__DCN31_H__ + +#include "dcn30/dcn30_dio_link_encoder.h" + + +#define LE_DCN31_REG_LIST(id)\ + LE_DCN3_REG_LIST(id),\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + SR(DIO_LINKA_CNTL), \ + SR(DIO_LINKB_CNTL), \ + SR(DIO_LINKC_CNTL), \ + SR(DIO_LINKD_CNTL), \ + SR(DIO_LINKE_CNTL), \ + SR(DIO_LINKF_CNTL) + +#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \ + LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ + LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ + LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\ + LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\ + LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh) + +#define DPCS_DCN31_REG_LIST(id) \ + SRI(TMDS_CTL_BITS, DIG, id), \ + SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \ + SRI(RDPCSTX_CNTL, RDPCSTX, id), \ + SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \ + SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \ + SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \ + SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \ + SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ + SR(RDPCSTX0_RDPCSTX_SCRATCH), \ + SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\ + SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id) + +#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\ + LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\ + LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\ + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh) + +void dcn31_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask); + +/* + * Create a minimal link encoder object with no dc_link object associated with it. + */ +void dcn31_link_encoder_construct_minimal( + struct dcn20_link_encoder *enc20, + struct dc_context *ctx, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + enum engine_id eng_id); + +void dcn31_link_encoder_set_dio_phy_mux( + struct link_encoder *enc, + enum encoder_type_select sel, + uint32_t hpo_inst); + +/* + * Enable DP transmitter and its encoder. + */ +void dcn31_link_encoder_enable_dp_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + +/* + * Enable DP transmitter and its encoder in MST mode. + */ +void dcn31_link_encoder_enable_dp_mst_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + +/* + * Disable transmitter and its encoder. + */ +void dcn31_link_encoder_disable_output( + struct link_encoder *enc, + enum signal_type signal); + +#endif /* __DC_LINK_ENCODER__DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c new file mode 100644 index 000000000000..bb9648488900 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c @@ -0,0 +1,956 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dcn30/dcn30_hubbub.h" +#include "dcn31_hubbub.h" +#include "dm_services.h" +#include "reg_helper.h" + + +#define CTX \ + hubbub2->base.ctx +#define DC_LOGGER \ + hubbub2->base.ctx->logger +#define REG(reg)\ + hubbub2->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hubbub2->shifts->field_name, hubbub2->masks->field_name + +#ifdef NUM_VMID +#undef NUM_VMID +#endif +#define NUM_VMID 16 + +#define DCN31_CRB_SEGMENT_SIZE_KB 64 + +static void dcn31_init_crb(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, + &hubbub2->det0_size); + + REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, + &hubbub2->det1_size); + + REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, + &hubbub2->det2_size); + + REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, + &hubbub2->det3_size); + + REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, + &hubbub2->compbuf_size_segments); + + REG_SET_2(COMPBUF_RESERVED_SPACE, 0, + COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32, + COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128); + REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F); +} + +static void dcn31_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB; + + switch (hubp_inst) { + case 0: + REG_UPDATE(DCHUBBUB_DET0_CTRL, + DET0_SIZE, det_size_segments); + hubbub2->det0_size = det_size_segments; + break; + case 1: + REG_UPDATE(DCHUBBUB_DET1_CTRL, + DET1_SIZE, det_size_segments); + hubbub2->det1_size = det_size_segments; + break; + case 2: + REG_UPDATE(DCHUBBUB_DET2_CTRL, + DET2_SIZE, det_size_segments); + hubbub2->det2_size = det_size_segments; + break; + case 3: + REG_UPDATE(DCHUBBUB_DET3_CTRL, + DET3_SIZE, det_size_segments); + hubbub2->det3_size = det_size_segments; + break; + default: + break; + } + /* Should never be hit, if it is we have an erroneous hw config*/ + ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size + + hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs); +} + +static void dcn31_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + unsigned int compbuf_size_segments = (compbuf_size_kb + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB; + + if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) { + if (compbuf_size_segments > hubbub2->compbuf_size_segments) { + REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); + REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); + REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); + REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); + } + /* Should never be hit, if it is we have an erroneous hw config*/ + ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size + + hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs); + REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments); + REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100); + hubbub2->compbuf_size_segments = compbuf_size_segments; + } +} + +static uint32_t convert_and_clamp( + uint32_t wm_ns, + uint32_t refclk_mhz, + uint32_t clamp_value) +{ + uint32_t ret_val = 0; + ret_val = wm_ns * refclk_mhz; + ret_val /= 1000; + + if (ret_val > clamp_value) + ret_val = clamp_value; + + return ret_val; +} + +static bool hubbub31_program_urgent_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + bool wm_pending = false; + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { + hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.urgent_ns, prog_wm_value); + } else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->a.frac_urg_bw_flip + > hubbub2->watermarks.a.frac_urg_bw_flip) { + hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); + } else if (watermarks->a.frac_urg_bw_flip + < hubbub2->watermarks.a.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->a.frac_urg_bw_nom + > hubbub2->watermarks.a.frac_urg_bw_nom) { + hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom); + } else if (watermarks->a.frac_urg_bw_nom + < hubbub2->watermarks.a.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) { + hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value); + } else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) { + hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.urgent_ns, prog_wm_value); + } else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->b.frac_urg_bw_flip + > hubbub2->watermarks.b.frac_urg_bw_flip) { + hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip); + } else if (watermarks->b.frac_urg_bw_flip + < hubbub2->watermarks.b.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->b.frac_urg_bw_nom + > hubbub2->watermarks.b.frac_urg_bw_nom) { + hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom); + } else if (watermarks->b.frac_urg_bw_nom + < hubbub2->watermarks.b.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) { + hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value); + } else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) { + hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.urgent_ns, prog_wm_value); + } else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->c.frac_urg_bw_flip + > hubbub2->watermarks.c.frac_urg_bw_flip) { + hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip); + } else if (watermarks->c.frac_urg_bw_flip + < hubbub2->watermarks.c.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->c.frac_urg_bw_nom + > hubbub2->watermarks.c.frac_urg_bw_nom) { + hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom); + } else if (watermarks->c.frac_urg_bw_nom + < hubbub2->watermarks.c.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) { + hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value); + } else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) { + hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns; + prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); + + DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.urgent_ns, prog_wm_value); + } else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->d.frac_urg_bw_flip + > hubbub2->watermarks.d.frac_urg_bw_flip) { + hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip); + } else if (watermarks->d.frac_urg_bw_flip + < hubbub2->watermarks.d.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->d.frac_urg_bw_nom + > hubbub2->watermarks.d.frac_urg_bw_nom) { + hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom; + + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom); + } else if (watermarks->d.frac_urg_bw_nom + < hubbub2->watermarks.d.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) { + hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns; + prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value); + } else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub31_program_stutter_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns = + watermarks->a.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = + watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns + > hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) { + hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns = + watermarks->a.cstate_pstate.cstate_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.cstate_exit_z8_ns + < hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns = + watermarks->b.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = + watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns + > hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) { + hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns = + watermarks->b.cstate_pstate.cstate_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.cstate_exit_z8_ns + < hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns = + watermarks->c.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = + watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns + > hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) { + hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns = + watermarks->c.cstate_pstate.cstate_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.cstate_exit_z8_ns + < hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns = + watermarks->d.cstate_pstate.cstate_exit_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_exit_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = + watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) + wm_pending = true; + + if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns + > hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) { + hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns = + watermarks->d.cstate_pstate.cstate_exit_z8_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_z8_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.cstate_exit_z8_ns + < hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub31_program_pstate_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t prog_wm_value; + + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.a.cstate_pstate.pstate_change_ns = + watermarks->a.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->a.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.b.cstate_pstate.pstate_change_ns = + watermarks->b.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->b.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) + wm_pending = false; + + /* clock state C */ + if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.c.cstate_pstate.pstate_change_ns = + watermarks->c.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->c.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns + > hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) { + hubbub2->watermarks.d.cstate_pstate.pstate_change_ns = + watermarks->d.cstate_pstate.pstate_change_ns; + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); + DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); + } else if (watermarks->d.cstate_pstate.pstate_change_ns + < hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub31_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + bool wm_pending = false; + + if (hubbub31_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + if (hubbub31_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + if (hubbub31_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) + wm_pending = true; + + /* + * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. + * If the memory controller is fully utilized and the DCHub requestors are + * well ahead of their amortized schedule, then it is safe to prevent the next winner + * from being committed and sent to the fabric. + * The utilization of the memory controller is approximated by ensuring that + * the number of outstanding requests is greater than a threshold specified + * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, + * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. + * + * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF) + * to turn off it for now. + */ + /*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/ + + hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + return wm_pending; +} + +static void hubbub3_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, + unsigned int bytes_per_element) +{ + /* copied from DML. might want to refactor DML to leverage from DML */ + /* DML : get_blk256_size */ + if (bytes_per_element == 1) { + *blk256_width = 16; + *blk256_height = 16; + } else if (bytes_per_element == 2) { + *blk256_width = 16; + *blk256_height = 8; + } else if (bytes_per_element == 4) { + *blk256_width = 8; + *blk256_height = 8; + } else if (bytes_per_element == 8) { + *blk256_width = 8; + *blk256_height = 4; + } +} + +static void hubbub31_det_request_size( + unsigned int detile_buf_size, + unsigned int height, + unsigned int width, + unsigned int bpe, + bool *req128_horz_wc, + bool *req128_vert_wc) +{ + unsigned int blk256_height = 0; + unsigned int blk256_width = 0; + unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; + + hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe); + + swath_bytes_horz_wc = width * blk256_height * bpe; + swath_bytes_vert_wc = height * blk256_width * bpe; + + *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? + false : /* full 256B request */ + true; /* half 128b request */ + + *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? + false : /* full 256B request */ + true; /* half 128b request */ +} + +static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub, + const struct dc_dcc_surface_param *input, + struct dc_surface_dcc_cap *output) +{ + struct dc *dc = hubbub->ctx->dc; + enum dcc_control dcc_control; + unsigned int bpe; + enum segment_order segment_order_horz, segment_order_vert; + bool req128_horz_wc, req128_vert_wc; + + memset(output, 0, sizeof(*output)); + + if (dc->debug.disable_dcc == DCC_DISABLE) + return false; + + if (!hubbub->funcs->dcc_support_pixel_format(input->format, + &bpe)) + return false; + + if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, + &segment_order_horz, &segment_order_vert)) + return false; + + hubbub31_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size, + input->surface_size.height, input->surface_size.width, + bpe, &req128_horz_wc, &req128_vert_wc); + + if (!req128_horz_wc && !req128_vert_wc) { + dcc_control = dcc_control__256_256_xxx; + } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { + if (!req128_horz_wc) + dcc_control = dcc_control__256_256_xxx; + else if (segment_order_horz == segment_order__contiguous) + dcc_control = dcc_control__128_128_xxx; + else + dcc_control = dcc_control__256_64_64; + } else if (input->scan == SCAN_DIRECTION_VERTICAL) { + if (!req128_vert_wc) + dcc_control = dcc_control__256_256_xxx; + else if (segment_order_vert == segment_order__contiguous) + dcc_control = dcc_control__128_128_xxx; + else + dcc_control = dcc_control__256_64_64; + } else { + if ((req128_horz_wc && + segment_order_horz == segment_order__non_contiguous) || + (req128_vert_wc && + segment_order_vert == segment_order__non_contiguous)) + /* access_dir not known, must use most constraining */ + dcc_control = dcc_control__256_64_64; + else + /* reg128 is true for either horz and vert + * but segment_order is contiguous + */ + dcc_control = dcc_control__128_128_xxx; + } + + /* Exception for 64KB_R_X */ + if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) + dcc_control = dcc_control__128_128_xxx; + + if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && + dcc_control != dcc_control__256_256_xxx) + return false; + + switch (dcc_control) { + case dcc_control__256_256_xxx: + output->grph.rgb.max_uncompressed_blk_size = 256; + output->grph.rgb.max_compressed_blk_size = 256; + output->grph.rgb.independent_64b_blks = false; + output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1; + output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; + break; + case dcc_control__128_128_xxx: + output->grph.rgb.max_uncompressed_blk_size = 128; + output->grph.rgb.max_compressed_blk_size = 128; + output->grph.rgb.independent_64b_blks = false; + output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1; + output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; + break; + case dcc_control__256_64_64: + output->grph.rgb.max_uncompressed_blk_size = 256; + output->grph.rgb.max_compressed_blk_size = 64; + output->grph.rgb.independent_64b_blks = true; + output->grph.rgb.dcc_controls.dcc_256_64_64 = 1; + break; + case dcc_control__256_128_128: + output->grph.rgb.max_uncompressed_blk_size = 256; + output->grph.rgb.max_compressed_blk_size = 128; + output->grph.rgb.independent_64b_blks = false; + output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; + break; + } + output->capable = true; + output->const_color_support = true; + + return true; +} + +static int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub, + struct dcn_hubbub_phys_addr_config *pa_config) +{ + hubbub3_init_dchub_sys_ctx(hubbub, pa_config); + + dcn21_dchvm_init(hubbub); + + return NUM_VMID; +} + +static void hubbub31_get_dchub_ref_freq(struct hubbub *hubbub, + unsigned int dccg_ref_freq_inKhz, + unsigned int *dchub_ref_freq_inKhz) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t ref_div = 0; + uint32_t ref_en = 0; + unsigned int dc_refclk_khz = 24000; + + REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, + DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en); + + if (ref_en) { + if (ref_div == 2) + *dchub_ref_freq_inKhz = dc_refclk_khz / 2; + else + *dchub_ref_freq_inKhz = dc_refclk_khz; + + /* + * The external Reference Clock may change based on the board or + * platform requirements and the programmable integer divide must + * be programmed to provide a suitable DLG RefClk frequency between + * a minimum of 20MHz and maximum of 50MHz + */ + if (*dchub_ref_freq_inKhz < 20000 || *dchub_ref_freq_inKhz > 50000) + ASSERT_CRITICAL(false); + + return; + } else { + *dchub_ref_freq_inKhz = dc_refclk_khz; + + // HUBBUB global timer must be enabled. + ASSERT_CRITICAL(false); + return; + } +} + +static const struct hubbub_funcs hubbub31_funcs = { + .update_dchub = hubbub2_update_dchub, + .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, + .init_vm_ctx = hubbub2_init_vm_ctx, + .dcc_support_swizzle = hubbub3_dcc_support_swizzle, + .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, + .get_dcc_compression_cap = hubbub31_get_dcc_compression_cap, + .wm_read_state = hubbub21_wm_read_state, + .get_dchub_ref_freq = hubbub31_get_dchub_ref_freq, + .program_watermarks = hubbub31_program_watermarks, + .allow_self_refresh_control = hubbub1_allow_self_refresh_control, + .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, + .program_det_size = dcn31_program_det_size, + .program_compbuf_size = dcn31_program_compbuf_size, + .init_crb = dcn31_init_crb +}; + +void hubbub31_construct(struct dcn20_hubbub *hubbub31, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb) +{ + + hubbub3_construct(hubbub31, ctx, hubbub_regs, hubbub_shift, hubbub_mask); + hubbub31->base.funcs = &hubbub31_funcs; + hubbub31->detile_buf_size = det_size_kb * 1024; + hubbub31->pixel_chunk_size = pixel_chunk_size_kb * 1024; + hubbub31->crb_size_segs = config_return_buffer_size_kb / DCN31_CRB_SEGMENT_SIZE_KB; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h new file mode 100644 index 000000000000..8ec98cbcbd47 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h @@ -0,0 +1,122 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN31_H__ +#define __DC_HUBBUB_DCN31_H__ + +#include "dcn21/dcn21_hubbub.h" + +#define HUBBUB_REG_LIST_DCN31(id)\ + HUBBUB_REG_LIST_DCN30(id),\ + SR(DCHVM_CTRL0),\ + SR(DCHVM_MEM_CTRL),\ + SR(DCHVM_CLK_CTRL),\ + SR(DCHVM_RIOMMU_CTRL0),\ + SR(DCHVM_RIOMMU_STAT0),\ + SR(DCHUBBUB_DET0_CTRL),\ + SR(DCHUBBUB_DET1_CTRL),\ + SR(DCHUBBUB_DET2_CTRL),\ + SR(DCHUBBUB_DET3_CTRL),\ + SR(DCHUBBUB_COMPBUF_CTRL),\ + SR(COMPBUF_RESERVED_SPACE),\ + SR(DCHUBBUB_DEBUG_CTRL_0),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D) + +#define HUBBUB_MASK_SH_LIST_DCN31(mask_sh)\ + HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ + HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh) + + +void hubbub31_construct(struct dcn20_hubbub *hubbub3, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c new file mode 100644 index 000000000000..53b792b997b7 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c @@ -0,0 +1,103 @@ +/* + * Copyright 2012-20 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dce_calcs.h" +#include "reg_helper.h" +#include "basics/conversion.h" +#include "dcn31_hubp.h" + +#define REG(reg)\ + hubp2->hubp_regs->reg + +#define CTX \ + hubp2->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name + +void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable); + REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable); +} + +void hubp31_soft_reset(struct hubp *hubp, bool reset) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(DCHUBP_CNTL, HUBP_SOFT_RESET, reset); +} + +static struct hubp_funcs dcn31_hubp_funcs = { + .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, + .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, + .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, + .hubp_program_surface_config = hubp3_program_surface_config, + .hubp_is_flip_pending = hubp2_is_flip_pending, + .hubp_setup = hubp3_setup, + .hubp_setup_interdependent = hubp2_setup_interdependent, + .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, + .set_blank = hubp2_set_blank, + .dcc_control = hubp3_dcc_control, + .mem_program_viewport = min_set_viewport, + .set_cursor_attributes = hubp2_cursor_set_attributes, + .set_cursor_position = hubp2_cursor_set_position, + .hubp_clk_cntl = hubp2_clk_cntl, + .hubp_vtg_sel = hubp2_vtg_sel, + .dmdata_set_attributes = hubp3_dmdata_set_attributes, + .dmdata_load = hubp2_dmdata_load, + .dmdata_status_done = hubp2_dmdata_status_done, + .hubp_read_state = hubp3_read_state, + .hubp_clear_underflow = hubp2_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp3_init, + .set_unbounded_requesting = hubp31_set_unbounded_requesting, + .hubp_soft_reset = hubp31_soft_reset, + .hubp_in_blank = hubp1_in_blank, +}; + +bool hubp31_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask) +{ + hubp2->base.funcs = &dcn31_hubp_funcs; + hubp2->base.ctx = ctx; + hubp2->hubp_regs = hubp_regs; + hubp2->hubp_shift = hubp_shift; + hubp2->hubp_mask = hubp_mask; + hubp2->base.inst = inst; + hubp2->base.opp_id = OPP_ID_INVALID; + hubp2->base.mpcc_id = 0xf; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h new file mode 100644 index 000000000000..c31a7b8f81ee --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h @@ -0,0 +1,246 @@ +/* + * Copyright 2012-20 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBP_DCN31_H__ +#define __DC_HUBP_DCN31_H__ + +#include "dcn20/dcn20_hubp.h" +#include "dcn21/dcn21_hubp.h" +#include "dcn30/dcn30_hubp.h" + +#define HUBP_MASK_SH_LIST_DCN31(mask_sh)\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\ + HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ + HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ + HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ + HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ + HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) + + +bool hubp31_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask); + +void hubp31_soft_reset(struct hubp *hubp, bool reset); + +void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable); + +#endif /* __DC_HUBP_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c new file mode 100644 index 000000000000..fc1fc1a4bf8b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -0,0 +1,596 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dm_services.h" +#include "dm_helpers.h" +#include "core_types.h" +#include "resource.h" +#include "dccg.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "reg_helper.h" +#include "abm.h" +#include "hubp.h" +#include "dchubbub.h" +#include "timing_generator.h" +#include "opp.h" +#include "ipp.h" +#include "mpc.h" +#include "mcif_wb.h" +#include "dc_dmub_srv.h" +#include "dcn31_hwseq.h" +#include "link_hwss.h" +#include "dpcd_defs.h" +#include "dce/dmub_outbox.h" +#include "dc_link_dp.h" +#include "inc/link_dpcd.h" + +#define DC_LOGGER_INIT(logger) + +#define CTX \ + hws->ctx +#define REG(reg)\ + hws->regs->reg +#define DC_LOGGER \ + dc->ctx->logger + + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + +void dcn31_init_hw(struct dc *dc) +{ + struct abm **abms = dc->res_pool->multiple_abms; + struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct resource_pool *res_pool = dc->res_pool; + uint32_t backlight = MAX_BACKLIGHT_LEVEL; + int i, j; + int edp_num; + + if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) + dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); + + // Initialize the dccg + if (res_pool->dccg->funcs->dccg_init) + res_pool->dccg->funcs->dccg_init(res_pool->dccg); + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + + REG_WRITE(REFCLK_CNTL, 0); + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + //Enable ability to power gate / don't force power on permanently + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(hws, true); + + return; + } + + if (!dcb->funcs->is_accelerated_mode(dcb)) { + hws->funcs.bios_golden_init(dc); + hws->funcs.disable_vga(dc->hwseq); + } + + if (dc->debug.enable_mem_low_power.bits.dmcu) { + // Force ERAM to shutdown if DMCU is not enabled + if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { + REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); + } + } + + // Set default OPTC memory power states + if (dc->debug.enable_mem_low_power.bits.optc) { + // Shutdown when unassigned and light sleep in VBLANK + REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); + } + + if (dc->debug.enable_mem_low_power.bits.vga) { + // Power down VGA memory + REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); + } + + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + if (res_pool->dccg && res_pool->hubbub) { + + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } + } else + ASSERT_CRITICAL(false); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + link->link_enc->funcs->hw_init(link->link_enc); + + /* Check for enabled DIG to identify enabled display */ + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) + link->link_status.link_active = true; + } + + /* Power gate DSCs */ + for (i = 0; i < res_pool->res_cap->num_dsc; i++) + if (hws->funcs.dsc_pg_control != NULL) + hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); + + /* we want to turn off all dp displays before doing detection */ + if (dc->config.power_down_display_on_boot) { + uint8_t dpcd_power_state = '\0'; + enum dc_status status = DC_ERROR_UNEXPECTED; + + for (i = 0; i < dc->link_count; i++) { + if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) + continue; + + /* if any of the displays are lit up turn them off */ + status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, + &dpcd_power_state, sizeof(dpcd_power_state)); + if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { + /* blank dp stream before power off receiver*/ + if (dc->links[i]->link_enc->funcs->get_dig_frontend) { + unsigned int fe; + + fe = dc->links[i]->link_enc->funcs->get_dig_frontend( + dc->links[i]->link_enc); + if (fe == ENGINE_ID_UNKNOWN) + continue; + + for (j = 0; j < dc->res_pool->stream_enc_count; j++) { + if (fe == dc->res_pool->stream_enc[j]->id) { + dc->res_pool->stream_enc[j]->funcs->dp_blank( + dc->res_pool->stream_enc[j]); + break; + } + } + } + dp_receiver_power_ctrl(dc->links[i], false); + } + } + } + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which + * pipes we want to use. + * Otherwise, if taking control is not possible, we need to power + * everything down. + */ + if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { + hws->funcs.init_pipes(dc, dc->current_state); + if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) + dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, + !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); + } + + /* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on and seamless boot not enabled + */ + if (dc->config.power_down_display_on_boot) { + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link; + + get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwss.edp_backlight_control && + dc->hwss.power_down && + dc->hwss.edp_power_control) { + dc->hwss.edp_backlight_control(edp_link, false); + dc->hwss.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + dc->hwss.power_down) { + dc->hwss.power_down(dc); + break; + } + + } + } + } + + for (i = 0; i < res_pool->audio_count; i++) { + struct audio *audio = res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->panel_cntl) + backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (abms[i] != NULL) + abms[i]->funcs->abm_init(abms[i], backlight); + } + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(dc->hwseq, true); + + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) + dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); + + if (dc->clk_mgr->funcs->notify_wm_ranges) + dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); + + if (dc->clk_mgr->funcs->set_hard_max_memclk) + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); + + if (dc->res_pool->hubbub->funcs->force_pstate_change_control) + dc->res_pool->hubbub->funcs->force_pstate_change_control( + dc->res_pool->hubbub, false, false); + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); +} + +void dcn31_dsc_pg_control( + struct dce_hwseq *hws, + unsigned int dsc_inst, + bool power_on) +{ + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl = 0; + + if (hws->ctx->dc->debug.disable_dsc_power_gate) + return; + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); +} + + +void dcn31_enable_power_gating_plane( + struct dce_hwseq *hws, + bool enable) +{ + bool force_on = true; /* disable power gating */ + + if (enable) + force_on = false; + + /* DCHUBP0/1/2/3/4/5 */ + REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + + /* DPP0/1/2/3/4/5 */ + REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + + /* DCS0/1/2/3/4/5 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); + REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); +} + +void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) +{ + bool is_hdmi_tmds; + bool is_dp; + + ASSERT(pipe_ctx->stream); + + if (pipe_ctx->stream_res.stream_enc == NULL) + return; /* this is not root pipe */ + + is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); + is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); + + if (!is_hdmi_tmds) + return; + + if (is_hdmi_tmds) + pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( + pipe_ctx->stream_res.stream_enc, + &pipe_ctx->stream_res.encoder_info_frame); + else { + pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( + pipe_ctx->stream_res.stream_enc, + &pipe_ctx->stream_res.encoder_info_frame); + } +} + +void dcn31_z10_restore(struct dc *dc) +{ + union dmub_rb_cmd cmd; + + /* + * DMUB notifies whether restore is required. + * Optimization to avoid sending commands when not required. + */ + if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) + return; + + memset(&cmd, 0, sizeof(cmd)); + cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; + cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; + + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); +} + +void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) +{ + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + + if (hws->ctx->dc->debug.disable_hubp_power_gate) + return; + + if (REG(DOMAIN0_PG_CONFIG) == 0) + return; + + switch (hubp_inst) { + case 0: + REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 1: + REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 2: + REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 3: + REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } +} + +int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) +{ + struct dcn_hubbub_phys_addr_config config; + + config.system_aperture.fb_top = pa_config->system_aperture.fb_top; + config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; + config.system_aperture.fb_base = pa_config->system_aperture.fb_base; + config.system_aperture.agp_top = pa_config->system_aperture.agp_top; + config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; + config.system_aperture.agp_base = pa_config->system_aperture.agp_base; + config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; + config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; + + if (pa_config->gart_config.base_addr_is_mc_addr) { + /* Convert from MC address to offset into FB */ + config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - + pa_config->system_aperture.fb_base + + pa_config->system_aperture.fb_offset; + } else + config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; + + return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); +} + +static void dcn31_reset_back_end_for_pipe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +{ + struct dc_link *link; + + DC_LOGGER_INIT(dc->ctx->logger); + if (pipe_ctx->stream_res.stream_enc == NULL) { + pipe_ctx->stream = NULL; + return; + } + ASSERT(!pipe_ctx->top_pipe); + + dc->hwss.set_abm_immediate_disable(pipe_ctx); + + pipe_ctx->stream_res.tg->funcs->set_dsc_config( + pipe_ctx->stream_res.tg, + OPTC_DSC_DISABLED, 0, 0); + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); + if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + + if (pipe_ctx->stream_res.tg->funcs->set_drr) + pipe_ctx->stream_res.tg->funcs->set_drr( + pipe_ctx->stream_res.tg, NULL); + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + link = pipe_ctx->stream->link; + /* DPMS may already disable or */ + /* dpms_off status is incorrect due to fastboot + * feature. When system resume from S4 with second + * screen only, the dpms_off would be true but + * VBIOS lit up eDP, so check link status too. + */ + if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) + core_link_disable_stream(pipe_ctx); + else if (pipe_ctx->stream_res.audio) + dc->hwss.disable_audio_stream(pipe_ctx); + + /* free acquired resources */ + if (pipe_ctx->stream_res.audio) { + /*disable az_endpoint*/ + pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); + + /*free audio*/ + if (dc->caps.dynamic_audio == true) { + /*we have to dynamic arbitrate the audio endpoints*/ + /*we free the resource, need reset is_audio_acquired*/ + update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, + pipe_ctx->stream_res.audio, false); + pipe_ctx->stream_res.audio = NULL; + } + } + } else if (pipe_ctx->stream_res.dsc) { + dp_set_dsc_enable(pipe_ctx, false); + } + + pipe_ctx->stream = NULL; + DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", + pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); +} + +void dcn31_reset_hw_ctx_wrap( + struct dc *dc, + struct dc_state *context) +{ + int i; + struct dce_hwseq *hws = dc->hwseq; + + /* Reset Back End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx_old->stream) + continue; + + if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) + continue; + + if (!pipe_ctx->stream || + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + struct clock_source *old_clk = pipe_ctx_old->clock_source; + + dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); + if (hws->funcs.enable_stream_gating) + hws->funcs.enable_stream_gating(dc, pipe_ctx); + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + } + } +} + +bool dcn31_is_abm_supported(struct dc *dc, + struct dc_state *context, struct dc_stream_state *stream) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == stream && + (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL)) + return true; + } + return false; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h new file mode 100644 index 000000000000..ff72f0fdd5be --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h @@ -0,0 +1,56 @@ +/* +* Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HWSS_DCN31_H__ +#define __DC_HWSS_DCN31_H__ + +#include "hw_sequencer_private.h" + +struct dc; + +void dcn31_init_hw(struct dc *dc); + +void dcn31_dsc_pg_control( + struct dce_hwseq *hws, + unsigned int dsc_inst, + bool power_on); + +void dcn31_enable_power_gating_plane( + struct dce_hwseq *hws, + bool enable); + +void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx); + +void dcn31_z10_restore(struct dc *dc); + +void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); +int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config); +void dcn31_reset_hw_ctx_wrap( + struct dc *dc, + struct dc_state *context); +bool dcn31_is_abm_supported(struct dc *dc, + struct dc_state *context, struct dc_stream_state *stream); + +#endif /* __DC_HWSS_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c new file mode 100644 index 000000000000..e3048f8827d2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c @@ -0,0 +1,150 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dce110/dce110_hw_sequencer.h" +#include "dcn10/dcn10_hw_sequencer.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn21/dcn21_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dcn301/dcn301_hwseq.h" +#include "dcn31/dcn31_hwseq.h" + +static const struct hw_sequencer_funcs dcn31_funcs = { + .program_gamut_remap = dcn10_program_gamut_remap, + .init_hw = dcn31_init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, + .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, + .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, + .update_plane_addr = dcn20_update_plane_addr, + .update_dchub = dcn10_update_dchub, + .update_pending_status = dcn10_update_pending_status, + .program_output_csc = dcn20_program_output_csc, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, + .update_info_frame = dcn31_update_info_frame, + .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, + .enable_stream = dcn20_enable_stream, + .disable_stream = dce110_disable_stream, + .unblank_stream = dcn20_unblank_stream, + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, + .disable_plane = dcn20_disable_plane, + .pipe_control_lock = dcn20_pipe_control_lock, + .interdependent_update_lock = dcn10_lock_all_pipes, + .cursor_lock = dcn10_cursor_lock, + .prepare_bandwidth = dcn20_prepare_bandwidth, + .optimize_bandwidth = dcn20_optimize_bandwidth, + .update_bandwidth = dcn20_update_bandwidth, + .set_drr = dcn10_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn10_set_static_screen_control, + .setup_stereo = dcn10_setup_stereo, + .set_avmute = dcn30_set_avmute, + .log_hw_state = dcn10_log_hw_state, + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_T12 = dce110_edp_wait_for_T12, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .set_cursor_position = dcn10_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, + .program_triplebuffer = dcn20_program_triple_buffer, + .enable_writeback = dcn30_enable_writeback, + .disable_writeback = dcn30_disable_writeback, + .update_writeback = dcn30_update_writeback, + .mmhubbub_warmup = dcn30_mmhubbub_warmup, + .dmdata_status_done = dcn20_dmdata_status_done, + .program_dmdata_engine = dcn30_program_dmdata_engine, + .set_dmdata_attributes = dcn20_set_dmdata_attributes, + .init_sys_ctx = dcn31_init_sys_ctx, + .init_vm_ctx = dcn20_init_vm_ctx, + .set_flip_control_gsl = dcn20_set_flip_control_gsl, + .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + .calc_vupdate_position = dcn10_calc_vupdate_position, + .apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations, + .set_backlight_level = dcn21_set_backlight_level, + .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, + .set_pipe = dcn21_set_pipe, + .z10_restore = dcn31_z10_restore, + .is_abm_supported = dcn31_is_abm_supported, + .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, +}; + +static const struct hwseq_private_funcs dcn31_private_funcs = { + .init_pipes = dcn10_init_pipes, + .update_plane_addr = dcn20_update_plane_addr, + .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_mpcc = dcn20_update_mpcc, + .set_input_transfer_func = dcn30_set_input_transfer_func, + .set_output_transfer_func = dcn30_set_output_transfer_func, + .power_down = dce110_power_down, + .enable_display_power_gating = dcn10_dummy_display_power_gating, + .blank_pixel_data = dcn20_blank_pixel_data, + .reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap, + .enable_stream_timing = dcn20_enable_stream_timing, + .edp_backlight_control = dce110_edp_backlight_control, + .disable_stream_gating = dcn20_disable_stream_gating, + .enable_stream_gating = dcn20_enable_stream_gating, + .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn20_init_blank, + .disable_vga = dcn20_disable_vga, + .bios_golden_init = dcn10_bios_golden_init, + .plane_atomic_disable = dcn20_plane_atomic_disable, + .plane_atomic_power_down = dcn10_plane_atomic_power_down, + .enable_power_gating_plane = dcn31_enable_power_gating_plane, + .hubp_pg_control = dcn31_hubp_pg_control, + .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .update_odm = dcn20_update_odm, + .dsc_pg_control = dcn31_dsc_pg_control, + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, + .wait_for_blank_complete = dcn20_wait_for_blank_complete, + .dccg_init = dcn20_dccg_init, + .set_blend_lut = dcn30_set_blend_lut, + .set_shaper_3dlut = dcn20_set_shaper_3dlut, +}; + +void dcn31_hw_sequencer_construct(struct dc *dc) +{ + dc->hwss = dcn31_funcs; + dc->hwseq->funcs = dcn31_private_funcs; + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + dc->hwss.init_hw = dcn20_fpga_init_hw; + dc->hwseq->funcs.init_pipes = NULL; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h new file mode 100644 index 000000000000..a3db08c8bd35 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h @@ -0,0 +1,33 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DCN31_INIT_H__ +#define __DC_DCN31_INIT_H__ + +struct dc; + +void dcn31_hw_sequencer_construct(struct dc *dc); + +#endif /* __DC_DCN31_INIT_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c new file mode 100644 index 000000000000..a4b1d98f0007 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c @@ -0,0 +1,287 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dcn31_optc.h" + +#include "dcn30/dcn30_optc.h" +#include "reg_helper.h" +#include "dc.h" +#include "dcn_calc_math.h" + +#define REG(reg)\ + optc1->tg_regs->reg + +#define CTX \ + optc1->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + optc1->tg_shift->field_name, optc1->tg_mask->field_name + +static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, + struct dc_crtc_timing *timing) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) + / opp_cnt; + uint32_t memory_mask = 0; + int mem_count_per_opp = (mpcc_hactive + 2559) / 2560; + + /* Assume less than 6 pipes */ + if (opp_cnt == 4) { + if (mem_count_per_opp == 1) + memory_mask = 0xf; + else { + ASSERT(mem_count_per_opp == 2); + memory_mask = 0xff; + } + } else if (mem_count_per_opp == 1) + memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); + else if (mem_count_per_opp == 2) + memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); + else if (mem_count_per_opp == 3) + memory_mask = 0x77; + else if (mem_count_per_opp == 4) + memory_mask = 0xff; + + if (REG(OPTC_MEMORY_CONFIG)) + REG_SET(OPTC_MEMORY_CONFIG, 0, + OPTC_MEM_SEL, memory_mask); + + if (opp_cnt == 2) { + REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 1, + OPTC_SEG0_SRC_SEL, opp_id[0], + OPTC_SEG1_SRC_SEL, opp_id[1]); + } else if (opp_cnt == 4) { + REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, + OPTC_NUM_OF_INPUT_SEGMENT, 3, + OPTC_SEG0_SRC_SEL, opp_id[0], + OPTC_SEG1_SRC_SEL, opp_id[1], + OPTC_SEG2_SRC_SEL, opp_id[2], + OPTC_SEG3_SRC_SEL, opp_id[3]); + } + + REG_UPDATE(OPTC_WIDTH_CONTROL, + OPTC_SEGMENT_WIDTH, mpcc_hactive); + + REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + optc1->opp_count = opp_cnt; +} + +/** + * Enable CRTC + * Enable CRTC - call ASIC Control Object to enable Timing generator. + */ +static bool optc31_enable_crtc(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ + REG_UPDATE(OPTC_DATA_SOURCE_SELECT, + OPTC_SEG0_SRC_SEL, optc->inst); + + /* VTG enable first is for HW workaround */ + REG_UPDATE(CONTROL, + VTG0_ENABLE, 1); + + REG_SEQ_START(); + + /* Enable CRTC */ + REG_UPDATE_2(OTG_CONTROL, + OTG_DISABLE_POINT_CNTL, 2, + OTG_MASTER_EN, 1); + + REG_SEQ_SUBMIT(); + REG_SEQ_WAIT_DONE(); + + return true; +} + +/* disable_crtc - call ASIC Control Object to disable Timing generator. */ +static bool optc31_disable_crtc(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + /* disable otg request until end of the first line + * in the vertical blank region + */ + REG_UPDATE(OTG_CONTROL, + OTG_MASTER_EN, 0); + + REG_UPDATE(CONTROL, + VTG0_ENABLE, 0); + + /* CRTC disabled, so disable clock. */ + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_BUSY, 0, + 1, 100000); + + return true; +} + +static bool optc31_immediate_disable_crtc(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE_2(OTG_CONTROL, + OTG_DISABLE_POINT_CNTL, 0, + OTG_MASTER_EN, 0); + + REG_UPDATE(CONTROL, + VTG0_ENABLE, 0); + + /* CRTC disabled, so disable clock. */ + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_BUSY, 0, + 1, 100000); + + return true; +} + +static void optc31_set_drr( + struct timing_generator *optc, + const struct drr_params *params) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + if (params != NULL && + params->vertical_total_max > 0 && + params->vertical_total_min > 0) { + + if (params->vertical_total_mid != 0) { + + REG_SET(OTG_V_TOTAL_MID, 0, + OTG_V_TOTAL_MID, params->vertical_total_mid - 1); + + REG_UPDATE_2(OTG_V_TOTAL_CONTROL, + OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, + OTG_VTOTAL_MID_FRAME_NUM, + (uint8_t)params->vertical_total_mid_frame_num); + + } + + optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); + + /* + * MIN_MASK_EN is gone and MASK is now always enabled. + * + * To get it to it work with manual trigger we need to make sure + * we program the correct bit. + */ + REG_UPDATE_4(OTG_V_TOTAL_CONTROL, + OTG_V_TOTAL_MIN_SEL, 1, + OTG_V_TOTAL_MAX_SEL, 1, + OTG_FORCE_LOCK_ON_EVENT, 0, + OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ + + // Setup manual flow control for EOF via TRIG_A + optc->funcs->setup_manual_trigger(optc); + + } else { + REG_UPDATE_4(OTG_V_TOTAL_CONTROL, + OTG_SET_V_TOTAL_MIN_MASK, 0, + OTG_V_TOTAL_MIN_SEL, 0, + OTG_V_TOTAL_MAX_SEL, 0, + OTG_FORCE_LOCK_ON_EVENT, 0); + + optc->funcs->set_vtotal_min_max(optc, 0, 0); + } +} + +static struct timing_generator_funcs dcn31_tg_funcs = { + .validate_timing = optc1_validate_timing, + .program_timing = optc1_program_timing, + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, + .program_global_sync = optc1_program_global_sync, + .enable_crtc = optc31_enable_crtc, + .disable_crtc = optc31_disable_crtc, + .immediate_disable_crtc = optc31_immediate_disable_crtc, + /* used by enable_timing_synchronization. Not need for FPGA */ + .is_counter_moving = optc1_is_counter_moving, + .get_position = optc1_get_position, + .get_frame_count = optc1_get_vblank_counter, + .get_scanoutpos = optc1_get_crtc_scanoutpos, + .get_otg_active_size = optc1_get_otg_active_size, + .set_early_control = optc1_set_early_control, + /* used by enable_timing_synchronization. Not need for FPGA */ + .wait_for_state = optc1_wait_for_state, + .set_blank_color = optc3_program_blank_color, + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, + .triplebuffer_lock = optc3_triplebuffer_lock, + .triplebuffer_unlock = optc2_triplebuffer_unlock, + .enable_reset_trigger = optc1_enable_reset_trigger, + .enable_crtc_reset = optc1_enable_crtc_reset, + .disable_reset_trigger = optc1_disable_reset_trigger, + .lock = optc3_lock, + .is_locked = optc1_is_locked, + .unlock = optc1_unlock, + .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, + .enable_optc_clock = optc1_enable_optc_clock, + .set_drr = optc31_set_drr, + .set_vtotal_min_max = optc1_set_vtotal_min_max, + .set_static_screen_control = optc1_set_static_screen_control, + .program_stereo = optc1_program_stereo, + .is_stereo_left_eye = optc1_is_stereo_left_eye, + .tg_init = optc3_tg_init, + .is_tg_enabled = optc1_is_tg_enabled, + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, + .clear_optc_underflow = optc1_clear_optc_underflow, + .setup_global_swap_lock = NULL, + .get_crc = optc1_get_crc, + .configure_crc = optc2_configure_crc, + .set_dsc_config = optc3_set_dsc_config, + .set_dwb_source = NULL, + .set_odm_bypass = optc3_set_odm_bypass, + .set_odm_combine = optc31_set_odm_combine, + .get_optc_source = optc2_get_optc_source, + .set_out_mux = optc3_set_out_mux, + .set_drr_trigger_window = optc3_set_drr_trigger_window, + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, + .set_gsl = optc2_set_gsl, + .set_gsl_source_select = optc2_set_gsl_source_select, + .set_vtg_params = optc1_set_vtg_params, + .program_manual_trigger = optc2_program_manual_trigger, + .setup_manual_trigger = optc2_setup_manual_trigger, + .get_hw_timing = optc1_get_hw_timing, +}; + +void dcn31_timing_generator_init(struct optc *optc1) +{ + optc1->base.funcs = &dcn31_tg_funcs; + + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; + + optc1->min_h_blank = 32; + optc1->min_v_blank = 3; + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 4; + optc1->min_v_sync_width = 1; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h new file mode 100644 index 000000000000..d8ef2f0d0c95 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h @@ -0,0 +1,259 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPTC_DCN31_H__ +#define __DC_OPTC_DCN31_H__ + +#include "dcn10/dcn10_optc.h" + +#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \ + SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ + SRI(OTG_VUPDATE_PARAM, OTG, inst),\ + SRI(OTG_VREADY_PARAM, OTG, inst),\ + SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\ + SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ + SRI(OTG_H_TOTAL, OTG, inst),\ + SRI(OTG_H_BLANK_START_END, OTG, inst),\ + SRI(OTG_H_SYNC_A, OTG, inst),\ + SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ + SRI(OTG_H_TIMING_CNTL, OTG, inst),\ + SRI(OTG_V_TOTAL, OTG, inst),\ + SRI(OTG_V_BLANK_START_END, OTG, inst),\ + SRI(OTG_V_SYNC_A, OTG, inst),\ + SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ + SRI(OTG_CONTROL, OTG, inst),\ + SRI(OTG_STEREO_CONTROL, OTG, inst),\ + SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ + SRI(OTG_STEREO_STATUS, OTG, inst),\ + SRI(OTG_V_TOTAL_MAX, OTG, inst),\ + SRI(OTG_V_TOTAL_MIN, OTG, inst),\ + SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ + SRI(OTG_TRIGA_CNTL, OTG, inst),\ + SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ + SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ + SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ + SRI(OTG_STATUS, OTG, inst),\ + SRI(OTG_STATUS_POSITION, OTG, inst),\ + SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ + SRI(OTG_M_CONST_DTO0, OTG, inst),\ + SRI(OTG_M_CONST_DTO1, OTG, inst),\ + SRI(OTG_CLOCK_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ + SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ + SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ + SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ + SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ + SRI(CONTROL, VTG, inst),\ + SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ + SRI(OTG_GSL_CONTROL, OTG, inst),\ + SRI(OTG_CRC_CNTL, OTG, inst),\ + SRI(OTG_CRC0_DATA_RG, OTG, inst),\ + SRI(OTG_CRC0_DATA_B, OTG, inst),\ + SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ + SR(GSL_SOURCE_SELECT),\ + SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ + SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ + SRI(OTG_GSL_WINDOW_X, OTG, inst),\ + SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ + SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ + SRI(OTG_DSC_START_POSITION, OTG, inst),\ + SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\ + SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\ + SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ + SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ + SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ + SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ + SRI(OTG_CRC_CNTL2, OTG, inst),\ + SR(DWB_SOURCE_SELECT) + +#define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\ + SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ + SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ + SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ + SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ + SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ + SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ + SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ + SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ + SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ + SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ + SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ + SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh) + +void dcn31_timing_generator_init(struct optc *optc1); + +#endif /* __DC_OPTC_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c new file mode 100644 index 000000000000..7db268da6976 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c @@ -0,0 +1,157 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "reg_helper.h" +#include "core_types.h" +#include "dc_dmub_srv.h" +#include "dcn31_panel_cntl.h" +#include "atom.h" + +#define TO_DCN31_PANEL_CNTL(panel_cntl)\ + container_of(panel_cntl, struct dcn31_panel_cntl, base) + +#define CTX \ + dcn31_panel_cntl->base.ctx + +#define DC_LOGGER \ + dcn31_panel_cntl->base.ctx->logger + +static bool dcn31_query_backlight_info(struct panel_cntl *panel_cntl, union dmub_rb_cmd *cmd) +{ + struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl); + struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv; + + if (!dc_dmub_srv) + return false; + + memset(cmd, 0, sizeof(*cmd)); + cmd->panel_cntl.header.type = DMUB_CMD__PANEL_CNTL; + cmd->panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO; + cmd->panel_cntl.header.payload_bytes = sizeof(cmd->panel_cntl.data); + cmd->panel_cntl.data.inst = dcn31_panel_cntl->base.inst; + + return dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, cmd); +} + +static uint32_t dcn31_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl) +{ + union dmub_rb_cmd cmd; + + if (!dcn31_query_backlight_info(panel_cntl, &cmd)) + return 0; + + return cmd.panel_cntl.data.current_backlight; +} + +uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl) +{ + struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl); + struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv; + union dmub_rb_cmd cmd; + + if (!dc_dmub_srv) + return 0; + + memset(&cmd, 0, sizeof(cmd)); + cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL; + cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_HW_INIT; + cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data); + cmd.panel_cntl.data.inst = dcn31_panel_cntl->base.inst; + cmd.panel_cntl.data.bl_pwm_cntl = panel_cntl->stored_backlight_registers.BL_PWM_CNTL; + cmd.panel_cntl.data.bl_pwm_period_cntl = panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL; + cmd.panel_cntl.data.bl_pwm_ref_div1 = + panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; + + if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, &cmd)) + return 0; + + panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl; + panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */ + panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl; + panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = + cmd.panel_cntl.data.bl_pwm_ref_div1; + + return cmd.panel_cntl.data.current_backlight; +} + +void dcn31_panel_cntl_destroy(struct panel_cntl **panel_cntl) +{ + struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(*panel_cntl); + + kfree(dcn31_panel_cntl); + *panel_cntl = NULL; +} + +bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl) +{ + union dmub_rb_cmd cmd; + + if (!dcn31_query_backlight_info(panel_cntl, &cmd)) + return 0; + + return cmd.panel_cntl.data.is_backlight_on; +} + +bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl) +{ + union dmub_rb_cmd cmd; + + if (!dcn31_query_backlight_info(panel_cntl, &cmd)) + return 0; + + return cmd.panel_cntl.data.is_powered_on; +} + +void dcn31_store_backlight_level(struct panel_cntl *panel_cntl) +{ + union dmub_rb_cmd cmd; + + if (!dcn31_query_backlight_info(panel_cntl, &cmd)) + return; + + panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl; + panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */ + panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl; + panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = + cmd.panel_cntl.data.bl_pwm_ref_div1; +} + +static const struct panel_cntl_funcs dcn31_link_panel_cntl_funcs = { + .destroy = dcn31_panel_cntl_destroy, + .hw_init = dcn31_panel_cntl_hw_init, + .is_panel_backlight_on = dcn31_is_panel_backlight_on, + .is_panel_powered_on = dcn31_is_panel_powered_on, + .store_backlight_level = dcn31_store_backlight_level, + .get_current_backlight = dcn31_get_16_bit_backlight_from_pwm, +}; + +void dcn31_panel_cntl_construct( + struct dcn31_panel_cntl *dcn31_panel_cntl, + const struct panel_cntl_init_data *init_data) +{ + dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs; + dcn31_panel_cntl->base.ctx = init_data->ctx; + dcn31_panel_cntl->base.inst = init_data->inst; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h new file mode 100644 index 000000000000..d33ccd6ef8c3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h @@ -0,0 +1,40 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_PANEL_CNTL__DCN31_H__ +#define __DC_PANEL_CNTL__DCN31_H__ + +#include "panel_cntl.h" +#include "dce/dce_panel_cntl.h" + +struct dcn31_panel_cntl { + struct panel_cntl base; +}; + +void dcn31_panel_cntl_construct( + struct dcn31_panel_cntl *dcn31_panel_cntl, + const struct panel_cntl_init_data *init_data); + +#endif /* __DC_PANEL_CNTL__DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c new file mode 100644 index 000000000000..c67bc9544f5d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -0,0 +1,2195 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#include "dm_services.h" +#include "dc.h" + +#include "dcn31/dcn31_init.h" + +#include "resource.h" +#include "include/irq_service_interface.h" +#include "dcn31_resource.h" + +#include "dcn20/dcn20_resource.h" +#include "dcn30/dcn30_resource.h" + +#include "dcn10/dcn10_ipp.h" +#include "dcn30/dcn30_hubbub.h" +#include "dcn31/dcn31_hubbub.h" +#include "dcn30/dcn30_mpc.h" +#include "dcn31/dcn31_hubp.h" +#include "irq/dcn31/irq_service_dcn31.h" +#include "dcn30/dcn30_dpp.h" +#include "dcn31/dcn31_optc.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dce110/dce110_hw_sequencer.h" +#include "dcn30/dcn30_opp.h" +#include "dcn20/dcn20_dsc.h" +#include "dcn30/dcn30_vpg.h" +#include "dcn30/dcn30_afmt.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_audio.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "virtual/virtual_stream_encoder.h" +#include "dce110/dce110_resource.h" +#include "dml/display_mode_vba.h" +#include "dcn31/dcn31_dccg.h" +#include "dcn10/dcn10_resource.h" +#include "dcn31_panel_cntl.h" + +#include "dcn30/dcn30_dwb.h" +#include "dcn30/dcn30_mmhubbub.h" + +// TODO: change include headers /amd/include/asic_reg after upstream +#include "yellow_carp_offset.h" +#include "dcn/dcn_3_1_2_offset.h" +#include "dcn/dcn_3_1_2_sh_mask.h" +#include "nbio/nbio_7_2_0_offset.h" +#include "dpcs/dpcs_4_2_0_offset.h" +#include "dpcs/dpcs_4_2_0_sh_mask.h" +#include "mmhub/mmhub_2_3_0_offset.h" +#include "mmhub/mmhub_2_3_0_sh_mask.h" + + +#define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 +#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L + +#include "reg_helper.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "dce/dce_aux.h" +#include "dce/dce_i2c.h" + +#include "dml/dcn30/display_mode_vba_30.h" +#include "vm_helper.h" +#include "dcn20/dcn20_vmid.h" + +#include "link_enc_cfg.h" + +#define DC_LOGGER_INIT(logger) +#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) +#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) + +#define DCN3_1_DEFAULT_DET_SIZE 384 + +struct _vcs_dpi_ip_params_st dcn3_1_ip = { + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 1, + .hostvm_max_page_table_levels = 2, + .rob_buffer_size_kbytes = 64, + .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE, + .config_return_buffer_size_in_kbytes = 1792, + .compressed_buffer_segment_size_in_kbytes = 64, + .meta_fifo_size_in_kentries = 32, + .zero_size_buffer_entries = 512, + .compbuf_reserved_space_64b = 256, + .compbuf_reserved_space_zs = 64, + .dpp_output_buffer_pixels = 2560, + .opp_output_buffer_lines = 1, + .pixel_chunk_size_kbytes = 8, + .meta_chunk_size_kbytes = 2, + .min_meta_chunk_size_bytes = 256, + .writeback_chunk_size_kbytes = 8, + .ptoi_supported = false, + .num_dsc = 3, + .maximum_dsc_bits_per_component = 10, + .dsc422_native_support = false, + .is_line_buffer_bpp_fixed = true, + .line_buffer_fixed_bpp = 48, + .line_buffer_size_bits = 789504, + .max_line_buffer_lines = 12, + .writeback_interface_buffer_size_kbytes = 90, + .max_num_dpp = 4, + .max_num_otg = 4, + .max_num_hdmi_frl_outputs = 1, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dpte_buffer_size_in_pte_reqs_luma = 64, + .dpte_buffer_size_in_pte_reqs_chroma = 34, + .dispclk_ramp_margin_percent = 1, + .max_inter_dcn_tile_repeaters = 8, + .cursor_buffer_size = 16, + .cursor_chunk_size = 2, + .writeback_line_buffer_buffer_size = 0, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .dppclk_delay_subtotal = 46, + .dppclk_delay_scl = 50, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_cnvc_formatter = 27, + .dppclk_delay_cnvc_cursor = 6, + .dispclk_delay_subtotal = 119, + .dynamic_metadata_vm_enabled = false, + .odm_combine_4to1_supported = false, + .dcc_supported = true, +}; + +struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { + /*TODO: correct dispclk/dppclk voltage level determination*/ + .clock_limits = { + { + .state = 0, + .dispclk_mhz = 1200.0, + .dppclk_mhz = 1200.0, + .phyclk_mhz = 600.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 186.0, + .dtbclk_mhz = 625.0, + }, + { + .state = 1, + .dispclk_mhz = 1200.0, + .dppclk_mhz = 1200.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 209.0, + .dtbclk_mhz = 625.0, + }, + { + .state = 2, + .dispclk_mhz = 1200.0, + .dppclk_mhz = 1200.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 209.0, + .dtbclk_mhz = 625.0, + }, + { + .state = 3, + .dispclk_mhz = 1200.0, + .dppclk_mhz = 1200.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 371.0, + .dtbclk_mhz = 625.0, + }, + { + .state = 4, + .dispclk_mhz = 1200.0, + .dppclk_mhz = 1200.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .dscclk_mhz = 417.0, + .dtbclk_mhz = 625.0, + }, + }, + .num_states = 5, + .sr_exit_time_us = 9.0, + .sr_enter_plus_exit_time_us = 11.0, + .sr_exit_z8_time_us = 402.0, + .sr_enter_plus_exit_z8_time_us = 520.0, + .writeback_latency_us = 12.0, + .round_trip_ping_latency_dcfclk_cycles = 106, + .urgent_latency_pixel_data_only_us = 4.0, + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, + .urgent_latency_vm_data_only_us = 4.0, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + .pct_ideal_sdp_bw_after_urgent = 80.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, + .max_avg_sdp_bw_use_normal_percent = 60.0, + .max_avg_dram_bw_use_normal_percent = 60.0, + .fabric_datapath_to_dcn_data_return_bytes = 32, + .return_bus_width_bytes = 64, + .downspread_percent = 0.38, + .dcn_downspread_percent = 0.5, + .gpuvm_min_page_size_bytes = 4096, + .hostvm_min_page_size_bytes = 4096, + .do_urgent_latency_adjustment = false, + .urgent_latency_adjustment_fabric_clock_component_us = 0, + .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, +}; + +enum dcn31_clk_src_array_id { + DCN31_CLK_SRC_PLL0, + DCN31_CLK_SRC_PLL1, + DCN31_CLK_SRC_PLL2, + DCN31_CLK_SRC_PLL3, + DCN31_CLK_SRC_PLL4, + DCN30_CLK_SRC_TOTAL +}; + +/* begin ********************* + * macros to expend register list macro defined in HW object header file + */ + +/* DCN */ +/* TODO awful hack. fixup dcn20_dwb.h */ +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRI(reg_name, block, id)\ + .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRI2(reg_name, block, id)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define SRIR(var_name, reg_name, block, id)\ + .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_MPC_RMU(reg_name, block, id)\ + .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRII_DWB(reg_name, temp_name, block, id)\ + .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## temp_name + +#define DCCG_SRII(reg_name, block, id)\ + .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define VUPDATE_SRII(reg_name, block, id)\ + .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ + reg ## reg_name ## _ ## block ## id + +/* NBIO */ +#define NBIO_BASE_INNER(seg) \ + NBIO_BASE__INST0_SEG ## seg + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name)\ + .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ + regBIF_BX1_ ## reg_name + +/* MMHUB */ +#define MMHUB_BASE_INNER(seg) \ + MMHUB_BASE__INST0_SEG ## seg + +#define MMHUB_BASE(seg) \ + MMHUB_BASE_INNER(seg) + +#define MMHUB_SR(reg_name)\ + .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ + mm ## reg_name + +/* CLOCK */ +#define CLK_BASE_INNER(seg) \ + CLK_BASE__INST0_SEG ## seg + +#define CLK_BASE(seg) \ + CLK_BASE_INNER(seg) + +#define CLK_SRI(reg_name, block, inst)\ + .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## _ ## inst ## _ ## reg_name + + +static const struct bios_registers bios_regs = { + NBIO_SR(BIOS_SCRATCH_3), + NBIO_SR(BIOS_SCRATCH_6) +}; + +#define clk_src_regs(index, pllid)\ +[index] = {\ + CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ +} + +static const struct dce110_clk_src_regs clk_src_regs[] = { + clk_src_regs(0, A), + clk_src_regs(1, B), + clk_src_regs(2, C), + clk_src_regs(3, D), + clk_src_regs(4, E) +}; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) +}; + +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) +}; + +#define abm_regs(id)\ +[id] = {\ + ABM_DCN301_REG_LIST(id)\ +} + +static const struct dce_abm_registers abm_regs[] = { + abm_regs(0), + abm_regs(1), + abm_regs(2), + abm_regs(3), +}; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN30(_MASK) +}; + +#define audio_regs(id)\ +[id] = {\ + AUD_COMMON_REG_LIST(id)\ +} + +static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), + audio_regs(3), + audio_regs(4), + audio_regs(5), + audio_regs(6) +}; + +#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) + +static const struct dce_audio_shift audio_shift = { + DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +#define vpg_regs(id)\ +[id] = {\ + VPG_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_vpg_registers vpg_regs[] = { + vpg_regs(0), + vpg_regs(1), + vpg_regs(2), + vpg_regs(3), + vpg_regs(4), + vpg_regs(5), + vpg_regs(6), + vpg_regs(7), + vpg_regs(8), + vpg_regs(9), +}; + +static const struct dcn30_vpg_shift vpg_shift = { + DCN3_VPG_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_vpg_mask vpg_mask = { + DCN3_VPG_MASK_SH_LIST(_MASK) +}; + +#define afmt_regs(id)\ +[id] = {\ + AFMT_DCN3_REG_LIST(id)\ +} + +static const struct dcn30_afmt_registers afmt_regs[] = { + afmt_regs(0), + afmt_regs(1), + afmt_regs(2), + afmt_regs(3), + afmt_regs(4), + afmt_regs(5) +}; + +static const struct dcn30_afmt_shift afmt_shift = { + DCN3_AFMT_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn30_afmt_mask afmt_mask = { + DCN3_AFMT_MASK_SH_LIST(_MASK) +}; + +#define stream_enc_regs(id)\ +[id] = {\ + SE_DCN3_REG_LIST(id)\ +} + +static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(0), + stream_enc_regs(1), + stream_enc_regs(2), + stream_enc_regs(3), + stream_enc_regs(4) +}; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + + +#define aux_regs(id)\ +[id] = {\ + DCN2_AUX_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { + aux_regs(0), + aux_regs(1), + aux_regs(2), + aux_regs(3), + aux_regs(4) +}; + +#define hpd_regs(id)\ +[id] = {\ + HPD_REG_LIST(id)\ +} + +static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4) +}; + +#define link_regs(id, phyid)\ +[id] = {\ + LE_DCN31_REG_LIST(id), \ + UNIPHY_DCN2_REG_LIST(phyid), \ + DPCS_DCN31_REG_LIST(id), \ +} + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK) +}; + +static const struct dcn10_link_enc_registers link_enc_regs[] = { + link_regs(0, A), + link_regs(1, B), + link_regs(2, C), + link_regs(3, D), + link_regs(4, E) +}; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ + DPCS_DCN31_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ + DPCS_DCN31_MASK_SH_LIST(_MASK) +}; + +#define dpp_regs(id)\ +[id] = {\ + DPP_REG_LIST_DCN30(id),\ +} + +static const struct dcn3_dpp_registers dpp_regs[] = { + dpp_regs(0), + dpp_regs(1), + dpp_regs(2), + dpp_regs(3) +}; + +static const struct dcn3_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) +}; + +static const struct dcn3_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN30(_MASK) +}; + +#define opp_regs(id)\ +[id] = {\ + OPP_REG_LIST_DCN30(id),\ +} + +static const struct dcn20_opp_registers opp_regs[] = { + opp_regs(0), + opp_regs(1), + opp_regs(2), + opp_regs(3) +}; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT) +}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK) +}; + +#define aux_engine_regs(id)\ +[id] = {\ + AUX_COMMON_REG_LIST0(id), \ + .AUXN_IMPCAL = 0, \ + .AUXP_IMPCAL = 0, \ + .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ +} + +static const struct dce110_aux_registers aux_engine_regs[] = { + aux_engine_regs(0), + aux_engine_regs(1), + aux_engine_regs(2), + aux_engine_regs(3), + aux_engine_regs(4) +}; + +#define dwbc_regs_dcn3(id)\ +[id] = {\ + DWBC_COMMON_REG_LIST_DCN30(id),\ +} + +static const struct dcn30_dwbc_registers dwbc30_regs[] = { + dwbc_regs_dcn3(0), +}; + +static const struct dcn30_dwbc_shift dwbc30_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_dwbc_mask dwbc30_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +#define mcif_wb_regs_dcn3(id)\ +[id] = {\ + MCIF_WB_COMMON_REG_LIST_DCN30(id),\ +} + +static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { + mcif_wb_regs_dcn3(0) +}; + +static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +#define dsc_regsDCN20(id)\ +[id] = {\ + DSC_REG_LIST_DCN20(id)\ +} + +static const struct dcn20_dsc_registers dsc_regs[] = { + dsc_regsDCN20(0), + dsc_regsDCN20(1), + dsc_regsDCN20(2) +}; + +static const struct dcn20_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) +}; + +static const struct dcn20_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN20(_MASK) +}; + +static const struct dcn30_mpc_registers mpc_regs = { + MPC_REG_LIST_DCN3_0(0), + MPC_REG_LIST_DCN3_0(1), + MPC_REG_LIST_DCN3_0(2), + MPC_REG_LIST_DCN3_0(3), + MPC_OUT_MUX_REG_LIST_DCN3_0(0), + MPC_OUT_MUX_REG_LIST_DCN3_0(1), + MPC_OUT_MUX_REG_LIST_DCN3_0(2), + MPC_OUT_MUX_REG_LIST_DCN3_0(3), + MPC_RMU_GLOBAL_REG_LIST_DCN3AG, + MPC_RMU_REG_LIST_DCN3AG(0), + MPC_RMU_REG_LIST_DCN3AG(1), + //MPC_RMU_REG_LIST_DCN3AG(2), + MPC_DWB_MUX_REG_LIST_DCN3_0(0), +}; + +static const struct dcn30_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dcn30_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +#define optc_regs(id)\ +[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} + +static const struct dcn_optc_registers optc_regs[] = { + optc_regs(0), + optc_regs(1), + optc_regs(2), + optc_regs(3) +}; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) +}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) +}; + +#define hubp_regs(id)\ +[id] = {\ + HUBP_REG_LIST_DCN30(id)\ +} + +static const struct dcn_hubp2_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1), + hubp_regs(2), + hubp_regs(3) +}; + + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN31(__SHIFT) +}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN31(_MASK) +}; +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN31(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN31(_MASK) +}; + +static const struct dccg_registers dccg_regs = { + DCCG_REG_LIST_DCN31() +}; + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN31(__SHIFT) +}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN31(_MASK) +}; + + +#define SRII2(reg_name_pre, reg_name_post, id)\ + .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ + ## id ## _ ## reg_name_post ## _BASE_IDX) + \ + reg ## reg_name_pre ## id ## _ ## reg_name_post + + +#define HWSEQ_DCN31_REG_LIST()\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DIO_MEM_PWR_CTRL), \ + SR(ODM_MEM_PWR_CTRL3), \ + SR(DMU_MEM_PWR_CNTL), \ + SR(MMHUBBUB_MEM_PWR_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ + SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_GB), \ + SR(MPC_CRC_RESULT_C), \ + SR(MPC_CRC_RESULT_AR), \ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL), \ + SR(D5VGA_CONTROL), \ + SR(D6VGA_CONTROL), \ + SR(DC_IP_REQUEST_CNTL), \ + SR(AZALIA_AUDIO_DTO), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING) + +static const struct dce_hwseq_registers hwseq_reg = { + HWSEQ_DCN31_REG_LIST() +}; + +#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ + HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ + HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN31_MASK_SH_LIST(_MASK) +}; +#define vmid_regs(id)\ +[id] = {\ + DCN20_VMID_REG_LIST(id)\ +} + +static const struct dcn_vmid_registers vmid_regs[] = { + vmid_regs(0), + vmid_regs(1), + vmid_regs(2), + vmid_regs(3), + vmid_regs(4), + vmid_regs(5), + vmid_regs(6), + vmid_regs(7), + vmid_regs(8), + vmid_regs(9), + vmid_regs(10), + vmid_regs(11), + vmid_regs(12), + vmid_regs(13), + vmid_regs(14), + vmid_regs(15) +}; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT) +}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) +}; + +static const struct resource_caps res_cap_dcn31 = { + .num_timing_generator = 4, + .num_opp = 4, + .num_video_plane = 4, + .num_audio = 5, + .num_stream_encoder = 5, + .num_dig_link_enc = 5, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 16, + .num_mpc_3dlut = 2, + .num_dsc = 3, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .blends_with_above = true, + .blends_with_below = true, + .per_pixel_alpha = true, + + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = false, + .ayuv = false, + }, + + .max_upscale_factor = { + .argb8888 = 16000, + .nv12 = 16000, + .fp16 = 16000 + }, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = { + .argb8888 = 167, + .nv12 = 167, + .fp16 = 167 + }, + 64, + 64 +}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = false, + .pipe_split_policy = MPC_SPLIT_AVOID, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 7680,/*upto 8K*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .pstate_enabled = true, + .use_max_lb = true, + .enable_mem_low_power = { + .bits = { + .vga = false, + .i2c = false, + .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled + .dscl = false, + .cm = false, + .mpc = false, + .optc = false, + } + }, + .optimize_edp_link_rate = true, + .enable_sw_cntl_psr = true, +}; + +static const struct dc_debug_options debug_defaults_diags = { + .disable_dmcu = true, + .force_abm_enable = false, + .timing_trace = true, + .clock_trace = true, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_clock_gate = true, + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = true, + .disable_stutter = false, + .scl_reset_length10 = true, + .dwb_fi_phase = -1, // -1 = disable + .dmub_command_table = true, + .enable_tri_buf = true, + .use_max_lb = true +}; + +static void dcn31_dpp_destroy(struct dpp **dpp) +{ + kfree(TO_DCN20_DPP(*dpp)); + *dpp = NULL; +} + +static struct dpp *dcn31_dpp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn3_dpp *dpp = + kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); + + if (!dpp) + return NULL; + + if (dpp3_construct(dpp, ctx, inst, + &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp); + return NULL; +} + +static struct output_pixel_processor *dcn31_opp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp = + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn20_opp_construct(opp, ctx, inst, + &opp_regs[inst], &opp_shift, &opp_mask); + return &opp->base; +} + +static struct dce_aux *dcn31_aux_engine_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, + &aux_shift, + ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } + +static const struct dce_i2c_registers i2c_hw_regs[] = { + i2c_inst_regs(1), + i2c_inst_regs(2), + i2c_inst_regs(3), + i2c_inst_regs(4), + i2c_inst_regs(5), +}; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) +}; + +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) +}; + +static struct dce_i2c_hw *dcn31_i2c_hw_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, + &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} +static struct mpc *dcn31_mpc_create( + struct dc_context *ctx, + int num_mpcc, + int num_rmu) +{ + struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), + GFP_KERNEL); + + if (!mpc30) + return NULL; + + dcn30_mpc_construct(mpc30, ctx, + &mpc_regs, + &mpc_shift, + &mpc_mask, + num_mpcc, + num_rmu); + + return &mpc30->base; +} + +static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), + GFP_KERNEL); + + if (!hubbub3) + return NULL; + + hubbub31_construct(hubbub3, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask, + dcn3_1_ip.det_buffer_size_kbytes, + dcn3_1_ip.pixel_chunk_size_kbytes, + dcn3_1_ip.config_return_buffer_size_in_kbytes); + + + for (i = 0; i < res_cap_dcn31.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub3->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub3->base; +} + +static struct timing_generator *dcn31_timing_generator_create( + struct dc_context *ctx, + uint32_t instance) +{ + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; + + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn31_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true +}; + +static struct link_encoder *dcn31_link_encoder_create( + const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20) + return NULL; + + dcn31_link_encoder_construct(enc20, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], + &le_shift, + &le_mask); + + return &enc20->enc10.base; +} + +/* Create a minimal link encoder object not associated with a particular + * physical connector. + * resource_funcs.link_enc_create_minimal + */ +static struct link_encoder *dcn31_link_enc_create_minimal( + struct dc_context *ctx, enum engine_id eng_id) +{ + struct dcn20_link_encoder *enc20; + + if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + return NULL; + + enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + if (!enc20) + return NULL; + + dcn31_link_encoder_construct_minimal( + enc20, + ctx, + &link_enc_feature, + &link_enc_regs[eng_id - ENGINE_ID_DIGA], + eng_id); + + return &enc20->enc10.base; +} + +struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) +{ + struct dcn31_panel_cntl *panel_cntl = + kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); + + if (!panel_cntl) + return NULL; + + dcn31_panel_cntl_construct(panel_cntl, init_data); + + return &panel_cntl->base; +} + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); + +} + +static struct audio *dcn31_create_audio( + struct dc_context *ctx, unsigned int inst) +{ + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct vpg *dcn31_vpg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); + + if (!vpg3) + return NULL; + + vpg3_construct(vpg3, ctx, inst, + &vpg_regs[inst], + &vpg_shift, + &vpg_mask); + + return &vpg3->base; +} + +static struct afmt *dcn31_afmt_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); + + if (!afmt3) + return NULL; + + afmt3_construct(afmt3, ctx, inst, + &afmt_regs[inst], + &afmt_shift, + &afmt_mask); + + return &afmt3->base; +} + +static struct stream_encoder *dcn31_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct afmt *afmt; + int vpg_inst; + int afmt_inst; + + /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGF) { + vpg_inst = eng_id; + afmt_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn31_vpg_create(ctx, vpg_inst); + afmt = dcn31_afmt_create(ctx, afmt_inst); + + if (!enc1 || !vpg || !afmt) + return NULL; + + dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, + eng_id, vpg, afmt, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + + return &enc1->base; +} + +static struct dce_hwseq *dcn31_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + return hws; +} +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn31_create_audio, + .create_stream_encoder = dcn31_stream_encoder_create, + .create_hwseq = dcn31_hwseq_create, +}; + +static const struct resource_create_funcs res_create_maximus_funcs = { + .read_dce_straps = NULL, + .create_audio = NULL, + .create_stream_encoder = NULL, + .create_hwseq = dcn31_hwseq_create, +}; + +static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) { + if (pool->base.stream_enc[i]->vpg != NULL) { + kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); + pool->base.stream_enc[i]->vpg = NULL; + } + if (pool->base.stream_enc[i]->afmt != NULL) { + kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); + pool->base.stream_enc[i]->afmt = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); + pool->base.stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn20_dsc_destroy(&pool->base.dscs[i]); + } + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); + pool->base.mpc = NULL; + } + if (pool->base.hubbub != NULL) { + kfree(pool->base.hubbub); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.dpps[i] != NULL) + dcn31_dpp_destroy(&pool->base.dpps[i]); + + if (pool->base.ipps[i] != NULL) + pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; + } + + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + if (pool->base.engines[i] != NULL) + dce110_engine_destroy(&pool->base.engines[i]); + if (pool->base.hw_i2cs[i] != NULL) { + kfree(pool->base.hw_i2cs[i]); + pool->base.hw_i2cs[i] = NULL; + } + if (pool->base.sw_i2cs[i] != NULL) { + kfree(pool->base.sw_i2cs[i]); + pool->base.sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + if (pool->base.opps[i] != NULL) + pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + if (pool->base.dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); + pool->base.dwbc[i] = NULL; + } + if (pool->base.mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); + pool->base.mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i]) + dce_aud_destroy(&pool->base.audios[i]); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dcn20_clock_source_destroy(&pool->base.clock_sources[i]); + pool->base.clock_sources[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + if (pool->base.mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->base.mpc_lut[i]); + pool->base.mpc_lut[i] = NULL; + } + if (pool->base.mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->base.mpc_shaper[i]); + pool->base.mpc_shaper[i] = NULL; + } + } + + if (pool->base.dp_clock_source != NULL) { + dcn20_clock_source_destroy(&pool->base.dp_clock_source); + pool->base.dp_clock_source = NULL; + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.multiple_abms[i] != NULL) + dce_abm_destroy(&pool->base.multiple_abms[i]); + } + + if (pool->base.psr != NULL) + dmub_psr_destroy(&pool->base.psr); + + if (pool->base.dccg != NULL) + dcn_dccg_destroy(&pool->base.dccg); +} + +static struct hubp *dcn31_hubp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn20_hubp *hubp2 = + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + + if (hubp31_construct(hubp2, ctx, inst, + &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} + +static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), + GFP_KERNEL); + + if (!dwbc30) { + dm_error("DC: failed to create dwbc30!\n"); + return false; + } + + dcn30_dwbc_construct(dwbc30, ctx, + &dwbc30_regs[i], + &dwbc30_shift, + &dwbc30_mask, + i); + + pool->dwbc[i] = &dwbc30->base; + } + return true; +} + +static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), + GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + + dcn30_mmhubbub_construct(mcif_wb30, ctx, + &mcif_wb30_regs[i], + &mcif_wb30_shift, + &mcif_wb30_mask, + i); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +static struct display_stream_compressor *dcn31_dsc_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_dsc *dsc = + kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + return &dsc->base; +} + +static void dcn31_destroy_resource_pool(struct resource_pool **pool) +{ + struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); + + dcn31_resource_destruct(dcn31_pool); + kfree(dcn31_pool); + *pool = NULL; +} + +static struct clock_source *dcn31_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +static bool is_dual_plane(enum surface_pixel_format format) +{ + return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; +} + +static int dcn31_populate_dml_pipes_from_context( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + bool fast_validate) +{ + int i, pipe_cnt; + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + + dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); + + for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { + struct dc_crtc_timing *timing; + + if (!res_ctx->pipe_ctx[i].stream) + continue; + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + + pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; + pipes[pipe_cnt].pipe.src.gpuvm = true; + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; + pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; + pipes[pipe_cnt].pipe.src.dcc_rate = 3; + pipes[pipe_cnt].dout.dsc_input_bpc = 0; + + if (pipes[pipe_cnt].dout.dsc_enable) { + switch (timing->display_color_depth) { + case COLOR_DEPTH_888: + pipes[pipe_cnt].dout.dsc_input_bpc = 8; + break; + case COLOR_DEPTH_101010: + pipes[pipe_cnt].dout.dsc_input_bpc = 10; + break; + case COLOR_DEPTH_121212: + pipes[pipe_cnt].dout.dsc_input_bpc = 12; + break; + default: + ASSERT(0); + break; + } + } + + pipe_cnt++; + } + context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; + dc->config.enable_4to1MPC = false; + if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { + if (is_dual_plane(pipe->plane_state->format) + && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { + dc->config.enable_4to1MPC = true; + } else if (!is_dual_plane(pipe->plane_state->format)) { + context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; + pipes[0].pipe.src.unbounded_req_mode = true; + } + } + + return pipe_cnt; +} + +static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) +{ + if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; + } +} + +static void dcn31_calculate_wm_and_dlg_fp( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel) +{ + int i, pipe_idx; + double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + + if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) + dcfclk = context->bw_ctx.dml.soc.min_dcfclk; + + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; + +#if 0 // TODO + /* Set B: + * TODO + */ + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { + if (vlevel == 0) { + pipes[0].clks_cfg.voltage = 1; + pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; + } + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; + + /* Set C: + * TODO + */ + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + + /* Set D: + * TODO + */ + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; + } + context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; +#endif + + /* Set A: + * All clocks min required + * + * Set A calculated last so that following calculations are based on Set A + */ + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + /* TODO: remove: */ + context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; + context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; + context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; + /* end remove*/ + + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; + + pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); + pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + + if (dc->config.forced_clocks) { + pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; + pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; + } + if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; + if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) + pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; + + pipe_idx++; + } + + dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); +} + +static void dcn31_calculate_wm_and_dlg( + struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel) +{ + DC_FP_START(); + dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); + DC_FP_END(); +} + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap +}; + +static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + struct clk_limit_table *clk_table = &bw_params->clk_table; + struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; + unsigned int i, closest_clk_lvl; + int j; + + // Default clock levels are used for diags, which may lead to overclocking. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + + dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; + dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; + dcn3_1_soc.num_chans = bw_params->num_channels; + + ASSERT(clk_table->num_entries); + + /* Prepass to find max clocks independent of voltage level. */ + for (i = 0; i < clk_table->num_entries; ++i) { + if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; + if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; + } + + for (i = 0; i < clk_table->num_entries; i++) { + /* loop backwards*/ + for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { + if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { + closest_clk_lvl = j; + break; + } + } + + clock_limits[i].state = i; + + /* Clocks dependent on voltage level. */ + clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; + clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; + clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; + clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; + + /* Clocks independent of voltage level. */ + clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + + clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + + clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + } + for (i = 0; i < clk_table->num_entries; i++) + dcn3_1_soc.clock_limits[i] = clock_limits[i]; + if (clk_table->num_entries) { + dcn3_1_soc.num_states = clk_table->num_entries; + } + } + + dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) + dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); + else + dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA); +} + +static struct resource_funcs dcn31_res_pool_funcs = { + .destroy = dcn31_destroy_resource_pool, + .link_enc_create = dcn31_link_encoder_create, + .link_enc_create_minimal = dcn31_link_enc_create_minimal, + .link_encs_assign = link_enc_cfg_link_encs_assign, + .link_enc_unassign = link_enc_cfg_link_enc_unassign, + .panel_cntl_create = dcn31_panel_cntl_create, + .validate_bandwidth = dcn30_validate_bandwidth, + .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, + .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, + .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn31_update_bw_bounding_box, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, +}; + +static struct clock_source *dcn30_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn3_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + BREAK_TO_DEBUGGER(); + return NULL; +} + +static bool dcn31_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct dcn31_resource_pool *pool) +{ + int i; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + + DC_FP_START(); + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = &res_cap_dcn31; + + pool->base.funcs = &dcn31_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = pool->base.res_cap->num_timing_generator; + pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ + dc->caps.max_cursor_size = 256; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; + + dc->caps.max_slave_planes = 1; + dc->caps.max_slave_yuv_planes = 1; + dc->caps.max_slave_rgb_planes = 1; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + dc->caps.is_apu = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 1; + dc->caps.color.dpp.ogam_ram = 1; + // no OGAM ROM on DCN301 + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { + dc->debug = debug_defaults_diags; + } else + dc->debug = debug_defaults_diags; + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = + dcn30_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = + dcn30_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = + dcn30_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); + pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = + dcn30_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = + dcn30_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); + + pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->base.dp_clock_source = + dcn31_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* TODO: DCCG */ + pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->base.dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* TODO: IRQ */ + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dcn31_create(&init_data); + if (!pool->base.irqs) + goto create_fail; + + /* HUBBUB */ + pool->base.hubbub = dcn31_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs and TGs */ + for (i = 0; i < pool->base.pipe_count; i++) { + pool->base.hubps[i] = dcn31_hubp_create(ctx, i); + if (pool->base.hubps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create hubps!\n"); + goto create_fail; + } + + pool->base.dpps[i] = dcn31_dpp_create(ctx, i); + if (pool->base.dpps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create dpps!\n"); + goto create_fail; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + pool->base.opps[i] = dcn31_opp_create(ctx, i); + if (pool->base.opps[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto create_fail; + } + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + pool->base.timing_generators[i] = dcn31_timing_generator_create( + ctx, i); + if (pool->base.timing_generators[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + } + pool->base.timing_generator_count = i; + + /* PSR */ + pool->base.psr = dmub_psr_create(ctx); + if (pool->base.psr == NULL) { + dm_error("DC: failed to create psr obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* ABM */ + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + pool->base.multiple_abms[i] = dmub_abm_create(ctx, + &abm_regs[i], + &abm_shift, + &abm_mask); + if (pool->base.multiple_abms[i] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* MPC and DSC */ + pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn31_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB and MMHUBBUB */ + if (!dcn31_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + if (!dcn31_mmhubbub_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); + if (pool->base.engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); + if (pool->base.hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->base.sw_i2cs[i] = NULL; + } + + /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, &pool->base, + (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? + &res_create_funcs : &res_create_maximus_funcs))) + goto create_fail; + + /* HW Sequencer and Plane caps */ + dcn31_hw_sequencer_construct(dc); + + dc->caps.max_planes = pool->base.pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->cap_funcs = cap_funcs; + + DC_FP_END(); + + return true; + +create_fail: + + DC_FP_END(); + dcn31_resource_destruct(pool); + + return false; +} + +struct resource_pool *dcn31_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc) +{ + struct dcn31_resource_pool *pool = + kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h new file mode 100644 index 000000000000..93571c976996 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h @@ -0,0 +1,42 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCN31_RESOURCE_H_ +#define _DCN31_RESOURCE_H_ + +#include "core_types.h" + +#define TO_DCN31_RES_POOL(pool)\ + container_of(pool, struct dcn31_resource_pool, base) + +struct dcn31_resource_pool { + struct resource_pool base; +}; + +struct resource_pool *dcn31_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc); + +#endif /* _DCN31_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h index cac0b2c0d31b..a9170b9f84d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h +++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h @@ -32,6 +32,9 @@ struct cp_psp_stream_config { uint8_t otg_inst; uint8_t dig_be; uint8_t dig_fe; + uint8_t link_enc_idx; + uint8_t stream_enc_idx; + uint8_t phy_idx; uint8_t assr_enabled; uint8_t mst_enabled; void *dm_stream_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 7617fab9e1f9..9ab854293ace 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -34,6 +34,8 @@ #include "dc.h" struct dp_mst_stream_allocation_table; +struct aux_payload; +enum aux_return_code_type; /* * Allocate memory accessible by the GPU @@ -158,6 +160,17 @@ void dm_set_dcn_clocks( struct dc_context *ctx, struct dc_clocks *clks); -bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable); +bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable); +void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us); + +// 0x1 = Result_OK, 0xFE = Result_UnkmownCmd +#define IS_SMU_TIMEOUT(result) \ + (!(result == 0x1 || result == 0xFE)) + +int dm_helper_dmub_aux_transfer_sync( + struct dc_context *ctx, + const struct dc_link *link, + struct aux_payload *payload, + enum aux_return_code_type *operation_result); #endif /* __DM_HELPERS__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h index fb41140e8381..4440d08743aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h @@ -245,6 +245,8 @@ struct pp_smu_funcs_nv { #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 #define PP_SMU_NUM_FCLK_DPM_LEVELS 4 #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 +#define PP_SMU_NUM_DCLK_DPM_LEVELS 8 +#define PP_SMU_NUM_VCLK_DPM_LEVELS 8 struct dpm_clock { uint32_t Freq; // In MHz @@ -258,6 +260,8 @@ struct dpm_clocks { struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS]; struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS]; struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS]; + struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS]; + struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS]; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 6bb7f2905821..d34024fd798a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -62,6 +62,8 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048 +CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags) @@ -72,6 +74,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags) endif CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags) @@ -86,6 +90,7 @@ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o +DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o endif AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML)) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 9729cf292e84..d3b5b6fedf04 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2895,7 +2895,7 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) RoundedUpMaxSwathSizeBytesC = 0.0; if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { + <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; } else { @@ -2904,17 +2904,17 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024; + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2; } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 3; } } @@ -3819,7 +3819,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaximumSwathWidthInDETBuffer = dml_min( mode_lib->vba.MaximumSwathWidthSupport, - mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0 + mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0 / (locals->BytePerPixelInDETY[k] * locals->MinSwathHeightY[k] + locals->BytePerPixelInDETC[k] @@ -4322,7 +4322,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->RoundedUpMaxSwathSizeBytesC = 0; } - if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) { + if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024 / 2) { locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; } else { @@ -4331,15 +4331,15 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } if (locals->BytePerPixelInDETC[k] == 0) { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; locals->LinesInDETChroma = 0; } else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] / + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; - locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); + locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } else { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; - locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; + locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 51098c2c9854..fbed5304692d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2968,7 +2968,7 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) RoundedUpMaxSwathSizeBytesC = 0.0; if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { + <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; } else { @@ -2977,17 +2977,17 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024; + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2; } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte + mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 3; } } @@ -3926,7 +3926,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.MaximumSwathWidthInDETBuffer = dml_min( mode_lib->vba.MaximumSwathWidthSupport, - mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0 + mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0 / (locals->BytePerPixelInDETY[k] * locals->MinSwathHeightY[k] + locals->BytePerPixelInDETC[k] @@ -4443,7 +4443,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode locals->RoundedUpMaxSwathSizeBytesC = 0; } - if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) { + if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024 / 2) { locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; } else { @@ -4452,15 +4452,15 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode } if (locals->BytePerPixelInDETC[k] == 0) { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; locals->LinesInDETChroma = 0; } else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] / + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; - locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); + locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } else { - locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; - locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); + locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; + locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 398210d1af34..c26e742e8137 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -148,7 +148,7 @@ static double CalculateDCCConfiguration( bool DCCProgrammingAssumesScanDirectionUnknown, unsigned int ViewportWidth, unsigned int ViewportHeight, - double DETBufferSize, + unsigned int DETBufferSize, unsigned int RequestHeight256Byte, unsigned int SwathHeight, enum dm_swizzle_mode TilingFormat, @@ -289,7 +289,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, @@ -354,11 +354,11 @@ static void CalculateDCFCLKDeepSleep( double DPPCLK[], double *DCFCLKDeepSleep); static void CalculateDETBufferSize( - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int SwathHeightY, unsigned int SwathHeightC, - double *DETBufferSizeY, - double *DETBufferSizeC); + unsigned int *DETBufferSizeY, + unsigned int *DETBufferSizeC); static void CalculateUrgentBurstFactor( unsigned int DETBufferSizeInKByte, unsigned int SwathHeightY, @@ -1074,7 +1074,7 @@ static double CalculateDCCConfiguration( bool DCCProgrammingAssumesScanDirectionUnknown, unsigned int ViewportWidth, unsigned int ViewportHeight, - double DETBufferSize, + unsigned int DETBufferSize, unsigned int RequestHeight256Byte, unsigned int SwathHeight, enum dm_swizzle_mode TilingFormat, @@ -2246,7 +2246,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } CalculateUrgentBurstFactor( - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], locals->SwathWidthY[k], @@ -2415,7 +2415,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.MaxLineBufferLines, mode_lib->vba.LineBufferSize, mode_lib->vba.DPPOutputBufferPixels, - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.WritebackInterfaceLumaBufferSize, mode_lib->vba.WritebackInterfaceChromaBufferSize, mode_lib->vba.DCFCLK, @@ -2588,7 +2588,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown, mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - mode_lib->vba.DETBufferSizeInKByte * 1024, + mode_lib->vba.DETBufferSizeInKByte[0] * 1024, locals->BlockHeight256BytesY[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SurfaceTiling[k], @@ -2689,13 +2689,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman // Stutter Efficiency for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { CalculateDETBufferSize( - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], &locals->DETBufferSizeY[k], &locals->DETBufferSizeC[k]); - locals->LinesInDETY[k] = locals->DETBufferSizeY[k] + locals->LinesInDETY[k] = (double)locals->DETBufferSizeY[k] / locals->BytePerPixelDETY[k] / locals->SwathWidthY[k]; locals->LinesInDETYRoundedDownToSwath[k] = dml_floor( locals->LinesInDETY[k], @@ -2984,7 +2984,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) RoundedUpMaxSwathSizeBytesC = 0.0; if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { + <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; } else { @@ -2993,7 +2993,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) } CalculateDETBufferSize( - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], &mode_lib->vba.DETBufferSizeY[k], @@ -3888,7 +3888,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaximumSwathWidthInDETBuffer = dml_min( mode_lib->vba.MaximumSwathWidthSupport, - mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0 + mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0 / (locals->BytePerPixelInDETY[k] * locals->MinSwathHeightY[k] + locals->BytePerPixelInDETC[k] @@ -4437,7 +4437,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0; } if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC - <= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) { + <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k]; locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k]; } else { @@ -4801,7 +4801,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } CalculateUrgentBurstFactor( - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], locals->SwathHeightYThisState[k], locals->SwathHeightCThisState[k], locals->SwathWidthYThisState[k], @@ -4975,7 +4975,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaxLineBufferLines, mode_lib->vba.LineBufferSize, mode_lib->vba.DPPOutputBufferPixels, - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.WritebackInterfaceLumaBufferSize, mode_lib->vba.WritebackInterfaceChromaBufferSize, mode_lib->vba.DCFCLKPerState[i], @@ -5230,7 +5230,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, @@ -5285,8 +5285,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double EffectiveLBLatencyHidingC; double DPPOutputBufferLinesY; double DPPOutputBufferLinesC; - double DETBufferSizeY; - double DETBufferSizeC; + unsigned int DETBufferSizeY; + unsigned int DETBufferSizeC; double LinesInDETY[DC__NUM_DPP__MAX]; double LinesInDETC; unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; @@ -5382,12 +5382,12 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( &DETBufferSizeY, &DETBufferSizeC); - LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; if (BytePerPixelDETC[k] > 0) { - LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); + LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2); @@ -5574,11 +5574,11 @@ static void CalculateDCFCLKDeepSleep( } static void CalculateDETBufferSize( - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int SwathHeightY, unsigned int SwathHeightC, - double *DETBufferSizeY, - double *DETBufferSizeC) + unsigned int *DETBufferSizeY, + unsigned int *DETBufferSizeC) { if (SwathHeightC == 0) { *DETBufferSizeY = DETBufferSizeInKByte * 1024; @@ -5625,8 +5625,8 @@ static void CalculateUrgentBurstFactor( double DETBufferSizeInTimeLumaPre; double DETBufferSizeInTimeChroma; double DETBufferSizeInTimeChromaPre; - double DETBufferSizeY; - double DETBufferSizeC; + unsigned int DETBufferSizeY; + unsigned int DETBufferSizeC; *NotEnoughUrgentLatencyHiding = 0; *NotEnoughUrgentLatencyHidingPre = 0; @@ -5663,7 +5663,7 @@ static void CalculateUrgentBurstFactor( &DETBufferSizeY, &DETBufferSizeC); - LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / SwathWidthY; + LinesInDETLuma = (double)DETBufferSizeY / BytePerPixelInDETY / SwathWidthY; DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio; if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) { *NotEnoughUrgentLatencyHiding = 1; @@ -5687,7 +5687,7 @@ static void CalculateUrgentBurstFactor( } if (BytePerPixelInDETC > 0) { - LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2); + LinesInDETChroma = (double)DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2); DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / (VRatio / 2); if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index cb3f70a71b51..9d2016d8fafe 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -64,6 +64,7 @@ typedef struct { #define BPP_INVALID 0 #define BPP_BLENDED_PIPE 0xffffffff #define DCN30_MAX_DSC_IMAGE_WIDTH 5184 +#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib); static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation( @@ -299,7 +300,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceBufferSize, double DCFCLK, double ReturnBW, @@ -318,8 +319,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], - double DETBufferSizeY[], - double DETBufferSizeC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], unsigned int LBBitPerPixel[], @@ -570,7 +571,7 @@ static void CalculateStutterEfficiency( double SRExitTime, bool SynchronizedVBlank, int DPPPerPlane[], - double DETBufferSizeY[], + unsigned int DETBufferSizeY[], int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], @@ -603,7 +604,7 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, int NumberOfActivePlanes, - long DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], enum scan_direction_class SourceScan[], @@ -635,8 +636,8 @@ static void CalculateSwathAndDETConfiguration( double SwathWidthChroma[], int SwathHeightY[], int SwathHeightC[], - double DETBufferSizeY[], - double DETBufferSizeC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport); static void CalculateSwathWidth( @@ -2052,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed); v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown( - v->soc.clock_limits[mode_lib->soc.num_states].dispclk_mhz, + v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, v->DISPCLKDPPCLKVCOSpeed); if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) { @@ -2613,7 +2614,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman CalculateUrgentBurstFactor( v->swath_width_luma_ub[k], v->swath_width_chroma_ub[k], - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->SwathHeightY[k], v->SwathHeightC[k], v->HTotal[k] / v->PixelClock[k], @@ -2635,7 +2636,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman CalculateUrgentBurstFactor( v->swath_width_luma_ub[k], v->swath_width_chroma_ub[k], - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->SwathHeightY[k], v->SwathHeightC[k], v->HTotal[k] / v->PixelClock[k], @@ -2808,7 +2809,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaxLineBufferLines, v->LineBufferSize, v->DPPOutputBufferPixels, - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->WritebackInterfaceBufferSize, v->DCFCLK, v->ReturnBW, @@ -3027,7 +3028,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceWidthC[k], v->SurfaceHeightY[k], v->SurfaceHeightC[k], - v->DETBufferSizeInKByte * 1024, + v->DETBufferSizeInKByte[0] * 1024, v->BlockHeight256BytesY[k], v->BlockHeight256BytesC[k], v->SurfaceTiling[k], @@ -3177,7 +3178,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) CalculateSwathAndDETConfiguration( false, mode_lib->vba.NumberOfActivePlanes, - mode_lib->vba.DETBufferSizeInKByte, + mode_lib->vba.DETBufferSizeInKByte[0], dummy1, dummy2, mode_lib->vba.SourceScan, @@ -3911,7 +3912,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l CalculateSwathAndDETConfiguration( true, v->NumberOfActivePlanes, - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->MaximumSwathWidthLuma, v->MaximumSwathWidthChroma, v->SourceScan, @@ -3957,20 +3958,20 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1.0 + v->DISPCLKRampingMargin / 100.0); - if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states] - && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) { + if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); } v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + v->DISPCLKRampingMargin / 100.0); - if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states] - && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) { + if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); } v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + v->DISPCLKRampingMargin / 100.0); - if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states] - && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) { + if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); } @@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) { v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; - } else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) { - v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; - v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; } else { v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine; - /*420 format workaround*/ - if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) { + } + if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH + && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) { + if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + } else { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; + } + } + if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH + && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) { + if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + } else { v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; } } - if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { v->MPCCombine[i][j][k] = false; v->NoOfDPP[i][j][k] = 4; @@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = 0; i < v->soc.num_states; i++) { - v->DSCCLKRequiredMoreThanSupported[i] = false; - for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { - if (v->BlendingAndTiming[k] == k) { - if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) { - if (v->OutputFormat[k] == dm_420) { - v->DSCFormatFactor = 2; - } else if (v->OutputFormat[k] == dm_444) { - v->DSCFormatFactor = 1; - } else if (v->OutputFormat[k] == dm_n422) { - v->DSCFormatFactor = 2; - } else { - v->DSCFormatFactor = 1; - } - if (v->RequiresDSC[i][k] == true) { - if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { - if (v->PixelClockBackEnd[k] / 12.0 / v->DSCFormatFactor - > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) { - v->DSCCLKRequiredMoreThanSupported[i] = true; - } - } else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { - if (v->PixelClockBackEnd[k] / 6.0 / v->DSCFormatFactor - > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) { - v->DSCCLKRequiredMoreThanSupported[i] = true; - } - } else { - if (v->PixelClockBackEnd[k] / 3.0 / v->DSCFormatFactor - > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) { - v->DSCCLKRequiredMoreThanSupported[i] = true; - } - } - } - } - } - } - } + /* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */ + for (i = 0; i < v->soc.num_states; i++) { v->NotEnoughDSCUnits[i] = false; v->TotalDSCUnitsRequired = 0.0; @@ -4399,7 +4377,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l CalculateSwathAndDETConfiguration( false, v->NumberOfActivePlanes, - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->MaximumSwathWidthLuma, v->MaximumSwathWidthChroma, v->SourceScan, @@ -4622,7 +4600,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l CalculateUrgentBurstFactor( v->swath_width_luma_ub_this_state[k], v->swath_width_chroma_ub_this_state[k], - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->SwathHeightYThisState[k], v->SwathHeightCThisState[k], v->HTotal[k] / v->PixelClock[k], @@ -5025,7 +5003,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l CalculateUrgentBurstFactor( v->swath_width_luma_ub_this_state[k], v->swath_width_chroma_ub_this_state[k], - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->SwathHeightYThisState[k], v->SwathHeightCThisState[k], v->HTotal[k] / v->PixelClock[k], @@ -5197,7 +5175,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->MaxLineBufferLines, v->LineBufferSize, v->DPPOutputBufferPixels, - v->DETBufferSizeInKByte, + v->DETBufferSizeInKByte[0], v->WritebackInterfaceBufferSize, v->DCFCLKState[i][j], v->ReturnBWPerState[i][j], @@ -5319,7 +5297,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (j = 0; j < 2; j++) { if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1 && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1 - && v->NotEnoughDSCUnits[i] == 0 && v->DSCCLKRequiredMoreThanSupported[i] == 0 + && v->NotEnoughDSCUnits[i] == 0 && v->DTBCLKRequiredMoreThanSupported[i] == 0 && v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1 && EnoughWritebackUnits == 1 && WritebackModeSupport == 1 @@ -5369,7 +5347,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, - double DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceBufferSize, double DCFCLK, double ReturnBW, @@ -5388,8 +5366,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], - double DETBufferSizeY[], - double DETBufferSizeC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], unsigned int LBBitPerPixel[], @@ -6126,7 +6104,7 @@ static void CalculateStutterEfficiency( double SRExitTime, bool SynchronizedVBlank, int DPPPerPlane[], - double DETBufferSizeY[], + unsigned int DETBufferSizeY[], int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], @@ -6273,7 +6251,7 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, int NumberOfActivePlanes, - long DETBufferSizeInKByte, + unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], enum scan_direction_class SourceScan[], @@ -6305,8 +6283,8 @@ static void CalculateSwathAndDETConfiguration( double SwathWidthChroma[], int SwathHeightY[], int SwathHeightC[], - double DETBufferSizeY[], - double DETBufferSizeC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c new file mode 100644 index 000000000000..a9667068c690 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -0,0 +1,7510 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dc.h" +#include "dc_link.h" +#include "../display_mode_lib.h" +#include "display_mode_vba_31.h" +#include "../dml_inline_defs.h" + +/* + * NOTE: + * This file is gcc-parsable HW gospel, coming straight from HW engineers. + * + * It doesn't adhere to Linux kernel style and sometimes will do things in odd + * ways. Unless there is something clearly wrong with it the code should + * remain as-is as it provides us with a guarantee from HW that it is correct. + */ + +#define BPP_INVALID 0 +#define BPP_BLENDED_PIPE 0xffffffff +#define DCN31_MAX_DSC_IMAGE_WIDTH 5184 +#define DCN31_MAX_FMT_420_BUFFER_WIDTH 4096 + +// For DML-C changes that hasn't been propagated to VBA yet +//#define __DML_VBA_ALLOW_DELTA__ + +// Move these to ip paramaters/constant + +// At which vstartup the DML start to try if the mode can be supported +#define __DML_VBA_MIN_VSTARTUP__ 9 + +// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET) +#define __DML_ARB_TO_RET_DELAY__ (7 + 95) + +// fudge factor for min dcfclk calclation +#define __DML_MIN_DCFCLK_FACTOR__ 1.15 + +typedef struct { + double DPPCLK; + double DISPCLK; + double PixelClock; + double DCFCLKDeepSleep; + unsigned int DPPPerPlane; + bool ScalerEnabled; + enum scan_direction_class SourceScan; + unsigned int BlockWidth256BytesY; + unsigned int BlockHeight256BytesY; + unsigned int BlockWidth256BytesC; + unsigned int BlockHeight256BytesC; + unsigned int InterlaceEnable; + unsigned int NumberOfCursors; + unsigned int VBlank; + unsigned int HTotal; + unsigned int DCCEnable; + bool ODMCombineIsEnabled; + enum source_format_class SourcePixelFormat; + int BytePerPixelY; + int BytePerPixelC; + bool ProgressiveToInterlaceUnitInOPP; +} Pipe; + +#define BPP_INVALID 0 +#define BPP_BLENDED_PIPE 0xffffffff + +static bool CalculateBytePerPixelAnd256BBlockSizes( + enum source_format_class SourcePixelFormat, + enum dm_swizzle_mode SurfaceTiling, + unsigned int *BytePerPixelY, + unsigned int *BytePerPixelC, + double *BytePerPixelDETY, + double *BytePerPixelDETC, + unsigned int *BlockHeight256BytesY, + unsigned int *BlockHeight256BytesC, + unsigned int *BlockWidth256BytesY, + unsigned int *BlockWidth256BytesC); +static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib); +static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib); +static unsigned int dscceComputeDelay( + unsigned int bpc, + double BPP, + unsigned int sliceWidth, + unsigned int numSlices, + enum output_format_class pixelFormat, + enum output_encoder_class Output); +static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output); +static bool CalculatePrefetchSchedule( + struct display_mode_lib *mode_lib, + double HostVMInefficiencyFactor, + Pipe *myPipe, + unsigned int DSCDelay, + double DPPCLKDelaySubtotalPlusCNVCFormater, + double DPPCLKDelaySCL, + double DPPCLKDelaySCLLBOnly, + double DPPCLKDelayCNVCCursor, + double DISPCLKDelaySubtotal, + unsigned int DPP_RECOUT_WIDTH, + enum output_format_class OutputFormat, + unsigned int MaxInterDCNTileRepeaters, + unsigned int VStartup, + unsigned int MaxVStartup, + unsigned int GPUVMPageTableLevels, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + double HostVMMinPageSize, + bool DynamicMetadataEnable, + bool DynamicMetadataVMEnabled, + int DynamicMetadataLinesBeforeActiveRequired, + unsigned int DynamicMetadataTransmittedBytes, + double UrgentLatency, + double UrgentExtraLatency, + double TCalc, + unsigned int PDEAndMetaPTEBytesFrame, + unsigned int MetaRowByte, + unsigned int PixelPTEBytesPerRow, + double PrefetchSourceLinesY, + unsigned int SwathWidthY, + double VInitPreFillY, + unsigned int MaxNumSwathY, + double PrefetchSourceLinesC, + unsigned int SwathWidthC, + double VInitPreFillC, + unsigned int MaxNumSwathC, + int swath_width_luma_ub, + int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double TWait, + double *DSTXAfterScaler, + double *DSTYAfterScaler, + double *DestinationLinesForPrefetch, + double *PrefetchBandwidth, + double *DestinationLinesToRequestVMInVBlank, + double *DestinationLinesToRequestRowInVBlank, + double *VRatioPrefetchY, + double *VRatioPrefetchC, + double *RequiredPrefetchPixDataBWLuma, + double *RequiredPrefetchPixDataBWChroma, + bool *NotEnoughTimeForDynamicMetadata, + double *Tno_bw, + double *prefetch_vmrow_bw, + double *Tdmdl_vm, + double *Tdmdl, + double *TSetup, + int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix); +static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); +static double RoundToDFSGranularityDown(double Clock, double VCOSpeed); +static void CalculateDCCConfiguration( + bool DCCEnabled, + bool DCCProgrammingAssumesScanDirectionUnknown, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceWidthLuma, + unsigned int SurfaceWidthChroma, + unsigned int SurfaceHeightLuma, + unsigned int SurfaceHeightChroma, + double DETBufferSize, + unsigned int RequestHeight256ByteLuma, + unsigned int RequestHeight256ByteChroma, + enum dm_swizzle_mode TilingFormat, + unsigned int BytePerPixelY, + unsigned int BytePerPixelC, + double BytePerPixelDETY, + double BytePerPixelDETC, + enum scan_direction_class ScanOrientation, + unsigned int *MaxUncompressedBlockLuma, + unsigned int *MaxUncompressedBlockChroma, + unsigned int *MaxCompressedBlockLuma, + unsigned int *MaxCompressedBlockChroma, + unsigned int *IndependentBlockLuma, + unsigned int *IndependentBlockChroma); +static double CalculatePrefetchSourceLines( + struct display_mode_lib *mode_lib, + double VRatio, + double vtaps, + bool Interlace, + bool ProgressiveToInterlaceUnitInOPP, + unsigned int SwathHeight, + unsigned int ViewportYStart, + double *VInitPreFill, + unsigned int *MaxNumSwath); +static unsigned int CalculateVMAndRowBytes( + struct display_mode_lib *mode_lib, + bool DCCEnable, + unsigned int BlockHeight256Bytes, + unsigned int BlockWidth256Bytes, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceTiling, + unsigned int BytePerPixel, + enum scan_direction_class ScanDirection, + unsigned int SwathWidth, + unsigned int ViewportHeight, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMinPageSize, + unsigned int HostVMMinPageSize, + unsigned int PTEBufferSizeInRequests, + unsigned int Pitch, + unsigned int DCCMetaPitch, + unsigned int *MacroTileWidth, + unsigned int *MetaRowByte, + unsigned int *PixelPTEBytesPerRow, + bool *PTEBufferSizeNotExceeded, + int *dpte_row_width_ub, + unsigned int *dpte_row_height, + unsigned int *MetaRequestWidth, + unsigned int *MetaRequestHeight, + unsigned int *meta_row_width, + unsigned int *meta_row_height, + int *vm_group_bytes, + unsigned int *dpte_group_bytes, + unsigned int *PixelPTEReqWidth, + unsigned int *PixelPTEReqHeight, + unsigned int *PTERequestSize, + int *DPDE0BytesFrame, + int *MetaPTEBytesFrame); +static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime); +static void CalculateRowBandwidth( + bool GPUVMEnable, + enum source_format_class SourcePixelFormat, + double VRatio, + double VRatioChroma, + bool DCCEnable, + double LineTime, + unsigned int MetaRowByteLuma, + unsigned int MetaRowByteChroma, + unsigned int meta_row_height_luma, + unsigned int meta_row_height_chroma, + unsigned int PixelPTEBytesPerRowLuma, + unsigned int PixelPTEBytesPerRowChroma, + unsigned int dpte_row_height_luma, + unsigned int dpte_row_height_chroma, + double *meta_row_bw, + double *dpte_row_bw); + +static void CalculateFlipSchedule( + struct display_mode_lib *mode_lib, + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool GPUVMEnable, + double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, + double DPTEBytesPerRow, + double BandwidthAvailableForImmediateFlip, + unsigned int TotImmediateFlipBytes, + enum source_format_class SourcePixelFormat, + double LineTime, + double VRatio, + double VRatioChroma, + double Tno_bw, + bool DCCEnable, + unsigned int dpte_row_height, + unsigned int meta_row_height, + unsigned int dpte_row_height_chroma, + unsigned int meta_row_height_chroma, + double *DestinationLinesToRequestVMInImmediateFlip, + double *DestinationLinesToRequestRowInImmediateFlip, + double *final_flip_bw, + bool *ImmediateFlipSupportedForPipe); +static double CalculateWriteBackDelay( + enum source_format_class WritebackPixelFormat, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackVTaps, + int WritebackDestinationWidth, + int WritebackDestinationHeight, + int WritebackSourceHeight, + unsigned int HTotal); + +static void CalculateVupdateAndDynamicMetadataParameters( + int MaxInterDCNTileRepeaters, + double DPPCLK, + double DISPCLK, + double DCFClkDeepSleep, + double PixelClock, + int HTotal, + int VBlank, + int DynamicMetadataTransmittedBytes, + int DynamicMetadataLinesBeforeActiveRequired, + int InterlaceEnable, + bool ProgressiveToInterlaceUnitInOPP, + double *TSetup, + double *Tdmbf, + double *Tdmec, + double *Tdmsks, + int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix); + +static void CalculateWatermarksAndDRAMSpeedChangeSupport( + struct display_mode_lib *mode_lib, + unsigned int PrefetchMode, + unsigned int NumberOfActivePlanes, + unsigned int MaxLineBufferLines, + unsigned int LineBufferSize, + unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, + bool SynchronizedVBlank, + unsigned int dpte_group_bytes[], + unsigned int MetaChunkSize, + double UrgentLatency, + double ExtraLatency, + double WritebackLatency, + double WritebackChunkSize, + double SOCCLK, + double DRAMClockChangeLatency, + double SRExitTime, + double SREnterPlusExitTime, + double SRExitZ8Time, + double SREnterPlusExitZ8Time, + double DCFCLKDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], + double HRatio[], + double HRatioChroma[], + unsigned int vtaps[], + unsigned int VTAPsChroma[], + double VRatio[], + double VRatioChroma[], + unsigned int HTotal[], + double PixelClock[], + unsigned int BlendingAndTiming[], + unsigned int DPPPerPlane[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], + double DSTXAfterScaler[], + double DSTYAfterScaler[], + bool WritebackEnable[], + enum source_format_class WritebackPixelFormat[], + double WritebackDestinationWidth[], + double WritebackDestinationHeight[], + double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + int unsigned CompressedBufferSizeInkByte, + enum clock_change_support *DRAMClockChangeSupport, + double *UrgentWatermark, + double *WritebackUrgentWatermark, + double *DRAMClockChangeWatermark, + double *WritebackDRAMClockChangeWatermark, + double *StutterExitWatermark, + double *StutterEnterPlusExitWatermark, + double *Z8StutterExitWatermark, + double *Z8StutterEnterPlusExitWatermark, + double *MinActiveDRAMClockChangeLatencySupported); + +static void CalculateDCFCLKDeepSleep( + struct display_mode_lib *mode_lib, + unsigned int NumberOfActivePlanes, + int BytePerPixelY[], + int BytePerPixelC[], + double VRatio[], + double VRatioChroma[], + double SwathWidthY[], + double SwathWidthC[], + unsigned int DPPPerPlane[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double DPPCLK[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + int ReturnBusWidth, + double *DCFCLKDeepSleep); + +static void CalculateUrgentBurstFactor( + int swath_width_luma_ub, + int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double LineTime, + double UrgentLatency, + double CursorBufferSize, + unsigned int CursorWidth, + unsigned int CursorBPP, + double VRatio, + double VRatioC, + double BytePerPixelInDETY, + double BytePerPixelInDETC, + double DETBufferSizeY, + double DETBufferSizeC, + double *UrgentBurstFactorCursor, + double *UrgentBurstFactorLuma, + double *UrgentBurstFactorChroma, + bool *NotEnoughUrgentLatencyHiding); + +static void UseMinimumDCFCLK( + struct display_mode_lib *mode_lib, + int MaxInterDCNTileRepeaters, + int MaxPrefetchMode, + double FinalDRAMClockChangeLatency, + double SREnterPlusExitTime, + int ReturnBusWidth, + int RoundTripPingLatencyCycles, + int ReorderingBytes, + int PixelChunkSizeInKByte, + int MetaChunkSize, + bool GPUVMEnable, + int GPUVMMaxPageTableLevels, + bool HostVMEnable, + int NumberOfActivePlanes, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels, + bool DynamicMetadataVMEnabled, + enum immediate_flip_requirement ImmediateFlipRequirement, + bool ProgressiveToInterlaceUnitInOPP, + double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, + double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, + int VTotal[], + int VActive[], + int DynamicMetadataTransmittedBytes[], + int DynamicMetadataLinesBeforeActiveRequired[], + bool Interlace[], + double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], + double RequiredDISPCLK[][2], + double UrgLatency[], + unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], + double ProjectedDCFCLKDeepSleep[][2], + double MaximumVStartup[][2][DC__NUM_DPP__MAX], + double TotalVActivePixelBandwidth[][2], + double TotalVActiveCursorBandwidth[][2], + double TotalMetaRowBandwidth[][2], + double TotalDPTERowBandwidth[][2], + unsigned int TotalNumberOfActiveDPP[][2], + unsigned int TotalNumberOfDCCActiveDPP[][2], + int dpte_group_bytes[], + double PrefetchLinesY[][2][DC__NUM_DPP__MAX], + double PrefetchLinesC[][2][DC__NUM_DPP__MAX], + int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + int BytePerPixelY[], + int BytePerPixelC[], + int HTotal[], + double PixelClock[], + double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], + double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], + double MetaRowBytes[][2][DC__NUM_DPP__MAX], + bool DynamicMetadataEnable[], + double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], + double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double DCFCLKPerState[], + double DCFCLKState[][2]); + +static void CalculatePixelDeliveryTimes( + unsigned int NumberOfActivePlanes, + double VRatio[], + double VRatioChroma[], + double VRatioPrefetchY[], + double VRatioPrefetchC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double DPPCLK[], + int BytePerPixelC[], + enum scan_direction_class SourceScan[], + unsigned int NumberOfCursors[], + unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], + unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesC[], + unsigned int BlockHeight256BytesC[], + double DisplayPipeLineDeliveryTimeLuma[], + double DisplayPipeLineDeliveryTimeChroma[], + double DisplayPipeLineDeliveryTimeLumaPrefetch[], + double DisplayPipeLineDeliveryTimeChromaPrefetch[], + double DisplayPipeRequestDeliveryTimeLuma[], + double DisplayPipeRequestDeliveryTimeChroma[], + double DisplayPipeRequestDeliveryTimeLumaPrefetch[], + double DisplayPipeRequestDeliveryTimeChromaPrefetch[], + double CursorRequestDeliveryTime[], + double CursorRequestDeliveryTimePrefetch[]); + +static void CalculateMetaAndPTETimes( + int NumberOfActivePlanes, + bool GPUVMEnable, + int MetaChunkSize, + int MinMetaChunkSizeBytes, + int HTotal[], + double VRatio[], + double VRatioChroma[], + double DestinationLinesToRequestRowInVBlank[], + double DestinationLinesToRequestRowInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + int BytePerPixelY[], + int BytePerPixelC[], + enum scan_direction_class SourceScan[], + int dpte_row_height[], + int dpte_row_height_chroma[], + int meta_row_width[], + int meta_row_width_chroma[], + int meta_row_height[], + int meta_row_height_chroma[], + int meta_req_width[], + int meta_req_width_chroma[], + int meta_req_height[], + int meta_req_height_chroma[], + int dpte_group_bytes[], + int PTERequestSizeY[], + int PTERequestSizeC[], + int PixelPTEReqWidthY[], + int PixelPTEReqHeightY[], + int PixelPTEReqWidthC[], + int PixelPTEReqHeightC[], + int dpte_row_width_luma_ub[], + int dpte_row_width_chroma_ub[], + double DST_Y_PER_PTE_ROW_NOM_L[], + double DST_Y_PER_PTE_ROW_NOM_C[], + double DST_Y_PER_META_ROW_NOM_L[], + double DST_Y_PER_META_ROW_NOM_C[], + double TimePerMetaChunkNominal[], + double TimePerChromaMetaChunkNominal[], + double TimePerMetaChunkVBlank[], + double TimePerChromaMetaChunkVBlank[], + double TimePerMetaChunkFlip[], + double TimePerChromaMetaChunkFlip[], + double time_per_pte_group_nom_luma[], + double time_per_pte_group_vblank_luma[], + double time_per_pte_group_flip_luma[], + double time_per_pte_group_nom_chroma[], + double time_per_pte_group_vblank_chroma[], + double time_per_pte_group_flip_chroma[]); + +static void CalculateVMGroupAndRequestTimes( + unsigned int NumberOfActivePlanes, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + unsigned int HTotal[], + int BytePerPixelC[], + double DestinationLinesToRequestVMInVBlank[], + double DestinationLinesToRequestVMInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + int dpte_row_width_luma_ub[], + int dpte_row_width_chroma_ub[], + int vm_group_bytes[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + int meta_pte_bytes_per_frame_ub_l[], + int meta_pte_bytes_per_frame_ub_c[], + double TimePerVMGroupVBlank[], + double TimePerVMGroupFlip[], + double TimePerVMRequestVBlank[], + double TimePerVMRequestFlip[]); + +static void CalculateStutterEfficiency( + struct display_mode_lib *mode_lib, + int CompressedBufferSizeInkByte, + bool UnboundedRequestEnabled, + int ConfigReturnBufferSizeInKByte, + int MetaFIFOSizeInKEntries, + int ZeroSizeBufferEntries, + int NumberOfActivePlanes, + int ROBBufferSizeInKByte, + double TotalDataReadBandwidth, + double DCFCLK, + double ReturnBW, + double COMPBUF_RESERVED_SPACE_64B, + double COMPBUF_RESERVED_SPACE_ZS, + double SRExitTime, + double SRExitZ8Time, + bool SynchronizedVBlank, + double Z8StutterEnterPlusExitWatermark, + double StutterEnterPlusExitWatermark, + bool ProgressiveToInterlaceUnitInOPP, + bool Interlace[], + double MinTTUVBlank[], + int DPPPerPlane[], + unsigned int DETBufferSizeY[], + int BytePerPixelY[], + double BytePerPixelDETY[], + double SwathWidthY[], + int SwathHeightY[], + int SwathHeightC[], + double NetDCCRateLuma[], + double NetDCCRateChroma[], + double DCCFractionOfZeroSizeRequestsLuma[], + double DCCFractionOfZeroSizeRequestsChroma[], + int HTotal[], + int VTotal[], + double PixelClock[], + double VRatio[], + enum scan_direction_class SourceScan[], + int BlockHeight256BytesY[], + int BlockWidth256BytesY[], + int BlockHeight256BytesC[], + int BlockWidth256BytesC[], + int DCCYMaxUncompressedBlock[], + int DCCCMaxUncompressedBlock[], + int VActive[], + bool DCCEnable[], + bool WritebackEnable[], + double ReadBandwidthPlaneLuma[], + double ReadBandwidthPlaneChroma[], + double meta_row_bw[], + double dpte_row_bw[], + double *StutterEfficiencyNotIncludingVBlank, + double *StutterEfficiency, + int *NumberOfStutterBurstsPerFrame, + double *Z8StutterEfficiencyNotIncludingVBlank, + double *Z8StutterEfficiency, + int *Z8NumberOfStutterBurstsPerFrame, + double *StutterPeriod); + +static void CalculateSwathAndDETConfiguration( + bool ForceSingleDPP, + int NumberOfActivePlanes, + unsigned int DETBufferSizeInKByte, + double MaximumSwathWidthLuma[], + double MaximumSwathWidthChroma[], + enum scan_direction_class SourceScan[], + enum source_format_class SourcePixelFormat[], + enum dm_swizzle_mode SurfaceTiling[], + int ViewportWidth[], + int ViewportHeight[], + int SurfaceWidthY[], + int SurfaceWidthC[], + int SurfaceHeightY[], + int SurfaceHeightC[], + int Read256BytesBlockHeightY[], + int Read256BytesBlockHeightC[], + int Read256BytesBlockWidthY[], + int Read256BytesBlockWidthC[], + enum odm_combine_mode ODMCombineEnabled[], + int BlendingAndTiming[], + int BytePerPixY[], + int BytePerPixC[], + double BytePerPixDETY[], + double BytePerPixDETC[], + int HActive[], + double HRatio[], + double HRatioChroma[], + int DPPPerPlane[], + int swath_width_luma_ub[], + int swath_width_chroma_ub[], + double SwathWidth[], + double SwathWidthChroma[], + int SwathHeightY[], + int SwathHeightC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + bool ViewportSizeSupportPerPlane[], + bool *ViewportSizeSupport); +static void CalculateSwathWidth( + bool ForceSingleDPP, + int NumberOfActivePlanes, + enum source_format_class SourcePixelFormat[], + enum scan_direction_class SourceScan[], + int ViewportWidth[], + int ViewportHeight[], + int SurfaceWidthY[], + int SurfaceWidthC[], + int SurfaceHeightY[], + int SurfaceHeightC[], + enum odm_combine_mode ODMCombineEnabled[], + int BytePerPixY[], + int BytePerPixC[], + int Read256BytesBlockHeightY[], + int Read256BytesBlockHeightC[], + int Read256BytesBlockWidthY[], + int Read256BytesBlockWidthC[], + int BlendingAndTiming[], + int HActive[], + double HRatio[], + int DPPPerPlane[], + double SwathWidthSingleDPPY[], + double SwathWidthSingleDPPC[], + double SwathWidthY[], + double SwathWidthC[], + int MaximumSwathHeightY[], + int MaximumSwathHeightC[], + int swath_width_luma_ub[], + int swath_width_chroma_ub[]); + +static double CalculateExtraLatency( + int RoundTripPingLatencyCycles, + int ReorderingBytes, + double DCFCLK, + int TotalNumberOfActiveDPP, + int PixelChunkSizeInKByte, + int TotalNumberOfDCCActiveDPP, + int MetaChunkSize, + double ReturnBW, + bool GPUVMEnable, + bool HostVMEnable, + int NumberOfActivePlanes, + int NumberOfDPP[], + int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels); + +static double CalculateExtraLatencyBytes( + int ReorderingBytes, + int TotalNumberOfActiveDPP, + int PixelChunkSizeInKByte, + int TotalNumberOfDCCActiveDPP, + int MetaChunkSize, + bool GPUVMEnable, + bool HostVMEnable, + int NumberOfActivePlanes, + int NumberOfDPP[], + int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels); + +static double CalculateUrgentLatency( + double UrgentLatencyPixelDataOnly, + double UrgentLatencyPixelMixedWithVMData, + double UrgentLatencyVMDataOnly, + bool DoUrgentLatencyAdjustment, + double UrgentLatencyAdjustmentFabricClockComponent, + double UrgentLatencyAdjustmentFabricClockReference, + double FabricClockSingle); + +static void CalculateUnboundedRequestAndCompressedBufferSize( + unsigned int DETBufferSizeInKByte, + int ConfigReturnBufferSizeInKByte, + enum unbounded_requesting_policy UseUnboundedRequestingFinal, + int TotalActiveDPP, + bool NoChromaPlanes, + int MaxNumDPP, + int CompressedBufferSegmentSizeInkByteFinal, + enum output_encoder_class *Output, + bool *UnboundedRequestEnabled, + int *CompressedBufferSizeInkByte); + +static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output); + +void dml31_recalculate(struct display_mode_lib *mode_lib) +{ + ModeSupportAndSystemConfiguration(mode_lib); + PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib); + DisplayPipeConfiguration(mode_lib); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__); +#endif + DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib); +} + +static unsigned int dscceComputeDelay( + unsigned int bpc, + double BPP, + unsigned int sliceWidth, + unsigned int numSlices, + enum output_format_class pixelFormat, + enum output_encoder_class Output) +{ + // valid bpc = source bits per component in the set of {8, 10, 12} + // valid bpp = increments of 1/16 of a bit + // min = 6/7/8 in N420/N422/444, respectively + // max = such that compression is 1:1 + //valid sliceWidth = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode) + //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} + //valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420} + + // fixed value + unsigned int rcModelSize = 8192; + + // N422/N420 operate at 2 pixels per clock + unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay, pixels; + + if (pixelFormat == dm_420) + pixelsPerClock = 2; + else if (pixelFormat == dm_444) + pixelsPerClock = 1; + else if (pixelFormat == dm_n422) + pixelsPerClock = 2; + // #all other modes operate at 1 pixel per clock + else + pixelsPerClock = 1; + + //initial transmit delay as per PPS + initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + + //compute ssm delay + if (bpc == 8) + D = 81; + else if (bpc == 10) + D = 89; + else + D = 113; + + //divide by pixel per cycle to compute slice width as seen by DSC + w = sliceWidth / pixelsPerClock; + + //422 mode has an additional cycle of delay + if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422) + s = 0; + else + s = 1; + + //main calculation for the dscce + ix = initalXmitDelay + 45; + wx = (w + 2) / 3; + P = 3 * wx - w; + l0 = ix / w; + a = ix + P * l0; + ax = (a + 2) / 3 + D + 6 + 1; + L = (ax + wx - 1) / wx; + if ((ix % w) == 0 && P != 0) + lstall = 1; + else + lstall = 0; + Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22; + + //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels + pixels = Delay * 3 * pixelsPerClock; + return pixels; +} + +static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output) +{ + unsigned int Delay = 0; + + if (pixelFormat == dm_420) { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 0; + // dscc - input deserializer + Delay = Delay + 3; + // dscc gets pixels every other cycle + Delay = Delay + 2; + // dscc - input cdc fifo + Delay = Delay + 12; + // dscc gets pixels every other cycle + Delay = Delay + 13; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 7; + // dscc gets pixels every other cycle + Delay = Delay + 3; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output serializer + Delay = Delay + 1; + // sft + Delay = Delay + 1; + } else if (pixelFormat == dm_n422) { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 1; + // dscc - input deserializer + Delay = Delay + 5; + // dscc - input cdc fifo + Delay = Delay + 25; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 10; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output serializer + Delay = Delay + 1; + // sft + Delay = Delay + 1; + } else { + // sfr + Delay = Delay + 2; + // dsccif + Delay = Delay + 0; + // dscc - input deserializer + Delay = Delay + 3; + // dscc - input cdc fifo + Delay = Delay + 12; + // dscc - cdc uncertainty + Delay = Delay + 2; + // dscc - output cdc fifo + Delay = Delay + 7; + // dscc - output serializer + Delay = Delay + 1; + // dscc - cdc uncertainty + Delay = Delay + 2; + // sft + Delay = Delay + 1; + } + + return Delay; +} + +static bool CalculatePrefetchSchedule( + struct display_mode_lib *mode_lib, + double HostVMInefficiencyFactor, + Pipe *myPipe, + unsigned int DSCDelay, + double DPPCLKDelaySubtotalPlusCNVCFormater, + double DPPCLKDelaySCL, + double DPPCLKDelaySCLLBOnly, + double DPPCLKDelayCNVCCursor, + double DISPCLKDelaySubtotal, + unsigned int DPP_RECOUT_WIDTH, + enum output_format_class OutputFormat, + unsigned int MaxInterDCNTileRepeaters, + unsigned int VStartup, + unsigned int MaxVStartup, + unsigned int GPUVMPageTableLevels, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + double HostVMMinPageSize, + bool DynamicMetadataEnable, + bool DynamicMetadataVMEnabled, + int DynamicMetadataLinesBeforeActiveRequired, + unsigned int DynamicMetadataTransmittedBytes, + double UrgentLatency, + double UrgentExtraLatency, + double TCalc, + unsigned int PDEAndMetaPTEBytesFrame, + unsigned int MetaRowByte, + unsigned int PixelPTEBytesPerRow, + double PrefetchSourceLinesY, + unsigned int SwathWidthY, + double VInitPreFillY, + unsigned int MaxNumSwathY, + double PrefetchSourceLinesC, + unsigned int SwathWidthC, + double VInitPreFillC, + unsigned int MaxNumSwathC, + int swath_width_luma_ub, + int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double TWait, + double *DSTXAfterScaler, + double *DSTYAfterScaler, + double *DestinationLinesForPrefetch, + double *PrefetchBandwidth, + double *DestinationLinesToRequestVMInVBlank, + double *DestinationLinesToRequestRowInVBlank, + double *VRatioPrefetchY, + double *VRatioPrefetchC, + double *RequiredPrefetchPixDataBWLuma, + double *RequiredPrefetchPixDataBWChroma, + bool *NotEnoughTimeForDynamicMetadata, + double *Tno_bw, + double *prefetch_vmrow_bw, + double *Tdmdl_vm, + double *Tdmdl, + double *TSetup, + int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix) +{ + bool MyError = false; + unsigned int DPPCycles, DISPCLKCycles; + double DSTTotalPixelsAfterScaler; + double LineTime; + double dst_y_prefetch_equ; + double Tsw_oto; + double prefetch_bw_oto; + double Tvm_oto; + double Tr0_oto; + double Tvm_oto_lines; + double Tr0_oto_lines; + double dst_y_prefetch_oto; + double TimeForFetchingMetaPTE = 0; + double TimeForFetchingRowInVBlank = 0; + double LinesToRequestPrefetchPixelData = 0; + unsigned int HostVMDynamicLevelsTrips; + double trip_to_mem; + double Tvm_trips; + double Tr0_trips; + double Tvm_trips_rounded; + double Tr0_trips_rounded; + double Lsw_oto; + double Tpre_rounded; + double prefetch_bw_equ; + double Tvm_equ; + double Tr0_equ; + double Tdmbf; + double Tdmec; + double Tdmsks; + double prefetch_sw_bytes; + double bytes_pp; + double dep_bytes; + int max_vratio_pre = 4; + double min_Lsw; + double Tsw_est1 = 0; + double Tsw_est3 = 0; + + if (GPUVMEnable == true && HostVMEnable == true) { + HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; + } else { + HostVMDynamicLevelsTrips = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: GPUVMEnable=%d HostVMEnable=%d HostVMInefficiencyFactor=%f\n", __func__, GPUVMEnable, HostVMEnable, HostVMInefficiencyFactor); +#endif + CalculateVupdateAndDynamicMetadataParameters( + MaxInterDCNTileRepeaters, + myPipe->DPPCLK, + myPipe->DISPCLK, + myPipe->DCFCLKDeepSleep, + myPipe->PixelClock, + myPipe->HTotal, + myPipe->VBlank, + DynamicMetadataTransmittedBytes, + DynamicMetadataLinesBeforeActiveRequired, + myPipe->InterlaceEnable, + myPipe->ProgressiveToInterlaceUnitInOPP, + TSetup, + &Tdmbf, + &Tdmec, + &Tdmsks, + VUpdateOffsetPix, + VUpdateWidthPix, + VReadyOffsetPix); + + LineTime = myPipe->HTotal / myPipe->PixelClock; + trip_to_mem = UrgentLatency; + Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1); + +#ifdef __DML_VBA_ALLOW_DELTA__ + if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) { +#else + if (DynamicMetadataVMEnabled == true) { +#endif + *Tdmdl = TWait + Tvm_trips + trip_to_mem; + } else { + *Tdmdl = TWait + UrgentExtraLatency; + } + +#ifdef __DML_VBA_ALLOW_DELTA__ + if (DynamicMetadataEnable == false) { + *Tdmdl = 0.0; + } +#endif + + if (DynamicMetadataEnable == true) { + if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) { + *NotEnoughTimeForDynamicMetadata = true; + dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__); + dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf); + dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec); + dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, Tdmsks); + dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *Tdmdl); + } else { + *NotEnoughTimeForDynamicMetadata = false; + } + } else { + *NotEnoughTimeForDynamicMetadata = false; + } + + *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); + + if (myPipe->ScalerEnabled) + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + else + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + + DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + + DISPCLKCycles = DISPCLKDelaySubtotal; + + if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) + return true; + + *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles); + dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock); + dml_print("DML::%s: DPPCLK: %f\n", __func__, myPipe->DPPCLK); + dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles); + dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->DISPCLK); + dml_print("DML::%s: DSCDelay: %d\n", __func__, DSCDelay); + dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler); + dml_print("DML::%s: ODMCombineIsEnabled: %d\n", __func__, myPipe->ODMCombineIsEnabled); +#endif + + *DSTXAfterScaler = *DSTXAfterScaler + ((myPipe->ODMCombineIsEnabled) ? 18 : 0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH; + + if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP)) + *DSTYAfterScaler = 1; + else + *DSTYAfterScaler = 0; + + DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler; + *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); + *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__, *DSTXAfterScaler); +#endif + + MyError = false; + + Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1); + Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime; + Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime; + +#ifdef __DML_VBA_ALLOW_DELTA__ + if (!myPipe->DCCEnable) { + Tr0_trips = 0.0; + Tr0_trips_rounded = 0.0; + } +#endif + + if (!GPUVMEnable) { + Tvm_trips = 0.0; + Tvm_trips_rounded = 0.0; + } + + if (GPUVMEnable) { + if (GPUVMPageTableLevels >= 3) { + *Tno_bw = UrgentExtraLatency + trip_to_mem * ((GPUVMPageTableLevels - 2) - 1); + } else { + *Tno_bw = 0; + } + } else if (!myPipe->DCCEnable) { + *Tno_bw = LineTime; + } else { + *Tno_bw = LineTime / 4; + } + + if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10 || myPipe->SourcePixelFormat == dm_420_12) + bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4; + else + bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC; + + prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC; + prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime)); + + min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre; + Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4; + Tsw_oto = Lsw_oto * LineTime; + + prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC) / Tsw_oto; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML: HTotal: %d\n", myPipe->HTotal); + dml_print("DML: prefetch_bw_oto: %f\n", prefetch_bw_oto); + dml_print("DML: PrefetchSourceLinesY: %f\n", PrefetchSourceLinesY); + dml_print("DML: swath_width_luma_ub: %d\n", swath_width_luma_ub); + dml_print("DML: BytePerPixelY: %d\n", myPipe->BytePerPixelY); + dml_print("DML: Tsw_oto: %f\n", Tsw_oto); +#endif + + if (GPUVMEnable == true) + Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_trips, LineTime / 4.0); + else + Tvm_oto = LineTime / 4.0; + + if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { + Tr0_oto = dml_max4((MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, Tr0_trips, // PREVIOUS_ERROR (missing this term) + LineTime - Tvm_oto, + LineTime / 4); + } else { + Tr0_oto = (LineTime - Tvm_oto) / 2.0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips); + dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips); + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, MetaRowByte); + dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte); + dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow); + dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor); + dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto); + dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto); + dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto); +#endif + + Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0; + Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; + dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto; + dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); + dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0; + Tpre_rounded = dst_y_prefetch_equ * LineTime; + + dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor); + + if (prefetch_sw_bytes < dep_bytes) + prefetch_sw_bytes = 2 * dep_bytes; + + dml_print("DML: dst_y_prefetch_oto: %f\n", dst_y_prefetch_oto); + dml_print("DML: Tvm_oto_lines: %f\n", Tvm_oto_lines); + dml_print("DML: Tr0_oto_lines: %f\n", Tr0_oto_lines); + dml_print("DML: Lsw_oto: %f\n", Lsw_oto); + dml_print("DML: LineTime: %f\n", LineTime); + dml_print("DML: dst_y_prefetch_equ: %f (after round)\n", dst_y_prefetch_equ); + + dml_print("DML: LineTime: %f\n", LineTime); + dml_print("DML: VStartup: %d\n", VStartup); + dml_print("DML: Tvstartup: %fus - time between vstartup and first pixel of active\n", VStartup * LineTime); + dml_print("DML: TSetup: %fus - time from vstartup to vready\n", *TSetup); + dml_print("DML: TCalc: %fus - time for calculations in dchub starting at vready\n", TCalc); + dml_print("DML: TWait: %fus - time for fabric to become ready max(pstate exit,cstate enter/exit, urgent latency) after TCalc\n", TWait); + dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf); + dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec); + dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks); + dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", *Tdmdl_vm); + dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl); + dml_print("DML: DSTXAfterScaler: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", *DSTXAfterScaler); + dml_print("DML: DSTYAfterScaler: %f lines - number of lines of pipeline and buffer delay after scaler \n", *DSTYAfterScaler); + + *PrefetchBandwidth = 0; + *DestinationLinesToRequestVMInVBlank = 0; + *DestinationLinesToRequestRowInVBlank = 0; + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + if (dst_y_prefetch_equ > 1) { + double PrefetchBandwidth1; + double PrefetchBandwidth2; + double PrefetchBandwidth3; + double PrefetchBandwidth4; + + if (Tpre_rounded - *Tno_bw > 0) { + PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor + + prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw); + Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1; + } else { + PrefetchBandwidth1 = 0; + } + + if (VStartup == MaxVStartup && Tsw_est1 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) { + PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw); + } + + if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0) + PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded); + else + PrefetchBandwidth2 = 0; + + if (Tpre_rounded - Tvm_trips_rounded > 0) { + PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor + + prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded); + Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3; + } else { + PrefetchBandwidth3 = 0; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded); + dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded); + dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3); +#endif + if (VStartup == MaxVStartup && Tsw_est3 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded > 0) { + PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) + / (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded); + } + + if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0) + PrefetchBandwidth4 = prefetch_sw_bytes / (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded); + else + PrefetchBandwidth4 = 0; + + { + bool Case1OK; + bool Case2OK; + bool Case3OK; + + if (PrefetchBandwidth1 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= Tvm_trips_rounded + && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) { + Case1OK = true; + } else { + Case1OK = false; + } + } else { + Case1OK = false; + } + + if (PrefetchBandwidth2 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= Tvm_trips_rounded + && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) { + Case2OK = true; + } else { + Case2OK = false; + } + } else { + Case2OK = false; + } + + if (PrefetchBandwidth3 > 0) { + if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < Tvm_trips_rounded + && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) { + Case3OK = true; + } else { + Case3OK = false; + } + } else { + Case3OK = false; + } + + if (Case1OK) { + prefetch_bw_equ = PrefetchBandwidth1; + } else if (Case2OK) { + prefetch_bw_equ = PrefetchBandwidth2; + } else if (Case3OK) { + prefetch_bw_equ = PrefetchBandwidth3; + } else { + prefetch_bw_equ = PrefetchBandwidth4; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK); + dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK); + dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK); + dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ); +#endif + + if (prefetch_bw_equ > 0) { + if (GPUVMEnable == true) { + Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4); + } else { + Tvm_equ = LineTime / 4; + } + + if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { + Tr0_equ = dml_max4( + (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ, + Tr0_trips, + (LineTime - Tvm_equ) / 2, + LineTime / 4); + } else { + Tr0_equ = (LineTime - Tvm_equ) / 2; + } + } else { + Tvm_equ = 0; + Tr0_equ = 0; + dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__); + } + } + + if (dst_y_prefetch_oto < dst_y_prefetch_equ) { + *DestinationLinesForPrefetch = dst_y_prefetch_oto; + TimeForFetchingMetaPTE = Tvm_oto; + TimeForFetchingRowInVBlank = Tr0_oto; + *PrefetchBandwidth = prefetch_bw_oto; + } else { + *DestinationLinesForPrefetch = dst_y_prefetch_equ; + TimeForFetchingMetaPTE = Tvm_equ; + TimeForFetchingRowInVBlank = Tr0_equ; + *PrefetchBandwidth = prefetch_bw_equ; + } + + *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; + + *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0; + +#ifdef __DML_VBA_ALLOW_DELTA__ + LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch + // See note above dated 5/30/2018 + // - ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ? + - ((GPUVMEnable || myPipe->DCCEnable) ? (*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) : 0.0); // TODO: Did someone else add this?? +#else + LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; +#endif + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch); + dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank); + dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); + dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank); + dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY); + dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData); +#endif + + if (LinesToRequestPrefetchPixelData > 0 && prefetch_bw_equ > 0) { + + *VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData; + *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY); + dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY); + dml_print("DML::%s: VInitPreFillY = %f\n", __func__, VInitPreFillY); +#endif + if ((SwathHeightY > 4) && (VInitPreFillY > 3)) { + if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) { + *VRatioPrefetchY = dml_max( + (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData, + (double) MaxNumSwathY * SwathHeightY / (LinesToRequestPrefetchPixelData - (VInitPreFillY - 3.0) / 2.0)); + *VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0); + } else { + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + *VRatioPrefetchY = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY); + dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY); + dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY); +#endif + } + + *VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData; + *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC); + dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC); + dml_print("DML::%s: VInitPreFillC = %f\n", __func__, VInitPreFillC); +#endif + if ((SwathHeightC > 4)) { + if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) { + *VRatioPrefetchC = dml_max( + *VRatioPrefetchC, + (double) MaxNumSwathC * SwathHeightC / (LinesToRequestPrefetchPixelData - (VInitPreFillC - 3.0) / 2.0)); + *VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0); + } else { + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + *VRatioPrefetchC = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC); + dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC); + dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC); +#endif + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY); + dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); +#endif + + *RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub / LineTime; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n", __func__, *RequiredPrefetchPixDataBWLuma); +#endif + + *RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelC * swath_width_chroma_ub + / LineTime; + } else { + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + dml_print("DML: LinesToRequestPrefetchPixelData: %f, should be > 0\n", LinesToRequestPrefetchPixelData); + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + *RequiredPrefetchPixDataBWChroma = 0; + } + + dml_print( + "DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n", + (double) LinesToRequestPrefetchPixelData * LineTime + 2.0 * TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE); + dml_print("DML: Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE); + dml_print("DML: Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank); + dml_print( + "DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", + (double) LinesToRequestPrefetchPixelData * LineTime); + dml_print("DML: To: %fus - time for propagation from scaler to optc\n", + (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / + (double) myPipe->HTotal)) * LineTime); + dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n"); + dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", + VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank + - (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup); + dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow); + + } else { + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + } + + { + double prefetch_vm_bw; + double prefetch_row_bw; + + if (PDEAndMetaPTEBytesFrame == 0) { + prefetch_vm_bw = 0; + } else if (*DestinationLinesToRequestVMInVBlank > 0) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); + dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor); + dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank); + dml_print("DML::%s: LineTime = %f\n", __func__, LineTime); +#endif + prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw); +#endif + } else { + prefetch_vm_bw = 0; + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + } + + if (MetaRowByte + PixelPTEBytesPerRow == 0) { + prefetch_row_bw = 0; + } else if (*DestinationLinesToRequestRowInVBlank > 0) { + prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte); + dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow); + dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank); + dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw); +#endif + } else { + prefetch_row_bw = 0; + MyError = true; + dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); + } + + *prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw); + } + + if (MyError) { + *PrefetchBandwidth = 0; + TimeForFetchingMetaPTE = 0; + TimeForFetchingRowInVBlank = 0; + *DestinationLinesToRequestVMInVBlank = 0; + *DestinationLinesToRequestRowInVBlank = 0; + *DestinationLinesForPrefetch = 0; + LinesToRequestPrefetchPixelData = 0; + *VRatioPrefetchY = 0; + *VRatioPrefetchC = 0; + *RequiredPrefetchPixDataBWLuma = 0; + *RequiredPrefetchPixDataBWChroma = 0; + } + + return MyError; +} + +static double RoundToDFSGranularityUp(double Clock, double VCOSpeed) +{ + return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1); +} + +static double RoundToDFSGranularityDown(double Clock, double VCOSpeed) +{ + return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1); +} + +static void CalculateDCCConfiguration( + bool DCCEnabled, + bool DCCProgrammingAssumesScanDirectionUnknown, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceWidthLuma, + unsigned int SurfaceWidthChroma, + unsigned int SurfaceHeightLuma, + unsigned int SurfaceHeightChroma, + double DETBufferSize, + unsigned int RequestHeight256ByteLuma, + unsigned int RequestHeight256ByteChroma, + enum dm_swizzle_mode TilingFormat, + unsigned int BytePerPixelY, + unsigned int BytePerPixelC, + double BytePerPixelDETY, + double BytePerPixelDETC, + enum scan_direction_class ScanOrientation, + unsigned int *MaxUncompressedBlockLuma, + unsigned int *MaxUncompressedBlockChroma, + unsigned int *MaxCompressedBlockLuma, + unsigned int *MaxCompressedBlockChroma, + unsigned int *IndependentBlockLuma, + unsigned int *IndependentBlockChroma) +{ + int yuv420; + int horz_div_l; + int horz_div_c; + int vert_div_l; + int vert_div_c; + + int swath_buf_size; + double detile_buf_vp_horz_limit; + double detile_buf_vp_vert_limit; + + int MAS_vp_horz_limit; + int MAS_vp_vert_limit; + int max_vp_horz_width; + int max_vp_vert_height; + int eff_surf_width_l; + int eff_surf_width_c; + int eff_surf_height_l; + int eff_surf_height_c; + + int full_swath_bytes_horz_wc_l; + int full_swath_bytes_horz_wc_c; + int full_swath_bytes_vert_wc_l; + int full_swath_bytes_vert_wc_c; + int req128_horz_wc_l; + int req128_horz_wc_c; + int req128_vert_wc_l; + int req128_vert_wc_c; + int segment_order_horz_contiguous_luma; + int segment_order_horz_contiguous_chroma; + int segment_order_vert_contiguous_luma; + int segment_order_vert_contiguous_chroma; + + typedef enum { + REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA + } RequestType; + RequestType RequestLuma; + RequestType RequestChroma; + + yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12) ? 1 : 0); + horz_div_l = 1; + horz_div_c = 1; + vert_div_l = 1; + vert_div_c = 1; + + if (BytePerPixelY == 1) + vert_div_l = 0; + if (BytePerPixelC == 1) + vert_div_c = 0; + if (BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x)) + horz_div_l = 0; + if (BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x)) + horz_div_c = 0; + + if (BytePerPixelC == 0) { + swath_buf_size = DETBufferSize / 2 - 2 * 256; + detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); + detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); + } else { + swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + detile_buf_vp_horz_limit = (double) swath_buf_size + / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + + (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); + detile_buf_vp_vert_limit = (double) swath_buf_size + / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma / (1 + vert_div_c) / (1 + yuv420)); + } + + if (SourcePixelFormat == dm_420_10) { + detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit; + detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit; + } + + detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16); + detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16); + + MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760; + MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); + max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); + eff_surf_width_c = eff_surf_width_l / (1 + yuv420); + eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); + eff_surf_height_c = eff_surf_height_l / (1 + yuv420); + + full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY; + full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma; + if (BytePerPixelC > 0) { + full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC; + full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma; + } else { + full_swath_bytes_horz_wc_c = 0; + full_swath_bytes_vert_wc_c = 0; + } + + if (SourcePixelFormat == dm_420_10) { + full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + } + + if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { + req128_horz_wc_l = 0; + req128_horz_wc_c = 0; + } else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l + full_swath_bytes_horz_wc_c <= DETBufferSize) { + req128_horz_wc_l = 0; + req128_horz_wc_c = 1; + } else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { + req128_horz_wc_l = 1; + req128_horz_wc_c = 0; + } else { + req128_horz_wc_l = 1; + req128_horz_wc_c = 1; + } + + if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) { + req128_vert_wc_l = 0; + req128_vert_wc_c = 0; + } else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 * full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSize) { + req128_vert_wc_l = 0; + req128_vert_wc_c = 1; + } else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c && full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) { + req128_vert_wc_l = 1; + req128_vert_wc_c = 0; + } else { + req128_vert_wc_l = 1; + req128_vert_wc_c = 1; + } + + if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) { + segment_order_horz_contiguous_luma = 0; + } else { + segment_order_horz_contiguous_luma = 1; + } + if ((BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x)) + || (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) { + segment_order_vert_contiguous_luma = 0; + } else { + segment_order_vert_contiguous_luma = 1; + } + if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) { + segment_order_horz_contiguous_chroma = 0; + } else { + segment_order_horz_contiguous_chroma = 1; + } + if ((BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x)) + || (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) { + segment_order_vert_contiguous_chroma = 0; + } else { + segment_order_vert_contiguous_chroma = 1; + } + + if (DCCProgrammingAssumesScanDirectionUnknown == true) { + if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0) { + RequestLuma = REQ_256Bytes; + } else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) || (req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0)) { + RequestLuma = REQ_128BytesNonContiguous; + } else { + RequestLuma = REQ_128BytesContiguous; + } + if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0) { + RequestChroma = REQ_256Bytes; + } else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) || (req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0)) { + RequestChroma = REQ_128BytesNonContiguous; + } else { + RequestChroma = REQ_128BytesContiguous; + } + } else if (ScanOrientation != dm_vert) { + if (req128_horz_wc_l == 0) { + RequestLuma = REQ_256Bytes; + } else if (segment_order_horz_contiguous_luma == 0) { + RequestLuma = REQ_128BytesNonContiguous; + } else { + RequestLuma = REQ_128BytesContiguous; + } + if (req128_horz_wc_c == 0) { + RequestChroma = REQ_256Bytes; + } else if (segment_order_horz_contiguous_chroma == 0) { + RequestChroma = REQ_128BytesNonContiguous; + } else { + RequestChroma = REQ_128BytesContiguous; + } + } else { + if (req128_vert_wc_l == 0) { + RequestLuma = REQ_256Bytes; + } else if (segment_order_vert_contiguous_luma == 0) { + RequestLuma = REQ_128BytesNonContiguous; + } else { + RequestLuma = REQ_128BytesContiguous; + } + if (req128_vert_wc_c == 0) { + RequestChroma = REQ_256Bytes; + } else if (segment_order_vert_contiguous_chroma == 0) { + RequestChroma = REQ_128BytesNonContiguous; + } else { + RequestChroma = REQ_128BytesContiguous; + } + } + + if (RequestLuma == REQ_256Bytes) { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 256; + *IndependentBlockLuma = 0; + } else if (RequestLuma == REQ_128BytesContiguous) { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 128; + *IndependentBlockLuma = 128; + } else { + *MaxUncompressedBlockLuma = 256; + *MaxCompressedBlockLuma = 64; + *IndependentBlockLuma = 64; + } + + if (RequestChroma == REQ_256Bytes) { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 256; + *IndependentBlockChroma = 0; + } else if (RequestChroma == REQ_128BytesContiguous) { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 128; + *IndependentBlockChroma = 128; + } else { + *MaxUncompressedBlockChroma = 256; + *MaxCompressedBlockChroma = 64; + *IndependentBlockChroma = 64; + } + + if (DCCEnabled != true || BytePerPixelC == 0) { + *MaxUncompressedBlockChroma = 0; + *MaxCompressedBlockChroma = 0; + *IndependentBlockChroma = 0; + } + + if (DCCEnabled != true) { + *MaxUncompressedBlockLuma = 0; + *MaxCompressedBlockLuma = 0; + *IndependentBlockLuma = 0; + } +} + +static double CalculatePrefetchSourceLines( + struct display_mode_lib *mode_lib, + double VRatio, + double vtaps, + bool Interlace, + bool ProgressiveToInterlaceUnitInOPP, + unsigned int SwathHeight, + unsigned int ViewportYStart, + double *VInitPreFill, + unsigned int *MaxNumSwath) +{ + struct vba_vars_st *v = &mode_lib->vba; + unsigned int MaxPartialSwath; + + if (ProgressiveToInterlaceUnitInOPP) + *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); + else + *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); + + if (!v->IgnoreViewportPositioning) { + + *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + + if (*VInitPreFill > 1.0) + MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; + else + MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; + MaxPartialSwath = dml_max(1U, MaxPartialSwath); + + } else { + + if (ViewportYStart != 0) + dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); + + *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + + if (*VInitPreFill > 1.0) + MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; + else + MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) % SwathHeight; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VRatio = %f\n", __func__, VRatio); + dml_print("DML::%s: vtaps = %f\n", __func__, vtaps); + dml_print("DML::%s: VInitPreFill = %f\n", __func__, *VInitPreFill); + dml_print("DML::%s: ProgressiveToInterlaceUnitInOPP = %d\n", __func__, ProgressiveToInterlaceUnitInOPP); + dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning); + dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight); + dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath); + dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath); + dml_print("DML::%s: Prefetch source lines = %d\n", __func__, *MaxNumSwath * SwathHeight + MaxPartialSwath); +#endif + return *MaxNumSwath * SwathHeight + MaxPartialSwath; +} + +static unsigned int CalculateVMAndRowBytes( + struct display_mode_lib *mode_lib, + bool DCCEnable, + unsigned int BlockHeight256Bytes, + unsigned int BlockWidth256Bytes, + enum source_format_class SourcePixelFormat, + unsigned int SurfaceTiling, + unsigned int BytePerPixel, + enum scan_direction_class ScanDirection, + unsigned int SwathWidth, + unsigned int ViewportHeight, + bool GPUVMEnable, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + unsigned int GPUVMMinPageSize, + unsigned int HostVMMinPageSize, + unsigned int PTEBufferSizeInRequests, + unsigned int Pitch, + unsigned int DCCMetaPitch, + unsigned int *MacroTileWidth, + unsigned int *MetaRowByte, + unsigned int *PixelPTEBytesPerRow, + bool *PTEBufferSizeNotExceeded, + int *dpte_row_width_ub, + unsigned int *dpte_row_height, + unsigned int *MetaRequestWidth, + unsigned int *MetaRequestHeight, + unsigned int *meta_row_width, + unsigned int *meta_row_height, + int *vm_group_bytes, + unsigned int *dpte_group_bytes, + unsigned int *PixelPTEReqWidth, + unsigned int *PixelPTEReqHeight, + unsigned int *PTERequestSize, + int *DPDE0BytesFrame, + int *MetaPTEBytesFrame) +{ + struct vba_vars_st *v = &mode_lib->vba; + unsigned int MPDEBytesFrame; + unsigned int DCCMetaSurfaceBytes; + unsigned int MacroTileSizeBytes; + unsigned int MacroTileHeight; + unsigned int ExtraDPDEBytesFrame; + unsigned int PDEAndMetaPTEBytesFrame; + unsigned int PixelPTEReqHeightPTEs = 0; + unsigned int HostVMDynamicLevels = 0; + double FractionOfPTEReturnDrop; + + if (GPUVMEnable == true && HostVMEnable == true) { + if (HostVMMinPageSize < 2048) { + HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; + } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + } else { + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + } + } + + *MetaRequestHeight = 8 * BlockHeight256Bytes; + *MetaRequestWidth = 8 * BlockWidth256Bytes; + if (ScanDirection != dm_vert) { + *meta_row_height = *MetaRequestHeight; + *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; + *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + } else { + *meta_row_height = *MetaRequestWidth; + *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; + *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + } + DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + if (GPUVMEnable == true) { + *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1); + } else { + *MetaPTEBytesFrame = 0; + MPDEBytesFrame = 0; + } + + if (DCCEnable != true) { + *MetaPTEBytesFrame = 0; + MPDEBytesFrame = 0; + *MetaRowByte = 0; + } + + if (SurfaceTiling == dm_sw_linear) { + MacroTileSizeBytes = 256; + MacroTileHeight = BlockHeight256Bytes; + } else { + MacroTileSizeBytes = 65536; + MacroTileHeight = 16 * BlockHeight256Bytes; + } + *MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight; + + if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) { + if (ScanDirection != dm_vert) { + *DPDE0BytesFrame = 64 + * (dml_ceil( + ((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) + / (8 * 2097152), + 1) + 1); + } else { + *DPDE0BytesFrame = 64 + * (dml_ceil( + ((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) + / (8 * 2097152), + 1) + 1); + } + ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2); + } else { + *DPDE0BytesFrame = 0; + ExtraDPDEBytesFrame = 0; + } + + PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame); + dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame); + dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame); + dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame); + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); +#endif + + if (HostVMEnable == true) { + PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels); + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame); +#endif + + if (SurfaceTiling == dm_sw_linear) { + PixelPTEReqHeightPTEs = 1; + *PixelPTEReqHeight = 1; + *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PTERequestSize = 64; + FractionOfPTEReturnDrop = 0; + } else if (MacroTileSizeBytes == 4096) { + PixelPTEReqHeightPTEs = 1; + *PixelPTEReqHeight = MacroTileHeight; + *PixelPTEReqWidth = 8 * *MacroTileWidth; + *PTERequestSize = 64; + if (ScanDirection != dm_vert) + FractionOfPTEReturnDrop = 0; + else + FractionOfPTEReturnDrop = 7 / 8; + } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { + PixelPTEReqHeightPTEs = 16; + *PixelPTEReqHeight = 16 * BlockHeight256Bytes; + *PixelPTEReqWidth = 16 * BlockWidth256Bytes; + *PTERequestSize = 128; + FractionOfPTEReturnDrop = 0; + } else { + PixelPTEReqHeightPTEs = 1; + *PixelPTEReqHeight = MacroTileHeight; + *PixelPTEReqWidth = 8 * *MacroTileWidth; + *PTERequestSize = 64; + FractionOfPTEReturnDrop = 0; + } + + if (SurfaceTiling == dm_sw_linear) { + *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; + } else if (ScanDirection != dm_vert) { + *dpte_row_height = *PixelPTEReqHeight; + *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; + } else { + *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; + } + + if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) <= 64 * PTEBufferSizeInRequests) { + *PTEBufferSizeNotExceeded = true; + } else { + *PTEBufferSizeNotExceeded = false; + } + + if (GPUVMEnable != true) { + *PixelPTEBytesPerRow = 0; + *PTEBufferSizeNotExceeded = true; + } + + dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n", *MetaPTEBytesFrame); + + if (HostVMEnable == true) { + *PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels); + } + + if (HostVMEnable == true) { + *vm_group_bytes = 512; + *dpte_group_bytes = 512; + } else if (GPUVMEnable == true) { + *vm_group_bytes = 2048; + if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) { + *dpte_group_bytes = 512; + } else { + *dpte_group_bytes = 2048; + } + } else { + *vm_group_bytes = 0; + *dpte_group_bytes = 0; + } + return PDEAndMetaPTEBytesFrame; +} + +static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib) +{ + struct vba_vars_st *v = &mode_lib->vba; + unsigned int j, k; + double HostVMInefficiencyFactor = 1.0; + bool NoChromaPlanes = true; + int ReorderBytes; + double VMDataOnlyReturnBW; + double MaxTotalRDBandwidth = 0; + int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb]; + + v->WritebackDISPCLK = 0.0; + v->DISPCLKWithRamping = 0; + v->DISPCLKWithoutRamping = 0; + v->GlobalDPPCLK = 0.0; + /* DAL custom code: need to update ReturnBW in case min dcfclk is overriden */ + { + double IdealFabricAndSDPPortBandwidthPerState = dml_min( + v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb], + v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn); + double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth; + if (v->HostVMEnable != true) { + v->ReturnBW = dml_min( + IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0); + } else { + v->ReturnBW = dml_min( + IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0); + } + } + /* End DAL custom code */ + + // DISPCLK and DPPCLK Calculation + // + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->WritebackEnable[k]) { + v->WritebackDISPCLK = dml_max( + v->WritebackDISPCLK, + dml31_CalculateWriteBackDISPCLK( + v->WritebackPixelFormat[k], + v->PixelClock[k], + v->WritebackHRatio[k], + v->WritebackVRatio[k], + v->WritebackHTaps[k], + v->WritebackVTaps[k], + v->WritebackSourceWidth[k], + v->WritebackDestinationWidth[k], + v->HTotal[k], + v->WritebackLineBufferSize)); + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->HRatio[k] > 1) { + v->PSCL_THROUGHPUT_LUMA[k] = dml_min( + v->MaxDCHUBToPSCLThroughput, + v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1)); + } else { + v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput); + } + + v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k] + * dml_max( + v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), + dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0)); + + if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) { + v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k]; + } + + if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12 + && v->SourcePixelFormat[k] != dm_rgbe_alpha)) { + v->PSCL_THROUGHPUT_CHROMA[k] = 0.0; + v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma; + } else { + if (v->HRatioChroma[k] > 1) { + v->PSCL_THROUGHPUT_CHROMA[k] = dml_min( + v->MaxDCHUBToPSCLThroughput, + v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0)); + } else { + v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput); + } + v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k] + * dml_max3( + v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]), + v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k], + 1.0); + + if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) { + v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k]; + } + + v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma); + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] != k) + continue; + if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) { + v->DISPCLKWithRamping = dml_max( + v->DISPCLKWithRamping, + v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) + * (1 + v->DISPCLKRampingMargin / 100)); + v->DISPCLKWithoutRamping = dml_max( + v->DISPCLKWithoutRamping, + v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)); + } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) { + v->DISPCLKWithRamping = dml_max( + v->DISPCLKWithRamping, + v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) + * (1 + v->DISPCLKRampingMargin / 100)); + v->DISPCLKWithoutRamping = dml_max( + v->DISPCLKWithoutRamping, + v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)); + } else { + v->DISPCLKWithRamping = dml_max( + v->DISPCLKWithRamping, + v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100)); + v->DISPCLKWithoutRamping = dml_max( + v->DISPCLKWithoutRamping, + v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)); + } + } + + v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK); + v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK); + + ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0); + v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed); + v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed); + v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown( + v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz, + v->DISPCLKDPPCLKVCOSpeed); + if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) { + v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity; + } else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) { + v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity; + } else { + v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity; + } + v->DISPCLK = v->DISPCLK_calculated; + DTRACE(" dispclk_mhz (calculated) = %f", v->DISPCLK_calculated); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); + v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]); + } + v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed); + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1); + DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]); + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->DPPCLK[k] = v->DPPCLK_calculated[k]; + } + + // Urgent and B P-State/DRAM Clock Change Watermark + DTRACE(" dcfclk_mhz = %f", v->DCFCLK); + DTRACE(" return_bus_bw = %f", v->ReturnBW); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + CalculateBytePerPixelAnd256BBlockSizes( + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + &v->BytePerPixelY[k], + &v->BytePerPixelC[k], + &v->BytePerPixelDETY[k], + &v->BytePerPixelDETC[k], + &v->BlockHeight256BytesY[k], + &v->BlockHeight256BytesC[k], + &v->BlockWidth256BytesY[k], + &v->BlockWidth256BytesC[k]); + } + + CalculateSwathWidth( + false, + v->NumberOfActivePlanes, + v->SourcePixelFormat, + v->SourceScan, + v->ViewportWidth, + v->ViewportHeight, + v->SurfaceWidthY, + v->SurfaceWidthC, + v->SurfaceHeightY, + v->SurfaceHeightC, + v->ODMCombineEnabled, + v->BytePerPixelY, + v->BytePerPixelC, + v->BlockHeight256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesY, + v->BlockWidth256BytesC, + v->BlendingAndTiming, + v->HActive, + v->HRatio, + v->DPPPerPlane, + v->SwathWidthSingleDPPY, + v->SwathWidthSingleDPPC, + v->SwathWidthY, + v->SwathWidthC, + v->dummyinteger3, + v->dummyinteger4, + v->swath_width_luma_ub, + v->swath_width_chroma_ub); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k]) + * v->VRatio[k]; + v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k]) + * v->VRatioChroma[k]; + DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]); + } + + // DCFCLK Deep Sleep + CalculateDCFCLKDeepSleep( + mode_lib, + v->NumberOfActivePlanes, + v->BytePerPixelY, + v->BytePerPixelC, + v->VRatio, + v->VRatioChroma, + v->SwathWidthY, + v->SwathWidthC, + v->DPPPerPlane, + v->HRatio, + v->HRatioChroma, + v->PixelClock, + v->PSCL_THROUGHPUT_LUMA, + v->PSCL_THROUGHPUT_CHROMA, + v->DPPCLK, + v->ReadBandwidthPlaneLuma, + v->ReadBandwidthPlaneChroma, + v->ReturnBusWidth, + &v->DCFCLKDeepSleep); + + // DSCCLK + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) { + v->DSCCLK_calculated[k] = 0.0; + } else { + if (v->OutputFormat[k] == dm_420) + v->DSCFormatFactor = 2; + else if (v->OutputFormat[k] == dm_444) + v->DSCFormatFactor = 1; + else if (v->OutputFormat[k] == dm_n422) + v->DSCFormatFactor = 2; + else + v->DSCFormatFactor = 1; + if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) + v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor + / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); + else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) + v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor + / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); + else + v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor + / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); + } + } + + // DSC Delay + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + double BPP = v->OutputBpp[k]; + + if (v->DSCEnabled[k] && BPP != 0) { + if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) { + v->DSCDelay[k] = dscceComputeDelay( + v->DSCInputBitPerComponent[k], + BPP, + dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + v->NumberOfDSCSlices[k], + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); + } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) { + v->DSCDelay[k] = 2 + * (dscceComputeDelay( + v->DSCInputBitPerComponent[k], + BPP, + dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + v->NumberOfDSCSlices[k] / 2.0, + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); + } else { + v->DSCDelay[k] = 4 + * (dscceComputeDelay( + v->DSCInputBitPerComponent[k], + BPP, + dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + v->NumberOfDSCSlices[k] / 4.0, + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); + } + v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + } else { + v->DSCDelay[k] = 0; + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) + for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes + if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j]) + v->DSCDelay[k] = v->DSCDelay[j]; + + // Prefetch + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + unsigned int PDEAndMetaPTEBytesFrameY; + unsigned int PixelPTEBytesPerRowY; + unsigned int MetaRowByteY; + unsigned int MetaRowByteC; + unsigned int PDEAndMetaPTEBytesFrameC; + unsigned int PixelPTEBytesPerRowC; + bool PTEBufferSizeNotExceededY; + bool PTEBufferSizeNotExceededC; + + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12 + || v->SourcePixelFormat[k] == dm_rgbe_alpha) { + if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) { + v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2; + v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma; + } else { + v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma; + v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma; + } + + PDEAndMetaPTEBytesFrameC = CalculateVMAndRowBytes( + mode_lib, + v->DCCEnable[k], + v->BlockHeight256BytesC[k], + v->BlockWidth256BytesC[k], + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + v->BytePerPixelC[k], + v->SourceScan[k], + v->SwathWidthC[k], + v->ViewportHeightChroma[k], + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMMinPageSize, + v->HostVMMinPageSize, + v->PTEBufferSizeInRequestsForChroma, + v->PitchC[k], + v->DCCMetaPitchC[k], + &v->MacroTileWidthC[k], + &MetaRowByteC, + &PixelPTEBytesPerRowC, + &PTEBufferSizeNotExceededC, + &v->dpte_row_width_chroma_ub[k], + &v->dpte_row_height_chroma[k], + &v->meta_req_width_chroma[k], + &v->meta_req_height_chroma[k], + &v->meta_row_width_chroma[k], + &v->meta_row_height_chroma[k], + &v->dummyinteger1, + &v->dummyinteger2, + &v->PixelPTEReqWidthC[k], + &v->PixelPTEReqHeightC[k], + &v->PTERequestSizeC[k], + &v->dpde0_bytes_per_frame_ub_c[k], + &v->meta_pte_bytes_per_frame_ub_c[k]); + + v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( + mode_lib, + v->VRatioChroma[k], + v->VTAPsChroma[k], + v->Interlace[k], + v->ProgressiveToInterlaceUnitInOPP, + v->SwathHeightC[k], + v->ViewportYStartC[k], + &v->VInitPreFillC[k], + &v->MaxNumSwathC[k]); + } else { + v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; + v->PTEBufferSizeInRequestsForChroma = 0; + PixelPTEBytesPerRowC = 0; + PDEAndMetaPTEBytesFrameC = 0; + MetaRowByteC = 0; + v->MaxNumSwathC[k] = 0; + v->PrefetchSourceLinesC[k] = 0; + } + + PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes( + mode_lib, + v->DCCEnable[k], + v->BlockHeight256BytesY[k], + v->BlockWidth256BytesY[k], + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + v->BytePerPixelY[k], + v->SourceScan[k], + v->SwathWidthY[k], + v->ViewportHeight[k], + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMMinPageSize, + v->HostVMMinPageSize, + v->PTEBufferSizeInRequestsForLuma, + v->PitchY[k], + v->DCCMetaPitchY[k], + &v->MacroTileWidthY[k], + &MetaRowByteY, + &PixelPTEBytesPerRowY, + &PTEBufferSizeNotExceededY, + &v->dpte_row_width_luma_ub[k], + &v->dpte_row_height[k], + &v->meta_req_width[k], + &v->meta_req_height[k], + &v->meta_row_width[k], + &v->meta_row_height[k], + &v->vm_group_bytes[k], + &v->dpte_group_bytes[k], + &v->PixelPTEReqWidthY[k], + &v->PixelPTEReqHeightY[k], + &v->PTERequestSizeY[k], + &v->dpde0_bytes_per_frame_ub_l[k], + &v->meta_pte_bytes_per_frame_ub_l[k]); + + v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( + mode_lib, + v->VRatio[k], + v->vtaps[k], + v->Interlace[k], + v->ProgressiveToInterlaceUnitInOPP, + v->SwathHeightY[k], + v->ViewportYStartY[k], + &v->VInitPreFillY[k], + &v->MaxNumSwathY[k]); + v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; + v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC; + v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC; + + CalculateRowBandwidth( + v->GPUVMEnable, + v->SourcePixelFormat[k], + v->VRatio[k], + v->VRatioChroma[k], + v->DCCEnable[k], + v->HTotal[k] / v->PixelClock[k], + MetaRowByteY, + MetaRowByteC, + v->meta_row_height[k], + v->meta_row_height_chroma[k], + PixelPTEBytesPerRowY, + PixelPTEBytesPerRowC, + v->dpte_row_height[k], + v->dpte_row_height_chroma[k], + &v->meta_row_bw[k], + &v->dpte_row_bw[k]); + } + + v->TotalDCCActiveDPP = 0; + v->TotalActiveDPP = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k]; + if (v->DCCEnable[k]) + v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k]; + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12 + || v->SourcePixelFormat[k] == dm_rgbe_alpha) + NoChromaPlanes = false; + } + + ReorderBytes = v->NumberOfChannels + * dml_max3( + v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, + v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, + v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + + VMDataOnlyReturnBW = dml_min( + dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn) + * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth + * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: v->ReturnBusWidth = %f\n", __func__, v->ReturnBusWidth); + dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK); + dml_print("DML::%s: v->FabricClock = %f\n", __func__, v->FabricClock); + dml_print("DML::%s: v->FabricDatapathToDCNDataReturn = %f\n", __func__, v->FabricDatapathToDCNDataReturn); + dml_print("DML::%s: v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = %f\n", __func__, v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency); + dml_print("DML::%s: v->DRAMSpeed = %f\n", __func__, v->DRAMSpeed); + dml_print("DML::%s: v->NumberOfChannels = %f\n", __func__, v->NumberOfChannels); + dml_print("DML::%s: v->DRAMChannelWidth = %f\n", __func__, v->DRAMChannelWidth); + dml_print("DML::%s: v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", __func__, v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly); + dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW); + dml_print("DML::%s: ReturnBW = %f\n", __func__, v->ReturnBW); +#endif + + if (v->GPUVMEnable && v->HostVMEnable) + HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW; + + v->UrgentExtraLatency = CalculateExtraLatency( + v->RoundTripPingLatencyCycles, + ReorderBytes, + v->DCFCLK, + v->TotalActiveDPP, + v->PixelChunkSizeInKByte, + v->TotalDCCActiveDPP, + v->MetaChunkSize, + v->ReturnBW, + v->GPUVMEnable, + v->HostVMEnable, + v->NumberOfActivePlanes, + v->DPPPerPlane, + v->dpte_group_bytes, + HostVMInefficiencyFactor, + v->HostVMMinPageSize, + v->HostVMMaxNonCachedPageTableLevels); + + v->TCalc = 24.0 / v->DCFCLKDeepSleep; + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] == k) { + if (v->WritebackEnable[k] == true) { + v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency + + CalculateWriteBackDelay( + v->WritebackPixelFormat[k], + v->WritebackHRatio[k], + v->WritebackVRatio[k], + v->WritebackVTaps[k], + v->WritebackDestinationWidth[k], + v->WritebackDestinationHeight[k], + v->WritebackSourceHeight[k], + v->HTotal[k]) / v->DISPCLK; + } else + v->WritebackDelay[v->VoltageLevel][k] = 0; + for (j = 0; j < v->NumberOfActivePlanes; ++j) { + if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) { + v->WritebackDelay[v->VoltageLevel][k] = dml_max( + v->WritebackDelay[v->VoltageLevel][k], + v->WritebackLatency + + CalculateWriteBackDelay( + v->WritebackPixelFormat[j], + v->WritebackHRatio[j], + v->WritebackVRatio[j], + v->WritebackVTaps[j], + v->WritebackDestinationWidth[j], + v->WritebackDestinationHeight[j], + v->WritebackSourceHeight[j], + v->HTotal[k]) / v->DISPCLK); + } + } + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) + for (j = 0; j < v->NumberOfActivePlanes; ++j) + if (v->BlendingAndTiming[k] == j) + v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->MaxVStartupLines[k] = + (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ? + dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) : + v->VTotal[k] - v->VActive[k] + - dml_max( + 1.0, + dml_ceil( + (double) v->WritebackDelay[v->VoltageLevel][k] + / (v->HTotal[k] / v->PixelClock[k]), + 1)); + if (v->MaxVStartupLines[k] > 1023) + v->MaxVStartupLines[k] = 1023; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]); + dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel); + dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]); +#endif + } + + v->MaximumMaxVStartupLines = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) + v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + + // VBA_DELTA + // We don't really care to iterate between the various prefetch modes + //v->PrefetchERROR = CalculateMinAndMaxPrefetchMode(v->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &v->MinPrefetchMode, &v->MaxPrefetchMode); + + v->UrgentLatency = CalculateUrgentLatency( + v->UrgentLatencyPixelDataOnly, + v->UrgentLatencyPixelMixedWithVMData, + v->UrgentLatencyVMDataOnly, + v->DoUrgentLatencyAdjustment, + v->UrgentLatencyAdjustmentFabricClockComponent, + v->UrgentLatencyAdjustmentFabricClockReference, + v->FabricClock); + + v->FractionOfUrgentBandwidth = 0.0; + v->FractionOfUrgentBandwidthImmediateFlip = 0.0; + + v->VStartupLines = __DML_VBA_MIN_VSTARTUP__; + + do { + double MaxTotalRDBandwidthNoUrgentBurst = 0.0; + bool DestinationLineTimesForPrefetchLessThan2 = false; + bool VRatioPrefetchMoreThan4 = false; + double TWait = CalculateTWait(PrefetchMode, v->DRAMClockChangeLatency, v->UrgentLatency, v->SREnterPlusExitTime); + MaxTotalRDBandwidth = 0; + + dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, v->VStartupLines); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + Pipe myPipe; + + myPipe.DPPCLK = v->DPPCLK[k]; + myPipe.DISPCLK = v->DISPCLK; + myPipe.PixelClock = v->PixelClock[k]; + myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep; + myPipe.DPPPerPlane = v->DPPPerPlane[k]; + myPipe.ScalerEnabled = v->ScalerEnabled[k]; + myPipe.SourceScan = v->SourceScan[k]; + myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k]; + myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k]; + myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k]; + myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k]; + myPipe.InterlaceEnable = v->Interlace[k]; + myPipe.NumberOfCursors = v->NumberOfCursors[k]; + myPipe.VBlank = v->VTotal[k] - v->VActive[k]; + myPipe.HTotal = v->HTotal[k]; + myPipe.DCCEnable = v->DCCEnable[k]; + myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1 + || v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1; + myPipe.SourcePixelFormat = v->SourcePixelFormat[k]; + myPipe.BytePerPixelY = v->BytePerPixelY[k]; + myPipe.BytePerPixelC = v->BytePerPixelC[k]; + myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP; + v->ErrorResult[k] = CalculatePrefetchSchedule( + mode_lib, + HostVMInefficiencyFactor, + &myPipe, + v->DSCDelay[k], + v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, + v->DPPCLKDelaySCL, + v->DPPCLKDelaySCLLBOnly, + v->DPPCLKDelayCNVCCursor, + v->DISPCLKDelaySubtotal, + (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), + v->OutputFormat[k], + v->MaxInterDCNTileRepeaters, + dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + v->MaxVStartupLines[k], + v->GPUVMMaxPageTableLevels, + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->HostVMMinPageSize, + v->DynamicMetadataEnable[k], + v->DynamicMetadataVMEnabled, + v->DynamicMetadataLinesBeforeActiveRequired[k], + v->DynamicMetadataTransmittedBytes[k], + v->UrgentLatency, + v->UrgentExtraLatency, + v->TCalc, + v->PDEAndMetaPTEBytesFrame[k], + v->MetaRowByte[k], + v->PixelPTEBytesPerRow[k], + v->PrefetchSourceLinesY[k], + v->SwathWidthY[k], + v->VInitPreFillY[k], + v->MaxNumSwathY[k], + v->PrefetchSourceLinesC[k], + v->SwathWidthC[k], + v->VInitPreFillC[k], + v->MaxNumSwathC[k], + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + v->SwathHeightY[k], + v->SwathHeightC[k], + TWait, + &v->DSTXAfterScaler[k], + &v->DSTYAfterScaler[k], + &v->DestinationLinesForPrefetch[k], + &v->PrefetchBandwidth[k], + &v->DestinationLinesToRequestVMInVBlank[k], + &v->DestinationLinesToRequestRowInVBlank[k], + &v->VRatioPrefetchY[k], + &v->VRatioPrefetchC[k], + &v->RequiredPrefetchPixDataBWLuma[k], + &v->RequiredPrefetchPixDataBWChroma[k], + &v->NotEnoughTimeForDynamicMetadata[k], + &v->Tno_bw[k], + &v->prefetch_vmrow_bw[k], + &v->Tdmdl_vm[k], + &v->Tdmdl[k], + &v->TSetup[k], + &v->VUpdateOffsetPix[k], + &v->VUpdateWidthPix[k], + &v->VReadyOffsetPix[k]); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]); +#endif + v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + } + + v->NoEnoughUrgentLatencyHiding = false; + v->NoEnoughUrgentLatencyHidingPre = false; + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k]; + v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k]; + + CalculateUrgentBurstFactor( + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + v->SwathHeightY[k], + v->SwathHeightC[k], + v->HTotal[k] / v->PixelClock[k], + v->UrgentLatency, + v->CursorBufferSize, + v->CursorWidth[k][0], + v->CursorBPP[k][0], + v->VRatio[k], + v->VRatioChroma[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + v->DETBufferSizeY[k], + v->DETBufferSizeC[k], + &v->UrgBurstFactorCursor[k], + &v->UrgBurstFactorLuma[k], + &v->UrgBurstFactorChroma[k], + &v->NoUrgentLatencyHiding[k]); + + CalculateUrgentBurstFactor( + v->swath_width_luma_ub[k], + v->swath_width_chroma_ub[k], + v->SwathHeightY[k], + v->SwathHeightC[k], + v->HTotal[k] / v->PixelClock[k], + v->UrgentLatency, + v->CursorBufferSize, + v->CursorWidth[k][0], + v->CursorBPP[k][0], + v->VRatioPrefetchY[k], + v->VRatioPrefetchC[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + v->DETBufferSizeY[k], + v->DETBufferSizeC[k], + &v->UrgBurstFactorCursorPre[k], + &v->UrgBurstFactorLumaPre[k], + &v->UrgBurstFactorChromaPre[k], + &v->NoUrgentLatencyHidingPre[k]); + + MaxTotalRDBandwidth = MaxTotalRDBandwidth + + dml_max3( + v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k], + v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k] + + v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k] + + v->cursor_bw[k] * v->UrgBurstFactorCursor[k] + + v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]), + v->DPPPerPlane[k] + * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k] + + v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]); + + MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst + + dml_max3( + v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k], + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k] + + v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]), + v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + + v->cursor_bw_pre[k]); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]); + dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]); + + dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]); + dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]); + + dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]); + dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]); + dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]); + dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]); + dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]); + dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]); + dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]); + dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]); + dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]); + dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst); +#endif + + if (v->DestinationLinesForPrefetch[k] < 2) + DestinationLineTimesForPrefetchLessThan2 = true; + + if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4) + VRatioPrefetchMoreThan4 = true; + + if (v->NoUrgentLatencyHiding[k] == true) + v->NoEnoughUrgentLatencyHiding = true; + + if (v->NoUrgentLatencyHidingPre[k] == true) + v->NoEnoughUrgentLatencyHidingPre = true; + } + + v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f \n", __func__, MaxTotalRDBandwidthNoUrgentBurst); + dml_print("DML::%s: ReturnBW=%f \n", __func__, v->ReturnBW); + dml_print("DML::%s: FractionOfUrgentBandwidth=%f \n", __func__, v->FractionOfUrgentBandwidth); +#endif + + if (MaxTotalRDBandwidth <= v->ReturnBW && v->NoEnoughUrgentLatencyHiding == 0 && v->NoEnoughUrgentLatencyHidingPre == 0 + && !VRatioPrefetchMoreThan4 && !DestinationLineTimesForPrefetchLessThan2) + v->PrefetchModeSupported = true; + else { + v->PrefetchModeSupported = false; + dml_print("DML::%s: ***failed***. Bandwidth violation. Results are NOT valid\n", __func__); + dml_print("DML::%s: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", __func__, MaxTotalRDBandwidth, v->ReturnBW); + dml_print("DML::%s: VRatioPrefetch %s more than 4\n", __func__, (VRatioPrefetchMoreThan4) ? "is" : "is not"); + dml_print("DML::%s: DestinationLines for Prefetch %s less than 2\n", __func__, (DestinationLineTimesForPrefetchLessThan2) ? "is" : "is not"); + } + + // PREVIOUS_ERROR + // This error result check was done after the PrefetchModeSupported. So we will + // still try to calculate flip schedule even prefetch mode not supported + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) { + v->PrefetchModeSupported = false; + dml_print("DML::%s: ***failed***. Prefetch schedule violation. Results are NOT valid\n", __func__); + } + } + + if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) { + v->BandwidthAvailableForImmediateFlip = v->ReturnBW; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip + - dml_max( + v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k] + + v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k] + + v->cursor_bw[k] * v->UrgBurstFactorCursor[k], + v->DPPPerPlane[k] + * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k] + + v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]); + } + + v->TotImmediateFlipBytes = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + } + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + CalculateFlipSchedule( + mode_lib, + HostVMInefficiencyFactor, + v->UrgentExtraLatency, + v->UrgentLatency, + v->GPUVMMaxPageTableLevels, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMEnable, + v->HostVMMinPageSize, + v->PDEAndMetaPTEBytesFrame[k], + v->MetaRowByte[k], + v->PixelPTEBytesPerRow[k], + v->BandwidthAvailableForImmediateFlip, + v->TotImmediateFlipBytes, + v->SourcePixelFormat[k], + v->HTotal[k] / v->PixelClock[k], + v->VRatio[k], + v->VRatioChroma[k], + v->Tno_bw[k], + v->DCCEnable[k], + v->dpte_row_height[k], + v->meta_row_height[k], + v->dpte_row_height_chroma[k], + v->meta_row_height_chroma[k], + &v->DestinationLinesToRequestVMInImmediateFlip[k], + &v->DestinationLinesToRequestRowInImmediateFlip[k], + &v->final_flip_bw[k], + &v->ImmediateFlipSupportedForPipe[k]); + } + + v->total_dcn_read_bw_with_flip = 0.0; + v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip + + dml_max3( + v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k], + v->DPPPerPlane[k] * v->final_flip_bw[k] + + v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k] + + v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k] + + v->cursor_bw[k] * v->UrgBurstFactorCursor[k], + v->DPPPerPlane[k] + * (v->final_flip_bw[k] + + v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k] + + v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]); + v->total_dcn_read_bw_with_flip_no_urgent_burst = v->total_dcn_read_bw_with_flip_no_urgent_burst + + dml_max3( + v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k], + v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k] + + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k], + v->DPPPerPlane[k] + * (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k] + + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]); + } + v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW; + + v->ImmediateFlipSupported = true; + if (v->total_dcn_read_bw_with_flip > v->ReturnBW) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: total_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip); +#endif + v->ImmediateFlipSupported = false; + v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth; + } + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->ImmediateFlipSupportedForPipe[k] == false) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Pipe %0d not supporting iflip\n", + __func__, k); +#endif + v->ImmediateFlipSupported = false; + } + } + } else { + v->ImmediateFlipSupported = false; + } + + v->PrefetchAndImmediateFlipSupported = + (v->PrefetchModeSupported == true + && ((!v->ImmediateFlipSupport && !v->HostVMEnable + && v->ImmediateFlipRequirement != dm_immediate_flip_required) || v->ImmediateFlipSupported)) ? + true : false; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported); + dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required); + dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported); + dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport); + dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable); + dml_print("DML::%s: PrefetchAndImmediateFlipSupported %d\n", __func__, v->PrefetchAndImmediateFlipSupported); +#endif + dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup is %d\n", __func__, v->VStartupLines, v->MaximumMaxVStartupLines); + + v->VStartupLines = v->VStartupLines + 1; + } while (!v->PrefetchAndImmediateFlipSupported && v->VStartupLines <= v->MaximumMaxVStartupLines); + ASSERT(v->PrefetchAndImmediateFlipSupported); + + // Unbounded Request Enabled + CalculateUnboundedRequestAndCompressedBufferSize( + v->DETBufferSizeInKByte[0], + v->ConfigReturnBufferSizeInKByte, + v->UseUnboundedRequesting, + v->TotalActiveDPP, + NoChromaPlanes, + v->MaxNumDPP, + v->CompressedBufferSegmentSizeInkByte, + v->Output, + &v->UnboundedRequestEnabled, + &v->CompressedBufferSizeInkByte); + + //Watermarks and NB P-State/DRAM Clock Change Support + { + enum clock_change_support DRAMClockChangeSupport; // dummy + CalculateWatermarksAndDRAMSpeedChangeSupport( + mode_lib, + PrefetchMode, + v->NumberOfActivePlanes, + v->MaxLineBufferLines, + v->LineBufferSize, + v->WritebackInterfaceBufferSize, + v->DCFCLK, + v->ReturnBW, + v->SynchronizedVBlank, + v->dpte_group_bytes, + v->MetaChunkSize, + v->UrgentLatency, + v->UrgentExtraLatency, + v->WritebackLatency, + v->WritebackChunkSize, + v->SOCCLK, + v->DRAMClockChangeLatency, + v->SRExitTime, + v->SREnterPlusExitTime, + v->SRExitZ8Time, + v->SREnterPlusExitZ8Time, + v->DCFCLKDeepSleep, + v->DETBufferSizeY, + v->DETBufferSizeC, + v->SwathHeightY, + v->SwathHeightC, + v->LBBitPerPixel, + v->SwathWidthY, + v->SwathWidthC, + v->HRatio, + v->HRatioChroma, + v->vtaps, + v->VTAPsChroma, + v->VRatio, + v->VRatioChroma, + v->HTotal, + v->PixelClock, + v->BlendingAndTiming, + v->DPPPerPlane, + v->BytePerPixelDETY, + v->BytePerPixelDETC, + v->DSTXAfterScaler, + v->DSTYAfterScaler, + v->WritebackEnable, + v->WritebackPixelFormat, + v->WritebackDestinationWidth, + v->WritebackDestinationHeight, + v->WritebackSourceHeight, + v->UnboundedRequestEnabled, + v->CompressedBufferSizeInkByte, + &DRAMClockChangeSupport, + &v->UrgentWatermark, + &v->WritebackUrgentWatermark, + &v->DRAMClockChangeWatermark, + &v->WritebackDRAMClockChangeWatermark, + &v->StutterExitWatermark, + &v->StutterEnterPlusExitWatermark, + &v->Z8StutterExitWatermark, + &v->Z8StutterEnterPlusExitWatermark, + &v->MinActiveDRAMClockChangeLatencySupported); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->WritebackEnable[k] == true) { + v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max( + 0, + v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark); + } else { + v->WritebackAllowDRAMClockChangeEndPosition[k] = 0; + } + } + } + + //Display Pipeline Delivery Time in Prefetch, Groups + CalculatePixelDeliveryTimes( + v->NumberOfActivePlanes, + v->VRatio, + v->VRatioChroma, + v->VRatioPrefetchY, + v->VRatioPrefetchC, + v->swath_width_luma_ub, + v->swath_width_chroma_ub, + v->DPPPerPlane, + v->HRatio, + v->HRatioChroma, + v->PixelClock, + v->PSCL_THROUGHPUT_LUMA, + v->PSCL_THROUGHPUT_CHROMA, + v->DPPCLK, + v->BytePerPixelC, + v->SourceScan, + v->NumberOfCursors, + v->CursorWidth, + v->CursorBPP, + v->BlockWidth256BytesY, + v->BlockHeight256BytesY, + v->BlockWidth256BytesC, + v->BlockHeight256BytesC, + v->DisplayPipeLineDeliveryTimeLuma, + v->DisplayPipeLineDeliveryTimeChroma, + v->DisplayPipeLineDeliveryTimeLumaPrefetch, + v->DisplayPipeLineDeliveryTimeChromaPrefetch, + v->DisplayPipeRequestDeliveryTimeLuma, + v->DisplayPipeRequestDeliveryTimeChroma, + v->DisplayPipeRequestDeliveryTimeLumaPrefetch, + v->DisplayPipeRequestDeliveryTimeChromaPrefetch, + v->CursorRequestDeliveryTime, + v->CursorRequestDeliveryTimePrefetch); + + CalculateMetaAndPTETimes( + v->NumberOfActivePlanes, + v->GPUVMEnable, + v->MetaChunkSize, + v->MinMetaChunkSizeBytes, + v->HTotal, + v->VRatio, + v->VRatioChroma, + v->DestinationLinesToRequestRowInVBlank, + v->DestinationLinesToRequestRowInImmediateFlip, + v->DCCEnable, + v->PixelClock, + v->BytePerPixelY, + v->BytePerPixelC, + v->SourceScan, + v->dpte_row_height, + v->dpte_row_height_chroma, + v->meta_row_width, + v->meta_row_width_chroma, + v->meta_row_height, + v->meta_row_height_chroma, + v->meta_req_width, + v->meta_req_width_chroma, + v->meta_req_height, + v->meta_req_height_chroma, + v->dpte_group_bytes, + v->PTERequestSizeY, + v->PTERequestSizeC, + v->PixelPTEReqWidthY, + v->PixelPTEReqHeightY, + v->PixelPTEReqWidthC, + v->PixelPTEReqHeightC, + v->dpte_row_width_luma_ub, + v->dpte_row_width_chroma_ub, + v->DST_Y_PER_PTE_ROW_NOM_L, + v->DST_Y_PER_PTE_ROW_NOM_C, + v->DST_Y_PER_META_ROW_NOM_L, + v->DST_Y_PER_META_ROW_NOM_C, + v->TimePerMetaChunkNominal, + v->TimePerChromaMetaChunkNominal, + v->TimePerMetaChunkVBlank, + v->TimePerChromaMetaChunkVBlank, + v->TimePerMetaChunkFlip, + v->TimePerChromaMetaChunkFlip, + v->time_per_pte_group_nom_luma, + v->time_per_pte_group_vblank_luma, + v->time_per_pte_group_flip_luma, + v->time_per_pte_group_nom_chroma, + v->time_per_pte_group_vblank_chroma, + v->time_per_pte_group_flip_chroma); + + CalculateVMGroupAndRequestTimes( + v->NumberOfActivePlanes, + v->GPUVMEnable, + v->GPUVMMaxPageTableLevels, + v->HTotal, + v->BytePerPixelC, + v->DestinationLinesToRequestVMInVBlank, + v->DestinationLinesToRequestVMInImmediateFlip, + v->DCCEnable, + v->PixelClock, + v->dpte_row_width_luma_ub, + v->dpte_row_width_chroma_ub, + v->vm_group_bytes, + v->dpde0_bytes_per_frame_ub_l, + v->dpde0_bytes_per_frame_ub_c, + v->meta_pte_bytes_per_frame_ub_l, + v->meta_pte_bytes_per_frame_ub_c, + v->TimePerVMGroupVBlank, + v->TimePerVMGroupFlip, + v->TimePerVMRequestVBlank, + v->TimePerVMRequestFlip); + + // Min TTUVBlank + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (PrefetchMode == 0) { + v->AllowDRAMClockChangeDuringVBlank[k] = true; + v->AllowDRAMSelfRefreshDuringVBlank[k] = true; + v->MinTTUVBlank[k] = dml_max( + v->DRAMClockChangeWatermark, + dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark)); + } else if (PrefetchMode == 1) { + v->AllowDRAMClockChangeDuringVBlank[k] = false; + v->AllowDRAMSelfRefreshDuringVBlank[k] = true; + v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark); + } else { + v->AllowDRAMClockChangeDuringVBlank[k] = false; + v->AllowDRAMSelfRefreshDuringVBlank[k] = false; + v->MinTTUVBlank[k] = v->UrgentWatermark; + } + if (!v->DynamicMetadataEnable[k]) + v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k]; + } + + // DCC Configuration + v->ActiveDPPs = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown, + v->SourcePixelFormat[k], + v->SurfaceWidthY[k], + v->SurfaceWidthC[k], + v->SurfaceHeightY[k], + v->SurfaceHeightC[k], + v->DETBufferSizeInKByte[0] * 1024, + v->BlockHeight256BytesY[k], + v->BlockHeight256BytesC[k], + v->SurfaceTiling[k], + v->BytePerPixelY[k], + v->BytePerPixelC[k], + v->BytePerPixelDETY[k], + v->BytePerPixelDETC[k], + v->SourceScan[k], + &v->DCCYMaxUncompressedBlock[k], + &v->DCCCMaxUncompressedBlock[k], + &v->DCCYMaxCompressedBlock[k], + &v->DCCCMaxCompressedBlock[k], + &v->DCCYIndependentBlock[k], + &v->DCCCIndependentBlock[k]); + } + + // VStartup Adjustment + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + bool isInterlaceTiming; + double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]); +#endif + + v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin); + dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]); + dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]); +#endif + + v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin; + if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) { + v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin; + } + + isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP); + + v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k]) + - v->VFrontPorch[k]) + + dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0)) + + dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0; + + v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); + + if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k]) + <= (isInterlaceTiming ? + dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) : + (int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) { + v->VREADY_AT_OR_AFTER_VSYNC[k] = true; + } else { + v->VREADY_AT_OR_AFTER_VSYNC[k] = false; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]); + dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]); + dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]); + dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]); + dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]); + dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]); + dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]); + dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]); + dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]); + dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]); +#endif + } + + { + //Maximum Bandwidth Used + double TotalWRBandwidth = 0; + double MaxPerPlaneVActiveWRBandwidth = 0; + double WRBandwidth = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) { + WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] + / (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4; + } else if (v->WritebackEnable[k] == true) { + WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] + / (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8; + } + TotalWRBandwidth = TotalWRBandwidth + WRBandwidth; + MaxPerPlaneVActiveWRBandwidth = dml_max(MaxPerPlaneVActiveWRBandwidth, WRBandwidth); + } + + v->TotalDataReadBandwidth = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]; + } + } + // Stutter Efficiency + CalculateStutterEfficiency( + mode_lib, + v->CompressedBufferSizeInkByte, + v->UnboundedRequestEnabled, + v->ConfigReturnBufferSizeInKByte, + v->MetaFIFOSizeInKEntries, + v->ZeroSizeBufferEntries, + v->NumberOfActivePlanes, + v->ROBBufferSizeInKByte, + v->TotalDataReadBandwidth, + v->DCFCLK, + v->ReturnBW, + v->COMPBUF_RESERVED_SPACE_64B, + v->COMPBUF_RESERVED_SPACE_ZS, + v->SRExitTime, + v->SRExitZ8Time, + v->SynchronizedVBlank, + v->StutterEnterPlusExitWatermark, + v->Z8StutterEnterPlusExitWatermark, + v->ProgressiveToInterlaceUnitInOPP, + v->Interlace, + v->MinTTUVBlank, + v->DPPPerPlane, + v->DETBufferSizeY, + v->BytePerPixelY, + v->BytePerPixelDETY, + v->SwathWidthY, + v->SwathHeightY, + v->SwathHeightC, + v->DCCRateLuma, + v->DCCRateChroma, + v->DCCFractionOfZeroSizeRequestsLuma, + v->DCCFractionOfZeroSizeRequestsChroma, + v->HTotal, + v->VTotal, + v->PixelClock, + v->VRatio, + v->SourceScan, + v->BlockHeight256BytesY, + v->BlockWidth256BytesY, + v->BlockHeight256BytesC, + v->BlockWidth256BytesC, + v->DCCYMaxUncompressedBlock, + v->DCCCMaxUncompressedBlock, + v->VActive, + v->DCCEnable, + v->WritebackEnable, + v->ReadBandwidthPlaneLuma, + v->ReadBandwidthPlaneChroma, + v->meta_row_bw, + v->dpte_row_bw, + &v->StutterEfficiencyNotIncludingVBlank, + &v->StutterEfficiency, + &v->NumberOfStutterBurstsPerFrame, + &v->Z8StutterEfficiencyNotIncludingVBlank, + &v->Z8StutterEfficiency, + &v->Z8NumberOfStutterBurstsPerFrame, + &v->StutterPeriod); +} + +static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) +{ + struct vba_vars_st *v = &mode_lib->vba; + // Display Pipe Configuration + double BytePerPixDETY[DC__NUM_DPP__MAX]; + double BytePerPixDETC[DC__NUM_DPP__MAX]; + int BytePerPixY[DC__NUM_DPP__MAX]; + int BytePerPixC[DC__NUM_DPP__MAX]; + int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; + int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; + int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; + int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; + double dummy1[DC__NUM_DPP__MAX]; + double dummy2[DC__NUM_DPP__MAX]; + double dummy3[DC__NUM_DPP__MAX]; + double dummy4[DC__NUM_DPP__MAX]; + int dummy5[DC__NUM_DPP__MAX]; + int dummy6[DC__NUM_DPP__MAX]; + bool dummy7[DC__NUM_DPP__MAX]; + bool dummysinglestring; + + unsigned int k; + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + + CalculateBytePerPixelAnd256BBlockSizes( + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + &BytePerPixY[k], + &BytePerPixC[k], + &BytePerPixDETY[k], + &BytePerPixDETC[k], + &Read256BytesBlockHeightY[k], + &Read256BytesBlockHeightC[k], + &Read256BytesBlockWidthY[k], + &Read256BytesBlockWidthC[k]); + } + + CalculateSwathAndDETConfiguration( + false, + v->NumberOfActivePlanes, + v->DETBufferSizeInKByte[0], + dummy1, + dummy2, + v->SourceScan, + v->SourcePixelFormat, + v->SurfaceTiling, + v->ViewportWidth, + v->ViewportHeight, + v->SurfaceWidthY, + v->SurfaceWidthC, + v->SurfaceHeightY, + v->SurfaceHeightC, + Read256BytesBlockHeightY, + Read256BytesBlockHeightC, + Read256BytesBlockWidthY, + Read256BytesBlockWidthC, + v->ODMCombineEnabled, + v->BlendingAndTiming, + BytePerPixY, + BytePerPixC, + BytePerPixDETY, + BytePerPixDETC, + v->HActive, + v->HRatio, + v->HRatioChroma, + v->DPPPerPlane, + dummy5, + dummy6, + dummy3, + dummy4, + v->SwathHeightY, + v->SwathHeightC, + v->DETBufferSizeY, + v->DETBufferSizeC, + dummy7, + &dummysinglestring); +} + +static bool CalculateBytePerPixelAnd256BBlockSizes( + enum source_format_class SourcePixelFormat, + enum dm_swizzle_mode SurfaceTiling, + unsigned int *BytePerPixelY, + unsigned int *BytePerPixelC, + double *BytePerPixelDETY, + double *BytePerPixelDETC, + unsigned int *BlockHeight256BytesY, + unsigned int *BlockHeight256BytesC, + unsigned int *BlockWidth256BytesY, + unsigned int *BlockWidth256BytesC) +{ + if (SourcePixelFormat == dm_444_64) { + *BytePerPixelDETY = 8; + *BytePerPixelDETC = 0; + *BytePerPixelY = 8; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 0; + *BytePerPixelY = 4; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_16) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 0; + *BytePerPixelY = 2; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 0; + *BytePerPixelY = 1; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 1; + *BytePerPixelY = 4; + *BytePerPixelC = 1; + } else if (SourcePixelFormat == dm_420_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 2; + *BytePerPixelY = 1; + *BytePerPixelC = 2; + } else if (SourcePixelFormat == dm_420_12) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 4; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } else { + *BytePerPixelDETY = 4.0 / 3; + *BytePerPixelDETC = 8.0 / 3; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } + + if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16 + || SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) { + if (SurfaceTiling == dm_sw_linear) { + *BlockHeight256BytesY = 1; + } else if (SourcePixelFormat == dm_444_64) { + *BlockHeight256BytesY = 4; + } else if (SourcePixelFormat == dm_444_8) { + *BlockHeight256BytesY = 16; + } else { + *BlockHeight256BytesY = 8; + } + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockHeight256BytesC = 0; + *BlockWidth256BytesC = 0; + } else { + if (SurfaceTiling == dm_sw_linear) { + *BlockHeight256BytesY = 1; + *BlockHeight256BytesC = 1; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 16; + } else if (SourcePixelFormat == dm_420_8) { + *BlockHeight256BytesY = 16; + *BlockHeight256BytesC = 8; + } else { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 8; + } + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC; + } + return true; +} + +static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime) +{ + if (PrefetchMode == 0) { + return dml_max(DRAMClockChangeLatency + UrgentLatency, dml_max(SREnterPlusExitTime, UrgentLatency)); + } else if (PrefetchMode == 1) { + return dml_max(SREnterPlusExitTime, UrgentLatency); + } else { + return UrgentLatency; + } +} + +double dml31_CalculateWriteBackDISPCLK( + enum source_format_class WritebackPixelFormat, + double PixelClock, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackHTaps, + unsigned int WritebackVTaps, + long WritebackSourceWidth, + long WritebackDestinationWidth, + unsigned int HTotal, + unsigned int WritebackLineBufferSize) +{ + double DISPCLK_H, DISPCLK_V, DISPCLK_HB; + + DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; + DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal; + DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth; + return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB); +} + +static double CalculateWriteBackDelay( + enum source_format_class WritebackPixelFormat, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackVTaps, + int WritebackDestinationWidth, + int WritebackDestinationHeight, + int WritebackSourceHeight, + unsigned int HTotal) +{ + double CalculateWriteBackDelay; + double Line_length; + double Output_lines_last_notclamped; + double WritebackVInit; + + WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2; + Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps); + Output_lines_last_notclamped = WritebackDestinationHeight - 1 - dml_ceil((WritebackSourceHeight - WritebackVInit) / WritebackVRatio, 1); + if (Output_lines_last_notclamped < 0) { + CalculateWriteBackDelay = 0; + } else { + CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + (HTotal - WritebackDestinationWidth) + 80; + } + return CalculateWriteBackDelay; +} + +static void CalculateVupdateAndDynamicMetadataParameters( + int MaxInterDCNTileRepeaters, + double DPPCLK, + double DISPCLK, + double DCFClkDeepSleep, + double PixelClock, + int HTotal, + int VBlank, + int DynamicMetadataTransmittedBytes, + int DynamicMetadataLinesBeforeActiveRequired, + int InterlaceEnable, + bool ProgressiveToInterlaceUnitInOPP, + double *TSetup, + double *Tdmbf, + double *Tdmec, + double *Tdmsks, + int *VUpdateOffsetPix, + double *VUpdateWidthPix, + double *VReadyOffsetPix) +{ + double TotalRepeaterDelayTime; + + TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); + *VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0); + *VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0); + *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; + *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; + *Tdmec = HTotal / PixelClock; + if (DynamicMetadataLinesBeforeActiveRequired == 0) { + *Tdmsks = VBlank * HTotal / PixelClock / 2.0; + } else { + *Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock; + } + if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { + *Tdmsks = *Tdmsks / 2; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix); + dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix); + dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix); +#endif +} + +static void CalculateRowBandwidth( + bool GPUVMEnable, + enum source_format_class SourcePixelFormat, + double VRatio, + double VRatioChroma, + bool DCCEnable, + double LineTime, + unsigned int MetaRowByteLuma, + unsigned int MetaRowByteChroma, + unsigned int meta_row_height_luma, + unsigned int meta_row_height_chroma, + unsigned int PixelPTEBytesPerRowLuma, + unsigned int PixelPTEBytesPerRowChroma, + unsigned int dpte_row_height_luma, + unsigned int dpte_row_height_chroma, + double *meta_row_bw, + double *dpte_row_bw) +{ + if (DCCEnable != true) { + *meta_row_bw = 0; + } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) { + *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma * MetaRowByteChroma / (meta_row_height_chroma * LineTime); + } else { + *meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime); + } + + if (GPUVMEnable != true) { + *dpte_row_bw = 0; + } else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) { + *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) + + VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime); + } else { + *dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime); + } +} + +static void CalculateFlipSchedule( + struct display_mode_lib *mode_lib, + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, + unsigned int GPUVMMaxPageTableLevels, + bool HostVMEnable, + unsigned int HostVMMaxNonCachedPageTableLevels, + bool GPUVMEnable, + double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, + double DPTEBytesPerRow, + double BandwidthAvailableForImmediateFlip, + unsigned int TotImmediateFlipBytes, + enum source_format_class SourcePixelFormat, + double LineTime, + double VRatio, + double VRatioChroma, + double Tno_bw, + bool DCCEnable, + unsigned int dpte_row_height, + unsigned int meta_row_height, + unsigned int dpte_row_height_chroma, + unsigned int meta_row_height_chroma, + double *DestinationLinesToRequestVMInImmediateFlip, + double *DestinationLinesToRequestRowInImmediateFlip, + double *final_flip_bw, + bool *ImmediateFlipSupportedForPipe) +{ + double min_row_time = 0.0; + unsigned int HostVMDynamicLevelsTrips; + double TimeForFetchingMetaPTEImmediateFlip; + double TimeForFetchingRowInVBlankImmediateFlip; + double ImmediateFlipBW; + + if (GPUVMEnable == true && HostVMEnable == true) { + HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; + } else { + HostVMDynamicLevelsTrips = 0; + } + + if (GPUVMEnable == true || DCCEnable == true) { + ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; + } + + if (GPUVMEnable == true) { + TimeForFetchingMetaPTEImmediateFlip = dml_max3( + Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, + UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), + LineTime / 4.0); + } else { + TimeForFetchingMetaPTEImmediateFlip = 0; + } + + *DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; + if ((GPUVMEnable == true || DCCEnable == true)) { + TimeForFetchingRowInVBlankImmediateFlip = dml_max3( + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW, + UrgentLatency * (HostVMDynamicLevelsTrips + 1), + LineTime / 4); + } else { + TimeForFetchingRowInVBlankImmediateFlip = 0; + } + + *DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; + + if (GPUVMEnable == true) { + *final_flip_bw = dml_max( + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime)); + } else if ((GPUVMEnable == true || DCCEnable == true)) { + *final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime); + } else { + *final_flip_bw = 0; + } + + if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) { + if (GPUVMEnable == true && DCCEnable != true) { + min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma); + } else if (GPUVMEnable != true && DCCEnable == true) { + min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma); + } else { + min_row_time = dml_min4( + dpte_row_height * LineTime / VRatio, + meta_row_height * LineTime / VRatio, + dpte_row_height_chroma * LineTime / VRatioChroma, + meta_row_height_chroma * LineTime / VRatioChroma); + } + } else { + if (GPUVMEnable == true && DCCEnable != true) { + min_row_time = dpte_row_height * LineTime / VRatio; + } else if (GPUVMEnable != true && DCCEnable == true) { + min_row_time = meta_row_height * LineTime / VRatio; + } else { + min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio); + } + } + + if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16 + || TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) { + *ImmediateFlipSupportedForPipe = false; + } else { + *ImmediateFlipSupportedForPipe = true; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip); + dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip); + dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip); + dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip); + dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time); + dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe); +#endif + +} + +static double TruncToValidBPP( + double LinkBitRate, + int Lanes, + int HTotal, + int HActive, + double PixelClock, + double DesiredBPP, + bool DSCEnable, + enum output_encoder_class Output, + enum output_format_class Format, + unsigned int DSCInputBitPerComponent, + int DSCSlices, + int AudioRate, + int AudioLayout, + enum odm_combine_mode ODMCombine) +{ + double MaxLinkBPP; + int MinDSCBPP; + double MaxDSCBPP; + int NonDSCBPP0; + int NonDSCBPP1; + int NonDSCBPP2; + + if (Format == dm_420) { + NonDSCBPP0 = 12; + NonDSCBPP1 = 15; + NonDSCBPP2 = 18; + MinDSCBPP = 6; + MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16; + } else if (Format == dm_444) { + NonDSCBPP0 = 24; + NonDSCBPP1 = 30; + NonDSCBPP2 = 36; + MinDSCBPP = 8; + MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16; + } else { + if (Output == dm_hdmi) { + NonDSCBPP0 = 24; + NonDSCBPP1 = 24; + NonDSCBPP2 = 24; + } else { + NonDSCBPP0 = 16; + NonDSCBPP1 = 20; + NonDSCBPP2 = 24; + } + if (Format == dm_n422) { + MinDSCBPP = 7; + MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0; + } else { + MinDSCBPP = 8; + MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0; + } + } + + if (DSCEnable && Output == dm_dp) { + MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100); + } else { + MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock; + } + + if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) { + MaxLinkBPP = 16; + } else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) { + MaxLinkBPP = 32; + } + + if (DesiredBPP == 0) { + if (DSCEnable) { + if (MaxLinkBPP < MinDSCBPP) { + return BPP_INVALID; + } else if (MaxLinkBPP >= MaxDSCBPP) { + return MaxDSCBPP; + } else { + return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0; + } + } else { + if (MaxLinkBPP >= NonDSCBPP2) { + return NonDSCBPP2; + } else if (MaxLinkBPP >= NonDSCBPP1) { + return NonDSCBPP1; + } else if (MaxLinkBPP >= NonDSCBPP0) { + return 16.0; + } else { + return BPP_INVALID; + } + } + } else { + if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0)) + || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { + return BPP_INVALID; + } else { + return DesiredBPP; + } + } + return BPP_INVALID; +} + +void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) +{ + struct vba_vars_st *v = &mode_lib->vba; + + int i, j; + unsigned int k, m; + int ReorderingBytes; + int MinPrefetchMode = 0, MaxPrefetchMode = 2; + bool NoChroma = true; + bool EnoughWritebackUnits = true; + bool P2IWith420 = false; + bool DSCOnlyIfNecessaryWithBPP = false; + bool DSC422NativeNotSupported = false; + double MaxTotalVActiveRDBandwidth; + bool ViewportExceedsSurface = false; + bool FMTBufferExceeded = false; + + /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ + + CalculateMinAndMaxPrefetchMode( + mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, + &MinPrefetchMode, &MaxPrefetchMode); + + /*Scale Ratio, taps Support Check*/ + + v->ScaleRatioAndTapsSupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->ScalerEnabled[k] == false + && ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 + && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16 + && v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe + && v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0 + || v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) { + v->ScaleRatioAndTapsSupport = false; + } else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0 + || (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio + || v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k] + || v->VRatio[k] > v->vtaps[k] + || (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 + && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16 + && v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe + && (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1 + || v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1) + || v->HRatioChroma[k] > v->MaxHSCLRatio + || v->VRatioChroma[k] > v->MaxVSCLRatio + || v->HRatioChroma[k] > v->HTAPsChroma[k] + || v->VRatioChroma[k] > v->VTAPsChroma[k]))) { + v->ScaleRatioAndTapsSupport = false; + } + } + /*Source Format, Pixel Format and Scan Support Check*/ + + v->SourceFormatPixelAndScanSupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) + || ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t + || v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) { + v->SourceFormatPixelAndScanSupport = false; + } + } + /*Bandwidth Support Check*/ + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + CalculateBytePerPixelAnd256BBlockSizes( + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + &v->BytePerPixelY[k], + &v->BytePerPixelC[k], + &v->BytePerPixelInDETY[k], + &v->BytePerPixelInDETC[k], + &v->Read256BlockHeightY[k], + &v->Read256BlockHeightC[k], + &v->Read256BlockWidthY[k], + &v->Read256BlockWidthC[k]); + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->SourceScan[k] != dm_vert) { + v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k]; + v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k]; + } else { + v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k]; + v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k]; + } + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k]; + v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0) + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0; + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) { + v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] + / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0; + } else if (v->WritebackEnable[k] == true) { + v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] + / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0; + } else { + v->WriteBandwidth[k] = 0.0; + } + } + + /*Writeback Latency support check*/ + + v->WritebackLatencySupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) { + v->WritebackLatencySupport = false; + } + } + + /*Writeback Mode Support Check*/ + + v->TotalNumberOfActiveWriteback = 0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->WritebackEnable[k] == true) { + v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1; + } + } + + if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) { + EnoughWritebackUnits = false; + } + + /*Writeback Scale Ratio and Taps Support Check*/ + + v->WritebackScaleRatioAndTapsSupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->WritebackEnable[k] == true) { + if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio + || v->WritebackHRatio[k] < v->WritebackMinHSCLRatio + || v->WritebackVRatio[k] < v->WritebackMinVSCLRatio + || v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps + || v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps + || v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k] + || (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) { + v->WritebackScaleRatioAndTapsSupport = false; + } + if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) { + v->WritebackScaleRatioAndTapsSupport = false; + } + } + } + /*Maximum DISPCLK/DPPCLK Support check*/ + + v->WritebackRequiredDISPCLK = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->WritebackEnable[k] == true) { + v->WritebackRequiredDISPCLK = dml_max( + v->WritebackRequiredDISPCLK, + dml31_CalculateWriteBackDISPCLK( + v->WritebackPixelFormat[k], + v->PixelClock[k], + v->WritebackHRatio[k], + v->WritebackVRatio[k], + v->WritebackHTaps[k], + v->WritebackVTaps[k], + v->WritebackSourceWidth[k], + v->WritebackDestinationWidth[k], + v->HTotal[k], + v->WritebackLineBufferSize)); + } + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->HRatio[k] > 1.0) { + v->PSCL_FACTOR[k] = dml_min( + v->MaxDCHUBToPSCLThroughput, + v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0)); + } else { + v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput); + } + if (v->BytePerPixelC[k] == 0.0) { + v->PSCL_FACTOR_CHROMA[k] = 0.0; + v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] + * dml_max3( + v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), + v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], + 1.0); + if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) { + v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k]; + } + } else { + if (v->HRatioChroma[k] > 1.0) { + v->PSCL_FACTOR_CHROMA[k] = dml_min( + v->MaxDCHUBToPSCLThroughput, + v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0)); + } else { + v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput); + } + v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] + * dml_max5( + v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), + v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], + v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]), + v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k], + 1.0); + if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0) + && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) { + v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k]; + } + } + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + int MaximumSwathWidthSupportLuma; + int MaximumSwathWidthSupportChroma; + + if (v->SurfaceTiling[k] == dm_sw_linear) { + MaximumSwathWidthSupportLuma = 8192.0; + } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { + MaximumSwathWidthSupportLuma = 2880.0; + } else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) { + MaximumSwathWidthSupportLuma = 3840.0; + } else { + MaximumSwathWidthSupportLuma = 5760.0; + } + + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { + MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + } else { + MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; + } + v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k] + / (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0)); + if (v->BytePerPixelC[k] == 0.0) { + v->MaximumSwathWidthInLineBufferChroma = 0; + } else { + v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k] + / (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0)); + } + v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma); + v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma); + } + + CalculateSwathAndDETConfiguration( + true, + v->NumberOfActivePlanes, + v->DETBufferSizeInKByte[0], + v->MaximumSwathWidthLuma, + v->MaximumSwathWidthChroma, + v->SourceScan, + v->SourcePixelFormat, + v->SurfaceTiling, + v->ViewportWidth, + v->ViewportHeight, + v->SurfaceWidthY, + v->SurfaceWidthC, + v->SurfaceHeightY, + v->SurfaceHeightC, + v->Read256BlockHeightY, + v->Read256BlockHeightC, + v->Read256BlockWidthY, + v->Read256BlockWidthC, + v->odm_combine_dummy, + v->BlendingAndTiming, + v->BytePerPixelY, + v->BytePerPixelC, + v->BytePerPixelInDETY, + v->BytePerPixelInDETC, + v->HActive, + v->HRatio, + v->HRatioChroma, + v->NoOfDPPThisState, + v->swath_width_luma_ub_this_state, + v->swath_width_chroma_ub_this_state, + v->SwathWidthYThisState, + v->SwathWidthCThisState, + v->SwathHeightYThisState, + v->SwathHeightCThisState, + v->DETBufferSizeYThisState, + v->DETBufferSizeCThisState, + v->SingleDPPViewportSizeSupportPerPlane, + &v->ViewportSizeSupport[0][0]); + + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed); + v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed); + v->RequiredDISPCLK[i][j] = 0.0; + v->DISPCLK_DPPCLK_Support[i][j] = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + * (1.0 + v->DISPCLKRampingMargin / 100.0); + if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] + && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) { + v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] + * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } + v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + * (1 + v->DISPCLKRampingMargin / 100.0); + if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] + && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) { + v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 + * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } + v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + * (1 + v->DISPCLKRampingMargin / 100.0); + if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] + && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) { + v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 + * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } + + if (v->ODMCombinePolicy == dm_odm_combine_policy_none + || !(v->Output[k] == dm_dp || + v->Output[k] == dm_edp)) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine; + + if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) + FMTBufferExceeded = true; + } else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; + } else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1 + || v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + } else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; + } else { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine; + } + if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH + && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) { + if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + } else { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; + } + } + if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH + && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) { + if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + + if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH) + FMTBufferExceeded = true; + } else { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; + } + } + if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { + v->MPCCombine[i][j][k] = false; + v->NoOfDPP[i][j][k] = 4; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4; + } else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { + v->MPCCombine[i][j][k] = false; + v->NoOfDPP[i][j][k] = 2; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2; + } else if ((v->WhenToDoMPCCombine == dm_mpc_never + || (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + <= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) { + v->MPCCombine[i][j][k] = false; + v->NoOfDPP[i][j][k] = 1; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } else { + v->MPCCombine[i][j][k] = true; + v->NoOfDPP[i][j][k] = 2; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; + } + v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK); + if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + > v->MaxDppclkRoundedDownToDFSGranularity) + || (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) { + v->DISPCLK_DPPCLK_Support[i][j] = false; + } + } + v->TotalNumberOfActiveDPP[i][j] = 0; + v->TotalNumberOfSingleDPPPlanes[i][j] = 0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; + if (v->NoOfDPP[i][j][k] == 1) + v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1; + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 + || v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) + NoChroma = false; + } + + // UPTO + if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never + && !UnboundedRequest(v->UseUnboundedRequesting, v->TotalNumberOfActiveDPP[i][j], NoChroma, v->Output[0])) { + while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) { + double BWOfNonSplitPlaneOfMaximumBandwidth; + unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth; + BWOfNonSplitPlaneOfMaximumBandwidth = 0; + NumberOfNonSplitPlaneOfMaximumBandwidth = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth + && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) { + BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]; + NumberOfNonSplitPlaneOfMaximumBandwidth = k; + } + } + v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true; + v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2; + v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = + v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth] + * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2; + v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1; + v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1; + } + } + if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) { + v->RequiredDISPCLK[i][j] = 0.0; + v->DISPCLK_DPPCLK_Support[i][j] = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; + if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) { + v->MPCCombine[i][j][k] = true; + v->NoOfDPP[i][j][k] = 2; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] + * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; + } else { + v->MPCCombine[i][j][k] = false; + v->NoOfDPP[i][j][k] = 1; + v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] + * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } + if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] + && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) { + v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + * (1.0 + v->DISPCLKRampingMargin / 100.0); + } else { + v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); + } + v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK); + if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) + > v->MaxDppclkRoundedDownToDFSGranularity) + || (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) { + v->DISPCLK_DPPCLK_Support[i][j] = false; + } + } + v->TotalNumberOfActiveDPP[i][j] = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; + } + } + v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK); + if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) { + v->DISPCLK_DPPCLK_Support[i][j] = false; + } + } + } + + /*Total Available Pipes Support Check*/ + + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) { + v->TotalAvailablePipesSupport[i][j] = true; + } else { + v->TotalAvailablePipesSupport[i][j] = false; + } + } + } + /*Display IO and DSC Support Check*/ + + v->NonsupportedDSCInputBPC = false; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0) + || v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) { + v->NonsupportedDSCInputBPC = true; + } + } + + /*Number Of DSC Slices*/ + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] == k) { + if (v->PixelClockBackEnd[k] > 3200) { + v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + } else if (v->PixelClockBackEnd[k] > 1360) { + v->NumberOfDSCSlices[k] = 8; + } else if (v->PixelClockBackEnd[k] > 680) { + v->NumberOfDSCSlices[k] = 4; + } else if (v->PixelClockBackEnd[k] > 340) { + v->NumberOfDSCSlices[k] = 2; + } else { + v->NumberOfDSCSlices[k] = 1; + } + } else { + v->NumberOfDSCSlices[k] = 0; + } + } + + for (i = 0; i < v->soc.num_states; i++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->RequiresDSC[i][k] = false; + v->RequiresFEC[i][k] = false; + if (v->BlendingAndTiming[k] == k) { + if (v->Output[k] == dm_hdmi) { + v->RequiresDSC[i][k] = false; + v->RequiresFEC[i][k] = false; + v->OutputBppPerState[i][k] = TruncToValidBPP( + dml_min(600.0, v->PHYCLKPerState[i]) * 10, + 3, + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + false, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + } else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) { + if (v->DSCEnable[k] == true) { + v->RequiresDSC[i][k] = true; + v->LinkDSCEnable = true; + if (v->Output[k] == dm_dp) { + v->RequiresFEC[i][k] = true; + } else { + v->RequiresFEC[i][k] = false; + } + } else { + v->RequiresDSC[i][k] = false; + v->LinkDSCEnable = false; + v->RequiresFEC[i][k] = false; + } + + v->Outbpp = BPP_INVALID; + if (v->PHYCLKPerState[i] >= 270.0) { + v->Outbpp = TruncToValidBPP( + (1.0 - v->Downspreading / 100.0) * 2700, + v->OutputLinkDPLanes[k], + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + v->LinkDSCEnable, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + v->OutputBppPerState[i][k] = v->Outbpp; + // TODO: Need some other way to handle this nonsense + // v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR" + } + if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { + v->Outbpp = TruncToValidBPP( + (1.0 - v->Downspreading / 100.0) * 5400, + v->OutputLinkDPLanes[k], + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + v->LinkDSCEnable, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + v->OutputBppPerState[i][k] = v->Outbpp; + // TODO: Need some other way to handle this nonsense + // v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR2" + } + if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { + v->Outbpp = TruncToValidBPP( + (1.0 - v->Downspreading / 100.0) * 8100, + v->OutputLinkDPLanes[k], + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + v->LinkDSCEnable, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + v->OutputBppPerState[i][k] = v->Outbpp; + // TODO: Need some other way to handle this nonsense + // v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR3" + } + if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 10000.0 / 18) { + v->Outbpp = TruncToValidBPP( + (1.0 - v->Downspreading / 100.0) * 10000, + 4, + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + v->LinkDSCEnable, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + v->OutputBppPerState[i][k] = v->Outbpp; + //v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "10x4"; + } + if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 12000.0 / 18) { + v->Outbpp = TruncToValidBPP( + 12000, + 4, + v->HTotal[k], + v->HActive[k], + v->PixelClockBackEnd[k], + v->ForcedOutputLinkBPP[k], + v->LinkDSCEnable, + v->Output[k], + v->OutputFormat[k], + v->DSCInputBitPerComponent[k], + v->NumberOfDSCSlices[k], + v->AudioSampleRate[k], + v->AudioSampleLayout[k], + v->ODMCombineEnablePerState[i][k]); + v->OutputBppPerState[i][k] = v->Outbpp; + //v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "12x4"; + } + } + } else { + v->OutputBppPerState[i][k] = 0; + } + } + } + + for (i = 0; i < v->soc.num_states; i++) { + v->LinkCapacitySupport[i] = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->BlendingAndTiming[k] == k + && (v->Output[k] == dm_dp || + v->Output[k] == dm_edp || + v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) { + v->LinkCapacitySupport[i] = false; + } + } + } + + // UPTO 2172 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] == k + && (v->Output[k] == dm_dp || + v->Output[k] == dm_edp || + v->Output[k] == dm_hdmi)) { + if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) { + P2IWith420 = true; + } + if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422 + && !v->DSC422NativeSupport) { + DSC422NativeNotSupported = true; + } + } + } + + for (i = 0; i < v->soc.num_states; ++i) { + v->ODMCombine4To1SupportCheckOK[i] = true; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1 + && (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp + || v->Output[k] == dm_hdmi)) { + v->ODMCombine4To1SupportCheckOK[i] = false; + } + } + } + + /* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */ + + for (i = 0; i < v->soc.num_states; i++) { + v->NotEnoughDSCUnits[i] = false; + v->TotalDSCUnitsRequired = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->RequiresDSC[i][k] == true) { + if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) { + v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0; + } else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { + v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0; + } else { + v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0; + } + } + } + if (v->TotalDSCUnitsRequired > v->NumberOfDSC) { + v->NotEnoughDSCUnits[i] = true; + } + } + /*DSC Delay per state*/ + + for (i = 0; i < v->soc.num_states; i++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->OutputBppPerState[i][k] == BPP_INVALID) { + v->BPP = 0.0; + } else { + v->BPP = v->OutputBppPerState[i][k]; + } + if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) { + if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) { + v->DSCDelayPerState[i][k] = dscceComputeDelay( + v->DSCInputBitPerComponent[k], + v->BPP, + dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + v->NumberOfDSCSlices[k], + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); + } else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) { + v->DSCDelayPerState[i][k] = 2.0 + * (dscceComputeDelay( + v->DSCInputBitPerComponent[k], + v->BPP, + dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + v->NumberOfDSCSlices[k] / 2, + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); + } else { + v->DSCDelayPerState[i][k] = 4.0 + * (dscceComputeDelay( + v->DSCInputBitPerComponent[k], + v->BPP, + dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + v->NumberOfDSCSlices[k] / 4, + v->OutputFormat[k], + v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); + } + v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + } else { + v->DSCDelayPerState[i][k] = 0.0; + } + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + for (m = 0; m < v->NumberOfActivePlanes; m++) { + if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) { + v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m]; + } + } + } + } + + //Calculate Swath, DET Configuration, DCFCLKDeepSleep + // + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k]; + v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k]; + v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k]; + } + + CalculateSwathAndDETConfiguration( + false, + v->NumberOfActivePlanes, + v->DETBufferSizeInKByte[0], + v->MaximumSwathWidthLuma, + v->MaximumSwathWidthChroma, + v->SourceScan, + v->SourcePixelFormat, + v->SurfaceTiling, + v->ViewportWidth, + v->ViewportHeight, + v->SurfaceWidthY, + v->SurfaceWidthC, + v->SurfaceHeightY, + v->SurfaceHeightC, + v->Read256BlockHeightY, + v->Read256BlockHeightC, + v->Read256BlockWidthY, + v->Read256BlockWidthC, + v->ODMCombineEnableThisState, + v->BlendingAndTiming, + v->BytePerPixelY, + v->BytePerPixelC, + v->BytePerPixelInDETY, + v->BytePerPixelInDETC, + v->HActive, + v->HRatio, + v->HRatioChroma, + v->NoOfDPPThisState, + v->swath_width_luma_ub_this_state, + v->swath_width_chroma_ub_this_state, + v->SwathWidthYThisState, + v->SwathWidthCThisState, + v->SwathHeightYThisState, + v->SwathHeightCThisState, + v->DETBufferSizeYThisState, + v->DETBufferSizeCThisState, + v->dummystring, + &v->ViewportSizeSupport[i][j]); + + CalculateDCFCLKDeepSleep( + mode_lib, + v->NumberOfActivePlanes, + v->BytePerPixelY, + v->BytePerPixelC, + v->VRatio, + v->VRatioChroma, + v->SwathWidthYThisState, + v->SwathWidthCThisState, + v->NoOfDPPThisState, + v->HRatio, + v->HRatioChroma, + v->PixelClock, + v->PSCL_FACTOR, + v->PSCL_FACTOR_CHROMA, + v->RequiredDPPCLKThisState, + v->ReadBandwidthLuma, + v->ReadBandwidthChroma, + v->ReturnBusWidth, + &v->ProjectedDCFCLKDeepSleep[i][j]); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; + v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; + v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; + v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; + v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; + v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k]; + } + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k]; + } + + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX]; + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k]; + v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k]; + v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k]; + v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; + v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; + v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + } + + v->TotalNumberOfDCCActiveDPP[i][j] = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->DCCEnable[k] == true) { + v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k]; + } + } + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 + || v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) { + + if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) + && v->SourceScan[k] != dm_vert) { + v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) + / 2; + v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma; + } else { + v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma; + v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma; + } + + v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes( + mode_lib, + v->DCCEnable[k], + v->Read256BlockHeightC[k], + v->Read256BlockWidthC[k], + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + v->BytePerPixelC[k], + v->SourceScan[k], + v->SwathWidthCThisState[k], + v->ViewportHeightChroma[k], + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMMinPageSize, + v->HostVMMinPageSize, + v->PTEBufferSizeInRequestsForChroma, + v->PitchC[k], + 0.0, + &v->MacroTileWidthC[k], + &v->MetaRowBytesC, + &v->DPTEBytesPerRowC, + &v->PTEBufferSizeNotExceededC[i][j][k], + &v->dummyinteger7, + &v->dpte_row_height_chroma[k], + &v->dummyinteger28, + &v->dummyinteger26, + &v->dummyinteger23, + &v->meta_row_height_chroma[k], + &v->dummyinteger8, + &v->dummyinteger9, + &v->dummyinteger19, + &v->dummyinteger20, + &v->dummyinteger17, + &v->dummyinteger10, + &v->dummyinteger11); + + v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines( + mode_lib, + v->VRatioChroma[k], + v->VTAPsChroma[k], + v->Interlace[k], + v->ProgressiveToInterlaceUnitInOPP, + v->SwathHeightCThisState[k], + v->ViewportYStartC[k], + &v->PrefillC[k], + &v->MaxNumSwC[k]); + } else { + v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; + v->PTEBufferSizeInRequestsForChroma = 0; + v->PDEAndMetaPTEBytesPerFrameC = 0.0; + v->MetaRowBytesC = 0.0; + v->DPTEBytesPerRowC = 0.0; + v->PrefetchLinesC[i][j][k] = 0.0; + v->PTEBufferSizeNotExceededC[i][j][k] = true; + } + v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes( + mode_lib, + v->DCCEnable[k], + v->Read256BlockHeightY[k], + v->Read256BlockWidthY[k], + v->SourcePixelFormat[k], + v->SurfaceTiling[k], + v->BytePerPixelY[k], + v->SourceScan[k], + v->SwathWidthYThisState[k], + v->ViewportHeight[k], + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMMinPageSize, + v->HostVMMinPageSize, + v->PTEBufferSizeInRequestsForLuma, + v->PitchY[k], + v->DCCMetaPitchY[k], + &v->MacroTileWidthY[k], + &v->MetaRowBytesY, + &v->DPTEBytesPerRowY, + &v->PTEBufferSizeNotExceededY[i][j][k], + &v->dummyinteger7, + &v->dpte_row_height[k], + &v->dummyinteger29, + &v->dummyinteger27, + &v->dummyinteger24, + &v->meta_row_height[k], + &v->dummyinteger25, + &v->dpte_group_bytes[k], + &v->dummyinteger21, + &v->dummyinteger22, + &v->dummyinteger18, + &v->dummyinteger5, + &v->dummyinteger6); + v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines( + mode_lib, + v->VRatio[k], + v->vtaps[k], + v->Interlace[k], + v->ProgressiveToInterlaceUnitInOPP, + v->SwathHeightYThisState[k], + v->ViewportYStartY[k], + &v->PrefillY[k], + &v->MaxNumSwY[k]); + v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC; + v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC; + v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC; + + CalculateRowBandwidth( + v->GPUVMEnable, + v->SourcePixelFormat[k], + v->VRatio[k], + v->VRatioChroma[k], + v->DCCEnable[k], + v->HTotal[k] / v->PixelClock[k], + v->MetaRowBytesY, + v->MetaRowBytesC, + v->meta_row_height[k], + v->meta_row_height_chroma[k], + v->DPTEBytesPerRowY, + v->DPTEBytesPerRowC, + v->dpte_row_height[k], + v->dpte_row_height_chroma[k], + &v->meta_row_bandwidth[i][j][k], + &v->dpte_row_bandwidth[i][j][k]); + } + v->UrgLatency[i] = CalculateUrgentLatency( + v->UrgentLatencyPixelDataOnly, + v->UrgentLatencyPixelMixedWithVMData, + v->UrgentLatencyVMDataOnly, + v->DoUrgentLatencyAdjustment, + v->UrgentLatencyAdjustmentFabricClockComponent, + v->UrgentLatencyAdjustmentFabricClockReference, + v->FabricClockPerState[i]); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + CalculateUrgentBurstFactor( + v->swath_width_luma_ub_this_state[k], + v->swath_width_chroma_ub_this_state[k], + v->SwathHeightYThisState[k], + v->SwathHeightCThisState[k], + v->HTotal[k] / v->PixelClock[k], + v->UrgLatency[i], + v->CursorBufferSize, + v->CursorWidth[k][0], + v->CursorBPP[k][0], + v->VRatio[k], + v->VRatioChroma[k], + v->BytePerPixelInDETY[k], + v->BytePerPixelInDETC[k], + v->DETBufferSizeYThisState[k], + v->DETBufferSizeCThisState[k], + &v->UrgentBurstFactorCursor[k], + &v->UrgentBurstFactorLuma[k], + &v->UrgentBurstFactorChroma[k], + &NotUrgentLatencyHiding[k]); + } + + v->NotEnoughUrgentLatencyHidingA[i][j] = false; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (NotUrgentLatencyHiding[k]) { + v->NotEnoughUrgentLatencyHidingA[i][j] = true; + } + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k] + + v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k]; + v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k]; + } + + v->TotalVActivePixelBandwidth[i][j] = 0; + v->TotalVActiveCursorBandwidth[i][j] = 0; + v->TotalMetaRowBandwidth[i][j] = 0; + v->TotalDPTERowBandwidth[i][j] = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k]; + v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k]; + v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k]; + v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k]; + } + } + } + + //Calculate Return BW + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->BlendingAndTiming[k] == k) { + if (v->WritebackEnable[k] == true) { + v->WritebackDelayTime[k] = v->WritebackLatency + + CalculateWriteBackDelay( + v->WritebackPixelFormat[k], + v->WritebackHRatio[k], + v->WritebackVRatio[k], + v->WritebackVTaps[k], + v->WritebackDestinationWidth[k], + v->WritebackDestinationHeight[k], + v->WritebackSourceHeight[k], + v->HTotal[k]) / v->RequiredDISPCLK[i][j]; + } else { + v->WritebackDelayTime[k] = 0.0; + } + for (m = 0; m < v->NumberOfActivePlanes; m++) { + if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) { + v->WritebackDelayTime[k] = dml_max( + v->WritebackDelayTime[k], + v->WritebackLatency + + CalculateWriteBackDelay( + v->WritebackPixelFormat[m], + v->WritebackHRatio[m], + v->WritebackVRatio[m], + v->WritebackVTaps[m], + v->WritebackDestinationWidth[m], + v->WritebackDestinationHeight[m], + v->WritebackSourceHeight[m], + v->HTotal[m]) / v->RequiredDISPCLK[i][j]); + } + } + } + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + for (m = 0; m < v->NumberOfActivePlanes; m++) { + if (v->BlendingAndTiming[k] == m) { + v->WritebackDelayTime[k] = v->WritebackDelayTime[m]; + } + } + } + v->MaxMaxVStartup[i][j] = 0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->MaximumVStartup[i][j][k] = + (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ? + dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) : + v->VTotal[k] - v->VActive[k] + - dml_max( + 1.0, + dml_ceil( + 1.0 * v->WritebackDelayTime[k] + / (v->HTotal[k] + / v->PixelClock[k]), + 1.0)); + if (v->MaximumVStartup[i][j][k] > 1023) + v->MaximumVStartup[i][j][k] = 1023; + v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]); + } + } + } + + ReorderingBytes = v->NumberOfChannels + * dml_max3( + v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, + v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, + v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + v->DCFCLKState[i][j] = v->DCFCLKPerState[i]; + } + } + + if (v->UseMinimumRequiredDCFCLK == true) { + UseMinimumDCFCLK( + mode_lib, + v->MaxInterDCNTileRepeaters, + MaxPrefetchMode, + v->DRAMClockChangeLatency, + v->SREnterPlusExitTime, + v->ReturnBusWidth, + v->RoundTripPingLatencyCycles, + ReorderingBytes, + v->PixelChunkSizeInKByte, + v->MetaChunkSize, + v->GPUVMEnable, + v->GPUVMMaxPageTableLevels, + v->HostVMEnable, + v->NumberOfActivePlanes, + v->HostVMMinPageSize, + v->HostVMMaxNonCachedPageTableLevels, + v->DynamicMetadataVMEnabled, + v->ImmediateFlipRequirement, + v->ProgressiveToInterlaceUnitInOPP, + v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, + v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, + v->VTotal, + v->VActive, + v->DynamicMetadataTransmittedBytes, + v->DynamicMetadataLinesBeforeActiveRequired, + v->Interlace, + v->RequiredDPPCLK, + v->RequiredDISPCLK, + v->UrgLatency, + v->NoOfDPP, + v->ProjectedDCFCLKDeepSleep, + v->MaximumVStartup, + v->TotalVActivePixelBandwidth, + v->TotalVActiveCursorBandwidth, + v->TotalMetaRowBandwidth, + v->TotalDPTERowBandwidth, + v->TotalNumberOfActiveDPP, + v->TotalNumberOfDCCActiveDPP, + v->dpte_group_bytes, + v->PrefetchLinesY, + v->PrefetchLinesC, + v->swath_width_luma_ub_all_states, + v->swath_width_chroma_ub_all_states, + v->BytePerPixelY, + v->BytePerPixelC, + v->HTotal, + v->PixelClock, + v->PDEAndMetaPTEBytesPerFrame, + v->DPTEBytesPerRow, + v->MetaRowBytes, + v->DynamicMetadataEnable, + v->VActivePixelBandwidth, + v->VActiveCursorBandwidth, + v->ReadBandwidthLuma, + v->ReadBandwidthChroma, + v->DCFCLKPerState, + v->DCFCLKState); + } + + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + double IdealFabricAndSDPPortBandwidthPerState = dml_min( + v->ReturnBusWidth * v->DCFCLKState[i][j], + v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn); + double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth; + double PixelDataOnlyReturnBWPerState = dml_min( + IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0); + double PixelMixedWithVMDataReturnBWPerState = dml_min( + IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0); + + if (v->HostVMEnable != true) { + v->ReturnBWPerState[i][j] = PixelDataOnlyReturnBWPerState; + } else { + v->ReturnBWPerState[i][j] = PixelMixedWithVMDataReturnBWPerState; + } + } + } + + //Re-ordering Buffer Support Check + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j] + > (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) { + v->ROBSupport[i][j] = true; + } else { + v->ROBSupport[i][j] = false; + } + } + } + + //Vertical Active BW support check + + MaxTotalVActiveRDBandwidth = 0; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]; + } + + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min( + dml_min( + v->ReturnBusWidth * v->DCFCLKState[i][j], + v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn) + * v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100, + v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth + * v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100); + + if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) { + v->TotalVerticalActiveBandwidthSupport[i][j] = true; + } else { + v->TotalVerticalActiveBandwidthSupport[i][j] = false; + } + } + } + + v->UrgentLatency = CalculateUrgentLatency( + v->UrgentLatencyPixelDataOnly, + v->UrgentLatencyPixelMixedWithVMData, + v->UrgentLatencyVMDataOnly, + v->DoUrgentLatencyAdjustment, + v->UrgentLatencyAdjustmentFabricClockComponent, + v->UrgentLatencyAdjustmentFabricClockReference, + v->FabricClock); + //Prefetch Check + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + double VMDataOnlyReturnBWPerState; + double HostVMInefficiencyFactor = 1; + int NextPrefetchModeState = MinPrefetchMode; + bool UnboundedRequestEnabledThisState = false; + int CompressedBufferSizeInkByteThisState = 0; + double dummy; + + v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; + + v->BandwidthWithoutPrefetchSupported[i][j] = true; + if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j] + + v->TotalDPTERowBandwidth[i][j] > v->ReturnBWPerState[i][j] || v->NotEnoughUrgentLatencyHidingA[i][j]) { + v->BandwidthWithoutPrefetchSupported[i][j] = false; + } + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k]; + v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k]; + v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k]; + v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k]; + v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; + v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; + v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + } + + VMDataOnlyReturnBWPerState = dml_min( + dml_min( + v->ReturnBusWidth * v->DCFCLKState[i][j], + v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn) + * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0, + v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth + * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0); + if (v->GPUVMEnable && v->HostVMEnable) + HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState; + + v->ExtraLatency = CalculateExtraLatency( + v->RoundTripPingLatencyCycles, + ReorderingBytes, + v->DCFCLKState[i][j], + v->TotalNumberOfActiveDPP[i][j], + v->PixelChunkSizeInKByte, + v->TotalNumberOfDCCActiveDPP[i][j], + v->MetaChunkSize, + v->ReturnBWPerState[i][j], + v->GPUVMEnable, + v->HostVMEnable, + v->NumberOfActivePlanes, + v->NoOfDPPThisState, + v->dpte_group_bytes, + HostVMInefficiencyFactor, + v->HostVMMinPageSize, + v->HostVMMaxNonCachedPageTableLevels); + + v->NextMaxVStartup = v->MaxMaxVStartup[i][j]; + do { + v->PrefetchModePerState[i][j] = NextPrefetchModeState; + v->MaxVStartup = v->NextMaxVStartup; + + v->TWait = CalculateTWait( + v->PrefetchModePerState[i][j], + v->DRAMClockChangeLatency, + v->UrgLatency[i], + v->SREnterPlusExitTime); + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + Pipe myPipe; + + myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k]; + myPipe.DISPCLK = v->RequiredDISPCLK[i][j]; + myPipe.PixelClock = v->PixelClock[k]; + myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j]; + myPipe.DPPPerPlane = v->NoOfDPP[i][j][k]; + myPipe.ScalerEnabled = v->ScalerEnabled[k]; + myPipe.SourceScan = v->SourceScan[k]; + myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k]; + myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k]; + myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k]; + myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k]; + myPipe.InterlaceEnable = v->Interlace[k]; + myPipe.NumberOfCursors = v->NumberOfCursors[k]; + myPipe.VBlank = v->VTotal[k] - v->VActive[k]; + myPipe.HTotal = v->HTotal[k]; + myPipe.DCCEnable = v->DCCEnable[k]; + myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1 + || v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1; + myPipe.SourcePixelFormat = v->SourcePixelFormat[k]; + myPipe.BytePerPixelY = v->BytePerPixelY[k]; + myPipe.BytePerPixelC = v->BytePerPixelC[k]; + myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP; + v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule( + mode_lib, + HostVMInefficiencyFactor, + &myPipe, + v->DSCDelayPerState[i][k], + v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, + v->DPPCLKDelaySCL, + v->DPPCLKDelaySCLLBOnly, + v->DPPCLKDelayCNVCCursor, + v->DISPCLKDelaySubtotal, + v->SwathWidthYThisState[k] / v->HRatio[k], + v->OutputFormat[k], + v->MaxInterDCNTileRepeaters, + dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + v->MaximumVStartup[i][j][k], + v->GPUVMMaxPageTableLevels, + v->GPUVMEnable, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->HostVMMinPageSize, + v->DynamicMetadataEnable[k], + v->DynamicMetadataVMEnabled, + v->DynamicMetadataLinesBeforeActiveRequired[k], + v->DynamicMetadataTransmittedBytes[k], + v->UrgLatency[i], + v->ExtraLatency, + v->TimeCalc, + v->PDEAndMetaPTEBytesPerFrame[i][j][k], + v->MetaRowBytes[i][j][k], + v->DPTEBytesPerRow[i][j][k], + v->PrefetchLinesY[i][j][k], + v->SwathWidthYThisState[k], + v->PrefillY[k], + v->MaxNumSwY[k], + v->PrefetchLinesC[i][j][k], + v->SwathWidthCThisState[k], + v->PrefillC[k], + v->MaxNumSwC[k], + v->swath_width_luma_ub_this_state[k], + v->swath_width_chroma_ub_this_state[k], + v->SwathHeightYThisState[k], + v->SwathHeightCThisState[k], + v->TWait, + &v->DSTXAfterScaler[k], + &v->DSTYAfterScaler[k], + &v->LineTimesForPrefetch[k], + &v->PrefetchBW[k], + &v->LinesForMetaPTE[k], + &v->LinesForMetaAndDPTERow[k], + &v->VRatioPreY[i][j][k], + &v->VRatioPreC[i][j][k], + &v->RequiredPrefetchPixelDataBWLuma[i][j][k], + &v->RequiredPrefetchPixelDataBWChroma[i][j][k], + &v->NoTimeForDynamicMetadata[i][j][k], + &v->Tno_bw[k], + &v->prefetch_vmrow_bw[k], + &v->dummy7[k], + &v->dummy8[k], + &v->dummy13[k], + &v->VUpdateOffsetPix[k], + &v->VUpdateWidthPix[k], + &v->VReadyOffsetPix[k]); + } + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + CalculateUrgentBurstFactor( + v->swath_width_luma_ub_this_state[k], + v->swath_width_chroma_ub_this_state[k], + v->SwathHeightYThisState[k], + v->SwathHeightCThisState[k], + v->HTotal[k] / v->PixelClock[k], + v->UrgentLatency, + v->CursorBufferSize, + v->CursorWidth[k][0], + v->CursorBPP[k][0], + v->VRatioPreY[i][j][k], + v->VRatioPreC[i][j][k], + v->BytePerPixelInDETY[k], + v->BytePerPixelInDETC[k], + v->DETBufferSizeYThisState[k], + v->DETBufferSizeCThisState[k], + &v->UrgentBurstFactorCursorPre[k], + &v->UrgentBurstFactorLumaPre[k], + &v->UrgentBurstFactorChroma[k], + &v->NotUrgentLatencyHidingPre[k]); + } + + v->MaximumReadBandwidthWithPrefetch = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 + / (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k]; + + v->MaximumReadBandwidthWithPrefetch = + v->MaximumReadBandwidthWithPrefetch + + dml_max4( + v->VActivePixelBandwidth[i][j][k], + v->VActiveCursorBandwidth[i][j][k] + + v->NoOfDPP[i][j][k] + * (v->meta_row_bandwidth[i][j][k] + + v->dpte_row_bandwidth[i][j][k]), + v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k], + v->NoOfDPP[i][j][k] + * (v->RequiredPrefetchPixelDataBWLuma[i][j][k] + * v->UrgentBurstFactorLumaPre[k] + + v->RequiredPrefetchPixelDataBWChroma[i][j][k] + * v->UrgentBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); + } + + v->NotEnoughUrgentLatencyHidingPre = false; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->NotUrgentLatencyHidingPre[k] == true) { + v->NotEnoughUrgentLatencyHidingPre = true; + } + } + + v->PrefetchSupported[i][j] = true; + if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j] + || v->NotEnoughUrgentLatencyHidingPre == 1) { + v->PrefetchSupported[i][j] = false; + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0 + || v->NoTimeForPrefetch[i][j][k] == true) { + v->PrefetchSupported[i][j] = false; + } + } + + v->DynamicMetadataSupported[i][j] = true; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->NoTimeForDynamicMetadata[i][j][k] == true) { + v->DynamicMetadataSupported[i][j] = false; + } + } + + v->VRatioInPrefetchSupported[i][j] = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) { + v->VRatioInPrefetchSupported[i][j] = false; + } + } + v->AnyLinesForVMOrRowTooLarge = false; + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) { + v->AnyLinesForVMOrRowTooLarge = true; + } + } + + v->NextPrefetchMode = v->NextPrefetchMode + 1; + + if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) { + v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j]; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip + - dml_max( + v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k], + v->NoOfDPP[i][j][k] + * (v->RequiredPrefetchPixelDataBWLuma[i][j][k] + * v->UrgentBurstFactorLumaPre[k] + + v->RequiredPrefetchPixelDataBWChroma[i][j][k] + * v->UrgentBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); + } + v->TotImmediateFlipBytes = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + + v->NoOfDPP[i][j][k] * v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k] + + v->DPTEBytesPerRow[i][j][k]; + } + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + CalculateFlipSchedule( + mode_lib, + HostVMInefficiencyFactor, + v->ExtraLatency, + v->UrgLatency[i], + v->GPUVMMaxPageTableLevels, + v->HostVMEnable, + v->HostVMMaxNonCachedPageTableLevels, + v->GPUVMEnable, + v->HostVMMinPageSize, + v->PDEAndMetaPTEBytesPerFrame[i][j][k], + v->MetaRowBytes[i][j][k], + v->DPTEBytesPerRow[i][j][k], + v->BandwidthAvailableForImmediateFlip, + v->TotImmediateFlipBytes, + v->SourcePixelFormat[k], + v->HTotal[k] / v->PixelClock[k], + v->VRatio[k], + v->VRatioChroma[k], + v->Tno_bw[k], + v->DCCEnable[k], + v->dpte_row_height[k], + v->meta_row_height[k], + v->dpte_row_height_chroma[k], + v->meta_row_height_chroma[k], + &v->DestinationLinesToRequestVMInImmediateFlip[k], + &v->DestinationLinesToRequestRowInImmediateFlip[k], + &v->final_flip_bw[k], + &v->ImmediateFlipSupportedForPipe[k]); + } + v->total_dcn_read_bw_with_flip = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip + + dml_max3( + v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k], + v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k] + + v->VActiveCursorBandwidth[i][j][k], + v->NoOfDPP[i][j][k] + * (v->final_flip_bw[k] + + v->RequiredPrefetchPixelDataBWLuma[i][j][k] + * v->UrgentBurstFactorLumaPre[k] + + v->RequiredPrefetchPixelDataBWChroma[i][j][k] + * v->UrgentBurstFactorChromaPre[k]) + + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); + } + v->ImmediateFlipSupportedForState[i][j] = true; + if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) { + v->ImmediateFlipSupportedForState[i][j] = false; + } + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->ImmediateFlipSupportedForPipe[k] == false) { + v->ImmediateFlipSupportedForState[i][j] = false; + } + } + } else { + v->ImmediateFlipSupportedForState[i][j] = false; + } + + if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) { + v->NextMaxVStartup = v->MaxMaxVStartup[i][j]; + NextPrefetchModeState = NextPrefetchModeState + 1; + } else { + v->NextMaxVStartup = v->NextMaxVStartup - 1; + } + v->NextPrefetchMode = v->NextPrefetchMode + 1; + } while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true + && ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required) + || v->ImmediateFlipSupportedForState[i][j] == true)) + || (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode))); + + CalculateUnboundedRequestAndCompressedBufferSize( + v->DETBufferSizeInKByte[0], + v->ConfigReturnBufferSizeInKByte, + v->UseUnboundedRequesting, + v->TotalNumberOfActiveDPP[i][j], + NoChroma, + v->MaxNumDPP, + v->CompressedBufferSegmentSizeInkByte, + v->Output, + &UnboundedRequestEnabledThisState, + &CompressedBufferSizeInkByteThisState); + + CalculateWatermarksAndDRAMSpeedChangeSupport( + mode_lib, + v->PrefetchModePerState[i][j], + v->NumberOfActivePlanes, + v->MaxLineBufferLines, + v->LineBufferSize, + v->WritebackInterfaceBufferSize, + v->DCFCLKState[i][j], + v->ReturnBWPerState[i][j], + v->SynchronizedVBlank, + v->dpte_group_bytes, + v->MetaChunkSize, + v->UrgLatency[i], + v->ExtraLatency, + v->WritebackLatency, + v->WritebackChunkSize, + v->SOCCLKPerState[i], + v->DRAMClockChangeLatency, + v->SRExitTime, + v->SREnterPlusExitTime, + v->SRExitZ8Time, + v->SREnterPlusExitZ8Time, + v->ProjectedDCFCLKDeepSleep[i][j], + v->DETBufferSizeYThisState, + v->DETBufferSizeCThisState, + v->SwathHeightYThisState, + v->SwathHeightCThisState, + v->LBBitPerPixel, + v->SwathWidthYThisState, + v->SwathWidthCThisState, + v->HRatio, + v->HRatioChroma, + v->vtaps, + v->VTAPsChroma, + v->VRatio, + v->VRatioChroma, + v->HTotal, + v->PixelClock, + v->BlendingAndTiming, + v->NoOfDPPThisState, + v->BytePerPixelInDETY, + v->BytePerPixelInDETC, + v->DSTXAfterScaler, + v->DSTYAfterScaler, + v->WritebackEnable, + v->WritebackPixelFormat, + v->WritebackDestinationWidth, + v->WritebackDestinationHeight, + v->WritebackSourceHeight, + UnboundedRequestEnabledThisState, + CompressedBufferSizeInkByteThisState, + &v->DRAMClockChangeSupport[i][j], + &v->UrgentWatermark, + &v->WritebackUrgentWatermark, + &v->DRAMClockChangeWatermark, + &v->WritebackDRAMClockChangeWatermark, + &dummy, + &dummy, + &dummy, + &dummy, + &v->MinActiveDRAMClockChangeLatencySupported); + } + } + + /*PTE Buffer Size Check*/ + for (i = 0; i < v->soc.num_states; i++) { + for (j = 0; j < 2; j++) { + v->PTEBufferSizeNotExceeded[i][j] = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) { + v->PTEBufferSizeNotExceeded[i][j] = false; + } + } + } + } + + /*Cursor Support Check*/ + v->CursorSupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->CursorWidth[k][0] > 0.0) { + if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) { + v->CursorSupport = false; + } + } + } + + /*Valid Pitch Check*/ + v->PitchSupport = true; + for (k = 0; k < v->NumberOfActivePlanes; k++) { + v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]); + if (v->DCCEnable[k] == true) { + v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]); + } else { + v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k]; + } + if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16 + && v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe + && v->SourcePixelFormat[k] != dm_mono_8) { + v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]); + if (v->DCCEnable[k] == true) { + v->AlignedDCCMetaPitchC[k] = dml_ceil( + dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]), + 64.0 * v->Read256BlockWidthC[k]); + } else { + v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k]; + } + } else { + v->AlignedCPitch[k] = v->PitchC[k]; + v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k]; + } + if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] + || v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) { + v->PitchSupport = false; + } + } + + for (k = 0; k < v->NumberOfActivePlanes; k++) { + if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) { + ViewportExceedsSurface = true; + if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 + && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8 + && v->SourcePixelFormat[k] != dm_rgbe) { + if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] + || v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) { + ViewportExceedsSurface = true; + } + } + } + } + + /*Mode Support, Voltage State and SOC Configuration*/ + for (i = v->soc.num_states - 1; i >= 0; i--) { + for (j = 0; j < 2; j++) { + if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true + && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP + && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false + && v->DTBCLKRequiredMoreThanSupported[i] == false + && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true + && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true + && v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true + && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false + && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true + && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true + && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false + && ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required) + || v->ImmediateFlipSupportedForState[i][j] == true) + && FMTBufferExceeded == false) { + v->ModeSupport[i][j] = true; + } else { + v->ModeSupport[i][j] = false; + } + } + } + + { + unsigned int MaximumMPCCombine = 0; + for (i = v->soc.num_states; i >= 0; i--) { + if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { + v->VoltageLevel = i; + v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; + if (v->ModeSupport[i][0] == true) { + MaximumMPCCombine = 0; + } else { + MaximumMPCCombine = 1; + } + } + } + v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine]; + for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { + v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k]; + v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; + } + v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; + v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel]; + v->FabricClock = v->FabricClockPerState[v->VoltageLevel]; + v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel]; + v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine]; + v->maxMpcComb = MaximumMPCCombine; + } +} + +static void CalculateWatermarksAndDRAMSpeedChangeSupport( + struct display_mode_lib *mode_lib, + unsigned int PrefetchMode, + unsigned int NumberOfActivePlanes, + unsigned int MaxLineBufferLines, + unsigned int LineBufferSize, + unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, + bool SynchronizedVBlank, + unsigned int dpte_group_bytes[], + unsigned int MetaChunkSize, + double UrgentLatency, + double ExtraLatency, + double WritebackLatency, + double WritebackChunkSize, + double SOCCLK, + double DRAMClockChangeLatency, + double SRExitTime, + double SREnterPlusExitTime, + double SRExitZ8Time, + double SREnterPlusExitZ8Time, + double DCFCLKDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], + unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], + double HRatio[], + double HRatioChroma[], + unsigned int vtaps[], + unsigned int VTAPsChroma[], + double VRatio[], + double VRatioChroma[], + unsigned int HTotal[], + double PixelClock[], + unsigned int BlendingAndTiming[], + unsigned int DPPPerPlane[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], + double DSTXAfterScaler[], + double DSTYAfterScaler[], + bool WritebackEnable[], + enum source_format_class WritebackPixelFormat[], + double WritebackDestinationWidth[], + double WritebackDestinationHeight[], + double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + int unsigned CompressedBufferSizeInkByte, + enum clock_change_support *DRAMClockChangeSupport, + double *UrgentWatermark, + double *WritebackUrgentWatermark, + double *DRAMClockChangeWatermark, + double *WritebackDRAMClockChangeWatermark, + double *StutterExitWatermark, + double *StutterEnterPlusExitWatermark, + double *Z8StutterExitWatermark, + double *Z8StutterEnterPlusExitWatermark, + double *MinActiveDRAMClockChangeLatencySupported) +{ + struct vba_vars_st *v = &mode_lib->vba; + double EffectiveLBLatencyHidingY; + double EffectiveLBLatencyHidingC; + double LinesInDETY[DC__NUM_DPP__MAX]; + double LinesInDETC; + unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; + unsigned int LinesInDETCRoundedDownToSwath; + double FullDETBufferingTimeY; + double FullDETBufferingTimeC; + double ActiveDRAMClockChangeLatencyMarginY; + double ActiveDRAMClockChangeLatencyMarginC; + double WritebackDRAMClockChangeLatencyMargin; + double PlaneWithMinActiveDRAMClockChangeMargin; + double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; + double WritebackDRAMClockChangeLatencyHiding; + double TotalPixelBW = 0.0; + int k, j; + + *UrgentWatermark = UrgentLatency + ExtraLatency; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency); + dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency); + dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark); +#endif + + *DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency); + dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark); +#endif + + v->TotalActiveWriteback = 0; + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (WritebackEnable[k] == true) { + v->TotalActiveWriteback = v->TotalActiveWriteback + 1; + } + } + + if (v->TotalActiveWriteback <= 1) { + *WritebackUrgentWatermark = WritebackLatency; + } else { + *WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + } + + if (v->TotalActiveWriteback <= 1) { + *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency; + } else { + *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + TotalPixelBW = TotalPixelBW + + DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) + / (HTotal[k] / PixelClock[k]); + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + double EffectiveDETBufferSizeY = DETBufferSizeY[k]; + + v->LBLatencyHidingSourceLinesY = dml_min( + (double) MaxLineBufferLines, + dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1); + + v->LBLatencyHidingSourceLinesC = dml_min( + (double) MaxLineBufferLines, + dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1); + + EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); + + EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); + + if (UnboundedRequestEnabled) { + EffectiveDETBufferSizeY = EffectiveDETBufferSizeY + + CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW; + } + + LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; + if (BytePerPixelDETC[k] > 0) { + LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; + LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k]; + } else { + LinesInDETC = 0; + FullDETBufferingTimeC = 999999; + } + + ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY + - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; + + if (NumberOfActivePlanes > 1) { + ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY + - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; + } + + if (BytePerPixelDETC[k] > 0) { + ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC + - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; + + if (NumberOfActivePlanes > 1) { + ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC + - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k]; + } + v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC); + } else { + v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; + } + + if (WritebackEnable[k] == true) { + WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 + / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); + if (WritebackPixelFormat[k] == dm_444_64) { + WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2; + } + WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark; + v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin); + } + } + + v->MinActiveDRAMClockChangeMargin = 999999; + PlaneWithMinActiveDRAMClockChangeMargin = 0; + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) { + v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k]; + if (BlendingAndTiming[k] == k) { + PlaneWithMinActiveDRAMClockChangeMargin = k; + } else { + for (j = 0; j < NumberOfActivePlanes; ++j) { + if (BlendingAndTiming[k] == j) { + PlaneWithMinActiveDRAMClockChangeMargin = j; + } + } + } + } + } + + *MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency; + + SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999; + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) + && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { + SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k]; + } + } + + v->TotalNumberOfActiveOTG = 0; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (BlendingAndTiming[k] == k) { + v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1; + } + } + + if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) { + *DRAMClockChangeSupport = dm_dram_clock_change_vactive; + } else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 + || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) { + *DRAMClockChangeSupport = dm_dram_clock_change_vblank; + } else { + *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; + } + + *StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; + *StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep); + *Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; + *Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark); + dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, *StutterEnterPlusExitWatermark); + dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, *Z8StutterExitWatermark); + dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, *Z8StutterEnterPlusExitWatermark); +#endif +} + +static void CalculateDCFCLKDeepSleep( + struct display_mode_lib *mode_lib, + unsigned int NumberOfActivePlanes, + int BytePerPixelY[], + int BytePerPixelC[], + double VRatio[], + double VRatioChroma[], + double SwathWidthY[], + double SwathWidthC[], + unsigned int DPPPerPlane[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double DPPCLK[], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + int ReturnBusWidth, + double *DCFCLKDeepSleep) +{ + struct vba_vars_st *v = &mode_lib->vba; + double DisplayPipeLineDeliveryTimeLuma; + double DisplayPipeLineDeliveryTimeChroma; + double ReadBandwidth = 0.0; + int k; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + + if (VRatio[k] <= 1) { + DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k]; + } + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChroma = 0; + } else { + if (VRatioChroma[k] <= 1) { + DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; + } + } + + if (BytePerPixelC[k] > 0) { + v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma, + __DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma); + } else { + v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma; + } + v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16); + + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k]; + } + + *DCFCLKDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / ReturnBusWidth); + + for (k = 0; k < NumberOfActivePlanes; ++k) { + *DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]); + } +} + +static void CalculateUrgentBurstFactor( + int swath_width_luma_ub, + int swath_width_chroma_ub, + unsigned int SwathHeightY, + unsigned int SwathHeightC, + double LineTime, + double UrgentLatency, + double CursorBufferSize, + unsigned int CursorWidth, + unsigned int CursorBPP, + double VRatio, + double VRatioC, + double BytePerPixelInDETY, + double BytePerPixelInDETC, + double DETBufferSizeY, + double DETBufferSizeC, + double *UrgentBurstFactorCursor, + double *UrgentBurstFactorLuma, + double *UrgentBurstFactorChroma, + bool *NotEnoughUrgentLatencyHiding) +{ + double LinesInDETLuma; + double LinesInDETChroma; + unsigned int LinesInCursorBuffer; + double CursorBufferSizeInTime; + double DETBufferSizeInTimeLuma; + double DETBufferSizeInTimeChroma; + + *NotEnoughUrgentLatencyHiding = 0; + + if (CursorWidth > 0) { + LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0); + if (VRatio > 0) { + CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio; + if (CursorBufferSizeInTime - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorCursor = 0; + } else { + *UrgentBurstFactorCursor = CursorBufferSizeInTime / (CursorBufferSizeInTime - UrgentLatency); + } + } else { + *UrgentBurstFactorCursor = 1; + } + } + + LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / swath_width_luma_ub; + if (VRatio > 0) { + DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio; + if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorLuma = 0; + } else { + *UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency); + } + } else { + *UrgentBurstFactorLuma = 1; + } + + if (BytePerPixelInDETC > 0) { + LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / swath_width_chroma_ub; + if (VRatio > 0) { + DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio; + if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) { + *NotEnoughUrgentLatencyHiding = 1; + *UrgentBurstFactorChroma = 0; + } else { + *UrgentBurstFactorChroma = DETBufferSizeInTimeChroma / (DETBufferSizeInTimeChroma - UrgentLatency); + } + } else { + *UrgentBurstFactorChroma = 1; + } + } +} + +static void CalculatePixelDeliveryTimes( + unsigned int NumberOfActivePlanes, + double VRatio[], + double VRatioChroma[], + double VRatioPrefetchY[], + double VRatioPrefetchC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + double HRatio[], + double HRatioChroma[], + double PixelClock[], + double PSCL_THROUGHPUT[], + double PSCL_THROUGHPUT_CHROMA[], + double DPPCLK[], + int BytePerPixelC[], + enum scan_direction_class SourceScan[], + unsigned int NumberOfCursors[], + unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], + unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesC[], + unsigned int BlockHeight256BytesC[], + double DisplayPipeLineDeliveryTimeLuma[], + double DisplayPipeLineDeliveryTimeChroma[], + double DisplayPipeLineDeliveryTimeLumaPrefetch[], + double DisplayPipeLineDeliveryTimeChromaPrefetch[], + double DisplayPipeRequestDeliveryTimeLuma[], + double DisplayPipeRequestDeliveryTimeChroma[], + double DisplayPipeRequestDeliveryTimeLumaPrefetch[], + double DisplayPipeRequestDeliveryTimeChromaPrefetch[], + double CursorRequestDeliveryTime[], + double CursorRequestDeliveryTimePrefetch[]) +{ + double req_per_swath_ub; + int k; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (VRatio[k] <= 1) { + DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k]; + } + + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChroma[k] = 0; + } else { + if (VRatioChroma[k] <= 1) { + DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; + } + } + + if (VRatioPrefetchY[k] <= 1) { + DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k]; + } + + if (BytePerPixelC[k] == 0) { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; + } else { + if (VRatioPrefetchC[k] <= 1) { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k]; + } else { + DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; + } + } + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (SourceScan[k] != dm_vert) { + req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k]; + } else { + req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k]; + } + DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub; + DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub; + if (BytePerPixelC[k] == 0) { + DisplayPipeRequestDeliveryTimeChroma[k] = 0; + DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0; + } else { + if (SourceScan[k] != dm_vert) { + req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k]; + } else { + req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k]; + } + DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub; + DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]); + dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]); + dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]); + dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]); + dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]); + dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]); +#endif + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + int cursor_req_per_width; + cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + if (NumberOfCursors[k] > 0) { + if (VRatio[k] <= 1) { + CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; + } else { + CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width; + } + if (VRatioPrefetchY[k] <= 1) { + CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; + } else { + CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width; + } + } else { + CursorRequestDeliveryTime[k] = 0; + CursorRequestDeliveryTimePrefetch[k] = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]); + dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]); + dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]); +#endif + } +} + +static void CalculateMetaAndPTETimes( + int NumberOfActivePlanes, + bool GPUVMEnable, + int MetaChunkSize, + int MinMetaChunkSizeBytes, + int HTotal[], + double VRatio[], + double VRatioChroma[], + double DestinationLinesToRequestRowInVBlank[], + double DestinationLinesToRequestRowInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + int BytePerPixelY[], + int BytePerPixelC[], + enum scan_direction_class SourceScan[], + int dpte_row_height[], + int dpte_row_height_chroma[], + int meta_row_width[], + int meta_row_width_chroma[], + int meta_row_height[], + int meta_row_height_chroma[], + int meta_req_width[], + int meta_req_width_chroma[], + int meta_req_height[], + int meta_req_height_chroma[], + int dpte_group_bytes[], + int PTERequestSizeY[], + int PTERequestSizeC[], + int PixelPTEReqWidthY[], + int PixelPTEReqHeightY[], + int PixelPTEReqWidthC[], + int PixelPTEReqHeightC[], + int dpte_row_width_luma_ub[], + int dpte_row_width_chroma_ub[], + double DST_Y_PER_PTE_ROW_NOM_L[], + double DST_Y_PER_PTE_ROW_NOM_C[], + double DST_Y_PER_META_ROW_NOM_L[], + double DST_Y_PER_META_ROW_NOM_C[], + double TimePerMetaChunkNominal[], + double TimePerChromaMetaChunkNominal[], + double TimePerMetaChunkVBlank[], + double TimePerChromaMetaChunkVBlank[], + double TimePerMetaChunkFlip[], + double TimePerChromaMetaChunkFlip[], + double time_per_pte_group_nom_luma[], + double time_per_pte_group_vblank_luma[], + double time_per_pte_group_flip_luma[], + double time_per_pte_group_nom_chroma[], + double time_per_pte_group_vblank_chroma[], + double time_per_pte_group_flip_chroma[]) +{ + unsigned int meta_chunk_width; + unsigned int min_meta_chunk_width; + unsigned int meta_chunk_per_row_int; + unsigned int meta_row_remainder; + unsigned int meta_chunk_threshold; + unsigned int meta_chunks_per_row_ub; + unsigned int meta_chunk_width_chroma; + unsigned int min_meta_chunk_width_chroma; + unsigned int meta_chunk_per_row_int_chroma; + unsigned int meta_row_remainder_chroma; + unsigned int meta_chunk_threshold_chroma; + unsigned int meta_chunks_per_row_ub_chroma; + unsigned int dpte_group_width_luma; + unsigned int dpte_groups_per_row_luma_ub; + unsigned int dpte_group_width_chroma; + unsigned int dpte_groups_per_row_chroma_ub; + int k; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; + if (BytePerPixelC[k] == 0) { + DST_Y_PER_PTE_ROW_NOM_C[k] = 0; + } else { + DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k]; + } + DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k]; + if (BytePerPixelC[k] == 0) { + DST_Y_PER_META_ROW_NOM_C[k] = 0; + } else { + DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k]; + } + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (DCCEnable[k] == true) { + meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k]; + min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k]; + meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; + meta_row_remainder = meta_row_width[k] % meta_chunk_width; + if (SourceScan[k] != dm_vert) { + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; + } else { + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; + } + if (meta_row_remainder <= meta_chunk_threshold) { + meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; + } else { + meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; + } + TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; + if (BytePerPixelC[k] == 0) { + TimePerChromaMetaChunkNominal[k] = 0; + TimePerChromaMetaChunkVBlank[k] = 0; + TimePerChromaMetaChunkFlip[k] = 0; + } else { + meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; + min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; + meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; + if (SourceScan[k] != dm_vert) { + meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; + } else { + meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k]; + } + if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma) { + meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1; + } else { + meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2; + } + TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma; + } + } else { + TimePerMetaChunkNominal[k] = 0; + TimePerMetaChunkVBlank[k] = 0; + TimePerMetaChunkFlip[k] = 0; + TimePerChromaMetaChunkNominal[k] = 0; + TimePerChromaMetaChunkVBlank[k] = 0; + TimePerChromaMetaChunkFlip[k] = 0; + } + } + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (GPUVMEnable == true) { + if (SourceScan[k] != dm_vert) { + dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k]; + } else { + dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; + } + dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; + if (BytePerPixelC[k] == 0) { + time_per_pte_group_nom_chroma[k] = 0; + time_per_pte_group_vblank_chroma[k] = 0; + time_per_pte_group_flip_chroma[k] = 0; + } else { + if (SourceScan[k] != dm_vert) { + dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k]; + } else { + dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; + } + dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; + } + } else { + time_per_pte_group_nom_luma[k] = 0; + time_per_pte_group_vblank_luma[k] = 0; + time_per_pte_group_flip_luma[k] = 0; + time_per_pte_group_nom_chroma[k] = 0; + time_per_pte_group_vblank_chroma[k] = 0; + time_per_pte_group_flip_chroma[k] = 0; + } + } +} + +static void CalculateVMGroupAndRequestTimes( + unsigned int NumberOfActivePlanes, + bool GPUVMEnable, + unsigned int GPUVMMaxPageTableLevels, + unsigned int HTotal[], + int BytePerPixelC[], + double DestinationLinesToRequestVMInVBlank[], + double DestinationLinesToRequestVMInImmediateFlip[], + bool DCCEnable[], + double PixelClock[], + int dpte_row_width_luma_ub[], + int dpte_row_width_chroma_ub[], + int vm_group_bytes[], + unsigned int dpde0_bytes_per_frame_ub_l[], + unsigned int dpde0_bytes_per_frame_ub_c[], + int meta_pte_bytes_per_frame_ub_l[], + int meta_pte_bytes_per_frame_ub_c[], + double TimePerVMGroupVBlank[], + double TimePerVMGroupFlip[], + double TimePerVMRequestVBlank[], + double TimePerVMRequestFlip[]) +{ + int num_group_per_lower_vm_stage; + int num_req_per_lower_vm_stage; + int k; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { + if (DCCEnable[k] == false) { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + } else { + num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + } + } else { + if (GPUVMMaxPageTableLevels == 1) { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + } else { + num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + } + } else { + if (BytePerPixelC[k] > 0) { + num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + } else { + num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + } + } + } + + if (DCCEnable[k] == false) { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64; + } + } else { + if (GPUVMMaxPageTableLevels == 1) { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64; + } + } else { + if (BytePerPixelC[k] > 0) { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64 + + meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64; + } else { + num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64; + } + } + } + + TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; + TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; + TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; + TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; + + if (GPUVMMaxPageTableLevels > 2) { + TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2; + TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2; + TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2; + TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2; + } + + } else { + TimePerVMGroupVBlank[k] = 0; + TimePerVMGroupFlip[k] = 0; + TimePerVMRequestVBlank[k] = 0; + TimePerVMRequestFlip[k] = 0; + } + } +} + +static void CalculateStutterEfficiency( + struct display_mode_lib *mode_lib, + int CompressedBufferSizeInkByte, + bool UnboundedRequestEnabled, + int ConfigReturnBufferSizeInKByte, + int MetaFIFOSizeInKEntries, + int ZeroSizeBufferEntries, + int NumberOfActivePlanes, + int ROBBufferSizeInKByte, + double TotalDataReadBandwidth, + double DCFCLK, + double ReturnBW, + double COMPBUF_RESERVED_SPACE_64B, + double COMPBUF_RESERVED_SPACE_ZS, + double SRExitTime, + double SRExitZ8Time, + bool SynchronizedVBlank, + double Z8StutterEnterPlusExitWatermark, + double StutterEnterPlusExitWatermark, + bool ProgressiveToInterlaceUnitInOPP, + bool Interlace[], + double MinTTUVBlank[], + int DPPPerPlane[], + unsigned int DETBufferSizeY[], + int BytePerPixelY[], + double BytePerPixelDETY[], + double SwathWidthY[], + int SwathHeightY[], + int SwathHeightC[], + double NetDCCRateLuma[], + double NetDCCRateChroma[], + double DCCFractionOfZeroSizeRequestsLuma[], + double DCCFractionOfZeroSizeRequestsChroma[], + int HTotal[], + int VTotal[], + double PixelClock[], + double VRatio[], + enum scan_direction_class SourceScan[], + int BlockHeight256BytesY[], + int BlockWidth256BytesY[], + int BlockHeight256BytesC[], + int BlockWidth256BytesC[], + int DCCYMaxUncompressedBlock[], + int DCCCMaxUncompressedBlock[], + int VActive[], + bool DCCEnable[], + bool WritebackEnable[], + double ReadBandwidthPlaneLuma[], + double ReadBandwidthPlaneChroma[], + double meta_row_bw[], + double dpte_row_bw[], + double *StutterEfficiencyNotIncludingVBlank, + double *StutterEfficiency, + int *NumberOfStutterBurstsPerFrame, + double *Z8StutterEfficiencyNotIncludingVBlank, + double *Z8StutterEfficiency, + int *Z8NumberOfStutterBurstsPerFrame, + double *StutterPeriod) +{ + struct vba_vars_st *v = &mode_lib->vba; + + double DETBufferingTimeY; + double SwathWidthYCriticalPlane = 0; + double VActiveTimeCriticalPlane = 0; + double FrameTimeCriticalPlane = 0; + int BytePerPixelYCriticalPlane = 0; + double LinesToFinishSwathTransferStutterCriticalPlane = 0; + double MinTTUVBlankCriticalPlane = 0; + double TotalCompressedReadBandwidth; + double TotalRowReadBandwidth; + double AverageDCCCompressionRate; + double EffectiveCompressedBufferSize; + double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; + double StutterBurstTime; + int TotalActiveWriteback; + double LinesInDETY; + double LinesInDETYRoundedDownToSwath; + double MaximumEffectiveCompressionLuma; + double MaximumEffectiveCompressionChroma; + double TotalZeroSizeRequestReadBandwidth; + double TotalZeroSizeCompressedReadBandwidth; + double AverageDCCZeroSizeFraction; + double AverageZeroSizeCompressionRate; + int TotalNumberOfActiveOTG = 0; + double LastStutterPeriod = 0.0; + double LastZ8StutterPeriod = 0.0; + int k; + + TotalZeroSizeRequestReadBandwidth = 0; + TotalZeroSizeCompressedReadBandwidth = 0; + TotalRowReadBandwidth = 0; + TotalCompressedReadBandwidth = 0; + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (DCCEnable[k] == true) { + if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k]) + || DCCYMaxUncompressedBlock[k] < 256) { + MaximumEffectiveCompressionLuma = 2; + } else { + MaximumEffectiveCompressionLuma = 4; + } + TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma); + TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]; + TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma; + if (ReadBandwidthPlaneChroma[k] > 0) { + if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k]) + || (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) { + MaximumEffectiveCompressionChroma = 2; + } else { + MaximumEffectiveCompressionChroma = 4; + } + TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + + ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma); + TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k]; + TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma; + } + } else { + TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k]; + } + TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]); + } + + AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth; + AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth); + dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth); + dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n", __func__, TotalZeroSizeCompressedReadBandwidth); + dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma); + dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma); + dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate); + dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction); + dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte); +#endif + + if (AverageDCCZeroSizeFraction == 1) { + AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth; + EffectiveCompressedBufferSize = MetaFIFOSizeInKEntries * 1024 * 64 * AverageZeroSizeCompressionRate + (ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 * AverageZeroSizeCompressionRate; + } else if (AverageDCCZeroSizeFraction > 0) { + AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth; + EffectiveCompressedBufferSize = dml_min( + CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate, + MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate)) + + dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate, + (ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate)); + dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate); + dml_print( + "DML::%s: min 2 = %f\n", + __func__, + MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate)); + dml_print("DML::%s: min 3 = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate); + dml_print("DML::%s: min 4 = %f\n", __func__, ZeroSizeBufferEntries * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate)); + } else { + EffectiveCompressedBufferSize = dml_min( + CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate, + MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate) + (ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate; + dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate); + dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate); + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries); + dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate); + dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize); +#endif + + *StutterPeriod = 0; + for (k = 0; k < NumberOfActivePlanes; ++k) { + LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth) + / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]); + DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k]; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]); + dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]); + dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]); + dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]); + dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth); + dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY); + dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath); + dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]); + dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]); + dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]); + dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY); + dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]); +#endif + + if (k == 0 || DETBufferingTimeY < *StutterPeriod) { + bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP; + + *StutterPeriod = DETBufferingTimeY; + FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k]; + VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k]; + BytePerPixelYCriticalPlane = BytePerPixelY[k]; + SwathWidthYCriticalPlane = SwathWidthY[k]; + LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath); + MinTTUVBlankCriticalPlane = MinTTUVBlank[k]; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod); + dml_print("DML::%s: MinTTUVBlankCriticalPlane = %f\n", __func__, MinTTUVBlankCriticalPlane); + dml_print("DML::%s: FrameTimeCriticalPlane = %f\n", __func__, FrameTimeCriticalPlane); + dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane); + dml_print("DML::%s: BytePerPixelYCriticalPlane = %d\n", __func__, BytePerPixelYCriticalPlane); + dml_print("DML::%s: SwathWidthYCriticalPlane = %f\n", __func__, SwathWidthYCriticalPlane); + dml_print("DML::%s: LinesToFinishSwathTransferStutterCriticalPlane = %f\n", __func__, LinesToFinishSwathTransferStutterCriticalPlane); +#endif + } + } + + PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize); +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte); + dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate); + dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, *StutterPeriod * TotalDataReadBandwidth); + dml_print("DML::%s: ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize); + dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize); + dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer); + dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW); + dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth); + dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth); + dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK); +#endif + + StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW + + (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64) + + *StutterPeriod * TotalRowReadBandwidth / ReturnBW; +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW); + dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth)); + dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)); + dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW); + dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime); +#endif + StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW); + + dml_print( + "DML::%s: Time to finish residue swath=%f\n", + __func__, + LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW); + + TotalActiveWriteback = 0; + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (WritebackEnable[k]) { + TotalActiveWriteback = TotalActiveWriteback + 1; + } + } + + if (TotalActiveWriteback == 0) { +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime); + dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time); + dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime); + dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod); +#endif + *StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; + *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; + *NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + } else { + *StutterEfficiencyNotIncludingVBlank = 0.; + *Z8StutterEfficiencyNotIncludingVBlank = 0.; + *NumberOfStutterBurstsPerFrame = 0; + *Z8NumberOfStutterBurstsPerFrame = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane); + dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *Z8StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame); + dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); +#endif + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] == k) { + TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1; + } + } + + if (*StutterEfficiencyNotIncludingVBlank > 0) { + LastStutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod; + + if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastStutterPeriod + MinTTUVBlankCriticalPlane > StutterEnterPlusExitWatermark) { + *StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime + StutterBurstTime * VActiveTimeCriticalPlane + / *StutterPeriod) / FrameTimeCriticalPlane) * 100; + } else { + *StutterEfficiency = *StutterEfficiencyNotIncludingVBlank; + } + } else { + *StutterEfficiency = 0; + } + + if (*Z8StutterEfficiencyNotIncludingVBlank > 0) { + LastZ8StutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod; + if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastZ8StutterPeriod + MinTTUVBlankCriticalPlane > Z8StutterEnterPlusExitWatermark) { + *Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime * VActiveTimeCriticalPlane + / *StutterPeriod) / FrameTimeCriticalPlane) * 100; + } else { + *Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank; + } + } else { + *Z8StutterEfficiency = 0.; + } + + dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod); + dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark); + dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime); + dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod); + dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency); + dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency); + dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank); + dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); +} + +static void CalculateSwathAndDETConfiguration( + bool ForceSingleDPP, + int NumberOfActivePlanes, + unsigned int DETBufferSizeInKByte, + double MaximumSwathWidthLuma[], + double MaximumSwathWidthChroma[], + enum scan_direction_class SourceScan[], + enum source_format_class SourcePixelFormat[], + enum dm_swizzle_mode SurfaceTiling[], + int ViewportWidth[], + int ViewportHeight[], + int SurfaceWidthY[], + int SurfaceWidthC[], + int SurfaceHeightY[], + int SurfaceHeightC[], + int Read256BytesBlockHeightY[], + int Read256BytesBlockHeightC[], + int Read256BytesBlockWidthY[], + int Read256BytesBlockWidthC[], + enum odm_combine_mode ODMCombineEnabled[], + int BlendingAndTiming[], + int BytePerPixY[], + int BytePerPixC[], + double BytePerPixDETY[], + double BytePerPixDETC[], + int HActive[], + double HRatio[], + double HRatioChroma[], + int DPPPerPlane[], + int swath_width_luma_ub[], + int swath_width_chroma_ub[], + double SwathWidth[], + double SwathWidthChroma[], + int SwathHeightY[], + int SwathHeightC[], + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + bool ViewportSizeSupportPerPlane[], + bool *ViewportSizeSupport) +{ + int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + int MinimumSwathHeightY; + int MinimumSwathHeightC; + int RoundedUpMaxSwathSizeBytesY; + int RoundedUpMaxSwathSizeBytesC; + int RoundedUpMinSwathSizeBytesY; + int RoundedUpMinSwathSizeBytesC; + int RoundedUpSwathSizeBytesY; + int RoundedUpSwathSizeBytesC; + double SwathWidthSingleDPP[DC__NUM_DPP__MAX]; + double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX]; + int k; + + CalculateSwathWidth( + ForceSingleDPP, + NumberOfActivePlanes, + SourcePixelFormat, + SourceScan, + ViewportWidth, + ViewportHeight, + SurfaceWidthY, + SurfaceWidthC, + SurfaceHeightY, + SurfaceHeightC, + ODMCombineEnabled, + BytePerPixY, + BytePerPixC, + Read256BytesBlockHeightY, + Read256BytesBlockHeightC, + Read256BytesBlockWidthY, + Read256BytesBlockWidthC, + BlendingAndTiming, + HActive, + HRatio, + DPPPerPlane, + SwathWidthSingleDPP, + SwathWidthSingleDPPChroma, + SwathWidth, + SwathWidthChroma, + MaximumSwathHeightY, + MaximumSwathHeightC, + swath_width_luma_ub, + swath_width_chroma_ub); + + *ViewportSizeSupport = true; + for (k = 0; k < NumberOfActivePlanes; ++k) { + if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16 + || SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) { + if (SurfaceTiling[k] == dm_sw_linear + || (SourcePixelFormat[k] == dm_444_64 + && (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x) + && SourceScan[k] != dm_vert)) { + MinimumSwathHeightY = MaximumSwathHeightY[k]; + } else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) { + MinimumSwathHeightY = MaximumSwathHeightY[k]; + } else { + MinimumSwathHeightY = MaximumSwathHeightY[k] / 2; + } + MinimumSwathHeightC = MaximumSwathHeightC[k]; + } else { + if (SurfaceTiling[k] == dm_sw_linear) { + MinimumSwathHeightY = MaximumSwathHeightY[k]; + MinimumSwathHeightC = MaximumSwathHeightC[k]; + } else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) { + MinimumSwathHeightY = MaximumSwathHeightY[k] / 2; + MinimumSwathHeightC = MaximumSwathHeightC[k]; + } else if (SourcePixelFormat[k] == dm_rgbe_alpha) { + MinimumSwathHeightY = MaximumSwathHeightY[k] / 2; + MinimumSwathHeightC = MaximumSwathHeightC[k] / 2; + } else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) { + MinimumSwathHeightY = MaximumSwathHeightY[k]; + MinimumSwathHeightC = MaximumSwathHeightC[k] / 2; + } else { + MinimumSwathHeightC = MaximumSwathHeightC[k] / 2; + MinimumSwathHeightY = MaximumSwathHeightY[k] / 2; + } + } + + RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; + RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY; + if (SourcePixelFormat[k] == dm_420_10) { + RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + } + RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; + RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC; + if (SourcePixelFormat[k] == dm_420_10) { + RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + } + + if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { + SwathHeightY[k] = MaximumSwathHeightY[k]; + SwathHeightC[k] = MaximumSwathHeightC[k]; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; + } else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC + && RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { + SwathHeightY[k] = MinimumSwathHeightY; + SwathHeightC[k] = MaximumSwathHeightC[k]; + RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY; + RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; + } else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC + && RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { + SwathHeightY[k] = MaximumSwathHeightY[k]; + SwathHeightC[k] = MinimumSwathHeightC; + RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; + RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC; + } else { + SwathHeightY[k] = MinimumSwathHeightY; + SwathHeightC[k] = MinimumSwathHeightC; + RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY; + RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC; + } + { + double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); + if (SwathHeightC[k] == 0) { + DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024; + DETBufferSizeC[k] = 0; + } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { + DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2; + DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2; + } else { + DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3; + } + + if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] + || (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) { + *ViewportSizeSupport = false; + ViewportSizeSupportPerPlane[k] = false; + } else { + ViewportSizeSupportPerPlane[k] = true; + } + } + } +} + +static void CalculateSwathWidth( + bool ForceSingleDPP, + int NumberOfActivePlanes, + enum source_format_class SourcePixelFormat[], + enum scan_direction_class SourceScan[], + int ViewportWidth[], + int ViewportHeight[], + int SurfaceWidthY[], + int SurfaceWidthC[], + int SurfaceHeightY[], + int SurfaceHeightC[], + enum odm_combine_mode ODMCombineEnabled[], + int BytePerPixY[], + int BytePerPixC[], + int Read256BytesBlockHeightY[], + int Read256BytesBlockHeightC[], + int Read256BytesBlockWidthY[], + int Read256BytesBlockWidthC[], + int BlendingAndTiming[], + int HActive[], + double HRatio[], + int DPPPerPlane[], + double SwathWidthSingleDPPY[], + double SwathWidthSingleDPPC[], + double SwathWidthY[], + double SwathWidthC[], + int MaximumSwathHeightY[], + int MaximumSwathHeightC[], + int swath_width_luma_ub[], + int swath_width_chroma_ub[]) +{ + enum odm_combine_mode MainPlaneODMCombine; + int j, k; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: NumberOfActivePlanes = %d\n", __func__, NumberOfActivePlanes); +#endif + + for (k = 0; k < NumberOfActivePlanes; ++k) { + if (SourceScan[k] != dm_vert) { + SwathWidthSingleDPPY[k] = ViewportWidth[k]; + } else { + SwathWidthSingleDPPY[k] = ViewportHeight[k]; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]); + dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]); +#endif + + MainPlaneODMCombine = ODMCombineEnabled[k]; + for (j = 0; j < NumberOfActivePlanes; ++j) { + if (BlendingAndTiming[k] == j) { + MainPlaneODMCombine = ODMCombineEnabled[j]; + } + } + + if (MainPlaneODMCombine == dm_odm_combine_mode_4to1) { + SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k])); + } else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1) { + SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k])); + } else if (DPPPerPlane[k] == 2) { + SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2; + } else { + SwathWidthY[k] = SwathWidthSingleDPPY[k]; + } + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]); + dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]); +#endif + + if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) { + SwathWidthC[k] = SwathWidthY[k] / 2; + SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2; + } else { + SwathWidthC[k] = SwathWidthY[k]; + SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k]; + } + + if (ForceSingleDPP == true) { + SwathWidthY[k] = SwathWidthSingleDPPY[k]; + SwathWidthC[k] = SwathWidthSingleDPPC[k]; + } + { + int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); +#endif + + if (SourceScan[k] != dm_vert) { + MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; + MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; + swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); + if (BytePerPixC[k] > 0) { + swath_width_chroma_ub[k] = dml_min( + surface_width_ub_c, + (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); + } else { + swath_width_chroma_ub[k] = 0; + } + } else { + MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; + MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; + swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + if (BytePerPixC[k] > 0) { + swath_width_chroma_ub[k] = dml_min( + surface_height_ub_c, + (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); + } else { + swath_width_chroma_ub[k] = 0; + } + } + } + } +} + +static double CalculateExtraLatency( + int RoundTripPingLatencyCycles, + int ReorderingBytes, + double DCFCLK, + int TotalNumberOfActiveDPP, + int PixelChunkSizeInKByte, + int TotalNumberOfDCCActiveDPP, + int MetaChunkSize, + double ReturnBW, + bool GPUVMEnable, + bool HostVMEnable, + int NumberOfActivePlanes, + int NumberOfDPP[], + int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels) +{ + double ExtraLatencyBytes; + double ExtraLatency; + + ExtraLatencyBytes = CalculateExtraLatencyBytes( + ReorderingBytes, + TotalNumberOfActiveDPP, + PixelChunkSizeInKByte, + TotalNumberOfDCCActiveDPP, + MetaChunkSize, + GPUVMEnable, + HostVMEnable, + NumberOfActivePlanes, + NumberOfDPP, + dpte_group_bytes, + HostVMInefficiencyFactor, + HostVMMinPageSize, + HostVMMaxNonCachedPageTableLevels); + + ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles); + dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); + dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes); + dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW); + dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency); +#endif + + return ExtraLatency; +} + +static double CalculateExtraLatencyBytes( + int ReorderingBytes, + int TotalNumberOfActiveDPP, + int PixelChunkSizeInKByte, + int TotalNumberOfDCCActiveDPP, + int MetaChunkSize, + bool GPUVMEnable, + bool HostVMEnable, + int NumberOfActivePlanes, + int NumberOfDPP[], + int dpte_group_bytes[], + double HostVMInefficiencyFactor, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels) +{ + double ret; + int HostVMDynamicLevels = 0, k; + + if (GPUVMEnable == true && HostVMEnable == true) { + if (HostVMMinPageSize < 2048) { + HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; + } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + } else { + HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + } + } else { + HostVMDynamicLevels = 0; + } + + ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0; + + if (GPUVMEnable == true) { + for (k = 0; k < NumberOfActivePlanes; ++k) { + ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor; + } + } + return ret; +} + +static double CalculateUrgentLatency( + double UrgentLatencyPixelDataOnly, + double UrgentLatencyPixelMixedWithVMData, + double UrgentLatencyVMDataOnly, + bool DoUrgentLatencyAdjustment, + double UrgentLatencyAdjustmentFabricClockComponent, + double UrgentLatencyAdjustmentFabricClockReference, + double FabricClock) +{ + double ret; + + ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly); + if (DoUrgentLatencyAdjustment == true) { + ret = ret + UrgentLatencyAdjustmentFabricClockComponent * (UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1); + } + return ret; +} + +static void UseMinimumDCFCLK( + struct display_mode_lib *mode_lib, + int MaxInterDCNTileRepeaters, + int MaxPrefetchMode, + double FinalDRAMClockChangeLatency, + double SREnterPlusExitTime, + int ReturnBusWidth, + int RoundTripPingLatencyCycles, + int ReorderingBytes, + int PixelChunkSizeInKByte, + int MetaChunkSize, + bool GPUVMEnable, + int GPUVMMaxPageTableLevels, + bool HostVMEnable, + int NumberOfActivePlanes, + double HostVMMinPageSize, + int HostVMMaxNonCachedPageTableLevels, + bool DynamicMetadataVMEnabled, + enum immediate_flip_requirement ImmediateFlipRequirement, + bool ProgressiveToInterlaceUnitInOPP, + double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, + double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, + int VTotal[], + int VActive[], + int DynamicMetadataTransmittedBytes[], + int DynamicMetadataLinesBeforeActiveRequired[], + bool Interlace[], + double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], + double RequiredDISPCLK[][2], + double UrgLatency[], + unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], + double ProjectedDCFCLKDeepSleep[][2], + double MaximumVStartup[][2][DC__NUM_DPP__MAX], + double TotalVActivePixelBandwidth[][2], + double TotalVActiveCursorBandwidth[][2], + double TotalMetaRowBandwidth[][2], + double TotalDPTERowBandwidth[][2], + unsigned int TotalNumberOfActiveDPP[][2], + unsigned int TotalNumberOfDCCActiveDPP[][2], + int dpte_group_bytes[], + double PrefetchLinesY[][2][DC__NUM_DPP__MAX], + double PrefetchLinesC[][2][DC__NUM_DPP__MAX], + int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], + int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], + int BytePerPixelY[], + int BytePerPixelC[], + int HTotal[], + double PixelClock[], + double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], + double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], + double MetaRowBytes[][2][DC__NUM_DPP__MAX], + bool DynamicMetadataEnable[], + double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], + double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], + double ReadBandwidthLuma[], + double ReadBandwidthChroma[], + double DCFCLKPerState[], + double DCFCLKState[][2]) +{ + struct vba_vars_st *v = &mode_lib->vba; + int dummy1, i, j, k; + double NormalEfficiency, dummy2, dummy3; + double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; + + NormalEfficiency = PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; + for (i = 0; i < v->soc.num_states; ++i) { + for (j = 0; j <= 1; ++j) { + double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; + double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; + double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX]; + double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; + double MinimumTWait; + double NonDPTEBandwidth; + double DPTEBandwidth; + double DCFCLKRequiredForAverageBandwidth; + double ExtraLatencyBytes; + double ExtraLatencyCycles; + double DCFCLKRequiredForPeakBandwidth; + int NoOfDPPState[DC__NUM_DPP__MAX]; + double MinimumTvmPlus2Tr0; + + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; + for (k = 0; k < NumberOfActivePlanes; ++k) { + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j] + + NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]); + } + + for (k = 0; k <= NumberOfActivePlanes - 1; ++k) { + NoOfDPPState[k] = NoOfDPP[i][j][k]; + } + + MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime); + NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j]; + DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ? + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j]; + DCFCLKRequiredForAverageBandwidth = dml_max3( + ProjectedDCFCLKDeepSleep[i][j], + (NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth + / (MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100), + (NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / ReturnBusWidth); + + ExtraLatencyBytes = CalculateExtraLatencyBytes( + ReorderingBytes, + TotalNumberOfActiveDPP[i][j], + PixelChunkSizeInKByte, + TotalNumberOfDCCActiveDPP[i][j], + MetaChunkSize, + GPUVMEnable, + HostVMEnable, + NumberOfActivePlanes, + NoOfDPPState, + dpte_group_bytes, + 1, + HostVMMinPageSize, + HostVMMaxNonCachedPageTableLevels); + ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth; + for (k = 0; k < NumberOfActivePlanes; ++k) { + double DCFCLKCyclesRequiredInPrefetch; + double ExpectedPrefetchBWAcceleration; + double PrefetchTime; + + PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k] + + PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth; + DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + + PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0) + + 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth + + 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k]; + PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k]; + ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k]) + / (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]); + DynamicMetadataVMExtraLatency[k] = + (GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ? + UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; + PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait + - UrgLatency[i] + * ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels : GPUVMMaxPageTableLevels - 2) + * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) + - DynamicMetadataVMExtraLatency[k]; + + if (PrefetchTime > 0) { + double ExpectedVRatioPrefetch; + ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] + / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch); + DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k] + * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration; + if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) { + DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k] + + NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / ReturnBusWidth; + } + } else { + DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i]; + } + if (DynamicMetadataEnable[k] == true) { + double TSetupPipe; + double TdmbfPipe; + double TdmsksPipe; + double TdmecPipe; + double AllowedTimeForUrgentExtraLatency; + + CalculateVupdateAndDynamicMetadataParameters( + MaxInterDCNTileRepeaters, + RequiredDPPCLK[i][j][k], + RequiredDISPCLK[i][j], + ProjectedDCFCLKDeepSleep[i][j], + PixelClock[k], + HTotal[k], + VTotal[k] - VActive[k], + DynamicMetadataTransmittedBytes[k], + DynamicMetadataLinesBeforeActiveRequired[k], + Interlace[k], + ProgressiveToInterlaceUnitInOPP, + &TSetupPipe, + &TdmbfPipe, + &TdmecPipe, + &TdmsksPipe, + &dummy1, + &dummy2, + &dummy3); + AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe + - TdmsksPipe - DynamicMetadataVMExtraLatency[k]; + if (AllowedTimeForUrgentExtraLatency > 0) { + DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max( + DCFCLKRequiredForPeakBandwidthPerPlane[k], + ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency); + } else { + DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i]; + } + } + } + DCFCLKRequiredForPeakBandwidth = 0; + for (k = 0; k <= NumberOfActivePlanes - 1; ++k) { + DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; + } + MinimumTvmPlus2Tr0 = UrgLatency[i] + * (GPUVMEnable == true ? + (HostVMEnable == true ? + (GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : + 0); + for (k = 0; k < NumberOfActivePlanes; ++k) { + double MaximumTvmPlus2Tr0PlusTsw; + MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; + if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) { + DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i]; + } else { + DCFCLKRequiredForPeakBandwidth = dml_max3( + DCFCLKRequiredForPeakBandwidth, + 2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4), + (2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0)); + } + } + DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth)); + } + } +} + +static void CalculateUnboundedRequestAndCompressedBufferSize( + unsigned int DETBufferSizeInKByte, + int ConfigReturnBufferSizeInKByte, + enum unbounded_requesting_policy UseUnboundedRequestingFinal, + int TotalActiveDPP, + bool NoChromaPlanes, + int MaxNumDPP, + int CompressedBufferSegmentSizeInkByteFinal, + enum output_encoder_class *Output, + bool *UnboundedRequestEnabled, + int *CompressedBufferSizeInkByte) +{ + double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); + + *UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]); + *CompressedBufferSizeInkByte = ( + *UnboundedRequestEnabled == true ? + ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte : + ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte); + *CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64; + +#ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP); + dml_print("DML::%s: DETBufferSizeInKByte = %d\n", __func__, DETBufferSizeInKByte); + dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte); + dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal); + dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte); + dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled); + dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte); +#endif +} + +static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output) +{ + bool ret_val = false; + + ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable && TotalNumberOfActiveDPP == 1 && NoChroma); + if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp) { + ret_val = false; + } + return (ret_val); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h new file mode 100644 index 000000000000..90be612f26b2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h @@ -0,0 +1,43 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DML31_DISPLAY_MODE_VBA_H__ +#define __DML31_DISPLAY_MODE_VBA_H__ + +void dml31_recalculate(struct display_mode_lib *mode_lib); +void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); +double dml31_CalculateWriteBackDISPCLK( + enum source_format_class WritebackPixelFormat, + double PixelClock, + double WritebackHRatio, + double WritebackVRatio, + unsigned int WritebackHTaps, + unsigned int WritebackVTaps, + long WritebackSourceWidth, + long WritebackDestinationWidth, + unsigned int HTotal, + unsigned int WritebackLineBufferSize); + +#endif /* __DML31_DISPLAY_MODE_VBA_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c new file mode 100644 index 000000000000..3def093ef88e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -0,0 +1,1724 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "../display_mode_lib.h" +#include "../display_mode_vba.h" +#include "../dml_inline_defs.h" +#include "display_rq_dlg_calc_31.h" + +static bool CalculateBytePerPixelAnd256BBlockSizes( + enum source_format_class SourcePixelFormat, + enum dm_swizzle_mode SurfaceTiling, + unsigned int *BytePerPixelY, + unsigned int *BytePerPixelC, + double *BytePerPixelDETY, + double *BytePerPixelDETC, + unsigned int *BlockHeight256BytesY, + unsigned int *BlockHeight256BytesC, + unsigned int *BlockWidth256BytesY, + unsigned int *BlockWidth256BytesC) +{ + if (SourcePixelFormat == dm_444_64) { + *BytePerPixelDETY = 8; + *BytePerPixelDETC = 0; + *BytePerPixelY = 8; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 0; + *BytePerPixelY = 4; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_16) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 0; + *BytePerPixelY = 2; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_444_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 0; + *BytePerPixelY = 1; + *BytePerPixelC = 0; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BytePerPixelDETY = 4; + *BytePerPixelDETC = 1; + *BytePerPixelY = 4; + *BytePerPixelC = 1; + } else if (SourcePixelFormat == dm_420_8) { + *BytePerPixelDETY = 1; + *BytePerPixelDETC = 2; + *BytePerPixelY = 1; + *BytePerPixelC = 2; + } else if (SourcePixelFormat == dm_420_12) { + *BytePerPixelDETY = 2; + *BytePerPixelDETC = 4; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } else { + *BytePerPixelDETY = 4.0 / 3; + *BytePerPixelDETC = 8.0 / 3; + *BytePerPixelY = 2; + *BytePerPixelC = 4; + } + + if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16 + || SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) { + if (SurfaceTiling == dm_sw_linear) { + *BlockHeight256BytesY = 1; + } else if (SourcePixelFormat == dm_444_64) { + *BlockHeight256BytesY = 4; + } else if (SourcePixelFormat == dm_444_8) { + *BlockHeight256BytesY = 16; + } else { + *BlockHeight256BytesY = 8; + } + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockHeight256BytesC = 0; + *BlockWidth256BytesC = 0; + } else { + if (SurfaceTiling == dm_sw_linear) { + *BlockHeight256BytesY = 1; + *BlockHeight256BytesC = 1; + } else if (SourcePixelFormat == dm_rgbe_alpha) { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 16; + } else if (SourcePixelFormat == dm_420_8) { + *BlockHeight256BytesY = 16; + *BlockHeight256BytesC = 8; + } else { + *BlockHeight256BytesY = 8; + *BlockHeight256BytesC = 8; + } + *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; + *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC; + } + return true; +} + +static bool is_dual_plane(enum source_format_class source_format) +{ + bool ret_val = 0; + + if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha)) + ret_val = 1; + + return ret_val; +} + +static double get_refcyc_per_delivery( + struct display_mode_lib *mode_lib, + double refclk_freq_in_mhz, + double pclk_freq_in_mhz, + unsigned int odm_combine, + unsigned int recout_width, + unsigned int hactive, + double vratio, + double hscale_pixel_rate, + unsigned int delivery_width, + unsigned int req_per_swath_ub) +{ + double refcyc_per_delivery = 0.0; + + if (vratio <= 1.0) { + if (odm_combine) + refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2) + * dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub; + else + refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub; + } else { + refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub; + } + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); + dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); + dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); + dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); + dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); + dml_print("DML_DLG: %s: hscale_pixel_rate = %3.2f\n", __func__, hscale_pixel_rate); + dml_print("DML_DLG: %s: delivery_width = %d\n", __func__, delivery_width); + dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); +#endif + + return refcyc_per_delivery; + +} + +static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) +{ + if (tile_size == dm_256k_tile) + return (256 * 1024); + else if (tile_size == dm_64k_tile) + return (64 * 1024); + else + return (4 * 1024); +} + +static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st rq_sizing) +{ + print__data_rq_sizing_params_st(mode_lib, rq_sizing); + + rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; + + if (rq_sizing.min_chunk_bytes == 0) + rq_regs->min_chunk_size = 0; + else + rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; + + rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; + if (rq_sizing.min_meta_chunk_bytes == 0) + rq_regs->min_meta_chunk_size = 0; + else + rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; + + rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; + rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; +} + +static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st rq_param) +{ + unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; + unsigned int detile_buf_plane1_addr = 0; + + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); + + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 1) - 3; + + if (rq_param.yuv420) { + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 1) - 3; + } + + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); + + // FIXME: take the max between luma, chroma chunk size? + // okay for now, as we are setting chunk_bytes to 8kb anyways + if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb + rq_regs->drq_expansion_mode = 0; + } else { + rq_regs->drq_expansion_mode = 2; + } + rq_regs->prq_expansion_mode = 1; + rq_regs->mrq_expansion_mode = 1; + rq_regs->crq_expansion_mode = 1; + + // Note: detile_buf_plane1_addr is in unit of 1KB + if (rq_param.yuv420) { + if ((double) rq_param.misc.rq_l.stored_swath_bytes / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { + detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); +#endif + } else { + detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); +#endif + } + } + rq_regs->plane1_base_address = detile_buf_plane1_addr; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes); + dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr); + dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address); + dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_l.stored_swath_bytes); + dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_c.stored_swath_bytes); + dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param.dlg.rq_l.swath_height); + dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param.dlg.rq_c.swath_height); +#endif +} + +static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st pipe_src_param) +{ + unsigned int total_swath_bytes = 0; + unsigned int swath_bytes_l = 0; + unsigned int swath_bytes_c = 0; + unsigned int full_swath_bytes_packed_l = 0; + unsigned int full_swath_bytes_packed_c = 0; + bool req128_l = 0; + bool req128_c = 0; + bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); + bool surf_vert = (pipe_src_param.source_scan == dm_vert); + unsigned int log2_swath_height_l = 0; + unsigned int log2_swath_height_c = 0; + unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; + + full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; + full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l); + dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c); +#endif + + if (rq_param->yuv420_10bpc) { + full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; + full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); + dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); +#endif + } + + if (rq_param->yuv420) + total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; + else + total_swath_bytes = 2 * full_swath_bytes_packed_l; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes); + dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes); +#endif + + if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request + req128_l = 0; + req128_c = 0; + swath_bytes_l = full_swath_bytes_packed_l; + swath_bytes_c = full_swath_bytes_packed_c; + } else if (!rq_param->yuv420) { + req128_l = 1; + req128_c = 0; + swath_bytes_c = full_swath_bytes_packed_c; + swath_bytes_l = full_swath_bytes_packed_l / 2; + } else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) { + req128_l = 0; + req128_c = 1; + swath_bytes_l = full_swath_bytes_packed_l; + swath_bytes_c = full_swath_bytes_packed_c / 2; + + total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; + + if (total_swath_bytes > detile_buf_size_in_bytes) { + req128_l = 1; + swath_bytes_l = full_swath_bytes_packed_l / 2; + } + } else { + req128_l = 1; + req128_c = 0; + swath_bytes_l = full_swath_bytes_packed_l / 2; + swath_bytes_c = full_swath_bytes_packed_c; + + total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; + + if (total_swath_bytes > detile_buf_size_in_bytes) { + req128_c = 1; + swath_bytes_c = full_swath_bytes_packed_c / 2; + } + } + + if (rq_param->yuv420) + total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; + else + total_swath_bytes = 2 * swath_bytes_l; + + rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; + rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes); + dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes); + dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes); +#endif + if (surf_linear) { + log2_swath_height_l = 0; + log2_swath_height_c = 0; + } else { + unsigned int swath_height_l; + unsigned int swath_height_c; + + if (!surf_vert) { + swath_height_l = rq_param->misc.rq_l.blk256_height; + swath_height_c = rq_param->misc.rq_c.blk256_height; + } else { + swath_height_l = rq_param->misc.rq_l.blk256_width; + swath_height_c = rq_param->misc.rq_c.blk256_width; + } + + if (swath_height_l > 0) + log2_swath_height_l = dml_log2(swath_height_l); + + if (req128_l && log2_swath_height_l > 0) + log2_swath_height_l -= 1; + + if (swath_height_c > 0) + log2_swath_height_c = dml_log2(swath_height_c); + + if (req128_c && log2_swath_height_c > 0) + log2_swath_height_c -= 1; + } + + rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; + rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; + +#ifdef __DML_RQ_DLG_CALC_DEBUG__ + dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); + dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); + dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l); + dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c); + dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height); + dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height); +#endif +} + +static void get_meta_and_pte_attr( + struct display_mode_lib *mode_lib, + display_data_rq_dlg_params_st *rq_dlg_param, + display_data_rq_misc_params_st *rq_misc_param, + display_data_rq_sizing_params_st *rq_sizing_param, + unsigned int vp_width, + unsigned int vp_height, + unsigned int data_pitch, + unsigned int meta_pitch, + unsigned int source_format, + unsigned int tiling, + unsigned int macro_tile_size, + unsigned int source_scan, + unsigned int hostvm_enable, + unsigned int is_chroma, + unsigned int surface_height) +{ + bool surf_linear = (tiling == dm_sw_linear); + bool surf_vert = (source_scan == dm_vert); + + unsigned int bytes_per_element; + unsigned int bytes_per_element_y; + unsigned int bytes_per_element_c; + + unsigned int blk256_width = 0; + unsigned int blk256_height = 0; + + unsigned int blk256_width_y = 0; + unsigned int blk256_height_y = 0; + unsigned int blk256_width_c = 0; + unsigned int blk256_height_c = 0; + unsigned int log2_bytes_per_element; + unsigned int log2_blk256_width; + unsigned int log2_blk256_height; + unsigned int blk_bytes; + unsigned int log2_blk_bytes; + unsigned int log2_blk_height; + unsigned int log2_blk_width; + unsigned int log2_meta_req_bytes; + unsigned int log2_meta_req_height; + unsigned int log2_meta_req_width; + unsigned int meta_req_width; + unsigned int meta_req_height; + unsigned int log2_meta_row_height; + unsigned int meta_row_width_ub; + unsigned int log2_meta_chunk_bytes; + unsigned int log2_meta_chunk_height; + + //full sized meta chunk width in unit of data elements + unsigned int log2_meta_chunk_width; + unsigned int log2_min_meta_chunk_bytes; + unsigned int min_meta_chunk_width; + unsigned int meta_chunk_width; + unsigned int meta_chunk_per_row_int; + unsigned int meta_row_remainder; + unsigned int meta_chunk_threshold; + unsigned int meta_blk_height; + unsigned int meta_surface_bytes; + unsigned int vmpg_bytes; + unsigned int meta_pte_req_per_frame_ub; + unsigned int meta_pte_bytes_per_frame_ub; + const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes); + const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format)); + const unsigned int dpte_buf_in_pte_reqs = + dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma); + + unsigned int log2_vmpg_height = 0; + unsigned int log2_vmpg_width = 0; + unsigned int log2_dpte_req_height_ptes = 0; + unsigned int log2_dpte_req_height = 0; + unsigned int log2_dpte_req_width = 0; + unsigned int log2_dpte_row_height_linear = 0; + unsigned int log2_dpte_row_height = 0; + unsigned int log2_dpte_group_width = 0; + unsigned int dpte_row_width_ub = 0; + unsigned int dpte_req_height = 0; + unsigned int dpte_req_width = 0; + unsigned int dpte_group_width = 0; + unsigned int log2_dpte_group_bytes = 0; + unsigned int log2_dpte_group_length = 0; + double byte_per_pixel_det_y; + double byte_per_pixel_det_c; + + CalculateBytePerPixelAnd256BBlockSizes( + (enum source_format_class) (source_format), + (enum dm_swizzle_mode) (tiling), + &bytes_per_element_y, + &bytes_per_element_c, + &byte_per_pixel_det_y, + &byte_per_pixel_det_c, + &blk256_height_y, + &blk256_height_c, + &blk256_width_y, + &blk256_width_c); + + if (!is_chroma) { + blk256_width = blk256_width_y; + blk256_height = blk256_height_y; + bytes_per_element = bytes_per_element_y; + } else { + blk256_width = blk256_width_c; + blk256_height = blk256_height_c; + bytes_per_element = bytes_per_element_c; + } + + log2_bytes_per_element = dml_log2(bytes_per_element); + + dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); + dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); + dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); + dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); + + log2_blk256_width = dml_log2((double) blk256_width); + log2_blk256_height = dml_log2((double) blk256_height); + blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); + log2_blk_bytes = dml_log2((double) blk_bytes); + log2_blk_height = 0; + log2_blk_width = 0; + + // remember log rule + // "+" in log is multiply + // "-" in log is divide + // "/2" is like square root + // blk is vertical biased + if (tiling != dm_sw_linear) + log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + else + log2_blk_height = 0; // blk height of 1 + + log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; + + if (!surf_vert) { + int unsigned temp; + + temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width; + if (data_pitch < blk256_width) { + dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width); + } else { + if (temp > data_pitch) { + if (data_pitch >= vp_width) + temp = data_pitch; + else + dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width); + } + } + rq_dlg_param->swath_width_ub = temp; + rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width; + } else { + int unsigned temp; + + temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height; + if (surface_height < blk256_height) { + dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height); + } else { + if (temp > surface_height) { + if (surface_height >= vp_height) + temp = surface_height; + else + dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height); + } + } + rq_dlg_param->swath_width_ub = temp; + rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height; + } + + if (!surf_vert) + rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element; + else + rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element; + + rq_misc_param->blk256_height = blk256_height; + rq_misc_param->blk256_width = blk256_width; + + // ------- + // meta + // ------- + log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element + + // each 64b meta request for dcn is 8x8 meta elements and + // a meta element covers one 256b block of the the data surface. + log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 + log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height; + meta_req_width = 1 << log2_meta_req_width; + meta_req_height = 1 << log2_meta_req_height; + log2_meta_row_height = 0; + meta_row_width_ub = 0; + + // the dimensions of a meta row are meta_row_width x meta_row_height in elements. + // calculate upper bound of the meta_row_width + if (!surf_vert) { + log2_meta_row_height = log2_meta_req_height; + meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; + rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; + } else { + log2_meta_row_height = log2_meta_req_width; + meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; + rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; + } + rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; + + rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; + + log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); + log2_meta_chunk_height = log2_meta_row_height; + + //full sized meta chunk width in unit of data elements + log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height; + log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); + min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height); + meta_chunk_width = 1 << log2_meta_chunk_width; + meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); + meta_row_remainder = meta_row_width_ub % meta_chunk_width; + meta_chunk_threshold = 0; + meta_blk_height = blk256_height * 64; + meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256; + vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes; + meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); + meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request + rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; + + dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); + dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); + dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", __func__, meta_pte_req_per_frame_ub); + dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub); + + if (!surf_vert) + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; + else + meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; + + if (meta_row_remainder <= meta_chunk_threshold) + rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; + else + rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; + + // ------ + // dpte + // ------ + if (surf_linear) { + log2_vmpg_height = 0; // one line high + } else { + log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; + } + log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; + + // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. + if (surf_linear) { //one 64B PTE request returns 8 PTEs + log2_dpte_req_height_ptes = 0; + log2_dpte_req_width = log2_vmpg_width + 3; + log2_dpte_req_height = 0; + } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size + //one 64B req gives 8x1 PTEs for 4KB tile + log2_dpte_req_height_ptes = 0; + log2_dpte_req_width = log2_blk_width + 3; + log2_dpte_req_height = log2_blk_height + 0; + } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB + //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB + log2_dpte_req_height_ptes = 4; + log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width + log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height + } else { //64KB page size and must 64KB tile block + //one 64B req gives 8x1 PTEs for 64KB tile + log2_dpte_req_height_ptes = 0; + log2_dpte_req_width = log2_blk_width + 3; + log2_dpte_req_height = log2_blk_height + 0; + } + + // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height + // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent + // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) + //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; + //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; + dpte_req_height = 1 << log2_dpte_req_height; + dpte_req_width = 1 << log2_dpte_req_width; + + // calculate pitch dpte row buffer can hold + // round the result down to a power of two. + if (surf_linear) { + unsigned int dpte_row_height; + + log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + + dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); + dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); + dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear); + + ASSERT(log2_dpte_row_height_linear >= 3); + + if (log2_dpte_row_height_linear > 7) + log2_dpte_row_height_linear = 7; + + log2_dpte_row_height = log2_dpte_row_height_linear; + // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. + // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. + dpte_row_height = 1 << log2_dpte_row_height; + dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width; + rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; + } else { + // the upper bound of the dpte_row_width without dependency on viewport position follows. + // for tiled mode, row height is the same as req height and row store up to vp size upper bound + if (!surf_vert) { + log2_dpte_row_height = log2_dpte_req_height; + dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width; + rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; + } else { + log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width; + dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height; + rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; + } + } + if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB + rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request + else + rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request + + rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; + + // the dpte_group_bytes is reduced for the specific case of vertical + // access of a tile surface that has dpte request of 8x1 ptes. + if (hostvm_enable) + rq_sizing_param->dpte_group_bytes = 512; + else { + if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + rq_sizing_param->dpte_group_bytes = 512; + else + rq_sizing_param->dpte_group_bytes = 2048; + } + + //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. + log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); + log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests + + // full sized data pte group width in elements + if (!surf_vert) + log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; + else + log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; + + //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B + if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB + log2_dpte_group_width = log2_dpte_group_width - 1; + + dpte_group_width = 1 << log2_dpte_group_width; + + // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, + // the upper bound for the dpte groups per row is as follows. + rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); +} + +static void get_surf_rq_param( + struct display_mode_lib *mode_lib, + display_data_rq_sizing_params_st *rq_sizing_param, + display_data_rq_dlg_params_st *rq_dlg_param, + display_data_rq_misc_params_st *rq_misc_param, + const display_pipe_params_st pipe_param, + bool is_chroma, + bool is_alpha) +{ + bool mode_422 = 0; + unsigned int vp_width = 0; + unsigned int vp_height = 0; + unsigned int data_pitch = 0; + unsigned int meta_pitch = 0; + unsigned int surface_height = 0; + unsigned int ppe = mode_422 ? 2 : 1; + + // FIXME check if ppe apply for both luma and chroma in 422 case + if (is_chroma | is_alpha) { + vp_width = pipe_param.src.viewport_width_c / ppe; + vp_height = pipe_param.src.viewport_height_c; + data_pitch = pipe_param.src.data_pitch_c; + meta_pitch = pipe_param.src.meta_pitch_c; + surface_height = pipe_param.src.surface_height_y / 2.0; + } else { + vp_width = pipe_param.src.viewport_width / ppe; + vp_height = pipe_param.src.viewport_height; + data_pitch = pipe_param.src.data_pitch; + meta_pitch = pipe_param.src.meta_pitch; + surface_height = pipe_param.src.surface_height_y; + } + + if (pipe_param.dest.odm_combine) { + unsigned int access_dir; + unsigned int full_src_vp_width; + unsigned int hactive_odm; + unsigned int src_hactive_odm; + + access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed + hactive_odm = pipe_param.dest.hactive / ((unsigned int) pipe_param.dest.odm_combine * 2); + if (is_chroma) { + full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width; + src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm; + } else { + full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width; + src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm; + } + + if (access_dir == 0) { + vp_width = dml_min(full_src_vp_width, src_hactive_odm); + dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); + } else { + vp_height = dml_min(full_src_vp_width, src_hactive_odm); + dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); + + } + dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); + dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm); + dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm); + } + + rq_sizing_param->chunk_bytes = 8192; + + if (is_alpha) { + rq_sizing_param->chunk_bytes = 4096; + } + + if (rq_sizing_param->chunk_bytes == 64 * 1024) + rq_sizing_param->min_chunk_bytes = 0; + else + rq_sizing_param->min_chunk_bytes = 1024; + + rq_sizing_param->meta_chunk_bytes = 2048; + rq_sizing_param->min_meta_chunk_bytes = 256; + + if (pipe_param.src.hostvm) + rq_sizing_param->mpte_group_bytes = 512; + else + rq_sizing_param->mpte_group_bytes = 2048; + + get_meta_and_pte_attr( + mode_lib, + rq_dlg_param, + rq_misc_param, + rq_sizing_param, + vp_width, + vp_height, + data_pitch, + meta_pitch, + pipe_param.src.source_format, + pipe_param.src.sw_mode, + pipe_param.src.macro_tile_size, + pipe_param.src.source_scan, + pipe_param.src.hostvm, + is_chroma, + surface_height); +} + +static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st pipe_param) +{ + // get param for luma surface + rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 || pipe_param.src.source_format == dm_420_10 || pipe_param.src.source_format == dm_rgbe_alpha + || pipe_param.src.source_format == dm_420_12; + + rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10; + + rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha) ? 1 : 0; + + get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0); + + if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) { + // get param for chroma surface + get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha); + } + + // calculate how to split the det buffer space between luma and chroma + handle_det_buf_split(mode_lib, rq_param, pipe_param.src); + print__rq_params_st(mode_lib, *rq_param); +} + +void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st pipe_param) +{ + display_rq_params_st rq_param = {0}; + + memset(rq_regs, 0, sizeof(*rq_regs)); + dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); + extract_rq_regs(mode_lib, rq_regs, rq_param); + + print__rq_regs_st(mode_lib, *rq_regs); +} + +static void calculate_ttu_cursor( + struct display_mode_lib *mode_lib, + double *refcyc_per_req_delivery_pre_cur, + double *refcyc_per_req_delivery_cur, + double refclk_freq_in_mhz, + double ref_freq_to_pix_freq, + double hscale_pixel_rate_l, + double hscl_ratio, + double vratio_pre_l, + double vratio_l, + unsigned int cur_width, + enum cursor_bpp cur_bpp) +{ + unsigned int cur_src_width = cur_width; + unsigned int cur_req_size = 0; + unsigned int cur_req_width = 0; + double cur_width_ub = 0.0; + double cur_req_per_width = 0.0; + double hactive_cur = 0.0; + + ASSERT(cur_src_width <= 256); + + *refcyc_per_req_delivery_pre_cur = 0.0; + *refcyc_per_req_delivery_cur = 0.0; + if (cur_src_width > 0) { + unsigned int cur_bit_per_pixel = 0; + + if (cur_bpp == dm_cur_2bit) { + cur_req_size = 64; // byte + cur_bit_per_pixel = 2; + } else { // 32bit + cur_bit_per_pixel = 32; + if (cur_src_width >= 1 && cur_src_width <= 16) + cur_req_size = 64; + else if (cur_src_width >= 17 && cur_src_width <= 31) + cur_req_size = 128; + else + cur_req_size = 256; + } + + cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; + cur_req_per_width = cur_width_ub / (double) cur_req_width; + hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor + + if (vratio_pre_l <= 1.0) { + *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; + } else { + *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width; + } + + ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); + + if (vratio_l <= 1.0) { + *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; + } else { + *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width; + } + + dml_print("DML_DLG: %s: cur_req_width = %d\n", __func__, cur_req_width); + dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", __func__, cur_width_ub); + dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", __func__, cur_req_per_width); + dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", __func__, hactive_cur); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_cur); + + ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); + } +} + +// Note: currently taken in as is. +// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. +static void dml_rq_dlg_get_dlg_params( + struct display_mode_lib *mode_lib, + const display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx, + display_dlg_regs_st *disp_dlg_regs, + display_ttu_regs_st *disp_ttu_regs, + const display_rq_dlg_params_st rq_dlg_param, + const display_dlg_sys_params_st dlg_sys_param, + const bool cstate_en, + const bool pstate_en, + const bool vm_en, + const bool ignore_viewport_pos, + const bool immediate_flip_support) +{ + const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; + const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; + const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; + const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; + const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; + const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; + unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX]; + + // ------------------------- + // Section 1.15.2.1: OTG dependent Params + // ------------------------- + // Timing + unsigned int htotal = dst->htotal; + unsigned int hblank_end = dst->hblank_end; + unsigned int vblank_start = dst->vblank_start; + unsigned int vblank_end = dst->vblank_end; + + double dppclk_freq_in_mhz = clks->dppclk_mhz; + double refclk_freq_in_mhz = clks->refclk_mhz; + double pclk_freq_in_mhz = dst->pixel_rate_mhz; + bool interlaced = dst->interlaced; + double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; + double min_ttu_vblank; + unsigned int dlg_vblank_start; + bool dual_plane; + bool mode_422; + unsigned int access_dir; + unsigned int vp_height_l; + unsigned int vp_width_l; + unsigned int vp_height_c; + unsigned int vp_width_c; + + // Scaling + unsigned int htaps_l; + unsigned int htaps_c; + double hratio_l; + double hratio_c; + double vratio_l; + double vratio_c; + bool scl_enable; + + unsigned int swath_width_ub_l; + unsigned int dpte_groups_per_row_ub_l; + unsigned int swath_width_ub_c; + unsigned int dpte_groups_per_row_ub_c; + + unsigned int meta_chunks_per_row_ub_l; + unsigned int meta_chunks_per_row_ub_c; + unsigned int vupdate_offset; + unsigned int vupdate_width; + unsigned int vready_offset; + + unsigned int dppclk_delay_subtotal; + unsigned int dispclk_delay_subtotal; + + unsigned int vstartup_start; + unsigned int dst_x_after_scaler; + unsigned int dst_y_after_scaler; + double dst_y_prefetch; + double dst_y_per_vm_vblank; + double dst_y_per_row_vblank; + double dst_y_per_vm_flip; + double dst_y_per_row_flip; + double max_dst_y_per_vm_vblank; + double max_dst_y_per_row_vblank; + double vratio_pre_l; + double vratio_pre_c; + unsigned int req_per_swath_ub_l; + unsigned int req_per_swath_ub_c; + unsigned int meta_row_height_l; + unsigned int meta_row_height_c; + unsigned int swath_width_pixels_ub_l; + unsigned int swath_width_pixels_ub_c; + unsigned int scaler_rec_in_width_l; + unsigned int scaler_rec_in_width_c; + unsigned int dpte_row_height_l; + unsigned int dpte_row_height_c; + double hscale_pixel_rate_l; + double hscale_pixel_rate_c; + double min_hratio_fact_l; + double min_hratio_fact_c; + double refcyc_per_line_delivery_pre_l; + double refcyc_per_line_delivery_pre_c; + double refcyc_per_line_delivery_l; + double refcyc_per_line_delivery_c; + + double refcyc_per_req_delivery_pre_l; + double refcyc_per_req_delivery_pre_c; + double refcyc_per_req_delivery_l; + double refcyc_per_req_delivery_c; + + unsigned int full_recout_width; + double refcyc_per_req_delivery_pre_cur0; + double refcyc_per_req_delivery_cur0; + double refcyc_per_req_delivery_pre_cur1; + double refcyc_per_req_delivery_cur1; + int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA + int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); + memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); + + dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); + dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); + dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en); + dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos); + dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support); + + dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); + dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); + dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); + dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0); + + disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); + disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); + disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits + + //set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support); + min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; + + disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); + ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); + + dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); + dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start); + dml_print("DML_DLG: %s: dlg_vblank_start = 0x%0x\n", __func__, dlg_vblank_start); + dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); + dml_print("DML_DLG: %s: vba__min_dst_y_next_start = 0x%0x\n", __func__, vba__min_dst_y_next_start); + + //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start); + + // ------------------------- + // Section 1.15.2.2: Prefetch, Active and TTU + // ------------------------- + // Prefetch Calc + // Source + dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); + mode_422 = 0; + access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed + vp_height_l = src->viewport_height; + vp_width_l = src->viewport_width; + vp_height_c = src->viewport_height_c; + vp_width_c = src->viewport_width_c; + + // Scaling + htaps_l = taps->htaps; + htaps_c = taps->htaps_c; + hratio_l = scl->hscl_ratio; + hratio_c = scl->hscl_ratio_c; + vratio_l = scl->vscl_ratio; + vratio_c = scl->vscl_ratio_c; + scl_enable = scl->scl_enable; + + swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; + dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; + swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; + dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; + + meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; + meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; + vupdate_offset = dst->vupdate_offset; + vupdate_width = dst->vupdate_width; + vready_offset = dst->vready_offset; + + dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; + dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; + + if (scl_enable) + dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; + else + dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; + + dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; + + if (dout->dsc_enable) { + double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA + dispclk_delay_subtotal += dsc_delay; + } + + vstartup_start = dst->vstartup_start; + if (interlaced) { + if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) + disp_dlg_regs->vready_after_vcount0 = 1; + else + disp_dlg_regs->vready_after_vcount0 = 0; + } else { + if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) + disp_dlg_regs->vready_after_vcount0 = 1; + else + disp_dlg_regs->vready_after_vcount0 = 0; + } + + dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0); + dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0); + //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0); + + if (interlaced) + vstartup_start = vstartup_start / 2; + + dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + // do some adjustment on the dst_after scaler to account for odm combine mode + dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); + dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler); + + // need to figure out which side of odm combine we're in + if (dst->odm_combine) { + // figure out which pipes go together + bool visited[DC__NUM_PIPES__MAX]; + unsigned int i, j, k; + + for (k = 0; k < num_pipes; ++k) { + visited[k] = false; + pipe_index_in_combine[k] = 0; + } + + for (i = 0; i < num_pipes; i++) { + if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { + + unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; + unsigned int grp_idx = 0; + + for (j = i; j < num_pipes; j++) { + if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { + pipe_index_in_combine[j] = grp_idx; + dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx); + grp_idx++; + visited[j] = true; + } + } + } + } + + } + + if (dst->odm_combine == dm_odm_combine_mode_disabled) { + disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); + } else { + unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 + unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; + disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); + } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); + + dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); + dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_x_after_scaler); + dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler); + + dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + max_dst_y_per_vm_vblank = 32.0; //U5.2 + max_dst_y_per_row_vblank = 16.0; //U4.2 + + // magic! + if (htotal <= 75) { + max_dst_y_per_vm_vblank = 100.0; + max_dst_y_per_row_vblank = 100.0; + } + + dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); + dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); + dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); + dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); + dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); + + ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); + + ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); + + vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l); + dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); + + // Active + req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; + req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; + meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; + meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; + swath_width_pixels_ub_l = 0; + swath_width_pixels_ub_c = 0; + scaler_rec_in_width_l = 0; + scaler_rec_in_width_c = 0; + dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; + dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; + + if (mode_422) { + swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element + swath_width_pixels_ub_c = swath_width_ub_c * 2; + } else { + swath_width_pixels_ub_l = swath_width_ub_l * 1; + swath_width_pixels_ub_c = swath_width_ub_c * 1; + } + + hscale_pixel_rate_l = 0.; + hscale_pixel_rate_c = 0.; + min_hratio_fact_l = 1.0; + min_hratio_fact_c = 1.0; + + if (hratio_l <= 1) + min_hratio_fact_l = 2.0; + else if (htaps_l <= 6) { + if ((hratio_l * 2.0) > 4.0) + min_hratio_fact_l = 4.0; + else + min_hratio_fact_l = hratio_l * 2.0; + } else { + if (hratio_l > 4.0) + min_hratio_fact_l = 4.0; + else + min_hratio_fact_l = hratio_l; + } + + hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; + + dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l); + dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l); + dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l); + + if (hratio_c <= 1) + min_hratio_fact_c = 2.0; + else if (htaps_c <= 6) { + if ((hratio_c * 2.0) > 4.0) + min_hratio_fact_c = 4.0; + else + min_hratio_fact_c = hratio_c * 2.0; + } else { + if (hratio_c > 4.0) + min_hratio_fact_c = 4.0; + else + min_hratio_fact_c = hratio_c; + } + + hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; + + refcyc_per_line_delivery_pre_l = 0.; + refcyc_per_line_delivery_pre_c = 0.; + refcyc_per_line_delivery_l = 0.; + refcyc_per_line_delivery_c = 0.; + + refcyc_per_req_delivery_pre_l = 0.; + refcyc_per_req_delivery_pre_c = 0.; + refcyc_per_req_delivery_l = 0.; + refcyc_per_req_delivery_c = 0.; + + full_recout_width = 0; + // In ODM + if (src->is_hsplit) { + // This "hack" is only allowed (and valid) for MPC combine. In ODM + // combine, you MUST specify the full_recout_width...according to Oswin + if (dst->full_recout_width == 0 && !dst->odm_combine) { + dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__); + full_recout_width = dst->recout_width * 2; // assume half split for dcn1 + } else + full_recout_width = dst->full_recout_width; + } else + full_recout_width = dst->recout_width; + + // As of DCN2, mpc_combine and odm_combine are mutually exclusive + refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_pre_l, + hscale_pixel_rate_l, + swath_width_pixels_ub_l, + 1); // per line + + refcyc_per_line_delivery_l = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_l, + hscale_pixel_rate_l, + swath_width_pixels_ub_l, + 1); // per line + + dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width); + dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l); + dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l); + dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l); + dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l); + dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l); + + //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l); + //old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l); + + if (dual_plane) { + float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_pre_c, + hscale_pixel_rate_c, + swath_width_pixels_ub_c, + 1); // per line + + refcyc_per_line_delivery_c = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_c, + hscale_pixel_rate_c, + swath_width_pixels_ub_c, + 1); // per line + + dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c); + dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, refcyc_per_line_delivery_c); + dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c); + dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c); + + //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c); + //old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c); + } + + if (src->dynamic_metadata_enable && src->gpuvm) + disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + // TTU - Luma / Chroma + if (access_dir) { // vertical access + scaler_rec_in_width_l = vp_height_l; + scaler_rec_in_width_c = vp_height_c; + } else { + scaler_rec_in_width_l = vp_width_l; + scaler_rec_in_width_c = vp_width_c; + } + + refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_pre_l, + hscale_pixel_rate_l, + scaler_rec_in_width_l, + req_per_swath_ub_l); // per req + + refcyc_per_req_delivery_l = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_l, + hscale_pixel_rate_l, + scaler_rec_in_width_l, + req_per_swath_ub_l); // per req + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l); + + //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l); + //old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l); + + ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); + + if (dual_plane) { + float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_pre_c, + hscale_pixel_rate_c, + scaler_rec_in_width_c, + req_per_swath_ub_c); // per req + refcyc_per_req_delivery_c = get_refcyc_per_delivery( + mode_lib, + refclk_freq_in_mhz, + pclk_freq_in_mhz, + dst->odm_combine, + full_recout_width, + dst->hactive, + vratio_c, + hscale_pixel_rate_c, + scaler_rec_in_width_c, + req_per_swath_ub_c); // per req + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c); + + //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c); + //old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c); + + ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); + } + + // TTU - Cursor + refcyc_per_req_delivery_pre_cur0 = 0.0; + refcyc_per_req_delivery_cur0 = 0.0; + + ASSERT(src->num_cursors <= 1); + + if (src->num_cursors > 0) { + float vba__refcyc_per_req_delivery_pre_cur0; + float vba__refcyc_per_req_delivery_cur0; + + calculate_ttu_cursor( + mode_lib, + &refcyc_per_req_delivery_pre_cur0, + &refcyc_per_req_delivery_cur0, + refclk_freq_in_mhz, + ref_freq_to_pix_freq, + hscale_pixel_rate_l, + scl->hscl_ratio, + vratio_pre_l, + vratio_l, + src->cur0_src_width, + (enum cursor_bpp) (src->cur0_bpp)); + + vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + + dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); + dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0); + dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0); + + //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0); + //old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0); + } + + refcyc_per_req_delivery_pre_cur1 = 0.0; + refcyc_per_req_delivery_cur1 = 0.0; + + // TTU - Misc + // all hard-coded + + // Assignment to register structures + disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line + ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); + disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); + disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + + disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + + dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); + dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); + dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); + dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); + + // hack for FPGA + if (mode_lib->project == DML_PROJECT_DCN31_FPGA) { + if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) { + disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1; + dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n"); + } + } + + disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); + ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); + + if (dual_plane) { + disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); + ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13)); + } + + disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); + + disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now + + disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; + disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; + + if (dual_plane) { + disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; + disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; + } + + disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + + // Clamp to max for now + if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + + if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + + if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + + if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + + disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); + ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); + if (dual_plane) { + disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2)); + if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { + dml_print( + "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", + __func__, + disp_dlg_regs->dst_y_per_pte_row_nom_c, + (unsigned int) dml_pow(2, 17) - 1); + } + } + + disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2)); + ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); + + disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2)); + ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); + + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_l); + if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_l); + if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + + if (dual_plane) { + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c); + if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + + // TODO: Is this the right calculation? Does htotal need to be halved? + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_c); + if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + } + + disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); + disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); + ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); + + disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); + disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1); + ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); + + disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; + disp_dlg_regs->dst_y_offset_cur0 = 0; + disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; + disp_dlg_regs->dst_y_offset_cur1 = 0; + + disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off + + disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10)); + + disp_ttu_regs->qos_level_low_wm = 0; + ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); + + disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq); + ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); + + disp_ttu_regs->qos_level_flip = 14; + disp_ttu_regs->qos_level_fixed_l = 8; + disp_ttu_regs->qos_level_fixed_c = 8; + disp_ttu_regs->qos_level_fixed_cur0 = 8; + disp_ttu_regs->qos_ramp_disable_l = 0; + disp_ttu_regs->qos_ramp_disable_c = 0; + disp_ttu_regs->qos_ramp_disable_cur0 = 0; + + disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); + + print__ttu_regs_st(mode_lib, *disp_ttu_regs); + print__dlg_regs_st(mode_lib, *disp_dlg_regs); +} + +void dml31_rq_dlg_get_dlg_reg( + struct display_mode_lib *mode_lib, + display_dlg_regs_st *dlg_regs, + display_ttu_regs_st *ttu_regs, + display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx, + const bool cstate_en, + const bool pstate_en, + const bool vm_en, + const bool ignore_viewport_pos, + const bool immediate_flip_support) +{ + display_rq_params_st rq_param = {0}; + display_dlg_sys_params_st dlg_sys_param = {0}; + + // Get watermark and Tex. + dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); + + print__dlg_sys_params_st(mode_lib, dlg_sys_param); + + // system parameter calculation done + + dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); + dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); + dml_rq_dlg_get_dlg_params( + mode_lib, + e2e_pipe_param, + num_pipes, + pipe_idx, + dlg_regs, + ttu_regs, + rq_param.dlg, + dlg_sys_param, + cstate_en, + pstate_en, + vm_en, + ignore_viewport_pos, + immediate_flip_support); + dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h new file mode 100644 index 000000000000..adf8518f761f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h @@ -0,0 +1,69 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DML31_DISPLAY_RQ_DLG_CALC_H__ +#define __DML31_DISPLAY_RQ_DLG_CALC_H__ + +#include "../display_rq_dlg_helpers.h" + +struct display_mode_lib; + +// Function: dml_rq_dlg_get_rq_reg +// Main entry point for test to get the register values out of this DML class. +// This function calls and fucntions to calculate +// and then populate the rq_regs struct +// Input: +// pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.) +// Output: +// rq_regs - struct that holds all the RQ registers field value. +// See also: +void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, + display_rq_regs_st *rq_regs, + const display_pipe_params_st pipe_param); + +// Function: dml_rq_dlg_get_dlg_reg +// Calculate and return DLG and TTU register struct given the system setting +// Output: +// dlg_regs - output DLG register struct +// ttu_regs - output DLG TTU register struct +// Input: +// e2e_pipe_param - "compacted" array of e2e pipe param struct +// num_pipes - num of active "pipe" or "route" +// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg +// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered. +// Added for legacy or unrealistic timing tests. +void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, + display_dlg_regs_st *dlg_regs, + display_ttu_regs_st *ttu_regs, + display_e2e_pipe_params_st *e2e_pipe_param, + const unsigned int num_pipes, + const unsigned int pipe_idx, + const bool cstate_en, + const bool pstate_en, + const bool vm_en, + const bool ignore_viewport_pos, + const bool immediate_flip_support); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c index 1f7b6ddf3020..8a5bd919aec8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c @@ -33,6 +33,8 @@ #include "dcn21/display_rq_dlg_calc_21.h" #include "dcn30/display_mode_vba_30.h" #include "dcn30/display_rq_dlg_calc_30.h" +#include "dcn31/display_mode_vba_31.h" +#include "dcn31/display_rq_dlg_calc_31.h" #include "dml_logger.h" const struct dml_funcs dml20_funcs = { @@ -63,6 +65,13 @@ const struct dml_funcs dml30_funcs = { .rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg }; +const struct dml_funcs dml31_funcs = { + .validate = dml31_ModeSupportAndSystemConfigurationFull, + .recalculate = dml31_recalculate, + .rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg, + .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg +}; + void dml_init_instance(struct display_mode_lib *lib, const struct _vcs_dpi_soc_bounding_box_st *soc_bb, const struct _vcs_dpi_ip_params_st *ip_params, @@ -84,6 +93,10 @@ void dml_init_instance(struct display_mode_lib *lib, case DML_PROJECT_DCN30: lib->funcs = dml30_funcs; break; + case DML_PROJECT_DCN31: + case DML_PROJECT_DCN31_FPGA: + lib->funcs = dml31_funcs; + break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h index 6ae5df58a4fc..d42a0aeca6be 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h @@ -38,6 +38,8 @@ enum dml_project { DML_PROJECT_NAVI10v2, DML_PROJECT_DCN21, DML_PROJECT_DCN30, + DML_PROJECT_DCN31, + DML_PROJECT_DCN31_FPGA, }; struct display_mode_lib; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index 2ece3690bfa3..64daa0507393 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -74,6 +74,8 @@ struct _vcs_dpi_soc_bounding_box_st { unsigned int num_states; double sr_exit_time_us; double sr_enter_plus_exit_time_us; + double sr_exit_z8_time_us; + double sr_enter_plus_exit_z8_time_us; double urgent_latency_us; double urgent_latency_pixel_data_only_us; double urgent_latency_pixel_mixed_with_vm_data_us; @@ -209,6 +211,12 @@ struct _vcs_dpi_ip_params_st { unsigned int is_line_buffer_bpp_fixed; unsigned int line_buffer_fixed_bpp; unsigned int dcc_supported; + unsigned int config_return_buffer_size_in_kbytes; + unsigned int compressed_buffer_segment_size_in_kbytes; + unsigned int meta_fifo_size_in_kentries; + unsigned int zero_size_buffer_entries; + unsigned int compbuf_reserved_space_64b; + unsigned int compbuf_reserved_space_zs; unsigned int IsLineBufferBppFixed; unsigned int LineBufferFixedBpp; @@ -253,6 +261,8 @@ struct _vcs_dpi_display_pipe_source_params_st { unsigned int viewport_y_c; unsigned int viewport_width_c; unsigned int viewport_height_c; + unsigned int viewport_width_max; + unsigned int viewport_height_max; unsigned int data_pitch; unsigned int data_pitch_c; unsigned int meta_pitch; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 2a967458065b..d3b1b6d4ce2f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -89,6 +89,10 @@ dml_get_attr_func(wm_memory_trip, mode_lib->vba.UrgentLatency); dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark); dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark); dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark); +dml_get_attr_func(wm_z8_stutter_exit, mode_lib->vba.Z8StutterExitWatermark); +dml_get_attr_func(wm_z8_stutter_enter_exit, mode_lib->vba.Z8StutterEnterPlusExitWatermark); +dml_get_attr_func(stutter_efficiency_z8, mode_lib->vba.Z8StutterEfficiency); +dml_get_attr_func(stutter_num_bursts_z8, mode_lib->vba.Z8NumberOfStutterBurstsPerFrame); dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark); dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark); dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency); @@ -153,11 +157,12 @@ dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_l_in_us, mode_lib->vba.TimeP dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimePerChromaMetaChunkVBlank); dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip); dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip); - dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup); dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix); dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix); dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix); +dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC); +dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START); double get_total_immediate_flip_bytes( struct display_mode_lib *mode_lib, @@ -226,6 +231,14 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) mode_lib->vba.WritebackLatency = soc->writeback_latency_us; mode_lib->vba.SRExitTime = soc->sr_exit_time_us; mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us; + mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = soc->pct_ideal_sdp_bw_after_urgent; + mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; + mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only; + mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only; + mode_lib->vba.MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation = + soc->max_avg_sdp_bw_use_normal_percent; + mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us; + mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us; mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support || @@ -299,7 +312,15 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib) mode_lib->vba.MaxDCHUBToPSCLThroughput = ip->max_dchub_pscl_bw_pix_per_clk; mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk; mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes; - mode_lib->vba.DETBufferSizeInKByte = ip->det_buffer_size_kbytes; + mode_lib->vba.DETBufferSizeInKByte[0] = ip->det_buffer_size_kbytes; + mode_lib->vba.ConfigReturnBufferSizeInKByte = ip->config_return_buffer_size_in_kbytes; + mode_lib->vba.CompressedBufferSegmentSizeInkByte = ip->compressed_buffer_segment_size_in_kbytes; + mode_lib->vba.MetaFIFOSizeInKEntries = ip->meta_fifo_size_in_kentries; + mode_lib->vba.ZeroSizeBufferEntries = ip->zero_size_buffer_entries; + mode_lib->vba.COMPBUF_RESERVED_SPACE_64B = ip->compbuf_reserved_space_64b; + mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs; + mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component; + mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support; mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes; mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes; @@ -389,7 +410,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) visited[j] = true; mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; - mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1; mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] = (enum scan_direction_class) (src->source_scan); @@ -429,6 +449,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c; mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal; mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal; + mode_lib->vba.VFrontPorch[mode_lib->vba.NumberOfActivePlanes] = dst->vfront_porch; + mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_luma; + mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_chroma; mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = src->dcc_use_global ? ip->dcc_supported : src->dcc && ip->dcc_supported; @@ -630,6 +653,19 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) } } } + if (src->viewport_width_max) { + int hdiv_c = src->source_format >= dm_420_8 && src->source_format <= dm_422_10 ? 2 : 1; + int vdiv_c = src->source_format >= dm_420_8 && src->source_format <= dm_420_12 ? 2 : 1; + + if (mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] > src->viewport_width_max) + mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_max; + if (mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] > src->viewport_height_max) + mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_max; + if (mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] > src->viewport_width_max / hdiv_c) + mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_max / hdiv_c; + if (mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] > src->viewport_height_max / vdiv_c) + mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_max / vdiv_c; + } if (pipes[k].pipe.src.immediate_flip) { mode_lib->vba.ImmediateFlipSupport = true; @@ -662,6 +698,11 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) } } + mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting; + for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) { + if (pipes[k].pipe.src.unbounded_req_mode == 0) + mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting_disable; + } // TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified // Do we want the dscclk to automatically be halved? Guess not since the value is specified mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 025aa5bd8ea0..d18a021d4d32 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -39,6 +39,10 @@ dml_get_attr_decl(wm_memory_trip); dml_get_attr_decl(wm_writeback_urgent); dml_get_attr_decl(wm_stutter_exit); dml_get_attr_decl(wm_stutter_enter_exit); +dml_get_attr_decl(wm_z8_stutter_exit); +dml_get_attr_decl(wm_z8_stutter_enter_exit); +dml_get_attr_decl(stutter_efficiency_z8); +dml_get_attr_decl(stutter_num_bursts_z8); dml_get_attr_decl(wm_dram_clock_change); dml_get_attr_decl(wm_writeback_dram_clock_change); dml_get_attr_decl(stutter_efficiency_no_vblank); @@ -102,6 +106,8 @@ dml_get_pipe_attr_decl(vstartup); dml_get_pipe_attr_decl(vupdate_offset); dml_get_pipe_attr_decl(vupdate_width); dml_get_pipe_attr_decl(vready_offset); +dml_get_pipe_attr_decl(vready_at_or_after_vsync); +dml_get_pipe_attr_decl(min_dst_y_next_start); double get_total_immediate_flip_bytes( struct display_mode_lib *mode_lib, @@ -233,7 +239,7 @@ struct vba_vars_st { // IP Parameters // unsigned int ROBBufferSizeInKByte; - double DETBufferSizeInKByte; + unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX]; double DETBufferSizeInTime; unsigned int DPPOutputBufferPixels; unsigned int OPPOutputBufferLines; @@ -351,8 +357,8 @@ struct vba_vars_st { // Intermediates/Informational bool ImmediateFlipSupport; - double DETBufferSizeY[DC__NUM_DPP__MAX]; - double DETBufferSizeC[DC__NUM_DPP__MAX]; + unsigned int DETBufferSizeY[DC__NUM_DPP__MAX]; + unsigned int DETBufferSizeC[DC__NUM_DPP__MAX]; unsigned int SwathHeightY[DC__NUM_DPP__MAX]; unsigned int SwathHeightC[DC__NUM_DPP__MAX]; unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; @@ -631,8 +637,8 @@ struct vba_vars_st { enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; double dummy1[DC__NUM_DPP__MAX]; double dummy2[DC__NUM_DPP__MAX]; - double dummy3[DC__NUM_DPP__MAX]; - double dummy4[DC__NUM_DPP__MAX]; + unsigned int dummy3[DC__NUM_DPP__MAX]; + unsigned int dummy4[DC__NUM_DPP__MAX]; double dummy5; double dummy6; double dummy7[DC__NUM_DPP__MAX]; @@ -872,8 +878,8 @@ struct vba_vars_st { int PercentMarginOverMinimumRequiredDCFCLK; bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2]; enum immediate_flip_requirement ImmediateFlipRequirement; - double DETBufferSizeYThisState[DC__NUM_DPP__MAX]; - double DETBufferSizeCThisState[DC__NUM_DPP__MAX]; + unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX]; + unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; @@ -923,6 +929,46 @@ struct vba_vars_st { bool ClampMinDCFCLK; bool AllowDramClockChangeOneDisplayVactive; + double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation; + double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency; + double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData; + double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly; + double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly; + double SRExitZ8Time; + double SREnterPlusExitZ8Time; + double Z8StutterExitWatermark; + double Z8StutterEnterPlusExitWatermark; + double Z8StutterEfficiencyNotIncludingVBlank; + double Z8StutterEfficiency; + double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX]; + double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX]; + double UrgBurstFactorCursor[DC__NUM_DPP__MAX]; + double UrgBurstFactorLuma[DC__NUM_DPP__MAX]; + double UrgBurstFactorChroma[DC__NUM_DPP__MAX]; + double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX]; + double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX]; + double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX]; + bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; + bool LinkCapacitySupport[DC__NUM_DPP__MAX]; + bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX]; + unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX]; + unsigned int VFrontPorch[DC__NUM_DPP__MAX]; + int ConfigReturnBufferSizeInKByte; + enum unbounded_requesting_policy UseUnboundedRequesting; + int CompressedBufferSegmentSizeInkByte; + int CompressedBufferSizeInkByte; + int MetaFIFOSizeInKEntries; + int ZeroSizeBufferEntries; + int COMPBUF_RESERVED_SPACE_64B; + int COMPBUF_RESERVED_SPACE_ZS; + bool UnboundedRequestEnabled; + bool DSC422NativeSupport; + bool NoEnoughUrgentLatencyHiding; + bool NoEnoughUrgentLatencyHidingPre; + int NumberOfStutterBurstsPerFrame; + int Z8NumberOfStutterBurstsPerFrame; + unsigned int MaximumDSCBitsPerComponent; + unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; }; bool CalculateMinAndMaxPrefetchMode( diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index be57088d185d..f403d8e84a8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -37,6 +37,8 @@ static uint32_t dsc_policy_max_target_bpp_limit = 16; /* default DSC policy enables DSC only when needed */ static bool dsc_policy_enable_dsc_when_not_needed; +static bool dsc_policy_disable_dsc_stream_overhead; + static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size) { @@ -250,6 +252,7 @@ static bool intersect_dsc_caps( if (pixel_encoding == PIXEL_ENCODING_YCBCR422 || pixel_encoding == PIXEL_ENCODING_YCBCR420) dsc_common_caps->bpp_increment_div = min(dsc_common_caps->bpp_increment_div, (uint32_t)8); + dsc_common_caps->is_dp = dsc_sink_caps->is_dp; return true; } @@ -258,12 +261,63 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value) return (value + 9) / 10; } +static struct fixed31_32 compute_dsc_max_bandwidth_overhead( + const struct dc_crtc_timing *timing, + const int num_slices_h, + const bool is_dp) +{ + struct fixed31_32 max_dsc_overhead; + struct fixed31_32 refresh_rate; + + if (dsc_policy_disable_dsc_stream_overhead || !is_dp) + return dc_fixpt_from_int(0); + + /* use target bpp that can take entire target bandwidth */ + refresh_rate = dc_fixpt_from_int(timing->pix_clk_100hz); + refresh_rate = dc_fixpt_div_int(refresh_rate, timing->h_total); + refresh_rate = dc_fixpt_div_int(refresh_rate, timing->v_total); + refresh_rate = dc_fixpt_mul_int(refresh_rate, 100); + + max_dsc_overhead = dc_fixpt_from_int(num_slices_h); + max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, timing->v_total); + max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, 256); + max_dsc_overhead = dc_fixpt_div_int(max_dsc_overhead, 1000); + max_dsc_overhead = dc_fixpt_mul(max_dsc_overhead, refresh_rate); + + return max_dsc_overhead; +} + +static uint32_t compute_bpp_x16_from_target_bandwidth( + const uint32_t bandwidth_in_kbps, + const struct dc_crtc_timing *timing, + const uint32_t num_slices_h, + const uint32_t bpp_increment_div, + const bool is_dp) +{ + struct fixed31_32 overhead_in_kbps; + struct fixed31_32 effective_bandwidth_in_kbps; + struct fixed31_32 bpp_x16; + + overhead_in_kbps = compute_dsc_max_bandwidth_overhead( + timing, num_slices_h, is_dp); + effective_bandwidth_in_kbps = dc_fixpt_from_int(bandwidth_in_kbps); + effective_bandwidth_in_kbps = dc_fixpt_sub(effective_bandwidth_in_kbps, + overhead_in_kbps); + bpp_x16 = dc_fixpt_mul_int(effective_bandwidth_in_kbps, 10); + bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz); + bpp_x16 = dc_fixpt_from_int(dc_fixpt_floor(dc_fixpt_mul_int(bpp_x16, bpp_increment_div))); + bpp_x16 = dc_fixpt_div_int(bpp_x16, bpp_increment_div); + bpp_x16 = dc_fixpt_mul_int(bpp_x16, 16); + return dc_fixpt_floor(bpp_x16); +} + /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock * and uncompressed bandwidth. */ static void get_dsc_bandwidth_range( const uint32_t min_bpp_x16, const uint32_t max_bpp_x16, + const uint32_t num_slices_h, const struct dsc_enc_caps *dsc_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) @@ -272,16 +326,21 @@ static void get_dsc_bandwidth_range( range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing); /* max dsc target bpp */ - range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, max_bpp_x16); + range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing, + max_bpp_x16, num_slices_h, dsc_caps->is_dp); range->max_target_bpp_x16 = max_bpp_x16; if (range->max_kbps > range->stream_kbps) { /* max dsc target bpp is capped to native bandwidth */ range->max_kbps = range->stream_kbps; - range->max_target_bpp_x16 = calc_dsc_bpp_x16(range->stream_kbps, timing->pix_clk_100hz, dsc_caps->bpp_increment_div); + range->max_target_bpp_x16 = compute_bpp_x16_from_target_bandwidth( + range->max_kbps, timing, num_slices_h, + dsc_caps->bpp_increment_div, + dsc_caps->is_dp); } /* min dsc target bpp */ - range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, min_bpp_x16); + range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing, + min_bpp_x16, num_slices_h, dsc_caps->is_dp); range->min_target_bpp_x16 = min_bpp_x16; if (range->min_kbps > range->max_kbps) { /* min dsc target bpp is capped to max dsc bandwidth*/ @@ -290,7 +349,6 @@ static void get_dsc_bandwidth_range( } } - /* Decides if DSC should be used and calculates target bpp if it should, applying DSC policy. * * Returns: @@ -303,6 +361,7 @@ static bool decide_dsc_target_bpp_x16( const struct dsc_enc_caps *dsc_common_caps, const int target_bandwidth_kbps, const struct dc_crtc_timing *timing, + const int num_slices_h, int *target_bpp_x16) { bool should_use_dsc = false; @@ -311,7 +370,7 @@ static bool decide_dsc_target_bpp_x16( memset(&range, 0, sizeof(range)); get_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16, - dsc_common_caps, timing, &range); + num_slices_h, dsc_common_caps, timing, &range); if (!policy->enable_dsc_when_not_needed && target_bandwidth_kbps >= range.stream_kbps) { /* enough bandwidth without dsc */ *target_bpp_x16 = 0; @@ -327,7 +386,10 @@ static bool decide_dsc_target_bpp_x16( should_use_dsc = true; } else if (target_bandwidth_kbps >= range.min_kbps) { /* use target bpp that can take entire target bandwidth */ - *target_bpp_x16 = calc_dsc_bpp_x16(target_bandwidth_kbps, timing->pix_clk_100hz, dsc_common_caps->bpp_increment_div); + *target_bpp_x16 = compute_bpp_x16_from_target_bandwidth( + target_bandwidth_kbps, timing, num_slices_h, + dsc_common_caps->bpp_increment_div, + dsc_common_caps->is_dp); should_use_dsc = true; } else { /* not enough bandwidth to fulfill minimum requirement */ @@ -531,18 +593,6 @@ static bool setup_dsc_config( if (!is_dsc_possible) goto done; - if (target_bandwidth_kbps > 0) { - is_dsc_possible = decide_dsc_target_bpp_x16( - &policy, - &dsc_common_caps, - target_bandwidth_kbps, - timing, - &target_bpp); - dsc_cfg->bits_per_pixel = target_bpp; - } - if (!is_dsc_possible) - goto done; - sink_per_slice_throughput_mps = 0; // Validate available DSC settings against the mode timing @@ -690,12 +740,26 @@ static bool setup_dsc_config( dsc_cfg->num_slices_v = pic_height/slice_height; + if (target_bandwidth_kbps > 0) { + is_dsc_possible = decide_dsc_target_bpp_x16( + &policy, + &dsc_common_caps, + target_bandwidth_kbps, + timing, + num_slices_h, + &target_bpp); + dsc_cfg->bits_per_pixel = target_bpp; + } + if (!is_dsc_possible) + goto done; + // Final decission: can we do DSC or not? if (is_dsc_possible) { // Fill out the rest of DSC settings dsc_cfg->block_pred_enable = dsc_common_caps.is_block_pred_supported; dsc_cfg->linebuf_depth = dsc_common_caps.lb_bit_depth; dsc_cfg->version_minor = (dsc_common_caps.dsc_version & 0xf0) >> 4; + dsc_cfg->is_dp = dsc_sink_caps->is_dp; } done: @@ -806,6 +870,7 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da dsc_sink_caps->branch_max_line_width = dpcd_dsc_branch_decoder_caps[DP_DSC_BRANCH_MAX_LINE_WIDTH - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0] * 320; ASSERT(dsc_sink_caps->branch_max_line_width == 0 || dsc_sink_caps->branch_max_line_width >= 5120); + dsc_sink_caps->is_dp = true; return true; } @@ -838,7 +903,8 @@ bool dc_dsc_compute_bandwidth_range( dsc_min_slice_height_override, max_bpp_x16, &config); if (is_dsc_possible) - get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range); + get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, + config.num_slices_h, &dsc_common_caps, timing, range); return is_dsc_possible; } @@ -864,13 +930,20 @@ bool dc_dsc_compute_config( return is_dsc_possible; } -uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16) +uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, + uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp) { - struct fixed31_32 link_bw_kbps; - link_bw_kbps = dc_fixpt_from_int(pix_clk_100hz); - link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160); - link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, bpp_x16); - return dc_fixpt_ceil(link_bw_kbps); + struct fixed31_32 overhead_in_kbps; + struct fixed31_32 bpp; + struct fixed31_32 actual_bandwidth_in_kbps; + + overhead_in_kbps = compute_dsc_max_bandwidth_overhead( + timing, num_slices_h, is_dp); + bpp = dc_fixpt_from_fraction(bpp_x16, 16); + actual_bandwidth_in_kbps = dc_fixpt_from_fraction(timing->pix_clk_100hz, 10); + actual_bandwidth_in_kbps = dc_fixpt_mul(actual_bandwidth_in_kbps, bpp); + actual_bandwidth_in_kbps = dc_fixpt_add(actual_bandwidth_in_kbps, overhead_in_kbps); + return dc_fixpt_ceil(actual_bandwidth_in_kbps); } void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy) @@ -954,3 +1027,8 @@ void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable) { dsc_policy_enable_dsc_when_not_needed = enable; } + +void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable) +{ + dsc_policy_disable_dsc_stream_overhead = disable; +} diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index c6a1cd80aeae..7b294f637881 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -284,26 +284,6 @@ static u32 _do_bytes_per_pixel_calc(int slice_width, u16 drm_bpp, return bytes_per_pixel; } -static u32 _do_calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz, - u32 bpp_increment_div) -{ - u32 dsc_target_bpp_x16; - float f_dsc_target_bpp; - float f_stream_bandwidth_100bps; - // bpp_increment_div is actually precision - u32 precision = bpp_increment_div; - - f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f; - f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz; - - // Round down to the nearest precision stop to bring it into DSC spec - // range - dsc_target_bpp_x16 = (u32)(f_dsc_target_bpp * precision); - dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision; - - return dsc_target_bpp_x16; -} - /** * calc_rc_params - reads the user's cmdline mode * @rc: DC internal DSC parameters @@ -367,26 +347,3 @@ u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps) DC_FP_END(); return ret; } - -/** - * calc_dsc_bpp_x16 - retrieve the dsc bits per pixel - * @stream_bandwidth_kbps: - * @pix_clk_100hz: - * @bpp_increment_div: - * - * Calculate the total of bits per pixel for DSC configuration. - * - * @note This calculation requires float point operation, most of it executes - * under kernel_fpu_{begin,end}. - */ -u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz, - u32 bpp_increment_div) -{ - u32 dsc_bpp; - - DC_FP_START(); - dsc_bpp = _do_calc_dsc_bpp_x16(stream_bandwidth_kbps, pix_clk_100hz, - bpp_increment_div); - DC_FP_END(); - return dsc_bpp; -} diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h index 8123827840c5..262f06afcbf9 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h @@ -79,8 +79,6 @@ typedef struct qp_entry qp_table[]; void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps); u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps); -u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz, - u32 bpp_increment_div); #endif diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index 92280cc05e2d..dae8e489c8cf 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -53,8 +53,8 @@ */ struct gpio_service *dal_gpio_service_create( - enum dce_version dce_version_major, - enum dce_version dce_version_minor, + enum dce_version dce_version, + enum dce_environment dce_environment, struct dc_context *ctx) { struct gpio_service *service; @@ -67,14 +67,14 @@ struct gpio_service *dal_gpio_service_create( return NULL; } - if (!dal_hw_translate_init(&service->translate, dce_version_major, - dce_version_minor)) { + if (!dal_hw_translate_init(&service->translate, dce_version, + dce_environment)) { BREAK_TO_DEBUGGER(); goto failure_1; } - if (!dal_hw_factory_init(&service->factory, dce_version_major, - dce_version_minor)) { + if (!dal_hw_factory_init(&service->factory, dce_version, + dce_environment)) { BREAK_TO_DEBUGGER(); goto failure_1; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 92c65d2fa7d7..c5c840a06050 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -111,6 +111,8 @@ bool dal_hw_factory_init( case DCN_VERSION_3_0: case DCN_VERSION_3_01: case DCN_VERSION_3_02: + case DCN_VERSION_3_03: + case DCN_VERSION_3_1: dal_hw_factory_dcn30_init(factory); return true; #endif diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index da9499c09a11..4a9848308766 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -106,6 +106,8 @@ bool dal_hw_translate_init( case DCN_VERSION_3_0: case DCN_VERSION_3_01: case DCN_VERSION_3_02: + case DCN_VERSION_3_03: + case DCN_VERSION_3_1: dal_hw_translate_dcn30_init(translate); return true; #endif diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c index 51855a2624cf..4233955e3c47 100644 --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c @@ -33,6 +33,7 @@ #include "core_types.h" #include "dc_link_ddc.h" #include "link_hwss.h" +#include "inc/link_dpcd.h" #define DC_LOGGER \ link->ctx->logger diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 81b92f20d5b6..45a6216dfa2a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -338,6 +338,7 @@ union pipe_update_flags { uint32_t scaler : 1; uint32_t viewport : 1; uint32_t plane_changed : 1; + uint32_t det_size : 1; } bits; uint32_t raw; }; @@ -365,6 +366,8 @@ struct pipe_ctx { struct _vcs_dpi_display_ttu_regs_st ttu_regs; struct _vcs_dpi_display_rq_regs_st rq_regs; struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; + int det_buffer_size_kb; + bool unbounded_req; #endif union pipe_update_flags update_flags; struct dwbc *dwbc; @@ -415,6 +418,7 @@ struct dcn_bw_output { struct dc_clocks clk; struct dcn_watermark_set watermarks; struct dcn_bw_writeback bw_writeback; + int compbuf_size_kb; }; union bw_output { diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 3ae05c96d557..e2b58ec9912d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,11 +30,29 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/ +#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 +#define TRAINING_AUX_RD_INTERVAL 100 //us struct dc_link; struct dc_stream_state; struct dc_link_settings; +enum { + LINK_TRAINING_MAX_RETRY_COUNT = 5, + /* to avoid infinite loop where-in the receiver + * switches between different VS + */ + LINK_TRAINING_MAX_CR_RETRY = 100, + /* + * Some receivers fail to train on first try and are good + * on subsequent tries. 2 retries should be plenty. If we + * don't have a successful training then we don't expect to + * ever get one. + */ + LINK_TRAINING_MAX_VERIFY_RETRY = 2, + PEAK_FACTOR_X1000 = 1006, +}; + bool dp_verify_link_cap( struct dc_link *link, struct dc_link_settings *known_limit_link_setting, @@ -65,7 +83,12 @@ bool perform_link_training_with_retries( bool skip_video_pattern, int attempts, struct pipe_ctx *pipe_ctx, - enum signal_type signal); + enum signal_type signal, + bool do_fallback); + +bool hpd_rx_irq_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data); bool is_mst_supported(struct dc_link *link); @@ -75,6 +98,8 @@ void detect_edp_sink_caps(struct dc_link *link); bool is_dp_active_dongle(const struct dc_link *link); +bool is_dp_branch_device(const struct dc_link *link); + bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); void dp_enable_mst_on_sink(struct dc_link *link, bool enable); @@ -85,8 +110,59 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); bool dp_overwrite_extended_receiver_cap(struct dc_link *link); void dpcd_set_source_specific_data(struct dc_link *link); +/* Write DPCD link configuration data. */ +enum dc_status dpcd_set_link_settings( + struct dc_link *link, + const struct link_training_settings *lt_settings); +/* Write DPCD drive settings. */ +enum dc_status dpcd_set_lane_settings( + struct dc_link *link, + const struct link_training_settings *link_training_setting, + uint32_t offset); +/* Read training status and adjustment requests from DPCD. */ +enum dc_status dp_get_lane_status_and_drive_settings( + struct dc_link *link, + const struct link_training_settings *link_training_setting, + union lane_status *ln_status, + union lane_align_status_updated *ln_status_updated, + struct link_training_settings *req_settings, + uint32_t offset); -void dp_set_fec_ready(struct dc_link *link, bool ready); +void dp_wait_for_training_aux_rd_interval( + struct dc_link *link, + uint32_t wait_in_micro_secs); + +bool dp_is_cr_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); + +enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); + +bool dp_is_ch_eq_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); +bool dp_is_symbol_locked(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status); +bool dp_is_interlane_aligned(union lane_align_status_updated align_status); + +bool dp_is_max_vs_reached( + const struct link_training_settings *lt_settings); + +void dp_update_drive_settings( + struct link_training_settings *dest, + struct link_training_settings src); + +uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval); + +enum dpcd_training_patterns + dc_dp_training_pattern_to_dpcd_training_pattern( + struct dc_link *link, + enum dc_dp_training_pattern pattern); + +uint8_t dc_dp_initialize_scrambling_data_symbols( + struct dc_link *link, + enum dc_dp_training_pattern pattern); + +enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready); void dp_set_fec_enable(struct dc_link *link, bool enable); bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); @@ -94,5 +170,25 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable); +/* Initialize output parameter lt_settings. */ +void dp_decide_training_settings( + struct dc_link *link, + const struct dc_link_settings *link_setting, + const struct dc_link_training_overrides *overrides, + struct link_training_settings *lt_settings); +/* Convert PHY repeater count read from DPCD uint8_t. */ +uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count); + +/* Check DPCD training status registers to detect link loss. */ +enum link_training_result dp_check_link_loss_status( + struct dc_link *link, + const struct link_training_settings *link_training_setting); + +enum dc_status dpcd_configure_lttpr_mode( + struct dc_link *link, + struct link_training_settings *lt_settings); + +enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings); +bool dp_retrieve_lttpr_cap(struct dc_link *link); #endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index e8ce8c85adf1..142753644377 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -52,7 +52,8 @@ struct abm_funcs { unsigned int (*get_target_backlight)(struct abm *abm); bool (*init_abm_config)(struct abm *abm, const char *src, - unsigned int bytes); + unsigned int bytes, + unsigned int inst); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 5dc8d02b40c3..a17e5de3b100 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -91,6 +91,7 @@ struct clk_limit_table_entry { unsigned int dispclk_mhz; unsigned int dppclk_mhz; unsigned int phyclk_mhz; + unsigned int wck_ratio; }; /* This table is contiguous */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 336c80a18175..0afa2364a986 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -29,11 +29,40 @@ #include "dc_types.h" #include "hw_shared.h" +enum phyd32clk_clock_source { + PHYD32CLKA, + PHYD32CLKB, + PHYD32CLKC, + PHYD32CLKD, + PHYD32CLKE, + PHYD32CLKF, + PHYD32CLKG, +}; + +enum physymclk_clock_source { + PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO. + PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO. + PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. +}; + +enum hdmistreamclk_source { + REFCLK, // Selects REFCLK as source for hdmistreamclk. + DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. +}; + +enum dentist_dispclk_change_mode { + DISPCLK_CHANGE_MODE_IMMEDIATE, + DISPCLK_CHANGE_MODE_RAMPING, +}; + struct dccg { struct dc_context *ctx; const struct dccg_funcs *funcs; int pipe_dppclk_khz[MAX_PIPES]; int ref_dppclk; + int dtbclk_khz[MAX_PIPES]; + int audio_dtbclk_khz; + int ref_dtbclk_khz; }; struct dccg_funcs { @@ -43,7 +72,34 @@ struct dccg_funcs { void (*get_dccg_ref_freq)(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz); + void (*set_fifo_errdet_ovr_en)(struct dccg *dccg, + bool en); + void (*otg_add_pixel)(struct dccg *dccg, + uint32_t otg_inst); + void (*otg_drop_pixel)(struct dccg *dccg, + uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); + + void (*set_physymclk)( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable); + + void (*set_dtbclk_dto)( + struct dccg *dccg, + int dtbclk_inst, + int req_dtbclk_khz, + int num_odm_segments, + const struct dc_crtc_timing *timing); + + void (*set_audio_dtbclk_dto)( + struct dccg *dccg, + uint32_t req_audio_dtbclk_khz); + + void (*set_dispclk_change_mode)( + struct dccg *dccg, + enum dentist_dispclk_change_mode change_mode); }; #endif //__DAL_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index d9fd28b34f2a..0638b337f143 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -152,6 +152,9 @@ struct hubbub_funcs { void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); void (*init_watermarks)(struct hubbub *hubbub); + void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); + void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); + void (*init_crb)(struct hubbub *hubbub); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index ddbe4bb52724..00fc81431b43 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -32,6 +32,12 @@ struct dpp { const struct dpp_funcs *funcs; struct dc_context *ctx; + /** + * @inst: + * + * inst stands for "instance," and it is an id number that references a + * specific DPP. + */ int inst; struct dpp_caps *caps; struct pwl_params regamma_params; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h index f520e13aee4c..f94135c6e3c2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h @@ -88,6 +88,7 @@ struct dsc_enc_caps { int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */ int32_t max_slice_width; uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ + bool is_dp; }; struct dsc_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 80bc99500645..9eaf345aa2a1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -127,6 +127,12 @@ struct link_enc_state { }; +enum encoder_type_select { + ENCODER_TYPE_DIG = 0, + ENCODER_TYPE_HDMI_FRL = 1, + ENCODER_TYPE_DP_128B132B = 2 +}; + struct link_encoder_funcs { void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); @@ -185,6 +191,10 @@ struct link_encoder_funcs { enum signal_type (*get_dig_mode)( struct link_encoder *enc); + void (*set_dio_phy_mux)( + struct link_encoder *enc, + enum encoder_type_select sel, + uint32_t hpo_inst); }; /* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 2e2310f1901a..8798cfa11a4d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -33,6 +33,8 @@ struct dchub_init_data; struct cstate_pstate_watermarks_st { uint32_t cstate_exit_ns; + uint32_t cstate_exit_z8_ns; + uint32_t cstate_enter_plus_exit_z8_ns; uint32_t cstate_enter_plus_exit_ns; uint32_t pstate_change_ns; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 75c77ad9cbfe..640bb432bd6a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -363,6 +363,9 @@ struct mpc_funcs { struct mpc *mpc, int opp_id); + void (*set_bg_color)(struct mpc *mpc, + struct tg_color *bg_color, + int mpcc_id); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 47c7e4c3a51b..564ea6a727b0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -237,6 +237,9 @@ struct stream_encoder_funcs { void (*dp_set_odm_combine)( struct stream_encoder *enc, bool odm_combine); + + uint32_t (*get_fifo_cal_average_level)( + struct stream_encoder *enc); }; #endif /* STREAM_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 9ff68b67780c..03f47f23fb65 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -173,6 +173,7 @@ struct timing_generator_funcs { bool (*enable_crtc)(struct timing_generator *tg); bool (*disable_crtc)(struct timing_generator *tg); + bool (*immediate_disable_crtc)(struct timing_generator *tg); bool (*is_counter_moving)(struct timing_generator *tg); void (*get_position)(struct timing_generator *tg, struct crtc_position *position); @@ -223,6 +224,8 @@ struct timing_generator_funcs { void (*enable_advanced_request)(struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing); void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); + void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); + void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); void (*set_static_screen_control)(struct timing_generator *tg, uint32_t event_triggers, uint32_t num_frames); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 2947d1b15512..2a0db2b03047 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -162,9 +162,7 @@ struct scl_inits { struct fixed31_32 h; struct fixed31_32 h_c; struct fixed31_32 v; - struct fixed31_32 v_bot; struct fixed31_32 v_c; - struct fixed31_32 v_c_bot; }; struct scaler_data { @@ -173,8 +171,6 @@ struct scaler_data { struct scaling_taps taps; struct rect viewport; struct rect viewport_c; - struct rect viewport_unadjusted; - struct rect viewport_c_unadjusted; struct rect recout; struct scaling_ratios ratios; struct scl_inits inits; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 1d5853c95448..5ab008e62b82 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -235,6 +235,13 @@ struct hw_sequencer_funcs { enum dc_color_depth color_depth, const struct tg_color *solid_color, int width, int height, int offset); + + void (*z10_restore)(struct dc *dc); + + void (*update_visual_confirm_color)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct tg_color *color, + int mpcc_id); }; void color_space_to_black_color( @@ -249,4 +256,17 @@ const uint16_t *find_color_matrix( enum dc_color_space color_space, uint32_t *array_size); +void get_surface_visual_confirm_color( + const struct pipe_ctx *pipe_ctx, + struct tg_color *color); + +void get_hdr_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); +void get_mpctree_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); +void get_surface_tile_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); #endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index 36e906bb6bfc..f7f7e4fff0c2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -127,11 +127,6 @@ struct hwseq_private_funcs { const struct dc_stream_state *stream, struct dc_state *context); bool (*s0i3_golden_init_wa)(struct dc *dc); - void (*get_surface_visual_confirm_color)( - const struct pipe_ctx *pipe_ctx, - struct tg_color *color); - void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx, - struct tg_color *color); void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); void (*verify_allow_pstate_change_high)(struct dc *dc); void (*program_pipe)(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h b/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h new file mode 100644 index 000000000000..d4d52ef1b165 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h @@ -0,0 +1,18 @@ +#ifndef __LINK_DPCD_H__ +#define __LINK_DPCD_H__ +#include +#include +#include + +enum dc_status core_link_read_dpcd( + struct dc_link *link, + uint32_t address, + uint8_t *data, + uint32_t size); + +enum dc_status core_link_write_dpcd( + struct dc_link *link, + uint32_t address, + const uint8_t *data, + uint32_t size); +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h index 7d36e55f3097..883dd8733ea4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h @@ -81,6 +81,11 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc( /* Return DIG link encoder used by link. NULL if unused. */ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link( struct dc_state *state, - struct dc_link *link); + const struct dc_link *link); + +/* Return next available DIG link encoder. NULL if none available. */ +struct link_encoder *link_enc_cfg_get_next_avail_link_enc( + const struct dc *dc, + const struct dc_state *state); #endif /* DC_INC_LINK_ENC_CFG_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h index 33590a728fc5..fc1d289bb9fe 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -26,20 +26,6 @@ #ifndef __DC_LINK_HWSS_H__ #define __DC_LINK_HWSS_H__ -#include "inc/core_status.h" - -enum dc_status core_link_read_dpcd( - struct dc_link *link, - uint32_t address, - uint8_t *data, - uint32_t size); - -enum dc_status core_link_write_dpcd( - struct dc_link *link, - uint32_t address, - const uint8_t *data, - uint32_t size); - struct gpio *get_hpd_gpio(struct dc_bios *dcb, struct graphics_object_id link_id, struct gpio_service *gpio_service); diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index ca8168726324..0d09181227c5 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -109,4 +109,21 @@ IRQ_DCN3_02 = irq_service_dcn302.o AMD_DAL_IRQ_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/irq/dcn302/,$(IRQ_DCN3_02)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_02) +############################################################################### +# DCN 3_03 +############################################################################### +IRQ_DCN3_03 = irq_service_dcn303.o + +AMD_DAL_IRQ_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/irq/dcn303/,$(IRQ_DCN3_03)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_03) + +############################################################################### +# DCN 31 +############################################################################### +IRQ_DCN31 = irq_service_dcn31.o + +AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31) endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c index 1a5be2792055..ed54e1c819be 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c @@ -58,8 +58,8 @@ enum dc_irq_source to_dal_irq_source_dcn21( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; - case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT: - return DC_IRQ_SOURCE_DMCUB_OUTBOX0; + case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX; case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: return DC_IRQ_SOURCE_DC1_VLINE0; case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: @@ -187,7 +187,7 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .ack = NULL }; -static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = { +static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = { .set = NULL, .ack = NULL }; @@ -301,11 +301,11 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = { .funcs = &vline0_irq_info_funcs\ } -#define dmub_trace_int_entry()\ - [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\ - IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\ - DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\ - .funcs = &dmub_trace_irq_info_funcs\ +#define dmub_outbox_int_entry()\ + [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ + IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ + DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ + .funcs = &dmub_outbox_irq_info_funcs\ } #define dummy_irq_entry() \ @@ -426,7 +426,7 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = { vline0_int_entry(3), vline0_int_entry(4), vline0_int_entry(5), - dmub_trace_int_entry(), + dmub_outbox_int_entry(), }; static const struct irq_service_funcs irq_service_funcs_dcn21 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c new file mode 100644 index 000000000000..66e60762388e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#include "dm_services.h" +#include "irq_service_dcn303.h" +#include "../dce110/irq_service_dce110.h" + +#include "sienna_cichlid_ip_offset.h" +#include "dcn/dcn_3_0_3_offset.h" +#include "dcn/dcn_3_0_3_sh_mask.h" + +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" + +static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id) +{ + switch (src_id) { + case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK1; + case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK2; + case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP1; + case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP2; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + + case DCN_1_0__SRCID__DC_HPD1_INT: + /* generic src_id for all HPD and HPDRX interrupts */ + switch (ext_id) { + case DCN_1_0__CTXID__DC_HPD1_INT: + return DC_IRQ_SOURCE_HPD1; + case DCN_1_0__CTXID__DC_HPD2_INT: + return DC_IRQ_SOURCE_HPD2; + case DCN_1_0__CTXID__DC_HPD1_RX_INT: + return DC_IRQ_SOURCE_HPD1RX; + case DCN_1_0__CTXID__DC_HPD2_RX_INT: + return DC_IRQ_SOURCE_HPD2RX; + default: + return DC_IRQ_SOURCE_INVALID; + } + break; + + default: + return DC_IRQ_SOURCE_INVALID; + } +} + +static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info) +{ + uint32_t addr = info->status_reg; + uint32_t value = dm_read_reg(irq_service->ctx, addr); + uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED); + + dal_irq_service_ack_generic(irq_service, info); + + value = dm_read_reg(irq_service->ctx, info->enable_reg); + + set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); + + dm_write_reg(irq_service->ctx, info->enable_reg, value); + + return true; +} + +static const struct irq_source_info_funcs hpd_irq_info_funcs = { + .set = NULL, + .ack = hpd_ack +}; + +static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs pflip_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vblank_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +/* compile time expand base address. */ +#define BASE(seg) BASE_INNER(seg) + +#define SRI(reg_name, block, id)\ + BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + mm ## block ## id ## _ ## reg_name + + +#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ + .enable_reg = SRI(reg1, block, reg_num),\ + .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI(reg2, block, reg_num),\ + .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ + + + +#define hpd_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_irq_info_funcs\ +} + +#define hpd_rx_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_rx_irq_info_funcs\ +} +#define pflip_int_entry(reg_num)\ + [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ + IRQ_REG_ENTRY(HUBPREQ, reg_num,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ + .funcs = &pflip_irq_info_funcs\ +} + +/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic + * of DCE's DC_IRQ_SOURCE_VUPDATEx. + */ +#define vupdate_no_lock_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ + .funcs = &vupdate_no_lock_irq_info_funcs\ + } + +#define vblank_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ + .funcs = &vblank_irq_info_funcs\ + } + +#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs } + +#define i2c_int_entry(reg_num) \ + [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() + +#define dp_sink_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() + +#define gpio_pad_int_entry(reg_num) \ + [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() + +#define dc_underflow_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() + +static const struct irq_source_info_funcs dummy_irq_info_funcs = { + .set = dal_irq_service_dummy_set, + .ack = dal_irq_service_dummy_ack +}; + +static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = { + [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), + hpd_int_entry(0), + hpd_int_entry(1), + hpd_rx_int_entry(0), + hpd_rx_int_entry(1), + i2c_int_entry(1), + i2c_int_entry(2), + dp_sink_int_entry(1), + dp_sink_int_entry(2), + [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), + pflip_int_entry(0), + pflip_int_entry(1), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), + gpio_pad_int_entry(2), + gpio_pad_int_entry(3), + gpio_pad_int_entry(4), + gpio_pad_int_entry(5), + gpio_pad_int_entry(6), + gpio_pad_int_entry(7), + gpio_pad_int_entry(8), + gpio_pad_int_entry(9), + gpio_pad_int_entry(10), + gpio_pad_int_entry(11), + gpio_pad_int_entry(12), + gpio_pad_int_entry(13), + gpio_pad_int_entry(14), + gpio_pad_int_entry(15), + gpio_pad_int_entry(16), + gpio_pad_int_entry(17), + gpio_pad_int_entry(18), + gpio_pad_int_entry(19), + gpio_pad_int_entry(20), + gpio_pad_int_entry(21), + gpio_pad_int_entry(22), + gpio_pad_int_entry(23), + gpio_pad_int_entry(24), + gpio_pad_int_entry(25), + gpio_pad_int_entry(26), + gpio_pad_int_entry(27), + gpio_pad_int_entry(28), + gpio_pad_int_entry(29), + gpio_pad_int_entry(30), + dc_underflow_int_entry(1), + dc_underflow_int_entry(2), + [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), + [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), + vupdate_no_lock_int_entry(0), + vupdate_no_lock_int_entry(1), + vblank_int_entry(0), + vblank_int_entry(1), +}; + +static const struct irq_service_funcs irq_service_funcs_dcn303 = { + .to_dal_irq_source = to_dal_irq_source_dcn303 +}; + +static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data) +{ + dal_irq_service_construct(irq_service, init_data); + + irq_service->info = irq_source_info_dcn303; + irq_service->funcs = &irq_service_funcs_dcn303; +} + +struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data) +{ + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL); + + if (!irq_service) + return NULL; + + dcn303_irq_construct(irq_service, init_data); + return irq_service; +} diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h new file mode 100644 index 000000000000..fd64e3848ff3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef __DAL_IRQ_SERVICE_DCN303_H__ +#define __DAL_IRQ_SERVICE_DCN303_H__ + +#include "../irq_service.h" + +struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data); + +#endif /* __DAL_IRQ_SERVICE_DCN303_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c new file mode 100644 index 000000000000..38e0ade60c7b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c @@ -0,0 +1,432 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "include/logger_interface.h" +#include "../dce110/irq_service_dce110.h" + + +#include "yellow_carp_offset.h" +#include "dcn/dcn_3_1_2_offset.h" +#include "dcn/dcn_3_1_2_sh_mask.h" + +#include "irq_service_dcn31.h" + +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" + +enum dc_irq_source to_dal_irq_source_dcn31( + struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id) +{ + switch (src_id) { + case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK1; + case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK2; + case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK3; + case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK4; + case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK5; + case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; + case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP1; + case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP2; + case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP3; + case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP4; + case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP5; + case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP6; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE3; + case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE4; + case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE5; + case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE6; + case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX; + case DCN_1_0__SRCID__DC_HPD1_INT: + /* generic src_id for all HPD and HPDRX interrupts */ + switch (ext_id) { + case DCN_1_0__CTXID__DC_HPD1_INT: + return DC_IRQ_SOURCE_HPD1; + case DCN_1_0__CTXID__DC_HPD2_INT: + return DC_IRQ_SOURCE_HPD2; + case DCN_1_0__CTXID__DC_HPD3_INT: + return DC_IRQ_SOURCE_HPD3; + case DCN_1_0__CTXID__DC_HPD4_INT: + return DC_IRQ_SOURCE_HPD4; + case DCN_1_0__CTXID__DC_HPD5_INT: + return DC_IRQ_SOURCE_HPD5; + case DCN_1_0__CTXID__DC_HPD6_INT: + return DC_IRQ_SOURCE_HPD6; + case DCN_1_0__CTXID__DC_HPD1_RX_INT: + return DC_IRQ_SOURCE_HPD1RX; + case DCN_1_0__CTXID__DC_HPD2_RX_INT: + return DC_IRQ_SOURCE_HPD2RX; + case DCN_1_0__CTXID__DC_HPD3_RX_INT: + return DC_IRQ_SOURCE_HPD3RX; + case DCN_1_0__CTXID__DC_HPD4_RX_INT: + return DC_IRQ_SOURCE_HPD4RX; + case DCN_1_0__CTXID__DC_HPD5_RX_INT: + return DC_IRQ_SOURCE_HPD5RX; + case DCN_1_0__CTXID__DC_HPD6_RX_INT: + return DC_IRQ_SOURCE_HPD6RX; + default: + return DC_IRQ_SOURCE_INVALID; + } + break; + + default: + return DC_IRQ_SOURCE_INVALID; + } +} + +static bool hpd_ack( + struct irq_service *irq_service, + const struct irq_source_info *info) +{ + uint32_t addr = info->status_reg; + uint32_t value = dm_read_reg(irq_service->ctx, addr); + uint32_t current_status = + get_reg_field_value( + value, + HPD0_DC_HPD_INT_STATUS, + DC_HPD_SENSE_DELAYED); + + dal_irq_service_ack_generic(irq_service, info); + + value = dm_read_reg(irq_service->ctx, info->enable_reg); + + set_reg_field_value( + value, + current_status ? 0 : 1, + HPD0_DC_HPD_INT_CONTROL, + DC_HPD_INT_POLARITY); + + dm_write_reg(irq_service->ctx, info->enable_reg, value); + + return true; +} + +static const struct irq_source_info_funcs hpd_irq_info_funcs = { + .set = NULL, + .ack = hpd_ack +}; + +static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs pflip_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vblank_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs outbox_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +/* compile time expand base address. */ +#define BASE(seg) \ + BASE_INNER(seg) + +#define SRI(reg_name, block, id)\ + BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name + +#define SRI_DMUB(reg_name)\ + BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ + .enable_reg = SRI(reg1, block, reg_num),\ + .enable_mask = \ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI(reg2, block, reg_num),\ + .ack_mask = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ + +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ + .enable_reg = SRI_DMUB(reg1),\ + .enable_mask = \ + reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + reg1 ## __ ## mask1 ## _MASK,\ + ~reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI_DMUB(reg2),\ + .ack_mask = \ + reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + reg2 ## __ ## mask2 ## _MASK \ + +#define hpd_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_irq_info_funcs\ + } + +#define hpd_rx_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_rx_irq_info_funcs\ + } +#define pflip_int_entry(reg_num)\ + [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ + IRQ_REG_ENTRY(HUBPREQ, reg_num,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ + .funcs = &pflip_irq_info_funcs\ + } + +/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic + * of DCE's DC_IRQ_SOURCE_VUPDATEx. + */ +#define vupdate_no_lock_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ + .funcs = &vupdate_no_lock_irq_info_funcs\ + } + +#define vblank_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ + .funcs = &vblank_irq_info_funcs\ + } + +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } +#define dmub_outbox_int_entry()\ + [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ + IRQ_REG_ENTRY_DMUB(\ + DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ + DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ + .funcs = &outbox_irq_info_funcs\ + } + +#define dummy_irq_entry() \ + {\ + .funcs = &dummy_irq_info_funcs\ + } + +#define i2c_int_entry(reg_num) \ + [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() + +#define dp_sink_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() + +#define gpio_pad_int_entry(reg_num) \ + [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() + +#define dc_underflow_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() + +static const struct irq_source_info_funcs dummy_irq_info_funcs = { + .set = dal_irq_service_dummy_set, + .ack = dal_irq_service_dummy_ack +}; + +static const struct irq_source_info +irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = { + [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), + hpd_int_entry(0), + hpd_int_entry(1), + hpd_int_entry(2), + hpd_int_entry(3), + hpd_int_entry(4), + hpd_rx_int_entry(0), + hpd_rx_int_entry(1), + hpd_rx_int_entry(2), + hpd_rx_int_entry(3), + hpd_rx_int_entry(4), + i2c_int_entry(1), + i2c_int_entry(2), + i2c_int_entry(3), + i2c_int_entry(4), + i2c_int_entry(5), + i2c_int_entry(6), + dp_sink_int_entry(1), + dp_sink_int_entry(2), + dp_sink_int_entry(3), + dp_sink_int_entry(4), + dp_sink_int_entry(5), + dp_sink_int_entry(6), + [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), + pflip_int_entry(0), + pflip_int_entry(1), + pflip_int_entry(2), + pflip_int_entry(3), + [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), + gpio_pad_int_entry(2), + gpio_pad_int_entry(3), + gpio_pad_int_entry(4), + gpio_pad_int_entry(5), + gpio_pad_int_entry(6), + gpio_pad_int_entry(7), + gpio_pad_int_entry(8), + gpio_pad_int_entry(9), + gpio_pad_int_entry(10), + gpio_pad_int_entry(11), + gpio_pad_int_entry(12), + gpio_pad_int_entry(13), + gpio_pad_int_entry(14), + gpio_pad_int_entry(15), + gpio_pad_int_entry(16), + gpio_pad_int_entry(17), + gpio_pad_int_entry(18), + gpio_pad_int_entry(19), + gpio_pad_int_entry(20), + gpio_pad_int_entry(21), + gpio_pad_int_entry(22), + gpio_pad_int_entry(23), + gpio_pad_int_entry(24), + gpio_pad_int_entry(25), + gpio_pad_int_entry(26), + gpio_pad_int_entry(27), + gpio_pad_int_entry(28), + gpio_pad_int_entry(29), + gpio_pad_int_entry(30), + dc_underflow_int_entry(1), + dc_underflow_int_entry(2), + dc_underflow_int_entry(3), + dc_underflow_int_entry(4), + dc_underflow_int_entry(5), + dc_underflow_int_entry(6), + [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), + [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), + vupdate_no_lock_int_entry(0), + vupdate_no_lock_int_entry(1), + vupdate_no_lock_int_entry(2), + vupdate_no_lock_int_entry(3), + vblank_int_entry(0), + vblank_int_entry(1), + vblank_int_entry(2), + vblank_int_entry(3), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), + [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), + dmub_outbox_int_entry(), +}; + +static const struct irq_service_funcs irq_service_funcs_dcn31 = { + .to_dal_irq_source = to_dal_irq_source_dcn31 +}; + +static void dcn31_irq_construct( + struct irq_service *irq_service, + struct irq_service_init_data *init_data) +{ + dal_irq_service_construct(irq_service, init_data); + + irq_service->info = irq_source_info_dcn31; + irq_service->funcs = &irq_service_funcs_dcn31; +} + +struct irq_service *dal_irq_service_dcn31_create( + struct irq_service_init_data *init_data) +{ + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); + + if (!irq_service) + return NULL; + + dcn31_irq_construct(irq_service, init_data); + return irq_service; +} diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h new file mode 100644 index 000000000000..67efbfe9b7aa --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h @@ -0,0 +1,34 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IRQ_SERVICE_DCN31_H__ +#define __DAL_IRQ_SERVICE_DCN31_H__ + +#include "../irq_service.h" + +struct irq_service *dal_irq_service_dcn31_create( + struct irq_service_init_data *init_data); + +#endif /* __DAL_IRQ_SERVICE_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h index ae8f47ec0f8c..5f9346622301 100644 --- a/drivers/gpu/drm/amd/display/dc/irq_types.h +++ b/drivers/gpu/drm/amd/display/dc/irq_types.h @@ -150,7 +150,7 @@ enum dc_irq_source { DC_IRQ_SOURCE_DC4_VLINE1, DC_IRQ_SOURCE_DC5_VLINE1, DC_IRQ_SOURCE_DC6_VLINE1, - DC_IRQ_DMCUB_OUTBOX1, + DC_IRQ_SOURCE_DMCUB_OUTBOX, DC_IRQ_SOURCE_DMCUB_OUTBOX0, DAL_IRQ_SOURCES_NUMBER diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index b4e14960b164..abbf7ae584c9 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -73,6 +73,7 @@ extern "C" { /* Forward declarations */ struct dmub_srv; struct dmub_srv_common_regs; +struct dmub_srv_dcn31_regs; struct dmcub_trace_buf_entry; @@ -93,6 +94,8 @@ enum dmub_asic { DMUB_ASIC_DCN30, DMUB_ASIC_DCN301, DMUB_ASIC_DCN302, + DMUB_ASIC_DCN303, + DMUB_ASIC_DCN31, DMUB_ASIC_MAX, }; @@ -216,6 +219,49 @@ struct dmub_srv_fb_info { struct dmub_fb fb[DMUB_WINDOW_TOTAL]; }; +/* + * struct dmub_srv_hw_params - params for dmub hardware initialization + * @fb: framebuffer info for each region + * @fb_base: base of the framebuffer aperture + * @fb_offset: offset of the framebuffer aperture + * @psp_version: psp version to pass for DMCU init + * @load_inst_const: true if DMUB should load inst const fw + */ +struct dmub_srv_hw_params { + struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; + uint64_t fb_base; + uint64_t fb_offset; + uint32_t psp_version; + bool load_inst_const; + bool skip_panel_power_sequence; + bool disable_z10; +}; + +/** + * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for + * debugging purposes, including logging, crash analysis, etc. + */ +struct dmub_diagnostic_data { + uint32_t dmcub_version; + uint32_t scratch[16]; + uint32_t pc; + uint32_t undefined_address_fault_addr; + uint32_t inst_fetch_fault_addr; + uint32_t data_write_fault_addr; + uint32_t inbox1_rptr; + uint32_t inbox1_wptr; + uint32_t inbox1_size; + uint32_t inbox0_rptr; + uint32_t inbox0_wptr; + uint32_t inbox0_size; + uint8_t is_dmcub_enabled : 1; + uint8_t is_dmcub_soft_reset : 1; + uint8_t is_dmcub_secure_reset : 1; + uint8_t is_traceport_en : 1; + uint8_t is_cw0_enabled : 1; + uint8_t is_cw6_enabled : 1; +}; + /** * struct dmub_srv_base_funcs - Driver specific base callbacks */ @@ -290,7 +336,8 @@ struct dmub_srv_hw_funcs { bool (*is_hw_init)(struct dmub_srv *dmub); bool (*is_phy_init)(struct dmub_srv *dmub); - void (*enable_dmub_boot_options)(struct dmub_srv *dmub); + void (*enable_dmub_boot_options)(struct dmub_srv *dmub, + const struct dmub_srv_hw_params *params); void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); @@ -305,6 +352,10 @@ struct dmub_srv_hw_funcs { uint32_t (*get_gpint_response)(struct dmub_srv *dmub); + void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); + uint32_t (*get_current_time)(struct dmub_srv *dmub); + + void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca); }; /** @@ -325,23 +376,6 @@ struct dmub_srv_create_params { bool is_virtual; }; -/* - * struct dmub_srv_hw_params - params for dmub hardware initialization - * @fb: framebuffer info for each region - * @fb_base: base of the framebuffer aperture - * @fb_offset: offset of the framebuffer aperture - * @psp_version: psp version to pass for DMCU init - * @load_inst_const: true if DMUB should load inst const fw - */ -struct dmub_srv_hw_params { - struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; - uint64_t fb_base; - uint64_t fb_offset; - uint32_t psp_version; - bool load_inst_const; - bool skip_panel_power_sequence; -}; - /** * struct dmub_srv - software state for dmcub * @asic: dmub asic identifier @@ -360,6 +394,7 @@ struct dmub_srv { /* private: internal use only */ const struct dmub_srv_common_regs *regs; + const struct dmub_srv_dcn31_regs *regs_dcn31; struct dmub_srv_base_funcs funcs; struct dmub_srv_hw_funcs hw_funcs; @@ -669,6 +704,8 @@ enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); +bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data); + #if defined(__cplusplus) } #endif diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 4195ff10c514..7c4734f905d9 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x23db9b126 +#define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 62 +#define DMUB_FW_VERSION_REVISION 71 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 @@ -121,14 +121,25 @@ #define TRACE_BUFFER_ENTRY_OFFSET 16 /** - * ABM backlight control version legacy + * + * PSR control version legacy */ -#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_UNKNOWN 0x0 +#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 +/** + * PSR control version with multi edp support + */ +#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 + /** - * ABM backlight control version with multi edp support + * ABM control version legacy */ -#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1 0x1 +#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 + +/** + * ABM control version with multi edp support + */ +#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 /** * Physical framebuffer address location, 64-bit. @@ -162,6 +173,13 @@ extern "C" { #define dmub_udelay(microseconds) udelay(microseconds) #endif +/** + * Number of nanoseconds per DMUB tick. + * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. + * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. + */ +#define NS_PER_DMUB_TICK 10 + /** * union dmub_addr - DMUB physical/virtual 64-bit address. */ @@ -291,6 +309,7 @@ struct dmcub_trace_buf_entry { * Current scratch register usage is as follows: * * SCRATCH0: FW Boot Status register + * SCRATCH5: LVTMA Status Register * SCRATCH15: FW Boot Options register */ @@ -317,6 +336,21 @@ enum dmub_fw_boot_status_bit { DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ }; +/* Register bit definition for SCRATCH5 */ +union dmub_lvtma_status { + struct { + uint32_t psp_ok : 1; + uint32_t edp_on : 1; + uint32_t reserved : 30; + } bits; + uint32_t all; +}; + +enum dmub_lvtma_status_bit { + DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), + DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), +}; + /** * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 */ @@ -328,7 +362,8 @@ union dmub_fw_boot_options { uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ - uint32_t reserved : 26; /**< reserved */ + uint32_t z10_disable: 1; /**< 1 to disable z10 */ + uint32_t reserved : 25; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; @@ -452,6 +487,61 @@ enum dmub_gpint_command { DMUB_GPINT__PSR_RESIDENCY = 9, }; +/** + * INBOX0 generic command definition + */ +union dmub_inbox0_cmd_common { + struct { + uint32_t command_code: 8; /**< INBOX0 command code */ + uint32_t param: 24; /**< 24-bit parameter */ + } bits; + uint32_t all; +}; + +/** + * INBOX0 hw_lock command definition + */ +union dmub_inbox0_cmd_lock_hw { + struct { + uint32_t command_code: 8; + + /* NOTE: Must be have enough bits to match: enum hw_lock_client */ + uint32_t hw_lock_client: 1; + + /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ + uint32_t otg_inst: 3; + uint32_t opp_inst: 3; + uint32_t dig_inst: 3; + + /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ + uint32_t lock_pipe: 1; + uint32_t lock_cursor: 1; + uint32_t lock_dig: 1; + uint32_t triple_buffer_lock: 1; + + uint32_t lock: 1; /**< Lock */ + uint32_t should_release: 1; /**< Release */ + uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ + } bits; + uint32_t all; +}; + +union dmub_inbox0_data_register { + union dmub_inbox0_cmd_common inbox0_cmd_common; + union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; +}; + +enum dmub_inbox0_command { + /** + * DESC: Invalid command, ignored. + */ + DMUB_INBOX0_CMD__INVALID_COMMAND = 0, + /** + * DESC: Notification to acquire/release HW lock + * ARGS: + */ + DMUB_INBOX0_CMD__HW_LOCK = 1, +}; //============================================================================== //================================================================= //============================================================================== @@ -537,6 +627,22 @@ enum dmub_cmd_type { * Command type used for OUTBOX1 notification enable */ DMUB_CMD__OUTBOX1_ENABLE = 71, + /** + * Command type used for all idle optimization commands. + */ + DMUB_CMD__IDLE_OPT = 72, + /** + * Command type used for all clock manager commands. + */ + DMUB_CMD__CLK_MGR = 73, + /** + * Command type used for all panel control commands. + */ + DMUB_CMD__PANEL_CNTL = 74, + /** + * Command type used for EDID CEA parsing + */ + DMUB_CMD__EDID_CEA = 79, /** * Command type used for all VBIOS interface commands. */ @@ -555,10 +661,6 @@ enum dmub_out_cmd_type { * Command type used for DP AUX Reply data notification */ DMUB_OUT_CMD__DP_AUX_REPLY = 1, - /** - * Command type used for DP HPD event notification - */ - DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, }; #pragma pack(push, 1) @@ -570,7 +672,8 @@ struct dmub_cmd_header { unsigned int type : 8; /**< command type */ unsigned int sub_type : 8; /**< command sub type */ unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ - unsigned int reserved0 : 7; /**< reserved bits */ + unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ + unsigned int reserved0 : 6; /**< reserved bits */ unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ unsigned int reserved1 : 2; /**< reserved bits */ }; @@ -745,6 +848,51 @@ struct dmub_rb_cmd_mall { uint8_t reserved2; /**< Reserved bits */ }; +/** + * enum dmub_cmd_idle_opt_type - Idle optimization command type. + */ +enum dmub_cmd_idle_opt_type { + /** + * DCN hardware restore. + */ + DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, +}; + +/** + * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. + */ +struct dmub_rb_cmd_idle_opt_dcn_restore { + struct dmub_cmd_header header; /**< header */ +}; + +/** + * struct dmub_clocks - Clock update notification. + */ +struct dmub_clocks { + uint32_t dispclk_khz; /**< dispclk kHz */ + uint32_t dppclk_khz; /**< dppclk kHz */ + uint32_t dcfclk_khz; /**< dcfclk kHz */ + uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ +}; + +/** + * enum dmub_cmd_clk_mgr_type - Clock manager commands. + */ +enum dmub_cmd_clk_mgr_type { + /** + * Notify DMCUB of clock update. + */ + DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, +}; + +/** + * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. + */ +struct dmub_rb_cmd_clk_mgr_notify_clocks { + struct dmub_cmd_header header; /**< header */ + struct dmub_clocks clocks; /**< clock data */ +}; + /** * struct dmub_cmd_digx_encoder_control_data - Encoder control data. */ @@ -1249,9 +1397,15 @@ struct dmub_cmd_psr_copy_settings_data { */ uint8_t fec_enable_delay_in100us; /** - * Explicit padding to 4 byte boundary. + * PSR control version. */ - uint8_t pad3[2]; + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; }; /** @@ -1276,10 +1430,16 @@ struct dmub_cmd_psr_set_level_data { * 16-bit value dicated by driver that will enable/disable different functionality. */ uint16_t psr_level; - /** - * Explicit padding to 4 byte boundary. + /** + * PSR control version. */ - uint8_t pad[2]; + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; }; /** @@ -1296,6 +1456,23 @@ struct dmub_rb_cmd_psr_set_level { struct dmub_cmd_psr_set_level_data psr_set_level_data; }; +struct dmub_rb_cmd_psr_enable_data { + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + /** * Definition of a DMUB_CMD__PSR_ENABLE command. * PSR enable/disable is controlled using the sub_type. @@ -1305,6 +1482,8 @@ struct dmub_rb_cmd_psr_enable { * Command header. */ struct dmub_cmd_header header; + + struct dmub_rb_cmd_psr_enable_data data; }; /** @@ -1315,6 +1494,20 @@ struct dmub_cmd_psr_set_version_data { * PSR version that FW should implement. */ enum psr_version version; + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -1331,6 +1524,23 @@ struct dmub_rb_cmd_psr_set_version { struct dmub_cmd_psr_set_version_data psr_set_version_data; }; +struct dmub_cmd_psr_force_static_data { + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + /** * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. */ @@ -1339,10 +1549,17 @@ struct dmub_rb_cmd_psr_force_static { * Command header. */ struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. + */ + struct dmub_cmd_psr_force_static_data psr_force_static_data; }; /** * Set of HW components that can be locked. + * + * Note: If updating with more HW components, fields + * in dmub_inbox0_cmd_lock_hw must be updated to match. */ union dmub_hw_lock_flags { /** @@ -1375,6 +1592,9 @@ union dmub_hw_lock_flags { /** * Instances of HW to be locked. + * + * Note: If updating with more HW components, fields + * in dmub_inbox0_cmd_lock_hw must be updated to match. */ struct dmub_hw_lock_inst_flags { /** @@ -1398,16 +1618,15 @@ struct dmub_hw_lock_inst_flags { /** * Clients that can acquire the HW Lock Manager. + * + * Note: If updating with more clients, fields in + * dmub_inbox0_cmd_lock_hw must be updated to match. */ enum hw_lock_client { /** * Driver is the client of HW Lock Manager. */ HW_LOCK_CLIENT_DRIVER = 0, - /** - * FW is the client of HW Lock Manager. - */ - HW_LOCK_CLIENT_FW, /** * Invalid client. */ @@ -1637,7 +1856,7 @@ struct dmub_cmd_abm_set_backlight_data { uint32_t backlight_user_level; /** - * Backlight data version. + * ABM control version. */ uint8_t version; @@ -1677,6 +1896,23 @@ struct dmub_cmd_abm_set_level_data { * Set current ABM operating/aggression level. */ uint32_t level; + + /** + * ABM control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -1702,6 +1938,23 @@ struct dmub_cmd_abm_set_ambient_level_data { * Ambient light sensor reading from OS. */ uint32_t ambient_lux; + + /** + * ABM control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -1728,6 +1981,23 @@ struct dmub_cmd_abm_set_pwm_frac_data { * TODO: Convert to uint8_t. */ uint32_t fractional_pwm; + + /** + * ABM control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -1758,6 +2028,24 @@ struct dmub_cmd_abm_init_config_data { * Indirect buffer length. */ uint16_t bytes; + + + /** + * ABM control version. + */ + uint8_t version; + + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -1815,6 +2103,41 @@ struct dmub_rb_cmd_drr_update { struct dmub_optc_state dmub_optc_state_req; }; +/** + * enum dmub_cmd_panel_cntl_type - Panel control command. + */ +enum dmub_cmd_panel_cntl_type { + /** + * Initializes embedded panel hardware blocks. + */ + DMUB_CMD__PANEL_CNTL_HW_INIT = 0, + /** + * Queries backlight info for the embedded panel. + */ + DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, +}; + +/** + * struct dmub_cmd_panel_cntl_data - Panel control data. + */ +struct dmub_cmd_panel_cntl_data { + uint32_t inst; /**< panel instance */ + uint32_t current_backlight; /* in/out */ + uint32_t bl_pwm_cntl; /* in/out */ + uint32_t bl_pwm_period_cntl; /* in/out */ + uint32_t bl_pwm_ref_div1; /* in/out */ + uint8_t is_backlight_on : 1; /* in/out */ + uint8_t is_powered_on : 1; /* in/out */ +}; + +/** + * struct dmub_rb_cmd_panel_cntl - Panel control command. + */ +struct dmub_rb_cmd_panel_cntl { + struct dmub_cmd_header header; /**< header */ + struct dmub_cmd_panel_cntl_data data; /**< payload */ +}; + /** * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. */ @@ -1839,6 +2162,68 @@ struct dmub_rb_cmd_lvtma_control { struct dmub_cmd_lvtma_control_data data; }; +/** + * Maximum number of bytes a chunk sent to DMUB for parsing + */ +#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 + +/** + * Represent a chunk of CEA blocks sent to DMUB for parsing + */ +struct dmub_cmd_send_edid_cea { + uint16_t offset; /**< offset into the CEA block */ + uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ + uint16_t total_length; /**< total length of the CEA block */ + uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ + uint8_t pad[3]; /**< padding and for future expansion */ +}; + +/** + * Result of VSDB parsing from CEA block + */ +struct dmub_cmd_edid_cea_amd_vsdb { + uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ + uint8_t freesync_supported; /**< 1 if Freesync is supported */ + uint16_t amd_vsdb_version; /**< AMD VSDB version */ + uint16_t min_frame_rate; /**< Maximum frame rate */ + uint16_t max_frame_rate; /**< Minimum frame rate */ +}; + +/** + * Result of sending a CEA chunk + */ +struct dmub_cmd_edid_cea_ack { + uint16_t offset; /**< offset of the chunk into the CEA block */ + uint8_t success; /**< 1 if this sending of chunk succeeded */ + uint8_t pad; /**< padding and for future expansion */ +}; + +/** + * Specify whether the result is an ACK/NACK or the parsing has finished + */ +enum dmub_cmd_edid_cea_reply_type { + DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ + DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ +}; + +/** + * Definition of a DMUB_CMD__EDID_CEA command. + */ +struct dmub_rb_cmd_edid_cea { + struct dmub_cmd_header header; /**< Command header */ + union dmub_cmd_edid_cea_data { + struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ + struct dmub_cmd_edid_cea_output { /**< output with results */ + uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ + union { + struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; + struct dmub_cmd_edid_cea_ack ack; + }; + } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ + } data; /**< Command data */ + +}; + /** * union dmub_rb_cmd - DMUB inbox command. */ @@ -1912,6 +2297,20 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__MALL command. */ struct dmub_rb_cmd_mall mall; + /** + * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. + */ + struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; + + /** + * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. + */ + struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; + + /** + * Definition of DMUB_CMD__PANEL_CNTL commands. + */ + struct dmub_rb_cmd_panel_cntl panel_cntl; /** * Definition of a DMUB_CMD__ABM_SET_PIPE command. */ @@ -1961,6 +2360,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. */ struct dmub_rb_cmd_lvtma_control lvtma_control; + /** + * Definition of a DMUB_CMD__EDID_CEA command. + */ + struct dmub_rb_cmd_edid_cea edid_cea; }; /** @@ -2126,6 +2529,46 @@ static inline bool dmub_rb_front(struct dmub_rb *rb, return true; } +/** + * @brief Determines the next ringbuffer offset. + * + * @param rb DMUB inbox ringbuffer + * @param num_cmds Number of commands + * @param next_rptr The next offset in the ringbuffer + */ +static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, + uint32_t num_cmds, + uint32_t *next_rptr) +{ + *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; + + if (*next_rptr >= rb->capacity) + *next_rptr %= rb->capacity; +} + +/** + * @brief Returns a pointer to a command in the inbox. + * + * @param rb DMUB inbox ringbuffer + * @param cmd The inbox command to return + * @param rptr The ringbuffer offset + * @return true if not empty + * @return false otherwise + */ +static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, + union dmub_rb_cmd **cmd, + uint32_t rptr) +{ + uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; + + if (dmub_rb_empty(rb)) + return false; + + *cmd = (union dmub_rb_cmd *)rb_cmd; + + return true; +} + /** * @brief Returns the next unprocessed command in the outbox. * diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index 7495c23c73a9..0495bcdd3463 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -21,8 +21,8 @@ # DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o -DMUB += dmub_dcn30.o dmub_dcn301.o -DMUB += dmub_dcn302.o +DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o +DMUB += dmub_dcn31.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index 6934906c665e..a6540e27044d 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -40,7 +40,10 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = { #define DMUB_SR(reg) REG_OFFSET(reg), - { DMUB_COMMON_REGS() }, + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), @@ -385,7 +388,7 @@ union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub) return status; } -void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub) +void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) { union dmub_fw_boot_options boot_options = {0}; @@ -399,3 +402,68 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) boot_options.bits.skip_phy_init_panel_sequence = skip; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } + +uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} + +void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) +{ + uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; + uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; + + if (!dmub || !diag_data) + return; + + memset(diag_data, 0, sizeof(*diag_data)); + + diag_data->dmcub_version = dmub->fw_version; + + diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); + diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); + diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); + diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); + diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); + diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); + diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); + diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); + diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); + diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); + diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); + diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); + diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); + diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); + diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); + diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); + + diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); + diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); + diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); + + diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); + diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); + diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); + + diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); + diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); + diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); + diag_data->is_dmcub_enabled = is_dmub_enabled; + + REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); + diag_data->is_dmcub_soft_reset = is_soft_reset; + + REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); + diag_data->is_dmcub_secure_reset = is_sec_reset; + + REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); + diag_data->is_traceport_en = is_traceport_enabled; + + REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); + diag_data->is_cw0_enabled = is_cw0_enabled; + + REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); + diag_data->is_cw6_enabled = is_cw6_enabled; +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h index de5351cd5abc..c2e5831ac52c 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h @@ -36,6 +36,9 @@ struct dmub_srv; DMUB_SR(DMCUB_CNTL) \ DMUB_SR(DMCUB_MEM_CNTL) \ DMUB_SR(DMCUB_SEC_CNTL) \ + DMUB_SR(DMCUB_INBOX0_SIZE) \ + DMUB_SR(DMCUB_INBOX0_RPTR) \ + DMUB_SR(DMCUB_INBOX0_WPTR) \ DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \ DMUB_SR(DMCUB_INBOX1_SIZE) \ DMUB_SR(DMCUB_INBOX1_RPTR) \ @@ -107,7 +110,13 @@ struct dmub_srv; DMUB_SR(MMHUBBUB_SOFT_RESET) \ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ DMUB_SR(DCN_VM_FB_OFFSET) \ - DMUB_SR(DMCUB_INTERRUPT_ACK) + DMUB_SR(DMCUB_INTERRUPT_ACK) \ + DMUB_SR(DMCUB_TIMER_CURRENT) \ + DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \ + DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \ + DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) + +#define DMCUB_INTERNAL_REGS() #define DMUB_COMMON_FIELDS() \ DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ @@ -117,6 +126,7 @@ struct dmub_srv; DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \ DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \ DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ @@ -146,6 +156,7 @@ struct dmub_srv; struct dmub_srv_common_reg_offset { #define DMUB_SR(reg) uint32_t reg; DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() #undef DMUB_SR }; @@ -221,7 +232,7 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub, uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub); -void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub); +void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); @@ -231,4 +242,8 @@ bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub); bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub); +uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub); + +void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca); + #endif /* _DMUB_DCN20_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c index 1cf67b3e4771..51bb9bceb1b1 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c @@ -39,7 +39,10 @@ const struct dmub_srv_common_regs dmub_srv_dcn21_regs = { #define DMUB_SR(reg) REG_OFFSET(reg), - { DMUB_COMMON_REGS() }, + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c index fb11c8d39208..81dae75e9ff8 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c @@ -40,7 +40,10 @@ const struct dmub_srv_common_regs dmub_srv_dcn30_regs = { #define DMUB_SR(reg) REG_OFFSET(reg), - { DMUB_COMMON_REGS() }, + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c index 197398257692..84c3ab3becc5 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c @@ -39,7 +39,10 @@ const struct dmub_srv_common_regs dmub_srv_dcn301_regs = { #define DMUB_SR(reg) REG_OFFSET(reg), - { DMUB_COMMON_REGS() }, + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c index f5db4437a882..8c02575e168d 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c @@ -39,7 +39,10 @@ const struct dmub_srv_common_regs dmub_srv_dcn302_regs = { #define DMUB_SR(reg) REG_OFFSET(reg), - { DMUB_COMMON_REGS() }, + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c new file mode 100644 index 000000000000..b42369984473 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn303.h" + +#include "sienna_cichlid_ip_offset.h" +#include "dcn/dcn_3_0_3_offset.h" +#include "dcn/dcn_3_0_3_sh_mask.h" + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg +#define CTX dmub +#define REGS dmub->regs + +/* Registers. */ + +const struct dmub_srv_common_regs dmub_srv_dcn303_regs = { +#define DMUB_SR(reg) REG_OFFSET(reg), + { + DMUB_COMMON_REGS() + DMCUB_INTERNAL_REGS() + }, +#undef DMUB_SR + +#define DMUB_SF(reg, field) FD_MASK(reg, field), + { DMUB_COMMON_FIELDS() }, +#undef DMUB_SF + +#define DMUB_SF(reg, field) FD_SHIFT(reg, field), + { DMUB_COMMON_FIELDS() }, +#undef DMUB_SF +}; + +/* Shared functions. */ + diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h new file mode 100644 index 000000000000..84141d450256 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _DMUB_DCN303_H_ +#define _DMUB_DCN303_H_ + +#include "dmub_dcn20.h" + +/* Registers. */ + +extern const struct dmub_srv_common_regs dmub_srv_dcn303_regs; + +/* Hardware functions. */ + +#endif /* _DMUB_DCN303_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c new file mode 100644 index 000000000000..8c886ece71f6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -0,0 +1,354 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn31.h" + +#include "yellow_carp_offset.h" +#include "dcn/dcn_3_1_2_offset.h" +#include "dcn/dcn_3_1_2_sh_mask.h" + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg +#define CTX dmub +#define REGS dmub->regs_dcn31 +#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = { +#define DMUB_SR(reg) REG_OFFSET_EXP(reg), + { DMUB_DCN31_REGS() }, +#undef DMUB_SR + +#define DMUB_SF(reg, field) FD_MASK(reg, field), + { DMUB_DCN31_FIELDS() }, +#undef DMUB_SF + +#define DMUB_SF(reg, field) FD_SHIFT(reg, field), + { DMUB_DCN31_FIELDS() }, +#undef DMUB_SF +}; + +static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub, + uint64_t *fb_base, + uint64_t *fb_offset) +{ + uint32_t tmp; + + if (dmub->fb_base || dmub->fb_offset) { + *fb_base = dmub->fb_base; + *fb_offset = dmub->fb_offset; + return; + } + + REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); + *fb_base = (uint64_t)tmp << 24; + + REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); + *fb_offset = (uint64_t)tmp << 24; +} + +static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in, + uint64_t fb_base, + uint64_t fb_offset, + union dmub_addr *addr_out) +{ + addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; +} + +void dmub_dcn31_reset(struct dmub_srv *dmub) +{ + union dmub_gpint_data_register cmd; + const uint32_t timeout = 30; + uint32_t in_reset, scratch, i; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); + + if (in_reset == 0) { + cmd.bits.status = 1; + cmd.bits.command_code = DMUB_GPINT__STOP_FW; + cmd.bits.param = 0; + + dmub->hw_funcs.set_gpint(dmub, cmd); + + /** + * Timeout covers both the ACK and the wait + * for remaining work to finish. + * + * This is mostly bound by the PHY disable sequence. + * Each register check will be greater than 1us, so + * don't bother using udelay. + */ + + for (i = 0; i < timeout; ++i) { + if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) + break; + } + + for (i = 0; i < timeout; ++i) { + scratch = dmub->hw_funcs.get_gpint_response(dmub); + if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) + break; + } + + /* Clear the GPINT command manually so we don't reset again. */ + cmd.all = 0; + dmub->hw_funcs.set_gpint(dmub, cmd); + + /* Force reset in case we timed out, DMCUB is likely hung. */ + } + + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); + REG_WRITE(DMCUB_INBOX1_RPTR, 0); + REG_WRITE(DMCUB_INBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); + REG_WRITE(DMCUB_SCRATCH0, 0); +} + +void dmub_dcn31_reset_release(struct dmub_srv *dmub) +{ + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); + REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); + REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); +} + +void dmub_dcn31_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + uint64_t fb_base, fb_offset; + + dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset); + + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + + dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + + dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + + REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, + 0x20); +} + +void dmub_dcn31_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6) +{ + union dmub_addr offset; + + offset = cw3->offset; + + REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); + REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, + DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, + DMCUB_REGION3_CW3_ENABLE, 1); + + offset = cw4->offset; + + REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); + REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, + DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, + DMCUB_REGION3_CW4_ENABLE, 1); + + offset = cw5->offset; + + REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); + REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, + DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, + DMCUB_REGION3_CW5_ENABLE, 1); + + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + + offset = cw6->offset; + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); +} + +void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1) +{ + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); +} + +uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_RPTR); +} + +void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) +{ + REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); +} + +void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1) +{ + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); + REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); +} + +uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub) +{ + /** + * outbox1 wptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + return REG_READ(DMCUB_OUTBOX1_WPTR); +} + +void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + /** + * outbox1 rptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); +} + +bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub) +{ + uint32_t is_hw_init; + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); + + return is_hw_init != 0; +} + +bool dmub_dcn31_is_supported(struct dmub_srv *dmub) +{ + uint32_t supported = 0; + + REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); + + return supported; +} + +void dmub_dcn31_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); +} + +bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + union dmub_gpint_data_register test; + + reg.bits.status = 0; + test.all = REG_READ(DMCUB_GPINT_DATAIN1); + + return test.all == reg.all; +} + +uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH7); +} + +union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + + status.all = REG_READ(DMCUB_SCRATCH0); + return status; +} + +void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) +{ + union dmub_fw_boot_options boot_options = {0}; + + boot_options.bits.z10_disable = params->disable_z10; + + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) +{ + union dmub_fw_boot_options boot_options; + boot_options.all = REG_READ(DMCUB_SCRATCH14); + boot_options.bits.skip_phy_init_panel_sequence = skip; + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0) +{ + REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); + + REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); +} + +uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_OUTBOX0_WPTR); +} + +void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); +} + +uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h new file mode 100644 index 000000000000..2829c3e9a310 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h @@ -0,0 +1,230 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_DCN31_H_ +#define _DMUB_DCN31_H_ + +#include "dmub_dcn20.h" + +struct dmub_srv; + +/* DCN31 register definitions. */ + +#define DMUB_DCN31_REGS() \ + DMUB_SR(DMCUB_CNTL) \ + DMUB_SR(DMCUB_CNTL2) \ + DMUB_SR(DMCUB_SEC_CNTL) \ + DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_INBOX1_SIZE) \ + DMUB_SR(DMCUB_INBOX1_RPTR) \ + DMUB_SR(DMCUB_INBOX1_WPTR) \ + DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX0_SIZE) \ + DMUB_SR(DMCUB_OUTBOX0_RPTR) \ + DMUB_SR(DMCUB_OUTBOX0_WPTR) \ + DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX1_SIZE) \ + DMUB_SR(DMCUB_OUTBOX1_RPTR) \ + DMUB_SR(DMCUB_OUTBOX1_WPTR) \ + DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \ + DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION4_OFFSET) \ + DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION5_OFFSET) \ + DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SR(DMCUB_SCRATCH0) \ + DMUB_SR(DMCUB_SCRATCH1) \ + DMUB_SR(DMCUB_SCRATCH2) \ + DMUB_SR(DMCUB_SCRATCH3) \ + DMUB_SR(DMCUB_SCRATCH4) \ + DMUB_SR(DMCUB_SCRATCH5) \ + DMUB_SR(DMCUB_SCRATCH6) \ + DMUB_SR(DMCUB_SCRATCH7) \ + DMUB_SR(DMCUB_SCRATCH8) \ + DMUB_SR(DMCUB_SCRATCH9) \ + DMUB_SR(DMCUB_SCRATCH10) \ + DMUB_SR(DMCUB_SCRATCH11) \ + DMUB_SR(DMCUB_SCRATCH12) \ + DMUB_SR(DMCUB_SCRATCH13) \ + DMUB_SR(DMCUB_SCRATCH14) \ + DMUB_SR(DMCUB_SCRATCH15) \ + DMUB_SR(DMCUB_GPINT_DATAIN1) \ + DMUB_SR(CC_DC_PIPE_DIS) \ + DMUB_SR(MMHUBBUB_SOFT_RESET) \ + DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ + DMUB_SR(DCN_VM_FB_OFFSET) \ + DMUB_SR(DMCUB_TIMER_CURRENT) + +#define DMUB_DCN31_FIELDS() \ + DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ + DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \ + DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ + DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \ + DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ + DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ + DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ + DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ + DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ + DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) + +struct dmub_srv_dcn31_reg_offset { +#define DMUB_SR(reg) uint32_t reg; + DMUB_DCN31_REGS() +#undef DMUB_SR +}; + +struct dmub_srv_dcn31_reg_shift { +#define DMUB_SF(reg, field) uint8_t reg##__##field; + DMUB_DCN31_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn31_reg_mask { +#define DMUB_SF(reg, field) uint32_t reg##__##field; + DMUB_DCN31_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn31_regs { + const struct dmub_srv_dcn31_reg_offset offset; + const struct dmub_srv_dcn31_reg_mask mask; + const struct dmub_srv_dcn31_reg_shift shift; +}; + +extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs; + +/* Hardware functions. */ + + +void dmub_dcn31_init(struct dmub_srv *dmub); + +void dmub_dcn31_reset(struct dmub_srv *dmub); + +void dmub_dcn31_reset_release(struct dmub_srv *dmub); + +void dmub_dcn31_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1); + +void dmub_dcn31_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6); + +void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + +uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub); + +void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); + +void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1); + +uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub); + +void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub); + +bool dmub_dcn31_is_supported(struct dmub_srv *dmub); + +void dmub_dcn31_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg); + +bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg); + +uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub); + +void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); + +void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); + +union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub); + +void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0); + +uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub); + +void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub); + +#endif /* _DMUB_DCN31_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 1cbb125b4063..fd7e996ab1d7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -30,6 +30,8 @@ #include "dmub_dcn30.h" #include "dmub_dcn301.h" #include "dmub_dcn302.h" +#include "dmub_dcn303.h" +#include "dmub_dcn31.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be @@ -142,6 +144,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) case DMUB_ASIC_DCN30: case DMUB_ASIC_DCN301: case DMUB_ASIC_DCN302: + case DMUB_ASIC_DCN303: dmub->regs = &dmub_srv_dcn20_regs; funcs->reset = dmub_dcn20_reset; @@ -159,6 +162,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; + funcs->get_current_time = dmub_dcn20_get_current_time; // Out mailbox register access functions for RN and above funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; @@ -170,6 +174,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; + funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; + if (asic == DMUB_ASIC_DCN21) { dmub->regs = &dmub_srv_dcn21_regs; @@ -193,6 +199,44 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->backdoor_load = dmub_dcn30_backdoor_load; funcs->setup_windows = dmub_dcn30_setup_windows; } + if (asic == DMUB_ASIC_DCN303) { + dmub->regs = &dmub_srv_dcn303_regs; + + funcs->backdoor_load = dmub_dcn30_backdoor_load; + funcs->setup_windows = dmub_dcn30_setup_windows; + } + break; + + case DMUB_ASIC_DCN31: + funcs->reset = dmub_dcn31_reset; + funcs->reset_release = dmub_dcn31_reset_release; + funcs->backdoor_load = dmub_dcn31_backdoor_load; + funcs->setup_windows = dmub_dcn31_setup_windows; + funcs->setup_mailbox = dmub_dcn31_setup_mailbox; + funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; + funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; + funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; + funcs->is_supported = dmub_dcn31_is_supported; + funcs->is_hw_init = dmub_dcn31_is_hw_init; + funcs->set_gpint = dmub_dcn31_set_gpint; + funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; + funcs->get_gpint_response = dmub_dcn31_get_gpint_response; + funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; + funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; + funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; + //outbox0 call stacks + funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; + funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; + funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; + + if (asic == DMUB_ASIC_DCN31) { + dmub->regs_dcn31 = &dmub_srv_dcn31_regs; + } + + funcs->get_current_time = dmub_dcn31_get_current_time; + break; default: @@ -514,6 +558,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); + /* Report to DMUB what features are supported by current driver */ + if (dmub->hw_funcs.enable_dmub_boot_options) + dmub->hw_funcs.enable_dmub_boot_options(dmub, params); + if (dmub->hw_funcs.reset_release) dmub->hw_funcs.reset_release(dmub); @@ -744,3 +792,11 @@ bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entr return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); } + +bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) +{ + if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) + return false; + dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); + return true; +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c index e6f3bfab33d3..70766d534c9c 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c @@ -35,20 +35,13 @@ */ /** - ***************************************************************************** - * Function: dmub_srv_stat_get_notification + * dmub_srv_stat_get_notification - Retrieves a dmub outbox notification, set up dmub notification + * structure with message information. Also a pending bit if queue + * is having more notifications + * @dmub: dmub srv structure + * @notify: dmub notification structure to be filled up * - * @brief - * Retrieves a dmub outbox notification, set up dmub notification - * structure with message information. Also a pending bit if queue - * is having more notifications - * - * @param [in] dmub: dmub srv structure - * @param [out] pnotify: dmub notification structure to be filled up - * - * @return - * dmub_status - ***************************************************************************** + * Returns: dmub_status */ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, struct dmub_notification *notify) diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 24346f1d7dd0..381c17caace1 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -196,6 +196,7 @@ enum { NV_NAVI14_M_A0 = 20, NV_SIENNA_CICHLID_P_A0 = 40, NV_DIMGREY_CAVEFISH_P_A0 = 60, + NV_BEIGE_GOBY_P_A0 = 70, NV_UNKNOWN = 0xFF }; @@ -204,7 +205,8 @@ enum { #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0)) -#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN)) +#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0)) +#define ASICREV_IS_BEIGE_GOBY_P(eChipRev) ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN)) #define GREEN_SARDINE_A0 0xA1 #ifndef ASICREV_IS_GREEN_SARDINE #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) @@ -222,6 +224,17 @@ enum { #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) #endif +#define FAMILY_YELLOW_CARP 146 + +#define YELLOW_CARP_A0 0x01 +#define YELLOW_CARP_B0 0x02 // TODO: DCN31 - update with correct B0 ID +#define YELLOW_CARP_UNKNOWN 0xFF + +#ifndef ASICREV_IS_YELLOW_CARP +#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN)) +#endif + + /* * ASIC chip ID */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 0d485802a2d0..fe75ec834892 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -54,6 +54,8 @@ enum dce_version { DCN_VERSION_3_0, DCN_VERSION_3_01, DCN_VERSION_3_02, + DCN_VERSION_3_03, + DCN_VERSION_3_1, DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h index 9c55d247227e..7e3240e73c1f 100644 --- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h +++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h @@ -42,8 +42,8 @@ void dal_gpio_destroy( struct gpio **ptr); struct gpio_service *dal_gpio_service_create( - enum dce_version dce_version_major, - enum dce_version dce_version_minor, + enum dce_version dce_version, + enum dce_environment dce_environment, struct dc_context *ctx); struct gpio *dal_gpio_service_create_irq( diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 7392a89e771f..32f5274ed34e 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -68,6 +68,14 @@ enum link_training_result { LINK_TRAINING_LQA_FAIL, /* one of the CR,EQ or symbol lock is dropped */ LINK_TRAINING_LINK_LOSS, + /* Abort link training (because sink unplugged) */ + LINK_TRAINING_ABORT, +}; + +enum lttpr_mode { + LTTPR_MODE_NON_LTTPR, + LTTPR_MODE_TRANSPARENT, + LTTPR_MODE_NON_TRANSPARENT, }; struct link_training_settings { @@ -77,6 +85,7 @@ struct link_training_settings { enum dc_voltage_swing *voltage_swing; enum dc_pre_emphasis *pre_emphasis; enum dc_post_cursor2 *post_cursor2; + bool should_set_fec_ready; uint16_t cr_pattern_time; uint16_t eq_pattern_time; @@ -85,6 +94,7 @@ struct link_training_settings { bool enhanced_framing; bool allow_invalid_msa_timing_param; + enum lttpr_mode lttpr_mode; }; /*TODO: Move this enum test harness*/ diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 3f4f44b44e6a..b99aa232bd8b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -516,7 +516,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr, - struct dc_info_packet *infopacket) + struct dc_info_packet *infopacket, + bool freesync_on_desktop) { /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ infopacket->sb[1] = 0x1A; @@ -542,10 +543,16 @@ static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr, vrr->state != VRR_STATE_UNSUPPORTED) infopacket->sb[6] |= 0x02; - /* PB6 = [Bit 2 = FreeSync Active] */ - if (vrr->state != VRR_STATE_DISABLED && + if (freesync_on_desktop) { + /* PB6 = [Bit 2 = FreeSync Active] */ + if (vrr->state != VRR_STATE_DISABLED && vrr->state != VRR_STATE_UNSUPPORTED) - infopacket->sb[6] |= 0x04; + infopacket->sb[6] |= 0x04; + } else { + if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || + vrr->state == VRR_STATE_ACTIVE_FIXED) + infopacket->sb[6] |= 0x04; + } // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range /* PB7 = FreeSync Minimum refresh rate (Hz) */ @@ -824,13 +831,14 @@ static void build_vrr_infopacket_checksum(unsigned int *payload_size, static void build_vrr_infopacket_v1(enum signal_type signal, const struct mod_vrr_params *vrr, - struct dc_info_packet *infopacket) + struct dc_info_packet *infopacket, + bool freesync_on_desktop) { /* SPD info packet for FreeSync */ unsigned int payload_size = 0; build_vrr_infopacket_header_v1(signal, infopacket, &payload_size); - build_vrr_infopacket_data_v1(vrr, infopacket); + build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); build_vrr_infopacket_checksum(&payload_size, infopacket); infopacket->valid = true; @@ -839,12 +847,13 @@ static void build_vrr_infopacket_v1(enum signal_type signal, static void build_vrr_infopacket_v2(enum signal_type signal, const struct mod_vrr_params *vrr, enum color_transfer_func app_tf, - struct dc_info_packet *infopacket) + struct dc_info_packet *infopacket, + bool freesync_on_desktop) { unsigned int payload_size = 0; build_vrr_infopacket_header_v2(signal, infopacket, &payload_size); - build_vrr_infopacket_data_v1(vrr, infopacket); + build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); build_vrr_infopacket_fs2_data(app_tf, infopacket); @@ -953,12 +962,12 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, #endif break; case PACKET_TYPE_FS_V2: - build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket); + build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop); break; case PACKET_TYPE_VRR: case PACKET_TYPE_FS_V1: default: - build_vrr_infopacket_v1(stream->signal, vrr, infopacket); + build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop); } if (true == pack_sdp_v1_3 && diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c index 68a6481d7f8f..b963226e8af4 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c @@ -260,7 +260,6 @@ enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp, struct mod_hdcp_output output; enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; - memset(hdcp, 0, sizeof(struct mod_hdcp)); memset(&output, 0, sizeof(output)); hdcp->config = *config; HDCP_TOP_INTERFACE_TRACE(hdcp); diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c index 2cbd931363bd..de872e7958b0 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c @@ -29,8 +29,10 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp) { uint64_t n = 0; uint8_t count = 0; + u8 bksv[sizeof(n)] = { }; - memcpy(&n, hdcp->auth.msg.hdcp1.bksv, sizeof(uint64_t)); + memcpy(bksv, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv)); + n = *(uint64_t *)bksv; while (n) { count++; @@ -128,6 +130,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp) static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp) { + /* Avoid device count == 0 to do authentication */ + if (0 == get_device_count(hdcp)) { + return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE; + } + /* Some MST display may choose to report the internal panel as an HDCP RX. * To update this condition with 1(because the immediate repeater's internal * panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c index c1331facdcb4..117c6b45f718 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c @@ -207,6 +207,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp) static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp) { + /* Avoid device count == 0 to do authentication */ + if (0 == get_device_count(hdcp)) { + return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE; + } + /* Some MST display may choose to report the internal panel as an HDCP RX. */ /* To update this condition with 1(because the immediate repeater's internal */ /* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). */ diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c index b0306ed6d6b4..70cb230d8f56 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c @@ -564,7 +564,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp, case D2_A5_AUTHENTICATED: if (input->rxstatus_read == FAIL || input->reauth_request_check == FAIL) { - fail_and_restart_in_ms(0, &status, output); + fail_and_restart_in_ms(100, &status, output); break; } else if (input->link_integrity_check_dp == FAIL) { if (hdcp->connection.hdcp2_retry_count >= 1) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index ee5230ccf3c4..1a0f7c3dc964 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -172,6 +172,8 @@ char *mod_hdcp_status_to_str(int32_t status) return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE"; case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE: return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE"; + case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE: + return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE"; default: return "MOD_HDCP_STATUS_UNKNOWN"; } diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c index 26f96c05e0ec..1b02056bc8bd 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c @@ -44,11 +44,12 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp, in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE; in->process.msg3_desc.msg_size = 0; } -enum mod_hdcp_status mod_hdcp_remove_display_from_topology( + +static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v2( struct mod_hdcp *hdcp, uint8_t index) - { - struct psp_context *psp = hdcp->config.psp.handle; - struct ta_dtm_shared_memory *dtm_cmd; +{ + struct psp_context *psp = hdcp->config.psp.handle; + struct ta_dtm_shared_memory *dtm_cmd; struct mod_hdcp_display *display = get_active_display_at_index(hdcp, index); enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; @@ -79,8 +80,61 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology( mutex_unlock(&psp->dtm_context.mutex); return status; } -enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp, - struct mod_hdcp_display *display) + +static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v3( + struct mod_hdcp *hdcp, uint8_t index) +{ + struct psp_context *psp = hdcp->config.psp.handle; + struct ta_dtm_shared_memory *dtm_cmd; + struct mod_hdcp_display *display = + get_active_display_at_index(hdcp, index); + enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; + + dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf; + + if (!display || !is_display_active(display)) + return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND; + + mutex_lock(&psp->dtm_context.mutex); + + memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); + + dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3; + dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index; + dtm_cmd->dtm_in_message.topology_update_v3.is_active = 0; + dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; + + psp_dtm_invoke(psp, dtm_cmd->cmd_id); + + if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { + status = mod_hdcp_remove_display_from_topology_v2(hdcp, index); + if (status != MOD_HDCP_STATUS_SUCCESS) + display->state = MOD_HDCP_DISPLAY_INACTIVE; + } else { + display->state = MOD_HDCP_DISPLAY_ACTIVE; + HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index); + } + + mutex_unlock(&psp->dtm_context.mutex); + + return status; +} + +enum mod_hdcp_status mod_hdcp_remove_display_from_topology( + struct mod_hdcp *hdcp, uint8_t index) +{ + enum mod_hdcp_status status = MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE; + + if (hdcp->config.psp.caps.dtm_v3_supported) + status = mod_hdcp_remove_display_from_topology_v3(hdcp, index); + else + status = mod_hdcp_remove_display_from_topology_v2(hdcp, index); + + return status; +} + +static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v2( + struct mod_hdcp *hdcp, struct mod_hdcp_display *display) { struct psp_context *psp = hdcp->config.psp.handle; struct ta_dtm_shared_memory *dtm_cmd; @@ -126,6 +180,71 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp, return status; } +static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v3( + struct mod_hdcp *hdcp, struct mod_hdcp_display *display) +{ + struct psp_context *psp = hdcp->config.psp.handle; + struct ta_dtm_shared_memory *dtm_cmd; + struct mod_hdcp_link *link = &hdcp->connection.link; + enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; + + if (!psp->dtm_context.dtm_initialized) { + DRM_INFO("Failed to add display topology, DTM TA is not initialized."); + display->state = MOD_HDCP_DISPLAY_INACTIVE; + return MOD_HDCP_STATUS_FAILURE; + } + + dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf; + + mutex_lock(&psp->dtm_context.mutex); + memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); + + dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3; + dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index; + dtm_cmd->dtm_in_message.topology_update_v3.is_active = 1; + dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller; + dtm_cmd->dtm_in_message.topology_update_v3.ddc_line = link->ddc_line; + dtm_cmd->dtm_in_message.topology_update_v3.link_enc = link->link_enc_idx; + dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx; + if (is_dp_hdcp(hdcp)) + dtm_cmd->dtm_in_message.topology_update_v3.is_assr = link->dp.assr_enabled; + + dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id; + dtm_cmd->dtm_in_message.topology_update_v3.max_hdcp_supported_version = + TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_3; + dtm_cmd->dtm_in_message.topology_update_v3.encoder_type = TA_DTM_ENCODER_TYPE__DIG; + dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; + dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx; + dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational; + + psp_dtm_invoke(psp, dtm_cmd->cmd_id); + + if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { + status = mod_hdcp_add_display_to_topology_v2(hdcp, display); + if (status != MOD_HDCP_STATUS_SUCCESS) + display->state = MOD_HDCP_DISPLAY_INACTIVE; + } else { + HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index); + } + + mutex_unlock(&psp->dtm_context.mutex); + + return status; +} + +enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp, + struct mod_hdcp_display *display) +{ + enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; + + if (hdcp->config.psp.caps.dtm_v3_supported) + status = mod_hdcp_add_display_to_topology_v3(hdcp, display); + else + status = mod_hdcp_add_display_to_topology_v2(hdcp, display); + + return status; +} + enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp) { @@ -371,19 +490,6 @@ enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp) return status; } -enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp, - enum mod_hdcp_encryption_status *encryption_status) -{ - *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; - - if (mod_hdcp_hdcp1_link_maintenance(hdcp) != MOD_HDCP_STATUS_SUCCESS) - return MOD_HDCP_STATUS_FAILURE; - - *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON; - - return MOD_HDCP_STATUS_SUCCESS; -} - enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp) { struct psp_context *psp = hdcp->config.psp.handle; diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h index 1a663dbbf810..2937b4b61461 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h @@ -44,7 +44,8 @@ enum bgd_security_hdcp2_content_type { enum ta_dtm_command { TA_DTM_COMMAND__UNUSED_1 = 1, TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2, - TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE + TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE, + TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3 }; /* DTM related enumerations */ @@ -86,6 +87,32 @@ struct ta_dtm_topology_update_input_v2 { uint32_t max_hdcp_supported_version; }; +/* For security reason/HW may change value, these encoder type enum values are not HW register values */ +/* Security code will check real HW register values and these SW enum values */ +enum ta_dtm_encoder_type { + TA_DTM_ENCODER_TYPE__INVALID = 0, + TA_DTM_ENCODER_TYPE__DIG = 0x10 +}; + +struct ta_dtm_topology_update_input_v3 { + /* display handle is unique across the driver and is used to identify a display */ + /* for all security interfaces which reference displays such as HDCP */ + /* link_hdcp_cap means link is HDCP-capable for audio HDCP capable property(informational), not for other logic(e.g. Crossbar) */ + uint32_t display_handle; + uint32_t is_active; + uint32_t is_miracast; + uint32_t controller; + uint32_t ddc_line; + uint32_t link_enc; + uint32_t stream_enc; + uint32_t dp_mst_vcid; + uint32_t is_assr; + uint32_t max_hdcp_supported_version; + enum ta_dtm_encoder_type encoder_type; + uint32_t phy_id; + uint32_t link_hdcp_cap; +}; + struct ta_dtm_topology_assr_enable { uint32_t display_topology_dig_be_index; }; @@ -99,6 +126,7 @@ struct ta_dtm_topology_assr_enable { union ta_dtm_cmd_input { struct ta_dtm_topology_update_input_v2 topology_update_v2; struct ta_dtm_topology_assr_enable topology_assr_enable; + struct ta_dtm_topology_update_input_v3 topology_update_v3; }; union ta_dtm_cmd_output { @@ -278,7 +306,8 @@ enum ta_hdcp2_version { TA_HDCP2_VERSION_UNKNOWN = 0, TA_HDCP2_VERSION_2_0 = 20, TA_HDCP2_VERSION_2_1 = 21, - TA_HDCP2_VERSION_2_2 = 22 + TA_HDCP2_VERSION_2_2 = 22, + TA_HDCP2_VERSION_2_3 = 23, }; /* input/output structures for HDCP commands */ diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index acbeada5215b..c590493fd293 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -97,6 +97,7 @@ enum mod_hdcp_status { MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST, MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, + MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, }; struct mod_hdcp_displayport { @@ -120,6 +121,11 @@ enum mod_hdcp_display_state { MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED }; +struct mod_hdcp_psp_caps { + uint8_t dtm_v3_supported; + uint8_t opm_state_query_supported; +}; + enum mod_hdcp_display_disable_option { MOD_HDCP_DISPLAY_NOT_DISABLE = 0, MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION, @@ -152,6 +158,7 @@ struct mod_hdcp_ddc { struct mod_hdcp_psp { void *handle; void *funcs; + struct mod_hdcp_psp_caps caps; }; struct mod_hdcp_display_adjustment { @@ -227,6 +234,7 @@ struct mod_hdcp_display { uint8_t index; uint8_t controller; uint8_t dig_fe; + uint8_t stream_enc_idx; union { uint8_t vc_id; }; @@ -239,6 +247,9 @@ struct mod_hdcp_link { enum mod_hdcp_operation_mode mode; uint8_t dig_be; uint8_t ddc_line; + uint8_t link_enc_idx; + uint8_t phy_idx; + uint8_t hdcp_supported_informational; union { struct mod_hdcp_displayport dp; struct mod_hdcp_hdmi hdmi; diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 6270ecbd2438..2b00f334e93d 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -87,19 +87,19 @@ struct abm_parameters { }; static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blStart blRed - {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xCCCC, 0xCCCC}, - {0xde, 0x85, 0x20, 0x00, 0xff, 0x90, 0xa8, 0x40, 0xdf, 0xCCCC, 0xCCCC}, - {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xCCCC, 0xCCCC}, - {0x82, 0x40, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC}, +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc}, + {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc}, + {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999}, + {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333}, }; static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blStart blRed - {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC}, - {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC}, - {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC}, - {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC}, +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, }; static const struct abm_parameters * const abm_settings[] = { @@ -660,7 +660,8 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram } bool dmub_init_abm_config(struct resource_pool *res_pool, - struct dmcu_iram_parameters params) + struct dmcu_iram_parameters params, + unsigned int inst) { struct iram_table_v_2_2 ram_table; struct abm_config_table config; @@ -669,7 +670,7 @@ bool dmub_init_abm_config(struct resource_pool *res_pool, uint32_t i, j = 0; #if defined(CONFIG_DRM_AMD_DC_DCN) - if (res_pool->abm == NULL && res_pool->multiple_abms[0] == NULL) + if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) return false; #else if (res_pool->abm == NULL) @@ -728,13 +729,13 @@ bool dmub_init_abm_config(struct resource_pool *res_pool, config.min_abm_backlight = ram_table.min_abm_backlight; #if defined(CONFIG_DRM_AMD_DC_DCN) - if (res_pool->multiple_abms[0]) - result = res_pool->multiple_abms[0]->funcs->init_abm_config( - res_pool->multiple_abms[0], (char *)(&config), sizeof(struct abm_config_table)); - else + if (res_pool->multiple_abms[inst]) { + result = res_pool->multiple_abms[inst]->funcs->init_abm_config( + res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); + } else #endif result = res_pool->abm->funcs->init_abm_config( - res_pool->abm, (char *)(&config), sizeof(struct abm_config_table)); + res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); return result; } diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 6f2eecce6baa..2a9f8e2d8080 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -49,6 +49,7 @@ struct dmcu_iram_parameters { bool dmcu_load_iram(struct dmcu *dmcu, struct dmcu_iram_parameters params); bool dmub_init_abm_config(struct resource_pool *res_pool, - struct dmcu_iram_parameters params); + struct dmcu_iram_parameters params, + unsigned int inst); #endif /* MODULES_POWER_POWER_HELPERS_H_ */ diff --git a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h index 644ffec2b0ce..cdd426b41c20 100644 --- a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h +++ b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h @@ -30,7 +30,7 @@ struct IP_BASE_INSTANCE { struct IP_BASE { struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; -}; +} __maybe_unused; static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0 } }, diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h index c72cbfe8f684..2d089d30518f 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -103,6 +103,13 @@ struct atcs_pref_req_output { u8 ret_val; /* return value */ } __packed; +struct atcs_pwr_shift_input { + u16 size; /* structure size in bytes (includes size field) */ + u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ + u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */ + u8 drv_state; /* 0 = operational, 1 = not operational */ +} __packed; + /* AMD hw uses four ACPI control methods: * 1. ATIF * ARG0: (ACPI_INTEGER) function code @@ -418,6 +425,7 @@ struct atcs_pref_req_output { # define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1) # define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2) # define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3) +# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) #define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1 /* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE * ARG1: none @@ -472,4 +480,14 @@ struct atcs_pref_req_output { * BYTE - number of active lanes */ +#define ATCS_FUNCTION_POWER_SHIFT_CONTROL 0x8 +/* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) + * BYTE - Device ACPI state + * BYTE - Driver state + * OUTPUT: none + */ + #endif diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 9ab706cd07ff..332b0df53e52 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -246,6 +246,7 @@ enum amd_dpm_forced_level; * @late_init: sets up late driver/hw state (post hw_init) - Optional * @sw_init: sets up driver state, does not configure hw * @sw_fini: tears down driver state, does not configure hw + * @early_fini: tears down stuff before dev detached from driver * @hw_init: sets up the hw state * @hw_fini: tears down the hw state * @late_fini: final cleanup @@ -274,6 +275,7 @@ struct amd_ip_funcs { int (*late_init)(void *handle); int (*sw_init)(void *handle); int (*sw_fini)(void *handle); + int (*early_fini)(void *handle); int (*hw_init)(void *handle); int (*hw_fini)(void *handle); void (*late_fini)(void *handle); diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h index 2a622c13817b..59155007c186 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h @@ -29292,6 +29292,7 @@ #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L @@ -34431,6 +34432,7 @@ #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h new file mode 100644 index 000000000000..daa8130636f0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h @@ -0,0 +1,8427 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _dcn_3_0_3_OFFSET_HEADER +#define _dcn_3_0_3_OFFSET_HEADER + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +// base address: 0x0 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 +#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_RENDER_CONTROL 0x0000 +#define mmVGA_RENDER_CONTROL_BASE_IDX 1 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define mmVGA_MODE_CONTROL 0x0002 +#define mmVGA_MODE_CONTROL_BASE_IDX 1 +#define mmVGA_SURFACE_PITCH_SELECT 0x0003 +#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 +#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define mmVGA_HDP_CONTROL 0x000a +#define mmVGA_HDP_CONTROL_BASE_IDX 1 +#define mmVGA_CACHE_CONTROL 0x000b +#define mmVGA_CACHE_CONTROL_BASE_IDX 1 +#define mmD1VGA_CONTROL 0x000c +#define mmD1VGA_CONTROL_BASE_IDX 1 +#define mmD2VGA_CONTROL 0x000e +#define mmD2VGA_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS 0x0010 +#define mmVGA_STATUS_BASE_IDX 1 +#define mmVGA_INTERRUPT_CONTROL 0x0011 +#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS_CLEAR 0x0012 +#define mmVGA_STATUS_CLEAR_BASE_IDX 1 +#define mmVGA_INTERRUPT_STATUS 0x0013 +#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define mmVGA_MAIN_CONTROL 0x0014 +#define mmVGA_MAIN_CONTROL_BASE_IDX 1 +#define mmVGA_TEST_CONTROL 0x0015 +#define mmVGA_TEST_CONTROL_BASE_IDX 1 +#define mmVGA_QOS_CTRL 0x0018 +#define mmVGA_QOS_CTRL_BASE_IDX 1 +#define mmCRTC8_IDX 0x002d +#define mmCRTC8_IDX_BASE_IDX 1 +#define mmCRTC8_DATA 0x002d +#define mmCRTC8_DATA_BASE_IDX 1 +#define mmGENFC_WT 0x002e +#define mmGENFC_WT_BASE_IDX 1 +#define mmGENS1 0x002e +#define mmGENS1_BASE_IDX 1 +#define mmATTRDW 0x0030 +#define mmATTRDW_BASE_IDX 1 +#define mmATTRX 0x0030 +#define mmATTRX_BASE_IDX 1 +#define mmATTRDR 0x0030 +#define mmATTRDR_BASE_IDX 1 +#define mmGENMO_WT 0x0030 +#define mmGENMO_WT_BASE_IDX 1 +#define mmGENS0 0x0030 +#define mmGENS0_BASE_IDX 1 +#define mmGENENB 0x0030 +#define mmGENENB_BASE_IDX 1 +#define mmSEQ8_IDX 0x0031 +#define mmSEQ8_IDX_BASE_IDX 1 +#define mmSEQ8_DATA 0x0031 +#define mmSEQ8_DATA_BASE_IDX 1 +#define mmDAC_MASK 0x0031 +#define mmDAC_MASK_BASE_IDX 1 +#define mmDAC_R_INDEX 0x0031 +#define mmDAC_R_INDEX_BASE_IDX 1 +#define mmDAC_W_INDEX 0x0032 +#define mmDAC_W_INDEX_BASE_IDX 1 +#define mmDAC_DATA 0x0032 +#define mmDAC_DATA_BASE_IDX 1 +#define mmGENFC_RD 0x0032 +#define mmGENFC_RD_BASE_IDX 1 +#define mmGENMO_RD 0x0033 +#define mmGENMO_RD_BASE_IDX 1 +#define mmGRPH8_IDX 0x0033 +#define mmGRPH8_IDX_BASE_IDX 1 +#define mmGRPH8_DATA 0x0033 +#define mmGRPH8_DATA_BASE_IDX 1 +#define mmCRTC8_IDX_1 0x0035 +#define mmCRTC8_IDX_1_BASE_IDX 1 +#define mmCRTC8_DATA_1 0x0035 +#define mmCRTC8_DATA_1_BASE_IDX 1 +#define mmGENFC_WT_1 0x0036 +#define mmGENFC_WT_1_BASE_IDX 1 +#define mmGENS1_1 0x0036 +#define mmGENS1_1_BASE_IDX 1 +#define mmD3VGA_CONTROL 0x0038 +#define mmD3VGA_CONTROL_BASE_IDX 1 +#define mmD4VGA_CONTROL 0x0039 +#define mmD4VGA_CONTROL_BASE_IDX 1 +#define mmD5VGA_CONTROL 0x003a +#define mmD5VGA_CONTROL_BASE_IDX 1 +#define mmD6VGA_CONTROL 0x003b +#define mmD6VGA_CONTROL_BASE_IDX 1 +#define mmVGA_SOURCE_SELECT 0x003c +#define mmVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDP_DTO_DBUF_EN 0x0044 +#define mmDP_DTO_DBUF_EN_BASE_IDX 1 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmREFCLK_CNTL 0x0049 +#define mmREFCLK_CNTL_BASE_IDX 1 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL2 0x004e +#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define mmDCCG_DS_DTO_INCR 0x0053 +#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 +#define mmDCCG_DS_DTO_MODULO 0x0054 +#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_DS_CNTL 0x0055 +#define mmDCCG_DS_CNTL_BASE_IDX 1 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define mmDPREFCLK_CNTL 0x0058 +#define mmDPREFCLK_CNTL_BASE_IDX 1 +#define mmDCE_VERSION 0x005e +#define mmDCE_VERSION_BASE_IDX 1 +#define mmDCCG_GTC_CNTL 0x0060 +#define mmDCCG_GTC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_DTO_INCR 0x0061 +#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define mmDCCG_GTC_DTO_MODULO 0x0062 +#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_GTC_CURRENT 0x0063 +#define mmDCCG_GTC_CURRENT_BASE_IDX 1 +#define mmDSCCLK0_DTO_PARAM 0x006c +#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define mmDSCCLK1_DTO_PARAM 0x006d +#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define mmMILLISECOND_TIME_BASE_DIV 0x0070 +#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL 0x0073 +#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL 0x0074 +#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CAC_STATUS 0x0077 +#define mmDCCG_CAC_STATUS_BASE_IDX 1 +#define mmMICROSECOND_TIME_BASE_DIV 0x007b +#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL2 0x007c +#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_DISP_CNTL_REG 0x007f +#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define mmOTG0_PIXEL_RATE_CNTL 0x0080 +#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO0_PHASE 0x0081 +#define mmDP_DTO0_PHASE_BASE_IDX 1 +#define mmDP_DTO0_MODULO 0x0082 +#define mmDP_DTO0_MODULO_BASE_IDX 1 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG1_PIXEL_RATE_CNTL 0x0084 +#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO1_PHASE 0x0085 +#define mmDP_DTO1_PHASE_BASE_IDX 1 +#define mmDP_DTO1_MODULO 0x0086 +#define mmDP_DTO1_MODULO_BASE_IDX 1 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDPPCLK0_DTO_PARAM 0x0099 +#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define mmDPPCLK1_DTO_PARAM 0x009a +#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define mmDCCG_CAC_STATUS2 0x009f +#define mmDCCG_CAC_STATUS2_BASE_IDX 1 +#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 +#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 +#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define mmDCCG_SOFT_RESET 0x00a6 +#define mmDCCG_SOFT_RESET_BASE_IDX 1 +#define mmDSCCLK_DTO_CTRL 0x00a7 +#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab +#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac +#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad +#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae +#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_MODULE 0x00af +#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define mmDPPCLK_DTO_CTRL 0x00b6 +#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 +#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define mmFORCE_SYMCLK_DISABLE 0x00ba +#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define mmPHYASYMCLK_CLOCK_CNTL 0x0052 +#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define mmDENTIST_DISPCLK_CNTL 0x0064 +#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 +#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_HI 0x0007 +#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_LOW 0x0008 +#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x00be +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x00bf +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x00c0 +#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL 0x00c1 +#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL2 0x00c2 +#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x00c3 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x00c4 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_HI 0x00c5 +#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_LOW 0x00c6 +#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define mmCC_DC_PIPE_DIS 0x00ca +#define mmCC_DC_PIPE_DIS_BASE_IDX 2 +#define mmDMU_CLK_CNTL 0x00cb +#define mmDMU_CLK_CNTL_BASE_IDX 2 +#define mmDMU_MEM_PWR_CNTL 0x00cc +#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd +#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define mmSMU_INTERRUPT_CONTROL 0x00ce +#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +// base address: 0x0 +#define mmDMCU_CTRL 0x00da +#define mmDMCU_CTRL_BASE_IDX 2 +#define mmDMCU_STATUS 0x00db +#define mmDMCU_STATUS_BASE_IDX 2 +#define mmDMCU_PC_START_ADDR 0x00dc +#define mmDMCU_PC_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_START_ADDR 0x00dd +#define mmDMCU_FW_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_END_ADDR 0x00de +#define mmDMCU_FW_END_ADDR_BASE_IDX 2 +#define mmDMCU_FW_ISR_START_ADDR 0x00df +#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_CS_HI 0x00e0 +#define mmDMCU_FW_CS_HI_BASE_IDX 2 +#define mmDMCU_FW_CS_LO 0x00e1 +#define mmDMCU_FW_CS_LO_BASE_IDX 2 +#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 +#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_CTRL 0x00e3 +#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_DATA 0x00e4 +#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_ERAM_RD_CTRL 0x00e5 +#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_RD_DATA 0x00e6 +#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_WR_CTRL 0x00e7 +#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_WR_DATA 0x00e8 +#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_RD_CTRL 0x00e9 +#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_RD_DATA 0x00ea +#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_EVENT_TRIGGER 0x00eb +#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec +#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS 0x00ee +#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_1 0x00ef +#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 +#define mmDC_DMCU_SCRATCH 0x00f5 +#define mmDC_DMCU_SCRATCH_BASE_IDX 2 +#define mmDMCU_INT_CNT 0x00f6 +#define mmDMCU_INT_CNT_BASE_IDX 2 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 +#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 +#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG1 0x00f9 +#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG2 0x00fa +#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG3 0x00fb +#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 +#define mmMASTER_COMM_CMD_REG 0x00fc +#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 +#define mmMASTER_COMM_CNTL_REG 0x00fd +#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG1 0x00fe +#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG2 0x00ff +#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG3 0x0100 +#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 +#define mmSLAVE_COMM_CMD_REG 0x0101 +#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 +#define mmSLAVE_COMM_CNTL_REG 0x0102 +#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 +#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 +#define mmDMCU_INT_CNT_CONTINUE 0x011c +#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_2 0x011e +#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ 0x0128 +#define mmDC_GPU_TIMER_READ_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ_CNTL 0x0129 +#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS 0x012a +#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define mmDCCG_INTERRUPT_DEST 0x0148 +#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define mmDMU_INTERRUPT_DEST 0x0149 +#define mmDMU_INTERRUPT_DEST_BASE_IDX 2 +#define mmDMU_INTERRUPT_DEST2 0x014a +#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define mmDCPG_INTERRUPT_DEST 0x014b +#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCPG_INTERRUPT_DEST2 0x014c +#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define mmMMHUBBUB_INTERRUPT_DEST 0x014d +#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define mmWB_INTERRUPT_DEST 0x014e +#define mmWB_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_INTERRUPT_DEST 0x014f +#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_INTERRUPT_DEST2 0x0151 +#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define mmMPC_INTERRUPT_DEST 0x0153 +#define mmMPC_INTERRUPT_DEST_BASE_IDX 2 +#define mmOPP_INTERRUPT_DEST 0x0154 +#define mmOPP_INTERRUPT_DEST_BASE_IDX 2 +#define mmOPTC_INTERRUPT_DEST 0x0155 +#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG0_INTERRUPT_DEST 0x0156 +#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG1_INTERRUPT_DEST 0x0157 +#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG2_INTERRUPT_DEST 0x0158 +#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG3_INTERRUPT_DEST 0x0159 +#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG4_INTERRUPT_DEST 0x015a +#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG5_INTERRUPT_DEST 0x015b +#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define mmDIG_INTERRUPT_DEST 0x015c +#define mmDIG_INTERRUPT_DEST_BASE_IDX 2 +#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define mmDIO_INTERRUPT_DEST 0x015f +#define mmDIO_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCIO_INTERRUPT_DEST 0x0160 +#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define mmHPD_INTERRUPT_DEST 0x0161 +#define mmHPD_INTERRUPT_DEST_BASE_IDX 2 +#define mmAZ_INTERRUPT_DEST 0x0162 +#define mmAZ_INTERRUPT_DEST_BASE_IDX 2 +#define mmAUX_INTERRUPT_DEST 0x0163 +#define mmAUX_INTERRUPT_DEST_BASE_IDX 2 +#define mmDSC_INTERRUPT_DEST 0x0164 +#define mmDSC_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +// base address: 0x0 +#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a +#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define mmRBBMIF_TIMEOUT 0x017f +#define mmRBBMIF_TIMEOUT_BASE_IDX 2 +#define mmRBBMIF_STATUS 0x0180 +#define mmRBBMIF_STATUS_BASE_IDX 2 +#define mmRBBMIF_STATUS_2 0x0181 +#define mmRBBMIF_STATUS_2_BASE_IDX 2 +#define mmRBBMIF_INT_STATUS 0x0182 +#define mmRBBMIF_INT_STATUS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS 0x0183 +#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS_2 0x0184 +#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define mmRBBMIF_STATUS_FLAG 0x0185 +#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define mmDMCUB_REGION0_OFFSET 0x018e +#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f +#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION1_OFFSET 0x0190 +#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION2_OFFSET 0x0192 +#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION4_OFFSET 0x0196 +#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION5_OFFSET 0x0198 +#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION6_OFFSET 0x019a +#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b +#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION7_OFFSET 0x019c +#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d +#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e +#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f +#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb +#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd +#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf +#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_ENABLE 0x01c5 +#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_ACK 0x01c6 +#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_STATUS 0x01c7 +#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_TYPE 0x01c8 +#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_SEC_CNTL 0x01ce +#define mmDMCUB_SEC_CNTL_BASE_IDX 2 +#define mmDMCUB_MEM_CNTL 0x01cf +#define mmDMCUB_MEM_CNTL_BASE_IDX 2 +#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_INBOX0_SIZE 0x01d1 +#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define mmDMCUB_INBOX0_WPTR 0x01d2 +#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define mmDMCUB_INBOX0_RPTR 0x01d3 +#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_INBOX1_SIZE 0x01d5 +#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define mmDMCUB_INBOX1_WPTR 0x01d6 +#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define mmDMCUB_INBOX1_RPTR 0x01d7 +#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_SIZE 0x01d9 +#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_WPTR 0x01da +#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_RPTR 0x01db +#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_SIZE 0x01dd +#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_WPTR 0x01de +#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_RPTR 0x01df +#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define mmDMCUB_TIMER_TRIGGER0 0x01e0 +#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define mmDMCUB_TIMER_TRIGGER1 0x01e1 +#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define mmDMCUB_TIMER_WINDOW 0x01e2 +#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define mmDMCUB_SCRATCH0 0x01e3 +#define mmDMCUB_SCRATCH0_BASE_IDX 2 +#define mmDMCUB_SCRATCH1 0x01e4 +#define mmDMCUB_SCRATCH1_BASE_IDX 2 +#define mmDMCUB_SCRATCH2 0x01e5 +#define mmDMCUB_SCRATCH2_BASE_IDX 2 +#define mmDMCUB_SCRATCH3 0x01e6 +#define mmDMCUB_SCRATCH3_BASE_IDX 2 +#define mmDMCUB_SCRATCH4 0x01e7 +#define mmDMCUB_SCRATCH4_BASE_IDX 2 +#define mmDMCUB_SCRATCH5 0x01e8 +#define mmDMCUB_SCRATCH5_BASE_IDX 2 +#define mmDMCUB_SCRATCH6 0x01e9 +#define mmDMCUB_SCRATCH6_BASE_IDX 2 +#define mmDMCUB_SCRATCH7 0x01ea +#define mmDMCUB_SCRATCH7_BASE_IDX 2 +#define mmDMCUB_SCRATCH8 0x01eb +#define mmDMCUB_SCRATCH8_BASE_IDX 2 +#define mmDMCUB_SCRATCH9 0x01ec +#define mmDMCUB_SCRATCH9_BASE_IDX 2 +#define mmDMCUB_SCRATCH10 0x01ed +#define mmDMCUB_SCRATCH10_BASE_IDX 2 +#define mmDMCUB_SCRATCH11 0x01ee +#define mmDMCUB_SCRATCH11_BASE_IDX 2 +#define mmDMCUB_SCRATCH12 0x01ef +#define mmDMCUB_SCRATCH12_BASE_IDX 2 +#define mmDMCUB_SCRATCH13 0x01f0 +#define mmDMCUB_SCRATCH13_BASE_IDX 2 +#define mmDMCUB_SCRATCH14 0x01f1 +#define mmDMCUB_SCRATCH14_BASE_IDX 2 +#define mmDMCUB_SCRATCH15 0x01f2 +#define mmDMCUB_SCRATCH15_BASE_IDX 2 +#define mmDMCUB_CNTL 0x01f6 +#define mmDMCUB_CNTL_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAIN0 0x01f7 +#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAIN1 0x01f8 +#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAOUT 0x01f9 +#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define mmDMCUB_MEM_PWR_CNTL 0x01fc +#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDMCUB_TIMER_CURRENT 0x01fd +#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define mmDMCUB_PROC_ID 0x01ff +#define mmDMCUB_PROC_ID_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_BUFMGR_STATUS 0x0274 +#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB_BUF_PITCH 0x0275 +#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_STATUS 0x0276 +#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_STATUS2 0x0277 +#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_STATUS 0x0278 +#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_STATUS2 0x0279 +#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_STATUS 0x027a +#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_STATUS2 0x027b +#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_STATUS 0x027c +#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_STATUS2 0x027d +#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e +#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_SCLK_CHANGE 0x027f +#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_ADDR_C 0x0284 +#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_ADDR_C 0x0288 +#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a +#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_ADDR_C 0x028c +#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e +#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_ADDR_C 0x0290 +#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMULTI_LEVEL_QOS_CTRL 0x0297 +#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 +#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 +#define mmMCIF_WB_VMID_CONTROL 0x02a8 +#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define mmMCIF_WB_MIN_TTO 0x02a9 +#define mmMCIF_WB_MIN_TTO_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB_WATERMARK 0x02ab +#define mmMCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac +#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define mmMMHUBBUB_MIN_TTO 0x02b1 +#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define mmWBIF_SMU_WM_CONTROL 0x0333 +#define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define mmWBIF0_MISC_CTRL 0x0334 +#define mmWBIF0_MISC_CTRL_BASE_IDX 2 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmVGA_SRC_SPLIT_CNTL 0x033d +#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e +#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f +#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_CLOCK_CNTL 0x0340 +#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_SOFT_RESET 0x0341 +#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define mmDMU_IF_ERR_STATUS 0x0345 +#define mmDMU_IF_ERR_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346 +#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 +#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define mmMCIF_CONTROL 0x034a +#define mmMCIF_CONTROL_BASE_IDX 2 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b +#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x0352 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x0353 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x0354 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL 0x0355 +#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL2 0x0356 +#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x0357 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x0358 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_HI 0x0359 +#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_LOW 0x035a +#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define mmAZ_CLOCK_CNTL 0x0372 +#define mmAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x037a +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x037b +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x037c +#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL 0x037d +#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x037e +#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x037f +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0380 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_HI 0x0381 +#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_LOW 0x0382 +#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO 0x03c3 +#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define mmAZALIA_SOCCLK_CONTROL 0x03c5 +#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 +#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 +#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define mmAZALIA_CORB_DMA_CONTROL 0x03ca +#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd +#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL0 0x03e3 +#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL1 0x03e4 +#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL2 0x03e5 +#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL3 0x03e6 +#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC0_RESULT 0x03e7 +#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL0 0x03e8 +#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL1 0x03e9 +#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL2 0x03ea +#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL3 0x03eb +#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC1_RESULT 0x03ec +#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_CTRL 0x03ee +#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_STATUS 0x03ef +#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +// base address: 0x0 +#define mmDCHUBBUB_SDPIF_CFG0 0x048f +#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define mmVM_REQUEST_PHYSICAL 0x0490 +#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 +#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 +#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define mmDCN_VM_FB_LOCATION_BASE 0x0493 +#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define mmDCN_VM_FB_LOCATION_TOP 0x0494 +#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define mmDCN_VM_FB_OFFSET 0x0495 +#define mmDCN_VM_FB_OFFSET_BASE_IDX 2 +#define mmDCN_VM_AGP_BOT 0x0496 +#define mmDCN_VM_AGP_BOT_BASE_IDX 2 +#define mmDCN_VM_AGP_TOP 0x0497 +#define mmDCN_VM_AGP_TOP_BASE_IDX 2 +#define mmDCN_VM_AGP_BASE 0x0498 +#define mmDCN_VM_AGP_BASE_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a +#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b +#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_CFG1 0x04bf +#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_CFG2 0x04c0 +#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +// base address: 0x0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf +#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_CRC_CTRL 0x04f1 +#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 +#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 +#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 +#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 +#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +// base address: 0x0 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 +#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 +#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 +#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 +#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 +#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 +#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 +#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 +#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 +#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 +#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define mmVTG0_CONTROL 0x0528 +#define mmVTG0_CONTROL_BASE_IDX 2 +#define mmVTG1_CONTROL 0x0529 +#define mmVTG1_CONTROL_BASE_IDX 2 +#define mmDCHUBBUB_SOFT_RESET 0x052e +#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define mmDCHUBBUB_CLOCK_CNTL 0x052f +#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmDCFCLK_CNTL 0x0530 +#define mmDCFCLK_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 +#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define mmDCHUBBUB_CTRL_STATUS 0x0534 +#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c +#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d +#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e +#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define mmFMON_CTRL 0x0548 +#define mmFMON_CTRL_BASE_IDX 2 +#define mmFMON_CTRL_1 0x0548 +#define mmFMON_CTRL_1_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x054d +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x054e +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x054f +#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL 0x0550 +#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL2 0x0551 +#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0552 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0553 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_HI 0x0554 +#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_LOW 0x0555 +#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define mmDCN_VM_CONTEXT0_CNTL 0x0559 +#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_CNTL 0x0560 +#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_CNTL 0x0567 +#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_CNTL 0x056e +#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_CNTL 0x0575 +#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_CNTL 0x057c +#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_CNTL 0x0583 +#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_CNTL 0x058a +#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_CNTL 0x0591 +#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_CNTL 0x0598 +#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_CNTL 0x059f +#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_CNTL 0x05a6 +#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_CNTL 0x05ad +#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_CNTL 0x05b4 +#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_CNTL 0x05bb +#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_CNTL 0x05c2 +#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmDCN_VM_FAULT_CNTL 0x05cb +#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define mmDCN_VM_FAULT_STATUS 0x05cc +#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd +#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce +#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_CNTL 0x05f3 +#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 +#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 +#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 +#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629 +#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a +#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 +#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644 +#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645 +#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ0_DST_DIMENSIONS 0x0646 +#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647 +#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648 +#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 +#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a +#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b +#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c +#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d +#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e +#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f +#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650 +#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651 +#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652 +#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653 +#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654 +#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655 +#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656 +#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657 +#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658 +#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659 +#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b +#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c +#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e +#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 +#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 +#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665 +#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666 +#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667 +#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668 +#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define mmHUBPRET0_HUBPRET_CONTROL 0x066c +#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 +#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SIZE 0x067b +#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_POSITION 0x067c +#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_CNTL 0x0684 +#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_STATUS 0x0686 +#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a74 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x069d +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x069e +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x069f +#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL 0x06a0 +#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL2 0x06a1 +#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x06a2 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x06a3 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_HI 0x06a4 +#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_LOW 0x06a5 +#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_CNTL 0x06cf +#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 +#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 +#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 +#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705 +#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706 +#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 +#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720 +#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721 +#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ1_DST_DIMENSIONS 0x0722 +#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723 +#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724 +#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 +#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a +#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b +#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c +#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d +#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e +#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f +#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730 +#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731 +#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732 +#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733 +#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734 +#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735 +#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737 +#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738 +#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a +#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f +#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 +#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741 +#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742 +#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743 +#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744 +#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define mmHUBPRET1_HUBPRET_CONTROL 0x0748 +#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 +#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SIZE 0x0757 +#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_POSITION 0x0758 +#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_CNTL 0x0760 +#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_STATUS 0x0762 +#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1de4 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0779 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x077a +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x077b +#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL 0x077c +#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL2 0x077d +#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x077e +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x077f +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_HI 0x0780 +#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_LOW 0x0781 +#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 +#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 +#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca +#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 +#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 +#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 +#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 +#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 +#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 +#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 +#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda +#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb +#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd +#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_DEALPHA 0x0cde +#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf +#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 +#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 +#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 +#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 +#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 +#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 +#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 +#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 +#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 +#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 +#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea +#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb +#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec +#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_DEGAM 0x0ced +#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define mmCNVC_CFG0_PRE_REALPHA 0x0cee +#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 +#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 +#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 +#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL0_SCL_MODE 0x0cfb +#define mmDSCL0_SCL_MODE_BASE_IDX 2 +#define mmDSCL0_SCL_TAP_CONTROL 0x0cfc +#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_CONTROL 0x0cfd +#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe +#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL0_SCL_BLACK_COLOR 0x0d0a +#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define mmDSCL0_DSCL_UPDATE 0x0d0b +#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL0_DSCL_AUTOCAL 0x0d0c +#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL0_OTG_H_BLANK 0x0d0f +#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL0_OTG_V_BLANK 0x0d10 +#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL0_RECOUT_START 0x0d11 +#define mmDSCL0_RECOUT_START_BASE_IDX 2 +#define mmDSCL0_RECOUT_SIZE 0x0d12 +#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL0_MPC_SIZE 0x0d13 +#define mmDSCL0_MPC_SIZE_BASE_IDX 2 +#define mmDSCL0_LB_DATA_FORMAT 0x0d14 +#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL0_LB_MEMORY_CTRL 0x0d15 +#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL0_LB_V_COUNTER 0x0d16 +#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 +#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 +#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL0_OBUF_CONTROL 0x0d19 +#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a +#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define mmCM0_CM_CONTROL 0x0d20 +#define mmCM0_CM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_CONTROL 0x0d21 +#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C11_C12 0x0d22 +#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C13_C14 0x0d23 +#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C21_C22 0x0d24 +#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C23_C24 0x0d25 +#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C31_C32 0x0d26 +#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_C33_C34 0x0d27 +#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28 +#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29 +#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a +#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b +#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c +#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d +#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e +#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f +#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 +#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 +#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 +#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 +#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 +#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 +#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 +#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 +#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 +#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 +#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a +#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM0_CM_BIAS_CR_R 0x0d3b +#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c +#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_CONTROL 0x0d3d +#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e +#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f +#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 +#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 +#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 +#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 +#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f +#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 +#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 +#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 +#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 +#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 +#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 +#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 +#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 +#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a +#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b +#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c +#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d +#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e +#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f +#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 +#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 +#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 +#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 +#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 +#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 +#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c +#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 +#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 +#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 +#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 +#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 +#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 +#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a +#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b +#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c +#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d +#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e +#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f +#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 +#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 +#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 +#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 +#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 +#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 +#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 +#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_CONTROL 0x0d87 +#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 +#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89 +#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a +#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 +#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 +#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c +#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d +#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e +#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f +#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa +#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab +#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac +#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad +#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 +#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 +#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf +#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca +#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb +#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc +#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd +#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce +#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf +#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_HDR_MULT_COEF 0x0dd1 +#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_CTRL 0x0dd2 +#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_STATUS 0x0dd3 +#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM0_CM_DEALPHA 0x0dd5 +#define mmCM0_CM_DEALPHA_BASE_IDX 2 +#define mmCM0_CM_COEF_FORMAT 0x0dd6 +#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM0_CM_SHAPER_CONTROL 0x0dd7 +#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8 +#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9 +#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_B 0x0dda +#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_SCALE_R 0x0ddb +#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc +#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd +#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_DATA 0x0dde +#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf +#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 +#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 +#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 +#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 +#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea +#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb +#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec +#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded +#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee +#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def +#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 +#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 +#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 +#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 +#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 +#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 +#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 +#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd +#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe +#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff +#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 +#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 +#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 +#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 +#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 +#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 +#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 +#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 +#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 +#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 +#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a +#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b +#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c +#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d +#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e +#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f +#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM0_CM_3DLUT_MODE 0x0e10 +#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM0_CM_3DLUT_INDEX 0x0e11 +#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_3DLUT_DATA 0x0e12 +#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13 +#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 +#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 +#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 +#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 +#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 +#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3890 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e24 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e25 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e26 +#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL 0x0e27 +#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e28 +#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e29 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e2a +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_HI 0x0e2b +#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_LOW 0x0e2c +#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define mmDPP_TOP1_DPP_CONTROL 0x0e30 +#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 +#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 +#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b +#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c +#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d +#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e +#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f +#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 +#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 +#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 +#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 +#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_DEALPHA 0x0e49 +#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a +#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b +#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c +#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d +#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e +#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f +#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 +#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 +#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 +#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 +#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 +#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 +#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 +#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 +#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_DEGAM 0x0e58 +#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define mmCNVC_CFG1_PRE_REALPHA 0x0e59 +#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x5ac +#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c +#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d +#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e +#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL1_SCL_MODE 0x0e66 +#define mmDSCL1_SCL_MODE_BASE_IDX 2 +#define mmDSCL1_SCL_TAP_CONTROL 0x0e67 +#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_CONTROL 0x0e68 +#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69 +#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c +#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL1_SCL_BLACK_COLOR 0x0e75 +#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define mmDSCL1_DSCL_UPDATE 0x0e76 +#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL1_DSCL_AUTOCAL 0x0e77 +#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL1_OTG_H_BLANK 0x0e7a +#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL1_OTG_V_BLANK 0x0e7b +#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL1_RECOUT_START 0x0e7c +#define mmDSCL1_RECOUT_START_BASE_IDX 2 +#define mmDSCL1_RECOUT_SIZE 0x0e7d +#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL1_MPC_SIZE 0x0e7e +#define mmDSCL1_MPC_SIZE_BASE_IDX 2 +#define mmDSCL1_LB_DATA_FORMAT 0x0e7f +#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL1_LB_MEMORY_CTRL 0x0e80 +#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL1_LB_V_COUNTER 0x0e81 +#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 +#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 +#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL1_OBUF_CONTROL 0x0e84 +#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 +#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define mmCM1_CM_CONTROL 0x0e8b +#define mmCM1_CM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_CONTROL 0x0e8c +#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C11_C12 0x0e8d +#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C13_C14 0x0e8e +#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C21_C22 0x0e8f +#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C23_C24 0x0e90 +#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C31_C32 0x0e91 +#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_C33_C34 0x0e92 +#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93 +#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94 +#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95 +#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96 +#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97 +#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98 +#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 +#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a +#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b +#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c +#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d +#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e +#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f +#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 +#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 +#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 +#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 +#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 +#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 +#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM1_CM_BIAS_CR_R 0x0ea6 +#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7 +#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_CONTROL 0x0ea8 +#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 +#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa +#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab +#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae +#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 +#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 +#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba +#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd +#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe +#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf +#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 +#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 +#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 +#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 +#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 +#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 +#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 +#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 +#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 +#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca +#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb +#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc +#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd +#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece +#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 +#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 +#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 +#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd +#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 +#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 +#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 +#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 +#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 +#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 +#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 +#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 +#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 +#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea +#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb +#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec +#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed +#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee +#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef +#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 +#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 +#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2 +#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 +#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 +#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 +#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb +#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe +#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 +#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a +#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b +#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c +#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d +#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e +#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f +#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e +#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 +#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a +#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b +#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c +#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d +#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e +#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f +#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a +#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b +#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_HDR_MULT_COEF 0x0f3c +#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_CTRL 0x0f3d +#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_STATUS 0x0f3e +#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM1_CM_DEALPHA 0x0f40 +#define mmCM1_CM_DEALPHA_BASE_IDX 2 +#define mmCM1_CM_COEF_FORMAT 0x0f41 +#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM1_CM_SHAPER_CONTROL 0x0f42 +#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_R 0x0f43 +#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_G 0x0f44 +#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_B 0x0f45 +#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_SCALE_R 0x0f46 +#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47 +#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48 +#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_DATA 0x0f49 +#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a +#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 +#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 +#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 +#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 +#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 +#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 +#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 +#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 +#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 +#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a +#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b +#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c +#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d +#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e +#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f +#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 +#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 +#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 +#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 +#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a +#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b +#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c +#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d +#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e +#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f +#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 +#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 +#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 +#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 +#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 +#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 +#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 +#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 +#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 +#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_CTRL2 0x0f79 +#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a +#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM1_CM_3DLUT_MODE 0x0f7b +#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM1_CM_3DLUT_INDEX 0x0f7c +#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_3DLUT_DATA 0x0f7d +#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e +#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f +#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 +#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 +#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 +#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 +#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e3c +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0f8f +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0f90 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0f91 +#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL 0x0f92 +#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL2 0x0f93 +#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0f94 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0f95 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_HI 0x0f96 +#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_LOW 0x0f97 +#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CONTROL 0x1840 +#define mmFMT0_FMT_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1845 +#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_422_CONTROL 0x1849 +#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define mmDPG0_DPG_CONTROL 0x1854 +#define mmDPG0_DPG_CONTROL_BASE_IDX 2 +#define mmDPG0_DPG_RAMP_CONTROL 0x1855 +#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG0_DPG_DIMENSIONS 0x1856 +#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_R_CR 0x1857 +#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_G_Y 0x1858 +#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_B_CB 0x1859 +#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a +#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG0_DPG_STATUS 0x185b +#define mmDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 +#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CONTROL 0x189a +#define mmFMT1_FMT_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_CNTL 0x189f +#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_422_CONTROL 0x18a3 +#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define mmDPG1_DPG_CONTROL 0x18ae +#define mmDPG1_DPG_CONTROL_BASE_IDX 2 +#define mmDPG1_DPG_RAMP_CONTROL 0x18af +#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG1_DPG_DIMENSIONS 0x18b0 +#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 +#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 +#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 +#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG1_DPG_STATUS 0x18b5 +#define mmDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define mmOPPBUF1_OPPBUF_CONTROL 0x18de +#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define mmOPP_TOP_CLK_CONTROL 0x1a5e +#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define mmOPP_ABM_CONTROL 0x1a60 +#define mmOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x1abe +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x1abf +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x1ac0 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL 0x1ac1 +#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL2 0x1ac2 +#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x1ac4 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_HI 0x1ac5 +#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_LOW 0x1ac6 +#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc +#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd +#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace +#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 +#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc +#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add +#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade +#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 +#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define mmOTG0_OTG_H_TOTAL 0x1b2a +#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b +#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A 0x1b2c +#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL 0x1b2f +#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 +#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 +#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A 0x1b37 +#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 +#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b +#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e +#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG0_OTG_CONTROL 0x1b41 +#define mmOTG0_OTG_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG0_OTG_STATUS 0x1b49 +#define mmOTG0_OTG_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_POSITION 0x1b4a +#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f +#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_RESET 0x1b50 +#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_STATUS 0x1b53 +#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 +#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a +#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_EN 0x1b5c +#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e +#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC_CNTL 0x1b68 +#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_CRC_CNTL2 0x1b69 +#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e +#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f +#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 +#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 +#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 +#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_B 0x1b77 +#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 +#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_B 0x1b79 +#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 +#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 +#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 +#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 +#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 +#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VREADY_PARAM 0x1b89 +#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b +#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_GSL_CONTROL 0x1b8c +#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d +#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e +#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f +#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 +#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 +#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 +#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 +#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94 +#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 +#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 +#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 +#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a +#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define mmOTG0_OTG_DRR_CONTROL 0x1b9b +#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_M_CONST_DTO0 0x1b9c +#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define mmOTG0_OTG_M_CONST_DTO1 0x1b9d +#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e +#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_DSC_START_POSITION 0x1b9f +#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 +#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_SPARE_REGISTER 0x1ba2 +#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x200 +#define mmOTG1_OTG_H_TOTAL 0x1baa +#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_H_BLANK_START_END 0x1bab +#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A 0x1bac +#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae +#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL 0x1baf +#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A 0x1bb7 +#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb +#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe +#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG1_OTG_CONTROL 0x1bc1 +#define mmOTG1_OTG_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG1_OTG_STATUS 0x1bc9 +#define mmOTG1_OTG_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_POSITION 0x1bca +#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf +#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_RESET 0x1bd0 +#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 +#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_UPDATE_LOCK 0x1bda +#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_EN 0x1bdc +#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde +#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC_CNTL 0x1be8 +#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_CRC_CNTL2 0x1be9 +#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee +#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_B 0x1bef +#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 +#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 +#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 +#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 +#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 +#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 +#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 +#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 +#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 +#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 +#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 +#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VREADY_PARAM 0x1c09 +#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b +#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_GSL_CONTROL 0x1c0c +#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d +#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e +#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f +#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 +#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 +#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 +#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 +#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14 +#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 +#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 +#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 +#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a +#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define mmOTG1_OTG_DRR_CONTROL 0x1c1b +#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_M_CONST_DTO0 0x1c1c +#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define mmOTG1_OTG_M_CONST_DTO1 0x1c1d +#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e +#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_DSC_START_POSITION 0x1c1f +#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 +#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_SPARE_REGISTER 0x1c22 +#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define mmDWB_SOURCE_SELECT 0x1e2a +#define mmDWB_SOURCE_SELECT_BASE_IDX 2 +#define mmGSL_SOURCE_SELECT 0x1e2b +#define mmGSL_SOURCE_SELECT_BASE_IDX 2 +#define mmOPTC_CLOCK_CONTROL 0x1e2c +#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL 0x1e2d +#define mmODM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL2 0x1e2e +#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL3 0x1e2f +#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define mmODM_MEM_PWR_STATUS 0x1e30 +#define mmODM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmOPTC_MISC_SPARE_REGISTER 0x1e31 +#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x1e6a +#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x1e6b +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x1e6c +#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL 0x1e6d +#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL2 0x1e6e +#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x1e6f +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x1e70 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_HI 0x1e71 +#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_LOW 0x1e72 +#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define mmDC_I2C_CONTROL 0x1e98 +#define mmDC_I2C_CONTROL_BASE_IDX 2 +#define mmDC_I2C_ARBITRATION 0x1e99 +#define mmDC_I2C_ARBITRATION_BASE_IDX 2 +#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDC_I2C_SW_STATUS 0x1e9b +#define mmDC_I2C_SW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c +#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d +#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_SPEED 0x1ea2 +#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC1_SETUP 0x1ea3 +#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC2_SPEED 0x1ea4 +#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC2_SETUP 0x1ea5 +#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION0 0x1eae +#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION1 0x1eaf +#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION2 0x1eb0 +#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION3 0x1eb1 +#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 +#define mmDC_I2C_DATA 0x1eb2 +#define mmDC_I2C_DATA_BASE_IDX 2 +#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define mmDIO_SCRATCH0 0x1eca +#define mmDIO_SCRATCH0_BASE_IDX 2 +#define mmDIO_SCRATCH1 0x1ecb +#define mmDIO_SCRATCH1_BASE_IDX 2 +#define mmDIO_SCRATCH2 0x1ecc +#define mmDIO_SCRATCH2_BASE_IDX 2 +#define mmDIO_SCRATCH3 0x1ecd +#define mmDIO_SCRATCH3_BASE_IDX 2 +#define mmDIO_SCRATCH4 0x1ece +#define mmDIO_SCRATCH4_BASE_IDX 2 +#define mmDIO_SCRATCH5 0x1ecf +#define mmDIO_SCRATCH5_BASE_IDX 2 +#define mmDIO_SCRATCH6 0x1ed0 +#define mmDIO_SCRATCH6_BASE_IDX 2 +#define mmDIO_SCRATCH7 0x1ed1 +#define mmDIO_SCRATCH7_BASE_IDX 2 +#define mmDIO_MEM_PWR_STATUS 0x1edd +#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL 0x1ede +#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL2 0x1edf +#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL 0x1ee0 +#define mmDIO_CLK_CNTL_BASE_IDX 2 +#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define mmDIG_SOFT_RESET 0x1eee +#define mmDIG_SOFT_RESET_BASE_IDX 2 +#define mmDIO_CLK_CNTL2 0x1ef2 +#define mmDIO_CLK_CNTL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL3 0x1ef3 +#define mmDIO_CLK_CNTL3_BASE_IDX 2 +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 +#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +// base address: 0x0 +#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 +#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_CONTROL 0x1f16 +#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +// base address: 0x20 +#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c +#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_CONTROL 0x1f1e +#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1f44 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1f45 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1f46 +#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL 0x1f47 +#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL2 0x1f48 +#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1f49 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1f4a +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_HI 0x1f4b +#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_LOW 0x1f4c +#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define mmDP_AUX0_AUX_CONTROL 0x1f50 +#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 +#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 +#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_DATA 0x1f56 +#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_DATA 0x1f57 +#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 +#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define mmDP_AUX1_AUX_CONTROL 0x1f6c +#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 +#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 +#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_DATA 0x1f72 +#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_DATA 0x1f73 +#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 +#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define mmVPG0_VPG_GENERIC_STATUS 0x206c +#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define mmVPG0_VPG_MEM_PWR 0x206d +#define mmVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define mmVPG0_VPG_ISRC1_2_DATA 0x206f +#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define mmVPG0_VPG_MPEG_INFO0 0x2070 +#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2 +#define mmVPG0_VPG_MPEG_INFO1 0x2071 +#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +// base address: 0x154cc +#define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 +#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 +#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_INFO0 0x2076 +#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_INFO1 0x2077 +#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmAFMT0_AFMT_60958_0 0x2078 +#define mmAFMT0_AFMT_60958_0_BASE_IDX 2 +#define mmAFMT0_AFMT_60958_1 0x2079 +#define mmAFMT0_AFMT_60958_1_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a +#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b +#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c +#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d +#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e +#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmAFMT0_AFMT_60958_2 0x207f +#define mmAFMT0_AFMT_60958_2_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 +#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmAFMT0_AFMT_STATUS 0x2081 +#define mmAFMT0_AFMT_STATUS_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 +#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 +#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084 +#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 +#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmAFMT0_AFMT_MEM_PWR 0x2087 +#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15524 +#define mmDME0_DME_CONTROL 0x2089 +#define mmDME0_DME_CONTROL_BASE_IDX 2 +#define mmDME0_DME_MEMORY_CONTROL 0x208a +#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define mmDIG0_DIG_FE_CNTL 0x208b +#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_DIG_CLOCK_PATTERN 0x208e +#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_TEST_PATTERN 0x208f +#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG0_DIG_FIFO_STATUS 0x2091 +#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 +#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_CONTROL 0x2093 +#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_STATUS 0x2094 +#define mmDIG0_HDMI_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG0_HDMI_GC 0x209d +#define mmDIG0_HDMI_GC_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define mmDIG0_HDMI_DB_CONTROL 0x20a6 +#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_0 0x20a7 +#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_1 0x20a8 +#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_0 0x20a9 +#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_1 0x20aa +#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_0 0x20ab +#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_1 0x20ac +#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_0 0x20ad +#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_1 0x20ae +#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG0_AFMT_CNTL 0x20af +#define mmDIG0_AFMT_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_BE_CNTL 0x20b0 +#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_BE_EN_CNTL 0x20b1 +#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CNTL 0x20d7 +#define mmDIG0_TMDS_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL_CHAR 0x20d8 +#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG0_TMDS_CTL_BITS 0x20de +#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df +#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 +#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_VERSION 0x20e4 +#define mmDIG0_DIG_VERSION_BASE_IDX 2 +#define mmDIG0_DIG_LANE_ENABLE 0x20e5 +#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG0_FORCE_DIG_DISABLE 0x20e6 +#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define mmDP0_DP_LINK_CNTL 0x2108 +#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP0_DP_PIXEL_FORMAT 0x2109 +#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP0_DP_MSA_COLORIMETRY 0x210a +#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP0_DP_CONFIG 0x210b +#define mmDP0_DP_CONFIG_BASE_IDX 2 +#define mmDP0_DP_VID_STREAM_CNTL 0x210c +#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_STEER_FIFO 0x210d +#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP0_DP_MSA_MISC 0x210e +#define mmDP0_DP_MSA_MISC_BASE_IDX 2 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f +#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define mmDP0_DP_VID_TIMING 0x2110 +#define mmDP0_DP_VID_TIMING_BASE_IDX 2 +#define mmDP0_DP_VID_N 0x2111 +#define mmDP0_DP_VID_N_BASE_IDX 2 +#define mmDP0_DP_VID_M 0x2112 +#define mmDP0_DP_VID_M_BASE_IDX 2 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP0_DP_VID_MSA_VBID 0x2115 +#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CNTL 0x2117 +#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM0 0x2119 +#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM1 0x211a +#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM2 0x211b +#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c +#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d +#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_EN 0x211f +#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 +#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 +#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL 0x212b +#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL1 0x212c +#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING1 0x212d +#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING2 0x212e +#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING3 0x212f +#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING4 0x2130 +#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N 0x2131 +#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M 0x2133 +#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_TIMESTAMP 0x2135 +#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 +#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_CNTL 0x2137 +#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 +#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0 0x213a +#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1 0x213b +#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2 0x213c +#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT_UPDATE 0x213d +#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_LINK_TIMING 0x213e +#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP0_DP_MSE_MISC_CNTL 0x213f +#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 +#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 +#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 +#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c +#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d +#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e +#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f +#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL 0x2150 +#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL1 0x2151 +#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP0_DP_DSC_CNTL 0x2152 +#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL2 0x2153 +#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL3 0x2154 +#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL4 0x2155 +#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL5 0x2156 +#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL6 0x2157 +#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL7 0x2158 +#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP0_DP_DB_CNTL 0x2159 +#define mmDP0_DP_DB_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSA_VBID_MISC 0x215a +#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b +#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c +#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP0_DP_ALPM_CNTL 0x215d +#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define mmDP0_DP_GSP8_CNTL 0x215e +#define mmDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define mmDP0_DP_GSP9_CNTL 0x215f +#define mmDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define mmDP0_DP_GSP10_CNTL 0x2160 +#define mmDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define mmDP0_DP_GSP11_CNTL 0x2161 +#define mmDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define mmDP0_DP_GSP_EN_DB_STATUS 0x2162 +#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x158a0 +#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 +#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169 +#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a +#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b +#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define mmVPG1_VPG_GENERIC_STATUS 0x216c +#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define mmVPG1_VPG_MEM_PWR 0x216d +#define mmVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e +#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define mmVPG1_VPG_ISRC1_2_DATA 0x216f +#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define mmVPG1_VPG_MPEG_INFO0 0x2170 +#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2 +#define mmVPG1_VPG_MPEG_INFO1 0x2171 +#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +// base address: 0x158cc +#define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 +#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 +#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_INFO0 0x2176 +#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_INFO1 0x2177 +#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmAFMT1_AFMT_60958_0 0x2178 +#define mmAFMT1_AFMT_60958_0_BASE_IDX 2 +#define mmAFMT1_AFMT_60958_1 0x2179 +#define mmAFMT1_AFMT_60958_1_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a +#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b +#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c +#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d +#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e +#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmAFMT1_AFMT_60958_2 0x217f +#define mmAFMT1_AFMT_60958_2_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 +#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmAFMT1_AFMT_STATUS 0x2181 +#define mmAFMT1_AFMT_STATUS_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 +#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 +#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184 +#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 +#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmAFMT1_AFMT_MEM_PWR 0x2187 +#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +// base address: 0x15924 +#define mmDME1_DME_CONTROL 0x2189 +#define mmDME1_DME_CONTROL_BASE_IDX 2 +#define mmDME1_DME_MEMORY_CONTROL 0x218a +#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x400 +#define mmDIG1_DIG_FE_CNTL 0x218b +#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_DIG_CLOCK_PATTERN 0x218e +#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_TEST_PATTERN 0x218f +#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG1_DIG_FIFO_STATUS 0x2191 +#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 +#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_CONTROL 0x2193 +#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_STATUS 0x2194 +#define mmDIG1_HDMI_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG1_HDMI_GC 0x219d +#define mmDIG1_HDMI_GC_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define mmDIG1_HDMI_DB_CONTROL 0x21a6 +#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_0 0x21a7 +#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_1 0x21a8 +#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_0 0x21a9 +#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_1 0x21aa +#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_0 0x21ab +#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_1 0x21ac +#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_0 0x21ad +#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_1 0x21ae +#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG1_AFMT_CNTL 0x21af +#define mmDIG1_AFMT_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_BE_CNTL 0x21b0 +#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_BE_EN_CNTL 0x21b1 +#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CNTL 0x21d7 +#define mmDIG1_TMDS_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL_CHAR 0x21d8 +#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG1_TMDS_CTL_BITS 0x21de +#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df +#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 +#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_VERSION 0x21e4 +#define mmDIG1_DIG_VERSION_BASE_IDX 2 +#define mmDIG1_DIG_LANE_ENABLE 0x21e5 +#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG1_FORCE_DIG_DISABLE 0x21e6 +#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x400 +#define mmDP1_DP_LINK_CNTL 0x2208 +#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP1_DP_PIXEL_FORMAT 0x2209 +#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP1_DP_MSA_COLORIMETRY 0x220a +#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP1_DP_CONFIG 0x220b +#define mmDP1_DP_CONFIG_BASE_IDX 2 +#define mmDP1_DP_VID_STREAM_CNTL 0x220c +#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_STEER_FIFO 0x220d +#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP1_DP_MSA_MISC 0x220e +#define mmDP1_DP_MSA_MISC_BASE_IDX 2 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f +#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define mmDP1_DP_VID_TIMING 0x2210 +#define mmDP1_DP_VID_TIMING_BASE_IDX 2 +#define mmDP1_DP_VID_N 0x2211 +#define mmDP1_DP_VID_N_BASE_IDX 2 +#define mmDP1_DP_VID_M 0x2212 +#define mmDP1_DP_VID_M_BASE_IDX 2 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP1_DP_VID_MSA_VBID 0x2215 +#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CNTL 0x2217 +#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM0 0x2219 +#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM1 0x221a +#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM2 0x221b +#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c +#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d +#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_EN 0x221f +#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 +#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 +#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL 0x222b +#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL1 0x222c +#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING1 0x222d +#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING2 0x222e +#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING3 0x222f +#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING4 0x2230 +#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N 0x2231 +#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M 0x2233 +#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_TIMESTAMP 0x2235 +#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 +#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_CNTL 0x2237 +#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 +#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0 0x223a +#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1 0x223b +#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2 0x223c +#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT_UPDATE 0x223d +#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_LINK_TIMING 0x223e +#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP1_DP_MSE_MISC_CNTL 0x223f +#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 +#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 +#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 +#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c +#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d +#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e +#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f +#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL 0x2250 +#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL1 0x2251 +#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP1_DP_DSC_CNTL 0x2252 +#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL2 0x2253 +#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL3 0x2254 +#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL4 0x2255 +#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL5 0x2256 +#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL6 0x2257 +#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL7 0x2258 +#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP1_DP_DB_CNTL 0x2259 +#define mmDP1_DP_DB_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSA_VBID_MISC 0x225a +#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b +#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c +#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP1_DP_ALPM_CNTL 0x225d +#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define mmDP1_DP_GSP8_CNTL 0x225e +#define mmDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define mmDP1_DP_GSP9_CNTL 0x225f +#define mmDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define mmDP1_DP_GSP10_CNTL 0x2260 +#define mmDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define mmDP1_DP_GSP11_CNTL 0x2261 +#define mmDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define mmDP1_DP_GSP_EN_DB_STATUS 0x2262 +#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +// base address: 0x0 +#define mmDC_GENERICA 0x2868 +#define mmDC_GENERICA_BASE_IDX 2 +#define mmDC_GENERICB 0x2869 +#define mmDC_GENERICB_BASE_IDX 2 +#define mmDCIO_CLOCK_CNTL 0x286a +#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 +#define mmDC_REF_CLK_CNTL 0x286b +#define mmDC_REF_CLK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_LINK_CNTL 0x286d +#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYB_LINK_CNTL 0x286f +#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmDCIO_WRCMD_DELAY 0x287e +#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_PINSTRAPS 0x2880 +#define mmDC_PINSTRAPS_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_CNTL 0x2883 +#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_STATE 0x2884 +#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 +#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY1 0x2886 +#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY2 0x2887 +#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 +#define mmBL_PWM_CNTL 0x2888 +#define mmBL_PWM_CNTL_BASE_IDX 2 +#define mmBL_PWM_CNTL2 0x2889 +#define mmBL_PWM_CNTL2_BASE_IDX 2 +#define mmBL_PWM_PERIOD_CNTL 0x288a +#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define mmBL_PWM_GRP1_REG_LOCK 0x288b +#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_SOFT_RESET 0x289e +#define mmDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x28c8 +#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_A 0x28c9 +#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_EN 0x28ca +#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_Y 0x28cb +#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC1_MASK 0x28d0 +#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC1_A 0x28d1 +#define mmDC_GPIO_DDC1_A_BASE_IDX 2 +#define mmDC_GPIO_DDC1_EN 0x28d2 +#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC1_Y 0x28d3 +#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC2_MASK 0x28d4 +#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC2_A 0x28d5 +#define mmDC_GPIO_DDC2_A_BASE_IDX 2 +#define mmDC_GPIO_DDC2_EN 0x28d6 +#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC2_Y 0x28d7 +#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_MASK 0x28e8 +#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_A 0x28e9 +#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_EN 0x28ea +#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_Y 0x28eb +#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define mmDC_GPIO_GENLK_MASK 0x28f0 +#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENLK_A 0x28f1 +#define mmDC_GPIO_GENLK_A_BASE_IDX 2 +#define mmDC_GPIO_GENLK_EN 0x28f2 +#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 +#define mmDC_GPIO_GENLK_Y 0x28f3 +#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 +#define mmDC_GPIO_HPD_MASK 0x28f4 +#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 +#define mmDC_GPIO_HPD_A 0x28f5 +#define mmDC_GPIO_HPD_A_BASE_IDX 2 +#define mmDC_GPIO_HPD_EN 0x28f6 +#define mmDC_GPIO_HPD_EN_BASE_IDX 2 +#define mmDC_GPIO_HPD_Y 0x28f7 +#define mmDC_GPIO_HPD_Y_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 +#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_A 0x28f9 +#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_EN 0x28fa +#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_Y 0x28fb +#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc +#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd +#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define mmPHY_AUX_CNTL 0x28ff +#define mmPHY_AUX_CNTL_BASE_IDX 2 +#define mmDC_GPIO_TX12_EN 0x2915 +#define mmDC_GPIO_TX12_EN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_0 0x2916 +#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_1 0x2917 +#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_2 0x2918 +#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define mmDC_GPIO_RXEN 0x2919 +#define mmDC_GPIO_RXEN_BASE_IDX 2 +#define mmDC_GPIO_PULLUPEN 0x291a +#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_3 0x291b +#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_4 0x291c +#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_5 0x291d +#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e +#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 +#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define mmDSCC0_DSCC_CONFIG0 0x300a +#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC0_DSCC_CONFIG1 0x300b +#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC0_DSCC_STATUS 0x300c +#define mmDSCC0_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d +#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e +#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f +#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 +#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 +#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 +#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 +#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 +#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 +#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 +#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 +#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 +#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 +#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a +#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b +#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c +#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d +#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e +#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f +#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 +#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 +#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 +#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 +#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 +#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 +#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c +#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d +#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e +#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f +#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 +#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 +#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc140 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x3050 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x3051 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x3052 +#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL 0x3053 +#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL2 0x3054 +#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x3055 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x3056 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_HI 0x3057 +#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_LOW 0x3058 +#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 +#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define mmDSCC1_DSCC_CONFIG0 0x3066 +#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC1_DSCC_CONFIG1 0x3067 +#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC1_DSCC_STATUS 0x3068 +#define mmDSCC1_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 +#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a +#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b +#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c +#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d +#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e +#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f +#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 +#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 +#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 +#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 +#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 +#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 +#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 +#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 +#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 +#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 +#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a +#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b +#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c +#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d +#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e +#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f +#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 +#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 +#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 +#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 +#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a +#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b +#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c +#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d +#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc2b0 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x30ac +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x30ad +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x30ae +#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL 0x30af +#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL2 0x30b0 +#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x30b1 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x30b2 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_HI 0x30b3 +#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_LOW 0x30b4 +#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define mmDWB_ENABLE_CLK_CTRL 0x3228 +#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define mmDWB_MEM_PWR_CTRL 0x3229 +#define mmDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define mmFC_MODE_CTRL 0x322a +#define mmFC_MODE_CTRL_BASE_IDX 2 +#define mmFC_FLOW_CTRL 0x322b +#define mmFC_FLOW_CTRL_BASE_IDX 2 +#define mmFC_WINDOW_START 0x322c +#define mmFC_WINDOW_START_BASE_IDX 2 +#define mmFC_WINDOW_SIZE 0x322d +#define mmFC_WINDOW_SIZE_BASE_IDX 2 +#define mmFC_SOURCE_SIZE 0x322e +#define mmFC_SOURCE_SIZE_BASE_IDX 2 +#define mmDWB_UPDATE_CTRL 0x322f +#define mmDWB_UPDATE_CTRL_BASE_IDX 2 +#define mmDWB_CRC_CTRL 0x3230 +#define mmDWB_CRC_CTRL_BASE_IDX 2 +#define mmDWB_CRC_MASK_R_G 0x3231 +#define mmDWB_CRC_MASK_R_G_BASE_IDX 2 +#define mmDWB_CRC_MASK_B_A 0x3232 +#define mmDWB_CRC_MASK_B_A_BASE_IDX 2 +#define mmDWB_CRC_VAL_R_G 0x3233 +#define mmDWB_CRC_VAL_R_G_BASE_IDX 2 +#define mmDWB_CRC_VAL_B_A 0x3234 +#define mmDWB_CRC_VAL_B_A_BASE_IDX 2 +#define mmDWB_OUT_CTRL 0x3235 +#define mmDWB_OUT_CTRL_BASE_IDX 2 +#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define mmDWB_HOST_READ_CONTROL 0x3238 +#define mmDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define mmDWB_OVERFLOW_STATUS 0x3239 +#define mmDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define mmDWB_OVERFLOW_COUNTER 0x323a +#define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define mmDWB_SOFT_RESET 0x323b +#define mmDWB_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0xca20 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x3288 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x3289 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x328a +#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL 0x328b +#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL2 0x328c +#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x328d +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x328e +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_HI 0x328f +#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_LOW 0x3290 +#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define mmDWB_HDR_MULT_COEF 0x3294 +#define mmDWB_HDR_MULT_COEF_BASE_IDX 2 +#define mmDWB_GAMUT_REMAP_MODE 0x3295 +#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C23_C24 0x329a +#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C31_C32 0x329b +#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPA_C33_C34 0x329c +#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C11_C12 0x329d +#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C13_C14 0x329e +#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C21_C22 0x329f +#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define mmDWB_OGAM_CONTROL 0x32a3 +#define mmDWB_OGAM_CONTROL_BASE_IDX 2 +#define mmDWB_OGAM_LUT_INDEX 0x32a4 +#define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmDWB_OGAM_LUT_DATA 0x32a5 +#define mmDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define mmDWB_OGAM_LUT_CONTROL 0x32a6 +#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_10_11 0x32be +#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_OFFSET_G 0x32da +#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_OFFSET_R 0x32db +#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_4_5 0x32de +#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_6_7 0x32df +#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define mmMPCC0_MPCC_TOP_SEL 0x0000 +#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define mmMPCC0_MPCC_BOT_SEL 0x0001 +#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define mmMPCC0_MPCC_OPP_ID 0x0002 +#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define mmMPCC0_MPCC_CONTROL 0x0003 +#define mmMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define mmMPCC0_MPCC_SM_CONTROL 0x0004 +#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define mmMPCC0_MPCC_TOP_GAIN 0x0006 +#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 +#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 +#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define mmMPCC0_MPCC_BG_R_CR 0x0009 +#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define mmMPCC0_MPCC_BG_G_Y 0x000a +#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define mmMPCC0_MPCC_BG_B_CB 0x000b +#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c +#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define mmMPCC0_MPCC_STATUS 0x000d +#define mmMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x80 +#define mmMPCC1_MPCC_TOP_SEL 0x0020 +#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define mmMPCC1_MPCC_BOT_SEL 0x0021 +#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define mmMPCC1_MPCC_OPP_ID 0x0022 +#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define mmMPCC1_MPCC_CONTROL 0x0023 +#define mmMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define mmMPCC1_MPCC_SM_CONTROL 0x0024 +#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define mmMPCC1_MPCC_TOP_GAIN 0x0026 +#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 +#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 +#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define mmMPCC1_MPCC_BG_R_CR 0x0029 +#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define mmMPCC1_MPCC_BG_G_Y 0x002a +#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define mmMPCC1_MPCC_BG_B_CB 0x002b +#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c +#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define mmMPCC1_MPCC_STATUS 0x002d +#define mmMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 +#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a +#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b +#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 +#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x200 +#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 +#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca +#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb +#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 +#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define mmMPC_CLOCK_CONTROL 0x0500 +#define mmMPC_CLOCK_CONTROL_BASE_IDX 3 +#define mmMPC_SOFT_RESET 0x0501 +#define mmMPC_SOFT_RESET_BASE_IDX 3 +#define mmMPC_CRC_CTRL 0x0502 +#define mmMPC_CRC_CTRL_BASE_IDX 3 +#define mmMPC_CRC_SEL_CONTROL 0x0503 +#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define mmMPC_CRC_RESULT_AR 0x0504 +#define mmMPC_CRC_RESULT_AR_BASE_IDX 3 +#define mmMPC_CRC_RESULT_GB 0x0505 +#define mmMPC_CRC_RESULT_GB_BASE_IDX 3 +#define mmMPC_CRC_RESULT_C 0x0506 +#define mmMPC_CRC_RESULT_C_BASE_IDX 3 +#define mmMPC_PERFMON_EVENT_CTRL 0x0509 +#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 +#define mmMPC_BYPASS_BG_AR 0x050a +#define mmMPC_BYPASS_BG_AR_BASE_IDX 3 +#define mmMPC_BYPASS_BG_GB 0x050b +#define mmMPC_BYPASS_BG_GB_BASE_IDX 3 +#define mmMPC_HOST_READ_CONTROL 0x050c +#define mmMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define mmMPC_DPP_PENDING_STATUS 0x050d +#define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define mmMPC_PENDING_STATUS_MISC 0x050e +#define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510 +#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define mmADR_VUPDATE_LOCK_SET0 0x0511 +#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define mmCFG_VUPDATE_LOCK_SET0 0x0512 +#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define mmCUR_VUPDATE_LOCK_SET0 0x0513 +#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515 +#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define mmADR_VUPDATE_LOCK_SET1 0x0516 +#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define mmCFG_VUPDATE_LOCK_SET1 0x0517 +#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define mmCUR_VUPDATE_LOCK_SET1 0x0518 +#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define mmMPC_DWB0_MUX 0x055c +#define mmMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define mmMPC_OUT0_MUX 0x0580 +#define mmMPC_OUT0_MUX_BASE_IDX 3 +#define mmMPC_OUT0_DENORM_CONTROL 0x0581 +#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 +#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 +#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define mmMPC_OUT1_MUX 0x0584 +#define mmMPC_OUT1_MUX_BASE_IDX 3 +#define mmMPC_OUT1_DENORM_CONTROL 0x0585 +#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 +#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 +#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define mmMPC_OUT_CSC_COEF_FORMAT 0x0598 +#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define mmMPC_OUT0_CSC_MODE 0x0599 +#define mmMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C11_C12_A 0x059a +#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C13_C14_A 0x059b +#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C21_C22_A 0x059c +#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C23_C24_A 0x059d +#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C31_C32_A 0x059e +#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C33_C34_A 0x059f +#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C11_C12_B 0x05a0 +#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C13_C14_B 0x05a1 +#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C21_C22_B 0x05a2 +#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C23_C24_B 0x05a3 +#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C31_C32_B 0x05a4 +#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define mmMPC_OUT0_CSC_C33_C34_B 0x05a5 +#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_MODE 0x05a6 +#define mmMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C11_C12_A 0x05a7 +#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C13_C14_A 0x05a8 +#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C21_C22_A 0x05a9 +#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C23_C24_A 0x05aa +#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C31_C32_A 0x05ab +#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C33_C34_A 0x05ac +#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C11_C12_B 0x05ad +#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C13_C14_B 0x05ae +#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C21_C22_B 0x05af +#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C23_C24_B 0x05b0 +#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C31_C32_B 0x05b1 +#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define mmMPC_OUT1_CSC_C33_C34_B 0x05b2 +#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmu_dispdec +// base address: 0x0 +#define mmMPC_RMU_CONTROL 0x0680 +#define mmMPC_RMU_CONTROL_BASE_IDX 3 +#define mmMPC_RMU_MEM_PWR_CTRL 0x0681 +#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_CONTROL 0x0682 +#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683 +#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684 +#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685 +#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_SCALE_R 0x0686 +#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687 +#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688 +#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689 +#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a +#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d +#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 +#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a +#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b +#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c +#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d +#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e +#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f +#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 +#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 +#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 +#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa +#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab +#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac +#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad +#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae +#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af +#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 +#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_MODE 0x06b9 +#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_INDEX 0x06ba +#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_DATA 0x06bb +#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc +#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd +#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be +#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 +#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x1901c +#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 +#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_CNTL 0x08ca +#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_CNTL2 0x08cb +#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_HI 0x08ce +#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 3 +#define mmDC_PERFMON15_PERFMON_LOW 0x08cf +#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +// base address: 0x2646c +#define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x091c +#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 +#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x091d +#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 +#define mmAFMT2_AFMT_60958_0 0x0920 +#define mmAFMT2_AFMT_60958_0_BASE_IDX 3 +#define mmAFMT2_AFMT_60958_1 0x0921 +#define mmAFMT2_AFMT_60958_1_BASE_IDX 3 +#define mmAFMT2_AFMT_60958_2 0x0927 +#define mmAFMT2_AFMT_60958_2_BASE_IDX 3 +#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x092a +#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 +#define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x092b +#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 +#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x092d +#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 +#define mmAFMT2_AFMT_MEM_PWR 0x092f +#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define mmVPG2_VPG_GENERIC_PACKET_DATA 0x0932 +#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define mmVPG2_VPG_GENERIC_STATUS 0x0935 +#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define mmDME2_DME_CONTROL 0x093c +#define mmDME2_DME_CONTROL_BASE_IDX 3 +#define mmDME2_DME_MEMORY_CONTROL 0x093d +#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x0 +#define mmHPO_TOP_CLOCK_CONTROL 0x0e43 +#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a698 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x0e66 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 3 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x0e67 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x0e68 +#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_CNTL 0x0e69 +#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_CNTL2 0x0e6a +#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x0e6b +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x0e6c +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_HI 0x0e6d +#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 3 +#define mmDC_PERFMON16_PERFMON_LOW 0x0e6e +#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define mmABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 +#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define mmABM0_DC_ABM1_CNTL 0x0e83 +#define mmABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 +#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a +#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b +#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c +#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e +#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f +#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 +#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 +#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 +#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 +#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 +#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 +#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 +#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 +#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 +#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 +#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a +#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b +#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c +#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d +#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e +#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f +#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0 +#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1 +#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2 +#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3 +#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4 +#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5 +#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6 +#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7 +#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8 +#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9 +#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa +#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab +#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac +#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead +#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae +#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf +#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0 +#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1 +#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2 +#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3 +#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4 +#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5 +#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 +#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x104 +#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 +#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define mmABM1_DC_ABM1_CNTL 0x0ec4 +#define mmABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 +#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb +#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc +#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd +#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf +#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 +#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 +#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 +#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 +#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 +#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 +#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 +#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 +#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 +#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 +#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda +#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb +#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc +#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd +#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede +#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf +#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0 +#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1 +#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2 +#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3 +#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4 +#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5 +#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6 +#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7 +#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8 +#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9 +#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea +#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb +#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec +#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed +#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee +#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef +#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0 +#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1 +#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2 +#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3 +#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4 +#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5 +#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6 +#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 +#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define mmCORB_WRITE_POINTER 0x0000 +#define mmCORB_WRITE_POINTER_BASE_IDX 0 +#define mmCORB_READ_POINTER 0x0000 +#define mmCORB_READ_POINTER_BASE_IDX 0 +#define mmCORB_CONTROL 0x0001 +#define mmCORB_CONTROL_BASE_IDX 0 +#define mmCORB_STATUS 0x0001 +#define mmCORB_STATUS_BASE_IDX 0 +#define mmCORB_SIZE 0x0001 +#define mmCORB_SIZE_BASE_IDX 0 +#define mmRIRB_LOWER_BASE_ADDRESS 0x0002 +#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmRIRB_UPPER_BASE_ADDRESS 0x0003 +#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmRIRB_WRITE_POINTER 0x0004 +#define mmRIRB_WRITE_POINTER_BASE_IDX 0 +#define mmRESPONSE_INTERRUPT_COUNT 0x0004 +#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define mmRIRB_CONTROL 0x0005 +#define mmRIRB_CONTROL_BASE_IDX 0 +#define mmRIRB_STATUS 0x0005 +#define mmRIRB_STATUS_BASE_IDX 0 +#define mmRIRB_SIZE 0x0005 +#define mmRIRB_SIZE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_STATUS 0x0008 +#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c +#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h new file mode 100644 index 000000000000..e8f4ad05932b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h @@ -0,0 +1,35330 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _dcn_3_0_3_SH_MASK_HEADER +#define _dcn_3_0_3_SH_MASK_HEADER + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//CRTC8_IDX +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL +//GENFC_WT +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L +//GENS1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1__NO_DISPLAY_MASK 0x01L +#define GENS1__VGA_VSTATUS_MASK 0x08L +#define GENS1__PIXEL_READ_BACK_MASK 0x30L +//ATTRDW +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDW__ATTR_DATA_MASK 0xFFL +//ATTRX +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRX__ATTR_IDX_MASK 0x1FL +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L +//ATTRDR +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xFFL +//GENMO_WT +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_WT__VGA_RAM_EN_MASK 0x02L +#define GENMO_WT__VGA_CKSEL_MASK 0x0CL +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L +//GENS0 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS0__SENSE_SWITCH_MASK 0x10L +#define GENS0__CRT_INTR_MASK 0x80L +//GENENB +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENENB__BLK_IO_BASE_MASK 0xFFL +//SEQ8_IDX +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x07L +//SEQ8_DATA +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL +//DAC_MASK +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xFFL +//DAC_R_INDEX +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL +//DAC_W_INDEX +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL +//DAC_DATA +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_DATA__DAC_DATA_MASK 0x3FL +//GENFC_RD +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L +//GENMO_RD +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_RD__VGA_RAM_EN_MASK 0x02L +#define GENMO_RD__VGA_CKSEL_MASK 0x0CL +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L +//GRPH8_IDX +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL +//GRPH8_DATA +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL +//CRTC8_IDX_1 +#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA_1 +#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL +//GENFC_WT_1 +#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L +//GENS1_1 +#define GENS1_1__NO_DISPLAY__SHIFT 0x0 +#define GENS1_1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1_1__NO_DISPLAY_MASK 0x01L +#define GENS1_1__VGA_VSTATUS_MASK 0x08L +#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//REFCLK_CNTL +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK 0x20000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x00001FFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK 0x00000010L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK 0x00000010L + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x5 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT 0x9 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000020L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK 0x00000200L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L +//DMU_MEM_PWR_CNTL +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L +//DMCU_SMU_INTERRUPT_CNTL +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +//DMCU_CTRL +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L +//DMCU_STATUS +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +//DMCU_PC_START_ADDR +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_START_ADDR +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_END_ADDR +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_ISR_START_ADDR +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_CS_HI +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL +//DMCU_FW_CS_LO +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL +//DMCU_RAM_ACCESS_CTRL +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +//DMCU_ERAM_WR_CTRL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_WR_DATA +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL +//DMCU_ERAM_RD_CTRL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_RD_DATA +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL +//DMCU_IRAM_WR_CTRL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL +//DMCU_IRAM_WR_DATA +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL +//DMCU_IRAM_RD_CTRL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL +//DMCU_IRAM_RD_DATA +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL +//DMCU_EVENT_TRIGGER +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +//DMCU_UC_INTERNAL_INT_STATUS +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +//DMCU_SS_INTERRUPT_CNTL_STATUS +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L +//DMCU_INTERRUPT_STATUS +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +//DMCU_INTERRUPT_STATUS_1 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L +//DMCU_INTERRUPT_TO_HOST_EN_MASK +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +//DMCU_INTERRUPT_TO_UC_EN_MASK +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +//DC_DMCU_SCRATCH +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL +//DMCU_INT_CNT +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_FW_CHECKSUM_SMPL_BYTE_POS +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL +//DMCU_UC_CLK_GATING_CNTL +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +//MASTER_COMM_DATA_REG1 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG2 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG3 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CMD_REG +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CNTL_REG +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +//SLAVE_COMM_DATA_REG1 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG2 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG3 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CMD_REG +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CNTL_REG +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_STATUS2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_STATUS4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_STATUS5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000200L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +//DMCU_DPRX_INTERRUPT_STATUS1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INTERRUPT_STATUS_CONTINUE +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INT_CNT_CONTINUE +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +//DMCU_INTERRUPT_STATUS_2 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK 0x00400000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK 0x00400000L + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK 0x00000800L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT 0x12 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x13 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x18 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x19 +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT 0x1c +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK 0x00040000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK 0x00080000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x01000000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x02000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK 0x08000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK 0x10000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000800L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT 0xc +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT 0xd +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT 0xe +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT 0xf +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1b +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1c +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1d +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1e +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1f +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK 0x00000800L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK 0x00001000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK 0x00002000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK 0x00004000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK 0x00008000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK 0x08000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK 0x10000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK 0x20000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK 0x40000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK 0x80000000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPP_INTERRUPT_DEST +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x17 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK 0x00800000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00008000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00002000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT 0x8 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT 0xc +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK 0x00000700L +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK 0x00007000L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT 0x11 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK 0x00020000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI +#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK 0x00000038L +//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK 0x00000038L +//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK 0x00000038L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000700L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_DCC_CFG +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L +//DCHUBBUB_RET_PATH_DCC_CFG0_0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG0_1 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_1 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_1 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_1 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xc +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x001FF000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT 0x9 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK 0x00000200L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L +//FMON_CTRL_1 +#define FMON_CTRL_1__FMON_START__SHIFT 0x0 +#define FMON_CTRL_1__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL_1__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL_1__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL_1__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL_1__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL_1__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL_1__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL_1__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL_1__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL_1__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL_1__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL_1__FMON_START_MASK 0x00000001L +#define FMON_CTRL_1__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL_1__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL_1__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL_1__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL_1__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL_1__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL_1__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL_1__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL_1__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL_1__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL_1__FMON_SOF_SEL_MASK 0x38000000L + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_DMDATA_VM_CNTL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C11_C12 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C13_C14 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C21_C22 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C23_C24 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C31_C32 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C33_C34 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_CONTROL +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_BLNDGAM_LUT_INDEX +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_BLNDGAM_LUT_DATA +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_LUT_CONTROL +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_OFFSET_B +#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_OFFSET_G +#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_OFFSET_R +#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_OFFSET_B +#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_OFFSET_G +#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_OFFSET_R +#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM0_CM_SHAPER_CONTROL +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_SHAPER_OFFSET_R +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_G +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_B +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_SHAPER_SCALE_R +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM0_CM_SHAPER_SCALE_G_B +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_SHAPER_LUT_INDEX +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM0_CM_SHAPER_LUT_DATA +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM0_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM0_CM_SHAPER_RAMA_START_CNTL_B +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_G +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_R +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_END_CNTL_B +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_G +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_R +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_REGION_0_1 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_2_3 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_4_5 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_6_7 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_8_9 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_10_11 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_12_13 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_14_15 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_16_17 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_18_19 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_20_21 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_22_23 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_24_25 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_26_27 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_28_29 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_30_31 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_32_33 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_START_CNTL_B +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_G +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_R +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_END_CNTL_B +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_G +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_R +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_REGION_0_1 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_2_3 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_4_5 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_6_7 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_8_9 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_10_11 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_12_13 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_14_15 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_16_17 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_18_19 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_20_21 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_22_23 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_24_25 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_26_27 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_28_29 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_30_31 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_32_33 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_MEM_PWR_CTRL2 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM0_CM_MEM_PWR_STATUS2 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM0_CM_3DLUT_MODE +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM0_CM_3DLUT_INDEX +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM0_CM_3DLUT_DATA +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM0_CM_3DLUT_DATA_30BIT +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM0_CM_3DLUT_READ_WRITE_CONTROL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM0_CM_3DLUT_OUT_NORM_FACTOR +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM0_CM_3DLUT_OUT_OFFSET_R +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_G +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_B +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C11_C12 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C13_C14 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C21_C22 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C23_C24 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C31_C32 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C33_C34 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_CONTROL +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_BLNDGAM_LUT_INDEX +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_BLNDGAM_LUT_DATA +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_LUT_CONTROL +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_OFFSET_B +#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_OFFSET_G +#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_OFFSET_R +#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_OFFSET_B +#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_OFFSET_G +#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_OFFSET_R +#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM1_CM_SHAPER_CONTROL +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_SHAPER_OFFSET_R +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_G +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_B +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_SHAPER_SCALE_R +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM1_CM_SHAPER_SCALE_G_B +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_SHAPER_LUT_INDEX +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM1_CM_SHAPER_LUT_DATA +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM1_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM1_CM_SHAPER_RAMA_START_CNTL_B +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_G +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_R +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_END_CNTL_B +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_G +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_R +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_REGION_0_1 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_2_3 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_4_5 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_6_7 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_8_9 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_10_11 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_12_13 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_14_15 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_16_17 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_18_19 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_20_21 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_22_23 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_24_25 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_26_27 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_28_29 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_30_31 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_32_33 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_START_CNTL_B +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_G +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_R +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_END_CNTL_B +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_G +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_R +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_REGION_0_1 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_2_3 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_4_5 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_6_7 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_8_9 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_10_11 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_12_13 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_14_15 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_16_17 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_18_19 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_20_21 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_22_23 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_24_25 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_26_27 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_28_29 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_30_31 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_32_33 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_MEM_PWR_CTRL2 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM1_CM_MEM_PWR_STATUS2 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM1_CM_3DLUT_MODE +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM1_CM_3DLUT_INDEX +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM1_CM_3DLUT_DATA +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM1_CM_3DLUT_DATA_30BIT +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM1_CM_3DLUT_READ_WRITE_CONTROL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM1_CM_3DLUT_OUT_NORM_FACTOR +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM1_CM_3DLUT_OUT_OFFSET_R +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_G +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_B +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0x00F00000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0x00F00000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00100000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_BLANK_DATA_COLOR +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG0_OTG_BLANK_DATA_COLOR_EXT +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC_CNTL2 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_DSC_START_POSITION +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00100000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_BLANK_DATA_COLOR +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG1_OTG_BLANK_DATA_COLOR_EXT +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC_CNTL2 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_DSC_START_POSITION +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//DWB_SOURCE_SELECT +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT 0x6 +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK 0x000001C0L +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +//ODM_MEM_PWR_CTRL2 +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK 0x40000000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_GENERIC_INTERRUPT_MESSAGE +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_GENERIC_INTERRUPT_CLEAR +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO1 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +//AFMT0_AFMT_VBI_PACKET_CONTROL +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT0_AFMT_AUDIO_INFO0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT0_AFMT_AUDIO_INFO1 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT0_AFMT_60958_0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT0_AFMT_60958_1 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_CONTROL +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT0_AFMT_RAMP_CONTROL0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT0_AFMT_RAMP_CONTROL1 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT0_AFMT_RAMP_CONTROL2 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_RAMP_CONTROL3 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_60958_2 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_RESULT +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT0_AFMT_STATUS +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT0_AFMT_INFOFRAME_CONTROL0 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT0_AFMT_AUDIO_SRC_CONTROL +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT0_AFMT_MEM_PWR +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_STATUS +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_DIG_LANE_ENABLE +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG0_FORCE_DIG_DISABLE +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_DSC_BYTES_PER_PIXEL +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO1 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +//AFMT1_AFMT_VBI_PACKET_CONTROL +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT1_AFMT_AUDIO_INFO0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT1_AFMT_AUDIO_INFO1 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT1_AFMT_60958_0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT1_AFMT_60958_1 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_CONTROL +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT1_AFMT_RAMP_CONTROL0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT1_AFMT_RAMP_CONTROL1 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT1_AFMT_RAMP_CONTROL2 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_RAMP_CONTROL3 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_60958_2 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_RESULT +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT1_AFMT_STATUS +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT1_AFMT_INFOFRAME_CONTROL0 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT1_AFMT_AUDIO_SRC_CONTROL +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT1_AFMT_MEM_PWR +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_STATUS +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L + +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_DIG_LANE_ENABLE +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG1_FORCE_DIG_DISABLE +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_DSC_BYTES_PER_PIXEL +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L +#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//LVTMA_PWRSEQ_CNTL +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +//LVTMA_PWRSEQ_STATE +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L +//LVTMA_PWRSEQ_REF_DIV +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//LVTMA_PWRSEQ_DELAY1 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L +//LVTMA_PWRSEQ_DELAY2 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//BL_PWM_CNTL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//BL_PWM_CNTL2 +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +//BL_PWM_PERIOD_CNTL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//BL_PWM_GRP1_REG_LOCK +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_PWRSEQ_MASK +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L +//DC_GPIO_PWRSEQ_A +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L +//DC_GPIO_PWRSEQ_EN +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L +//DC_GPIO_PWRSEQ_Y +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0x8 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17 +#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18 +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x1c +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00000100L +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L +#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x70000000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14 +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15 +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF0_DSCCIF_CONFIG1 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP1_DSC_DEBUG_CONTROL +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF1_DSCCIF_CONFIG1 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_rmu_dispdec +//MPC_RMU_CONTROL +#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT 0x0 +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT 0x4 +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK 0x0000000FL +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK 0x000000F0L +//MPC_RMU_MEM_PWR_CTRL +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT 0x8 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK 0x00000300L +//MPC_RMU0_SHAPER_CONTROL +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU0_SHAPER_OFFSET_R +#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_OFFSET_G +#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_OFFSET_B +#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_SCALE_R +#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMU0_SHAPER_SCALE_G_B +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMU0_SHAPER_LUT_INDEX +#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMU0_SHAPER_LUT_DATA +#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_B +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_G +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_R +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_B +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_G +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_R +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_REGION_0_1 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_2_3 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_4_5 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_6_7 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_8_9 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_10_11 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_12_13 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_14_15 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_16_17 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_18_19 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_20_21 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_22_23 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_24_25 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_26_27 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_28_29 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_30_31 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_32_33 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_B +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_G +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_R +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_B +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_G +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_R +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_REGION_0_1 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_2_3 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_4_5 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_6_7 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_8_9 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_10_11 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_12_13 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_14_15 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_16_17 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_18_19 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_20_21 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_22_23 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_24_25 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_26_27 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_28_29 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_30_31 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_32_33 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_3DLUT_MODE +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK 0x00000010L +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU0_3DLUT_INDEX +#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK 0x000007FFL +//MPC_RMU0_3DLUT_DATA +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_DATA_30BIT +#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMU0_3DLUT_READ_WRITE_CONTROL +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMU0_3DLUT_OUT_NORM_FACTOR +#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMU0_3DLUT_OUT_OFFSET_R +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_OUT_OFFSET_G +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_OUT_OFFSET_B +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_BL1_PWM_GRP2_REG_LOCK +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_12 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_34 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_1 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_2 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_3 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_4 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_5 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_6 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_7 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_8 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_9 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_10 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_11 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_12 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_13 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_14 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_15 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_16 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_17 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_18 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_19 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_20 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_21 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_22 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_23 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_24 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_BL1_PWM_GRP2_REG_LOCK +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_12 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_34 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_1 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_2 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_3 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_4 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_5 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_6 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_7 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_8 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_9 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_10 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_11 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_12 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_13 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_14 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_15 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_16 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_17 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_18 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_19 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_20 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_21 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_22 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_23 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_24 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//CORB_WRITE_POINTER +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//CORB_READ_POINTER +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//CORB_CONTROL +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//CORB_STATUS +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//CORB_SIZE +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//RIRB_LOWER_BASE_ADDRESS +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//RIRB_UPPER_BASE_ADDRESS +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//RIRB_WRITE_POINTER +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//RESPONSE_INTERRUPT_COUNT +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//RIRB_CONTROL +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//RIRB_STATUS +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//RIRB_SIZE +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_STATUS +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//DMA_POSITION_LOWER_BASE_ADDRESS +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//DMA_POSITION_UPPER_BASE_ADDRESS +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//WALL_CLOCK_COUNTER_ALIAS +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h new file mode 100644 index 000000000000..312c50ea30f3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h @@ -0,0 +1,15083 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_1_2_OFFSET_HEADER +#define _dcn_3_1_2_OFFSET_HEADER + + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x1300000 +#define regAZCONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000 +#define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX 3 +#define regAZCONTROLLER0_MINOR_VERSION 0x4b7000 +#define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX 3 +#define regAZCONTROLLER0_MAJOR_VERSION 0x4b7000 +#define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX 3 +#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regAZCONTROLLER0_GLOBAL_CONTROL 0x4b7002 +#define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER0_WAKE_ENABLE 0x4b7003 +#define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX 3 +#define regAZCONTROLLER0_STATE_CHANGE_STATUS 0x4b7003 +#define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_GLOBAL_STATUS 0x4b7004 +#define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regAZCONTROLLER0_INTERRUPT_CONTROL 0x4b7008 +#define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER0_INTERRUPT_STATUS 0x4b7009 +#define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER 0x4b700c +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX 3 +#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION 0x4b700e +#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS 0x4b7010 +#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS 0x4b7011 +#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 +#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 +#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 +#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_STATUS 0x4b7013 +#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_CORB_SIZE 0x4b7013 +#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 +#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 +#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 +#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x1300000 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x1300000 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +// base address: 0x48 +#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define regVGA_MEM_READ_PAGE_ADDR 0x0001 +#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +// base address: 0x3b4 +#define regCRTC8_IDX 0x002d +#define regCRTC8_IDX_BASE_IDX 1 +#define regCRTC8_DATA 0x002d +#define regCRTC8_DATA_BASE_IDX 1 +#define regGENFC_WT 0x002e +#define regGENFC_WT_BASE_IDX 1 +#define regGENS1 0x002e +#define regGENS1_BASE_IDX 1 +#define regATTRDW 0x0030 +#define regATTRDW_BASE_IDX 1 +#define regATTRX 0x0030 +#define regATTRX_BASE_IDX 1 +#define regATTRDR 0x0030 +#define regATTRDR_BASE_IDX 1 +#define regGENMO_WT 0x0030 +#define regGENMO_WT_BASE_IDX 1 +#define regGENS0 0x0030 +#define regGENS0_BASE_IDX 1 +#define regGENENB 0x0030 +#define regSEQ8_IDX 0x0031 +#define regSEQ8_IDX_BASE_IDX 1 +#define regSEQ8_DATA 0x0031 +#define regSEQ8_DATA_BASE_IDX 1 +#define regDAC_MASK 0x0031 +#define regDAC_MASK_BASE_IDX 1 +#define regDAC_R_INDEX 0x0031 +#define regDAC_R_INDEX_BASE_IDX 1 +#define regDAC_W_INDEX 0x0032 +#define regDAC_W_INDEX_BASE_IDX 1 +#define regDAC_DATA 0x0032 +#define regDAC_DATA_BASE_IDX 1 +#define regGENFC_RD 0x0032 +#define regGENFC_RD_BASE_IDX 1 +#define regGENMO_RD 0x0033 +#define regGENMO_RD_BASE_IDX 1 +#define regGRPH8_IDX 0x0033 +#define regGRPH8_IDX_BASE_IDX 1 +#define regGRPH8_DATA 0x0033 +#define regGRPH8_DATA_BASE_IDX 1 +#define regCRTC8_IDX_1 0x0035 +#define regCRTC8_IDX_1_BASE_IDX 1 +#define regCRTC8_DATA_1 0x0035 +#define regCRTC8_DATA_1_BASE_IDX 1 +#define regGENFC_WT_1 0x0036 +#define regGENFC_WT_1_BASE_IDX 1 +#define regGENS1_1 0x0036 +#define regGENS1_1_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 +#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 +#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 +#define regAZCONTROLLER1_CORB_CONTROL 0x0001 +#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER1_CORB_STATUS 0x0001 +#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER1_CORB_SIZE 0x0001 +#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_CONTROL 0x0005 +#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_STATUS 0x0005 +#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER1_RIRB_SIZE 0x0005 +#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDP_DTO_DBUF_EN 0x0044 +#define regDP_DTO_DBUF_EN_BASE_IDX 1 +#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL4 0x0049 +#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 +#define regDPSTREAMCLK_CNTL 0x004a +#define regDPSTREAMCLK_CNTL_BASE_IDX 1 +#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL2 0x004e +#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define regDCCG_DS_DTO_INCR 0x0053 +#define regDCCG_DS_DTO_INCR_BASE_IDX 1 +#define regDCCG_DS_DTO_MODULO 0x0054 +#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define regDCCG_DS_CNTL 0x0055 +#define regDCCG_DS_CNTL_BASE_IDX 1 +#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define regDPREFCLK_CNTL 0x0058 +#define regDPREFCLK_CNTL_BASE_IDX 1 +#define regDCE_VERSION 0x005e +#define regDCE_VERSION_BASE_IDX 1 +#define regDCCG_GTC_CNTL 0x0060 +#define regDCCG_GTC_CNTL_BASE_IDX 1 +#define regDCCG_GTC_DTO_INCR 0x0061 +#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define regDCCG_GTC_DTO_MODULO 0x0062 +#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define regDCCG_GTC_CURRENT 0x0063 +#define regDCCG_GTC_CURRENT_BASE_IDX 1 +#define regSYMCLK32_SE_CNTL 0x0065 +#define regSYMCLK32_SE_CNTL_BASE_IDX 1 +#define regSYMCLK32_LE_CNTL 0x0066 +#define regSYMCLK32_LE_CNTL_BASE_IDX 1 +#define regDSCCLK0_DTO_PARAM 0x006c +#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK1_DTO_PARAM 0x006d +#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK2_DTO_PARAM 0x006e +#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define regMILLISECOND_TIME_BASE_DIV 0x0070 +#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL 0x0073 +#define regDCCG_PERFMON_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL 0x0074 +#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_CAC_STATUS 0x0077 +#define regDCCG_CAC_STATUS_BASE_IDX 1 +#define regMICROSECOND_TIME_BASE_DIV 0x007b +#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL2 0x007c +#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_DISP_CNTL_REG 0x007f +#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define regOTG0_PIXEL_RATE_CNTL 0x0080 +#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO0_PHASE 0x0081 +#define regDP_DTO0_PHASE_BASE_IDX 1 +#define regDP_DTO0_MODULO 0x0082 +#define regDP_DTO0_MODULO_BASE_IDX 1 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG1_PIXEL_RATE_CNTL 0x0084 +#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO1_PHASE 0x0085 +#define regDP_DTO1_PHASE_BASE_IDX 1 +#define regDP_DTO1_MODULO 0x0086 +#define regDP_DTO1_MODULO_BASE_IDX 1 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG2_PIXEL_RATE_CNTL 0x0088 +#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO2_PHASE 0x0089 +#define regDP_DTO2_PHASE_BASE_IDX 1 +#define regDP_DTO2_MODULO 0x008a +#define regDP_DTO2_MODULO_BASE_IDX 1 +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG3_PIXEL_RATE_CNTL 0x008c +#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO3_PHASE 0x008d +#define regDP_DTO3_PHASE_BASE_IDX 1 +#define regDP_DTO3_MODULO 0x008e +#define regDP_DTO3_MODULO_BASE_IDX 1 +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDPPCLK0_DTO_PARAM 0x0099 +#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK1_DTO_PARAM 0x009a +#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK2_DTO_PARAM 0x009b +#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK3_DTO_PARAM 0x009c +#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define regDCCG_CAC_STATUS2 0x009f +#define regDCCG_CAC_STATUS2_BASE_IDX 1 +#define regSYMCLKA_CLOCK_ENABLE 0x00a0 +#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKB_CLOCK_ENABLE 0x00a1 +#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKC_CLOCK_ENABLE 0x00a2 +#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKD_CLOCK_ENABLE 0x00a3 +#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKE_CLOCK_ENABLE 0x00a4 +#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define regDCCG_SOFT_RESET 0x00a6 +#define regDCCG_SOFT_RESET_BASE_IDX 1 +#define regDSCCLK_DTO_CTRL 0x00a7 +#define regDSCCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_AUDIO_DTO_SOURCE 0x00ab +#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_PHASE 0x00ac +#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_MODULE 0x00ad +#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_PHASE 0x00ae +#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_MODULE 0x00af +#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define regDPPCLK_DTO_CTRL 0x00b6 +#define regDPPCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_CTRL 0x00b8 +#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define regFORCE_SYMCLK_DISABLE 0x00ba +#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define regDTBCLK_DTO0_PHASE 0x0018 +#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO1_PHASE 0x0019 +#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO2_PHASE 0x001a +#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO3_PHASE 0x001b +#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 +#define regDTBCLK_DTO0_MODULO 0x001f +#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO1_MODULO 0x0020 +#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO2_MODULO 0x0021 +#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO3_MODULO 0x0022 +#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 +#define regPHYASYMCLK_CLOCK_CNTL 0x0052 +#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 +#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 +#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYESYMCLK_CLOCK_CNTL 0x0056 +#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regDCCG_GATE_DISABLE_CNTL3 0x005a +#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 +#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 +#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 +#define regDTBCLK_DTO_DBUF_EN 0x0063 +#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL 0x0003 +#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_HI 0x0007 +#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_LOW 0x0008 +#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +// base address: 0x30 +#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c +#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d +#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e +#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL 0x000f +#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 +#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_HI 0x0013 +#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_LOW 0x0014 +#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +// base address: 0x0 +#define regDMCU_CTRL 0x00da +#define regDMCU_CTRL_BASE_IDX 2 +#define regDMCU_STATUS 0x00db +#define regDMCU_STATUS_BASE_IDX 2 +#define regDMCU_PC_START_ADDR 0x00dc +#define regDMCU_PC_START_ADDR_BASE_IDX 2 +#define regDMCU_FW_START_ADDR 0x00dd +#define regDMCU_FW_START_ADDR_BASE_IDX 2 +#define regDMCU_FW_END_ADDR 0x00de +#define regDMCU_FW_END_ADDR_BASE_IDX 2 +#define regDMCU_FW_ISR_START_ADDR 0x00df +#define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 +#define regDMCU_FW_CS_HI 0x00e0 +#define regDMCU_FW_CS_HI_BASE_IDX 2 +#define regDMCU_FW_CS_LO 0x00e1 +#define regDMCU_FW_CS_LO_BASE_IDX 2 +#define regDMCU_RAM_ACCESS_CTRL 0x00e2 +#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 +#define regDMCU_ERAM_WR_CTRL 0x00e3 +#define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 +#define regDMCU_ERAM_WR_DATA 0x00e4 +#define regDMCU_ERAM_WR_DATA_BASE_IDX 2 +#define regDMCU_ERAM_RD_CTRL 0x00e5 +#define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 +#define regDMCU_ERAM_RD_DATA 0x00e6 +#define regDMCU_ERAM_RD_DATA_BASE_IDX 2 +#define regDMCU_IRAM_WR_CTRL 0x00e7 +#define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 +#define regDMCU_IRAM_WR_DATA 0x00e8 +#define regDMCU_IRAM_WR_DATA_BASE_IDX 2 +#define regDMCU_IRAM_RD_CTRL 0x00e9 +#define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 +#define regDMCU_IRAM_RD_DATA 0x00ea +#define regDMCU_IRAM_RD_DATA_BASE_IDX 2 +#define regDMCU_EVENT_TRIGGER 0x00eb +#define regDMCU_EVENT_TRIGGER_BASE_IDX 2 +#define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec +#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 +#define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed +#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 +#define regDMCU_INTERRUPT_STATUS 0x00ee +#define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCU_INTERRUPT_STATUS_1 0x00ef +#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 +#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 +#define regDC_DMCU_SCRATCH 0x00f5 +#define regDC_DMCU_SCRATCH_BASE_IDX 2 +#define regDMCU_INT_CNT 0x00f6 +#define regDMCU_INT_CNT_BASE_IDX 2 +#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 +#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 +#define regDMCU_UC_CLK_GATING_CNTL 0x00f8 +#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 +#define regMASTER_COMM_DATA_REG1 0x00f9 +#define regMASTER_COMM_DATA_REG1_BASE_IDX 2 +#define regMASTER_COMM_DATA_REG2 0x00fa +#define regMASTER_COMM_DATA_REG2_BASE_IDX 2 +#define regMASTER_COMM_DATA_REG3 0x00fb +#define regMASTER_COMM_DATA_REG3_BASE_IDX 2 +#define regMASTER_COMM_CMD_REG 0x00fc +#define regMASTER_COMM_CMD_REG_BASE_IDX 2 +#define regMASTER_COMM_CNTL_REG 0x00fd +#define regMASTER_COMM_CNTL_REG_BASE_IDX 2 +#define regSLAVE_COMM_DATA_REG1 0x00fe +#define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 +#define regSLAVE_COMM_DATA_REG2 0x00ff +#define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 +#define regSLAVE_COMM_DATA_REG3 0x0100 +#define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 +#define regSLAVE_COMM_CMD_REG 0x0101 +#define regSLAVE_COMM_CMD_REG_BASE_IDX 2 +#define regSLAVE_COMM_CNTL_REG 0x0102 +#define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 +#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 +#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 +#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 +#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 +#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e +#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 +#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 +#define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 +#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 +#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 +#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 +#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 +#define regDMCU_INT_CNT_CONTINUE 0x011c +#define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d +#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 +#define regDMCU_INTERRUPT_STATUS_2 0x011e +#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f +#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 +#define regDMCU_INT_CNT_CONT2 0x0120 +#define regDMCU_INT_CNT_CONT2_BASE_IDX 2 +#define regDMCU_INT_CNT_CONT3 0x0121 +#define regDMCU_INT_CNT_CONT3_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +// base address: 0x0 +#define regDMCUB_RBBMIF_SEC_CNTL 0x017a +#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define regRBBMIF_TIMEOUT 0x017f +#define regRBBMIF_TIMEOUT_BASE_IDX 2 +#define regRBBMIF_STATUS 0x0180 +#define regRBBMIF_STATUS_BASE_IDX 2 +#define regRBBMIF_STATUS_2 0x0181 +#define regRBBMIF_STATUS_2_BASE_IDX 2 +#define regRBBMIF_INT_STATUS 0x0182 +#define regRBBMIF_INT_STATUS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS 0x0183 +#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS_2 0x0184 +#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define regRBBMIF_STATUS_FLAG 0x0185 +#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be +#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf +#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 +#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 +#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 +#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_HI 0x00c5 +#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_LOW 0x00c6 +#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define regDC_GPU_TIMER_READ 0x0128 +#define regDC_GPU_TIMER_READ_BASE_IDX 2 +#define regDC_GPU_TIMER_READ_CNTL 0x0129 +#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS 0x012a +#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define regDCCG_INTERRUPT_DEST 0x0148 +#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST 0x0149 +#define regDMU_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST2 0x014a +#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST 0x014b +#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST2 0x014c +#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define regMMHUBBUB_INTERRUPT_DEST 0x014d +#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define regWB_INTERRUPT_DEST 0x014e +#define regWB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST 0x014f +#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST2 0x0151 +#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regMPC_INTERRUPT_DEST 0x0153 +#define regMPC_INTERRUPT_DEST_BASE_IDX 2 +#define regOPP_INTERRUPT_DEST 0x0154 +#define regOPP_INTERRUPT_DEST_BASE_IDX 2 +#define regOPTC_INTERRUPT_DEST 0x0155 +#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG0_INTERRUPT_DEST 0x0156 +#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG1_INTERRUPT_DEST 0x0157 +#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG2_INTERRUPT_DEST 0x0158 +#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG3_INTERRUPT_DEST 0x0159 +#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG4_INTERRUPT_DEST 0x015a +#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG5_INTERRUPT_DEST 0x015b +#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define regDIG_INTERRUPT_DEST 0x015c +#define regDIG_INTERRUPT_DEST_BASE_IDX 2 +#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define regDIO_INTERRUPT_DEST 0x015f +#define regDIO_INTERRUPT_DEST_BASE_IDX 2 +#define regDCIO_INTERRUPT_DEST 0x0160 +#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define regHPD_INTERRUPT_DEST 0x0161 +#define regHPD_INTERRUPT_DEST_BASE_IDX 2 +#define regAZ_INTERRUPT_DEST 0x0162 +#define regAZ_INTERRUPT_DEST_BASE_IDX 2 +#define regAUX_INTERRUPT_DEST 0x0163 +#define regAUX_INTERRUPT_DEST_BASE_IDX 2 +#define regDSC_INTERRUPT_DEST 0x0164 +#define regDSC_INTERRUPT_DEST_BASE_IDX 2 +#define regHPO_INTERRUPT_DEST 0x0165 +#define regHPO_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define regCC_DC_PIPE_DIS 0x00ca +#define regCC_DC_PIPE_DIS_BASE_IDX 2 +#define regDMU_CLK_CNTL 0x00cb +#define regDMU_CLK_CNTL_BASE_IDX 2 +#define regDMU_MEM_PWR_CNTL 0x00cc +#define regDMU_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCU_SMU_INTERRUPT_CNTL 0x00cd +#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define regSMU_INTERRUPT_CONTROL 0x00ce +#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define regZSC_CNTL 0x00cf +#define regZSC_CNTL_BASE_IDX 2 +#define regZSC_CNTL2 0x00d0 +#define regZSC_CNTL2_BASE_IDX 2 +#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 +#define regZSC_STATUS 0x00d7 +#define regZSC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define regDOMAIN0_PG_CONFIG 0x0080 +#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN0_PG_STATUS 0x0081 +#define regDOMAIN0_PG_STATUS_BASE_IDX 2 +#define regDOMAIN1_PG_CONFIG 0x0082 +#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN1_PG_STATUS 0x0083 +#define regDOMAIN1_PG_STATUS_BASE_IDX 2 +#define regDOMAIN2_PG_CONFIG 0x0084 +#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN2_PG_STATUS 0x0085 +#define regDOMAIN2_PG_STATUS_BASE_IDX 2 +#define regDOMAIN3_PG_CONFIG 0x0086 +#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN3_PG_STATUS 0x0087 +#define regDOMAIN3_PG_STATUS_BASE_IDX 2 +#define regDOMAIN16_PG_CONFIG 0x0089 +#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN16_PG_STATUS 0x008a +#define regDOMAIN16_PG_STATUS_BASE_IDX 2 +#define regDOMAIN17_PG_CONFIG 0x008b +#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN17_PG_STATUS 0x008c +#define regDOMAIN17_PG_STATUS_BASE_IDX 2 +#define regDOMAIN18_PG_CONFIG 0x008d +#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN18_PG_STATUS 0x008e +#define regDOMAIN18_PG_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS 0x008f +#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_2 0x0090 +#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_1 0x0091 +#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_3 0x0092 +#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define regDC_IP_REQUEST_CNTL 0x0093 +#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define regDMCUB_REGION0_OFFSET 0x018e +#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION0_OFFSET_HIGH 0x018f +#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET 0x0190 +#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET 0x0192 +#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET 0x0196 +#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET 0x0198 +#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET 0x019a +#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET_HIGH 0x019b +#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET 0x019c +#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET_HIGH 0x019d +#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION0_TOP_ADDRESS 0x019e +#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION1_TOP_ADDRESS 0x019f +#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET 0x01bb +#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET 0x01bd +#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET 0x01bf +#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ENABLE 0x01c5 +#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ACK 0x01c6 +#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INTERRUPT_STATUS 0x01c7 +#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_INTERRUPT_TYPE 0x01c8 +#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_SEC_CNTL 0x01ce +#define regDMCUB_SEC_CNTL_BASE_IDX 2 +#define regDMCUB_MEM_CNTL 0x01cf +#define regDMCUB_MEM_CNTL_BASE_IDX 2 +#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX0_SIZE 0x01d1 +#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX0_WPTR 0x01d2 +#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX0_RPTR 0x01d3 +#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX1_SIZE 0x01d5 +#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX1_WPTR 0x01d6 +#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_RPTR 0x01d7 +#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX0_SIZE 0x01d9 +#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX0_WPTR 0x01da +#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_RPTR 0x01db +#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX1_SIZE 0x01dd +#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX1_WPTR 0x01de +#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_RPTR 0x01df +#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER0 0x01e0 +#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER1 0x01e1 +#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define regDMCUB_TIMER_WINDOW 0x01e2 +#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define regDMCUB_SCRATCH0 0x01e3 +#define regDMCUB_SCRATCH0_BASE_IDX 2 +#define regDMCUB_SCRATCH1 0x01e4 +#define regDMCUB_SCRATCH1_BASE_IDX 2 +#define regDMCUB_SCRATCH2 0x01e5 +#define regDMCUB_SCRATCH2_BASE_IDX 2 +#define regDMCUB_SCRATCH3 0x01e6 +#define regDMCUB_SCRATCH3_BASE_IDX 2 +#define regDMCUB_SCRATCH4 0x01e7 +#define regDMCUB_SCRATCH4_BASE_IDX 2 +#define regDMCUB_SCRATCH5 0x01e8 +#define regDMCUB_SCRATCH5_BASE_IDX 2 +#define regDMCUB_SCRATCH6 0x01e9 +#define regDMCUB_SCRATCH6_BASE_IDX 2 +#define regDMCUB_SCRATCH7 0x01ea +#define regDMCUB_SCRATCH7_BASE_IDX 2 +#define regDMCUB_SCRATCH8 0x01eb +#define regDMCUB_SCRATCH8_BASE_IDX 2 +#define regDMCUB_SCRATCH9 0x01ec +#define regDMCUB_SCRATCH9_BASE_IDX 2 +#define regDMCUB_SCRATCH10 0x01ed +#define regDMCUB_SCRATCH10_BASE_IDX 2 +#define regDMCUB_SCRATCH11 0x01ee +#define regDMCUB_SCRATCH11_BASE_IDX 2 +#define regDMCUB_SCRATCH12 0x01ef +#define regDMCUB_SCRATCH12_BASE_IDX 2 +#define regDMCUB_SCRATCH13 0x01f0 +#define regDMCUB_SCRATCH13_BASE_IDX 2 +#define regDMCUB_SCRATCH14 0x01f1 +#define regDMCUB_SCRATCH14_BASE_IDX 2 +#define regDMCUB_SCRATCH15 0x01f2 +#define regDMCUB_SCRATCH15_BASE_IDX 2 +#define regDMCUB_CNTL 0x01f6 +#define regDMCUB_CNTL_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN0 0x01f7 +#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN1 0x01f8 +#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define regDMCUB_GPINT_DATAOUT 0x01f9 +#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define regDMCUB_MEM_PWR_CNTL 0x01fc +#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCUB_TIMER_CURRENT 0x01fd +#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define regDMCUB_PROC_ID 0x01ff +#define regDMCUB_PROC_ID_BASE_IDX 2 +#define regDMCUB_CNTL2 0x0200 +#define regDMCUB_CNTL2_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define regDWB_ENABLE_CLK_CTRL 0x3228 +#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define regDWB_MEM_PWR_CTRL 0x3229 +#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define regFC_MODE_CTRL 0x322a +#define regFC_MODE_CTRL_BASE_IDX 2 +#define regFC_FLOW_CTRL 0x322b +#define regFC_FLOW_CTRL_BASE_IDX 2 +#define regFC_WINDOW_START 0x322c +#define regFC_WINDOW_START_BASE_IDX 2 +#define regFC_WINDOW_SIZE 0x322d +#define regFC_WINDOW_SIZE_BASE_IDX 2 +#define regFC_SOURCE_SIZE 0x322e +#define regFC_SOURCE_SIZE_BASE_IDX 2 +#define regDWB_UPDATE_CTRL 0x322f +#define regDWB_UPDATE_CTRL_BASE_IDX 2 +#define regDWB_CRC_CTRL 0x3230 +#define regDWB_CRC_CTRL_BASE_IDX 2 +#define regDWB_CRC_MASK_R_G 0x3231 +#define regDWB_CRC_MASK_R_G_BASE_IDX 2 +#define regDWB_CRC_MASK_B_A 0x3232 +#define regDWB_CRC_MASK_B_A_BASE_IDX 2 +#define regDWB_CRC_VAL_R_G 0x3233 +#define regDWB_CRC_VAL_R_G_BASE_IDX 2 +#define regDWB_CRC_VAL_B_A 0x3234 +#define regDWB_CRC_VAL_B_A_BASE_IDX 2 +#define regDWB_OUT_CTRL 0x3235 +#define regDWB_OUT_CTRL_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define regDWB_HOST_READ_CONTROL 0x3238 +#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define regDWB_OVERFLOW_STATUS 0x3239 +#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define regDWB_OVERFLOW_COUNTER 0x323a +#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define regDWB_SOFT_RESET 0x323b +#define regDWB_SOFT_RESET_BASE_IDX 2 +#define regDWB_DEBUG_CTRL 0x323c +#define regDWB_DEBUG_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define regDWB_HDR_MULT_COEF 0x3294 +#define regDWB_HDR_MULT_COEF_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_MODE 0x3295 +#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C23_C24 0x329a +#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C31_C32 0x329b +#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C33_C34 0x329c +#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C11_C12 0x329d +#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C13_C14 0x329e +#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C21_C22 0x329f +#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define regDWB_OGAM_CONTROL 0x32a3 +#define regDWB_OGAM_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_LUT_INDEX 0x32a4 +#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define regDWB_OGAM_LUT_DATA 0x32a5 +#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define regDWB_OGAM_LUT_CONTROL 0x32a6 +#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_10_11 0x32be +#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_G 0x32da +#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_R 0x32db +#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_4_5 0x32de +#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_6_7 0x32df +#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0xca20 +#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 +#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a +#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL 0x328b +#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL2 0x328c +#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e +#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_HI 0x328f +#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_LOW 0x3290 +#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +// base address: 0x0 +#define regVGA_RENDER_CONTROL 0x0000 +#define regVGA_RENDER_CONTROL_BASE_IDX 1 +#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define regVGA_MODE_CONTROL 0x0002 +#define regVGA_MODE_CONTROL_BASE_IDX 1 +#define regVGA_SURFACE_PITCH_SELECT 0x0003 +#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS 0x0004 +#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define regVGA_HDP_CONTROL 0x000a +#define regVGA_HDP_CONTROL_BASE_IDX 1 +#define regVGA_CACHE_CONTROL 0x000b +#define regVGA_CACHE_CONTROL_BASE_IDX 1 +#define regD1VGA_CONTROL 0x000c +#define regD1VGA_CONTROL_BASE_IDX 1 +#define regD2VGA_CONTROL 0x000e +#define regD2VGA_CONTROL_BASE_IDX 1 +#define regVGA_STATUS 0x0010 +#define regVGA_STATUS_BASE_IDX 1 +#define regVGA_INTERRUPT_CONTROL 0x0011 +#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define regVGA_STATUS_CLEAR 0x0012 +#define regVGA_STATUS_CLEAR_BASE_IDX 1 +#define regVGA_INTERRUPT_STATUS 0x0013 +#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define regVGA_MAIN_CONTROL 0x0014 +#define regVGA_MAIN_CONTROL_BASE_IDX 1 +#define regVGA_TEST_CONTROL 0x0015 +#define regVGA_TEST_CONTROL_BASE_IDX 1 +#define regVGA_QOS_CTRL 0x0018 +#define regVGA_QOS_CTRL_BASE_IDX 1 +#define regD3VGA_CONTROL 0x0038 +#define regD3VGA_CONTROL_BASE_IDX 1 +#define regD4VGA_CONTROL 0x0039 +#define regD4VGA_CONTROL_BASE_IDX 1 +#define regD5VGA_CONTROL 0x003a +#define regD5VGA_CONTROL_BASE_IDX 1 +#define regD6VGA_CONTROL 0x003b +#define regD6VGA_CONTROL_BASE_IDX 1 +#define regVGA_SOURCE_SELECT 0x003c +#define regVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define regMCIF_CONTROL 0x034a +#define regMCIF_CONTROL_BASE_IDX 2 +#define regMCIF_WRITE_COMBINE_CONTROL 0x034b +#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_STATUS 0x0274 +#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_PITCH 0x0275 +#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS 0x0276 +#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS2 0x0277 +#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS 0x0278 +#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS2 0x0279 +#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS 0x027a +#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS2 0x027b +#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS 0x027c +#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS2 0x027d +#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define regMCIF_WB_ARBITRATION_CONTROL 0x027e +#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SCLK_CHANGE 0x027f +#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C 0x0284 +#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C 0x0288 +#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y 0x028a +#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C 0x028c +#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y 0x028e +#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C 0x0290 +#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define regMULTI_LEVEL_QOS_CTRL 0x0297 +#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 +#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 +#define regMCIF_WB_VMID_CONTROL 0x02a8 +#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define regMCIF_WB_MIN_TTO 0x02a9 +#define regMCIF_WB_MIN_TTO_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 +#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 +#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 +#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL 0x0355 +#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL2 0x0356 +#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_HI 0x0359 +#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_LOW 0x035a +#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define regMCIF_WB_WATERMARK 0x02ab +#define regMCIF_WB_WATERMARK_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONFIG 0x02ac +#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define regMMHUBBUB_MIN_TTO 0x02b1 +#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define regMMHUBBUB_CTRL 0x0333 +#define regMMHUBBUB_CTRL_BASE_IDX 2 +#define regWBIF_SMU_WM_CONTROL 0x0334 +#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define regWBIF0_MISC_CTRL 0x0335 +#define regWBIF0_MISC_CTRL_BASE_IDX 2 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regVGA_SRC_SPLIT_CNTL 0x033e +#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_STATUS 0x033f +#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 +#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regMMHUBBUB_CLOCK_CNTL 0x0341 +#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regMMHUBBUB_SOFT_RESET 0x0342 +#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDMU_IF_ERR_STATUS 0x0346 +#define regDMU_IF_ERR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 +#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 +#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO 0x03c3 +#define regAZALIA_AUDIO_DTO_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define regAZALIA_SOCCLK_CONTROL 0x03c5 +#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define regAZALIA_DATA_DMA_CONTROL 0x03c7 +#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_BDL_DMA_CONTROL 0x03c8 +#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define regAZALIA_CORB_DMA_CONTROL 0x03ca +#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_RESULT 0x03dd +#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL0 0x03e3 +#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL1 0x03e4 +#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL2 0x03e5 +#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL3 0x03e6 +#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC0_RESULT 0x03e7 +#define regAZALIA_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL0 0x03e8 +#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL1 0x03e9 +#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL2 0x03ea +#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL3 0x03eb +#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC1_RESULT 0x03ec +#define regAZALIA_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_MEM_PWR_CTRL 0x03ee +#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define regAZALIA_MEM_PWR_STATUS 0x03ef +#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define regAZ_CLOCK_CNTL 0x0372 +#define regAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a +#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b +#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c +#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL 0x037d +#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL2 0x037e +#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_HI 0x0381 +#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_LOW 0x0382 +#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +// base address: 0x0 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa +#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb +#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e +#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 +#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 +#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 +#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 +#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 +#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 +#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_MSB 0x052a +#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_LSB 0x052b +#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_MSB 0x052c +#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define regVTG0_CONTROL 0x052d +#define regVTG0_CONTROL_BASE_IDX 2 +#define regVTG1_CONTROL 0x052e +#define regVTG1_CONTROL_BASE_IDX 2 +#define regVTG2_CONTROL 0x052f +#define regVTG2_CONTROL_BASE_IDX 2 +#define regVTG3_CONTROL 0x0530 +#define regVTG3_CONTROL_BASE_IDX 2 +#define regDCHUBBUB_SOFT_RESET 0x0531 +#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDCHUBBUB_CLOCK_CNTL 0x0532 +#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regDCFCLK_CNTL 0x0533 +#define regDCFCLK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 +#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define regDCHUBBUB_CTRL_STATUS 0x0537 +#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define regFMON_CTRL 0x0540 +#define regFMON_CTRL_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 +#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 +#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +// base address: 0x0 +#define regDCHUBBUB_SDPIF_CFG0 0x046f +#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG1 0x0470 +#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG2 0x0471 +#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 +#define regVM_REQUEST_PHYSICAL 0x0472 +#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 +#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 +#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_BASE 0x0475 +#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_TOP 0x0476 +#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define regDCN_VM_FB_OFFSET 0x0477 +#define regDCN_VM_FB_OFFSET_BASE_IDX 2 +#define regDCN_VM_AGP_BOT 0x0478 +#define regDCN_VM_AGP_BOT_BASE_IDX 2 +#define regDCN_VM_AGP_TOP 0x0479 +#define regDCN_VM_AGP_TOP_BASE_IDX 2 +#define regDCN_VM_AGP_BASE 0x047a +#define regDCN_VM_AGP_BASE_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b +#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c +#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +// base address: 0x0 +#define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af +#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 +#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 +#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 +#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 +#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 +#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 +#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 +#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 +#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 +#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 +#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba +#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb +#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc +#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd +#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be +#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf +#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define regDCHUBBUB_CRC_CTRL 0x04c2 +#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 +#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 +#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 +#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 +#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 +#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT0 0x04c8 +#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT1 0x04c9 +#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT2 0x04ca +#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 +#define regDCHUBBUB_COMPBUF_CTRL 0x04cb +#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET0_CTRL 0x04cc +#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET1_CTRL 0x04cd +#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET2_CTRL 0x04ce +#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET3_CTRL 0x04cf +#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 +#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 +#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 +#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regCOMPBUF_RESERVED_SPACE 0x04d5 +#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define regDCN_VM_CONTEXT0_CNTL 0x0559 +#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_CNTL 0x0560 +#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_CNTL 0x0567 +#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_CNTL 0x056e +#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_CNTL 0x0575 +#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_CNTL 0x057c +#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_CNTL 0x0583 +#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_CNTL 0x058a +#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_CNTL 0x0591 +#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_CNTL 0x0598 +#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_CNTL 0x059f +#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_CNTL 0x05a6 +#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_CNTL 0x05ad +#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_CNTL 0x05b4 +#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_CNTL 0x05bb +#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_CNTL 0x05c2 +#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regDCN_VM_FAULT_CNTL 0x05cb +#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define regDCN_VM_FAULT_STATUS 0x05cc +#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_MSB 0x05cd +#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_LSB 0x05ce +#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d +#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e +#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f +#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL 0x0550 +#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL2 0x0551 +#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_HI 0x0554 +#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_LOW 0x0555 +#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_CNTL 0x05f3 +#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP0_HUBP_CLK_CNTL 0x05f4 +#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 +#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG 0x05f7 +#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 +#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a +#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_0 0x0644 +#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_1 0x0645 +#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ0_DST_DIMENSIONS 0x0646 +#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ0_DST_AFTER_SCALER 0x0647 +#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 +#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 +#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a +#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b +#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c +#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d +#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e +#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f +#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 +#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 +#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 +#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 +#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 +#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 +#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 +#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 +#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 +#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 +#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY 0x065b +#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ0_CURSOR_SETTINGS 0x065c +#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 +#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 +#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 +#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 +#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 +#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 +#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define regHUBPRET0_HUBPRET_CONTROL 0x066c +#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define regCURSOR0_0_CURSOR_CONTROL 0x0678 +#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SIZE 0x067b +#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_POSITION 0x067c +#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_CNTL 0x0684 +#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_STATUS 0x0686 +#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a74 +#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d +#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e +#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f +#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL 0x06a0 +#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 +#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 +#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_HI 0x06a4 +#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_LOW 0x06a5 +#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_CNTL 0x06cf +#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP1_HUBP_CLK_CNTL 0x06d0 +#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 +#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG 0x06d3 +#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 +#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 +#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_0 0x0720 +#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_1 0x0721 +#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ1_DST_DIMENSIONS 0x0722 +#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ1_DST_AFTER_SCALER 0x0723 +#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 +#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 +#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 +#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 +#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 +#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 +#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a +#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b +#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c +#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d +#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_0 0x072e +#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_1 0x072f +#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 +#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 +#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 +#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 +#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 +#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 +#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 +#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ1_CURSOR_SETTINGS 0x0738 +#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f +#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 +#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 +#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 +#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 +#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 +#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define regHUBPRET1_HUBPRET_CONTROL 0x0748 +#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define regCURSOR0_1_CURSOR_CONTROL 0x0754 +#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SIZE 0x0757 +#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_POSITION 0x0758 +#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_CNTL 0x0760 +#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_STATUS 0x0762 +#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1de4 +#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 +#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a +#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b +#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL 0x077c +#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL2 0x077d +#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f +#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_HI 0x0780 +#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_LOW 0x0781 +#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_TILING_CONFIG 0x079f +#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_CNTL 0x07ab +#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP2_HUBP_CLK_CNTL 0x07ac +#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae +#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG 0x07af +#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 +#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 +#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_0 0x07fc +#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_1 0x07fd +#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ2_DST_DIMENSIONS 0x07fe +#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ2_DST_AFTER_SCALER 0x07ff +#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 +#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 +#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 +#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 +#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 +#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 +#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 +#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 +#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 +#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 +#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_0 0x080a +#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_1 0x080b +#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_2 0x080c +#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_3 0x080d +#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_4 0x080e +#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_5 0x080f +#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 +#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 +#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 +#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ2_CURSOR_SETTINGS 0x0814 +#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b +#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c +#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d +#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e +#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f +#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 +#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define regHUBPRET2_HUBPRET_CONTROL 0x0824 +#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define regCURSOR0_2_CURSOR_CONTROL 0x0830 +#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SIZE 0x0833 +#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_POSITION 0x0834 +#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_CNTL 0x083c +#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_STATUS 0x083e +#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x2154 +#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 +#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 +#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL 0x0858 +#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL2 0x0859 +#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b +#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_HI 0x085c +#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_LOW 0x085d +#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_TILING_CONFIG 0x087b +#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_CNTL 0x0887 +#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP3_HUBP_CLK_CNTL 0x0888 +#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG_DB 0x088a +#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG 0x088b +#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ3_VMID_SETTINGS_0 0x089d +#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd +#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be +#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 +#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 +#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ3_DST_DIMENSIONS 0x08da +#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ3_DST_AFTER_SCALER 0x08db +#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc +#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd +#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de +#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df +#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 +#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 +#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 +#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 +#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 +#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 +#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 +#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 +#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 +#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea +#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb +#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec +#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed +#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef +#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 +#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 +#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 +#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 +#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa +#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb +#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc +#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define regHUBPRET3_HUBPRET_CONTROL 0x0900 +#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define regCURSOR0_3_CURSOR_CONTROL 0x090c +#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SIZE 0x090f +#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_POSITION 0x0910 +#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_CNTL 0x0918 +#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_STATUS 0x091a +#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_DATA 0x091c +#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x24c4 +#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 +#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 +#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL 0x0934 +#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL2 0x0935 +#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 +#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_HI 0x0938 +#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_LOW 0x0939 +#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 +#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 +#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 +#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 +#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 +#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 +#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 +#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda +#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb +#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd +#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEALPHA 0x0cde +#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf +#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 +#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 +#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 +#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 +#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 +#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 +#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea +#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb +#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec +#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEGAM 0x0ced +#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG0_PRE_REALPHA 0x0cee +#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 +#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 +#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 +#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 +#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa +#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL0_SCL_MODE 0x0cfb +#define regDSCL0_SCL_MODE_BASE_IDX 2 +#define regDSCL0_SCL_TAP_CONTROL 0x0cfc +#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_CONTROL 0x0cfd +#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe +#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 +#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 +#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 +#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL0_SCL_BLACK_COLOR 0x0d0a +#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL0_DSCL_UPDATE 0x0d0b +#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL0_DSCL_AUTOCAL 0x0d0c +#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL0_OTG_H_BLANK 0x0d0f +#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL0_OTG_V_BLANK 0x0d10 +#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL0_RECOUT_START 0x0d11 +#define regDSCL0_RECOUT_START_BASE_IDX 2 +#define regDSCL0_RECOUT_SIZE 0x0d12 +#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL0_MPC_SIZE 0x0d13 +#define regDSCL0_MPC_SIZE_BASE_IDX 2 +#define regDSCL0_LB_DATA_FORMAT 0x0d14 +#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL0_LB_MEMORY_CTRL 0x0d15 +#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL0_LB_V_COUNTER 0x0d16 +#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 +#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 +#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL0_OBUF_CONTROL 0x0d19 +#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a +#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define regCM0_CM_CONTROL 0x0d20 +#define regCM0_CM_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_CONTROL 0x0d21 +#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C11_C12 0x0d22 +#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C13_C14 0x0d23 +#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C21_C22 0x0d24 +#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C23_C24 0x0d25 +#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C31_C32 0x0d26 +#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C33_C34 0x0d27 +#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 +#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 +#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a +#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b +#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c +#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d +#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e +#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f +#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 +#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 +#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 +#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 +#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 +#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 +#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 +#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 +#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 +#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 +#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a +#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_BIAS_CR_R 0x0d3b +#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c +#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_CONTROL 0x0d3d +#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e +#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f +#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 +#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_CONTROL 0x0d87 +#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 +#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 +#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a +#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d +#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 +#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 +#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 +#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c +#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d +#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e +#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f +#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 +#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 +#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 +#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 +#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 +#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 +#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 +#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 +#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 +#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa +#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab +#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac +#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad +#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 +#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 +#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 +#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc +#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf +#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 +#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 +#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 +#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 +#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 +#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 +#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 +#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 +#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 +#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca +#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb +#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc +#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd +#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce +#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf +#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 +#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_HDR_MULT_COEF 0x0dd1 +#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL 0x0dd2 +#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS 0x0dd3 +#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM0_CM_DEALPHA 0x0dd5 +#define regCM0_CM_DEALPHA_BASE_IDX 2 +#define regCM0_CM_COEF_FORMAT 0x0dd6 +#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM0_CM_SHAPER_CONTROL 0x0dd7 +#define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 +#define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 +#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 +#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_SHAPER_OFFSET_B 0x0dda +#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_SCALE_R 0x0ddb +#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc +#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd +#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_SHAPER_LUT_DATA 0x0dde +#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf +#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 +#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 +#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 +#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 +#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 +#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 +#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea +#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb +#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec +#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded +#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee +#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def +#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 +#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 +#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 +#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 +#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 +#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 +#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 +#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 +#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa +#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb +#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc +#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd +#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe +#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff +#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 +#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 +#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 +#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 +#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 +#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 +#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 +#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 +#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 +#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 +#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a +#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b +#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c +#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d +#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL2 0x0e0e +#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS2 0x0e0f +#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define regCM0_CM_3DLUT_MODE 0x0e10 +#define regCM0_CM_3DLUT_MODE_BASE_IDX 2 +#define regCM0_CM_3DLUT_INDEX 0x0e11 +#define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 +#define regCM0_CM_3DLUT_DATA 0x0e12 +#define regCM0_CM_3DLUT_DATA_BASE_IDX 2 +#define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 +#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 +#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 +#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 +#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 +#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 +#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 +#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_DATA 0x0e1a +#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define regDPP_TOP0_DPP_CONTROL 0x0cc5 +#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 +#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 +#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 +#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca +#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3890 +#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 +#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 +#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL 0x0e27 +#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 +#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a +#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_HI 0x0e2b +#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_LOW 0x0e2c +#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b +#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c +#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d +#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e +#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f +#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 +#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 +#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 +#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 +#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 +#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 +#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 +#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a +#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b +#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c +#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d +#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e +#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f +#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 +#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 +#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEGAM 0x0e58 +#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG1_PRE_REALPHA 0x0e59 +#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x5ac +#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c +#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d +#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e +#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f +#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL1_SCL_MODE 0x0e66 +#define regDSCL1_SCL_MODE_BASE_IDX 2 +#define regDSCL1_SCL_TAP_CONTROL 0x0e67 +#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_CONTROL 0x0e68 +#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 +#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c +#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e +#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 +#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 +#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL1_SCL_BLACK_COLOR 0x0e75 +#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL1_DSCL_UPDATE 0x0e76 +#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL1_DSCL_AUTOCAL 0x0e77 +#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL1_OTG_H_BLANK 0x0e7a +#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL1_OTG_V_BLANK 0x0e7b +#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL1_RECOUT_START 0x0e7c +#define regDSCL1_RECOUT_START_BASE_IDX 2 +#define regDSCL1_RECOUT_SIZE 0x0e7d +#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL1_MPC_SIZE 0x0e7e +#define regDSCL1_MPC_SIZE_BASE_IDX 2 +#define regDSCL1_LB_DATA_FORMAT 0x0e7f +#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL1_LB_MEMORY_CTRL 0x0e80 +#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL1_LB_V_COUNTER 0x0e81 +#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 +#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 +#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL1_OBUF_CONTROL 0x0e84 +#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 +#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define regCM1_CM_CONTROL 0x0e8b +#define regCM1_CM_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_CONTROL 0x0e8c +#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C11_C12 0x0e8d +#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C13_C14 0x0e8e +#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C21_C22 0x0e8f +#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C23_C24 0x0e90 +#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C31_C32 0x0e91 +#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C33_C34 0x0e92 +#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 +#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 +#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 +#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 +#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 +#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 +#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 +#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a +#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b +#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c +#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d +#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e +#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f +#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 +#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 +#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 +#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 +#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 +#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 +#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_BIAS_CR_R 0x0ea6 +#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 +#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 +#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 +#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa +#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab +#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 +#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 +#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 +#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 +#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 +#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb +#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe +#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 +#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 +#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 +#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 +#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a +#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b +#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c +#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d +#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e +#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f +#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 +#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 +#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 +#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 +#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 +#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 +#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 +#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 +#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 +#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b +#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e +#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 +#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 +#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a +#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b +#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c +#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d +#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e +#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f +#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 +#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 +#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 +#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 +#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 +#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 +#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 +#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 +#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 +#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 +#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a +#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b +#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_HDR_MULT_COEF 0x0f3c +#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL 0x0f3d +#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS 0x0f3e +#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM1_CM_DEALPHA 0x0f40 +#define regCM1_CM_DEALPHA_BASE_IDX 2 +#define regCM1_CM_COEF_FORMAT 0x0f41 +#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM1_CM_SHAPER_CONTROL 0x0f42 +#define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 +#define regCM1_CM_SHAPER_OFFSET_R 0x0f43 +#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_OFFSET_G 0x0f44 +#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_SHAPER_OFFSET_B 0x0f45 +#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_SCALE_R 0x0f46 +#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 +#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 +#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_SHAPER_LUT_DATA 0x0f49 +#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a +#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b +#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c +#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d +#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e +#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f +#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 +#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 +#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 +#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 +#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 +#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 +#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 +#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 +#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 +#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 +#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a +#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b +#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c +#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d +#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e +#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f +#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 +#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 +#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 +#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 +#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 +#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 +#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a +#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b +#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c +#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d +#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e +#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f +#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 +#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 +#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 +#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 +#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 +#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 +#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 +#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 +#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 +#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL2 0x0f79 +#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS2 0x0f7a +#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define regCM1_CM_3DLUT_MODE 0x0f7b +#define regCM1_CM_3DLUT_MODE_BASE_IDX 2 +#define regCM1_CM_3DLUT_INDEX 0x0f7c +#define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 +#define regCM1_CM_3DLUT_DATA 0x0f7d +#define regCM1_CM_3DLUT_DATA_BASE_IDX 2 +#define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e +#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f +#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 +#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 +#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 +#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 +#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 +#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_DATA 0x0f85 +#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define regDPP_TOP1_DPP_CONTROL 0x0e30 +#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 +#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 +#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 +#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 +#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e3c +#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f +#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 +#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 +#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL 0x0f92 +#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 +#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_HI 0x0f96 +#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_LOW 0x0f97 +#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 +#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 +#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 +#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 +#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa +#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab +#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac +#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad +#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae +#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf +#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 +#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 +#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 +#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 +#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 +#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 +#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 +#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 +#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 +#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba +#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb +#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc +#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd +#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe +#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf +#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 +#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 +#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +// base address: 0xb58 +#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 +#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 +#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 +#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca +#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL2_SCL_MODE 0x0fd1 +#define regDSCL2_SCL_MODE_BASE_IDX 2 +#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 +#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_CONTROL 0x0fd3 +#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 +#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 +#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb +#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde +#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 +#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL2_DSCL_UPDATE 0x0fe1 +#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL2_DSCL_AUTOCAL 0x0fe2 +#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL2_OTG_H_BLANK 0x0fe5 +#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL2_OTG_V_BLANK 0x0fe6 +#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL2_RECOUT_START 0x0fe7 +#define regDSCL2_RECOUT_START_BASE_IDX 2 +#define regDSCL2_RECOUT_SIZE 0x0fe8 +#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL2_MPC_SIZE 0x0fe9 +#define regDSCL2_MPC_SIZE_BASE_IDX 2 +#define regDSCL2_LB_DATA_FORMAT 0x0fea +#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL2_LB_MEMORY_CTRL 0x0feb +#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL2_LB_V_COUNTER 0x0fec +#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed +#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee +#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL2_OBUF_CONTROL 0x0fef +#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 +#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define regCM2_CM_CONTROL 0x0ff6 +#define regCM2_CM_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 +#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 +#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 +#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C21_C22 0x0ffa +#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C23_C24 0x0ffb +#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C31_C32 0x0ffc +#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C33_C34 0x0ffd +#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe +#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff +#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 +#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 +#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 +#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 +#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 +#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 +#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 +#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 +#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 +#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 +#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a +#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b +#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c +#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d +#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e +#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f +#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 +#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_BIAS_CR_R 0x1011 +#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 +#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_CONTROL 0x1013 +#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 +#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 +#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 +#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_CONTROL 0x105d +#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e +#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_LUT_DATA 0x105f +#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 +#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 +#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 +#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 +#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f +#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 +#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 +#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 +#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 +#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 +#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 +#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 +#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 +#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a +#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b +#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c +#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d +#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e +#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f +#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 +#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 +#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 +#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 +#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 +#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 +#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c +#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 +#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 +#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 +#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 +#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 +#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 +#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a +#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b +#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c +#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d +#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e +#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f +#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 +#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 +#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 +#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 +#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 +#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 +#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_HDR_MULT_COEF 0x10a7 +#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL 0x10a8 +#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS 0x10a9 +#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM2_CM_DEALPHA 0x10ab +#define regCM2_CM_DEALPHA_BASE_IDX 2 +#define regCM2_CM_COEF_FORMAT 0x10ac +#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM2_CM_SHAPER_CONTROL 0x10ad +#define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 +#define regCM2_CM_SHAPER_OFFSET_R 0x10ae +#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_OFFSET_G 0x10af +#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_SHAPER_OFFSET_B 0x10b0 +#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_SCALE_R 0x10b1 +#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 +#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 +#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_SHAPER_LUT_DATA 0x10b4 +#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 +#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 +#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 +#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba +#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb +#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc +#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd +#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be +#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf +#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 +#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 +#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 +#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 +#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 +#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 +#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 +#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 +#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 +#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 +#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca +#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb +#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc +#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd +#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce +#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf +#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 +#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 +#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 +#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 +#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 +#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 +#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 +#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 +#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da +#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db +#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc +#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd +#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de +#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df +#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 +#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 +#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 +#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 +#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL2 0x10e4 +#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS2 0x10e5 +#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define regCM2_CM_3DLUT_MODE 0x10e6 +#define regCM2_CM_3DLUT_MODE_BASE_IDX 2 +#define regCM2_CM_3DLUT_INDEX 0x10e7 +#define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 +#define regCM2_CM_3DLUT_DATA 0x10e8 +#define regCM2_CM_3DLUT_DATA_BASE_IDX 2 +#define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 +#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea +#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb +#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec +#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed +#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee +#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_INDEX 0x10ef +#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_DATA 0x10f0 +#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define regDPP_TOP2_DPP_CONTROL 0x0f9b +#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d +#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e +#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f +#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 +#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x43e8 +#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa +#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb +#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc +#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL 0x10fd +#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL2 0x10fe +#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 +#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_HI 0x1101 +#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_LOW 0x1102 +#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 +#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 +#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 +#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 +#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 +#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 +#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 +#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a +#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b +#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c +#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e +#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEALPHA 0x111f +#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 +#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 +#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 +#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 +#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 +#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 +#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 +#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a +#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b +#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c +#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d +#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEGAM 0x112e +#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG3_PRE_REALPHA 0x112f +#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +// base address: 0x1104 +#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 +#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 +#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 +#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 +#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b +#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL3_SCL_MODE 0x113c +#define regDSCL3_SCL_MODE_BASE_IDX 2 +#define regDSCL3_SCL_TAP_CONTROL 0x113d +#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_CONTROL 0x113e +#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_2TAP_CONTROL 0x113f +#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 +#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 +#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 +#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL3_SCL_BLACK_COLOR 0x114b +#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL3_DSCL_UPDATE 0x114c +#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL3_DSCL_AUTOCAL 0x114d +#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL3_OTG_H_BLANK 0x1150 +#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL3_OTG_V_BLANK 0x1151 +#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL3_RECOUT_START 0x1152 +#define regDSCL3_RECOUT_START_BASE_IDX 2 +#define regDSCL3_RECOUT_SIZE 0x1153 +#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL3_MPC_SIZE 0x1154 +#define regDSCL3_MPC_SIZE_BASE_IDX 2 +#define regDSCL3_LB_DATA_FORMAT 0x1155 +#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL3_LB_MEMORY_CTRL 0x1156 +#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL3_LB_V_COUNTER 0x1157 +#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 +#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 +#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL3_OBUF_CONTROL 0x115a +#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b +#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define regCM3_CM_CONTROL 0x1161 +#define regCM3_CM_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_CONTROL 0x1162 +#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C11_C12 0x1163 +#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C13_C14 0x1164 +#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C21_C22 0x1165 +#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C23_C24 0x1166 +#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C31_C32 0x1167 +#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C33_C34 0x1168 +#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 +#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C13_C14 0x116a +#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C21_C22 0x116b +#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C23_C24 0x116c +#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C31_C32 0x116d +#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C33_C34 0x116e +#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f +#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 +#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 +#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 +#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 +#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 +#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 +#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 +#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 +#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 +#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 +#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a +#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b +#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_BIAS_CR_R 0x117c +#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM3_CM_BIAS_Y_G_CB_B 0x117d +#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_CONTROL 0x117e +#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f +#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 +#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 +#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_CONTROL 0x11c8 +#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 +#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca +#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb +#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce +#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 +#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 +#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da +#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd +#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de +#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df +#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 +#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 +#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 +#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 +#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 +#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 +#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 +#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 +#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 +#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea +#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb +#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec +#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed +#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee +#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 +#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 +#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 +#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd +#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 +#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 +#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 +#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 +#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 +#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 +#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 +#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 +#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 +#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 +#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a +#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b +#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c +#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d +#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e +#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f +#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 +#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 +#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_HDR_MULT_COEF 0x1212 +#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL 0x1213 +#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS 0x1214 +#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM3_CM_DEALPHA 0x1216 +#define regCM3_CM_DEALPHA_BASE_IDX 2 +#define regCM3_CM_COEF_FORMAT 0x1217 +#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM3_CM_SHAPER_CONTROL 0x1218 +#define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 +#define regCM3_CM_SHAPER_OFFSET_R 0x1219 +#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_OFFSET_G 0x121a +#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_SHAPER_OFFSET_B 0x121b +#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_SCALE_R 0x121c +#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_SCALE_G_B 0x121d +#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_LUT_INDEX 0x121e +#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_SHAPER_LUT_DATA 0x121f +#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 +#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 +#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 +#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 +#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 +#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 +#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a +#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b +#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c +#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d +#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e +#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f +#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 +#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 +#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 +#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 +#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 +#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 +#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 +#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 +#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 +#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 +#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a +#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b +#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c +#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d +#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e +#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f +#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 +#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 +#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 +#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 +#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 +#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 +#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 +#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 +#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 +#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 +#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a +#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b +#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c +#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d +#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e +#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL2 0x124f +#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS2 0x1250 +#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define regCM3_CM_3DLUT_MODE 0x1251 +#define regCM3_CM_3DLUT_MODE_BASE_IDX 2 +#define regCM3_CM_3DLUT_INDEX 0x1252 +#define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 +#define regCM3_CM_3DLUT_DATA 0x1253 +#define regCM3_CM_3DLUT_DATA_BASE_IDX 2 +#define regCM3_CM_3DLUT_DATA_30BIT 0x1254 +#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 +#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 +#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 +#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 +#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 +#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_INDEX 0x125a +#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_DATA 0x125b +#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define regDPP_TOP3_DPP_CONTROL 0x1106 +#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 +#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 +#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_CTRL 0x110a +#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP3_HOST_READ_CONTROL 0x110b +#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x4994 +#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 +#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 +#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 +#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL 0x1268 +#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL2 0x1269 +#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b +#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_HI 0x126c +#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_LOW 0x126d +#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define regMPCC0_MPCC_TOP_SEL 0x0000 +#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_SEL 0x0001 +#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_OPP_ID 0x0002 +#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL 0x0003 +#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_SM_CONTROL 0x0004 +#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_TOP_GAIN 0x0006 +#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BG_R_CR 0x0009 +#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC0_MPCC_BG_G_Y 0x000a +#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC0_MPCC_BG_B_CB 0x000b +#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c +#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC0_MPCC_STATUS 0x000d +#define regMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x80 +#define regMPCC1_MPCC_TOP_SEL 0x0020 +#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_SEL 0x0021 +#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_OPP_ID 0x0022 +#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL 0x0023 +#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_SM_CONTROL 0x0024 +#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_TOP_GAIN 0x0026 +#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BG_R_CR 0x0029 +#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC1_MPCC_BG_G_Y 0x002a +#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC1_MPCC_BG_B_CB 0x002b +#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c +#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC1_MPCC_STATUS 0x002d +#define regMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0x100 +#define regMPCC2_MPCC_TOP_SEL 0x0040 +#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_SEL 0x0041 +#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_OPP_ID 0x0042 +#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL 0x0043 +#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_SM_CONTROL 0x0044 +#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_TOP_GAIN 0x0046 +#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BG_R_CR 0x0049 +#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC2_MPCC_BG_G_Y 0x004a +#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC2_MPCC_BG_B_CB 0x004b +#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c +#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC2_MPCC_STATUS 0x004d +#define regMPCC2_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0x180 +#define regMPCC3_MPCC_TOP_SEL 0x0060 +#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_SEL 0x0061 +#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_OPP_ID 0x0062 +#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL 0x0063 +#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_SM_CONTROL 0x0064 +#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_TOP_GAIN 0x0066 +#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BG_R_CR 0x0069 +#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC3_MPCC_BG_G_Y 0x006a +#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC3_MPCC_BG_B_CB 0x006b +#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c +#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC3_MPCC_STATUS 0x006d +#define regMPCC3_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define regMPC_CLOCK_CONTROL 0x0500 +#define regMPC_CLOCK_CONTROL_BASE_IDX 3 +#define regMPC_SOFT_RESET 0x0501 +#define regMPC_SOFT_RESET_BASE_IDX 3 +#define regMPC_CRC_CTRL 0x0502 +#define regMPC_CRC_CTRL_BASE_IDX 3 +#define regMPC_CRC_SEL_CONTROL 0x0503 +#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define regMPC_CRC_RESULT_AR 0x0504 +#define regMPC_CRC_RESULT_AR_BASE_IDX 3 +#define regMPC_CRC_RESULT_GB 0x0505 +#define regMPC_CRC_RESULT_GB_BASE_IDX 3 +#define regMPC_CRC_RESULT_C 0x0506 +#define regMPC_CRC_RESULT_C_BASE_IDX 3 +#define regMPC_PERFMON_EVENT_CTRL 0x0509 +#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 +#define regMPC_BYPASS_BG_AR 0x050a +#define regMPC_BYPASS_BG_AR_BASE_IDX 3 +#define regMPC_BYPASS_BG_GB 0x050b +#define regMPC_BYPASS_BG_GB_BASE_IDX 3 +#define regMPC_HOST_READ_CONTROL 0x050c +#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define regMPC_DPP_PENDING_STATUS 0x050d +#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define regMPC_PENDING_STATUS_MISC 0x050e +#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 +#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET0 0x0511 +#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET0 0x0512 +#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET0 0x0513 +#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 +#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET1 0x0516 +#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET1 0x0517 +#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET1 0x0518 +#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET2 0x051a +#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET2 0x051b +#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET2 0x051c +#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET2 0x051d +#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET3 0x051f +#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET3 0x0520 +#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET3 0x0521 +#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET3 0x0522 +#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regMPC_DWB0_MUX 0x055c +#define regMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x1901c +#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 +#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 +#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 +#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_CNTL 0x08ca +#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_CNTL2 0x08cb +#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd +#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_HI 0x08ce +#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON15_PERFMON_LOW 0x08cf +#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x200 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x400 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x600 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define regMPC_OUT0_MUX 0x0580 +#define regMPC_OUT0_MUX_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CONTROL 0x0581 +#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 +#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 +#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT1_MUX 0x0584 +#define regMPC_OUT1_MUX_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CONTROL 0x0585 +#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 +#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 +#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT2_MUX 0x0588 +#define regMPC_OUT2_MUX_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CONTROL 0x0589 +#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a +#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b +#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT3_MUX 0x058c +#define regMPC_OUT3_MUX_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CONTROL 0x058d +#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e +#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f +#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 +#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define regMPC_OUT0_CSC_MODE 0x05a1 +#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_A 0x05a2 +#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_A 0x05a3 +#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_A 0x05a4 +#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_A 0x05a5 +#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_A 0x05a6 +#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_A 0x05a7 +#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_B 0x05a8 +#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_B 0x05a9 +#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_B 0x05aa +#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_B 0x05ab +#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_B 0x05ac +#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_B 0x05ad +#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_MODE 0x05ae +#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_A 0x05af +#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_A 0x05b0 +#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_A 0x05b1 +#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_A 0x05b2 +#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_A 0x05b3 +#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_A 0x05b4 +#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_B 0x05b5 +#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_B 0x05b6 +#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_B 0x05b7 +#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_B 0x05b8 +#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_B 0x05b9 +#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_B 0x05ba +#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_MODE 0x05bb +#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_A 0x05bc +#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_A 0x05bd +#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_A 0x05be +#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_A 0x05bf +#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_A 0x05c0 +#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_A 0x05c1 +#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_B 0x05c2 +#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_B 0x05c3 +#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_B 0x05c4 +#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_B 0x05c5 +#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_B 0x05c6 +#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_B 0x05c7 +#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_MODE 0x05c8 +#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_A 0x05c9 +#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_A 0x05ca +#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_A 0x05cb +#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_A 0x05cc +#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_A 0x05cd +#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_A 0x05ce +#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_B 0x05cf +#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_B 0x05d0 +#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_B 0x05d1 +#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_B 0x05d2 +#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_B 0x05d3 +#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_B 0x05d4 +#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmu_dispdec +// base address: 0x0 +#define regMPC_RMU_CONTROL 0x0680 +#define regMPC_RMU_CONTROL_BASE_IDX 3 +#define regMPC_RMU_MEM_PWR_CTRL 0x0681 +#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_CONTROL 0x0682 +#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 +#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 +#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 +#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_SCALE_R 0x0686 +#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 +#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 +#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 +#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a +#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d +#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 +#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 +#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 +#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 +#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 +#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 +#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 +#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 +#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 +#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 +#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a +#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b +#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c +#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d +#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e +#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f +#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 +#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 +#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 +#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 +#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 +#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 +#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa +#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab +#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac +#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad +#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae +#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af +#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 +#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 +#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 +#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 +#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 +#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 +#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 +#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 +#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_MODE 0x06b9 +#define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_INDEX 0x06ba +#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_DATA 0x06bb +#define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc +#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd +#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be +#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf +#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 +#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 +#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_CONTROL 0x06c2 +#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 +#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 +#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 +#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 +#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 +#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 +#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 +#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca +#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd +#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 +#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 +#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 +#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 +#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 +#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 +#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 +#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 +#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 +#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da +#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db +#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc +#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd +#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de +#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df +#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 +#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 +#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 +#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 +#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 +#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 +#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea +#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb +#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec +#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed +#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee +#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef +#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 +#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 +#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 +#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 +#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 +#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 +#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 +#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 +#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_MODE 0x06f9 +#define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_INDEX 0x06fa +#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_DATA 0x06fb +#define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc +#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd +#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe +#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff +#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 +#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 +#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 +#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM0_DC_ABM1_CNTL 0x0e83 +#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a +#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b +#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c +#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f +#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e +#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f +#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 +#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 +#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 +#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 +#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 +#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 +#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 +#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 +#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 +#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 +#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa +#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab +#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac +#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead +#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae +#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf +#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 +#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 +#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 +#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 +#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 +#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 +#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 +#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x104 +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 +#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM1_DC_ABM1_CNTL 0x0ec4 +#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb +#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc +#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd +#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 +#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf +#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 +#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 +#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 +#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 +#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 +#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 +#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 +#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 +#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 +#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 +#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea +#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb +#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec +#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed +#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee +#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef +#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 +#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 +#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 +#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 +#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 +#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 +#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 +#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 +#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm2_dispdec +// base address: 0x208 +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_USER_LEVEL 0x0efd +#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 +#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 +#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM2_DC_ABM1_CNTL 0x0f05 +#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c +#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d +#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e +#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 +#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a +#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 +#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 +#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 +#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 +#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 +#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 +#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 +#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 +#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 +#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 +#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a +#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b +#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c +#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d +#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e +#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f +#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 +#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 +#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 +#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 +#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 +#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 +#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 +#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 +#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 +#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm3_dispdec +// base address: 0x30c +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e +#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 +#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 +#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 +#define regABM3_DC_ABM1_CNTL 0x0f46 +#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d +#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e +#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f +#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 +#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a +#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b +#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 +#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 +#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 +#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 +#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 +#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 +#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 +#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 +#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 +#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a +#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b +#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c +#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d +#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e +#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f +#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 +#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 +#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 +#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 +#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 +#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 +#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 +#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 +#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 +#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 +#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 +#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define regDPG0_DPG_CONTROL 0x1854 +#define regDPG0_DPG_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_RAMP_CONTROL 0x1855 +#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_DIMENSIONS 0x1856 +#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_R_CR 0x1857 +#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_G_Y 0x1858 +#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_B_CB 0x1859 +#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG0_DPG_OFFSET_SEGMENT 0x185a +#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG0_DPG_STATUS 0x185b +#define regDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_CONTROL 0x1840 +#define regFMT0_FMT_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_CNTL 0x1845 +#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_422_CONTROL 0x1849 +#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define regOPPBUF0_OPPBUF_CONTROL 0x1884 +#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define regDPG1_DPG_CONTROL 0x18ae +#define regDPG1_DPG_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_RAMP_CONTROL 0x18af +#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_DIMENSIONS 0x18b0 +#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_R_CR 0x18b1 +#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_G_Y 0x18b2 +#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_B_CB 0x18b3 +#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG1_DPG_STATUS 0x18b5 +#define regDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_CONTROL 0x189a +#define regFMT1_FMT_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_CNTL 0x189f +#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_422_CONTROL 0x18a3 +#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define regOPPBUF1_OPPBUF_CONTROL 0x18de +#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define regDPG2_DPG_CONTROL 0x1908 +#define regDPG2_DPG_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_RAMP_CONTROL 0x1909 +#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_DIMENSIONS 0x190a +#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_R_CR 0x190b +#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_G_Y 0x190c +#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_B_CB 0x190d +#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG2_DPG_OFFSET_SEGMENT 0x190e +#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG2_DPG_STATUS 0x190f +#define regDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_CONTROL 0x18f4 +#define regFMT2_FMT_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_CNTL 0x18f9 +#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_422_CONTROL 0x18fd +#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define regOPPBUF2_OPPBUF_CONTROL 0x1938 +#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_CONTROL1 0x193d +#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 +#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg3_dispdec +// base address: 0x438 +#define regDPG3_DPG_CONTROL 0x1962 +#define regDPG3_DPG_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_RAMP_CONTROL 0x1963 +#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_DIMENSIONS 0x1964 +#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_R_CR 0x1965 +#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_G_Y 0x1966 +#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_B_CB 0x1967 +#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG3_DPG_STATUS 0x1969 +#define regDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_CONTROL 0x194e +#define regFMT3_FMT_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_CNTL 0x1953 +#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_422_CONTROL 0x1957 +#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define regOPPBUF3_OPPBUF_CONTROL 0x1992 +#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a +#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define regOPP_TOP_CLK_CONTROL 0x1a5e +#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define regOPP_ABM_CONTROL 0x1a60 +#define regOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe +#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf +#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 +#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 +#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 +#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 +#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_HI 0x1ac5 +#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_LOW 0x1ac6 +#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc +#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd +#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL 0x1ace +#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf +#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 +#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 +#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc +#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add +#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL 0x1ade +#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf +#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 +#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 +#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb +#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec +#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed +#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL 0x1aee +#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef +#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 +#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 +#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb +#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc +#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd +#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL 0x1afe +#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff +#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 +#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 +#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define regOTG0_OTG_H_TOTAL 0x1b2a +#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_H_BLANK_START_END 0x1b2b +#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A 0x1b2c +#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL 0x1b2f +#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MID 0x1b32 +#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_V_BLANK_START_END 0x1b36 +#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A 0x1b37 +#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_CNTL 0x1b39 +#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_CNTL 0x1b3b +#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG0_OTG_FLOW_CONTROL 0x1b3e +#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG0_OTG_CONTROL 0x1b41 +#define regOTG0_OTG_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG0_OTG_STATUS 0x1b49 +#define regOTG0_OTG_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STATUS_POSITION 0x1b4a +#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG0_OTG_COUNT_CONTROL 0x1b4f +#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_COUNT_RESET 0x1b50 +#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_STATUS 0x1b53 +#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STEREO_CONTROL 0x1b54 +#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_UPDATE_LOCK 0x1b5a +#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MASTER_EN 0x1b5c +#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL 0x1b68 +#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL2 0x1b69 +#define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_RG 0x1b6e +#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_B 0x1b6f +#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_RG 0x1b74 +#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_B 0x1b75 +#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_RG 0x1b76 +#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_B 0x1b77 +#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_RG 0x1b78 +#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_B 0x1b79 +#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 +#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 +#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG0_OTG_CLOCK_CONTROL 0x1b86 +#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 +#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_PARAM 0x1b88 +#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VREADY_PARAM 0x1b89 +#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a +#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b +#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_GSL_CONTROL 0x1b8c +#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_X 0x1b8d +#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e +#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f +#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 +#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 +#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 +#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 +#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 +#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 +#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a +#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTROL 0x1b9b +#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO0 0x1b9c +#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO1 0x1b9d +#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG0_OTG_REQUEST_CONTROL 0x1b9e +#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DSC_START_POSITION 0x1b9f +#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 +#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SPARE_REGISTER 0x1ba2 +#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x200 +#define regOTG1_OTG_H_TOTAL 0x1baa +#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_H_BLANK_START_END 0x1bab +#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A 0x1bac +#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_H_TIMING_CNTL 0x1bae +#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL 0x1baf +#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A 0x1bb7 +#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_CNTL 0x1bbb +#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG1_OTG_FLOW_CONTROL 0x1bbe +#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG1_OTG_CONTROL 0x1bc1 +#define regOTG1_OTG_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG1_OTG_STATUS 0x1bc9 +#define regOTG1_OTG_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STATUS_POSITION 0x1bca +#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG1_OTG_COUNT_CONTROL 0x1bcf +#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_COUNT_RESET 0x1bd0 +#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_STATUS 0x1bd3 +#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_UPDATE_LOCK 0x1bda +#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MASTER_EN 0x1bdc +#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL 0x1be8 +#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL2 0x1be9 +#define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_RG 0x1bee +#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_B 0x1bef +#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 +#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_B 0x1bf5 +#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 +#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_B 0x1bf7 +#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 +#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_B 0x1bf9 +#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 +#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 +#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG1_OTG_CLOCK_CONTROL 0x1c06 +#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 +#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_PARAM 0x1c08 +#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VREADY_PARAM 0x1c09 +#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a +#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b +#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_GSL_CONTROL 0x1c0c +#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_X 0x1c0d +#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e +#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f +#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 +#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 +#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 +#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 +#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 +#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 +#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a +#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTROL 0x1c1b +#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO0 0x1c1c +#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO1 0x1c1d +#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG1_OTG_REQUEST_CONTROL 0x1c1e +#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DSC_START_POSITION 0x1c1f +#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 +#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SPARE_REGISTER 0x1c22 +#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x400 +#define regOTG2_OTG_H_TOTAL 0x1c2a +#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_H_BLANK_START_END 0x1c2b +#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A 0x1c2c +#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d +#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e +#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL 0x1c2f +#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 +#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 +#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MID 0x1c32 +#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 +#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 +#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_V_BLANK_START_END 0x1c36 +#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A 0x1c37 +#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 +#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_CNTL 0x1c39 +#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a +#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_CNTL 0x1c3b +#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c +#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG2_OTG_FLOW_CONTROL 0x1c3e +#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG2_OTG_CONTROL 0x1c41 +#define regOTG2_OTG_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 +#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 +#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 +#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 +#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG2_OTG_STATUS 0x1c49 +#define regOTG2_OTG_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STATUS_POSITION 0x1c4a +#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b +#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c +#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d +#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e +#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG2_OTG_COUNT_CONTROL 0x1c4f +#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_COUNT_RESET 0x1c50 +#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 +#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_STATUS 0x1c53 +#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STEREO_CONTROL 0x1c54 +#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 +#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 +#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 +#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 +#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 +#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_UPDATE_LOCK 0x1c5a +#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MASTER_EN 0x1c5c +#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL 0x1c68 +#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL2 0x1c69 +#define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_RG 0x1c6e +#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_B 0x1c6f +#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_RG 0x1c74 +#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_B 0x1c75 +#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_RG 0x1c76 +#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_B 0x1c77 +#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_RG 0x1c78 +#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_B 0x1c79 +#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 +#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 +#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG2_OTG_CLOCK_CONTROL 0x1c86 +#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 +#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_PARAM 0x1c88 +#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VREADY_PARAM 0x1c89 +#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a +#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b +#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_GSL_CONTROL 0x1c8c +#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_X 0x1c8d +#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e +#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f +#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 +#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 +#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 +#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 +#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 +#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 +#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a +#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTROL 0x1c9b +#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO0 0x1c9c +#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO1 0x1c9d +#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG2_OTG_REQUEST_CONTROL 0x1c9e +#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DSC_START_POSITION 0x1c9f +#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 +#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SPARE_REGISTER 0x1ca2 +#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x600 +#define regOTG3_OTG_H_TOTAL 0x1caa +#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_H_BLANK_START_END 0x1cab +#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A 0x1cac +#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad +#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_H_TIMING_CNTL 0x1cae +#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL 0x1caf +#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 +#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 +#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 +#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 +#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 +#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 +#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A 0x1cb7 +#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 +#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 +#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba +#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_CNTL 0x1cbb +#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc +#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG3_OTG_FLOW_CONTROL 0x1cbe +#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG3_OTG_CONTROL 0x1cc1 +#define regOTG3_OTG_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 +#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 +#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 +#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 +#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG3_OTG_STATUS 0x1cc9 +#define regOTG3_OTG_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STATUS_POSITION 0x1cca +#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb +#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc +#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd +#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce +#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG3_OTG_COUNT_CONTROL 0x1ccf +#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_COUNT_RESET 0x1cd0 +#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 +#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_STATUS 0x1cd3 +#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 +#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 +#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 +#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 +#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 +#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 +#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_UPDATE_LOCK 0x1cda +#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MASTER_EN 0x1cdc +#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL 0x1ce8 +#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL2 0x1ce9 +#define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_RG 0x1cee +#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_B 0x1cef +#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 +#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_B 0x1cf5 +#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 +#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_B 0x1cf7 +#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 +#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_B 0x1cf9 +#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 +#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 +#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG3_OTG_CLOCK_CONTROL 0x1d06 +#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 +#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_PARAM 0x1d08 +#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VREADY_PARAM 0x1d09 +#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a +#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b +#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_GSL_CONTROL 0x1d0c +#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_X 0x1d0d +#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e +#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f +#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 +#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 +#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 +#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 +#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 +#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 +#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a +#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTROL 0x1d1b +#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO0 0x1d1c +#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO1 0x1d1d +#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG3_OTG_REQUEST_CONTROL 0x1d1e +#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DSC_START_POSITION 0x1d1f +#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 +#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 +#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SPARE_REGISTER 0x1d22 +#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define regDWB_SOURCE_SELECT 0x1e2a +#define regDWB_SOURCE_SELECT_BASE_IDX 2 +#define regGSL_SOURCE_SELECT 0x1e2b +#define regGSL_SOURCE_SELECT_BASE_IDX 2 +#define regOPTC_CLOCK_CONTROL 0x1e2c +#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL 0x1e2d +#define regODM_MEM_PWR_CTRL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL3 0x1e2f +#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define regODM_MEM_PWR_STATUS 0x1e30 +#define regODM_MEM_PWR_STATUS_BASE_IDX 2 +#define regOPTC_MISC_SPARE_REGISTER 0x1e31 +#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a +#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b +#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c +#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL 0x1e6d +#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e +#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_HI 0x1e71 +#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_LOW 0x1e72 +#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +// base address: 0x0 +#define regHPD0_DC_HPD_INT_STATUS 0x1f14 +#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_CONTROL 0x1f16 +#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +// base address: 0x20 +#define regHPD1_DC_HPD_INT_STATUS 0x1f1c +#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_CONTROL 0x1f1e +#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd2_dispdec +// base address: 0x40 +#define regHPD2_DC_HPD_INT_STATUS 0x1f24 +#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 +#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_CONTROL 0x1f26 +#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd3_dispdec +// base address: 0x60 +#define regHPD3_DC_HPD_INT_STATUS 0x1f2c +#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d +#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_CONTROL 0x1f2e +#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd4_dispdec +// base address: 0x80 +#define regHPD4_DC_HPD_INT_STATUS 0x1f34 +#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 +#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_CONTROL 0x1f36 +#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define regDP0_DP_LINK_CNTL 0x2108 +#define regDP0_DP_LINK_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT 0x2109 +#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP0_DP_MSA_COLORIMETRY 0x210a +#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP0_DP_CONFIG 0x210b +#define regDP0_DP_CONFIG_BASE_IDX 2 +#define regDP0_DP_VID_STREAM_CNTL 0x210c +#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO 0x210d +#define regDP0_DP_STEER_FIFO_BASE_IDX 2 +#define regDP0_DP_MSA_MISC 0x210e +#define regDP0_DP_MSA_MISC_BASE_IDX 2 +#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f +#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP0_DP_VID_TIMING 0x2110 +#define regDP0_DP_VID_TIMING_BASE_IDX 2 +#define regDP0_DP_VID_N 0x2111 +#define regDP0_DP_VID_N_BASE_IDX 2 +#define regDP0_DP_VID_M 0x2112 +#define regDP0_DP_VID_M_BASE_IDX 2 +#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP0_DP_VID_MSA_VBID 0x2115 +#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CNTL 0x2117 +#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM0 0x2119 +#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM1 0x211a +#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM2 0x211b +#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP0_DP_DPHY_8B10B_CNTL 0x211c +#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_PRBS_CNTL 0x211d +#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_EN 0x211f +#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CNTL 0x2120 +#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT 0x2121 +#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL 0x212b +#define regDP0_DP_SEC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL1 0x212c +#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING1 0x212d +#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING2 0x212e +#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING3 0x212f +#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING4 0x2130 +#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N 0x2131 +#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M 0x2133 +#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_TIMESTAMP 0x2135 +#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP0_DP_SEC_PACKET_CNTL 0x2136 +#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_CNTL 0x2137 +#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_UPDATE 0x2139 +#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0 0x213a +#define regDP0_DP_MSE_SAT0_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1 0x213b +#define regDP0_DP_MSE_SAT1_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2 0x213c +#define regDP0_DP_MSE_SAT2_BASE_IDX 2 +#define regDP0_DP_MSE_SAT_UPDATE 0x213d +#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_LINK_TIMING 0x213e +#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP0_DP_MSE_MISC_CNTL 0x213f +#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0_STATUS 0x2147 +#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1_STATUS 0x2148 +#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2_STATUS 0x2149 +#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM1 0x214c +#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM2 0x214d +#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM3 0x214e +#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM4 0x214f +#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL 0x2150 +#define regDP0_DP_MSO_CNTL_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL1 0x2151 +#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP0_DP_DSC_CNTL 0x2152 +#define regDP0_DP_DSC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL2 0x2153 +#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL3 0x2154 +#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL4 0x2155 +#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL5 0x2156 +#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL6 0x2157 +#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL7 0x2158 +#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP0_DP_DB_CNTL 0x2159 +#define regDP0_DP_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_MSA_VBID_MISC 0x215a +#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b +#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c +#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regDP0_DP_ALPM_CNTL 0x215d +#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP8_CNTL 0x215e +#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP9_CNTL 0x215f +#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP10_CNTL 0x2160 +#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP11_CNTL 0x2161 +#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 +#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define regDIG0_DIG_FE_CNTL 0x208b +#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c +#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d +#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG0_DIG_CLOCK_PATTERN 0x208e +#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_TEST_PATTERN 0x208f +#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 +#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG0_DIG_FIFO_STATUS 0x2091 +#define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_CONTROL 0x2093 +#define regDIG0_HDMI_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_STATUS 0x2094 +#define regDIG0_HDMI_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 +#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 +#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 +#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 +#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG0_HDMI_GC 0x209d +#define regDIG0_HDMI_GC_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG0_HDMI_DB_CONTROL 0x20a6 +#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_0 0x20a7 +#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_1 0x20a8 +#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_0 0x20a9 +#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_1 0x20aa +#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_0 0x20ab +#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_1 0x20ac +#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_0 0x20ad +#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_1 0x20ae +#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG0_AFMT_CNTL 0x20af +#define regDIG0_AFMT_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CNTL 0x20b0 +#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_EN_CNTL 0x20b1 +#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CNTL 0x20d7 +#define regDIG0_TMDS_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL_CHAR 0x20d8 +#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 +#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG0_TMDS_CTL_BITS 0x20de +#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df +#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_VERSION 0x20e4 +#define regDIG0_DIG_VERSION_BASE_IDX 2 +#define regDIG0_FORCE_DIG_DISABLE 0x20e5 +#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x400 +#define regDP1_DP_LINK_CNTL 0x2208 +#define regDP1_DP_LINK_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT 0x2209 +#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP1_DP_MSA_COLORIMETRY 0x220a +#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP1_DP_CONFIG 0x220b +#define regDP1_DP_CONFIG_BASE_IDX 2 +#define regDP1_DP_VID_STREAM_CNTL 0x220c +#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO 0x220d +#define regDP1_DP_STEER_FIFO_BASE_IDX 2 +#define regDP1_DP_MSA_MISC 0x220e +#define regDP1_DP_MSA_MISC_BASE_IDX 2 +#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f +#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP1_DP_VID_TIMING 0x2210 +#define regDP1_DP_VID_TIMING_BASE_IDX 2 +#define regDP1_DP_VID_N 0x2211 +#define regDP1_DP_VID_N_BASE_IDX 2 +#define regDP1_DP_VID_M 0x2212 +#define regDP1_DP_VID_M_BASE_IDX 2 +#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP1_DP_VID_MSA_VBID 0x2215 +#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CNTL 0x2217 +#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM0 0x2219 +#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM1 0x221a +#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM2 0x221b +#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP1_DP_DPHY_8B10B_CNTL 0x221c +#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_PRBS_CNTL 0x221d +#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_EN 0x221f +#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CNTL 0x2220 +#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT 0x2221 +#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL 0x222b +#define regDP1_DP_SEC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL1 0x222c +#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING1 0x222d +#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING2 0x222e +#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING3 0x222f +#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING4 0x2230 +#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N 0x2231 +#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M 0x2233 +#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_TIMESTAMP 0x2235 +#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP1_DP_SEC_PACKET_CNTL 0x2236 +#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_CNTL 0x2237 +#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_UPDATE 0x2239 +#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0 0x223a +#define regDP1_DP_MSE_SAT0_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1 0x223b +#define regDP1_DP_MSE_SAT1_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2 0x223c +#define regDP1_DP_MSE_SAT2_BASE_IDX 2 +#define regDP1_DP_MSE_SAT_UPDATE 0x223d +#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_LINK_TIMING 0x223e +#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP1_DP_MSE_MISC_CNTL 0x223f +#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0_STATUS 0x2247 +#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1_STATUS 0x2248 +#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2_STATUS 0x2249 +#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM1 0x224c +#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM2 0x224d +#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM3 0x224e +#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM4 0x224f +#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL 0x2250 +#define regDP1_DP_MSO_CNTL_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL1 0x2251 +#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP1_DP_DSC_CNTL 0x2252 +#define regDP1_DP_DSC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL2 0x2253 +#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL3 0x2254 +#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL4 0x2255 +#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL5 0x2256 +#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL6 0x2257 +#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL7 0x2258 +#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP1_DP_DB_CNTL 0x2259 +#define regDP1_DP_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_MSA_VBID_MISC 0x225a +#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b +#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c +#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regDP1_DP_ALPM_CNTL 0x225d +#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP8_CNTL 0x225e +#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP9_CNTL 0x225f +#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP10_CNTL 0x2260 +#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP11_CNTL 0x2261 +#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 +#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x400 +#define regDIG1_DIG_FE_CNTL 0x218b +#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c +#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d +#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG1_DIG_CLOCK_PATTERN 0x218e +#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_TEST_PATTERN 0x218f +#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 +#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG1_DIG_FIFO_STATUS 0x2191 +#define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_CONTROL 0x2193 +#define regDIG1_HDMI_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_STATUS 0x2194 +#define regDIG1_HDMI_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 +#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 +#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 +#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 +#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG1_HDMI_GC 0x219d +#define regDIG1_HDMI_GC_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG1_HDMI_DB_CONTROL 0x21a6 +#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_0 0x21a7 +#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_1 0x21a8 +#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_0 0x21a9 +#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_1 0x21aa +#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_0 0x21ab +#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_1 0x21ac +#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_0 0x21ad +#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_1 0x21ae +#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG1_AFMT_CNTL 0x21af +#define regDIG1_AFMT_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CNTL 0x21b0 +#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_EN_CNTL 0x21b1 +#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CNTL 0x21d7 +#define regDIG1_TMDS_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL_CHAR 0x21d8 +#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 +#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG1_TMDS_CTL_BITS 0x21de +#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df +#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_VERSION 0x21e4 +#define regDIG1_DIG_VERSION_BASE_IDX 2 +#define regDIG1_FORCE_DIG_DISABLE 0x21e5 +#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x800 +#define regDP2_DP_LINK_CNTL 0x2308 +#define regDP2_DP_LINK_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT 0x2309 +#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP2_DP_MSA_COLORIMETRY 0x230a +#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP2_DP_CONFIG 0x230b +#define regDP2_DP_CONFIG_BASE_IDX 2 +#define regDP2_DP_VID_STREAM_CNTL 0x230c +#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO 0x230d +#define regDP2_DP_STEER_FIFO_BASE_IDX 2 +#define regDP2_DP_MSA_MISC 0x230e +#define regDP2_DP_MSA_MISC_BASE_IDX 2 +#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f +#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP2_DP_VID_TIMING 0x2310 +#define regDP2_DP_VID_TIMING_BASE_IDX 2 +#define regDP2_DP_VID_N 0x2311 +#define regDP2_DP_VID_N_BASE_IDX 2 +#define regDP2_DP_VID_M 0x2312 +#define regDP2_DP_VID_M_BASE_IDX 2 +#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 +#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 +#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP2_DP_VID_MSA_VBID 0x2315 +#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 +#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CNTL 0x2317 +#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM0 0x2319 +#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM1 0x231a +#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM2 0x231b +#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP2_DP_DPHY_8B10B_CNTL 0x231c +#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_PRBS_CNTL 0x231d +#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e +#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_EN 0x231f +#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CNTL 0x2320 +#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT 0x2321 +#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 +#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 +#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 +#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL 0x232b +#define regDP2_DP_SEC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL1 0x232c +#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING1 0x232d +#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING2 0x232e +#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING3 0x232f +#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING4 0x2330 +#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N 0x2331 +#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 +#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M 0x2333 +#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 +#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_TIMESTAMP 0x2335 +#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP2_DP_SEC_PACKET_CNTL 0x2336 +#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_CNTL 0x2337 +#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_UPDATE 0x2339 +#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0 0x233a +#define regDP2_DP_MSE_SAT0_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1 0x233b +#define regDP2_DP_MSE_SAT1_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2 0x233c +#define regDP2_DP_MSE_SAT2_BASE_IDX 2 +#define regDP2_DP_MSE_SAT_UPDATE 0x233d +#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_LINK_TIMING 0x233e +#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP2_DP_MSE_MISC_CNTL 0x233f +#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0_STATUS 0x2347 +#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1_STATUS 0x2348 +#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2_STATUS 0x2349 +#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM1 0x234c +#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM2 0x234d +#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM3 0x234e +#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM4 0x234f +#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL 0x2350 +#define regDP2_DP_MSO_CNTL_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL1 0x2351 +#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP2_DP_DSC_CNTL 0x2352 +#define regDP2_DP_DSC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL2 0x2353 +#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL3 0x2354 +#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL4 0x2355 +#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL5 0x2356 +#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL6 0x2357 +#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL7 0x2358 +#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP2_DP_DB_CNTL 0x2359 +#define regDP2_DP_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_MSA_VBID_MISC 0x235a +#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b +#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c +#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regDP2_DP_ALPM_CNTL 0x235d +#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP8_CNTL 0x235e +#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP9_CNTL 0x235f +#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP10_CNTL 0x2360 +#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP11_CNTL 0x2361 +#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 +#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x800 +#define regDIG2_DIG_FE_CNTL 0x228b +#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c +#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d +#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG2_DIG_CLOCK_PATTERN 0x228e +#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_TEST_PATTERN 0x228f +#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 +#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG2_DIG_FIFO_STATUS 0x2291 +#define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_CONTROL 0x2293 +#define regDIG2_HDMI_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_STATUS 0x2294 +#define regDIG2_HDMI_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 +#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 +#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 +#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 +#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG2_HDMI_GC 0x229d +#define regDIG2_HDMI_GC_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG2_HDMI_DB_CONTROL 0x22a6 +#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_0 0x22a7 +#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_1 0x22a8 +#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_0 0x22a9 +#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_1 0x22aa +#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_0 0x22ab +#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_1 0x22ac +#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_0 0x22ad +#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_1 0x22ae +#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG2_AFMT_CNTL 0x22af +#define regDIG2_AFMT_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CNTL 0x22b0 +#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_EN_CNTL 0x22b1 +#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CNTL 0x22d7 +#define regDIG2_TMDS_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL_CHAR 0x22d8 +#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 +#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG2_TMDS_CTL_BITS 0x22de +#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df +#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_VERSION 0x22e4 +#define regDIG2_DIG_VERSION_BASE_IDX 2 +#define regDIG2_FORCE_DIG_DISABLE 0x22e5 +#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xc00 +#define regDP3_DP_LINK_CNTL 0x2408 +#define regDP3_DP_LINK_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT 0x2409 +#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP3_DP_MSA_COLORIMETRY 0x240a +#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP3_DP_CONFIG 0x240b +#define regDP3_DP_CONFIG_BASE_IDX 2 +#define regDP3_DP_VID_STREAM_CNTL 0x240c +#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO 0x240d +#define regDP3_DP_STEER_FIFO_BASE_IDX 2 +#define regDP3_DP_MSA_MISC 0x240e +#define regDP3_DP_MSA_MISC_BASE_IDX 2 +#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f +#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP3_DP_VID_TIMING 0x2410 +#define regDP3_DP_VID_TIMING_BASE_IDX 2 +#define regDP3_DP_VID_N 0x2411 +#define regDP3_DP_VID_N_BASE_IDX 2 +#define regDP3_DP_VID_M 0x2412 +#define regDP3_DP_VID_M_BASE_IDX 2 +#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 +#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 +#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP3_DP_VID_MSA_VBID 0x2415 +#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 +#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CNTL 0x2417 +#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM0 0x2419 +#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM1 0x241a +#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM2 0x241b +#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP3_DP_DPHY_8B10B_CNTL 0x241c +#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_PRBS_CNTL 0x241d +#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e +#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_EN 0x241f +#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CNTL 0x2420 +#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT 0x2421 +#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 +#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 +#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 +#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL 0x242b +#define regDP3_DP_SEC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL1 0x242c +#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING1 0x242d +#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING2 0x242e +#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING3 0x242f +#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING4 0x2430 +#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N 0x2431 +#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 +#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M 0x2433 +#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 +#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_TIMESTAMP 0x2435 +#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP3_DP_SEC_PACKET_CNTL 0x2436 +#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_CNTL 0x2437 +#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_UPDATE 0x2439 +#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0 0x243a +#define regDP3_DP_MSE_SAT0_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1 0x243b +#define regDP3_DP_MSE_SAT1_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2 0x243c +#define regDP3_DP_MSE_SAT2_BASE_IDX 2 +#define regDP3_DP_MSE_SAT_UPDATE 0x243d +#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_LINK_TIMING 0x243e +#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP3_DP_MSE_MISC_CNTL 0x243f +#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0_STATUS 0x2447 +#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1_STATUS 0x2448 +#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2_STATUS 0x2449 +#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM1 0x244c +#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM2 0x244d +#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM3 0x244e +#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM4 0x244f +#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL 0x2450 +#define regDP3_DP_MSO_CNTL_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL1 0x2451 +#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP3_DP_DSC_CNTL 0x2452 +#define regDP3_DP_DSC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL2 0x2453 +#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL3 0x2454 +#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL4 0x2455 +#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL5 0x2456 +#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL6 0x2457 +#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL7 0x2458 +#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP3_DP_DB_CNTL 0x2459 +#define regDP3_DP_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_MSA_VBID_MISC 0x245a +#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b +#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c +#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regDP3_DP_ALPM_CNTL 0x245d +#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP8_CNTL 0x245e +#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP9_CNTL 0x245f +#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP10_CNTL 0x2460 +#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP11_CNTL 0x2461 +#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 +#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xc00 +#define regDIG3_DIG_FE_CNTL 0x238b +#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c +#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d +#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG3_DIG_CLOCK_PATTERN 0x238e +#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_TEST_PATTERN 0x238f +#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 +#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG3_DIG_FIFO_STATUS 0x2391 +#define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_CONTROL 0x2393 +#define regDIG3_HDMI_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_STATUS 0x2394 +#define regDIG3_HDMI_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 +#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 +#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 +#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 +#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG3_HDMI_GC 0x239d +#define regDIG3_HDMI_GC_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG3_HDMI_DB_CONTROL 0x23a6 +#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_0 0x23a7 +#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_1 0x23a8 +#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_0 0x23a9 +#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_1 0x23aa +#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_0 0x23ab +#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_1 0x23ac +#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_0 0x23ad +#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_1 0x23ae +#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG3_AFMT_CNTL 0x23af +#define regDIG3_AFMT_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CNTL 0x23b0 +#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_EN_CNTL 0x23b1 +#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CNTL 0x23d7 +#define regDIG3_TMDS_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL_CHAR 0x23d8 +#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 +#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG3_TMDS_CTL_BITS 0x23de +#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df +#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_VERSION 0x23e4 +#define regDIG3_DIG_VERSION_BASE_IDX 2 +#define regDIG3_FORCE_DIG_DISABLE 0x23e5 +#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1000 +#define regDP4_DP_LINK_CNTL 0x2508 +#define regDP4_DP_LINK_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT 0x2509 +#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP4_DP_MSA_COLORIMETRY 0x250a +#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP4_DP_CONFIG 0x250b +#define regDP4_DP_CONFIG_BASE_IDX 2 +#define regDP4_DP_VID_STREAM_CNTL 0x250c +#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO 0x250d +#define regDP4_DP_STEER_FIFO_BASE_IDX 2 +#define regDP4_DP_MSA_MISC 0x250e +#define regDP4_DP_MSA_MISC_BASE_IDX 2 +#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f +#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP4_DP_VID_TIMING 0x2510 +#define regDP4_DP_VID_TIMING_BASE_IDX 2 +#define regDP4_DP_VID_N 0x2511 +#define regDP4_DP_VID_N_BASE_IDX 2 +#define regDP4_DP_VID_M 0x2512 +#define regDP4_DP_VID_M_BASE_IDX 2 +#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 +#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 +#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP4_DP_VID_MSA_VBID 0x2515 +#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 +#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CNTL 0x2517 +#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM0 0x2519 +#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM1 0x251a +#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM2 0x251b +#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP4_DP_DPHY_8B10B_CNTL 0x251c +#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_PRBS_CNTL 0x251d +#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e +#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_EN 0x251f +#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CNTL 0x2520 +#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT 0x2521 +#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 +#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 +#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 +#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL 0x252b +#define regDP4_DP_SEC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL1 0x252c +#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING1 0x252d +#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING2 0x252e +#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING3 0x252f +#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING4 0x2530 +#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N 0x2531 +#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 +#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M 0x2533 +#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 +#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_TIMESTAMP 0x2535 +#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP4_DP_SEC_PACKET_CNTL 0x2536 +#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_CNTL 0x2537 +#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_UPDATE 0x2539 +#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0 0x253a +#define regDP4_DP_MSE_SAT0_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1 0x253b +#define regDP4_DP_MSE_SAT1_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2 0x253c +#define regDP4_DP_MSE_SAT2_BASE_IDX 2 +#define regDP4_DP_MSE_SAT_UPDATE 0x253d +#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_LINK_TIMING 0x253e +#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP4_DP_MSE_MISC_CNTL 0x253f +#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0_STATUS 0x2547 +#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1_STATUS 0x2548 +#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2_STATUS 0x2549 +#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM1 0x254c +#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM2 0x254d +#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM3 0x254e +#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM4 0x254f +#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL 0x2550 +#define regDP4_DP_MSO_CNTL_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL1 0x2551 +#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP4_DP_DSC_CNTL 0x2552 +#define regDP4_DP_DSC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL2 0x2553 +#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL3 0x2554 +#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL4 0x2555 +#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL5 0x2556 +#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL6 0x2557 +#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL7 0x2558 +#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP4_DP_DB_CNTL 0x2559 +#define regDP4_DP_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_MSA_VBID_MISC 0x255a +#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b +#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c +#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regDP4_DP_ALPM_CNTL 0x255d +#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP8_CNTL 0x255e +#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP9_CNTL 0x255f +#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP10_CNTL 0x2560 +#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP11_CNTL 0x2561 +#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 +#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1000 +#define regDIG4_DIG_FE_CNTL 0x248b +#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c +#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d +#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG4_DIG_CLOCK_PATTERN 0x248e +#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_TEST_PATTERN 0x248f +#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 +#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG4_DIG_FIFO_STATUS 0x2491 +#define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_CONTROL 0x2493 +#define regDIG4_HDMI_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_STATUS 0x2494 +#define regDIG4_HDMI_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 +#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 +#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 +#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 +#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG4_HDMI_GC 0x249d +#define regDIG4_HDMI_GC_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG4_HDMI_DB_CONTROL 0x24a6 +#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_0 0x24a7 +#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_1 0x24a8 +#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_0 0x24a9 +#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_1 0x24aa +#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_0 0x24ab +#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_1 0x24ac +#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_0 0x24ad +#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_1 0x24ae +#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG4_AFMT_CNTL 0x24af +#define regDIG4_AFMT_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CNTL 0x24b0 +#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_EN_CNTL 0x24b1 +#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CNTL 0x24d7 +#define regDIG4_TMDS_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL_CHAR 0x24d8 +#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 +#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG4_TMDS_CTL_BITS 0x24de +#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df +#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_VERSION 0x24e4 +#define regDIG4_DIG_VERSION_BASE_IDX 2 +#define regDIG4_FORCE_DIG_DISABLE 0x24e5 +#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +// base address: 0x154cc +#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 +#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 +#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 +#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT0_AFMT_60958_0 0x2078 +#define regAFMT0_AFMT_60958_0_BASE_IDX 2 +#define regAFMT0_AFMT_60958_1 0x2079 +#define regAFMT0_AFMT_60958_1_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a +#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b +#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c +#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d +#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e +#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT0_AFMT_60958_2 0x207f +#define regAFMT0_AFMT_60958_2_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 +#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT0_AFMT_STATUS 0x2081 +#define regAFMT0_AFMT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 +#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 +#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 +#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 +#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT0_AFMT_MEM_PWR 0x2087 +#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +// base address: 0x158cc +#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 +#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 +#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 +#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT1_AFMT_60958_0 0x2178 +#define regAFMT1_AFMT_60958_0_BASE_IDX 2 +#define regAFMT1_AFMT_60958_1 0x2179 +#define regAFMT1_AFMT_60958_1_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a +#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b +#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c +#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d +#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e +#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT1_AFMT_60958_2 0x217f +#define regAFMT1_AFMT_60958_2_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 +#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT1_AFMT_STATUS 0x2181 +#define regAFMT1_AFMT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 +#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 +#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 +#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 +#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT1_AFMT_MEM_PWR 0x2187 +#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec +// base address: 0x15ccc +#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 +#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 +#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 +#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT2_AFMT_60958_0 0x2278 +#define regAFMT2_AFMT_60958_0_BASE_IDX 2 +#define regAFMT2_AFMT_60958_1 0x2279 +#define regAFMT2_AFMT_60958_1_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a +#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b +#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c +#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d +#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e +#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT2_AFMT_60958_2 0x227f +#define regAFMT2_AFMT_60958_2_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 +#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT2_AFMT_STATUS 0x2281 +#define regAFMT2_AFMT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 +#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 +#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 +#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 +#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT2_AFMT_MEM_PWR 0x2287 +#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec +// base address: 0x160cc +#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 +#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 +#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 +#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT3_AFMT_60958_0 0x2378 +#define regAFMT3_AFMT_60958_0_BASE_IDX 2 +#define regAFMT3_AFMT_60958_1 0x2379 +#define regAFMT3_AFMT_60958_1_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a +#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b +#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c +#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d +#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e +#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT3_AFMT_60958_2 0x237f +#define regAFMT3_AFMT_60958_2_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 +#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT3_AFMT_STATUS 0x2381 +#define regAFMT3_AFMT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 +#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 +#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 +#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 +#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT3_AFMT_MEM_PWR 0x2387 +#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec +// base address: 0x164cc +#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 +#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 +#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 +#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define regAFMT4_AFMT_60958_0 0x2478 +#define regAFMT4_AFMT_60958_0_BASE_IDX 2 +#define regAFMT4_AFMT_60958_1 0x2479 +#define regAFMT4_AFMT_60958_1_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a +#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b +#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c +#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d +#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e +#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define regAFMT4_AFMT_60958_2 0x247f +#define regAFMT4_AFMT_60958_2_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 +#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAFMT4_AFMT_STATUS 0x2481 +#define regAFMT4_AFMT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 +#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 +#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 +#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 +#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define regAFMT4_AFMT_MEM_PWR 0x2487 +#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15524 +#define regDME0_DME_CONTROL 0x2089 +#define regDME0_DME_CONTROL_BASE_IDX 2 +#define regDME0_DME_MEMORY_CONTROL 0x208a +#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_STATUS 0x206c +#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG0_VPG_MEM_PWR 0x206d +#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_DATA 0x206f +#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO0 0x2070 +#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG0_VPG_MPEG_INFO1 0x2071 +#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +// base address: 0x15924 +#define regDME1_DME_CONTROL 0x2189 +#define regDME1_DME_CONTROL_BASE_IDX 2 +#define regDME1_DME_MEMORY_CONTROL 0x218a +#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x158a0 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 +#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_STATUS 0x216c +#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG1_VPG_MEM_PWR 0x216d +#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_DATA 0x216f +#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO0 0x2170 +#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG1_VPG_MPEG_INFO1 0x2171 +#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +// base address: 0x15d24 +#define regDME2_DME_CONTROL 0x2289 +#define regDME2_DME_CONTROL_BASE_IDX 2 +#define regDME2_DME_MEMORY_CONTROL 0x228a +#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +// base address: 0x15ca0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 +#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_STATUS 0x226c +#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG2_VPG_MEM_PWR 0x226d +#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_DATA 0x226f +#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO0 0x2270 +#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG2_VPG_MPEG_INFO1 0x2271 +#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +// base address: 0x16124 +#define regDME3_DME_CONTROL 0x2389 +#define regDME3_DME_CONTROL_BASE_IDX 2 +#define regDME3_DME_MEMORY_CONTROL 0x238a +#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +// base address: 0x160a0 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 +#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_STATUS 0x236c +#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG3_VPG_MEM_PWR 0x236d +#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_DATA 0x236f +#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO0 0x2370 +#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG3_VPG_MPEG_INFO1 0x2371 +#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +// base address: 0x16524 +#define regDME4_DME_CONTROL 0x2489 +#define regDME4_DME_CONTROL_BASE_IDX 2 +#define regDME4_DME_MEMORY_CONTROL 0x248a +#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +// base address: 0x164a0 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 +#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_STATUS 0x246c +#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG4_VPG_MEM_PWR 0x246d +#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_DATA 0x246f +#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO0 0x2470 +#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG4_VPG_MPEG_INFO1 0x2471 +#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define regDP_AUX0_AUX_CONTROL 0x1f50 +#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_STATUS 0x1f54 +#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_STATUS 0x1f55 +#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_DATA 0x1f56 +#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_DATA 0x1f57 +#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e +#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define regDP_AUX1_AUX_CONTROL 0x1f6c +#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_STATUS 0x1f70 +#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_STATUS 0x1f71 +#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_DATA 0x1f72 +#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_DATA 0x1f73 +#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a +#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +// base address: 0xe0 +#define regDP_AUX2_AUX_CONTROL 0x1f88 +#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 +#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a +#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b +#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_STATUS 0x1f8c +#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_STATUS 0x1f8d +#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_DATA 0x1f8e +#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_DATA 0x1f8f +#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 +#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 +#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 +#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 +#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 +#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e +#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +// base address: 0x150 +#define regDP_AUX3_AUX_CONTROL 0x1fa4 +#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 +#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 +#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 +#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 +#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_DATA 0x1faa +#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_DATA 0x1fab +#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad +#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 +#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 +#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 +#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 +#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 +#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba +#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +// base address: 0x1c0 +#define regDP_AUX4_AUX_CONTROL 0x1fc0 +#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 +#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 +#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 +#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 +#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_DATA 0x1fc6 +#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_DATA 0x1fc7 +#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc +#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd +#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce +#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf +#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 +#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 +#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define regDC_I2C_CONTROL 0x1e98 +#define regDC_I2C_CONTROL_BASE_IDX 2 +#define regDC_I2C_ARBITRATION 0x1e99 +#define regDC_I2C_ARBITRATION_BASE_IDX 2 +#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDC_I2C_SW_STATUS 0x1e9b +#define regDC_I2C_SW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_HW_STATUS 0x1e9c +#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC2_HW_STATUS 0x1e9d +#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC3_HW_STATUS 0x1e9e +#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC4_HW_STATUS 0x1e9f +#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_SPEED 0x1ea2 +#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC1_SETUP 0x1ea3 +#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC2_SPEED 0x1ea4 +#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC2_SETUP 0x1ea5 +#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC3_SPEED 0x1ea6 +#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC3_SETUP 0x1ea7 +#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC4_SPEED 0x1ea8 +#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC4_SETUP 0x1ea9 +#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC5_SPEED 0x1eaa +#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC5_SETUP 0x1eab +#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define regDC_I2C_TRANSACTION0 0x1eae +#define regDC_I2C_TRANSACTION0_BASE_IDX 2 +#define regDC_I2C_TRANSACTION1 0x1eaf +#define regDC_I2C_TRANSACTION1_BASE_IDX 2 +#define regDC_I2C_TRANSACTION2 0x1eb0 +#define regDC_I2C_TRANSACTION2_BASE_IDX 2 +#define regDC_I2C_TRANSACTION3 0x1eb1 +#define regDC_I2C_TRANSACTION3_BASE_IDX 2 +#define regDC_I2C_DATA 0x1eb2 +#define regDC_I2C_DATA_BASE_IDX 2 +#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define regDIO_SCRATCH0 0x1eca +#define regDIO_SCRATCH0_BASE_IDX 2 +#define regDIO_SCRATCH1 0x1ecb +#define regDIO_SCRATCH1_BASE_IDX 2 +#define regDIO_SCRATCH2 0x1ecc +#define regDIO_SCRATCH2_BASE_IDX 2 +#define regDIO_SCRATCH3 0x1ecd +#define regDIO_SCRATCH3_BASE_IDX 2 +#define regDIO_SCRATCH4 0x1ece +#define regDIO_SCRATCH4_BASE_IDX 2 +#define regDIO_SCRATCH5 0x1ecf +#define regDIO_SCRATCH5_BASE_IDX 2 +#define regDIO_SCRATCH6 0x1ed0 +#define regDIO_SCRATCH6_BASE_IDX 2 +#define regDIO_SCRATCH7 0x1ed1 +#define regDIO_SCRATCH7_BASE_IDX 2 +#define regDIO_MEM_PWR_STATUS 0x1edd +#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL 0x1ede +#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL2 0x1edf +#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define regDIO_CLK_CNTL 0x1ee0 +#define regDIO_CLK_CNTL_BASE_IDX 2 +#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define regDIG_SOFT_RESET 0x1eee +#define regDIG_SOFT_RESET_BASE_IDX 2 +#define regDIO_CLK_CNTL2 0x1ef2 +#define regDIO_CLK_CNTL2_BASE_IDX 2 +#define regDIO_CLK_CNTL3 0x1ef3 +#define regDIO_CLK_CNTL3_BASE_IDX 2 +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 +#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 +#define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 +#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 +#define regDIO_LINKA_CNTL 0x1f04 +#define regDIO_LINKA_CNTL_BASE_IDX 2 +#define regDIO_LINKB_CNTL 0x1f05 +#define regDIO_LINKB_CNTL_BASE_IDX 2 +#define regDIO_LINKC_CNTL 0x1f06 +#define regDIO_LINKC_CNTL_BASE_IDX 2 +#define regDIO_LINKD_CNTL 0x1f07 +#define regDIO_LINKD_CNTL_BASE_IDX 2 +#define regDIO_LINKE_CNTL 0x1f08 +#define regDIO_LINKE_CNTL_BASE_IDX 2 +#define regDIO_LINKF_CNTL 0x1f09 +#define regDIO_LINKF_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 +#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 +#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 +#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL 0x1f47 +#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 +#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a +#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_HI 0x1f4b +#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_LOW 0x1f4c +#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_LINK_CNTL 0x286d +#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_LINK_CNTL 0x286f +#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_LINK_CNTL 0x2871 +#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_LINK_CNTL 0x2873 +#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_LINK_CNTL 0x2875 +#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_GENERIC_MASK 0x28c8 +#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define regDC_GPIO_GENERIC_A 0x28c9 +#define regDC_GPIO_GENERIC_A_BASE_IDX 2 +#define regDC_GPIO_GENERIC_EN 0x28ca +#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define regDC_GPIO_GENERIC_Y 0x28cb +#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_GENLK_MASK 0x28f0 +#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define regDC_GPIO_GENLK_A 0x28f1 +#define regDC_GPIO_GENLK_A_BASE_IDX 2 +#define regDC_GPIO_GENLK_EN 0x28f2 +#define regDC_GPIO_GENLK_EN_BASE_IDX 2 +#define regDC_GPIO_GENLK_Y 0x28f3 +#define regDC_GPIO_GENLK_Y_BASE_IDX 2 +#define regDC_GPIO_HPD_MASK 0x28f4 +#define regDC_GPIO_HPD_MASK_BASE_IDX 2 +#define regDC_GPIO_HPD_A 0x28f5 +#define regDC_GPIO_HPD_A_BASE_IDX 2 +#define regDC_GPIO_HPD_EN 0x28f6 +#define regDC_GPIO_HPD_EN_BASE_IDX 2 +#define regDC_GPIO_HPD_Y 0x28f7 +#define regDC_GPIO_HPD_Y_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_2 0x28fd +#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ1_EN 0x2902 +#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 +#define regDC_GPIO_TX12_EN 0x2915 +#define regDC_GPIO_TX12_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_2 0x2918 +#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define regDC_GPIO_RXEN 0x2919 +#define regDC_GPIO_RXEN_BASE_IDX 2 +#define regDC_GPIO_PULLUPEN 0x291a +#define regDC_GPIO_PULLUPEN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +// base address: 0x360 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +// base address: 0x6c0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +// base address: 0xa20 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec +// base address: 0xd80 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec +// base address: 0x0 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 +#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 +#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 +#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a +#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b +#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c +#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 +#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec +// base address: 0x1b0 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c +#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d +#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e +#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f +#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 +#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 +#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 +#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 +#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 +#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 +#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d +#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define regDSCC0_DSCC_CONFIG0 0x300a +#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG1 0x300b +#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_STATUS 0x300c +#define regDSCC0_DSCC_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d +#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG0 0x300e +#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG1 0x300f +#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 +#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 +#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 +#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 +#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 +#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 +#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 +#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 +#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 +#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 +#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG12 0x301a +#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG13 0x301b +#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG14 0x301c +#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG15 0x301d +#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG16 0x301e +#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG17 0x301f +#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 +#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 +#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 +#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 +#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 +#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 +#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c +#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d +#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e +#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f +#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 +#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 +#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 +#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 +#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc140 +#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 +#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 +#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL 0x3053 +#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL2 0x3054 +#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 +#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_HI 0x3057 +#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_LOW 0x3058 +#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define regDSCC1_DSCC_CONFIG0 0x3066 +#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG1 0x3067 +#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_STATUS 0x3068 +#define regDSCC1_DSCC_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 +#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG0 0x306a +#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG1 0x306b +#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG2 0x306c +#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG3 0x306d +#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG4 0x306e +#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG5 0x306f +#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 +#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 +#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 +#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 +#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 +#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 +#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 +#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 +#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 +#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 +#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG16 0x307a +#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG17 0x307b +#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG18 0x307c +#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG19 0x307d +#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG20 0x307e +#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG21 0x307f +#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 +#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 +#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 +#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 +#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a +#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b +#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c +#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d +#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 +#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 +#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc2b0 +#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac +#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad +#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae +#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL 0x30af +#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 +#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 +#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_HI 0x30b3 +#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_LOW 0x30b4 +#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define regDSCC2_DSCC_CONFIG0 0x30c2 +#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG1 0x30c3 +#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_STATUS 0x30c4 +#define regDSCC2_DSCC_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 +#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 +#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 +#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 +#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 +#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca +#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb +#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc +#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd +#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce +#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf +#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 +#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 +#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 +#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 +#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 +#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 +#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 +#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 +#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 +#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 +#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG20 0x30da +#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG21 0x30db +#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc +#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd +#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 +#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 +#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 +#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 +#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 +#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 +#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed +#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 +#define regDSCCIF2_DSCCIF_CONFIG1 0x30be +#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc420 +#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 +#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a +#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL 0x310b +#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL2 0x310c +#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e +#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_HI 0x310f +#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_LOW 0x3110 +#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x2790c +#define regHPO_TOP_CLOCK_CONTROL 0x0e43 +#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 +#define regHPO_TOP_HW_CONTROL 0x0e4a +#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +// base address: 0x27958 +#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 +#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 +#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 +#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 +#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a698 +#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 +#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 +#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL 0x0e69 +#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a +#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c +#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_HI 0x0e6d +#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_LOW 0x0e6e +#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +// base address: 0x2646c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c +#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO0 0x091e +#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_INFO1 0x091f +#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 +#define regAFMT5_AFMT_60958_0 0x0920 +#define regAFMT5_AFMT_60958_0_BASE_IDX 3 +#define regAFMT5_AFMT_60958_1 0x0921 +#define regAFMT5_AFMT_60958_1_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 +#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 +#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 +#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 +#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 +#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 +#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 +#define regAFMT5_AFMT_60958_2 0x0927 +#define regAFMT5_AFMT_60958_2_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 +#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 +#define regAFMT5_AFMT_STATUS 0x0929 +#define regAFMT5_AFMT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a +#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b +#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 +#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c +#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d +#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 +#define regAFMT5_AFMT_MEM_PWR 0x092f +#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define regDME5_DME_CONTROL 0x093c +#define regDME5_DME_CONTROL_BASE_IDX 3 +#define regDME5_DME_MEMORY_CONTROL 0x093d +#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 +#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define regVPG5_VPG_GENERIC_STATUS 0x0935 +#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 +#define regVPG5_VPG_MEM_PWR 0x0936 +#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 +#define regVPG5_VPG_ISRC1_2_DATA 0x0938 +#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO0 0x0939 +#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 +#define regVPG5_VPG_MPEG_INFO1 0x093a +#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +// base address: 0x1ab8c +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +// base address: 0x1abc0 +#define regAPG0_APG_CONTROL 0x3630 +#define regAPG0_APG_CONTROL_BASE_IDX 2 +#define regAPG0_APG_CONTROL2 0x3631 +#define regAPG0_APG_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 +#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG0_APG_PACKET_CONTROL 0x3633 +#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a +#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b +#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c +#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG0_APG_STATUS 0x3641 +#define regAPG0_APG_STATUS_BASE_IDX 2 +#define regAPG0_APG_STATUS2 0x3642 +#define regAPG0_APG_STATUS2_BASE_IDX 2 +#define regAPG0_APG_MEM_PWR 0x3644 +#define regAPG0_APG_MEM_PWR_BASE_IDX 2 +#define regAPG0_APG_SPARE 0x3646 +#define regAPG0_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +// base address: 0x1ac38 +#define regDME6_DME_CONTROL 0x364e +#define regDME6_DME_CONTROL_BASE_IDX 2 +#define regDME6_DME_MEMORY_CONTROL 0x364f +#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +// base address: 0x1ac44 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 +#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_STATUS 0x3655 +#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG6_VPG_MEM_PWR 0x3656 +#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_DATA 0x3658 +#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO0 0x3659 +#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG6_VPG_MPEG_INFO1 0x365a +#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +// base address: 0x1ac74 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +// base address: 0x1aedc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +// base address: 0x1af10 +#define regAPG1_APG_CONTROL 0x3704 +#define regAPG1_APG_CONTROL_BASE_IDX 2 +#define regAPG1_APG_CONTROL2 0x3705 +#define regAPG1_APG_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 +#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG1_APG_PACKET_CONTROL 0x3707 +#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e +#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f +#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 +#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG1_APG_STATUS 0x3715 +#define regAPG1_APG_STATUS_BASE_IDX 2 +#define regAPG1_APG_STATUS2 0x3716 +#define regAPG1_APG_STATUS2_BASE_IDX 2 +#define regAPG1_APG_MEM_PWR 0x3718 +#define regAPG1_APG_MEM_PWR_BASE_IDX 2 +#define regAPG1_APG_SPARE 0x371a +#define regAPG1_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +// base address: 0x1af88 +#define regDME7_DME_CONTROL 0x3722 +#define regDME7_DME_CONTROL_BASE_IDX 2 +#define regDME7_DME_MEMORY_CONTROL 0x3723 +#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +// base address: 0x1af94 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 +#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_STATUS 0x3729 +#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG7_VPG_MEM_PWR 0x372a +#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_DATA 0x372c +#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO0 0x372d +#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG7_VPG_MPEG_INFO1 0x372e +#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +// base address: 0x1afc4 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +// base address: 0x1b22c +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +// base address: 0x1b260 +#define regAPG2_APG_CONTROL 0x37d8 +#define regAPG2_APG_CONTROL_BASE_IDX 2 +#define regAPG2_APG_CONTROL2 0x37d9 +#define regAPG2_APG_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_GEN_CONTROL 0x37da +#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG2_APG_PACKET_CONTROL 0x37db +#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 +#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 +#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 +#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG2_APG_STATUS 0x37e9 +#define regAPG2_APG_STATUS_BASE_IDX 2 +#define regAPG2_APG_STATUS2 0x37ea +#define regAPG2_APG_STATUS2_BASE_IDX 2 +#define regAPG2_APG_MEM_PWR 0x37ec +#define regAPG2_APG_MEM_PWR_BASE_IDX 2 +#define regAPG2_APG_SPARE 0x37ee +#define regAPG2_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +// base address: 0x1b2d8 +#define regDME8_DME_CONTROL 0x37f6 +#define regDME8_DME_CONTROL_BASE_IDX 2 +#define regDME8_DME_MEMORY_CONTROL 0x37f7 +#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +// base address: 0x1b2e4 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa +#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_STATUS 0x37fd +#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG8_VPG_MEM_PWR 0x37fe +#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_DATA 0x3800 +#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO0 0x3801 +#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG8_VPG_MPEG_INFO1 0x3802 +#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +// base address: 0x1b314 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +// base address: 0x1b57c +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +// base address: 0x1b5b0 +#define regAPG3_APG_CONTROL 0x38ac +#define regAPG3_APG_CONTROL_BASE_IDX 2 +#define regAPG3_APG_CONTROL2 0x38ad +#define regAPG3_APG_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae +#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG3_APG_PACKET_CONTROL 0x38af +#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 +#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 +#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 +#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG3_APG_STATUS 0x38bd +#define regAPG3_APG_STATUS_BASE_IDX 2 +#define regAPG3_APG_STATUS2 0x38be +#define regAPG3_APG_STATUS2_BASE_IDX 2 +#define regAPG3_APG_MEM_PWR 0x38c0 +#define regAPG3_APG_MEM_PWR_BASE_IDX 2 +#define regAPG3_APG_SPARE 0x38c2 +#define regAPG3_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +// base address: 0x1b628 +#define regDME9_DME_CONTROL 0x38ca +#define regDME9_DME_CONTROL_BASE_IDX 2 +#define regDME9_DME_MEMORY_CONTROL 0x38cb +#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +// base address: 0x1b634 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce +#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG9_VPG_GENERIC_STATUS 0x38d1 +#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG9_VPG_MEM_PWR 0x38d2 +#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 +#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO0 0x38d5 +#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 +#define regVPG9_VPG_MPEG_INFO1 0x38d6 +#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +// base address: 0x1b664 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +// base address: 0x1ad5c +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +// base address: 0x1ae00 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +// base address: 0x1b0ac +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +// base address: 0x1b150 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +// base address: 0x0 +#define regDCHVM_CTRL0 0x3603 +#define regDCHVM_CTRL0_BASE_IDX 2 +#define regDCHVM_CTRL1 0x3604 +#define regDCHVM_CTRL1_BASE_IDX 2 +#define regDCHVM_CLK_CTRL 0x3605 +#define regDCHVM_CLK_CTRL_BASE_IDX 2 +#define regDCHVM_MEM_CTRL 0x3606 +#define regDCHVM_MEM_CTRL_BASE_IDX 2 +#define regDCHVM_RIOMMU_CTRL0 0x3607 +#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 +#define regDCHVM_RIOMMU_STAT0 0x3608 +#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h new file mode 100644 index 000000000000..e5fd0121ceff --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h @@ -0,0 +1,60749 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_3_1_2_SH_MASK_HEADER +#define _dcn_3_1_2_SH_MASK_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//AZCONTROLLER0_GLOBAL_CAPABILITIES +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L +//AZCONTROLLER0_MINOR_VERSION +#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK 0xFFL +//AZCONTROLLER0_MAJOR_VERSION +#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK 0xFFL +//AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//AZCONTROLLER0_GLOBAL_CONTROL +#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x00000001L +#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x00000002L +#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000100L +//AZCONTROLLER0_WAKE_ENABLE +#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x0001L +//AZCONTROLLER0_STATE_CHANGE_STATUS +#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x0001L +//AZCONTROLLER0_GLOBAL_STATUS +#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK 0x00000002L +//AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFFL +//AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFFL +//AZCONTROLLER0_INTERRUPT_CONTROL +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x00000002L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x00000004L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x00000020L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x00000040L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x00000080L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x00000100L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x00000200L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x00000400L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x00000800L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x00001000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x00002000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x00004000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x00008000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000L +//AZCONTROLLER0_INTERRUPT_STATUS +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x00000001L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x00000002L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x00000004L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x00000008L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x00000010L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x00000020L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x00000040L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x00000080L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x00000100L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x00000200L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x00000400L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x00000800L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x00001000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x00002000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x00004000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x00008000L +#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000L +#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000L +//AZCONTROLLER0_WALL_CLOCK_COUNTER +#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xFFFFFFFFL +//AZCONTROLLER0_STREAM_SYNCHRONIZATION +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x00000001L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x00000002L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x00000004L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x00000008L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x00000010L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x00000020L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x00000040L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x00000080L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x00000100L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x00000200L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x00000400L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x00000800L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x00001000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x00002000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x00004000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x00008000L +//AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_CORB_WRITE_POINTER +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER0_CORB_READ_POINTER +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_CORB_CONTROL +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER0_CORB_STATUS +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER0_CORB_SIZE +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_RIRB_WRITE_POINTER +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER0_RIRB_CONTROL +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER0_RIRB_STATUS +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER0_RIRB_SIZE +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +//CRTC8_IDX +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL +//GENFC_WT +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L +//GENS1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1__NO_DISPLAY_MASK 0x01L +#define GENS1__VGA_VSTATUS_MASK 0x08L +#define GENS1__PIXEL_READ_BACK_MASK 0x30L +//ATTRDW +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDW__ATTR_DATA_MASK 0xFFL +//ATTRX +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_IDX_MASK 0x1FL +//ATTRDR +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xFFL +//GENMO_WT +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_WT__VGA_RAM_EN_MASK 0x02L +#define GENMO_WT__VGA_CKSEL_MASK 0x0CL +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L +//GENS0 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS0__SENSE_SWITCH_MASK 0x10L +#define GENS0__CRT_INTR_MASK 0x80L +//GENENB +//SEQ8_IDX +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x07L +//SEQ8_DATA +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL +//DAC_MASK +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xFFL +//DAC_R_INDEX +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL +//DAC_W_INDEX +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL +//DAC_DATA +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_DATA__DAC_DATA_MASK 0x3FL +//GENFC_RD +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L +//GENMO_RD +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_RD__VGA_RAM_EN_MASK 0x02L +#define GENMO_RD__VGA_CKSEL_MASK 0x0CL +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L +//GRPH8_IDX +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL +//GRPH8_DATA +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL +//CRTC8_IDX_1 +#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA_1 +#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL +//GENFC_WT_1 +#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L +//GENS1_1 +#define GENS1_1__NO_DISPLAY__SHIFT 0x0 +#define GENS1_1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1_1__NO_DISPLAY_MASK 0x01L +#define GENS1_1__VGA_VSTATUS_MASK 0x08L +#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//AZCONTROLLER1_CORB_WRITE_POINTER +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER1_CORB_READ_POINTER +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_CORB_CONTROL +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER1_CORB_STATUS +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER1_CORB_SIZE +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_RIRB_WRITE_POINTER +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER1_RIRB_CONTROL +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER1_RIRB_STATUS +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER1_RIRB_SIZE +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_GATE_DISABLE_CNTL4 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK 0x00020000L +//DPSTREAMCLK_CNTL +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN__SHIFT 0x1 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN__SHIFT 0x2 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN__SHIFT 0x3 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN__SHIFT 0x4 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN_MASK 0x00000002L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN_MASK 0x00000004L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN_MASK 0x00000008L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN_MASK 0x00000010L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT 0x9 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK 0x00000200L +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//SYMCLK32_SE_CNTL +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT 0x3 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT 0x7 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT 0xb +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT 0xf +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK 0x00000008L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK 0x00000080L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK 0x00000800L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK 0x00008000L +//SYMCLK32_LE_CNTL +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT 0x3 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT 0x7 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK 0x00000008L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK 0x00000080L +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK 0x20000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT 0x3 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT 0x6 +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT 0x7 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT 0xc +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV__SHIFT 0x1c +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK 0x00000008L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK 0x00000040L +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK 0x00000080L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK 0x00001000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV_MASK 0xF0000000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT 0x3 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT 0x6 +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT 0x7 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT 0xc +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV__SHIFT 0x1c +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK 0x00000008L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK 0x00000040L +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK 0x00000080L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK 0x00001000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV_MASK 0xF0000000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT 0x3 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT 0x6 +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT 0x7 +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT 0xc +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV__SHIFT 0x1c +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK 0x00000008L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK 0x00000040L +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK 0x00000080L +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK 0x00001000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV_MASK 0xF0000000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT 0x3 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT 0x6 +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT 0x7 +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT 0xc +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV__SHIFT 0x1c +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK 0x00000008L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK 0x00000040L +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK 0x00000080L +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK 0x00001000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV_MASK 0xF0000000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0007FFFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT 0x1d +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000070L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK 0x20000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DTBCLK_DTO0_PHASE +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT 0x0 +#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_PHASE +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT 0x0 +#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_PHASE +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT 0x0 +#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_PHASE +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT 0x0 +#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK 0xFFFFFFFFL +//DTBCLK_DTO0_MODULO +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT 0x0 +#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO1_MODULO +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT 0x0 +#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO2_MODULO +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT 0x0 +#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO3_MODULO +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT 0x0 +#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK 0xFFFFFFFFL +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYCSYMCLK_CLOCK_CNTL +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYDSYMCLK_CLOCK_CNTL +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//PHYESYMCLK_CLOCK_CNTL +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT 0x0 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT 0x4 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK 0x00000001L +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK 0x00000030L +//DCCG_GATE_DISABLE_CNTL3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK 0x00004000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L +//DCCG_AUDIO_DTBCLK_DTO_PHASE +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTBCLK_DTO_MODULO +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT 0x0 +#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK 0xFFFFFFFFL +//DTBCLK_DTO_DBUF_EN +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT 0x0 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT 0x1 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT 0x2 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT 0x3 +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK 0x00000001L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK 0x00000002L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK 0x00000004L +#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK 0x00000008L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +//DMCU_CTRL +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L +//DMCU_STATUS +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +//DMCU_PC_START_ADDR +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_START_ADDR +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_END_ADDR +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_ISR_START_ADDR +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_CS_HI +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL +//DMCU_FW_CS_LO +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL +//DMCU_RAM_ACCESS_CTRL +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +//DMCU_ERAM_WR_CTRL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_WR_DATA +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL +//DMCU_ERAM_RD_CTRL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_RD_DATA +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL +//DMCU_IRAM_WR_CTRL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL +//DMCU_IRAM_WR_DATA +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL +//DMCU_IRAM_RD_CTRL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL +//DMCU_IRAM_RD_DATA +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL +//DMCU_EVENT_TRIGGER +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +//DMCU_UC_INTERNAL_INT_STATUS +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +//DMCU_SS_INTERRUPT_CNTL_STATUS +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L +//DMCU_INTERRUPT_STATUS +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +//DMCU_INTERRUPT_STATUS_1 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR_MASK 0x00080000L +//DMCU_INTERRUPT_TO_HOST_EN_MASK +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK__SHIFT 0xc +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK__SHIFT 0xd +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK__SHIFT 0xe +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK__SHIFT 0xf +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK_MASK 0x00020000L +//DMCU_INTERRUPT_TO_UC_EN_MASK +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN_MASK 0x00080000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +//DC_DMCU_SCRATCH +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL +//DMCU_INT_CNT +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_FW_CHECKSUM_SMPL_BYTE_POS +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL +//DMCU_UC_CLK_GATING_CNTL +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +//MASTER_COMM_DATA_REG1 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG2 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG3 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CMD_REG +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CNTL_REG +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +//SLAVE_COMM_DATA_REG1 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG2 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG3 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CMD_REG +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CNTL_REG +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_STATUS2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_STATUS4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_STATUS5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000200L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +//DMCU_DPRX_INTERRUPT_STATUS1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INTERRUPT_STATUS_CONTINUE +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INT_CNT_CONTINUE +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +//DMCU_INTERRUPT_STATUS_2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK 0x00400000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK 0x00400000L +//DMCU_INT_CNT_CONT2 +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_INT_CNT_CONT3 +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT_MASK 0x00FF0000L + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +//DMCUB_RBBMIF_SEC_CNTL +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT 0x4 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT 0x8 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK 0x00000070L +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK 0x01FFFF00L + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000007FL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK 0x00000040L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON2_PERFCOUNTER_CNTL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_CNTL2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_STATE +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON2_PERFMON_CNTL +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON2_PERFMON_CNTL2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON2_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON2_PERFMON_CVALUE_LOW +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON2_PERFMON_HI +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFMON_LOW +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK 0x00000800L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT 0x12 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x13 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x18 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x19 +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT 0x1c +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK 0x00040000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK 0x00080000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x01000000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x02000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK 0x08000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK 0x10000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK 0x00000800L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK 0x04000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPP_INTERRUPT_DEST +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +//HPO_INTERRUPT_DEST +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x5 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT 0x9 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000020L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK 0x00000200L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L +//DMU_MEM_PWR_CNTL +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L +//DMCU_SMU_INTERRUPT_CNTL +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG__SHIFT 0x10 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT_MASK 0x00000001L +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//ZSC_CNTL +#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT 0x0 +#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK 0x00000003L +//ZSC_CNTL2 +#define ZSC_CNTL2__ALLOW_Z10__SHIFT 0x0 +#define ZSC_CNTL2__ALLOW_Z10_MASK 0x00000001L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L +//ZSC_STATUS +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0 +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT 0x4 +#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT 0x8 +#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT 0x9 +#define ZSC_STATUS__FENCE_STATUS__SHIFT 0xa +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK 0x00000003L +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK 0x00000030L +#define ZSC_STATUS__FENCE_REQ_STATUS_MASK 0x00000100L +#define ZSC_STATUS__FENCE_ACK_STATUS_MASK 0x00000200L +#define ZSC_STATUS__FENCE_STATUS_MASK 0x00000C00L + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00008000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00002000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL +//DMCUB_CNTL2 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT 0x0 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK 0x00000001L + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L +//DWB_DEBUG_CTRL +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT 0x0 +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT 0x6 +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK 0x00000001L +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK 0x000000C0L + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI +#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//MMHUBBUB_CTRL +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT 0x0 +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK 0x00000003L +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xc +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT 0x17 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x001FF000L +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK 0xFF800000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT 0xc +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK 0x0000F000L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT 0x9 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT 0xc +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK 0x00000200L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK 0x00001000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_HOSTVM_CNTL +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT 0x0 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT 0x1 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT 0x2 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT 0x3 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT 0x4 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT 0x6 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT 0x8 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT 0x10 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT 0x18 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT 0x1c +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK 0x00000001L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK 0x00000002L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK 0x00000004L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK 0x00000008L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK 0x00000010L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK 0x00000040L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK 0x00003F00L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK 0x00FF0000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK 0x0F000000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK 0xF0000000L +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT 0x10 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK 0x00010000L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT 0x2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK 0x00000002L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK 0x00000004L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x003FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x3FF80000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L +//DCHUBBUB_TEST_DEBUG_INDEX +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_TEST_DEBUG_DATA +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_DCC_CFG +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L +//DCHUBBUB_RET_PATH_DCC_CFG0_0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG0_1 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_1 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_1 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_1 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_1 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_1 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_1 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_1 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT_CNTL +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT 0x1 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT 0x2 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT 0x4 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT 0x10 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK 0x00000001L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK 0x00000002L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK 0x00000004L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK 0x000000F0L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT1 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT2 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_COMPBUF_CTRL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT 0x0 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT 0x10 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT 0x12 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT 0x13 +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT 0x1f +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK 0x0000001FL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK 0x00001F00L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK 0x00010000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK 0x00040000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK 0x00080000L +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK 0x80000000L +//DCHUBBUB_DET0_CTRL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK 0x00000007L +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK 0x00000700L +//DCHUBBUB_DET1_CTRL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK 0x00000007L +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK 0x00000700L +//DCHUBBUB_DET2_CTRL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK 0x00000007L +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK 0x00000700L +//DCHUBBUB_DET3_CTRL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK 0x00000007L +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK 0x00000700L +//DCHUBBUB_MEM_PWR_MODE_CTRL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x10 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT 0x12 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x14 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT 0x18 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT 0x19 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT 0x1a +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK 0x00030000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK 0x000C0000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00300000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK 0x01000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK 0x02000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK 0x04000000L +//COMPBUF_MEM_PWR_CTRL_1 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT 0x10 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT 0x18 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK 0x0000FF00L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK 0x00FF0000L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK 0xFF000000L +//COMPBUF_MEM_PWR_CTRL_2 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK 0x000000FFL +//DCHUBBUB_MEM_PWR_STATUS +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT 0xc +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT 0xe +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK 0x00003000L +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK 0x0000C000L +//COMPBUF_RESERVED_SPACE +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT 0x0 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT 0x10 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP0_HUBPREQ_DEBUG_DB +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBPREQ_DEBUG +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00001FF0L +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP1_HUBPREQ_DEBUG_DB +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBPREQ_DEBUG +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00001FF0L +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP2_HUBPREQ_DEBUG_DB +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBPREQ_DEBUG +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00001FF0L +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP3_HUBPREQ_DEBUG_DB +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBPREQ_DEBUG +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00001FF0L +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C11_C12 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C13_C14 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C21_C22 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C23_C24 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C31_C32 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C33_C34 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_CONTROL +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_BLNDGAM_LUT_INDEX +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_BLNDGAM_LUT_DATA +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_LUT_CONTROL +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_OFFSET_B +#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_OFFSET_G +#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_OFFSET_R +#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_OFFSET_B +#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_OFFSET_G +#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_OFFSET_R +#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM0_CM_SHAPER_CONTROL +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_SHAPER_OFFSET_R +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_G +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_B +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_SHAPER_SCALE_R +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM0_CM_SHAPER_SCALE_G_B +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_SHAPER_LUT_INDEX +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM0_CM_SHAPER_LUT_DATA +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM0_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM0_CM_SHAPER_RAMA_START_CNTL_B +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_G +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_R +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_END_CNTL_B +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_G +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_R +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_REGION_0_1 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_2_3 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_4_5 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_6_7 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_8_9 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_10_11 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_12_13 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_14_15 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_16_17 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_18_19 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_20_21 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_22_23 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_24_25 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_26_27 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_28_29 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_30_31 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_32_33 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_START_CNTL_B +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_G +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_R +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_END_CNTL_B +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_G +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_R +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_REGION_0_1 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_2_3 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_4_5 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_6_7 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_8_9 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_10_11 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_12_13 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_14_15 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_16_17 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_18_19 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_20_21 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_22_23 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_24_25 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_26_27 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_28_29 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_30_31 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_32_33 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_MEM_PWR_CTRL2 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM0_CM_MEM_PWR_STATUS2 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM0_CM_3DLUT_MODE +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM0_CM_3DLUT_INDEX +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM0_CM_3DLUT_DATA +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM0_CM_3DLUT_DATA_30BIT +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM0_CM_3DLUT_READ_WRITE_CONTROL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM0_CM_3DLUT_OUT_NORM_FACTOR +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM0_CM_3DLUT_OUT_OFFSET_R +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_G +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_B +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_TEST_DEBUG_INDEX +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM0_CM_TEST_DEBUG_DATA +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C11_C12 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C13_C14 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C21_C22 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C23_C24 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C31_C32 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C33_C34 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_CONTROL +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_BLNDGAM_LUT_INDEX +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_BLNDGAM_LUT_DATA +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_LUT_CONTROL +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_OFFSET_B +#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_OFFSET_G +#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_OFFSET_R +#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_OFFSET_B +#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_OFFSET_G +#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_OFFSET_R +#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM1_CM_SHAPER_CONTROL +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_SHAPER_OFFSET_R +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_G +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_B +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_SHAPER_SCALE_R +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM1_CM_SHAPER_SCALE_G_B +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_SHAPER_LUT_INDEX +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM1_CM_SHAPER_LUT_DATA +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM1_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM1_CM_SHAPER_RAMA_START_CNTL_B +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_G +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_R +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_END_CNTL_B +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_G +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_R +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_REGION_0_1 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_2_3 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_4_5 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_6_7 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_8_9 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_10_11 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_12_13 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_14_15 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_16_17 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_18_19 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_20_21 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_22_23 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_24_25 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_26_27 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_28_29 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_30_31 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_32_33 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_START_CNTL_B +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_G +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_R +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_END_CNTL_B +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_G +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_R +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_REGION_0_1 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_2_3 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_4_5 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_6_7 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_8_9 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_10_11 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_12_13 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_14_15 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_16_17 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_18_19 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_20_21 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_22_23 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_24_25 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_26_27 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_28_29 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_30_31 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_32_33 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_MEM_PWR_CTRL2 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM1_CM_MEM_PWR_STATUS2 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM1_CM_3DLUT_MODE +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM1_CM_3DLUT_INDEX +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM1_CM_3DLUT_DATA +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM1_CM_3DLUT_DATA_30BIT +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM1_CM_3DLUT_READ_WRITE_CONTROL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM1_CM_3DLUT_OUT_NORM_FACTOR +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM1_CM_3DLUT_OUT_OFFSET_R +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_G +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_B +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_TEST_DEBUG_INDEX +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM1_CM_TEST_DEBUG_DATA +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG2_PRE_DEALPHA +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG2_PRE_CSC_MODE +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG2_PRE_CSC_C11_C12 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C13_C14 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C21_C22 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C23_C24 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C31_C32 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C33_C34 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C11_C12 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C13_C14 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C21_C22 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C23_C24 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C31_C32 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C33_C34 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG2_CNVC_COEF_FORMAT +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG2_PRE_DEGAM +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG2_PRE_REALPHA +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +//CNVC_CUR2_CURSOR0_CONTROL +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR2_CURSOR0_COLOR0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_COLOR1 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_COLOR +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_POST_CSC_CONTROL +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_POST_CSC_C11_C12 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C13_C14 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C21_C22 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C23_C24 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C31_C32 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C33_C34 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C11_C12 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C13_C14 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C21_C22 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C23_C24 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C31_C32 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C33_C34 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_CONTROL +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_GAMUT_REMAP_C11_C12 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C13_C14 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C21_C22 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C23_C24 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C31_C32 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C33_C34 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C11_C12 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C13_C14 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C21_C22 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C23_C24 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C31_C32 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C33_C34 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_CONTROL +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_GAMCOR_LUT_INDEX +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_GAMCOR_LUT_DATA +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_LUT_CONTROL +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_GAMCOR_RAMA_START_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_OFFSET_B +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_G +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_R +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_REGION_0_1 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_2_3 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_4_5 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_6_7 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_8_9 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_10_11 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_12_13 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_14_15 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_16_17 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_18_19 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_20_21 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_22_23 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_24_25 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_26_27 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_28_29 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_30_31 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_32_33 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_OFFSET_B +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_G +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_R +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_REGION_0_1 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_2_3 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_4_5 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_6_7 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_8_9 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_10_11 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_12_13 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_14_15 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_16_17 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_18_19 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_20_21 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_22_23 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_24_25 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_26_27 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_28_29 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_30_31 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_32_33 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_CONTROL +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_BLNDGAM_LUT_INDEX +#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_BLNDGAM_LUT_DATA +#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_LUT_CONTROL +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_OFFSET_B +#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMA_OFFSET_G +#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMA_OFFSET_R +#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_OFFSET_B +#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMB_OFFSET_G +#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMB_OFFSET_R +#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM2_CM_SHAPER_CONTROL +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_SHAPER_OFFSET_R +#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_SHAPER_OFFSET_G +#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_SHAPER_OFFSET_B +#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_SHAPER_SCALE_R +#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM2_CM_SHAPER_SCALE_G_B +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM2_CM_SHAPER_LUT_INDEX +#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM2_CM_SHAPER_LUT_DATA +#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM2_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM2_CM_SHAPER_RAMA_START_CNTL_B +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_START_CNTL_G +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_START_CNTL_R +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_END_CNTL_B +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_END_CNTL_G +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_END_CNTL_R +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_REGION_0_1 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_2_3 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_4_5 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_6_7 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_8_9 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_10_11 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_12_13 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_14_15 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_16_17 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_18_19 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_20_21 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_22_23 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_24_25 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_26_27 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_28_29 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_30_31 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_32_33 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_START_CNTL_B +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_START_CNTL_G +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_START_CNTL_R +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_END_CNTL_B +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_END_CNTL_G +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_END_CNTL_R +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_REGION_0_1 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_2_3 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_4_5 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_6_7 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_8_9 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_10_11 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_12_13 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_14_15 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_16_17 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_18_19 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_20_21 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_22_23 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_24_25 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_26_27 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_28_29 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_30_31 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_32_33 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_MEM_PWR_CTRL2 +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM2_CM_MEM_PWR_STATUS2 +#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM2_CM_3DLUT_MODE +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM2_CM_3DLUT_INDEX +#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM2_CM_3DLUT_DATA +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM2_CM_3DLUT_DATA_30BIT +#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM2_CM_3DLUT_READ_WRITE_CONTROL +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM2_CM_3DLUT_OUT_NORM_FACTOR +#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM2_CM_3DLUT_OUT_OFFSET_R +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM2_CM_3DLUT_OUT_OFFSET_G +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM2_CM_3DLUT_OUT_OFFSET_B +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM2_CM_TEST_DEBUG_INDEX +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM2_CM_TEST_DEBUG_DATA +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP2_DPP_CRC_VAL_R_G +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_VAL_B_A +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L +//CNVC_CFG3_PRE_DEALPHA +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG3_PRE_CSC_MODE +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG3_PRE_CSC_C11_C12 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C13_C14 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C21_C22 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C23_C24 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C31_C32 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C33_C34 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C11_C12 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C13_C14 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C21_C22 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C23_C24 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C31_C32 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C33_C34 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG3_CNVC_COEF_FORMAT +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG3_PRE_DEGAM +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG3_PRE_REALPHA +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +//CNVC_CUR3_CURSOR0_CONTROL +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR3_CURSOR0_COLOR0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_COLOR1 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_COLOR +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_POST_CSC_CONTROL +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_POST_CSC_C11_C12 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C13_C14 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C21_C22 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C23_C24 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C31_C32 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C33_C34 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C11_C12 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C13_C14 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C21_C22 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C23_C24 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C31_C32 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C33_C34 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_CONTROL +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_GAMUT_REMAP_C11_C12 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C13_C14 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C21_C22 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C23_C24 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C31_C32 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C33_C34 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C11_C12 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C13_C14 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C21_C22 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C23_C24 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C31_C32 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C33_C34 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_CONTROL +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_GAMCOR_LUT_INDEX +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_GAMCOR_LUT_DATA +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_LUT_CONTROL +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_GAMCOR_RAMA_START_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_OFFSET_B +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_G +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_R +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_REGION_0_1 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_2_3 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_4_5 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_6_7 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_8_9 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_10_11 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_12_13 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_14_15 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_16_17 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_18_19 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_20_21 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_22_23 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_24_25 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_26_27 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_28_29 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_30_31 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_32_33 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_OFFSET_B +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_G +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_R +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_REGION_0_1 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_2_3 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_4_5 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_6_7 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_8_9 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_10_11 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_12_13 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_14_15 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_16_17 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_18_19 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_20_21 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_22_23 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_24_25 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_26_27 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_28_29 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_30_31 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_32_33 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_CONTROL +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT 0x0 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT 0x2 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK 0x00000003L +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK 0x00000004L +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_BLNDGAM_LUT_INDEX +#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_BLNDGAM_LUT_DATA +#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_LUT_CONTROL +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_OFFSET_B +#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMA_OFFSET_G +#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMA_OFFSET_R +#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_OFFSET_B +#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMB_OFFSET_G +#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMB_OFFSET_R +#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM3_CM_SHAPER_CONTROL +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_SHAPER_OFFSET_R +#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_SHAPER_OFFSET_G +#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_SHAPER_OFFSET_B +#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_SHAPER_SCALE_R +#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM3_CM_SHAPER_SCALE_G_B +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM3_CM_SHAPER_LUT_INDEX +#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM3_CM_SHAPER_LUT_DATA +#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM3_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//CM3_CM_SHAPER_RAMA_START_CNTL_B +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_START_CNTL_G +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_START_CNTL_R +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_END_CNTL_B +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_END_CNTL_G +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_END_CNTL_R +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_REGION_0_1 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_2_3 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_4_5 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_6_7 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_8_9 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_10_11 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_12_13 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_14_15 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_16_17 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_18_19 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_20_21 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_22_23 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_24_25 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_26_27 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_28_29 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_30_31 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_32_33 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_START_CNTL_B +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_START_CNTL_G +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_START_CNTL_R +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_END_CNTL_B +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_END_CNTL_G +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_END_CNTL_R +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_REGION_0_1 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_2_3 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_4_5 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_6_7 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_8_9 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_10_11 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_12_13 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_14_15 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_16_17 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_18_19 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_20_21 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_22_23 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_24_25 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_26_27 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_28_29 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_30_31 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_32_33 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_MEM_PWR_CTRL2 +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM3_CM_MEM_PWR_STATUS2 +#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM3_CM_3DLUT_MODE +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//CM3_CM_3DLUT_INDEX +#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM3_CM_3DLUT_DATA +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM3_CM_3DLUT_DATA_30BIT +#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM3_CM_3DLUT_READ_WRITE_CONTROL +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM3_CM_3DLUT_OUT_NORM_FACTOR +#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM3_CM_3DLUT_OUT_OFFSET_R +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM3_CM_3DLUT_OUT_OFFSET_G +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM3_CM_3DLUT_OUT_OFFSET_B +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM3_CM_TEST_DEBUG_INDEX +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM3_CM_TEST_DEBUG_DATA +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP3_DPP_CRC_VAL_R_G +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_VAL_B_A +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xe +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x0000C000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0x8 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0xd +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0xe +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00000100L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00002000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00004000L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x3 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0xb +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000008L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00000800L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_rmu_dispdec +//MPC_RMU_CONTROL +#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT 0x0 +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT 0x4 +#define MPC_RMU_CONTROL__MPC_RMU1_MUX__SHIFT 0x8 +#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS__SHIFT 0xc +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK 0x0000000FL +#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK 0x000000F0L +#define MPC_RMU_CONTROL__MPC_RMU1_MUX_MASK 0x00000F00L +#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS_MASK 0x0000F000L +//MPC_RMU_MEM_PWR_CTRL +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT 0x8 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE__SHIFT 0xa +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS__SHIFT 0xc +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE__SHIFT 0xe +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE__SHIFT 0x10 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE__SHIFT 0x12 +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK 0x00000300L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE_MASK 0x00000C00L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS_MASK 0x00001000L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE_MASK 0x0000C000L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE_MASK 0x00030000L +#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE_MASK 0x000C0000L +//MPC_RMU0_SHAPER_CONTROL +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU0_SHAPER_OFFSET_R +#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_OFFSET_G +#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_OFFSET_B +#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMU0_SHAPER_SCALE_R +#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMU0_SHAPER_SCALE_G_B +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMU0_SHAPER_LUT_INDEX +#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMU0_SHAPER_LUT_DATA +#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_B +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_G +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_START_CNTL_R +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_B +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_G +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_END_CNTL_R +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMA_REGION_0_1 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_2_3 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_4_5 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_6_7 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_8_9 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_10_11 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_12_13 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_14_15 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_16_17 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_18_19 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_20_21 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_22_23 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_24_25 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_26_27 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_28_29 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_30_31 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMA_REGION_32_33 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_B +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_G +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_START_CNTL_R +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_B +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_G +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_END_CNTL_R +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU0_SHAPER_RAMB_REGION_0_1 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_2_3 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_4_5 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_6_7 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_8_9 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_10_11 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_12_13 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_14_15 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_16_17 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_18_19 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_20_21 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_22_23 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_24_25 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_26_27 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_28_29 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_30_31 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_SHAPER_RAMB_REGION_32_33 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU0_3DLUT_MODE +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK 0x00000010L +#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU0_3DLUT_INDEX +#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK 0x000007FFL +//MPC_RMU0_3DLUT_DATA +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_DATA_30BIT +#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMU0_3DLUT_READ_WRITE_CONTROL +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMU0_3DLUT_OUT_NORM_FACTOR +#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMU0_3DLUT_OUT_OFFSET_R +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_OUT_OFFSET_G +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMU0_3DLUT_OUT_OFFSET_B +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPC_RMU1_SHAPER_CONTROL +#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU1_SHAPER_OFFSET_R +#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMU1_SHAPER_OFFSET_G +#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMU1_SHAPER_OFFSET_B +#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMU1_SHAPER_SCALE_R +#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMU1_SHAPER_SCALE_G_B +#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMU1_SHAPER_LUT_INDEX +#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMU1_SHAPER_LUT_DATA +#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMU1_SHAPER_RAMA_START_CNTL_B +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMA_START_CNTL_G +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMA_START_CNTL_R +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMA_END_CNTL_B +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMA_END_CNTL_G +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMA_END_CNTL_R +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMA_REGION_0_1 +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_2_3 +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_4_5 +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_6_7 +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_8_9 +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_10_11 +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_12_13 +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_14_15 +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_16_17 +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_18_19 +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_20_21 +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_22_23 +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_24_25 +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_26_27 +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_28_29 +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_30_31 +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMA_REGION_32_33 +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_START_CNTL_B +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMB_START_CNTL_G +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMB_START_CNTL_R +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMU1_SHAPER_RAMB_END_CNTL_B +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMB_END_CNTL_G +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMB_END_CNTL_R +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMU1_SHAPER_RAMB_REGION_0_1 +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_2_3 +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_4_5 +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_6_7 +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_8_9 +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_10_11 +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_12_13 +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_14_15 +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_16_17 +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_18_19 +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_20_21 +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_22_23 +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_24_25 +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_26_27 +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_28_29 +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_30_31 +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_SHAPER_RAMB_REGION_32_33 +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMU1_3DLUT_MODE +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK 0x00000010L +#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMU1_3DLUT_INDEX +#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK 0x000007FFL +//MPC_RMU1_3DLUT_DATA +#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMU1_3DLUT_DATA_30BIT +#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMU1_3DLUT_READ_WRITE_CONTROL +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMU1_3DLUT_OUT_NORM_FACTOR +#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMU1_3DLUT_OUT_OFFSET_R +#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMU1_3DLUT_OUT_OFFSET_G +#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMU1_3DLUT_OUT_OFFSET_B +#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_BL1_PWM_GRP2_REG_LOCK +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_12 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_34 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_1 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_2 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_3 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_4 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_5 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_6 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_7 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_8 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_9 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_10 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_11 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_12 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_13 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_14 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_15 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_16 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_17 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_18 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_19 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_20 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_21 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_22 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_23 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_24 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_BL1_PWM_GRP2_REG_LOCK +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_12 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_34 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_1 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_2 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_3 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_4 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_5 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_6 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_7 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_8 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_9 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_10 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_11 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_12 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_13 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_14 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_15 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_16 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_17 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_18 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_19 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_20 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_21 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_22 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_23 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_24 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm2_dispdec +//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_USER_LEVEL +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_TARGET_ABM_LEVEL +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_ABM_CNTL +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_BL1_PWM_GRP2_REG_LOCK +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM2_DC_ABM1_CNTL +#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM2_DC_ABM1_IPCSC_COEFF_SEL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_12 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_THRES_34 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_CNTL_MISC +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM2_DC_ABM1_HG_MISC_CTRL +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SUM_OF_LUMA +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM2_DC_ABM1_LS_PIXEL_COUNT +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_HG_SAMPLE_RATE +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_LS_SAMPLE_RATE +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_1 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_2 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_3 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_4 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_5 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_6 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_7 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_8 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_9 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_10 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_11 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_12 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_13 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_14 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_15 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_16 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_17 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_18 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_19 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_20 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_21 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_22 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_23 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_24 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_BL_MASTER_LOCK +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm3_dispdec +//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_USER_LEVEL +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_TARGET_ABM_LEVEL +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_ABM_CNTL +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_BL1_PWM_GRP2_REG_LOCK +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM3_DC_ABM1_CNTL +#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM3_DC_ABM1_IPCSC_COEFF_SEL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_12 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_THRES_34 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_CNTL_MISC +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM3_DC_ABM1_HG_MISC_CTRL +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SUM_OF_LUMA +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM3_DC_ABM1_LS_PIXEL_COUNT +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_HG_SAMPLE_RATE +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_LS_SAMPLE_RATE +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_1 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_2 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_3 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_4 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_5 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_6 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_7 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_8 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_9 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_10 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_11 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_12 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_13 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_14 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_15 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_16 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_17 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_18 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_19 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_20 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_21 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_22 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_23 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_24 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_BL_MASTER_LOCK +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT 0xe +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT 0xf +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK 0x00004000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK 0x00008000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC_CNTL2 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_DSC_START_POSITION +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC_CNTL2 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_DSC_START_POSITION +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_FLOW_CONTROL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC_CNTL2 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_RG +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_RG +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_RG +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_RG +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG2_OTG_GLOBAL_CONTROL4 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_MANUAL_FLOW_CONTROL +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG2_OTG_DRR_TIMING_INT_STATUS +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG2_OTG_DRR_V_TOTAL_CHANGE +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG2_OTG_DRR_TRIGGER_WINDOW +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_M_CONST_DTO0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO1 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_DSC_START_POSITION +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK 0x00000100L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_FLOW_CONTROL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC_CNTL2 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_RG +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_RG +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_RG +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_RG +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG3_OTG_GLOBAL_CONTROL4 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_MANUAL_FLOW_CONTROL +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG3_OTG_DRR_TIMING_INT_STATUS +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG3_OTG_DRR_V_TOTAL_CHANGE +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG3_OTG_DRR_TRIGGER_WINDOW +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_M_CONST_DTO0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO1 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_DSC_START_POSITION +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//DWB_SOURCE_SELECT +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT 0x6 +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK 0x000001C0L +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON17_PERFCOUNTER_CNTL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_CNTL2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_STATE +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON17_PERFMON_CNTL +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON17_PERFMON_CNTL2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON17_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON17_PERFMON_CVALUE_LOW +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON17_PERFMON_HI +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFMON_LOW +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_DPHY_INTERNAL_CTRL +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_DSC_BYTES_PER_PIXEL +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_STATUS +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_FORCE_DIG_DISABLE +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_DPHY_INTERNAL_CTRL +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_DSC_BYTES_PER_PIXEL +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_STATUS +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_FORCE_DIG_DISABLE +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_DPHY_INTERNAL_CTRL +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_EN +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CNTL +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP2_DP_DPHY_CRC_RESULT +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP2_DP_DPHY_CRC_MST_CNTL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_MST_STATUS +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_DSC_CNTL +#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_DSC_BYTES_PER_PIXEL +#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP8_CNTL +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP9_CNTL +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP10_CNTL +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP11_CNTL +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP_EN_DB_STATUS +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_STATUS +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG2_HDMI_INFOFRAME_CONTROL1 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_AFMT_CNTL +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG2_FORCE_DIG_DISABLE +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_DPHY_INTERNAL_CTRL +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_EN +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CNTL +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP3_DP_DPHY_CRC_RESULT +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP3_DP_DPHY_CRC_MST_CNTL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_MST_STATUS +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_DSC_CNTL +#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_DSC_BYTES_PER_PIXEL +#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP8_CNTL +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP9_CNTL +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP10_CNTL +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP11_CNTL +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP_EN_DB_STATUS +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_STATUS +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG3_HDMI_INFOFRAME_CONTROL1 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_AFMT_CNTL +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG3_FORCE_DIG_DISABLE +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_DPHY_INTERNAL_CTRL +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_EN +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CNTL +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP4_DP_DPHY_CRC_RESULT +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP4_DP_DPHY_CRC_MST_CNTL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_MST_STATUS +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_DSC_CNTL +#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_DSC_BYTES_PER_PIXEL +#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP8_CNTL +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP9_CNTL +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP10_CNTL +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP11_CNTL +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP_EN_DB_STATUS +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_STATUS +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG4_HDMI_INFOFRAME_CONTROL1 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_AFMT_CNTL +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG4_FORCE_DIG_DISABLE +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec +//AFMT0_AFMT_VBI_PACKET_CONTROL +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT0_AFMT_AUDIO_INFO0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT0_AFMT_AUDIO_INFO1 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT0_AFMT_60958_0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT0_AFMT_60958_1 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_CONTROL +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT0_AFMT_RAMP_CONTROL0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT0_AFMT_RAMP_CONTROL1 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT0_AFMT_RAMP_CONTROL2 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_RAMP_CONTROL3 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT0_AFMT_60958_2 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT0_AFMT_AUDIO_CRC_RESULT +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT0_AFMT_STATUS +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT0_AFMT_AUDIO_PACKET_CONTROL +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT0_AFMT_INFOFRAME_CONTROL0 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT0_AFMT_INTERRUPT_STATUS +//AFMT0_AFMT_AUDIO_SRC_CONTROL +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT0_AFMT_MEM_PWR +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec +//AFMT1_AFMT_VBI_PACKET_CONTROL +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT1_AFMT_AUDIO_INFO0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT1_AFMT_AUDIO_INFO1 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT1_AFMT_60958_0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT1_AFMT_60958_1 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_CONTROL +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT1_AFMT_RAMP_CONTROL0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT1_AFMT_RAMP_CONTROL1 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT1_AFMT_RAMP_CONTROL2 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_RAMP_CONTROL3 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT1_AFMT_60958_2 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT1_AFMT_AUDIO_CRC_RESULT +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT1_AFMT_STATUS +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT1_AFMT_AUDIO_PACKET_CONTROL +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT1_AFMT_INFOFRAME_CONTROL0 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT1_AFMT_INTERRUPT_STATUS +//AFMT1_AFMT_AUDIO_SRC_CONTROL +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT1_AFMT_MEM_PWR +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec +//AFMT2_AFMT_VBI_PACKET_CONTROL +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT2_AFMT_AUDIO_INFO0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT2_AFMT_AUDIO_INFO1 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT2_AFMT_60958_0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT2_AFMT_60958_1 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_CONTROL +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT2_AFMT_RAMP_CONTROL0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT2_AFMT_RAMP_CONTROL1 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT2_AFMT_RAMP_CONTROL2 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_RAMP_CONTROL3 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_60958_2 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_RESULT +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT2_AFMT_STATUS +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT2_AFMT_INFOFRAME_CONTROL0 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT2_AFMT_INTERRUPT_STATUS +//AFMT2_AFMT_AUDIO_SRC_CONTROL +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT2_AFMT_MEM_PWR +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec +//AFMT3_AFMT_VBI_PACKET_CONTROL +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT3_AFMT_AUDIO_INFO0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT3_AFMT_AUDIO_INFO1 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT3_AFMT_60958_0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT3_AFMT_60958_1 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_CONTROL +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT3_AFMT_RAMP_CONTROL0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT3_AFMT_RAMP_CONTROL1 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT3_AFMT_RAMP_CONTROL2 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_RAMP_CONTROL3 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT3_AFMT_60958_2 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT3_AFMT_AUDIO_CRC_RESULT +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT3_AFMT_STATUS +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT3_AFMT_AUDIO_PACKET_CONTROL +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT3_AFMT_INFOFRAME_CONTROL0 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT3_AFMT_INTERRUPT_STATUS +//AFMT3_AFMT_AUDIO_SRC_CONTROL +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT3_AFMT_MEM_PWR +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec +//AFMT4_AFMT_VBI_PACKET_CONTROL +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT4_AFMT_AUDIO_INFO0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT4_AFMT_AUDIO_INFO1 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT4_AFMT_60958_0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT4_AFMT_60958_1 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_CONTROL +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT4_AFMT_RAMP_CONTROL0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT4_AFMT_RAMP_CONTROL1 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT4_AFMT_RAMP_CONTROL2 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_RAMP_CONTROL3 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT4_AFMT_60958_2 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT4_AFMT_AUDIO_CRC_RESULT +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT4_AFMT_STATUS +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT4_AFMT_AUDIO_PACKET_CONTROL +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT4_AFMT_INFOFRAME_CONTROL0 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT4_AFMT_INTERRUPT_STATUS +//AFMT4_AFMT_AUDIO_SRC_CONTROL +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT4_AFMT_MEM_PWR +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG0_VPG_MPEG_INFO1 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG1_VPG_MPEG_INFO1 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO1 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +//DME3_DME_CONTROL +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME3_DME_MEMORY_CONTROL +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG3_VPG_GENERIC_PACKET_DATA +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GENERIC_STATUS +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG3_VPG_MEM_PWR +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG3_VPG_ISRC1_2_ACCESS_CTRL +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG3_VPG_ISRC1_2_DATA +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG3_VPG_MPEG_INFO1 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +//DME4_DME_CONTROL +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME4_DME_MEMORY_CONTROL +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG4_VPG_GENERIC_PACKET_DATA +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GENERIC_STATUS +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG4_VPG_MEM_PWR +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG4_VPG_ISRC1_2_ACCESS_CTRL +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG4_VPG_ISRC1_2_DATA +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG4_VPG_MPEG_INFO1 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_GTC_SYNC_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_STATUS +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_GTC_SYNC_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_STATUS +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_GTC_SYNC_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_STATUS +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK 0x40000000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_GENERIC_INTERRUPT_MESSAGE +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_GENERIC_INTERRUPT_CLEAR +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L +//DIO_LINKA_CNTL +#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKB_CNTL +#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKC_CNTL +#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKD_CNTL +#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKE_CNTL +#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L +//DIO_LINKF_CNTL +#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT 0x0 +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK 0x00000003L +#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK 0x00000700L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON18_PERFCOUNTER_CNTL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_CNTL2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_STATE +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON18_PERFMON_CNTL +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON18_PERFMON_CNTL2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON18_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON18_PERFMON_CVALUE_LOW +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON18_PERFMON_HI +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFMON_LOW +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK 0x00000200L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT 0x1c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK 0xF0000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_PWRSEQ1_EN +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec +//PWRSEQ0_DC_GPIO_PWRSEQ_EN +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT 0x2 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK 0x00000004L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +//PWRSEQ0_DC_GPIO_PWRSEQ_MASK +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PWRSEQ0_PANEL_PWRSEQ_CNTL +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PWRSEQ0_PANEL_PWRSEQ_STATE +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PWRSEQ0_PANEL_PWRSEQ_DELAY1 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PWRSEQ0_PANEL_PWRSEQ_DELAY2 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//PWRSEQ0_BL_PWM_CNTL +#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//PWRSEQ0_BL_PWM_CNTL2 +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//PWRSEQ0_BL_PWM_PERIOD_CNTL +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//PWRSEQ0_BL_PWM_GRP1_REG_LOCK +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ0_PWRSEQ_SPARE +#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec +//PWRSEQ1_DC_GPIO_PWRSEQ_EN +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT 0x2 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK 0x00000004L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +//PWRSEQ1_DC_GPIO_PWRSEQ_MASK +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PWRSEQ1_PANEL_PWRSEQ_CNTL +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PWRSEQ1_PANEL_PWRSEQ_STATE +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PWRSEQ1_PANEL_PWRSEQ_DELAY1 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PWRSEQ1_PANEL_PWRSEQ_DELAY2 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//PWRSEQ1_BL_PWM_CNTL +#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//PWRSEQ1_BL_PWM_CNTL2 +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//PWRSEQ1_BL_PWM_PERIOD_CNTL +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//PWRSEQ1_BL_PWM_GRP1_REG_LOCK +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ1_PWRSEQ_SPARE +#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF0_DSCCIF_CONFIG1 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON19_PERFCOUNTER_CNTL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_CNTL2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_STATE +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON19_PERFMON_CNTL +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON19_PERFMON_CNTL2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON19_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON19_PERFMON_CVALUE_LOW +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON19_PERFMON_HI +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFMON_LOW +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF1_DSCCIF_CONFIG1 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP1_DSC_DEBUG_CONTROL +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON20_PERFCOUNTER_CNTL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_CNTL2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_STATE +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON20_PERFMON_CNTL +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON20_PERFMON_CNTL2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON20_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON20_PERFMON_CVALUE_LOW +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON20_PERFMON_HI +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFMON_LOW +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF2_DSCCIF_CONFIG1 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP2_DSC_DEBUG_CONTROL +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON21_PERFCOUNTER_CNTL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_CNTL2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_STATE +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON21_PERFMON_CNTL +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON21_PERFMON_CNTL2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON21_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON21_PERFMON_CVALUE_LOW +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON21_PERFMON_HI +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFMON_LOW +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT 0x11 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT 0x12 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT 0x13 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT 0x14 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT 0x15 +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x18 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK 0x00010000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK 0x00020000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK 0x00040000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK 0x00080000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK 0x00100000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK 0x00200000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x7F000000L +//HPO_TOP_HW_CONTROL +#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT 0x0 +#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +//DP_STREAM_MAPPER_CONTROL0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL1 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL2 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL3 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON22_PERFCOUNTER_CNTL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_CNTL2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_STATE +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON22_PERFMON_CNTL +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON22_PERFMON_CNTL2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON22_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON22_PERFMON_CVALUE_LOW +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON22_PERFMON_HI +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFMON_LOW +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_INTERRUPT_STATUS +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +//APG0_APG_CONTROL +#define APG0_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG0_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG0_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG0_APG_CONTROL2 +#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG0_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG0_APG_DBG_GEN_CONTROL +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG0_APG_PACKET_CONTROL +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG0_APG_AUDIO_CRC_CONTROL +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG0_APG_AUDIO_CRC_CONTROL2 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG0_APG_AUDIO_CRC_RESULT +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG0_APG_STATUS +#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG0_APG_STATUS2 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG0_APG_MEM_PWR +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG0_APG_SPARE +#define APG0_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG0_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +//DME6_DME_CONTROL +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME6_DME_MEMORY_CONTROL +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG6_VPG_GENERIC_PACKET_DATA +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GENERIC_STATUS +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG6_VPG_MEM_PWR +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG6_VPG_ISRC1_2_ACCESS_CTRL +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG6_VPG_ISRC1_2_DATA +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG6_VPG_MPEG_INFO1 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +//APG1_APG_CONTROL +#define APG1_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG1_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG1_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG1_APG_CONTROL2 +#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG1_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG1_APG_PACKET_CONTROL +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG1_APG_AUDIO_CRC_CONTROL +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG1_APG_AUDIO_CRC_CONTROL2 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG1_APG_AUDIO_CRC_RESULT +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG1_APG_STATUS +#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG1_APG_STATUS2 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG1_APG_MEM_PWR +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG1_APG_SPARE +#define APG1_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG1_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +//DME7_DME_CONTROL +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME7_DME_MEMORY_CONTROL +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG7_VPG_GENERIC_PACKET_DATA +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GENERIC_STATUS +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG7_VPG_MEM_PWR +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG7_VPG_ISRC1_2_ACCESS_CTRL +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG7_VPG_ISRC1_2_DATA +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG7_VPG_MPEG_INFO1 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +//APG2_APG_CONTROL +#define APG2_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG2_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG2_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG2_APG_CONTROL2 +#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG2_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG2_APG_PACKET_CONTROL +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG2_APG_AUDIO_CRC_CONTROL +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG2_APG_AUDIO_CRC_CONTROL2 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG2_APG_AUDIO_CRC_RESULT +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG2_APG_STATUS +#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG2_APG_STATUS2 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG2_APG_MEM_PWR +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG2_APG_SPARE +#define APG2_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG2_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +//DME8_DME_CONTROL +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME8_DME_MEMORY_CONTROL +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG8_VPG_GENERIC_PACKET_DATA +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GENERIC_STATUS +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG8_VPG_MEM_PWR +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG8_VPG_ISRC1_2_ACCESS_CTRL +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG8_VPG_ISRC1_2_DATA +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG8_VPG_MPEG_INFO1 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00001F00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +//APG3_APG_CONTROL +#define APG3_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG3_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG3_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG3_APG_CONTROL2 +#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG3_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG3_APG_PACKET_CONTROL +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG3_APG_AUDIO_CRC_CONTROL +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG3_APG_AUDIO_CRC_CONTROL2 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG3_APG_AUDIO_CRC_RESULT +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG3_APG_STATUS +#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG3_APG_STATUS2 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG3_APG_MEM_PWR +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG3_APG_SPARE +#define APG3_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG3_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +//DME9_DME_CONTROL +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME9_DME_MEMORY_CONTROL +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG9_VPG_GENERIC_PACKET_DATA +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GENERIC_STATUS +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG9_VPG_MEM_PWR +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG9_VPG_ISRC1_2_ACCESS_CTRL +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG9_VPG_ISRC1_2_DATA +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG9_VPG_MPEG_INFO1 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC0_DP_LINK_ENC_SPARE +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC1_DP_LINK_ENC_SPARE +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT 0xa +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT 0x12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT 0x1a +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK 0x00000003L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK 0x000000F0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK 0x00000300L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK 0x00000400L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK 0x0000F000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK 0x00030000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK 0x00040000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK 0x00F00000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK 0x03000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK 0x04000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK 0xF0000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT 0x11 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT 0x15 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK 0x000000C0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK 0x00003F00L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK 0x00010000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK 0x000E0000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK 0x00100000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK 0x00600000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK 0x00FFFF00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +//DCHVM_CTRL0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT 0x0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK 0x00000001L +//DCHVM_CTRL1 +#define DCHVM_CTRL1__DUMMY1__SHIFT 0x0 +#define DCHVM_CTRL1__DUMMY1_MASK 0xFFFFFFFFL +//DCHVM_CLK_CTRL +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT 0x1 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT 0x4 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT 0x5 +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT 0x8 +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT 0xa +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK 0x00000002L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK 0x00000010L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK 0x00000020L +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK 0x00000300L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK 0x00000C00L +//DCHVM_MEM_CTRL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT 0x0 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT 0x2 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT 0x4 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK 0x00000001L +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK 0x0000000CL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK 0x00000030L +//DCHVM_RIOMMU_CTRL0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT 0x0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT 0x1 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK 0x00000001L +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK 0x00000002L +//DCHVM_RIOMMU_STAT0 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT 0x0 +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT 0x1 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK 0x00000001L +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK 0x00000002L + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h new file mode 100644 index 000000000000..6d6db95a391f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _dpcs_3_0_3_OFFSET_HEADER +#define _dpcs_3_0_3_OFFSET_HEADER + + + +// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec +// base address: 0x0 +#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 +#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 +#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a +#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b +#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +// base address: 0x0 +#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 +#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 +#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 +#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 +#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 +#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 +#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 +#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937 +#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938 +#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939 +#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 +#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 +#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +// base address: 0x0 +#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 +#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 +#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec +// base address: 0x360 +#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 +#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 +#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 +#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 +#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +// base address: 0x360 +#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 +#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 +#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a +#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b +#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c +#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d +#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e +#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f +#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10 +#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11 +#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b +#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e +#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr1_dispdec +// base address: 0x360 +#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c +#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d +#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h new file mode 100644 index 000000000000..55743d06f728 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _dpcs_3_0_3_SH_MASK_HEADER +#define _dpcs_3_0_3_SH_MASK_HEADER + + +// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec +//DPCSTX0_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L +//DPCSTX0_DPCSTX_TX_CNTL +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT 0xe +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT__SHIFT 0xf +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT__SHIFT 0x12 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT_MASK 0x00004000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT_MASK 0x00008000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT_MASK 0x00040000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX0_DPCSTX_CBUS_CNTL +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX0_DPCSTX_INTERRUPT_CNTL +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX0_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +//RDPCSTX0_RDPCSTX_CNTL +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_CLOCK_CNTL +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX0_RDPCS_TX_CR_ADDR +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_CR_DATA +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_SRAM_CNTL +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX0_RDPCSTX_SCRATCH +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_SPARE +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_CNTL2 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX0_RDPCSTX_PHY_CNTL0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x0001C000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX0_RDPCSTX_PHY_CNTL2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX0_RDPCSTX_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PHY_CNTL7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX0_RDPCSTX_PHY_CNTL8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX0_RDPCSTX_PHY_CNTL13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +//RDPCSTX0_RDPCSTX_PHY_FUSE1 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE2 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +//RDPCSTX0_RDPCSTX_PHY_FUSE3 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +//DPCSSYS_CR0_DPCSSYS_CR_ADDR +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_DPCSSYS_CR_DATA +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec +//DPCSTX1_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L +//DPCSTX1_DPCSTX_TX_CNTL +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT 0xe +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT__SHIFT 0xf +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT__SHIFT 0x12 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT_MASK 0x00004000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT_MASK 0x00008000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT_MASK 0x00040000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX1_DPCSTX_CBUS_CNTL +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX1_DPCSTX_INTERRUPT_CNTL +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX1_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +//RDPCSTX1_RDPCSTX_CNTL +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_CLOCK_CNTL +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX1_RDPCS_TX_CR_ADDR +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_CR_DATA +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_SRAM_CNTL +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX1_RDPCSTX_SCRATCH +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_SPARE +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_CNTL2 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX1_RDPCSTX_PHY_CNTL0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x0001C000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX1_RDPCSTX_PHY_CNTL2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX1_RDPCSTX_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PHY_CNTL7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX1_RDPCSTX_PHY_CNTL8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX1_RDPCSTX_PHY_CNTL13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +//RDPCSTX1_RDPCSTX_PHY_FUSE1 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE2 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +//RDPCSTX1_RDPCSTX_PHY_FUSE3 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h index bb2c9c7a18df..bd37aa6b6560 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h @@ -33,6 +33,9 @@ #define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0 +#define mmDF_GCM_AON0_DramMegaBaseAddress0 0x0064 +#define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX 0 + #define smnPerfMonCtlLo0 0x01d440UL #define smnPerfMonCtlHi0 0x01d444UL #define smnPerfMonCtlLo1 0x01d450UL diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h index 7afa87c7ff54..f804e13b002e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h @@ -50,6 +50,7 @@ #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL +#define ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000007CL #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h new file mode 100644 index 000000000000..92caf8441d1e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h @@ -0,0 +1,11936 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dpcs_4_2_0_OFFSET_HEADER +#define _dpcs_4_2_0_OFFSET_HEADER + + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +// base address: 0x0 +#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 +#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 +#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr1_dispdec +// base address: 0x360 +#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c +#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d +#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr2_dispdec +// base address: 0x6c0 +#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 +#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 +#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr3_dispdec +// base address: 0xa20 +#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc +#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd +#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr4_dispdec +// base address: 0xd80 +#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 +#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define regDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 +#define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec +// base address: 0x0 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 +#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 +#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 +#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 +#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 +#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a +#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b +#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c +#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d +#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 +#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec +// base address: 0x1b0 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c +#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d +#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e +#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f +#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 +#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 +#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 +#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 +#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 +#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 +#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 +#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 +#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 +#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d +#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +// base address: 0x0 +#define regRDPCSTX0_RDPCSTX_CNTL 0x2930 +#define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 +#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 +#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0x2933 +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 +#define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 +#define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 +#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_SCRATCH 0x2937 +#define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_SPARE 0x2938 +#define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_CNTL2 0x2939 +#define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a +#define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b +#define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c +#define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d +#define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e +#define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f +#define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 +#define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 +#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 +#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 +#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define regRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a +#define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_CNTL3 0x295c +#define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x295d +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x295e +#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +// base address: 0x360 +#define regRDPCSTX1_RDPCSTX_CNTL 0x2a08 +#define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 +#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a +#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0x2a0b +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c +#define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d +#define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e +#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f +#define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_SPARE 0x2a10 +#define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_CNTL2 0x2a11 +#define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a +#define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b +#define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c +#define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d +#define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e +#define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f +#define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a +#define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b +#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d +#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e +#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 +#define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_CNTL3 0x2a34 +#define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2a35 +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2a36 +#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec +// base address: 0x6c0 +#define regRDPCSTX2_RDPCSTX_CNTL 0x2ae0 +#define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 +#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 +#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0x2ae3 +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 +#define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 +#define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 +#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7 +#define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_SPARE 0x2ae8 +#define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 +#define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa +#define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb +#define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc +#define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd +#define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe +#define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff +#define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 +#define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 +#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 +#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 +#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define regRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a +#define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_CNTL3 0x2b0c +#define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2b0d +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2b0e +#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec +// base address: 0xa20 +#define regRDPCSTX3_RDPCSTX_CNTL 0x2bb8 +#define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 +#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba +#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0x2bbb +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc +#define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd +#define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe +#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf +#define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_SPARE 0x2bc0 +#define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 +#define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca +#define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb +#define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc +#define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd +#define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce +#define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf +#define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda +#define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb +#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd +#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde +#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 +#define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_CNTL3 0x2be4 +#define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2be5 +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2be6 +#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec +// base address: 0xd80 +#define regRDPCSTX4_RDPCSTX_CNTL 0x2c90 +#define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 +#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 +#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA 0x2c93 +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 +#define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 +#define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 +#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_SCRATCH 0x2c97 +#define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_SPARE 0x2c98 +#define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_CNTL2 0x2c99 +#define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa +#define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab +#define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac +#define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad +#define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae +#define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf +#define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 +#define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 +#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 +#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 +#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define regRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba +#define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_CNTL3 0x2cbc +#define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2cbd +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2cbe +#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_LINK_CNTL 0x286d +#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_LINK_CNTL 0x286f +#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_LINK_CNTL 0x2871 +#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_LINK_CNTL 0x2873 +#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_LINK_CNTL 0x2875 +#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_GENERIC_MASK 0x28c8 +#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define regDC_GPIO_GENERIC_A 0x28c9 +#define regDC_GPIO_GENERIC_A_BASE_IDX 2 +#define regDC_GPIO_GENERIC_EN 0x28ca +#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define regDC_GPIO_GENERIC_Y 0x28cb +#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_GENLK_MASK 0x28f0 +#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define regDC_GPIO_GENLK_A 0x28f1 +#define regDC_GPIO_GENLK_A_BASE_IDX 2 +#define regDC_GPIO_GENLK_EN 0x28f2 +#define regDC_GPIO_GENLK_EN_BASE_IDX 2 +#define regDC_GPIO_GENLK_Y 0x28f3 +#define regDC_GPIO_GENLK_Y_BASE_IDX 2 +#define regDC_GPIO_HPD_MASK 0x28f4 +#define regDC_GPIO_HPD_MASK_BASE_IDX 2 +#define regDC_GPIO_HPD_A 0x28f5 +#define regDC_GPIO_HPD_A_BASE_IDX 2 +#define regDC_GPIO_HPD_EN 0x28f6 +#define regDC_GPIO_HPD_EN_BASE_IDX 2 +#define regDC_GPIO_HPD_Y 0x28f7 +#define regDC_GPIO_HPD_Y_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_2 0x28fd +#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ1_EN 0x2902 +#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 +#define regDC_GPIO_TX12_EN 0x2915 +#define regDC_GPIO_TX12_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_2 0x2918 +#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define regDC_GPIO_RXEN 0x2919 +#define regDC_GPIO_RXEN_BASE_IDX 2 +#define regDC_GPIO_PULLUPEN 0x291a +#define regDC_GPIO_PULLUPEN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec +// base address: 0x360 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 +#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec +// base address: 0x6c0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 +#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec +// base address: 0xa20 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 +#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec +// base address: 0xd80 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 +#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 + + +// addressBlock: dpcssys_cr0_rdpcstxcrind +// base address: 0x0 +#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000 +#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001 +#define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3 0x000e +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4 0x000f +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3 0x001a +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4 0x001b +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5 0x001c +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e +#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN 0x001f +#define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN 0x0020 +#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT 0x0021 +#define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN 0x0022 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6 0x002a +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0 0x002b +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1 0x002c +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2 0x002d +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3 0x002e +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4 0x002f +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 +#define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN 0x0036 +#define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN 0x0037 +#define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN 0x0038 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c +#define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL 0x0040 +#define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL 0x0041 +#define ixDPCSSYS_CR0_SUP_ANA_BG1 0x0042 +#define ixDPCSSYS_CR0_SUP_ANA_BG2 0x0043 +#define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS 0x0044 +#define ixDPCSSYS_CR0_SUP_ANA_BG3 0x0045 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1 0x0046 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2 0x0047 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD 0x0048 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1 0x0049 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2 0x004a +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3 0x004b +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1 0x004c +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2 0x004d +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3 0x004e +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4 0x004f +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5 0x0050 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1 0x0051 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2 0x0052 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1 0x0053 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2 0x0054 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD 0x0055 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1 0x0056 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2 0x0057 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3 0x0058 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1 0x0059 +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2 0x005a +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3 0x005b +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4 0x005c +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5 0x005d +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1 0x005e +#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2 0x005f +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 +#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 +#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 +#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 +#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a +#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b +#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD 0x007c +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG 0x0081 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT 0x0082 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT 0x0086 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT 0x0087 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT 0x0088 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a +#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT 0x0093 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 +#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d +#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f +#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 +#define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL 0x1032 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 +#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0 0x10bb +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 +#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS 0x10e0 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD 0x10e1 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS 0x10e2 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1 0x10e3 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2 0x10e4 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC 0x10e5 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1 0x10e6 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE 0x10e7 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK 0x10e9 +#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1 0x10ea +#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2 0x10eb +#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3 0x10ec +#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2 0x10ed +#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3 0x10ee +#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4 0x10ef +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e +#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA 0x111f +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f +#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 +#define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL 0x1132 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e +#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f +#define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL 0x1151 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR 0x1152 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT 0x1158 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ 0x1159 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a +#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e +#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 +#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 +#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 +#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 +#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL 0x11ae +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE 0x11b4 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0 0x11bb +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1 0x11bc +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 +#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS 0x11e0 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD 0x11e1 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS 0x11e2 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1 0x11e3 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2 0x11e4 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC 0x11e5 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1 0x11e6 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE 0x11e7 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK 0x11e9 +#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1 0x11ea +#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2 0x11eb +#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3 0x11ec +#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2 0x11ed +#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3 0x11ee +#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4 0x11ef +#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1 0x11f0 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2 0x11f1 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES 0x11f2 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL 0x11f3 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1 0x11f4 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2 0x11f5 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ 0x11f6 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1 0x11f7 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2 0x11f8 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF 0x11f9 +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1 0x11fa +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2 0x11fb +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3 0x11fc +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4 0x11fd +#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC 0x11fe +#define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1 0x11ff +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e +#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA 0x121f +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f +#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 +#define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL 0x1232 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e +#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f +#define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL 0x1251 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR 0x1252 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT 0x1258 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ 0x1259 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a +#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e +#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 +#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 +#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 +#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 +#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL 0x12ae +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE 0x12b4 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0 0x12bb +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1 0x12bc +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 +#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS 0x12e0 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD 0x12e1 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS 0x12e2 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1 0x12e3 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2 0x12e4 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC 0x12e5 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1 0x12e6 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE 0x12e7 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK 0x12e9 +#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1 0x12ea +#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2 0x12eb +#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3 0x12ec +#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2 0x12ed +#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3 0x12ee +#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4 0x12ef +#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1 0x12f0 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2 0x12f1 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES 0x12f2 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL 0x12f3 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1 0x12f4 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2 0x12f5 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ 0x12f6 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1 0x12f7 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2 0x12f8 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF 0x12f9 +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1 0x12fa +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2 0x12fb +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3 0x12fc +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4 0x12fd +#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC 0x12fe +#define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1 0x12ff +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d +#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f +#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 +#define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL 0x1332 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 +#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0 0x13bb +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 +#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS 0x13e0 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD 0x13e1 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS 0x13e2 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1 0x13e3 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2 0x13e4 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC 0x13e5 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1 0x13e6 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE 0x13e7 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK 0x13e9 +#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1 0x13ea +#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2 0x13eb +#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3 0x13ec +#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2 0x13ed +#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3 0x13ee +#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4 0x13ef +#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL 0x2000 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 +#define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 +#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1 0x200a +#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL 0x200b +#define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE 0x200c +#define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE 0x200d +#define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA 0x200e +#define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD 0x200f +#define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 +#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1 0x2011 +#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2 0x2012 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f +#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP 0x302c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA 0x303c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e +#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c +#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 +#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP 0x312c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA 0x313c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e +#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c +#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 +#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP 0x322c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA 0x323c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e +#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c +#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 +#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP 0x332c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA 0x333c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e +#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c +#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 +#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS 0x401c +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS 0x4032 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 +#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS 0x411c +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS 0x4132 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 +#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS 0x421c +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS 0x4232 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 +#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS 0x431c +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS 0x4332 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 +#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS 0x701c +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS 0x7032 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 +#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 +#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO 0x8000 +#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI 0x8001 +#define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN 0x8002 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e +#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN 0x801f +#define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 +#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT 0x8021 +#define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN 0x8022 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 +#define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN 0x8036 +#define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN 0x8037 +#define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c +#define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL 0x8040 +#define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL 0x8041 +#define ixDPCSSYS_CR0_SUPX_ANA_BG1 0x8042 +#define ixDPCSSYS_CR0_SUPX_ANA_BG2 0x8043 +#define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 +#define ixDPCSSYS_CR0_SUPX_ANA_BG3 0x8045 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1 0x8046 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2 0x8047 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD 0x8048 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1 0x8049 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2 0x804a +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3 0x804b +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1 0x804c +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2 0x804d +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3 0x804e +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4 0x804f +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5 0x8050 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1 0x8051 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2 0x8052 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1 0x8053 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2 0x8054 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD 0x8055 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1 0x8056 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2 0x8057 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3 0x8058 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1 0x8059 +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2 0x805a +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3 0x805b +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4 0x805c +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5 0x805d +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1 0x805e +#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2 0x805f +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 +#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 +#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 +#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 +#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a +#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b +#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG 0x8081 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT 0x8082 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT 0x8086 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a +#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT 0x8093 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 +#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e +#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA 0x901f +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f +#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 +#define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL 0x9032 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e +#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f +#define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL 0x9051 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR 0x9052 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT 0x9058 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ 0x9059 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a +#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e +#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 +#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 +#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 +#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 +#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL 0x90ae +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE 0x90b4 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0 0x90bb +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1 0x90bc +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 +#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS 0x90e0 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD 0x90e1 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS 0x90e2 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1 0x90e3 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2 0x90e4 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC 0x90e5 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1 0x90e6 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE 0x90e7 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK 0x90e9 +#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1 0x90ea +#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2 0x90eb +#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3 0x90ec +#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2 0x90ed +#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3 0x90ee +#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4 0x90ef +#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1 0x90f0 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2 0x90f1 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES 0x90f2 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL 0x90f3 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1 0x90f4 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2 0x90f5 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ 0x90f6 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1 0x90f7 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2 0x90f8 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF 0x90f9 +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1 0x90fa +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2 0x90fb +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3 0x90fc +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4 0x90fd +#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC 0x90fe +#define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1 0x90ff +#define ixDPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 +#define ixDPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA 0xe03c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e +#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c +#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 +#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 + + +// addressBlock: dpcssys_cr1_rdpcstxcrind +// base address: 0x0 +#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO 0x0000 +#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI 0x0001 +#define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN 0x0002 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3 0x000e +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4 0x000f +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3 0x001a +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4 0x001b +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5 0x001c +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e +#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN 0x001f +#define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN 0x0020 +#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT 0x0021 +#define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN 0x0022 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6 0x002a +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0 0x002b +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1 0x002c +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2 0x002d +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3 0x002e +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4 0x002f +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 +#define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN 0x0036 +#define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN 0x0037 +#define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN 0x0038 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c +#define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL 0x0040 +#define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL 0x0041 +#define ixDPCSSYS_CR1_SUP_ANA_BG1 0x0042 +#define ixDPCSSYS_CR1_SUP_ANA_BG2 0x0043 +#define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS 0x0044 +#define ixDPCSSYS_CR1_SUP_ANA_BG3 0x0045 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1 0x0046 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2 0x0047 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD 0x0048 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1 0x0049 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2 0x004a +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3 0x004b +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1 0x004c +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2 0x004d +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3 0x004e +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4 0x004f +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5 0x0050 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1 0x0051 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2 0x0052 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1 0x0053 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2 0x0054 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD 0x0055 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1 0x0056 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2 0x0057 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3 0x0058 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1 0x0059 +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2 0x005a +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3 0x005b +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4 0x005c +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5 0x005d +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1 0x005e +#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2 0x005f +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 +#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 +#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 +#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 +#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a +#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b +#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD 0x007c +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG 0x0081 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT 0x0082 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT 0x0086 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT 0x0087 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT 0x0088 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a +#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT 0x0093 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 +#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d +#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f +#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 +#define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL 0x1032 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 +#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0 0x10bb +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 +#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS 0x10e0 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD 0x10e1 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS 0x10e2 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1 0x10e3 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2 0x10e4 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC 0x10e5 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1 0x10e6 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE 0x10e7 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK 0x10e9 +#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1 0x10ea +#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2 0x10eb +#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3 0x10ec +#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2 0x10ed +#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3 0x10ee +#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4 0x10ef +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e +#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA 0x111f +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f +#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 +#define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL 0x1132 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e +#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f +#define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL 0x1151 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR 0x1152 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT 0x1158 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ 0x1159 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a +#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e +#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 +#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 +#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 +#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 +#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL 0x11ae +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE 0x11b4 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0 0x11bb +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1 0x11bc +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 +#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS 0x11e0 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD 0x11e1 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS 0x11e2 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1 0x11e3 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2 0x11e4 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC 0x11e5 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1 0x11e6 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE 0x11e7 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK 0x11e9 +#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1 0x11ea +#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2 0x11eb +#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3 0x11ec +#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2 0x11ed +#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3 0x11ee +#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4 0x11ef +#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1 0x11f0 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2 0x11f1 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES 0x11f2 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL 0x11f3 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1 0x11f4 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2 0x11f5 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ 0x11f6 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1 0x11f7 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2 0x11f8 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF 0x11f9 +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1 0x11fa +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2 0x11fb +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3 0x11fc +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4 0x11fd +#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC 0x11fe +#define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1 0x11ff +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e +#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA 0x121f +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f +#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 +#define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL 0x1232 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e +#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f +#define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL 0x1251 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR 0x1252 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT 0x1258 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ 0x1259 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a +#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e +#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 +#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 +#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 +#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 +#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL 0x12ae +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE 0x12b4 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0 0x12bb +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1 0x12bc +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 +#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS 0x12e0 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD 0x12e1 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS 0x12e2 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1 0x12e3 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2 0x12e4 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC 0x12e5 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1 0x12e6 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE 0x12e7 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK 0x12e9 +#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1 0x12ea +#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2 0x12eb +#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3 0x12ec +#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2 0x12ed +#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3 0x12ee +#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4 0x12ef +#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1 0x12f0 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2 0x12f1 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES 0x12f2 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL 0x12f3 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1 0x12f4 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2 0x12f5 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ 0x12f6 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1 0x12f7 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2 0x12f8 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF 0x12f9 +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1 0x12fa +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2 0x12fb +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3 0x12fc +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4 0x12fd +#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC 0x12fe +#define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1 0x12ff +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d +#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f +#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 +#define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL 0x1332 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 +#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0 0x13bb +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 +#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS 0x13e0 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD 0x13e1 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS 0x13e2 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1 0x13e3 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2 0x13e4 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC 0x13e5 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1 0x13e6 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE 0x13e7 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK 0x13e9 +#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1 0x13ea +#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2 0x13eb +#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3 0x13ec +#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2 0x13ed +#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3 0x13ee +#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4 0x13ef +#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL 0x2000 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 +#define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 +#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1 0x200a +#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL 0x200b +#define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE 0x200c +#define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE 0x200d +#define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA 0x200e +#define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD 0x200f +#define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 +#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1 0x2011 +#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2 0x2012 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f +#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP 0x302c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA 0x303c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e +#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c +#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 +#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP 0x312c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA 0x313c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e +#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c +#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 +#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP 0x322c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA 0x323c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e +#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c +#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 +#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP 0x332c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA 0x333c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e +#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c +#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 +#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS 0x401c +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS 0x4032 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 +#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS 0x411c +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS 0x4132 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 +#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS 0x421c +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS 0x4232 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 +#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS 0x431c +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS 0x4332 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 +#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS 0x701c +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS 0x7032 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 +#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 +#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO 0x8000 +#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI 0x8001 +#define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN 0x8002 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e +#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN 0x801f +#define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 +#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT 0x8021 +#define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN 0x8022 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 +#define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN 0x8036 +#define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN 0x8037 +#define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c +#define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL 0x8040 +#define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL 0x8041 +#define ixDPCSSYS_CR1_SUPX_ANA_BG1 0x8042 +#define ixDPCSSYS_CR1_SUPX_ANA_BG2 0x8043 +#define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 +#define ixDPCSSYS_CR1_SUPX_ANA_BG3 0x8045 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1 0x8046 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2 0x8047 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD 0x8048 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1 0x8049 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2 0x804a +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3 0x804b +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1 0x804c +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2 0x804d +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3 0x804e +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4 0x804f +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5 0x8050 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1 0x8051 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2 0x8052 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1 0x8053 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2 0x8054 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD 0x8055 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1 0x8056 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2 0x8057 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3 0x8058 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1 0x8059 +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2 0x805a +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3 0x805b +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4 0x805c +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5 0x805d +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1 0x805e +#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2 0x805f +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 +#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 +#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 +#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 +#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a +#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b +#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG 0x8081 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT 0x8082 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT 0x8086 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a +#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT 0x8093 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 +#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e +#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA 0x901f +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f +#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 +#define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL 0x9032 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e +#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f +#define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL 0x9051 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR 0x9052 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT 0x9058 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ 0x9059 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a +#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e +#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 +#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 +#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 +#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 +#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL 0x90ae +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE 0x90b4 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0 0x90bb +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1 0x90bc +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 +#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS 0x90e0 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD 0x90e1 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS 0x90e2 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1 0x90e3 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2 0x90e4 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC 0x90e5 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1 0x90e6 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE 0x90e7 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK 0x90e9 +#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1 0x90ea +#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2 0x90eb +#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3 0x90ec +#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2 0x90ed +#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3 0x90ee +#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4 0x90ef +#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1 0x90f0 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2 0x90f1 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES 0x90f2 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL 0x90f3 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1 0x90f4 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2 0x90f5 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ 0x90f6 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1 0x90f7 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2 0x90f8 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF 0x90f9 +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1 0x90fa +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2 0x90fb +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3 0x90fc +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4 0x90fd +#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC 0x90fe +#define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1 0x90ff +#define ixDPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 +#define ixDPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA 0xe03c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e +#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c +#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 +#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 + + +// addressBlock: dpcssys_cr2_rdpcstxcrind +// base address: 0x0 +#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO 0x0000 +#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI 0x0001 +#define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN 0x0002 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3 0x000e +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4 0x000f +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3 0x001a +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4 0x001b +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5 0x001c +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e +#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN 0x001f +#define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN 0x0020 +#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT 0x0021 +#define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN 0x0022 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6 0x002a +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0 0x002b +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1 0x002c +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2 0x002d +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3 0x002e +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4 0x002f +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 +#define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN 0x0036 +#define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN 0x0037 +#define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN 0x0038 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c +#define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL 0x0040 +#define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL 0x0041 +#define ixDPCSSYS_CR2_SUP_ANA_BG1 0x0042 +#define ixDPCSSYS_CR2_SUP_ANA_BG2 0x0043 +#define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS 0x0044 +#define ixDPCSSYS_CR2_SUP_ANA_BG3 0x0045 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1 0x0046 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2 0x0047 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD 0x0048 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1 0x0049 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2 0x004a +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3 0x004b +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1 0x004c +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2 0x004d +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3 0x004e +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4 0x004f +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5 0x0050 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1 0x0051 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2 0x0052 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1 0x0053 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2 0x0054 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD 0x0055 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1 0x0056 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2 0x0057 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3 0x0058 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1 0x0059 +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2 0x005a +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3 0x005b +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4 0x005c +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5 0x005d +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1 0x005e +#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2 0x005f +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 +#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 +#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 +#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 +#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a +#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b +#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD 0x007c +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG 0x0081 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT 0x0082 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT 0x0086 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT 0x0087 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT 0x0088 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a +#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT 0x0093 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 +#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d +#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f +#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 +#define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL 0x1032 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 +#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0 0x10bb +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 +#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS 0x10e0 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD 0x10e1 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS 0x10e2 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1 0x10e3 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2 0x10e4 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC 0x10e5 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1 0x10e6 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE 0x10e7 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK 0x10e9 +#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1 0x10ea +#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2 0x10eb +#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3 0x10ec +#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2 0x10ed +#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3 0x10ee +#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4 0x10ef +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e +#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA 0x111f +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f +#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 +#define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL 0x1132 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e +#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f +#define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL 0x1151 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR 0x1152 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT 0x1158 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ 0x1159 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a +#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e +#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 +#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 +#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 +#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 +#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL 0x11ae +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE 0x11b4 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0 0x11bb +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1 0x11bc +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 +#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS 0x11e0 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD 0x11e1 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS 0x11e2 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1 0x11e3 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2 0x11e4 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC 0x11e5 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1 0x11e6 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE 0x11e7 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK 0x11e9 +#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1 0x11ea +#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2 0x11eb +#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3 0x11ec +#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2 0x11ed +#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3 0x11ee +#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4 0x11ef +#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1 0x11f0 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2 0x11f1 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES 0x11f2 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL 0x11f3 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1 0x11f4 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2 0x11f5 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ 0x11f6 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1 0x11f7 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2 0x11f8 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF 0x11f9 +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1 0x11fa +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2 0x11fb +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3 0x11fc +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4 0x11fd +#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC 0x11fe +#define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1 0x11ff +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e +#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA 0x121f +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f +#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 +#define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL 0x1232 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e +#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f +#define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL 0x1251 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR 0x1252 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT 0x1258 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ 0x1259 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a +#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e +#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 +#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 +#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 +#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 +#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL 0x12ae +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE 0x12b4 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0 0x12bb +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1 0x12bc +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 +#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS 0x12e0 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD 0x12e1 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS 0x12e2 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1 0x12e3 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2 0x12e4 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC 0x12e5 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1 0x12e6 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE 0x12e7 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK 0x12e9 +#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1 0x12ea +#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2 0x12eb +#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3 0x12ec +#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2 0x12ed +#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3 0x12ee +#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4 0x12ef +#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1 0x12f0 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2 0x12f1 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES 0x12f2 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL 0x12f3 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1 0x12f4 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2 0x12f5 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ 0x12f6 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1 0x12f7 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2 0x12f8 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF 0x12f9 +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1 0x12fa +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2 0x12fb +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3 0x12fc +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4 0x12fd +#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC 0x12fe +#define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1 0x12ff +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d +#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f +#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 +#define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL 0x1332 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 +#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0 0x13bb +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 +#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS 0x13e0 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD 0x13e1 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS 0x13e2 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1 0x13e3 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2 0x13e4 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC 0x13e5 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1 0x13e6 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE 0x13e7 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK 0x13e9 +#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1 0x13ea +#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2 0x13eb +#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3 0x13ec +#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2 0x13ed +#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3 0x13ee +#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4 0x13ef +#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL 0x2000 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 +#define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 +#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1 0x200a +#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL 0x200b +#define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE 0x200c +#define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE 0x200d +#define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA 0x200e +#define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD 0x200f +#define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 +#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1 0x2011 +#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2 0x2012 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f +#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP 0x302c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA 0x303c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e +#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c +#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 +#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP 0x312c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA 0x313c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e +#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c +#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 +#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP 0x322c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA 0x323c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e +#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c +#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 +#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP 0x332c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA 0x333c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e +#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c +#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 +#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS 0x401c +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS 0x4032 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 +#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS 0x411c +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS 0x4132 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 +#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS 0x421c +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS 0x4232 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 +#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS 0x431c +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS 0x4332 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 +#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS 0x701c +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS 0x7032 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 +#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 +#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO 0x8000 +#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI 0x8001 +#define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN 0x8002 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e +#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN 0x801f +#define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 +#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT 0x8021 +#define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN 0x8022 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 +#define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN 0x8036 +#define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN 0x8037 +#define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c +#define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL 0x8040 +#define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL 0x8041 +#define ixDPCSSYS_CR2_SUPX_ANA_BG1 0x8042 +#define ixDPCSSYS_CR2_SUPX_ANA_BG2 0x8043 +#define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 +#define ixDPCSSYS_CR2_SUPX_ANA_BG3 0x8045 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1 0x8046 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2 0x8047 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD 0x8048 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1 0x8049 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2 0x804a +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3 0x804b +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1 0x804c +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2 0x804d +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3 0x804e +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4 0x804f +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5 0x8050 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1 0x8051 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2 0x8052 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1 0x8053 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2 0x8054 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD 0x8055 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1 0x8056 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2 0x8057 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3 0x8058 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1 0x8059 +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2 0x805a +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3 0x805b +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4 0x805c +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5 0x805d +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1 0x805e +#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2 0x805f +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 +#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 +#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 +#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 +#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a +#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b +#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG 0x8081 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT 0x8082 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT 0x8086 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a +#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT 0x8093 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 +#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e +#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA 0x901f +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f +#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 +#define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL 0x9032 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e +#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f +#define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL 0x9051 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR 0x9052 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT 0x9058 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ 0x9059 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a +#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e +#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 +#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 +#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 +#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 +#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL 0x90ae +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE 0x90b4 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0 0x90bb +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1 0x90bc +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 +#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS 0x90e0 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD 0x90e1 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS 0x90e2 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1 0x90e3 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2 0x90e4 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC 0x90e5 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1 0x90e6 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE 0x90e7 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK 0x90e9 +#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1 0x90ea +#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2 0x90eb +#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3 0x90ec +#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2 0x90ed +#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3 0x90ee +#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4 0x90ef +#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1 0x90f0 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2 0x90f1 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES 0x90f2 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL 0x90f3 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1 0x90f4 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2 0x90f5 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ 0x90f6 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1 0x90f7 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2 0x90f8 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF 0x90f9 +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1 0x90fa +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2 0x90fb +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3 0x90fc +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4 0x90fd +#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC 0x90fe +#define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1 0x90ff +#define ixDPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 +#define ixDPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA 0xe03c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e +#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c +#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 +#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 + + +// addressBlock: dpcssys_cr3_rdpcstxcrind +// base address: 0x0 +#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO 0x0000 +#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI 0x0001 +#define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN 0x0002 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3 0x000e +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4 0x000f +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3 0x001a +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4 0x001b +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5 0x001c +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e +#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN 0x001f +#define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN 0x0020 +#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT 0x0021 +#define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN 0x0022 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6 0x002a +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0 0x002b +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1 0x002c +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2 0x002d +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3 0x002e +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4 0x002f +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 +#define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN 0x0036 +#define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN 0x0037 +#define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN 0x0038 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c +#define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL 0x0040 +#define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL 0x0041 +#define ixDPCSSYS_CR3_SUP_ANA_BG1 0x0042 +#define ixDPCSSYS_CR3_SUP_ANA_BG2 0x0043 +#define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS 0x0044 +#define ixDPCSSYS_CR3_SUP_ANA_BG3 0x0045 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1 0x0046 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2 0x0047 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD 0x0048 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1 0x0049 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2 0x004a +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3 0x004b +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1 0x004c +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2 0x004d +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3 0x004e +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4 0x004f +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5 0x0050 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1 0x0051 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2 0x0052 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1 0x0053 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2 0x0054 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD 0x0055 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1 0x0056 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2 0x0057 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3 0x0058 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1 0x0059 +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2 0x005a +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3 0x005b +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4 0x005c +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5 0x005d +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1 0x005e +#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2 0x005f +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 +#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 +#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 +#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 +#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a +#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b +#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD 0x007c +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG 0x0081 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT 0x0082 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT 0x0086 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT 0x0087 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT 0x0088 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a +#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT 0x0093 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 +#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d +#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f +#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 +#define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL 0x1032 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 +#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0 0x10bb +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 +#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS 0x10e0 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD 0x10e1 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS 0x10e2 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1 0x10e3 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2 0x10e4 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC 0x10e5 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1 0x10e6 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE 0x10e7 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK 0x10e9 +#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1 0x10ea +#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2 0x10eb +#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3 0x10ec +#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2 0x10ed +#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3 0x10ee +#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4 0x10ef +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e +#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA 0x111f +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f +#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 +#define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL 0x1132 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e +#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f +#define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL 0x1151 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR 0x1152 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT 0x1158 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ 0x1159 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a +#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e +#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 +#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 +#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 +#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 +#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL 0x11ae +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE 0x11b4 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0 0x11bb +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1 0x11bc +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 +#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS 0x11e0 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD 0x11e1 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS 0x11e2 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1 0x11e3 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2 0x11e4 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC 0x11e5 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1 0x11e6 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE 0x11e7 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK 0x11e9 +#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1 0x11ea +#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2 0x11eb +#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3 0x11ec +#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2 0x11ed +#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3 0x11ee +#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4 0x11ef +#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1 0x11f0 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2 0x11f1 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES 0x11f2 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL 0x11f3 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1 0x11f4 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2 0x11f5 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ 0x11f6 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1 0x11f7 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2 0x11f8 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF 0x11f9 +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1 0x11fa +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2 0x11fb +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3 0x11fc +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4 0x11fd +#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC 0x11fe +#define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1 0x11ff +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e +#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA 0x121f +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f +#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 +#define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL 0x1232 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e +#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f +#define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL 0x1251 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR 0x1252 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT 0x1258 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ 0x1259 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a +#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e +#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 +#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 +#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 +#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 +#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL 0x12ae +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE 0x12b4 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0 0x12bb +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1 0x12bc +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 +#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS 0x12e0 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD 0x12e1 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS 0x12e2 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1 0x12e3 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2 0x12e4 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC 0x12e5 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1 0x12e6 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE 0x12e7 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK 0x12e9 +#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1 0x12ea +#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2 0x12eb +#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3 0x12ec +#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2 0x12ed +#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3 0x12ee +#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4 0x12ef +#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1 0x12f0 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2 0x12f1 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES 0x12f2 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL 0x12f3 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1 0x12f4 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2 0x12f5 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ 0x12f6 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1 0x12f7 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2 0x12f8 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF 0x12f9 +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1 0x12fa +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2 0x12fb +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3 0x12fc +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4 0x12fd +#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC 0x12fe +#define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1 0x12ff +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d +#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f +#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 +#define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL 0x1332 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 +#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0 0x13bb +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 +#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS 0x13e0 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD 0x13e1 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS 0x13e2 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1 0x13e3 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2 0x13e4 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC 0x13e5 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1 0x13e6 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE 0x13e7 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK 0x13e9 +#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1 0x13ea +#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2 0x13eb +#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3 0x13ec +#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2 0x13ed +#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3 0x13ee +#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4 0x13ef +#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL 0x2000 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 +#define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 +#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1 0x200a +#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL 0x200b +#define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE 0x200c +#define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE 0x200d +#define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA 0x200e +#define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD 0x200f +#define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 +#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1 0x2011 +#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2 0x2012 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f +#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP 0x302c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA 0x303c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e +#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c +#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 +#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP 0x312c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA 0x313c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e +#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c +#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 +#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP 0x322c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA 0x323c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e +#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c +#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 +#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP 0x332c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA 0x333c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e +#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c +#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 +#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS 0x401c +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS 0x4032 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 +#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS 0x411c +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS 0x4132 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 +#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS 0x421c +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS 0x4232 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 +#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS 0x431c +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS 0x4332 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 +#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS 0x701c +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS 0x7032 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 +#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 +#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO 0x8000 +#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI 0x8001 +#define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN 0x8002 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e +#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN 0x801f +#define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 +#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT 0x8021 +#define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN 0x8022 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 +#define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN 0x8036 +#define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN 0x8037 +#define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c +#define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL 0x8040 +#define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL 0x8041 +#define ixDPCSSYS_CR3_SUPX_ANA_BG1 0x8042 +#define ixDPCSSYS_CR3_SUPX_ANA_BG2 0x8043 +#define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 +#define ixDPCSSYS_CR3_SUPX_ANA_BG3 0x8045 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1 0x8046 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2 0x8047 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD 0x8048 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1 0x8049 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2 0x804a +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3 0x804b +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1 0x804c +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2 0x804d +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3 0x804e +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4 0x804f +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5 0x8050 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1 0x8051 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2 0x8052 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1 0x8053 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2 0x8054 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD 0x8055 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1 0x8056 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2 0x8057 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3 0x8058 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1 0x8059 +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2 0x805a +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3 0x805b +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4 0x805c +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5 0x805d +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1 0x805e +#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2 0x805f +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 +#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 +#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 +#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 +#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a +#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b +#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG 0x8081 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT 0x8082 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT 0x8086 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a +#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT 0x8093 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 +#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e +#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA 0x901f +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f +#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 +#define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL 0x9032 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e +#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f +#define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL 0x9051 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR 0x9052 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT 0x9058 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ 0x9059 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a +#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e +#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 +#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 +#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 +#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 +#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL 0x90ae +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE 0x90b4 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0 0x90bb +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1 0x90bc +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 +#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS 0x90e0 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD 0x90e1 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS 0x90e2 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1 0x90e3 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2 0x90e4 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC 0x90e5 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1 0x90e6 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE 0x90e7 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK 0x90e9 +#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1 0x90ea +#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2 0x90eb +#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3 0x90ec +#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2 0x90ed +#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3 0x90ee +#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4 0x90ef +#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1 0x90f0 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2 0x90f1 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES 0x90f2 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL 0x90f3 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1 0x90f4 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2 0x90f5 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ 0x90f6 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1 0x90f7 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2 0x90f8 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF 0x90f9 +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1 0x90fa +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2 0x90fb +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3 0x90fc +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4 0x90fd +#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC 0x90fe +#define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1 0x90ff +#define ixDPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 +#define ixDPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA 0xe03c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e +#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c +#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 +#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 + + +// addressBlock: dpcssys_cr4_rdpcstxcrind +// base address: 0x0 +#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO 0x0000 +#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI 0x0001 +#define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN 0x0002 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3 0x000e +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4 0x000f +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3 0x001a +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4 0x001b +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5 0x001c +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e +#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN 0x001f +#define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN 0x0020 +#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT 0x0021 +#define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN 0x0022 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6 0x002a +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0 0x002b +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1 0x002c +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2 0x002d +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3 0x002e +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4 0x002f +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 +#define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN 0x0036 +#define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN 0x0037 +#define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN 0x0038 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c +#define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL 0x0040 +#define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL 0x0041 +#define ixDPCSSYS_CR4_SUP_ANA_BG1 0x0042 +#define ixDPCSSYS_CR4_SUP_ANA_BG2 0x0043 +#define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS 0x0044 +#define ixDPCSSYS_CR4_SUP_ANA_BG3 0x0045 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1 0x0046 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2 0x0047 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD 0x0048 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1 0x0049 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2 0x004a +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3 0x004b +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1 0x004c +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2 0x004d +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3 0x004e +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4 0x004f +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5 0x0050 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1 0x0051 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2 0x0052 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1 0x0053 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2 0x0054 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD 0x0055 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1 0x0056 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2 0x0057 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3 0x0058 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1 0x0059 +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2 0x005a +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3 0x005b +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4 0x005c +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5 0x005d +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1 0x005e +#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2 0x005f +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 +#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 +#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 +#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 +#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a +#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b +#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD 0x007c +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG 0x0081 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT 0x0082 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT 0x0086 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT 0x0087 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT 0x0088 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a +#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT 0x0093 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 +#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d +#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f +#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 +#define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL 0x1032 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 +#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0 0x10bb +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 +#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS 0x10e0 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD 0x10e1 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS 0x10e2 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1 0x10e3 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2 0x10e4 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC 0x10e5 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1 0x10e6 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE 0x10e7 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK 0x10e9 +#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1 0x10ea +#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2 0x10eb +#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3 0x10ec +#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2 0x10ed +#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3 0x10ee +#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4 0x10ef +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e +#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA 0x111f +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f +#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 +#define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL 0x1132 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e +#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f +#define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL 0x1151 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR 0x1152 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT 0x1158 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ 0x1159 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a +#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e +#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 +#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 +#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 +#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 +#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL 0x11ae +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE 0x11b4 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0 0x11bb +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1 0x11bc +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 +#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS 0x11e0 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD 0x11e1 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS 0x11e2 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1 0x11e3 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2 0x11e4 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC 0x11e5 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1 0x11e6 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE 0x11e7 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK 0x11e9 +#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1 0x11ea +#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2 0x11eb +#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3 0x11ec +#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2 0x11ed +#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3 0x11ee +#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4 0x11ef +#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1 0x11f0 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2 0x11f1 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES 0x11f2 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL 0x11f3 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1 0x11f4 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2 0x11f5 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ 0x11f6 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1 0x11f7 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2 0x11f8 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF 0x11f9 +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1 0x11fa +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2 0x11fb +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3 0x11fc +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4 0x11fd +#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC 0x11fe +#define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1 0x11ff +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e +#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA 0x121f +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f +#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 +#define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL 0x1232 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e +#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f +#define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL 0x1251 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR 0x1252 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT 0x1258 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ 0x1259 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a +#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e +#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 +#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 +#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 +#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 +#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL 0x12ae +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE 0x12b4 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0 0x12bb +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1 0x12bc +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 +#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS 0x12e0 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD 0x12e1 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS 0x12e2 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1 0x12e3 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2 0x12e4 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC 0x12e5 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1 0x12e6 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE 0x12e7 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK 0x12e9 +#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1 0x12ea +#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2 0x12eb +#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3 0x12ec +#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2 0x12ed +#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3 0x12ee +#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4 0x12ef +#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1 0x12f0 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2 0x12f1 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES 0x12f2 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL 0x12f3 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1 0x12f4 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2 0x12f5 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ 0x12f6 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1 0x12f7 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2 0x12f8 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF 0x12f9 +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1 0x12fa +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2 0x12fb +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3 0x12fc +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4 0x12fd +#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC 0x12fe +#define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1 0x12ff +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d +#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f +#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 +#define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL 0x1332 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 +#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0 0x13bb +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 +#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS 0x13e0 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD 0x13e1 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS 0x13e2 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1 0x13e3 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2 0x13e4 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC 0x13e5 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1 0x13e6 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE 0x13e7 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK 0x13e9 +#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1 0x13ea +#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2 0x13eb +#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3 0x13ec +#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2 0x13ed +#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3 0x13ee +#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4 0x13ef +#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL 0x2000 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 +#define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 +#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1 0x200a +#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL 0x200b +#define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE 0x200c +#define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE 0x200d +#define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA 0x200e +#define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD 0x200f +#define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 +#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1 0x2011 +#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2 0x2012 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f +#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP 0x302c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA 0x303c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e +#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c +#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 +#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP 0x312c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA 0x313c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e +#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c +#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 +#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP 0x322c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA 0x323c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e +#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c +#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 +#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP 0x332c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA 0x333c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e +#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c +#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 +#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS 0x401c +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS 0x4032 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 +#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS 0x411c +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS 0x4132 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 +#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS 0x421c +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS 0x4232 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 +#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS 0x431c +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS 0x4332 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 +#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS 0x701c +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS 0x7032 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 +#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 +#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO 0x8000 +#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI 0x8001 +#define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN 0x8002 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e +#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN 0x801f +#define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 +#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT 0x8021 +#define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN 0x8022 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 +#define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN 0x8036 +#define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN 0x8037 +#define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c +#define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL 0x8040 +#define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL 0x8041 +#define ixDPCSSYS_CR4_SUPX_ANA_BG1 0x8042 +#define ixDPCSSYS_CR4_SUPX_ANA_BG2 0x8043 +#define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 +#define ixDPCSSYS_CR4_SUPX_ANA_BG3 0x8045 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1 0x8046 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2 0x8047 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD 0x8048 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1 0x8049 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2 0x804a +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3 0x804b +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1 0x804c +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2 0x804d +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3 0x804e +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4 0x804f +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5 0x8050 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1 0x8051 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2 0x8052 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1 0x8053 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2 0x8054 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD 0x8055 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1 0x8056 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2 0x8057 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3 0x8058 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1 0x8059 +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2 0x805a +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3 0x805b +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4 0x805c +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5 0x805d +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1 0x805e +#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2 0x805f +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 +#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 +#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 +#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 +#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a +#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b +#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG 0x8081 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT 0x8082 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT 0x8086 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a +#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT 0x8093 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 +#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e +#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA 0x901f +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f +#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 +#define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL 0x9032 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e +#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f +#define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL 0x9051 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR 0x9052 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT 0x9058 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ 0x9059 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a +#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e +#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 +#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 +#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 +#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 +#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL 0x90ae +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE 0x90b4 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0 0x90bb +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1 0x90bc +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 +#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS 0x90e0 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD 0x90e1 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS 0x90e2 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1 0x90e3 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2 0x90e4 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC 0x90e5 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1 0x90e6 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE 0x90e7 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK 0x90e9 +#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1 0x90ea +#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2 0x90eb +#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3 0x90ec +#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2 0x90ed +#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3 0x90ee +#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4 0x90ef +#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1 0x90f0 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2 0x90f1 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES 0x90f2 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL 0x90f3 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1 0x90f4 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2 0x90f5 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ 0x90f6 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1 0x90f7 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2 0x90f8 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF 0x90f9 +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1 0x90fa +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2 0x90fb +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3 0x90fc +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4 0x90fd +#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC 0x90fe +#define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1 0x90ff +#define ixDPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 +#define ixDPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA 0xe03c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e +#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c +#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 +#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h new file mode 100644 index 000000000000..068f3b16a56b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h @@ -0,0 +1,103385 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dpcs_4_2_0_SH_MASK_HEADER +#define _dpcs_4_2_0_SH_MASK_HEADER + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +//DPCSSYS_CR0_DPCSSYS_CR_ADDR +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_DPCSSYS_CR_DATA +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcssys_cr1_dispdec +//DPCSSYS_CR1_DPCSSYS_CR_ADDR +#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_DPCSSYS_CR_DATA +#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcssys_cr2_dispdec +//DPCSSYS_CR2_DPCSSYS_CR_ADDR +#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_DPCSSYS_CR_DATA +#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcssys_cr3_dispdec +//DPCSSYS_CR3_DPCSSYS_CR_ADDR +#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_DPCSSYS_CR_DATA +#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcssys_cr4_dispdec +//DPCSSYS_CR4_DPCSSYS_CR_ADDR +#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_DPCSSYS_CR_DATA +#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec +//PWRSEQ0_DC_GPIO_PWRSEQ_EN +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT 0x2 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK 0x00000004L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +//PWRSEQ0_DC_GPIO_PWRSEQ_MASK +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PWRSEQ0_PANEL_PWRSEQ_CNTL +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PWRSEQ0_PANEL_PWRSEQ_STATE +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PWRSEQ0_PANEL_PWRSEQ_DELAY1 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PWRSEQ0_PANEL_PWRSEQ_DELAY2 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//PWRSEQ0_BL_PWM_CNTL +#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//PWRSEQ0_BL_PWM_CNTL2 +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//PWRSEQ0_BL_PWM_PERIOD_CNTL +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//PWRSEQ0_BL_PWM_GRP1_REG_LOCK +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ0_PWRSEQ_SPARE +#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec +//PWRSEQ1_DC_GPIO_PWRSEQ_EN +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00010000L +//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT 0x2 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT 0x3 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT 0x4 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT 0x5 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT 0x6 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT 0x7 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK 0x00000004L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK 0x00000008L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK 0x00000010L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK 0x00000020L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK 0x00000040L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK 0x00000080L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +//PWRSEQ1_DC_GPIO_PWRSEQ_MASK +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT 0x4 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT 0x6 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x14 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x16 +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK 0x00000010L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK 0x000000C0L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00010000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00100000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00C00000L +//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT 0x0 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT 0x1 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT 0x9 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT 0x10 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT 0x11 +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK 0x00000001L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK 0x00000002L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK 0x00000100L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK 0x00000200L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK 0x00010000L +#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK 0x00020000L +//PWRSEQ1_PANEL_PWRSEQ_CNTL +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT 0x9 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT 0x11 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT 0x12 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT 0x19 +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT 0x1a +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK 0x00000001L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK 0x00000100L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK 0x00000200L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK 0x00000400L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK 0x00010000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK 0x00020000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK 0x00040000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK 0x01000000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK 0x02000000L +#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK 0x04000000L +//PWRSEQ1_PANEL_PWRSEQ_STATE +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT 0x1 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT 0x2 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT 0x3 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT 0x4 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK 0x00000002L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK 0x00000004L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK 0x00000008L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK 0x00000010L +#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK 0x00000F00L +//PWRSEQ1_PANEL_PWRSEQ_DELAY1 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK 0x000000FFL +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK 0x0000FF00L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK 0x00FF0000L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK 0xFF000000L +//PWRSEQ1_PANEL_PWRSEQ_DELAY2 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK 0x0000FF00L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK 0x00FF0000L +#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//PWRSEQ1_BL_PWM_CNTL +#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT 0x13 +#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT 0x14 +#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x15 +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK 0x00080000L +#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK 0x00100000L +#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x00200000L +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//PWRSEQ1_BL_PWM_CNTL2 +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK 0x80000000L +//PWRSEQ1_BL_PWM_PERIOD_CNTL +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//PWRSEQ1_BL_PWM_GRP1_REG_LOCK +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT 0x0 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT 0x10 +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK 0x0000007FL +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK 0x00007F00L +#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK 0x00010000L +//PWRSEQ1_PWRSEQ_SPARE +#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT 0x0 +#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +//RDPCSTX0_RDPCSTX_CNTL +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_CLOCK_CNTL +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX0_RDPCS_TX_CR_ADDR +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_CR_DATA +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_SRAM_CNTL +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX0_RDPCSTX_SCRATCH +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_SPARE +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_CNTL2 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK 0x0000000CL +//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX0_RDPCSTX_PHY_CNTL0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX0_RDPCSTX_PHY_CNTL2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX0_RDPCSTX_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PHY_CNTL7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX0_RDPCSTX_PHY_CNTL8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX0_RDPCSTX_PHY_CNTL13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE1 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE2 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX0_RDPCSTX_PHY_FUSE3 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX0_RDPCSTX_PHY_CNTL15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PHY_CNTL16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX0_RDPCS_CNTL3 +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT 0x0 +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT 0x8 +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT 0x10 +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT 0x18 +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK 0x000000FFL +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK 0x0000FF00L +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK 0x00FF0000L +#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK 0xFF000000L +//RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK 0x0003FFFFL +//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +//RDPCSTX1_RDPCSTX_CNTL +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_CLOCK_CNTL +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX1_RDPCS_TX_CR_ADDR +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_CR_DATA +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_SRAM_CNTL +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX1_RDPCSTX_SCRATCH +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_SPARE +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_CNTL2 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK 0x0000000CL +//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX1_RDPCSTX_PHY_CNTL0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX1_RDPCSTX_PHY_CNTL2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX1_RDPCSTX_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PHY_CNTL7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX1_RDPCSTX_PHY_CNTL8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX1_RDPCSTX_PHY_CNTL13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE1 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE2 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX1_RDPCSTX_PHY_FUSE3 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX1_RDPCSTX_PHY_CNTL15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PHY_CNTL16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX1_RDPCS_CNTL3 +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT 0x0 +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT 0x8 +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT 0x10 +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT 0x18 +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK 0x000000FFL +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK 0x0000FF00L +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK 0x00FF0000L +#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK 0xFF000000L +//RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK 0x0003FFFFL +//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec +//RDPCSTX2_RDPCSTX_CNTL +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x40000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_CLOCK_CNTL +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK 0x00000800L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX2_RDPCS_TX_CR_ADDR +#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX2_RDPCS_TX_CR_DATA +#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX2_RDPCS_TX_SRAM_CNTL +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX2_RDPCSTX_SCRATCH +#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX2_RDPCSTX_SPARE +#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX2_RDPCSTX_CNTL2 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK 0x0000000CL +//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX2_RDPCSTX_PHY_CNTL0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX2_RDPCSTX_PHY_CNTL2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX2_RDPCSTX_PHY_CNTL3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_PHY_CNTL7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX2_RDPCSTX_PHY_CNTL8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX2_RDPCSTX_PHY_CNTL9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX2_RDPCSTX_PHY_CNTL11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX2_RDPCSTX_PHY_CNTL13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE1 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE2 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX2_RDPCSTX_PHY_FUSE3 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX2_RDPCSTX_PHY_CNTL15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_PHY_CNTL16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX2_RDPCS_CNTL3 +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT 0x0 +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT 0x8 +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT 0x10 +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT 0x18 +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK 0x000000FFL +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK 0x0000FF00L +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK 0x00FF0000L +#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK 0xFF000000L +//RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK 0x0003FFFFL +//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec +//RDPCSTX3_RDPCSTX_CNTL +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x40000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_CLOCK_CNTL +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK 0x00000800L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX3_RDPCS_TX_CR_ADDR +#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX3_RDPCS_TX_CR_DATA +#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX3_RDPCS_TX_SRAM_CNTL +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX3_RDPCSTX_SCRATCH +#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX3_RDPCSTX_SPARE +#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX3_RDPCSTX_CNTL2 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK 0x0000000CL +//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX3_RDPCSTX_PHY_CNTL0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX3_RDPCSTX_PHY_CNTL2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX3_RDPCSTX_PHY_CNTL3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_PHY_CNTL7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX3_RDPCSTX_PHY_CNTL8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX3_RDPCSTX_PHY_CNTL9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX3_RDPCSTX_PHY_CNTL11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX3_RDPCSTX_PHY_CNTL13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE1 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE2 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX3_RDPCSTX_PHY_FUSE3 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX3_RDPCSTX_PHY_CNTL15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_PHY_CNTL16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX3_RDPCS_CNTL3 +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT 0x0 +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT 0x8 +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT 0x10 +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT 0x18 +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK 0x000000FFL +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK 0x0000FF00L +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK 0x00FF0000L +#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK 0xFF000000L +//RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK 0x0003FFFFL +//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec +//RDPCSTX4_RDPCSTX_CNTL +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x40000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_CLOCK_CNTL +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK 0x00000800L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX4_RDPCS_TX_CR_ADDR +#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX4_RDPCS_TX_CR_DATA +#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX4_RDPCS_TX_SRAM_CNTL +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX4_RDPCSTX_SCRATCH +#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX4_RDPCSTX_SPARE +#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX4_RDPCSTX_CNTL2 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK 0x0000000CL +//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX4_RDPCSTX_PHY_CNTL0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX4_RDPCSTX_PHY_CNTL2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX4_RDPCSTX_PHY_CNTL3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_PHY_CNTL7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX4_RDPCSTX_PHY_CNTL8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX4_RDPCSTX_PHY_CNTL9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX4_RDPCSTX_PHY_CNTL11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX4_RDPCSTX_PHY_CNTL13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE1 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE2 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX4_RDPCSTX_PHY_FUSE3 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX4_RDPCSTX_PHY_CNTL15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_PHY_CNTL16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX4_RDPCS_CNTL3 +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT 0x0 +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT 0x8 +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT 0x10 +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT 0x18 +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK 0x000000FFL +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK 0x0000FF00L +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK 0x00FF0000L +#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK 0xFF000000L +//RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK 0x0003FFFFL +//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT 0x10 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK 0x00010000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK 0x00000200L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT 0x1c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK 0xF0000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_PWRSEQ1_EN +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + + +// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dpcssys_cr0_rdpcstxcrind +//DPCSSYS_CR0_SUP_DIG_IDCODE_LO +#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_IDCODE_HI +#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_BG1 +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_BG2 +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_BG3 +#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_RTUNE_STAT +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUP_DIG_ANA_STAT +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_ATB1 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_ATB2 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_MISC1 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_MISC2 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_MISC3 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_ATB1 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_ATB2 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_MISC1 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_MISC2 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_MISC3 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_CLK_1 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_CLK_2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_SQ +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_CAL1 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_CAL2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1 +#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_ATB1 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_ATB2 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_MISC1 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_MISC2 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_MISC3 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_CLK_1 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_CLK_2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_SQ +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_CAL1 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_CAL2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1 +#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_ATB1 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_ATB2 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_MISC1 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_MISC2 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_MISC3 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND +#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK 0x00000300L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT 0xe +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK 0x00001E00L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE +#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE +#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWCMN_DIG_OCLA +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE +#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1 +#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2 +#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT 0x3 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK 0x00000008L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_STATS +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_STATS +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_STATS +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_STATS +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_STATS +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_IDCODE_LO +#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_IDCODE_HI +#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_BG1 +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_BG2 +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_BG3 +#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_SUPX_DIG_ANA_STAT +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_ATB1 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_ATB2 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_MISC1 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_MISC2 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_MISC3 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_CLK_1 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_CLK_2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_SQ +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_CAL1 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_CAL2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1 +#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0 +#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0 +#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L + + +// addressBlock: dpcssys_cr1_rdpcstxcrind +//DPCSSYS_CR1_SUP_DIG_IDCODE_LO +#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_IDCODE_HI +#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_BG1 +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_BG2 +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_BG3 +#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_RTUNE_STAT +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUP_DIG_ANA_STAT +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_ATB1 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_ATB2 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_MISC1 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_MISC2 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_MISC3 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_ATB1 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_ATB2 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_MISC1 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_MISC2 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_MISC3 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_CLK_1 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_CLK_2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_SQ +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_CAL1 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_CAL2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1 +#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_ATB1 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_ATB2 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_MISC1 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_MISC2 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_MISC3 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_CLK_1 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_CLK_2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_SQ +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_CAL1 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_CAL2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1 +#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_ATB1 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_ATB2 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_MISC1 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_MISC2 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_MISC3 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND +#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK 0x00000300L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT 0xe +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK 0x00001E00L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE +#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE +#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWCMN_DIG_OCLA +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE +#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1 +#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2 +#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT 0x3 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK 0x00000008L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_STATS +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_STATS +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_STATS +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_STATS +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_STATS +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_IDCODE_LO +#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_IDCODE_HI +#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_BG1 +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_BG2 +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_BG3 +#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_SUPX_DIG_ANA_STAT +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_ATB1 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_ATB2 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_MISC1 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_MISC2 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_MISC3 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_CLK_1 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_CLK_2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_SQ +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_CAL1 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_CAL2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1 +#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0 +#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0 +#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L + + +// addressBlock: dpcssys_cr2_rdpcstxcrind +//DPCSSYS_CR2_SUP_DIG_IDCODE_LO +#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_IDCODE_HI +#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_BG1 +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_BG2 +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_BG3 +#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_RTUNE_STAT +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUP_DIG_ANA_STAT +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_ATB1 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_ATB2 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_MISC1 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_MISC2 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_MISC3 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_ATB1 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_ATB2 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_MISC1 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_MISC2 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_MISC3 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_CLK_1 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_CLK_2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_SQ +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_CAL1 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_CAL2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1 +#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_ATB1 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_ATB2 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_MISC1 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_MISC2 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_MISC3 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_CLK_1 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_CLK_2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_SQ +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_CAL1 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_CAL2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1 +#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_ATB1 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_ATB2 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_MISC1 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_MISC2 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_MISC3 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND +#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK 0x00000300L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT 0xe +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK 0x00001E00L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE +#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE +#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWCMN_DIG_OCLA +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE +#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1 +#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2 +#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT 0x3 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK 0x00000008L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_STATS +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_STATS +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_STATS +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_STATS +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_STATS +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_IDCODE_LO +#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_IDCODE_HI +#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_BG1 +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_BG2 +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_BG3 +#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_SUPX_DIG_ANA_STAT +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_ATB1 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_ATB2 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_MISC1 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_MISC2 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_MISC3 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_CLK_1 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_CLK_2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_SQ +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_CAL1 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_CAL2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1 +#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0 +#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0 +#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L + + +// addressBlock: dpcssys_cr3_rdpcstxcrind +//DPCSSYS_CR3_SUP_DIG_IDCODE_LO +#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_IDCODE_HI +#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_BG1 +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_BG2 +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_BG3 +#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_RTUNE_STAT +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUP_DIG_ANA_STAT +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_ATB1 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_ATB2 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_MISC1 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_MISC2 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_MISC3 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_ATB1 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_ATB2 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_MISC1 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_MISC2 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_MISC3 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_CLK_1 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_CLK_2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_SQ +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_CAL1 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_CAL2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1 +#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_ATB1 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_ATB2 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_MISC1 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_MISC2 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_MISC3 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_CLK_1 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_CLK_2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_SQ +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_CAL1 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_CAL2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1 +#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_ATB1 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_ATB2 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_MISC1 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_MISC2 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_MISC3 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND +#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK 0x00000300L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT 0xe +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK 0x00001E00L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE +#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE +#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWCMN_DIG_OCLA +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE +#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1 +#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2 +#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT 0x3 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK 0x00000008L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_STATS +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_STATS +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_STATS +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_STATS +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_STATS +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_IDCODE_LO +#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_IDCODE_HI +#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_BG1 +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_BG2 +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_BG3 +#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_SUPX_DIG_ANA_STAT +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_ATB1 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_ATB2 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_MISC1 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_MISC2 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_MISC3 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_CLK_1 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_CLK_2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_SQ +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_CAL1 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_CAL2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1 +#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0 +#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0 +#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L + + +// addressBlock: dpcssys_cr4_rdpcstxcrind +//DPCSSYS_CR4_SUP_DIG_IDCODE_LO +#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_IDCODE_HI +#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_BG1 +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_BG2 +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_BG3 +#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_RTUNE_STAT +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUP_DIG_ANA_STAT +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_ATB1 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_ATB2 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_MISC1 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_MISC2 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_MISC3 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_ATB1 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_ATB2 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_MISC1 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_MISC2 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_MISC3 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_CLK_1 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_CLK_2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_SQ +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_CAL1 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_CAL2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1 +#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_ATB1 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_ATB2 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_MISC1 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_MISC2 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_MISC3 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_CLK_1 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_CLK_2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_SQ +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_CAL1 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_CAL2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1 +#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_ATB1 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_ATB2 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_MISC1 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_MISC2 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_MISC3 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK 0x0000001CL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND +#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK 0x000007FFL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK 0x00000300L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT 0xe +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK 0x00001E00L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE +#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE +#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWCMN_DIG_OCLA +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE +#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1 +#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2 +#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT 0x3 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK 0x00000008L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_STATS +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_STATS +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_STATS +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_STATS +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x00001C00L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_STATS +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK 0x00000030L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK 0x00000007L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK 0x00000038L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK 0x0000003FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT 0x8 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT 0x5 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT 0xa +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK 0x000003E0L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK 0x00000400L +#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT 0x0 +#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_IDCODE_LO +#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_IDCODE_HI +#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x000001F0L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK 0x00000600L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK 0x00007F00L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK 0x00000078L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK 0x000000FCL +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK 0x00000700L +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK 0x00003800L +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x00000070L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK 0x00000700L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK 0x00000060L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK 0x00000060L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK 0x00000300L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK 0x00000FFFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0x000001FEL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK 0x0000001CL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00000038L +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK 0x000001C0L +#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK 0x00000030L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_BG1 +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK 0x00000060L +#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_BG2 +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_BG3 +#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK 0x0000000CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK 0x0000007CL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK 0x000000E0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK 0x00000060L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK 0x000000C0L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK 0x0000003EL +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK 0x0000F800L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK 0x000003E0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK 0x00003F00L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK 0x0000FF00L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK 0x00000FC0L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK 0x00000003L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK 0x000001FFL +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK 0x0000001FL +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x00000C00L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK 0x000000F0L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK 0x00000F00L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK 0x0000F000L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK 0x000001F0L +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK 0x0000000FL +#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK 0x00000800L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK 0x00002000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK 0x000003FFL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK 0x0000007FL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK 0x00003F80L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x00000006L +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x00003FF0L +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_SUPX_DIG_ANA_STAT +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT 0x1 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT 0x2 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT 0x4 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK 0x00000001L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK 0x00000002L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK 0x00000004L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK 0x00000010L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK 0x00000300L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT 0x6 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK 0x0000003FL +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK 0x00000040L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x000003F0L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x00001F80L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x00000C00L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x000000C0L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x00000700L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x00001800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0000007EL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x00000180L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x00000600L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x00007F80L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x000000FEL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0000000CL +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK 0x000000C0L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK 0x00001800L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK 0x00006000L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK 0x000000F0L +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x00007FE0L +#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x00001F80L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK 0x00000F00L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK 0x00003000L +#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK 0x000001C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x000001E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK 0x00003C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x00007800L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK +#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x0000000CL +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x000001FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x000001C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x000001C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x00000E00L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x00007000L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x00003FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x000007FEL +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x00003C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x00000700L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x00000F80L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x000000F0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x00000F00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x00000E00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x00007C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x000001C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x00000E00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x00007000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x00001C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x00000FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK 0x00007C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK 0x0000FC00L +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x00003C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x0000003EL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x000007C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x00000018L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x000003C0L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x00001C00L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x00000180L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x00001800L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x00000038L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x00007FFFL +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x00000C00L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK 0x000003FFL +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK 0x00001800L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK 0x00007FFEL +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK 0x00000078L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0x00001F80L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK 0x000001FFL +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK 0x0000FFFFL +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x00000006L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x00001FF8L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x000003E0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x00006000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK 0x00000780L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x000000F8L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x00000006L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x00000FF0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x000000F0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x00001FFFL +#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK 0x0000003FL +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT 0x9 +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK 0x00000030L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK 0x00000600L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK 0x0000F000L +//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT 0xb +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK 0x000003F0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK 0x00000FC0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT 0xe +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK 0x00001FE0L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK 0x00004000L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK 0x00000007L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK 0x00000070L +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_ATB1 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_ATB2 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK 0x0000001CL +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK 0x000000C0L +#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_MISC1 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK 0x0000000CL +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_MISC2 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_MISC3 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2_MASK 0x000000FCL +#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_CLK_1 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_CLK_2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK 0x0000001FL +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5_MASK 0x000000E0L +#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x0000000FL +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x000000F0L +#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK 0x00000030L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_SQ +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK 0x00000003L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3_MASK 0x00000018L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_CAL1 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_CAL2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK 0x0000007CL +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK 0x00000018L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT 0x5 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT 0x6 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK 0x00000010L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK 0x00000020L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK 0x00000040L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT 0x1 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT 0x2 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT 0x3 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT 0x4 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK 0x00000001L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK 0x00000002L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK 0x00000004L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK 0x00000008L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK 0x00000070L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT 0x7 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK 0x0000007FL +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK 0x00000080L +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1 +#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT 0x0 +#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0_MASK 0x000000FFL +#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0 +#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0 +#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT 0x0 +#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x00000F00L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x00000380L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x00000030L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK 0x0000C000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x00000006L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x00000060L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x00000078L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x00000780L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x000007F8L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK 0x00000038L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK 0x0000FFC0L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK 0x000000FFL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK 0x00001F00L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x00000FFFL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK 0x00007000L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK 0x0000000FL +#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK 0x0000000CL +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK 0x00000040L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK 0x0000FF80L +//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x0000001EL +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK 0x000007E0L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK 0x0000F800L +//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK 0x0000FFF8L +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x000001FFL +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0x0000FE00L +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x0000001FL +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0x0000FFE0L +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0x0000FFFEL +//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK 0x00000007L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK 0x0000FFF0L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK 0x000000C0L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK 0x00000018L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK 0x000000E0L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x000000F0L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT 0x9 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT 0xa +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT 0xb +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT 0xc +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK 0x00000003L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x00000070L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK 0x00000100L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK 0x00000200L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK 0x00000400L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK 0x00000800L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK 0x00001000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK 0x0000E000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x00001FFFL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x00002000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x00004000L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x00008000L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0x7 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT 0x8 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x0000007FL +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x00000080L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK 0x0000FF00L +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK 0x0000FFFCL +//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT 0x0 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT 0x1 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT 0x2 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT 0x3 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT 0x4 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT 0x5 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT 0x6 +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK 0x00000001L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK 0x00000002L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK 0x00000004L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK 0x00000008L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK 0x00000010L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK 0x00000020L +#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK 0x0000FFC0L + + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h new file mode 100644 index 000000000000..dfacc6b5d89d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h @@ -0,0 +1,355 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_13_0_1_OFFSET_HEADER +#define _mp_13_0_1_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define regMP0_SMN_C2PMSG_32 0x0060 +#define regMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_33 0x0061 +#define regMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_34 0x0062 +#define regMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_35 0x0063 +#define regMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_36 0x0064 +#define regMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_37 0x0065 +#define regMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_38 0x0066 +#define regMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_39 0x0067 +#define regMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_40 0x0068 +#define regMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_41 0x0069 +#define regMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_42 0x006a +#define regMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_43 0x006b +#define regMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_44 0x006c +#define regMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_45 0x006d +#define regMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_46 0x006e +#define regMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_47 0x006f +#define regMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_48 0x0070 +#define regMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_49 0x0071 +#define regMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_50 0x0072 +#define regMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_51 0x0073 +#define regMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_52 0x0074 +#define regMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_53 0x0075 +#define regMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_54 0x0076 +#define regMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_55 0x0077 +#define regMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_56 0x0078 +#define regMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_57 0x0079 +#define regMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_58 0x007a +#define regMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_59 0x007b +#define regMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_60 0x007c +#define regMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_61 0x007d +#define regMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_62 0x007e +#define regMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_63 0x007f +#define regMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_64 0x0080 +#define regMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_65 0x0081 +#define regMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_66 0x0082 +#define regMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_67 0x0083 +#define regMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_68 0x0084 +#define regMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_69 0x0085 +#define regMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_70 0x0086 +#define regMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_71 0x0087 +#define regMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_72 0x0088 +#define regMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_73 0x0089 +#define regMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_74 0x008a +#define regMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_75 0x008b +#define regMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_76 0x008c +#define regMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_77 0x008d +#define regMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_78 0x008e +#define regMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_79 0x008f +#define regMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_80 0x0090 +#define regMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_81 0x0091 +#define regMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_82 0x0092 +#define regMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_83 0x0093 +#define regMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_84 0x0094 +#define regMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_85 0x0095 +#define regMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_86 0x0096 +#define regMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_87 0x0097 +#define regMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_88 0x0098 +#define regMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_89 0x0099 +#define regMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_90 0x009a +#define regMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_91 0x009b +#define regMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_92 0x009c +#define regMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_93 0x009d +#define regMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_94 0x009e +#define regMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_95 0x009f +#define regMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_96 0x00a0 +#define regMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_97 0x00a1 +#define regMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_98 0x00a2 +#define regMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_99 0x00a3 +#define regMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_100 0x00a4 +#define regMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_101 0x00a5 +#define regMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_102 0x00a6 +#define regMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP0_SMN_C2PMSG_103 0x00a7 +#define regMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP0_SMN_IH_CREDIT 0x00c1 +#define regMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT 0x00c2 +#define regMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_32 0x0260 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_33 0x0261 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_34 0x0262 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_35 0x0263 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_36 0x0264 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_37 0x0265 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_38 0x0266 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_39 0x0267 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_40 0x0268 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_41 0x0269 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_42 0x026a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_43 0x026b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_44 0x026c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_45 0x026d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_46 0x026e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_47 0x026f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_48 0x0270 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_49 0x0271 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_50 0x0272 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_51 0x0273 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_52 0x0274 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_53 0x0275 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_54 0x0276 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_55 0x0277 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_56 0x0278 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_57 0x0279 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_58 0x027a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_59 0x027b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_60 0x027c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_61 0x027d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_62 0x027e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_63 0x027f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_64 0x0280 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_65 0x0281 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_66 0x0282 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_67 0x0283 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_68 0x0284 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_69 0x0285 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_70 0x0286 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_71 0x0287 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_72 0x0288 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_73 0x0289 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_74 0x028a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_75 0x028b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_76 0x028c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_77 0x028d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_78 0x028e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_79 0x028f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_80 0x0290 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_81 0x0291 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_82 0x0292 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_83 0x0293 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_84 0x0294 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_85 0x0295 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_86 0x0296 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_87 0x0297 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_88 0x0298 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_89 0x0299 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_90 0x029a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_91 0x029b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_92 0x029c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_93 0x029d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_94 0x029e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_95 0x029f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_96 0x02a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_97 0x02a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_98 0x02a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_99 0x02a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_100 0x02a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_101 0x02a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_102 0x02a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_103 0x02a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP1_SMN_IH_CREDIT 0x02c1 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT 0x02c2 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define regMP1_SMN_FPS_CNT 0x02c4 +#define regMP1_SMN_FPS_CNT_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH0 0x0340 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH1 0x0341 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH2 0x0342 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH3 0x0343 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH4 0x0344 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH5 0x0345 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH6 0x0346 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH7 0x0347 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h new file mode 100644 index 000000000000..2d5e8b58e693 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h @@ -0,0 +1,531 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_13_0_1_SH_MASK_HEADER +#define _mp_13_0_1_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index 47eb84598b96..6a505d1b82a5 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -5178,11 +5178,11 @@ typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 { ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 -// 14:7 � PSI0_VID -// 6 � PSI0_EN -// 5 � PSI1 -// 4:2 � load line slope trim. -// 1:0 � offset trim, +// 14:7 - PSI0_VID +// 6 - PSI0_EN +// 5 - PSI1 +// 4:2 - load line slope trim. +// 1:0 - offset trim, USHORT usLoadLine_PSI; // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index f2564ba21c0b..3811e58dd857 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -197,6 +197,9 @@ enum atom_dp_vs_preemph_def{ DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, }; +#define BIOS_ATOM_PREFIX "ATOMBIOS" +#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" +#define BIOS_STRING_LENGTH 43 /* enum atom_string_def{ @@ -209,12 +212,14 @@ atom_bios_string = "ATOM" #pragma pack(1) /* BIOS data must use byte aligment*/ enum atombios_image_offset{ -OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, -OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, -OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, -MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ -OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, -OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, + OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, + OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, + OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, + MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, + OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, + OFFSET_TO_VBIOS_PART_NUMBER = 0x80, + OFFSET_TO_VBIOS_DATE = 0x50, }; /**************************************************************************** @@ -501,6 +506,7 @@ enum atombios_firmware_capability ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, + ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, }; enum atom_cooling_solution_id{ @@ -877,7 +883,8 @@ struct atom_bracket_layout_record }; enum atom_display_device_tag_def{ - ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display + ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display + ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, @@ -1407,6 +1414,59 @@ struct atom_integrated_system_info_v2_1 }; +struct atom_n6_display_phy_tuning_set { + uint8_t display_signal_type; + uint8_t phy_sel; + uint8_t preset_level; + uint8_t reserved1; + uint32_t reserved2; + uint32_t speed_upto; + uint8_t tx_vboost_level; + uint8_t tx_vreg_v2i; + uint8_t tx_vregdrv_byp; + uint8_t tx_term_cntl; + uint8_t tx_peak_level; + uint8_t tx_slew_en; + uint8_t tx_eq_pre; + uint8_t tx_eq_main; + uint8_t tx_eq_post; + uint8_t tx_en_inv_pre; + uint8_t tx_en_inv_post; + uint8_t reserved3; + uint32_t reserved4; + uint32_t reserved5; + uint32_t reserved6; +}; + +struct atom_display_phy_tuning_info { + struct atom_common_table_header table_header; + struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; +}; + +struct atom_integrated_system_info_v2_2 +{ + struct atom_common_table_header table_header; + uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def + uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def + uint32_t system_config; + uint32_t cpucapinfo; + uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% + uint16_t gpuclk_ss_type; + uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def + uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. + uint8_t umachannelnumber; // number of memory channels + uint8_t htc_hyst_limit; + uint8_t htc_tmp_limit; + uint8_t reserved1; + uint8_t reserved2; + struct edp_info_table edp1_info; + struct edp_info_table edp2_info; + uint32_t reserved3[8]; + struct atom_external_display_connection_info extdispconninfo; + + uint32_t reserved4[189]; +}; + // system_config enum atom_system_vbiosmisc_def{ INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, diff --git a/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h b/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h new file mode 100644 index 000000000000..26044cb285d2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h @@ -0,0 +1,1274 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _beige_goby_ip_offset_HEADER +#define _beige_goby_ip_offset_HEADER + + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 6 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } }, + { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, + { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 +#define ATHUB_BASE__INST0_SEG5 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 +#define ATHUB_BASE__INST1_SEG5 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 +#define ATHUB_BASE__INST2_SEG5 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 +#define ATHUB_BASE__INST3_SEG5 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 +#define ATHUB_BASE__INST4_SEG5 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 +#define ATHUB_BASE__INST5_SEG5 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 +#define ATHUB_BASE__INST6_SEG5 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 +#define CLK_BASE__INST0_SEG5 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 +#define CLK_BASE__INST1_SEG5 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 +#define CLK_BASE__INST2_SEG5 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 +#define CLK_BASE__INST3_SEG5 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 +#define CLK_BASE__INST4_SEG5 0 + +#define CLK_BASE__INST5_SEG0 0x0001B200 +#define CLK_BASE__INST5_SEG1 0x0242DC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 +#define CLK_BASE__INST5_SEG5 0 + +#define CLK_BASE__INST6_SEG0 0x00017E00 +#define CLK_BASE__INST6_SEG1 0x0240BC00 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 +#define CLK_BASE__INST6_SEG5 0 + +#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 +#define DBGU_IO0_BASE__INST0_SEG2 0 +#define DBGU_IO0_BASE__INST0_SEG3 0 +#define DBGU_IO0_BASE__INST0_SEG4 0 +#define DBGU_IO0_BASE__INST0_SEG5 0 + +#define DBGU_IO0_BASE__INST1_SEG0 0x00000260 +#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00 +#define DBGU_IO0_BASE__INST1_SEG2 0 +#define DBGU_IO0_BASE__INST1_SEG3 0 +#define DBGU_IO0_BASE__INST1_SEG4 0 +#define DBGU_IO0_BASE__INST1_SEG5 0 + +#define DBGU_IO0_BASE__INST2_SEG0 0 +#define DBGU_IO0_BASE__INST2_SEG1 0 +#define DBGU_IO0_BASE__INST2_SEG2 0 +#define DBGU_IO0_BASE__INST2_SEG3 0 +#define DBGU_IO0_BASE__INST2_SEG4 0 +#define DBGU_IO0_BASE__INST2_SEG5 0 + +#define DBGU_IO0_BASE__INST3_SEG0 0 +#define DBGU_IO0_BASE__INST3_SEG1 0 +#define DBGU_IO0_BASE__INST3_SEG2 0 +#define DBGU_IO0_BASE__INST3_SEG3 0 +#define DBGU_IO0_BASE__INST3_SEG4 0 +#define DBGU_IO0_BASE__INST3_SEG5 0 + +#define DBGU_IO0_BASE__INST4_SEG0 0 +#define DBGU_IO0_BASE__INST4_SEG1 0 +#define DBGU_IO0_BASE__INST4_SEG2 0 +#define DBGU_IO0_BASE__INST4_SEG3 0 +#define DBGU_IO0_BASE__INST4_SEG4 0 +#define DBGU_IO0_BASE__INST4_SEG5 0 + +#define DBGU_IO0_BASE__INST5_SEG0 0 +#define DBGU_IO0_BASE__INST5_SEG1 0 +#define DBGU_IO0_BASE__INST5_SEG2 0 +#define DBGU_IO0_BASE__INST5_SEG3 0 +#define DBGU_IO0_BASE__INST5_SEG4 0 +#define DBGU_IO0_BASE__INST5_SEG5 0 + +#define DBGU_IO0_BASE__INST6_SEG0 0 +#define DBGU_IO0_BASE__INST6_SEG1 0 +#define DBGU_IO0_BASE__INST6_SEG2 0 +#define DBGU_IO0_BASE__INST6_SEG3 0 +#define DBGU_IO0_BASE__INST6_SEG4 0 +#define DBGU_IO0_BASE__INST6_SEG5 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 +#define DF_BASE__INST0_SEG5 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 +#define DF_BASE__INST1_SEG5 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 +#define DF_BASE__INST2_SEG5 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 +#define DF_BASE__INST3_SEG5 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 +#define DF_BASE__INST4_SEG5 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 +#define DF_BASE__INST5_SEG5 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 +#define DF_BASE__INST6_SEG5 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 +#define DIO_BASE__INST0_SEG5 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 +#define DIO_BASE__INST1_SEG5 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 +#define DIO_BASE__INST2_SEG5 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 +#define DIO_BASE__INST3_SEG5 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 +#define DIO_BASE__INST4_SEG5 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 +#define DIO_BASE__INST5_SEG5 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 +#define DIO_BASE__INST6_SEG5 0 + +#define DCN_BASE__INST0_SEG0 0x00000012 +#define DCN_BASE__INST0_SEG1 0x000000C0 +#define DCN_BASE__INST0_SEG2 0x000034C0 +#define DCN_BASE__INST0_SEG3 0x00009000 +#define DCN_BASE__INST0_SEG4 0x02403C00 +#define DCN_BASE__INST0_SEG5 0 + +#define DCN_BASE__INST1_SEG0 0 +#define DCN_BASE__INST1_SEG1 0 +#define DCN_BASE__INST1_SEG2 0 +#define DCN_BASE__INST1_SEG3 0 +#define DCN_BASE__INST1_SEG4 0 +#define DCN_BASE__INST1_SEG5 0 + +#define DCN_BASE__INST2_SEG0 0 +#define DCN_BASE__INST2_SEG1 0 +#define DCN_BASE__INST2_SEG2 0 +#define DCN_BASE__INST2_SEG3 0 +#define DCN_BASE__INST2_SEG4 0 +#define DCN_BASE__INST2_SEG5 0 + +#define DCN_BASE__INST3_SEG0 0 +#define DCN_BASE__INST3_SEG1 0 +#define DCN_BASE__INST3_SEG2 0 +#define DCN_BASE__INST3_SEG3 0 +#define DCN_BASE__INST3_SEG4 0 +#define DCN_BASE__INST3_SEG5 0 + +#define DCN_BASE__INST4_SEG0 0 +#define DCN_BASE__INST4_SEG1 0 +#define DCN_BASE__INST4_SEG2 0 +#define DCN_BASE__INST4_SEG3 0 +#define DCN_BASE__INST4_SEG4 0 +#define DCN_BASE__INST4_SEG5 0 + +#define DCN_BASE__INST5_SEG0 0 +#define DCN_BASE__INST5_SEG1 0 +#define DCN_BASE__INST5_SEG2 0 +#define DCN_BASE__INST5_SEG3 0 +#define DCN_BASE__INST5_SEG4 0 +#define DCN_BASE__INST5_SEG5 0 + +#define DCN_BASE__INST6_SEG0 0 +#define DCN_BASE__INST6_SEG1 0 +#define DCN_BASE__INST6_SEG2 0 +#define DCN_BASE__INST6_SEG3 0 +#define DCN_BASE__INST6_SEG4 0 +#define DCN_BASE__INST6_SEG5 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 +#define DPCS_BASE__INST0_SEG5 0 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 +#define DPCS_BASE__INST1_SEG5 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 +#define DPCS_BASE__INST2_SEG5 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 +#define DPCS_BASE__INST3_SEG5 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 +#define DPCS_BASE__INST4_SEG5 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 +#define DPCS_BASE__INST5_SEG5 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 +#define DPCS_BASE__INST6_SEG5 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 +#define FUSE_BASE__INST0_SEG5 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 +#define FUSE_BASE__INST1_SEG5 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 +#define FUSE_BASE__INST2_SEG5 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 +#define FUSE_BASE__INST3_SEG5 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 +#define FUSE_BASE__INST4_SEG5 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 +#define FUSE_BASE__INST5_SEG5 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 +#define FUSE_BASE__INST6_SEG5 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x0001C000 +#define GC_BASE__INST0_SEG3 0x02402C00 +#define GC_BASE__INST0_SEG4 0 +#define GC_BASE__INST0_SEG5 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 +#define GC_BASE__INST1_SEG5 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 +#define GC_BASE__INST2_SEG5 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 +#define GC_BASE__INST3_SEG5 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 +#define GC_BASE__INST4_SEG5 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 +#define GC_BASE__INST5_SEG5 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 +#define GC_BASE__INST6_SEG5 0 + +#define HDA_BASE__INST0_SEG0 0x004C0000 +#define HDA_BASE__INST0_SEG1 0x02404800 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 +#define HDA_BASE__INST0_SEG5 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 +#define HDA_BASE__INST1_SEG5 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 +#define HDA_BASE__INST2_SEG5 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 +#define HDA_BASE__INST3_SEG5 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 +#define HDA_BASE__INST4_SEG5 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 +#define HDA_BASE__INST5_SEG5 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 +#define HDA_BASE__INST6_SEG5 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 +#define HDP_BASE__INST0_SEG5 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 +#define HDP_BASE__INST1_SEG5 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 +#define HDP_BASE__INST2_SEG5 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 +#define HDP_BASE__INST3_SEG5 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 +#define HDP_BASE__INST4_SEG5 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 +#define HDP_BASE__INST5_SEG5 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 +#define HDP_BASE__INST6_SEG5 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 +#define MMHUB_BASE__INST0_SEG5 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 +#define MMHUB_BASE__INST1_SEG5 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 +#define MMHUB_BASE__INST2_SEG5 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 +#define MMHUB_BASE__INST3_SEG5 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 +#define MMHUB_BASE__INST4_SEG5 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 +#define MMHUB_BASE__INST5_SEG5 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 +#define MMHUB_BASE__INST6_SEG5 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 +#define MP0_BASE__INST0_SEG5 0 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 +#define MP0_BASE__INST1_SEG5 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 +#define MP0_BASE__INST2_SEG5 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 +#define MP0_BASE__INST3_SEG5 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 +#define MP0_BASE__INST4_SEG5 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 +#define MP0_BASE__INST5_SEG5 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 +#define MP0_BASE__INST6_SEG5 0 + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00DC0000 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E40000 +#define MP1_BASE__INST0_SEG4 0x0243FC00 +#define MP1_BASE__INST0_SEG5 0 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 +#define MP1_BASE__INST1_SEG5 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 +#define MP1_BASE__INST2_SEG5 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 +#define MP1_BASE__INST3_SEG5 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 +#define MP1_BASE__INST4_SEG5 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 +#define MP1_BASE__INST5_SEG5 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 +#define MP1_BASE__INST6_SEG5 0 + +#define NBIO_BASE__INST0_SEG0 0x00000000 +#define NBIO_BASE__INST0_SEG1 0x00000014 +#define NBIO_BASE__INST0_SEG2 0x00000D20 +#define NBIO_BASE__INST0_SEG3 0x00010400 +#define NBIO_BASE__INST0_SEG4 0x0241B000 +#define NBIO_BASE__INST0_SEG5 0x04040000 + +#define NBIO_BASE__INST1_SEG0 0 +#define NBIO_BASE__INST1_SEG1 0 +#define NBIO_BASE__INST1_SEG2 0 +#define NBIO_BASE__INST1_SEG3 0 +#define NBIO_BASE__INST1_SEG4 0 +#define NBIO_BASE__INST1_SEG5 0 + +#define NBIO_BASE__INST2_SEG0 0 +#define NBIO_BASE__INST2_SEG1 0 +#define NBIO_BASE__INST2_SEG2 0 +#define NBIO_BASE__INST2_SEG3 0 +#define NBIO_BASE__INST2_SEG4 0 +#define NBIO_BASE__INST2_SEG5 0 + +#define NBIO_BASE__INST3_SEG0 0 +#define NBIO_BASE__INST3_SEG1 0 +#define NBIO_BASE__INST3_SEG2 0 +#define NBIO_BASE__INST3_SEG3 0 +#define NBIO_BASE__INST3_SEG4 0 +#define NBIO_BASE__INST3_SEG5 0 + +#define NBIO_BASE__INST4_SEG0 0 +#define NBIO_BASE__INST4_SEG1 0 +#define NBIO_BASE__INST4_SEG2 0 +#define NBIO_BASE__INST4_SEG3 0 +#define NBIO_BASE__INST4_SEG4 0 +#define NBIO_BASE__INST4_SEG5 0 + +#define NBIO_BASE__INST5_SEG0 0 +#define NBIO_BASE__INST5_SEG1 0 +#define NBIO_BASE__INST5_SEG2 0 +#define NBIO_BASE__INST5_SEG3 0 +#define NBIO_BASE__INST5_SEG4 0 +#define NBIO_BASE__INST5_SEG5 0 + +#define NBIO_BASE__INST6_SEG0 0 +#define NBIO_BASE__INST6_SEG1 0 +#define NBIO_BASE__INST6_SEG2 0 +#define NBIO_BASE__INST6_SEG3 0 +#define NBIO_BASE__INST6_SEG4 0 +#define NBIO_BASE__INST6_SEG5 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 +#define OSSSYS_BASE__INST0_SEG5 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 +#define OSSSYS_BASE__INST1_SEG5 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 +#define OSSSYS_BASE__INST2_SEG5 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 +#define OSSSYS_BASE__INST3_SEG5 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 +#define OSSSYS_BASE__INST4_SEG5 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 +#define OSSSYS_BASE__INST5_SEG5 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 +#define OSSSYS_BASE__INST6_SEG5 0 + +#define PCIE0_BASE__INST0_SEG0 0x00000000 +#define PCIE0_BASE__INST0_SEG1 0x00000014 +#define PCIE0_BASE__INST0_SEG2 0x00000D20 +#define PCIE0_BASE__INST0_SEG3 0x00010400 +#define PCIE0_BASE__INST0_SEG4 0x0241B000 +#define PCIE0_BASE__INST0_SEG5 0x04040000 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 +#define PCIE0_BASE__INST1_SEG5 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 +#define PCIE0_BASE__INST2_SEG5 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 +#define PCIE0_BASE__INST3_SEG5 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 +#define PCIE0_BASE__INST4_SEG5 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 +#define PCIE0_BASE__INST5_SEG5 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 +#define PCIE0_BASE__INST6_SEG5 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x0000A000 +#define SDMA0_BASE__INST0_SEG2 0x0001C000 +#define SDMA0_BASE__INST0_SEG3 0x02402C00 +#define SDMA0_BASE__INST0_SEG4 0 +#define SDMA0_BASE__INST0_SEG5 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 +#define SDMA0_BASE__INST1_SEG5 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 +#define SDMA0_BASE__INST2_SEG5 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 +#define SDMA0_BASE__INST3_SEG5 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 +#define SDMA0_BASE__INST4_SEG5 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 +#define SDMA0_BASE__INST5_SEG5 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 +#define SDMA0_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x00440000 +#define SMUIO_BASE__INST0_SEG3 0x02401000 +#define SMUIO_BASE__INST0_SEG4 0 +#define SMUIO_BASE__INST0_SEG5 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 +#define SMUIO_BASE__INST1_SEG5 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 +#define SMUIO_BASE__INST2_SEG5 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 +#define SMUIO_BASE__INST3_SEG5 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 +#define SMUIO_BASE__INST4_SEG5 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 +#define SMUIO_BASE__INST5_SEG5 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 +#define SMUIO_BASE__INST6_SEG5 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 +#define THM_BASE__INST0_SEG5 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 +#define THM_BASE__INST1_SEG5 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 +#define THM_BASE__INST2_SEG5 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 +#define THM_BASE__INST3_SEG5 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 +#define THM_BASE__INST4_SEG5 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 +#define THM_BASE__INST5_SEG5 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 +#define THM_BASE__INST6_SEG5 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 +#define UMC_BASE__INST0_SEG5 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 +#define UMC_BASE__INST1_SEG5 0 + +#define UMC_BASE__INST2_SEG0 0 +#define UMC_BASE__INST2_SEG1 0 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 +#define UMC_BASE__INST2_SEG5 0 + +#define UMC_BASE__INST3_SEG0 0 +#define UMC_BASE__INST3_SEG1 0 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 +#define UMC_BASE__INST3_SEG5 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 +#define UMC_BASE__INST4_SEG5 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 +#define UMC_BASE__INST5_SEG5 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 +#define UMC_BASE__INST6_SEG5 0 + +#define VCN0_BASE__INST0_SEG0 0x00007800 +#define VCN0_BASE__INST0_SEG1 0x00007E00 +#define VCN0_BASE__INST0_SEG2 0x02403000 +#define VCN0_BASE__INST0_SEG3 0 +#define VCN0_BASE__INST0_SEG4 0 +#define VCN0_BASE__INST0_SEG5 0 + +#define VCN0_BASE__INST1_SEG0 0 +#define VCN0_BASE__INST1_SEG1 0 +#define VCN0_BASE__INST1_SEG2 0 +#define VCN0_BASE__INST1_SEG3 0 +#define VCN0_BASE__INST1_SEG4 0 +#define VCN0_BASE__INST1_SEG5 0 + +#define VCN0_BASE__INST2_SEG0 0 +#define VCN0_BASE__INST2_SEG1 0 +#define VCN0_BASE__INST2_SEG2 0 +#define VCN0_BASE__INST2_SEG3 0 +#define VCN0_BASE__INST2_SEG4 0 +#define VCN0_BASE__INST2_SEG5 0 + +#define VCN0_BASE__INST3_SEG0 0 +#define VCN0_BASE__INST3_SEG1 0 +#define VCN0_BASE__INST3_SEG2 0 +#define VCN0_BASE__INST3_SEG3 0 +#define VCN0_BASE__INST3_SEG4 0 +#define VCN0_BASE__INST3_SEG5 0 + +#define VCN0_BASE__INST4_SEG0 0 +#define VCN0_BASE__INST4_SEG1 0 +#define VCN0_BASE__INST4_SEG2 0 +#define VCN0_BASE__INST4_SEG3 0 +#define VCN0_BASE__INST4_SEG4 0 +#define VCN0_BASE__INST4_SEG5 0 + +#define VCN0_BASE__INST5_SEG0 0 +#define VCN0_BASE__INST5_SEG1 0 +#define VCN0_BASE__INST5_SEG2 0 +#define VCN0_BASE__INST5_SEG3 0 +#define VCN0_BASE__INST5_SEG4 0 +#define VCN0_BASE__INST5_SEG5 0 + +#define VCN0_BASE__INST6_SEG0 0 +#define VCN0_BASE__INST6_SEG1 0 +#define VCN0_BASE__INST6_SEG2 0 +#define VCN0_BASE__INST6_SEG3 0 +#define VCN0_BASE__INST6_SEG4 0 +#define VCN0_BASE__INST6_SEG5 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 353468667036..e38b191c7b7c 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -124,6 +124,8 @@ enum amd_pp_sensors { AMDGPU_PP_SENSOR_VCE_POWER, AMDGPU_PP_SENSOR_UVD_POWER, AMDGPU_PP_SENSOR_GPU_POWER, + AMDGPU_PP_SENSOR_SS_APU_SHARE, + AMDGPU_PP_SENSOR_SS_DGPU_SHARE, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, @@ -192,6 +194,48 @@ enum pp_df_cstate { DF_CSTATE_ALLOW, }; +/** + * DOC: amdgpu_pp_power + * + * APU power is managed to system-level requirements through the PPT + * (package power tracking) feature. PPT is intended to limit power to the + * requirements of the power source and could be dynamically updated to + * maximize APU performance within the system power budget. + * + * Two types of power measurement can be requested, where supported, with + * :c:type:`enum pp_power_type `. + */ + +/** + * enum pp_power_limit_level - Used to query the power limits + * + * @PP_PWR_LIMIT_MIN: Minimum Power Limit + * @PP_PWR_LIMIT_CURRENT: Current Power Limit + * @PP_PWR_LIMIT_DEFAULT: Default Power Limit + * @PP_PWR_LIMIT_MAX: Maximum Power Limit + */ +enum pp_power_limit_level +{ + PP_PWR_LIMIT_MIN = -1, + PP_PWR_LIMIT_CURRENT, + PP_PWR_LIMIT_DEFAULT, + PP_PWR_LIMIT_MAX, +}; + +/** + * enum pp_power_type - Used to specify the type of the requested power + * + * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant + * moving average of APU power (default ~5000 ms). + * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, + * where supported. + */ +enum pp_power_type +{ + PP_PWR_TYPE_SUSTAINED, + PP_PWR_TYPE_FAST, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 @@ -291,8 +335,9 @@ struct amd_pm_funcs { uint32_t block_type, bool gate); int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); int (*set_power_limit)(void *handle, uint32_t n); - int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit, - bool default_limit); + int (*get_power_limit)(void *handle, uint32_t *limit, + enum pp_power_limit_level pp_limit_level, + enum pp_power_type power_type); int (*get_power_profile_mode)(void *handle, char *buf); int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); @@ -350,6 +395,7 @@ struct amd_pm_funcs { unsigned int *num_states); int (*get_dpm_clock_table)(void *handle, struct dpm_clocks *clock_table); + int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); }; struct metrics_table_header { @@ -473,6 +519,140 @@ struct gpu_metrics_v1_1 { uint16_t temperature_hbm[NUM_HBM_INSTANCES]; }; +struct gpu_metrics_v1_2 { + struct metrics_table_header common_header; + + /* Temperature */ + uint16_t temperature_edge; + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrgfx; + uint16_t temperature_vrsoc; + uint16_t temperature_vrmem; + + /* Utilization */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + uint16_t average_mm_activity; // UVD or VCN + + /* Power/Energy */ + uint16_t average_socket_power; + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_uclk_frequency; + uint16_t average_vclk0_frequency; + uint16_t average_dclk0_frequency; + uint16_t average_vclk1_frequency; + uint16_t average_dclk1_frequency; + + /* Current clocks */ + uint16_t current_gfxclk; + uint16_t current_socclk; + uint16_t current_uclk; + uint16_t current_vclk0; + uint16_t current_dclk0; + uint16_t current_vclk1; + uint16_t current_dclk1; + + /* Throttle status (ASIC dependent) */ + uint32_t throttle_status; + + /* Fans */ + uint16_t current_fan_speed; + + /* Link width/speed */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; // in 0.1 GT/s + + uint16_t padding; + + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + uint16_t temperature_hbm[NUM_HBM_INSTANCES]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; +}; + +struct gpu_metrics_v1_3 { + struct metrics_table_header common_header; + + /* Temperature */ + uint16_t temperature_edge; + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrgfx; + uint16_t temperature_vrsoc; + uint16_t temperature_vrmem; + + /* Utilization */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + uint16_t average_mm_activity; // UVD or VCN + + /* Power/Energy */ + uint16_t average_socket_power; + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_uclk_frequency; + uint16_t average_vclk0_frequency; + uint16_t average_dclk0_frequency; + uint16_t average_vclk1_frequency; + uint16_t average_dclk1_frequency; + + /* Current clocks */ + uint16_t current_gfxclk; + uint16_t current_socclk; + uint16_t current_uclk; + uint16_t current_vclk0; + uint16_t current_dclk0; + uint16_t current_vclk1; + uint16_t current_dclk1; + + /* Throttle status */ + uint32_t throttle_status; + + /* Fans */ + uint16_t current_fan_speed; + + /* Link width/speed */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; // in 0.1 GT/s + + uint16_t padding; + + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + uint16_t temperature_hbm[NUM_HBM_INSTANCES]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; + + /* Voltage (mV) */ + uint16_t voltage_soc; + uint16_t voltage_gfx; + uint16_t voltage_mem; + + uint16_t padding1; + + /* Throttle status (ASIC independent) */ + uint64_t indep_throttle_status; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. @@ -577,4 +757,57 @@ struct gpu_metrics_v2_1 { uint16_t padding[3]; }; +struct gpu_metrics_v2_2 { + struct metrics_table_header common_header; + + /* Temperature */ + uint16_t temperature_gfx; // gfx temperature on APUs + uint16_t temperature_soc; // soc temperature on APUs + uint16_t temperature_core[8]; // CPU core temperature on APUs + uint16_t temperature_l3[2]; + + /* Utilization */ + uint16_t average_gfx_activity; + uint16_t average_mm_activity; // UVD or VCN + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Power/Energy */ + uint16_t average_socket_power; // dGPU + APU power on A + A platform + uint16_t average_cpu_power; + uint16_t average_soc_power; + uint16_t average_gfx_power; + uint16_t average_core_power[8]; // CPU core power on APUs + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_uclk_frequency; + uint16_t average_fclk_frequency; + uint16_t average_vclk_frequency; + uint16_t average_dclk_frequency; + + /* Current clocks */ + uint16_t current_gfxclk; + uint16_t current_socclk; + uint16_t current_uclk; + uint16_t current_fclk; + uint16_t current_vclk; + uint16_t current_dclk; + uint16_t current_coreclk[8]; // CPU core clocks + uint16_t current_l3clk[2]; + + /* Throttle status (ASIC dependent) */ + uint32_t throttle_status; + + /* Fans */ + uint16_t fan_pwm; + + uint16_t padding[3]; + + /* Throttle status (ASIC independent) */ + uint64_t indep_throttle_status; +}; + #endif diff --git a/drivers/gpu/drm/amd/include/yellow_carp_offset.h b/drivers/gpu/drm/amd/include/yellow_carp_offset.h new file mode 100644 index 000000000000..76b9eb3f441d --- /dev/null +++ b/drivers/gpu/drm/amd/include/yellow_carp_offset.h @@ -0,0 +1,1366 @@ +#ifndef YELLOW_CARP_OFFSET_H +#define YELLOW_CARP_OFFSET_H + + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 6 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, + { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0x00000260, 0x00000280, 0x0240B400, 0x02413C00, 0x02416000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x02447800, 0x00C00000, 0x03640000, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } }, + { { 0x02411C00, 0x04480000, 0, 0, 0, 0 } }, + { { 0x02412000, 0x044C0000, 0, 0, 0, 0 } }, + { { 0x02412400, 0x04500000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } }, + { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0x02425C00, 0, 0 } }, + { { 0x00094000, 0x000D4000, 0x02426000, 0x02426400, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + + +#define ACP_BASE__INST0_SEG0 0x02403800 +#define ACP_BASE__INST0_SEG1 0x00480000 +#define ACP_BASE__INST0_SEG2 0 +#define ACP_BASE__INST0_SEG3 0 +#define ACP_BASE__INST0_SEG4 0 +#define ACP_BASE__INST0_SEG5 0 + +#define ACP_BASE__INST1_SEG0 0 +#define ACP_BASE__INST1_SEG1 0 +#define ACP_BASE__INST1_SEG2 0 +#define ACP_BASE__INST1_SEG3 0 +#define ACP_BASE__INST1_SEG4 0 +#define ACP_BASE__INST1_SEG5 0 + +#define ACP_BASE__INST2_SEG0 0 +#define ACP_BASE__INST2_SEG1 0 +#define ACP_BASE__INST2_SEG2 0 +#define ACP_BASE__INST2_SEG3 0 +#define ACP_BASE__INST2_SEG4 0 +#define ACP_BASE__INST2_SEG5 0 + +#define ACP_BASE__INST3_SEG0 0 +#define ACP_BASE__INST3_SEG1 0 +#define ACP_BASE__INST3_SEG2 0 +#define ACP_BASE__INST3_SEG3 0 +#define ACP_BASE__INST3_SEG4 0 +#define ACP_BASE__INST3_SEG5 0 + +#define ACP_BASE__INST4_SEG0 0 +#define ACP_BASE__INST4_SEG1 0 +#define ACP_BASE__INST4_SEG2 0 +#define ACP_BASE__INST4_SEG3 0 +#define ACP_BASE__INST4_SEG4 0 +#define ACP_BASE__INST4_SEG5 0 + +#define ACP_BASE__INST5_SEG0 0 +#define ACP_BASE__INST5_SEG1 0 +#define ACP_BASE__INST5_SEG2 0 +#define ACP_BASE__INST5_SEG3 0 +#define ACP_BASE__INST5_SEG4 0 +#define ACP_BASE__INST5_SEG5 0 + +#define ACP_BASE__INST6_SEG0 0 +#define ACP_BASE__INST6_SEG1 0 +#define ACP_BASE__INST6_SEG2 0 +#define ACP_BASE__INST6_SEG3 0 +#define ACP_BASE__INST6_SEG4 0 +#define ACP_BASE__INST6_SEG5 0 + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x00013300 +#define ATHUB_BASE__INST0_SEG2 0x02408C00 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 +#define ATHUB_BASE__INST0_SEG5 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 +#define ATHUB_BASE__INST1_SEG5 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 +#define ATHUB_BASE__INST2_SEG5 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 +#define ATHUB_BASE__INST3_SEG5 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 +#define ATHUB_BASE__INST4_SEG5 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 +#define ATHUB_BASE__INST5_SEG5 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 +#define ATHUB_BASE__INST6_SEG5 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 +#define CLK_BASE__INST0_SEG5 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 +#define CLK_BASE__INST1_SEG5 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 +#define CLK_BASE__INST2_SEG5 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 +#define CLK_BASE__INST3_SEG5 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 +#define CLK_BASE__INST4_SEG5 0 + +#define CLK_BASE__INST5_SEG0 0x0001B200 +#define CLK_BASE__INST5_SEG1 0x0242DC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 +#define CLK_BASE__INST5_SEG5 0 + +#define CLK_BASE__INST6_SEG0 0x0001B400 +#define CLK_BASE__INST6_SEG1 0x0242E000 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 +#define CLK_BASE__INST6_SEG5 0 + +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO_BASE__INST0_SEG1 0x00000260 +#define DBGU_IO_BASE__INST0_SEG2 0x00000280 +#define DBGU_IO_BASE__INST0_SEG3 0x0240B400 +#define DBGU_IO_BASE__INST0_SEG4 0x02413C00 +#define DBGU_IO_BASE__INST0_SEG5 0x02416000 + +#define DBGU_IO_BASE__INST1_SEG0 0 +#define DBGU_IO_BASE__INST1_SEG1 0 +#define DBGU_IO_BASE__INST1_SEG2 0 +#define DBGU_IO_BASE__INST1_SEG3 0 +#define DBGU_IO_BASE__INST1_SEG4 0 +#define DBGU_IO_BASE__INST1_SEG5 0 + +#define DBGU_IO_BASE__INST2_SEG0 0 +#define DBGU_IO_BASE__INST2_SEG1 0 +#define DBGU_IO_BASE__INST2_SEG2 0 +#define DBGU_IO_BASE__INST2_SEG3 0 +#define DBGU_IO_BASE__INST2_SEG4 0 +#define DBGU_IO_BASE__INST2_SEG5 0 + +#define DBGU_IO_BASE__INST3_SEG0 0 +#define DBGU_IO_BASE__INST3_SEG1 0 +#define DBGU_IO_BASE__INST3_SEG2 0 +#define DBGU_IO_BASE__INST3_SEG3 0 +#define DBGU_IO_BASE__INST3_SEG4 0 +#define DBGU_IO_BASE__INST3_SEG5 0 + +#define DBGU_IO_BASE__INST4_SEG0 0 +#define DBGU_IO_BASE__INST4_SEG1 0 +#define DBGU_IO_BASE__INST4_SEG2 0 +#define DBGU_IO_BASE__INST4_SEG3 0 +#define DBGU_IO_BASE__INST4_SEG4 0 +#define DBGU_IO_BASE__INST4_SEG5 0 + +#define DBGU_IO_BASE__INST5_SEG0 0 +#define DBGU_IO_BASE__INST5_SEG1 0 +#define DBGU_IO_BASE__INST5_SEG2 0 +#define DBGU_IO_BASE__INST5_SEG3 0 +#define DBGU_IO_BASE__INST5_SEG4 0 +#define DBGU_IO_BASE__INST5_SEG5 0 + +#define DBGU_IO_BASE__INST6_SEG0 0 +#define DBGU_IO_BASE__INST6_SEG1 0 +#define DBGU_IO_BASE__INST6_SEG2 0 +#define DBGU_IO_BASE__INST6_SEG3 0 +#define DBGU_IO_BASE__INST6_SEG4 0 +#define DBGU_IO_BASE__INST6_SEG5 0 + +#define DCN_BASE__INST0_SEG0 0x00000012 +#define DCN_BASE__INST0_SEG1 0x000000C0 +#define DCN_BASE__INST0_SEG2 0x000034C0 +#define DCN_BASE__INST0_SEG3 0x00009000 +#define DCN_BASE__INST0_SEG4 0x02403C00 +#define DCN_BASE__INST0_SEG5 0 + +#define DCN_BASE__INST1_SEG0 0 +#define DCN_BASE__INST1_SEG1 0 +#define DCN_BASE__INST1_SEG2 0 +#define DCN_BASE__INST1_SEG3 0 +#define DCN_BASE__INST1_SEG4 0 +#define DCN_BASE__INST1_SEG5 0 + +#define DCN_BASE__INST2_SEG0 0 +#define DCN_BASE__INST2_SEG1 0 +#define DCN_BASE__INST2_SEG2 0 +#define DCN_BASE__INST2_SEG3 0 +#define DCN_BASE__INST2_SEG4 0 +#define DCN_BASE__INST2_SEG5 0 + +#define DCN_BASE__INST3_SEG0 0 +#define DCN_BASE__INST3_SEG1 0 +#define DCN_BASE__INST3_SEG2 0 +#define DCN_BASE__INST3_SEG3 0 +#define DCN_BASE__INST3_SEG4 0 +#define DCN_BASE__INST3_SEG5 0 + +#define DCN_BASE__INST4_SEG0 0 +#define DCN_BASE__INST4_SEG1 0 +#define DCN_BASE__INST4_SEG2 0 +#define DCN_BASE__INST4_SEG3 0 +#define DCN_BASE__INST4_SEG4 0 +#define DCN_BASE__INST4_SEG5 0 + +#define DCN_BASE__INST5_SEG0 0 +#define DCN_BASE__INST5_SEG1 0 +#define DCN_BASE__INST5_SEG2 0 +#define DCN_BASE__INST5_SEG3 0 +#define DCN_BASE__INST5_SEG4 0 +#define DCN_BASE__INST5_SEG5 0 + +#define DCN_BASE__INST6_SEG0 0 +#define DCN_BASE__INST6_SEG1 0 +#define DCN_BASE__INST6_SEG2 0 +#define DCN_BASE__INST6_SEG3 0 +#define DCN_BASE__INST6_SEG4 0 +#define DCN_BASE__INST6_SEG5 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 +#define DPCS_BASE__INST0_SEG5 0 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 +#define DPCS_BASE__INST1_SEG5 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 +#define DPCS_BASE__INST2_SEG5 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 +#define DPCS_BASE__INST3_SEG5 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 +#define DPCS_BASE__INST4_SEG5 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 +#define DPCS_BASE__INST5_SEG5 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 +#define DPCS_BASE__INST6_SEG5 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0x02447800 +#define DF_BASE__INST0_SEG3 0x00C00000 +#define DF_BASE__INST0_SEG4 0x03640000 +#define DF_BASE__INST0_SEG5 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 +#define DF_BASE__INST1_SEG5 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 +#define DF_BASE__INST2_SEG5 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 +#define DF_BASE__INST3_SEG5 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 +#define DF_BASE__INST4_SEG5 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 +#define DF_BASE__INST5_SEG5 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 +#define DF_BASE__INST6_SEG5 0 + +#define FCH_BASE__INST0_SEG0 0x0240C000 +#define FCH_BASE__INST0_SEG1 0x00B40000 +#define FCH_BASE__INST0_SEG2 0x11000000 +#define FCH_BASE__INST0_SEG3 0 +#define FCH_BASE__INST0_SEG4 0 +#define FCH_BASE__INST0_SEG5 0 + +#define FCH_BASE__INST1_SEG0 0 +#define FCH_BASE__INST1_SEG1 0 +#define FCH_BASE__INST1_SEG2 0 +#define FCH_BASE__INST1_SEG3 0 +#define FCH_BASE__INST1_SEG4 0 +#define FCH_BASE__INST1_SEG5 0 + +#define FCH_BASE__INST2_SEG0 0 +#define FCH_BASE__INST2_SEG1 0 +#define FCH_BASE__INST2_SEG2 0 +#define FCH_BASE__INST2_SEG3 0 +#define FCH_BASE__INST2_SEG4 0 +#define FCH_BASE__INST2_SEG5 0 + +#define FCH_BASE__INST3_SEG0 0 +#define FCH_BASE__INST3_SEG1 0 +#define FCH_BASE__INST3_SEG2 0 +#define FCH_BASE__INST3_SEG3 0 +#define FCH_BASE__INST3_SEG4 0 +#define FCH_BASE__INST3_SEG5 0 + +#define FCH_BASE__INST4_SEG0 0 +#define FCH_BASE__INST4_SEG1 0 +#define FCH_BASE__INST4_SEG2 0 +#define FCH_BASE__INST4_SEG3 0 +#define FCH_BASE__INST4_SEG4 0 +#define FCH_BASE__INST4_SEG5 0 + +#define FCH_BASE__INST5_SEG0 0 +#define FCH_BASE__INST5_SEG1 0 +#define FCH_BASE__INST5_SEG2 0 +#define FCH_BASE__INST5_SEG3 0 +#define FCH_BASE__INST5_SEG4 0 +#define FCH_BASE__INST5_SEG5 0 + +#define FCH_BASE__INST6_SEG0 0 +#define FCH_BASE__INST6_SEG1 0 +#define FCH_BASE__INST6_SEG2 0 +#define FCH_BASE__INST6_SEG3 0 +#define FCH_BASE__INST6_SEG4 0 +#define FCH_BASE__INST6_SEG5 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 +#define FUSE_BASE__INST0_SEG5 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 +#define FUSE_BASE__INST1_SEG5 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 +#define FUSE_BASE__INST2_SEG5 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 +#define FUSE_BASE__INST3_SEG5 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 +#define FUSE_BASE__INST4_SEG5 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 +#define FUSE_BASE__INST5_SEG5 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 +#define FUSE_BASE__INST6_SEG5 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 +#define GC_BASE__INST0_SEG5 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 +#define GC_BASE__INST1_SEG5 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 +#define GC_BASE__INST2_SEG5 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 +#define GC_BASE__INST3_SEG5 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 +#define GC_BASE__INST4_SEG5 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 +#define GC_BASE__INST5_SEG5 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 +#define GC_BASE__INST6_SEG5 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 +#define HDP_BASE__INST0_SEG5 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 +#define HDP_BASE__INST1_SEG5 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 +#define HDP_BASE__INST2_SEG5 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 +#define HDP_BASE__INST3_SEG5 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 +#define HDP_BASE__INST4_SEG5 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 +#define HDP_BASE__INST5_SEG5 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 +#define HDP_BASE__INST6_SEG5 0 + +#define IOHC0_BASE__INST0_SEG0 0x00010000 +#define IOHC0_BASE__INST0_SEG1 0x02406000 +#define IOHC0_BASE__INST0_SEG2 0x04EC0000 +#define IOHC0_BASE__INST0_SEG3 0 +#define IOHC0_BASE__INST0_SEG4 0 +#define IOHC0_BASE__INST0_SEG5 0 + +#define IOHC0_BASE__INST1_SEG0 0 +#define IOHC0_BASE__INST1_SEG1 0 +#define IOHC0_BASE__INST1_SEG2 0 +#define IOHC0_BASE__INST1_SEG3 0 +#define IOHC0_BASE__INST1_SEG4 0 +#define IOHC0_BASE__INST1_SEG5 0 + +#define IOHC0_BASE__INST2_SEG0 0 +#define IOHC0_BASE__INST2_SEG1 0 +#define IOHC0_BASE__INST2_SEG2 0 +#define IOHC0_BASE__INST2_SEG3 0 +#define IOHC0_BASE__INST2_SEG4 0 +#define IOHC0_BASE__INST2_SEG5 0 + +#define IOHC0_BASE__INST3_SEG0 0 +#define IOHC0_BASE__INST3_SEG1 0 +#define IOHC0_BASE__INST3_SEG2 0 +#define IOHC0_BASE__INST3_SEG3 0 +#define IOHC0_BASE__INST3_SEG4 0 +#define IOHC0_BASE__INST3_SEG5 0 + +#define IOHC0_BASE__INST4_SEG0 0 +#define IOHC0_BASE__INST4_SEG1 0 +#define IOHC0_BASE__INST4_SEG2 0 +#define IOHC0_BASE__INST4_SEG3 0 +#define IOHC0_BASE__INST4_SEG4 0 +#define IOHC0_BASE__INST4_SEG5 0 + +#define IOHC0_BASE__INST5_SEG0 0 +#define IOHC0_BASE__INST5_SEG1 0 +#define IOHC0_BASE__INST5_SEG2 0 +#define IOHC0_BASE__INST5_SEG3 0 +#define IOHC0_BASE__INST5_SEG4 0 +#define IOHC0_BASE__INST5_SEG5 0 + +#define IOHC0_BASE__INST6_SEG0 0 +#define IOHC0_BASE__INST6_SEG1 0 +#define IOHC0_BASE__INST6_SEG2 0 +#define IOHC0_BASE__INST6_SEG3 0 +#define IOHC0_BASE__INST6_SEG4 0 +#define IOHC0_BASE__INST6_SEG5 0 + +#define MMHUB_BASE__INST0_SEG0 0x00013200 +#define MMHUB_BASE__INST0_SEG1 0x0001A000 +#define MMHUB_BASE__INST0_SEG2 0x02408800 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 +#define MMHUB_BASE__INST0_SEG5 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 +#define MMHUB_BASE__INST1_SEG5 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 +#define MMHUB_BASE__INST2_SEG5 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 +#define MMHUB_BASE__INST3_SEG5 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 +#define MMHUB_BASE__INST4_SEG5 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 +#define MMHUB_BASE__INST5_SEG5 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 +#define MMHUB_BASE__INST6_SEG5 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x0243FC00 +#define MP0_BASE__INST0_SEG2 0x00DC0000 +#define MP0_BASE__INST0_SEG3 0x00E00000 +#define MP0_BASE__INST0_SEG4 0x00E40000 +#define MP0_BASE__INST0_SEG5 0 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 +#define MP0_BASE__INST1_SEG5 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 +#define MP0_BASE__INST2_SEG5 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 +#define MP0_BASE__INST3_SEG5 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 +#define MP0_BASE__INST4_SEG5 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 +#define MP0_BASE__INST5_SEG5 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 +#define MP0_BASE__INST6_SEG5 0 + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x0243FC00 +#define MP1_BASE__INST0_SEG2 0x00DC0000 +#define MP1_BASE__INST0_SEG3 0x00E00000 +#define MP1_BASE__INST0_SEG4 0x00E40000 +#define MP1_BASE__INST0_SEG5 0 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 +#define MP1_BASE__INST1_SEG5 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 +#define MP1_BASE__INST2_SEG5 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 +#define MP1_BASE__INST3_SEG5 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 +#define MP1_BASE__INST4_SEG5 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 +#define MP1_BASE__INST5_SEG5 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 +#define MP1_BASE__INST6_SEG5 0 + +#define MP2_BASE__INST0_SEG0 0x00016000 +#define MP2_BASE__INST0_SEG1 0x0243FC00 +#define MP2_BASE__INST0_SEG2 0x00DC0000 +#define MP2_BASE__INST0_SEG3 0x00E00000 +#define MP2_BASE__INST0_SEG4 0x00E40000 +#define MP2_BASE__INST0_SEG5 0 + +#define MP2_BASE__INST1_SEG0 0 +#define MP2_BASE__INST1_SEG1 0 +#define MP2_BASE__INST1_SEG2 0 +#define MP2_BASE__INST1_SEG3 0 +#define MP2_BASE__INST1_SEG4 0 +#define MP2_BASE__INST1_SEG5 0 + +#define MP2_BASE__INST2_SEG0 0 +#define MP2_BASE__INST2_SEG1 0 +#define MP2_BASE__INST2_SEG2 0 +#define MP2_BASE__INST2_SEG3 0 +#define MP2_BASE__INST2_SEG4 0 +#define MP2_BASE__INST2_SEG5 0 + +#define MP2_BASE__INST3_SEG0 0 +#define MP2_BASE__INST3_SEG1 0 +#define MP2_BASE__INST3_SEG2 0 +#define MP2_BASE__INST3_SEG3 0 +#define MP2_BASE__INST3_SEG4 0 +#define MP2_BASE__INST3_SEG5 0 + +#define MP2_BASE__INST4_SEG0 0 +#define MP2_BASE__INST4_SEG1 0 +#define MP2_BASE__INST4_SEG2 0 +#define MP2_BASE__INST4_SEG3 0 +#define MP2_BASE__INST4_SEG4 0 +#define MP2_BASE__INST4_SEG5 0 + +#define MP2_BASE__INST5_SEG0 0 +#define MP2_BASE__INST5_SEG1 0 +#define MP2_BASE__INST5_SEG2 0 +#define MP2_BASE__INST5_SEG3 0 +#define MP2_BASE__INST5_SEG4 0 +#define MP2_BASE__INST5_SEG5 0 + +#define MP2_BASE__INST6_SEG0 0 +#define MP2_BASE__INST6_SEG1 0 +#define MP2_BASE__INST6_SEG2 0 +#define MP2_BASE__INST6_SEG3 0 +#define MP2_BASE__INST6_SEG4 0 +#define MP2_BASE__INST6_SEG5 0 + +#define NBIO_BASE__INST0_SEG0 0x00000000 +#define NBIO_BASE__INST0_SEG1 0x00000014 +#define NBIO_BASE__INST0_SEG2 0x00000D20 +#define NBIO_BASE__INST0_SEG3 0x00010400 +#define NBIO_BASE__INST0_SEG4 0x0241B000 +#define NBIO_BASE__INST0_SEG5 0x04040000 + +#define NBIO_BASE__INST1_SEG0 0 +#define NBIO_BASE__INST1_SEG1 0 +#define NBIO_BASE__INST1_SEG2 0 +#define NBIO_BASE__INST1_SEG3 0 +#define NBIO_BASE__INST1_SEG4 0 +#define NBIO_BASE__INST1_SEG5 0 + +#define NBIO_BASE__INST2_SEG0 0 +#define NBIO_BASE__INST2_SEG1 0 +#define NBIO_BASE__INST2_SEG2 0 +#define NBIO_BASE__INST2_SEG3 0 +#define NBIO_BASE__INST2_SEG4 0 +#define NBIO_BASE__INST2_SEG5 0 + +#define NBIO_BASE__INST3_SEG0 0 +#define NBIO_BASE__INST3_SEG1 0 +#define NBIO_BASE__INST3_SEG2 0 +#define NBIO_BASE__INST3_SEG3 0 +#define NBIO_BASE__INST3_SEG4 0 +#define NBIO_BASE__INST3_SEG5 0 + +#define NBIO_BASE__INST4_SEG0 0 +#define NBIO_BASE__INST4_SEG1 0 +#define NBIO_BASE__INST4_SEG2 0 +#define NBIO_BASE__INST4_SEG3 0 +#define NBIO_BASE__INST4_SEG4 0 +#define NBIO_BASE__INST4_SEG5 0 + +#define NBIO_BASE__INST5_SEG0 0 +#define NBIO_BASE__INST5_SEG1 0 +#define NBIO_BASE__INST5_SEG2 0 +#define NBIO_BASE__INST5_SEG3 0 +#define NBIO_BASE__INST5_SEG4 0 +#define NBIO_BASE__INST5_SEG5 0 + +#define NBIO_BASE__INST6_SEG0 0 +#define NBIO_BASE__INST6_SEG1 0 +#define NBIO_BASE__INST6_SEG2 0 +#define NBIO_BASE__INST6_SEG3 0 +#define NBIO_BASE__INST6_SEG4 0 +#define NBIO_BASE__INST6_SEG5 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 +#define OSSSYS_BASE__INST0_SEG5 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 +#define OSSSYS_BASE__INST1_SEG5 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 +#define OSSSYS_BASE__INST2_SEG5 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 +#define OSSSYS_BASE__INST3_SEG5 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 +#define OSSSYS_BASE__INST4_SEG5 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 +#define OSSSYS_BASE__INST5_SEG5 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 +#define OSSSYS_BASE__INST6_SEG5 0 + +#define PCIE_BASE__INST0_SEG0 0x02411800 +#define PCIE_BASE__INST0_SEG1 0x04440000 +#define PCIE_BASE__INST0_SEG2 0 +#define PCIE_BASE__INST0_SEG3 0 +#define PCIE_BASE__INST0_SEG4 0 +#define PCIE_BASE__INST0_SEG5 0 + +#define PCIE_BASE__INST1_SEG0 0x02411C00 +#define PCIE_BASE__INST1_SEG1 0x04480000 +#define PCIE_BASE__INST1_SEG2 0 +#define PCIE_BASE__INST1_SEG3 0 +#define PCIE_BASE__INST1_SEG4 0 +#define PCIE_BASE__INST1_SEG5 0 + +#define PCIE_BASE__INST2_SEG0 0x02412000 +#define PCIE_BASE__INST2_SEG1 0x044C0000 +#define PCIE_BASE__INST2_SEG2 0 +#define PCIE_BASE__INST2_SEG3 0 +#define PCIE_BASE__INST2_SEG4 0 +#define PCIE_BASE__INST2_SEG5 0 + +#define PCIE_BASE__INST3_SEG0 0x02412400 +#define PCIE_BASE__INST3_SEG1 0x04500000 +#define PCIE_BASE__INST3_SEG2 0 +#define PCIE_BASE__INST3_SEG3 0 +#define PCIE_BASE__INST3_SEG4 0 +#define PCIE_BASE__INST3_SEG5 0 + +#define PCIE_BASE__INST4_SEG0 0 +#define PCIE_BASE__INST4_SEG1 0 +#define PCIE_BASE__INST4_SEG2 0 +#define PCIE_BASE__INST4_SEG3 0 +#define PCIE_BASE__INST4_SEG4 0 +#define PCIE_BASE__INST4_SEG5 0 + +#define PCIE_BASE__INST5_SEG0 0 +#define PCIE_BASE__INST5_SEG1 0 +#define PCIE_BASE__INST5_SEG2 0 +#define PCIE_BASE__INST5_SEG3 0 +#define PCIE_BASE__INST5_SEG4 0 +#define PCIE_BASE__INST5_SEG5 0 + +#define PCIE_BASE__INST6_SEG0 0 +#define PCIE_BASE__INST6_SEG1 0 +#define PCIE_BASE__INST6_SEG2 0 +#define PCIE_BASE__INST6_SEG3 0 +#define PCIE_BASE__INST6_SEG4 0 +#define PCIE_BASE__INST6_SEG5 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x0000A000 +#define SDMA0_BASE__INST0_SEG2 0x02402C00 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 +#define SDMA0_BASE__INST0_SEG5 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 +#define SDMA0_BASE__INST1_SEG5 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 +#define SDMA0_BASE__INST2_SEG5 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 +#define SDMA0_BASE__INST3_SEG5 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 +#define SDMA0_BASE__INST4_SEG5 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 +#define SDMA0_BASE__INST5_SEG5 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 +#define SDMA0_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x02401000 +#define SMUIO_BASE__INST0_SEG3 0x00440000 +#define SMUIO_BASE__INST0_SEG4 0 +#define SMUIO_BASE__INST0_SEG5 0 + +#define SMUIO_BASE__INST1_SEG0 0x0001BC00 +#define SMUIO_BASE__INST1_SEG1 0x0242D400 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 +#define SMUIO_BASE__INST1_SEG5 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 +#define SMUIO_BASE__INST2_SEG5 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 +#define SMUIO_BASE__INST3_SEG5 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 +#define SMUIO_BASE__INST4_SEG5 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 +#define SMUIO_BASE__INST5_SEG5 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 +#define SMUIO_BASE__INST6_SEG5 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 +#define THM_BASE__INST0_SEG5 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 +#define THM_BASE__INST1_SEG5 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 +#define THM_BASE__INST2_SEG5 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 +#define THM_BASE__INST3_SEG5 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 +#define THM_BASE__INST4_SEG5 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 +#define THM_BASE__INST5_SEG5 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 +#define THM_BASE__INST6_SEG5 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x00054000 +#define UMC_BASE__INST0_SEG2 0x02425800 +#define UMC_BASE__INST0_SEG3 0x02425C00 +#define UMC_BASE__INST0_SEG4 0 +#define UMC_BASE__INST0_SEG5 0 + +#define UMC_BASE__INST1_SEG0 0x00094000 +#define UMC_BASE__INST1_SEG1 0x000D4000 +#define UMC_BASE__INST1_SEG2 0x02426000 +#define UMC_BASE__INST1_SEG3 0x02426400 +#define UMC_BASE__INST1_SEG4 0 +#define UMC_BASE__INST1_SEG5 0 + +#define UMC_BASE__INST2_SEG0 0 +#define UMC_BASE__INST2_SEG1 0 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 +#define UMC_BASE__INST2_SEG5 0 + +#define UMC_BASE__INST3_SEG0 0 +#define UMC_BASE__INST3_SEG1 0 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 +#define UMC_BASE__INST3_SEG5 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 +#define UMC_BASE__INST4_SEG5 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 +#define UMC_BASE__INST5_SEG5 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 +#define UMC_BASE__INST6_SEG5 0 + +#define VCN_BASE__INST0_SEG0 0x00007800 +#define VCN_BASE__INST0_SEG1 0x00007E00 +#define VCN_BASE__INST0_SEG2 0x02403000 +#define VCN_BASE__INST0_SEG3 0 +#define VCN_BASE__INST0_SEG4 0 +#define VCN_BASE__INST0_SEG5 0 + +#define VCN_BASE__INST1_SEG0 0 +#define VCN_BASE__INST1_SEG1 0 +#define VCN_BASE__INST1_SEG2 0 +#define VCN_BASE__INST1_SEG3 0 +#define VCN_BASE__INST1_SEG4 0 +#define VCN_BASE__INST1_SEG5 0 + +#define VCN_BASE__INST2_SEG0 0 +#define VCN_BASE__INST2_SEG1 0 +#define VCN_BASE__INST2_SEG2 0 +#define VCN_BASE__INST2_SEG3 0 +#define VCN_BASE__INST2_SEG4 0 +#define VCN_BASE__INST2_SEG5 0 + +#define VCN_BASE__INST3_SEG0 0 +#define VCN_BASE__INST3_SEG1 0 +#define VCN_BASE__INST3_SEG2 0 +#define VCN_BASE__INST3_SEG3 0 +#define VCN_BASE__INST3_SEG4 0 +#define VCN_BASE__INST3_SEG5 0 + +#define VCN_BASE__INST4_SEG0 0 +#define VCN_BASE__INST4_SEG1 0 +#define VCN_BASE__INST4_SEG2 0 +#define VCN_BASE__INST4_SEG3 0 +#define VCN_BASE__INST4_SEG4 0 +#define VCN_BASE__INST4_SEG5 0 + +#define VCN_BASE__INST5_SEG0 0 +#define VCN_BASE__INST5_SEG1 0 +#define VCN_BASE__INST5_SEG2 0 +#define VCN_BASE__INST5_SEG3 0 +#define VCN_BASE__INST5_SEG4 0 +#define VCN_BASE__INST5_SEG5 0 + +#define VCN_BASE__INST6_SEG0 0 +#define VCN_BASE__INST6_SEG1 0 +#define VCN_BASE__INST6_SEG2 0 +#define VCN_BASE__INST6_SEG3 0 +#define VCN_BASE__INST6_SEG4 0 +#define VCN_BASE__INST6_SEG5 0 + +#endif diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 9a54066ec0af..a276ebad47e6 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -411,7 +411,8 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev, struct amdgpu_device *adev = drm_to_adev(ddev); const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; struct pp_states_info data; - int i, buf_len, ret; + uint32_t i; + int buf_len, ret; if (amdgpu_in_reset(adev)) return -EPERM; @@ -433,9 +434,9 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev, pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); - buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); + buf_len = sysfs_emit(buf, "states: %d\n", data.nums); for (i = 0; i < data.nums; i++) - buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i, + buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : @@ -735,6 +736,23 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * - a list of valid ranges for sclk, mclk, and voltage curve points * labeled OD_RANGE * + * < For APUs > + * + * Reading the file will display: + * + * - minimum and maximum engine clock labeled OD_SCLK + * + * - a list of valid ranges for sclk labeled OD_RANGE + * + * < For VanGogh > + * + * Reading the file will display: + * + * - minimum and maximum engine clock labeled OD_SCLK + * - minimum and maximum core clocks labeled OD_CCLK + * + * - a list of valid ranges for sclk and cclk labeled OD_RANGE + * * To manually adjust these settings: * * - First select manual using power_dpm_force_performance_level @@ -743,7 +761,10 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * string that contains "s/m index clock" to the file. The index * should be 0 if to set minimum clock. And 1 if to set maximum * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. - * "m 1 800" will update maximum mclk to be 800Mhz. + * "m 1 800" will update maximum mclk to be 800Mhz. For core + * clocks on VanGogh, the string contains "p core index clock". + * E.g., "p 2 0 800" would set the minimum core clock on core + * 2 to 800Mhz. * * For sclk voltage curve, enter the new values by writing a * string that contains "vc point clock voltage" to the file. The @@ -903,7 +924,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size); size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size); } else { - size = snprintf(buf, PAGE_SIZE, "\n"); + size = sysfs_emit(buf, "\n"); } pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -989,7 +1010,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev, if (adev->powerplay.pp_funcs->get_ppfeature_status) size = amdgpu_dpm_get_ppfeature_status(adev, buf); else - size = snprintf(buf, PAGE_SIZE, "\n"); + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -1050,7 +1071,7 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, if (adev->powerplay.pp_funcs->print_clock_levels) size = amdgpu_dpm_print_clock_levels(adev, type, buf); else - size = snprintf(buf, PAGE_SIZE, "\n"); + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -1449,7 +1470,7 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, if (adev->powerplay.pp_funcs->get_power_profile_mode) size = amdgpu_dpm_get_power_profile_mode(adev, buf); else - size = snprintf(buf, PAGE_SIZE, "\n"); + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); @@ -1797,6 +1818,190 @@ out: return size; } +/** + * DOC: smartshift_apu_power + * + * The amdgpu driver provides a sysfs API for reporting APU power + * share if it supports smartshift. The value is expressed as + * the proportion of stapm limit where stapm limit is the total APU + * power limit. The result is in percentage. If APU power is 130% of + * STAPM, then APU is using 30% of the dGPU's headroom. + */ + +static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + uint32_t ss_power, size; + int r = 0; + + if (amdgpu_in_reset(adev)) + return -EPERM; + if (adev->in_suspend && !adev->in_runpm) + return -EPERM; + + r = pm_runtime_get_sync(ddev->dev); + if (r < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return r; + } + + r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, + (void *)&ss_power, &size); + if (r) + goto out; + + r = sysfs_emit(buf, "%u%%\n", ss_power); + +out: + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return r; +} + +/** + * DOC: smartshift_dgpu_power + * + * The amdgpu driver provides a sysfs API for reporting the dGPU power + * share if the device is in HG and supports smartshift. The value + * is expressed as the proportion of stapm limit where stapm limit + * is the total APU power limit. The value is in percentage. If dGPU + * power is 20% higher than STAPM power(120%), it's using 20% of the + * APU's power headroom. + */ + +static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + uint32_t ss_power, size; + int r = 0; + + if (amdgpu_in_reset(adev)) + return -EPERM; + if (adev->in_suspend && !adev->in_runpm) + return -EPERM; + + r = pm_runtime_get_sync(ddev->dev); + if (r < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return r; + } + + r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, + (void *)&ss_power, &size); + + if (r) + goto out; + + r = sysfs_emit(buf, "%u%%\n", ss_power); + +out: + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return r; +} + +/** + * DOC: smartshift_bias + * + * The amdgpu driver provides a sysfs API for reporting the + * smartshift(SS2.0) bias level. The value ranges from -100 to 100 + * and the default is 0. -100 sets maximum preference to APU + * and 100 sets max perference to dGPU. + */ + +static ssize_t amdgpu_get_smartshift_bias(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int r = 0; + + r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); + + return r; +} + +static ssize_t amdgpu_set_smartshift_bias(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int r = 0; + int bias = 0; + + if (amdgpu_in_reset(adev)) + return -EPERM; + if (adev->in_suspend && !adev->in_runpm) + return -EPERM; + + r = pm_runtime_get_sync(ddev->dev); + if (r < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return r; + } + + r = kstrtoint(buf, 10, &bias); + if (r) + goto out; + + if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) + bias = AMDGPU_SMARTSHIFT_MAX_BIAS; + else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) + bias = AMDGPU_SMARTSHIFT_MIN_BIAS; + + amdgpu_smartshift_bias = bias; + r = count; + + /* TODO: upadte bias level with SMU message */ + +out: + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + return r; +} + + +static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, + uint32_t mask, enum amdgpu_device_attr_states *states) +{ + uint32_t ss_power, size; + + if (!amdgpu_acpi_is_power_shift_control_supported()) + *states = ATTR_STATE_UNSUPPORTED; + else if ((adev->flags & AMD_IS_PX) && + !amdgpu_device_supports_smart_shift(adev_to_drm(adev))) + *states = ATTR_STATE_UNSUPPORTED; + else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, + (void *)&ss_power, &size)) + *states = ATTR_STATE_UNSUPPORTED; + else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, + (void *)&ss_power, &size)) + *states = ATTR_STATE_UNSUPPORTED; + + return 0; +} + +static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, + uint32_t mask, enum amdgpu_device_attr_states *states) +{ + uint32_t ss_power, size; + + if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) + *states = ATTR_STATE_UNSUPPORTED; + else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, + (void *)&ss_power, &size)) + *states = ATTR_STATE_UNSUPPORTED; + else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, + (void *)&ss_power, &size)) + *states = ATTR_STATE_UNSUPPORTED; + + return 0; +} + static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), @@ -1823,6 +2028,12 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC), AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC), AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, + .attr_update = ss_power_attr_update), + AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, + .attr_update = ss_power_attr_update), + AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, + .attr_update = ss_bias_attr_update), }; static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, @@ -1922,7 +2133,7 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev, BUG_ON(!attr); - attr_update = attr->attr_update ? attr_update : default_attr_update; + attr_update = attr->attr_update ? attr->attr_update : default_attr_update; ret = attr_update(adev, attr, mask, &attr_states); if (ret) { @@ -2697,9 +2908,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, { struct amdgpu_device *adev = dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int limit_type = to_sensor_dev_attr(attr)->index; - uint32_t limit = limit_type << 24; - uint32_t max_limit = 0; + enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; + enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_MAX; + uint32_t limit; ssize_t size; int r; @@ -2714,16 +2925,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, return r; } - if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else if (pp_funcs && pp_funcs->get_power_limit) { - pp_funcs->get_power_limit(adev->powerplay.pp_handle, - &limit, &max_limit, true); - size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000); - } else { - size = snprintf(buf, PAGE_SIZE, "\n"); - } + if (pp_funcs && pp_funcs->get_power_limit) + r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, + pp_limit_level, power_type); + else + r = -ENODATA; + + if (!r) + size = sysfs_emit(buf, "%u\n", limit * 1000000); + else + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -2737,8 +2948,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, { struct amdgpu_device *adev = dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int limit_type = to_sensor_dev_attr(attr)->index; - uint32_t limit = limit_type << 24; + enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; + enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_CURRENT; + uint32_t limit; ssize_t size; int r; @@ -2753,16 +2965,16 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, return r; } - if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else if (pp_funcs && pp_funcs->get_power_limit) { - pp_funcs->get_power_limit(adev->powerplay.pp_handle, - &limit, NULL, false); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else { - size = snprintf(buf, PAGE_SIZE, "\n"); - } + if (pp_funcs && pp_funcs->get_power_limit) + r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, + pp_limit_level, power_type); + else + r = -ENODATA; + + if (!r) + size = sysfs_emit(buf, "%u\n", limit * 1000000); + else + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -2776,8 +2988,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, { struct amdgpu_device *adev = dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int limit_type = to_sensor_dev_attr(attr)->index; - uint32_t limit = limit_type << 24; + enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; + enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_DEFAULT; + uint32_t limit; ssize_t size; int r; @@ -2792,16 +3005,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, return r; } - if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else if (pp_funcs && pp_funcs->get_power_limit) { - pp_funcs->get_power_limit(adev->powerplay.pp_handle, - &limit, NULL, true); - size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); - } else { - size = snprintf(buf, PAGE_SIZE, "\n"); - } + if (pp_funcs && pp_funcs->get_power_limit) + r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, + pp_limit_level, power_type); + else + r = -ENODATA; + + if (!r) + size = sysfs_emit(buf, "%u\n", limit * 1000000); + else + size = sysfs_emit(buf, "\n"); pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -3534,6 +3747,45 @@ out: DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); +/* + * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW + * + * Reads debug memory region allocated to PMFW + */ +static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + void *pp_handle = adev->powerplay.pp_handle; + size_t smu_prv_buf_size; + void *smu_prv_buf; + + if (amdgpu_in_reset(adev)) + return -EPERM; + if (adev->in_suspend && !adev->in_runpm) + return -EPERM; + + if (pp_funcs && pp_funcs->get_smu_prv_buf_details) + pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf, + &smu_prv_buf_size); + else + return -ENOSYS; + + if (!smu_prv_buf || !smu_prv_buf_size) + return -EINVAL; + + return simple_read_from_buffer(buf, size, pos, smu_prv_buf, + smu_prv_buf_size); +} + +static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = amdgpu_pm_prv_buffer_read, + .llseek = default_llseek, +}; + #endif void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) @@ -3545,5 +3797,10 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_pm_info", 0444, root, adev, &amdgpu_debugfs_pm_info_fops); + if (adev->pm.smu_prv_buffer_size > 0) + debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, + adev, + &amdgpu_debugfs_pm_prv_buffer_fops, + adev->pm.smu_prv_buffer_size); #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 8bb224f6c762..3e89852e4820 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -35,6 +35,48 @@ #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) +// Power Throttlers +#define SMU_THROTTLER_PPT0_BIT 0 +#define SMU_THROTTLER_PPT1_BIT 1 +#define SMU_THROTTLER_PPT2_BIT 2 +#define SMU_THROTTLER_PPT3_BIT 3 +#define SMU_THROTTLER_SPL_BIT 4 +#define SMU_THROTTLER_FPPT_BIT 5 +#define SMU_THROTTLER_SPPT_BIT 6 +#define SMU_THROTTLER_SPPT_APU_BIT 7 + +// Current Throttlers +#define SMU_THROTTLER_TDC_GFX_BIT 16 +#define SMU_THROTTLER_TDC_SOC_BIT 17 +#define SMU_THROTTLER_TDC_MEM_BIT 18 +#define SMU_THROTTLER_TDC_VDD_BIT 19 +#define SMU_THROTTLER_TDC_CVIP_BIT 20 +#define SMU_THROTTLER_EDC_CPU_BIT 21 +#define SMU_THROTTLER_EDC_GFX_BIT 22 +#define SMU_THROTTLER_APCC_BIT 23 + +// Temperature +#define SMU_THROTTLER_TEMP_GPU_BIT 32 +#define SMU_THROTTLER_TEMP_CORE_BIT 33 +#define SMU_THROTTLER_TEMP_MEM_BIT 34 +#define SMU_THROTTLER_TEMP_EDGE_BIT 35 +#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 +#define SMU_THROTTLER_TEMP_SOC_BIT 37 +#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 +#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 +#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 +#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 +#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 +#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 +#define SMU_THROTTLER_VRHOT0_BIT 44 +#define SMU_THROTTLER_VRHOT1_BIT 45 +#define SMU_THROTTLER_PROCHOT_CPU_BIT 46 +#define SMU_THROTTLER_PROCHOT_GFX_BIT 47 + +// Other +#define SMU_THROTTLER_PPM_BIT 56 +#define SMU_THROTTLER_FIT_BIT 57 + struct smu_hw_power_state { unsigned int magic; }; @@ -392,10 +434,18 @@ struct smu_baco_context bool platform_support; }; +struct smu_freq_info { + uint32_t min; + uint32_t max; + uint32_t freq_level; +}; + struct pstates_clk_freq { uint32_t min; uint32_t standard; uint32_t peak; + struct smu_freq_info custom; + struct smu_freq_info curr; }; struct smu_umd_pstate_table { @@ -715,7 +765,10 @@ struct pptable_funcs { /** * @get_power_limit: Get the device's power limits. */ - int (*get_power_limit)(struct smu_context *smu); + int (*get_power_limit)(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit); /** * @get_ppt_limit: Get the device's ppt limits. @@ -924,7 +977,9 @@ struct pptable_funcs { * @disable_all_features_with_exception: Disable all features with * exception to those in &mask. */ - int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask); + int (*disable_all_features_with_exception)(struct smu_context *smu, + bool no_hw_disablement, + enum smu_feature_mask mask); /** * @notify_display_change: Enable fast memory clock switching. @@ -1177,6 +1232,12 @@ struct pptable_funcs { */ int (*wait_for_event)(struct smu_context *smu, enum smu_event_type event, uint64_t event_arg); + + /** + * @sned_hbm_bad_pages_num: message SMU to update bad page number + * of SMUBUS table. + */ + int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); }; typedef enum { @@ -1210,6 +1271,8 @@ typedef enum { METRICS_CURR_FANSPEED, METRICS_VOLTAGE_VDDSOC, METRICS_VOLTAGE_VDDGFX, + METRICS_SS_APU_SHARE, + METRICS_SS_DGPU_SHARE, } MetricsMember_t; enum smu_cmn2asic_mapping_type { @@ -1252,9 +1315,10 @@ enum smu_cmn2asic_mapping_type { [profile] = {1, (workload)} #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) -int smu_get_power_limit(struct smu_context *smu, +int smu_get_power_limit(void *handle, uint32_t *limit, - enum smu_ppt_limit_level limit_level); + enum pp_power_limit_level pp_limit_level, + enum pp_power_type pp_power_type); bool smu_mode1_reset_is_support(struct smu_context *smu); bool smu_mode2_reset_is_support(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h index fa95147b5a63..61c87c39be80 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h +++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h @@ -129,8 +129,8 @@ #define FEATURE_SMNCLK_DPM_BIT 47 #define FEATURE_PERLINK_GMIDOWN_BIT 48 #define FEATURE_GFX_EDC_BIT 49 -#define FEATURE_SPARE_50_BIT 50 -#define FEATURE_SPARE_51_BIT 51 +#define FEATURE_GFX_PER_PART_VMIN_BIT 50 +#define FEATURE_SMART_SHIFT_BIT 51 #define FEATURE_SPARE_52_BIT 52 #define FEATURE_SPARE_53_BIT 53 #define FEATURE_SPARE_54_BIT 54 @@ -940,6 +940,367 @@ typedef struct { } PPTable_t; +typedef struct { + // MAJOR SECTION: SKU PARAMETERS + + uint32_t Version; + + // SECTION: Feature Enablement + uint32_t FeaturesToRun[NUM_FEATURES / 32]; + + // SECTION: Infrastructure Limits + uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts + uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms + uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts + uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms + + uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps + uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms + + uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius + + uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) + + // SECTION: Power Configuration + uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e + uint8_t TotalPowerPadding[3]; + + // SECTION: APCC Settings + uint32_t ApccPlusResidencyLimit; + + //SECTION: SMNCLK DPM + uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz + uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) + + uint32_t PaddingAPCC; + uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) + uint16_t PaddingPerPartDroop; + + // SECTION: Throttler settings + uint32_t ThrottlerControlMask; // See Throtter masks defines + + // SECTION: FW DSTATE Settings + uint32_t FwDStateMask; // See FW DState masks defines + + // SECTION: ULV Settings + uint16_t UlvVoltageOffsetSoc; // In mV(Q2) + uint16_t UlvVoltageOffsetGfx; // In mV(Q2) + + uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode + uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode + + uint16_t SocLIVmin; + uint16_t SocLIVminoffset; + + uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events + uint8_t paddingRlcUlvParams[3]; + + // SECTION: Voltage Control Parameters + uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX + uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC + uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX + uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC + + uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits + uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits + + // SECTION: Temperature Dependent Vmin + uint16_t VDDGFX_TVmin; //Celcius + uint16_t VDDSOC_TVmin; //Celcius + uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 + uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 + uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 + uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 + + uint16_t VDDGFX_TVminHystersis; // Celcius + uint16_t VDDSOC_TVminHystersis; // Celcius + + //SECTION: DPM Config 1 + DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; + + uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz + uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz + uint32_t Paddingclks; + + DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format + + uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz + + uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 + + // Used for MALL performance boost + uint16_t FclkBoostFreq; // In Mhz + uint16_t FclkParamPadding; + + // SECTION: DPM Config 2 + uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz + uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) + uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) + uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) + // GFXCLK DPM + uint16_t GfxclkFgfxoffEntry; // in Mhz + uint16_t GfxclkFinit; // in Mhz + uint16_t GfxclkFidle; // in MHz + uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL + uint8_t GfxclkPadding; + + // GFX GPO + uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM + uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled + uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled + uint8_t GfxGpoPadding[1]; + uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation + + uint32_t GfxGpoPadding32[4]; + + uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz + uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz + uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz + + uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase + + uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase + uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. + + uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. + + uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. + uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. + + uint32_t DcsParamPadding[5]; + + uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 + + // UCLK section + uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only + uint8_t PaddingMem[3]; + + uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. + + // Used for 2-Step UCLK change workaround + UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz + UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz + uint16_t UclkDpmMidstepFreq; // In Mhz + uint16_t UclkMidstepPadding; + + // Link DPM Settings + uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 + uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 + uint16_t LclkFreq[NUM_LINK_LEVELS]; + + // SECTION: Fan Control + uint16_t FanStopTemp; //Celcius + uint16_t FanStartTemp; //Celcius + + uint16_t FanGain[TEMP_COUNT]; + + uint16_t FanPwmMin; + uint16_t FanAcousticLimitRpm; + uint16_t FanThrottlingRpm; + uint16_t FanMaximumRpm; + uint16_t MGpuFanBoostLimitRpm; + uint16_t FanTargetTemperature; + uint16_t FanTargetGfxclk; + uint16_t FanPadding16; + uint8_t FanTempInputSelect; + uint8_t FanPadding; + uint8_t FanZeroRpmEnable; + uint8_t FanTachEdgePerRev; + + // The following are AFC override parameters. Leave at 0 to use FW defaults. + int16_t FuzzyFan_ErrorSetDelta; + int16_t FuzzyFan_ErrorRateSetDelta; + int16_t FuzzyFan_PwmSetDelta; + uint16_t FuzzyFan_Reserved; + + // SECTION: AVFS + // Overrides + uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; + uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) + uint8_t Padding8_Avfs; + + QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve + DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb + DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb + DroopInt_t dBtcGbSoc; // GHz->V BtcGb + LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V + + PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format + + QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V + + uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 + + uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; + uint8_t Padding8_GfxBtc[2]; + + uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 + uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 + + uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 + + // SECTION: XGMI + uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. + uint8_t XgmiDpmSpare[2]; + + // SECTION: Advanced Options + uint32_t DebugOverrides; + QuadraticInt_t ReservedEquation0; + QuadraticInt_t ReservedEquation1; + QuadraticInt_t ReservedEquation2; + QuadraticInt_t ReservedEquation3; + + // SECTION: Sku Reserved + uint8_t CustomerVariant; + + //VC BTC parameters are only applicable to VDD_GFX domain + uint8_t VcBtcEnabled; + uint16_t VcBtcVminT0; // T0_VMIN + uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET + uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB + uint32_t VcBtcPsmA; // A_PSM + uint32_t VcBtcPsmB; // B_PSM + uint32_t VcBtcVminA; // A_VMIN + uint32_t VcBtcVminB; // B_VMIN + + //GPIO Board feature + uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs + uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages + + uint32_t SkuReserved[63]; + + + + // MAJOR SECTION: BOARD PARAMETERS + + //SECTION: Gaming Clocks + uint32_t GamingClk[6]; + + // SECTION: I2C Control + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + + uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 + uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 + uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off + uint8_t I2cSpare[1]; + + // SECTION: SVI2 Board Parameters + uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields + uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields + uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields + uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields + + uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode + + // SECTION: Telemetry Settings + uint16_t GfxMaxCurrent; // in Amps + int8_t GfxOffset; // in Amps + uint8_t Padding_TelemetryGfx; + + uint16_t SocMaxCurrent; // in Amps + int8_t SocOffset; // in Amps + uint8_t Padding_TelemetrySoc; + + uint16_t Mem0MaxCurrent; // in Amps + int8_t Mem0Offset; // in Amps + uint8_t Padding_TelemetryMem0; + + uint16_t Mem1MaxCurrent; // in Amps + int8_t Mem1Offset; // in Amps + uint8_t Padding_TelemetryMem1; + + uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) + + // SECTION: GPIO Settings + uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching + uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching + uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event + uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event + + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t GthrGpio; // GPIO pin configured for GTHR Event + uint8_t GthrPolarity; // replace GPIO polarity for GTHR + + // LED Display Settings + uint8_t LedPin0; // GPIO number for LedPin[0] + uint8_t LedPin1; // GPIO number for LedPin[1] + uint8_t LedPin2; // GPIO number for LedPin[2] + uint8_t LedEnableMask; + + uint8_t LedPcie; // GPIO number for PCIE results + uint8_t LedError; // GPIO number for Error Cases + uint8_t LedSpare1[2]; + + // SECTION: Clock Spread Spectrum + + // GFXCLK PLL Spread Spectrum + uint8_t PllGfxclkSpreadEnabled; // on or off + uint8_t PllGfxclkSpreadPercent; // Q4.4 + uint16_t PllGfxclkSpreadFreq; // kHz + + // GFXCLK DFLL Spread Spectrum + uint8_t DfllGfxclkSpreadEnabled; // on or off + uint8_t DfllGfxclkSpreadPercent; // Q4.4 + uint16_t DfllGfxclkSpreadFreq; // kHz + + // UCLK Spread Spectrum + uint16_t UclkSpreadPadding; + uint16_t UclkSpreadFreq; // kHz + + // FCLK Spread Spectrum + uint8_t FclkSpreadEnabled; // on or off + uint8_t FclkSpreadPercent; // Q4.4 + uint16_t FclkSpreadFreq; // kHz + + // Section: Memory Config + uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. + + uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines + uint8_t PaddingMem1[3]; + + // Section: Total Board Power + uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power + uint16_t BoardPowerPadding; + + // SECTION: XGMI Training + uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; + uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; + + uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; + uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; + + // SECTION: UMC feature flags + uint8_t HsrEnabled; + uint8_t VddqOffEnabled; + uint8_t PaddingUmcFlags[2]; + + // UCLK Spread Spectrum + uint8_t UclkSpreadPercent[16]; + + // SECTION: Board Reserved + uint32_t BoardReserved[11]; + + // SECTION: Structure Padding + + // Padding for MMHUB - do not modify this + uint32_t MmHubPadding[8]; // SMU internal use + + +} PPTable_beige_goby_t; + typedef struct { // Time constant parameters for clock averages in ms uint16_t GfxclkAverageLpfTau; @@ -1265,4 +1626,5 @@ typedef struct { // These defines are used with the SMC_MSG_SetUclkFastSwitch message. #define UCLK_SWITCH_SLOW 0 #define UCLK_SWITCH_FAST 1 +#define UCLK_SWITCH_DUMMY 2 #endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h index d23533bda002..a017983ff1fa 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h +++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h @@ -64,7 +64,7 @@ #define FEATURE_SMUIO_CG_BIT 28 #define FEATURE_THM_CG_BIT 29 #define FEATURE_CLK_CG_BIT 30 -#define FEATURE_SPARE_31_BIT 31 +#define FEATURE_EDC_BIT 31 #define FEATURE_SPARE_32_BIT 32 #define FEATURE_SPARE_33_BIT 33 #define FEATURE_SPARE_34_BIT 34 @@ -439,8 +439,11 @@ typedef struct { int8_t XgmiOffset; // in Amps uint8_t Padding_TelemetryXgmi; + uint16_t EdcPowerLimit; + uint16_t spare6; + //reserved - uint32_t reserved[15]; + uint32_t reserved[14]; } PPTable_t; diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h new file mode 100644 index 000000000000..25540cb28208 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h @@ -0,0 +1,222 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU13_DRIVER_IF_YELLOW_CARP_H__ +#define __SMU13_DRIVER_IF_YELLOW_CARP_H__ + +// *** IMPORTANT *** +// SMU TEAM: Always increment the interface version if +// any structure is changed in this file +#define SMU13_DRIVER_IF_VERSION 4 + +typedef struct { + int32_t value; + uint32_t numFractionalBits; +} FloatInIntFormat_t; + +typedef enum { + DSPCLK_DCFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; // in MHz + uint16_t Vid; // min voltage in SVI3 VID +} DisplayClockTable_t; + +typedef struct { + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t WmType; // Used for normal pstate change or memory retraining + uint8_t Padding[2]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 +#define WM_PSTATE_CHG 0 +#define WM_RETRAINING 1 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +} Watermarks_t; + +typedef enum { + CUSTOM_DPM_SETTING_GFXCLK, + CUSTOM_DPM_SETTING_CCLK, + CUSTOM_DPM_SETTING_FCLK_CCX, + CUSTOM_DPM_SETTING_FCLK_GFX, + CUSTOM_DPM_SETTING_FCLK_STALLS, + CUSTOM_DPM_SETTING_LCLK, + CUSTOM_DPM_SETTING_COUNT, +} CUSTOM_DPM_SETTING_e; + +typedef struct { + uint8_t ActiveHystLimit; + uint8_t IdleHystLimit; + uint8_t FPS; + uint8_t MinActiveFreqType; + FloatInIntFormat_t MinActiveFreq; + FloatInIntFormat_t PD_Data_limit; + FloatInIntFormat_t PD_Data_time_constant; + FloatInIntFormat_t PD_Data_error_coeff; + FloatInIntFormat_t PD_Data_error_rate_coeff; +} DpmActivityMonitorCoeffExt_t; + +typedef struct { + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; +} CustomDpmSettings_t; + +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_VCN_DPM_LEVELS 8 +#define NUM_SOC_VOLTAGE_LEVELS 8 +#define NUM_DF_PSTATE_LEVELS 4 + +typedef struct { + uint32_t FClk; + uint32_t MemClk; + uint32_t Voltage; + uint8_t WckRatio; + uint8_t Spare[3]; +} DfPstateTable_t; + +//Freq in MHz +//Voltage in milli volts with 2 fractional bits +typedef struct { + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + uint32_t VClocks[NUM_VCN_DPM_LEVELS]; + uint32_t DClocks[NUM_VCN_DPM_LEVELS]; + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; + DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS]; + + uint8_t NumDcfClkLevelsEnabled; + uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk + uint8_t NumSocClkLevelsEnabled; + uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk + uint8_t NumDfPstatesEnabled; + uint8_t spare[3]; + + uint32_t MinGfxClk; + uint32_t MaxGfxClk; +} DpmClocks_t; + + +// Throttler Status Bitmask +#define THROTTLER_STATUS_BIT_SPL 0 +#define THROTTLER_STATUS_BIT_FPPT 1 +#define THROTTLER_STATUS_BIT_SPPT 2 +#define THROTTLER_STATUS_BIT_SPPT_APU 3 +#define THROTTLER_STATUS_BIT_THM_CORE 4 +#define THROTTLER_STATUS_BIT_THM_GFX 5 +#define THROTTLER_STATUS_BIT_THM_SOC 6 +#define THROTTLER_STATUS_BIT_TDC_VDD 7 +#define THROTTLER_STATUS_BIT_TDC_SOC 8 +#define THROTTLER_STATUS_BIT_PROCHOT_CPU 9 +#define THROTTLER_STATUS_BIT_PROCHOT_GFX 10 +#define THROTTLER_STATUS_BIT_EDC_CPU 11 +#define THROTTLER_STATUS_BIT_EDC_GFX 12 + +typedef struct { + uint16_t GfxclkFrequency; //[MHz] + uint16_t SocclkFrequency; //[MHz] + uint16_t VclkFrequency; //[MHz] + uint16_t DclkFrequency; //[MHz] + uint16_t MemclkFrequency; //[MHz] + uint16_t spare; + + uint16_t GfxActivity; //[centi] + uint16_t UvdActivity; //[centi] + + uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC + uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC + uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC + + //3rd party tools in Windows need this info in the case of APUs + uint16_t CoreFrequency[8]; //[MHz] + uint16_t CorePower[8]; //[mW] + uint16_t CoreTemperature[8]; //[centi-Celsius] + uint16_t L3Frequency; //[MHz] + uint16_t L3Temperature; //[centi-Celsius] + + uint16_t GfxTemperature; //[centi-Celsius] + uint16_t SocTemperature; //[centi-Celsius] + uint16_t ThrottlerStatus; + + uint16_t CurrentSocketPower; //[mW] + uint16_t StapmOpnLimit; //[W] + uint16_t StapmCurrentLimit; //[W] + uint32_t ApuPower; //[mW] + uint32_t dGpuPower; //[mW] + + uint16_t VddTdcValue; //[mA] + uint16_t SocTdcValue; //[mA] + uint16_t VddEdcValue; //[mA] + uint16_t SocEdcValue; //[mA] + + uint16_t InfrastructureCpuMaxFreq; //[MHz] + uint16_t InfrastructureGfxMaxFreq; //[MHz] + + uint16_t SkinTemp; + uint16_t DeviceState; +} SmuMetrics_t; + + +// Workload bits +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 +#define WORKLOAD_PPLIB_VIDEO_BIT 2 +#define WORKLOAD_PPLIB_VR_BIT 3 +#define WORKLOAD_PPLIB_COMPUTE_BIT 4 +#define WORKLOAD_PPLIB_CUSTOM_BIT 5 +#define WORKLOAD_PPLIB_COUNT 6 + +#define TABLE_BIOS_IF 0 // Called by BIOS +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS +#define TABLE_CUSTOM_DPM 2 // Called by Driver +#define TABLE_SPARE1 3 +#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS +#define TABLE_MOMENTARY_PM 5 // Called by Tools +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log +#define TABLE_SMU_METRICS 7 // Called by Driver +#define TABLE_INFRASTRUCTURE_LIMITS 8 +#define TABLE_COUNT 9 + +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index bb55a96f98e9..1962a5877191 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -34,6 +34,7 @@ #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF +#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x9 /* MP Apertures */ #define MP0_Public 0x03800000 @@ -243,6 +244,9 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) int smu_v11_0_baco_enter(struct smu_context *smu); int smu_v11_0_baco_exit(struct smu_context *smu); +int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, + enum smu_v11_0_baco_seq baco_seq); + int smu_v11_0_mode1_reset(struct smu_context *smu); int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h index 8145e1cbf181..6119a36b2cba 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h @@ -26,7 +26,7 @@ #include "amdgpu_smu.h" #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF -#define SMU13_DRIVER_IF_VERSION_ALDE 0x6 +#define SMU13_DRIVER_IF_VERSION_ALDE 0x07 /* MP Apertures */ #define MP0_Public 0x03800000 @@ -51,12 +51,6 @@ #define CTF_OFFSET_HOTSPOT 5 #define CTF_OFFSET_MEM 5 -static const struct smu_temperature_range smu13_thermal_policy[] = -{ - {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, - { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, -}; - struct smu_13_0_max_sustainable_clocks { uint32_t display_clock; uint32_t phy_clock; diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h new file mode 100644 index 000000000000..b6c976a4d578 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h @@ -0,0 +1,57 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_V13_0_1_H__ +#define __SMU_V13_0_1_H__ + +#include "amdgpu_smu.h" + +#define SMU13_0_1_DRIVER_IF_VERSION_INV 0xFFFFFFFF +#define SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP 0x3 + +/* MP Apertures */ +#define MP0_Public 0x03800000 +#define MP0_SRAM 0x03900000 +#define MP1_Public 0x03b00000 +#define MP1_SRAM 0x03c00004 + +/* address block */ +#define smnMP1_FIRMWARE_FLAGS 0x3010024 + + +#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) + +int smu_v13_0_1_check_fw_status(struct smu_context *smu); + +int smu_v13_0_1_check_fw_version(struct smu_context *smu); + +int smu_v13_0_1_fini_smc_tables(struct smu_context *smu); + +int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu); + +int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu); + +int smu_v13_0_1_set_driver_table_location(struct smu_context *smu); + +int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable); +#endif +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h new file mode 100644 index 000000000000..5627de734246 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h @@ -0,0 +1,139 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SMU_V13_0_1_PMFW_H__ +#define __SMU_V13_0_1_PMFW_H__ + +#include "smu13_driver_if_yellow_carp.h" + +#pragma pack(push, 1) + +#define ENABLE_DEBUG_FEATURES + +// Firmware features +// Feature Control Defines +#define FEATURE_CCLK_DPM_BIT 0 +#define FEATURE_FAN_CONTROLLER_BIT 1 +#define FEATURE_DATA_CALCULATION_BIT 2 +#define FEATURE_PPT_BIT 3 +#define FEATURE_TDC_BIT 4 +#define FEATURE_THERMAL_BIT 5 +#define FEATURE_FIT_BIT 6 +#define FEATURE_EDC_BIT 7 +#define FEATURE_PLL_POWER_DOWN_BIT 8 +#define FEATURE_ULV_BIT 9 +#define FEATURE_VDDOFF_BIT 10 +#define FEATURE_VCN_DPM_BIT 11 +#define FEATURE_CSTATE_BOOST_BIT 12 +#define FEATURE_FCLK_DPM_BIT 13 +#define FEATURE_SOCCLK_DPM_BIT 14 +#define FEATURE_MP0CLK_DPM_BIT 15 +#define FEATURE_LCLK_DPM_BIT 16 +#define FEATURE_SHUBCLK_DPM_BIT 17 +#define FEATURE_DCFCLK_DPM_BIT 18 +#define FEATURE_GFX_DPM_BIT 19 +#define FEATURE_DS_GFXCLK_BIT 20 +#define FEATURE_DS_SOCCLK_BIT 21 +#define FEATURE_DS_LCLK_BIT 22 +#define FEATURE_DS_DCFCLK_BIT 23 +#define FEATURE_DS_SHUBCLK_BIT 24 +#define FEATURE_GFX_TEMP_VMIN_BIT 25 +#define FEATURE_ZSTATES_BIT 26 +#define FEATURE_WHISPER_MODE_BIT 27 +#define FEATURE_DS_FCLK_BIT 28 +#define FEATURE_DS_SMNCLK_BIT 29 +#define FEATURE_DS_MP1CLK_BIT 30 +#define FEATURE_DS_MP0CLK_BIT 31 +#define FEATURE_CLK_LOW_POWER_BIT 32 +#define FEATURE_FUSE_PG_BIT 33 +#define FEATURE_GFX_DEM_BIT 34 +#define FEATURE_PSI_BIT 35 +#define FEATURE_PROCHOT_BIT 36 +#define FEATURE_CPUOFF_BIT 37 +#define FEATURE_STAPM_BIT 38 +#define FEATURE_S0I3_BIT 39 +#define FEATURE_DF_LIGHT_CSTATE 40 // shift the order or DFCstate annd DF light Cstate +#define FEATURE_PERF_LIMIT_BIT 41 +#define FEATURE_CORE_DLDO_BIT 42 +#define FEATURE_RSMU_LOW_POWER_BIT 43 +#define FEATURE_SMN_LOW_POWER_BIT 44 +#define FEATURE_THM_LOW_POWER_BIT 45 +#define FEATURE_SMUIO_LOW_POWER_BIT 46 +#define FEATURE_MP1_LOW_POWER_BIT 47 +#define FEATURE_DS_VCN_BIT 48 +#define FEATURE_CPPC_BIT 49 +#define FEATURE_CPPC_PREFERRED_CORES 50 +#define FEATURE_SMART_SHIFT_BIT 51 +#define FEATURE_DF_CSTATES_BIT 52 +#define FEATURE_MSMU_LOW_POWER_BIT 53 +#define FEATURE_SOC_VOLTAGE_MON_BIT 54 +#define FEATURE_ATHUB_PG_BIT 55 +#define FEATURE_VDDOFF_ECO_BIT 56 +#define FEATURE_ZSTATES_ECO_BIT 57 +#define FEATURE_CC6_BIT 58 +#define FEATURE_DS_UMCCLK_BIT 59 +#define FEATURE_DS_HSPCLK_BIT 60 +#define NUM_FEATURES 61 + +typedef struct { + // MP1_EXT_SCRATCH0 + uint32_t DpmHandlerID : 8; + uint32_t ActivityMonitorID : 8; + uint32_t DpmTimerID : 8; + uint32_t DpmHubID : 4; + uint32_t DpmHubTask : 4; + // MP1_EXT_SCRATCH1 + uint32_t GfxoffStatus : 8; + uint32_t GfxStatus : 2; + uint32_t CpuOff : 2; + uint32_t VddOff : 1; + uint32_t InUlv : 1; + uint32_t InWhisperMode : 1; + uint32_t spare0 : 1; + uint32_t ZstateStatus : 4; + uint32_t spare1 :12; + // MP1_EXT_SCRATCH2 + uint32_t P2JobHandler :24; + uint32_t RsmuPmiP2FinishedCnt : 8; + // MP1_EXT_SCRATCH3 + uint32_t PostCode :32; + // MP1_EXT_SCRATCH4 + uint32_t MsgPortBusy :15; + uint32_t RsmuPmiP1Pending : 1; + uint32_t DfCstateExitPending : 1; + uint32_t Pc6EntryPending : 1; + uint32_t Pc6ExitPending : 1; + uint32_t WarmResetPending : 1; + uint32_t Mp0ClkPending : 1; + uint32_t spare2 : 3; + uint32_t RsmuPmiP2PendingCnt : 8; + // MP1_EXT_SCRATCH5 + uint32_t IdleMask :32; + // MP1_EXT_SCRATCH6 = RTOS threads' status + // MP1_EXT_SCRATCH7 = RTOS Current Job +} FwStatus_t; + + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h new file mode 100644 index 000000000000..1d3447991d0c --- /dev/null +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h @@ -0,0 +1,97 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU_13_0_1_PPSMC_H +#define SMU_13_0_1_PPSMC_H + +/** @def PPS_PMFW_IF_VER +* PPS (PPLib) to PMFW IF version 1.0 +*/ +#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor + +/** @defgroup ResponseCodes PMFW Response Codes: +* @{ +*/ +#define PPSMC_Result_OK 0x1 ///< Message Response OK +#define PPSMC_Result_Failed 0xFF ///< Message Response Failed +#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command +#define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite +#define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message +/** @}*/ + +/** @defgroup definitions Message definitions +* @{ +*/ +#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team +#define PPSMC_MSG_GetSmuVersion 0x02 ///< Get PMFW version +#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version +#define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF +#define PPSMC_MSG_DisableGfxOff 0x05 ///< Disable GFXOFF +#define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN +#define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default +#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display +#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz +#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work load type +#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF +#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload +#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer +#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer +#define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM +#define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM +#define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset +#define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK +#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK +#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK) +#define PPSMC_MSG_SPARE0 0x16 ///< Spared +#define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency +#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency +#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry +#define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK +#define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK +#define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK) +#define PPSMC_MSG_SetPowerLimitPercentage 0x20 ///< Set power limit percentage +#define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg +#define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by default +#define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK +#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK +#define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity +#define PPSMC_MSG_DisallowZstates 0x26 ///< Inform PMFW of disallowing Zstate entry, i.e. there is Miracast activity +#define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number +#define PPSMC_MSG_QueryActiveWgp 0x28 ///< Query the anumber of active WGP number +#define PPSMC_Message_Count 0x29 ///< Total number of PPS messages +/** @}*/ + +/** @enum Mode_Reset_e +* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset +*/ +typedef enum { + MODE1_RESET = 1, ///< Mode reset type 1 + MODE2_RESET = 2 ///< Mode reset type 2 +} Mode_Reset_e; +/** @}*/ + +#endif diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index ee6340c6f921..d2a38246a78a 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -1035,31 +1035,42 @@ static int pp_set_power_limit(void *handle, uint32_t limit) } static int pp_get_power_limit(void *handle, uint32_t *limit, - uint32_t *max_limit, bool default_limit) + enum pp_power_limit_level pp_limit_level, + enum pp_power_type power_type) { struct pp_hwmgr *hwmgr = handle; + int ret = 0; if (!hwmgr || !hwmgr->pm_en ||!limit) return -EINVAL; + if (power_type != PP_PWR_TYPE_SUSTAINED) + return -EOPNOTSUPP; + mutex_lock(&hwmgr->smu_lock); - if (default_limit) { - *limit = hwmgr->default_power_limit; - if (max_limit) { - *max_limit = *limit; + switch (pp_limit_level) { + case PP_PWR_LIMIT_CURRENT: + *limit = hwmgr->power_limit; + break; + case PP_PWR_LIMIT_DEFAULT: + *limit = hwmgr->default_power_limit; + break; + case PP_PWR_LIMIT_MAX: + *limit = hwmgr->default_power_limit; if (hwmgr->od_enabled) { - *max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); - *max_limit /= 100; + *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); + *limit /= 100; } - } + break; + default: + ret = -EOPNOTSUPP; + break; } - else - *limit = hwmgr->power_limit; mutex_unlock(&hwmgr->smu_lock); - return 0; + return ret; } static int pp_display_configuration_change(void *handle, @@ -1651,6 +1662,26 @@ static int pp_gfx_state_change_set(void *handle, uint32_t state) return 0; } +static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size) +{ + struct pp_hwmgr *hwmgr = handle; + struct amdgpu_device *adev = hwmgr->adev; + + if (!addr || !size) + return -EINVAL; + + *addr = NULL; + *size = 0; + mutex_lock(&hwmgr->smu_lock); + if (adev->pm.smu_prv_buffer) { + amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr); + *size = adev->pm.smu_prv_buffer_size; + } + mutex_unlock(&hwmgr->smu_lock); + + return 0; +} + static const struct amd_pm_funcs pp_dpm_funcs = { .load_firmware = pp_dpm_load_fw, .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, @@ -1714,4 +1745,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = { .set_xgmi_pstate = pp_set_xgmi_pstate, .get_gpu_metrics = pp_get_gpu_metrics, .gfx_state_change_set = pp_gfx_state_change_set, + .get_smu_prv_buf_details = pp_get_prv_buffer_details, }; diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c index 25b5831a15cd..981dc8c7112d 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c @@ -82,7 +82,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) /* Skip for suspend/resume case */ if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr) - && !amdgpu_passthrough(adev) && adev->in_suspend) { + && !amdgpu_passthrough(adev) && adev->in_suspend + && adev->asic_type != CHIP_RAVEN) { pr_info("dpm has been enabled\n"); return 0; } diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c index b1038d30c8dc..f503e61faa60 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c @@ -275,7 +275,7 @@ static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3( } /** - * atomctrl_get_memory_pll_dividers_si(). + * atomctrl_get_memory_pll_dividers_si * * @hwmgr: input parameter: pointer to HwMgr * @clock_value: input parameter: memory clock @@ -328,7 +328,7 @@ int atomctrl_get_memory_pll_dividers_si( } /** - * atomctrl_get_memory_pll_dividers_vi(). + * atomctrl_get_memory_pll_dividers_vi * * @hwmgr: input parameter: pointer to HwMgr * @clock_value: input parameter: memory clock @@ -1104,7 +1104,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( } /** - * atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table. + * atomctrl_get_voltage_evv_on_sclk: gets voltage via call to ATOM COMMAND table. * @hwmgr: input: pointer to hwManager * @voltage_type: input: type of EVV voltage VDDC or VDDGFX * @sclk: input: in 10Khz unit. DPM state SCLK frequency @@ -1144,7 +1144,7 @@ int atomctrl_get_voltage_evv_on_sclk( } /** - * atomctrl_get_voltage_evv gets voltage via call to ATOM COMMAND table. + * atomctrl_get_voltage_evv: gets voltage via call to ATOM COMMAND table. * @hwmgr: input: pointer to hwManager * @virtual_voltage_id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08 * @voltage: output: real voltage level in unit of mv diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 27cf22716793..43c3f6e755e7 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -377,6 +377,27 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { + struct amdgpu_device *adev = hwmgr->adev; + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); + int ret = -EINVAL; + + if (adev->in_suspend) { + pr_info("restore the fine grain parameters\n"); + + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetHardMinGfxClk, + smu10_data->gfx_actual_soft_min_freq, + NULL); + if (ret) + return ret; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetSoftMaxGfxClk, + smu10_data->gfx_actual_soft_max_freq, + NULL); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c index 0d38d4206848..6cfe148ed45b 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c @@ -129,10 +129,10 @@ int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) } /** -* Reset Fan Speed Control to default mode. -* @hwmgr: the address of the powerplay hardware manager. -* Exception: Should always succeed. -*/ + * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode. + * @hwmgr: the address of the powerplay hardware manager. + * Exception: Should always succeed. + */ int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) { if (!hwmgr->fan_ctrl_is_in_default_mode) { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 31c61ac3bd5e..25979106fd25 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -544,7 +544,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 /** - * Get Leakage VDDC based on leakage ID. + * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. * * @hwmgr: the address of the powerplay hardware manager. * return: always 0. @@ -600,7 +600,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) } /** - * Change virtual leakage voltage to actual value. + * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. * * @hwmgr: the address of the powerplay hardware manager. * @voltage: pointer to changing voltage @@ -626,7 +626,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, } /** - * Patch voltage lookup table by EVV leakages. + * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. * * @hwmgr: the address of the powerplay hardware manager. * @lookup_table: pointer to voltage lookup table @@ -1003,7 +1003,7 @@ static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) } /** - * Remove repeated voltage values and create table with unique values. + * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. * * @hwmgr: the address of the powerplay hardware manager. * @vol_table: the pointer to changing voltage table @@ -1152,7 +1152,7 @@ static void vega10_trim_voltage_table_to_fit_state_table( } /** - * Create Voltage Tables. + * vega10_construct_voltage_tables - Create Voltage Tables. * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 @@ -1595,7 +1595,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) } /** - * Populates single SMC GFXSCLK structure using the provided engine clock + * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure + * using the provided engine clock * * @hwmgr: the address of the hardware manager * @gfx_clock: the GFX clock to use to populate the structure. @@ -1660,7 +1661,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, } /** - * Populates single SMC SOCCLK structure using the provided clock. + * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure + * using the provided clock. * * @hwmgr: the address of the hardware manager. * @soc_clock: the SOC clock to use to populate the structure. @@ -1710,7 +1712,8 @@ static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, } /** - * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states + * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure + * based on the trimmed allowed dpm engine clock states * * @hwmgr: the address of the hardware manager */ @@ -1859,7 +1862,8 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, } /** - * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states. + * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure + * based on the trimmed allowed dpm memory clock states. * * @hwmgr: the address of the hardware manager. * return: PP_Result_OK on success. @@ -2537,7 +2541,7 @@ static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) } /** - * Initializes the SMC table and uploads it + * vega10_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 @@ -2919,7 +2923,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) } /** - * Tell SMC to enabled the supported DPMs. + * vega10_start_dpm - Tell SMC to enabled the supported DPMs. * * @hwmgr: the address of the powerplay hardware manager. * @bitmap: bitmap for the features to enabled. diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c index 1a097e608808..29e0d1d4035a 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c @@ -803,7 +803,7 @@ static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) #endif /** - * Initializes the SMC table and uploads it + * vega12_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c index 0dc16f25a463..ed3dff0b52d2 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c @@ -159,7 +159,8 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) } /** - * Set the requested temperature range for high and low alert signals + * vega12_thermal_set_temperature_range - Set the requested temperature range + * for high and low alert signals * * @hwmgr: The address of the hardware manager. * @range: Temperature range to be programmed for diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c index 2a28c9df15a0..8d99c7a5abf8 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c @@ -85,7 +85,7 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) return 0; if (state == BACO_STATE_IN) { - if (!ras || !ras->supported) { + if (!ras || !adev->ras_enabled) { data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); data |= 0x80000000; WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c index d3177a534fdf..0791309586c5 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c @@ -772,7 +772,7 @@ static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) } /** - * Initializes the SMC table and uploads it + * vega20_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index c29d8b3131b7..cb375f1beebd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -35,6 +35,7 @@ #include "renoir_ppt.h" #include "vangogh_ppt.h" #include "aldebaran_ppt.h" +#include "yellow_carp_ppt.h" #include "amd_pcie.h" /* @@ -570,6 +571,7 @@ static int smu_set_funcs(struct amdgpu_device *adev) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: sienna_cichlid_set_ppt_funcs(smu); break; case CHIP_ALDEBARAN: @@ -583,6 +585,9 @@ static int smu_set_funcs(struct amdgpu_device *adev) case CHIP_VANGOGH: vangogh_set_ppt_funcs(smu); break; + case CHIP_YELLOW_CARP: + yellow_carp_set_ppt_funcs(smu); + break; default: return -EINVAL; } @@ -666,6 +671,9 @@ static int smu_late_init(void *handle) return ret; } + if (adev->asic_type == CHIP_YELLOW_CARP) + return 0; + if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { ret = smu_set_default_od_settings(smu); if (ret) { @@ -680,13 +688,17 @@ static int smu_late_init(void *handle) return ret; } - ret = smu_get_asic_power_limits(smu); + ret = smu_get_asic_power_limits(smu, + &smu->current_power_limit, + &smu->default_power_limit, + &smu->max_power_limit); if (ret) { dev_err(adev->dev, "Failed to get asic power limits!\n"); return ret; } - smu_get_unique_id(smu); + if (!amdgpu_sriov_vf(adev)) + smu_get_unique_id(smu); smu_get_fan_parameters(smu); @@ -1370,15 +1382,20 @@ static int smu_disable_dpms(struct smu_context *smu) if (smu->uploading_custom_pp_table && (adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) - return 0; + return smu_disable_all_features_with_exception(smu, + true, + SMU_FEATURE_COUNT); /* * For Sienna_Cichlid, PMFW will handle the features disablement properly * on BACO in. Driver involvement is unnecessary. */ - if ((adev->asic_type == CHIP_SIENNA_CICHLID) && + if (((adev->asic_type == CHIP_SIENNA_CICHLID) || + ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) && use_baco) - return 0; + return smu_disable_all_features_with_exception(smu, + true, + SMU_FEATURE_BACO_BIT); /* * For gpu reset, runpm and hibernation through BACO, @@ -1386,6 +1403,7 @@ static int smu_disable_dpms(struct smu_context *smu) */ if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { ret = smu_disable_all_features_with_exception(smu, + false, SMU_FEATURE_BACO_BIT); if (ret) dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); @@ -2164,16 +2182,57 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) return ret; } -int smu_get_power_limit(struct smu_context *smu, +/** + * smu_get_power_limit - Request one of the SMU Power Limits + * + * @handle: pointer to smu context + * @limit: requested limit is written back to this variable + * @pp_limit_level: &pp_power_limit_level which limit of the power to return + * @pp_power_type: &pp_power_type type of power + * Return: 0 on success, <0 on error + * + */ +int smu_get_power_limit(void *handle, uint32_t *limit, - enum smu_ppt_limit_level limit_level) + enum pp_power_limit_level pp_limit_level, + enum pp_power_type pp_power_type) { - uint32_t limit_type = *limit >> 24; + struct smu_context *smu = handle; + enum smu_ppt_limit_level limit_level; + uint32_t limit_type; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; + switch(pp_power_type) { + case PP_PWR_TYPE_SUSTAINED: + limit_type = SMU_DEFAULT_PPT_LIMIT; + break; + case PP_PWR_TYPE_FAST: + limit_type = SMU_FAST_PPT_LIMIT; + break; + default: + return -EOPNOTSUPP; + break; + } + + switch(pp_limit_level){ + case PP_PWR_LIMIT_CURRENT: + limit_level = SMU_PPT_LIMIT_CURRENT; + break; + case PP_PWR_LIMIT_DEFAULT: + limit_level = SMU_PPT_LIMIT_DEFAULT; + break; + case PP_PWR_LIMIT_MAX: + limit_level = SMU_PPT_LIMIT_MAX; + break; + case PP_PWR_LIMIT_MIN: + default: + return -EOPNOTSUPP; + break; + } + mutex_lock(&smu->mutex); if (limit_type != SMU_DEFAULT_PPT_LIMIT) { @@ -2182,6 +2241,15 @@ int smu_get_power_limit(struct smu_context *smu, } else { switch (limit_level) { case SMU_PPT_LIMIT_CURRENT: + if ((smu->adev->asic_type == CHIP_ALDEBARAN) || + (smu->adev->asic_type == CHIP_SIENNA_CICHLID) || + (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) || + (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) || + (smu->adev->asic_type == CHIP_BEIGE_GOBY)) + ret = smu_get_asic_power_limits(smu, + &smu->current_power_limit, + NULL, + NULL); *limit = smu->current_power_limit; break; case SMU_PPT_LIMIT_DEFAULT: @@ -2933,6 +3001,26 @@ int smu_set_light_sbr(struct smu_context *smu, bool enable) return ret; } +static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) +{ + struct smu_context *smu = handle; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *memory_pool = &smu_table->memory_pool; + + if (!addr || !size) + return -EINVAL; + + *addr = NULL; + *size = 0; + mutex_lock(&smu->mutex); + if (memory_pool->bo) { + *addr = memory_pool->cpu_addr; + *size = memory_pool->size; + } + mutex_unlock(&smu->mutex); + + return 0; +} static const struct amd_pm_funcs swsmu_pm_funcs = { /* export for sysfs */ @@ -2940,6 +3028,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = { .get_fan_control_mode = smu_get_fan_control_mode, .set_fan_speed_percent = smu_set_fan_speed_percent, .get_fan_speed_percent = smu_get_fan_speed_percent, + .force_clock_level = smu_force_ppclk_levels, + .print_clock_levels = smu_print_ppclk_levels, .force_performance_level = smu_force_performance_level, .read_sensor = smu_read_sensor, .get_performance_level = smu_get_performance_level, @@ -2952,38 +3042,38 @@ static const struct amd_pm_funcs swsmu_pm_funcs = { .switch_power_profile = smu_switch_power_profile, /* export to amdgpu */ .dispatch_tasks = smu_handle_dpm_task, + .load_firmware = smu_load_microcode, .set_powergating_by_smu = smu_dpm_set_power_gate, .set_power_limit = smu_set_power_limit, + .get_power_limit = smu_get_power_limit, + .get_power_profile_mode = smu_get_power_profile_mode, + .set_power_profile_mode = smu_set_power_profile_mode, .odn_edit_dpm_table = smu_od_edit_dpm_table, .set_mp1_state = smu_set_mp1_state, + .gfx_state_change_set = smu_gfx_state_change_set, /* export to DC */ - .get_sclk = smu_get_sclk, - .get_mclk = smu_get_mclk, - .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, - .get_asic_baco_capability = smu_get_baco_capability, - .set_asic_baco_state = smu_baco_set_state, - .get_ppfeature_status = smu_sys_get_pp_feature_mask, - .set_ppfeature_status = smu_sys_set_pp_feature_mask, - .asic_reset_mode_2 = smu_mode2_reset, - .set_df_cstate = smu_set_df_cstate, - .set_xgmi_pstate = smu_set_xgmi_pstate, - .get_gpu_metrics = smu_sys_get_gpu_metrics, - .set_power_profile_mode = smu_set_power_profile_mode, - .get_power_profile_mode = smu_get_power_profile_mode, - .force_clock_level = smu_force_ppclk_levels, - .print_clock_levels = smu_print_ppclk_levels, - .get_uclk_dpm_states = smu_get_uclk_dpm_states, - .get_dpm_clock_table = smu_get_dpm_clock_table, - .display_configuration_change = smu_display_configuration_change, - .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, - .display_clock_voltage_request = smu_display_clock_voltage_request, - .set_active_display_count = smu_set_display_count, - .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, + .get_sclk = smu_get_sclk, + .get_mclk = smu_get_mclk, + .display_configuration_change = smu_display_configuration_change, + .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, + .display_clock_voltage_request = smu_display_clock_voltage_request, + .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, + .set_active_display_count = smu_set_display_count, + .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, + .get_asic_baco_capability = smu_get_baco_capability, + .set_asic_baco_state = smu_baco_set_state, + .get_ppfeature_status = smu_sys_get_pp_feature_mask, + .set_ppfeature_status = smu_sys_set_pp_feature_mask, + .asic_reset_mode_2 = smu_mode2_reset, + .set_df_cstate = smu_set_df_cstate, + .set_xgmi_pstate = smu_set_xgmi_pstate, + .get_gpu_metrics = smu_sys_get_gpu_metrics, .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, - .load_firmware = smu_load_microcode, - .gfx_state_change_set = smu_gfx_state_change_set, + .get_uclk_dpm_states = smu_get_uclk_dpm_states, + .get_dpm_clock_table = smu_get_dpm_clock_table, + .get_smu_prv_buf_details = smu_get_prv_buffer_details, }; int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 77693bf0840c..094df6f87cfc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -211,6 +211,26 @@ static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; +static const uint8_t arcturus_throttler_map[] = { + [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), + [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), + [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), + [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), + [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), + [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), + [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), + [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), + [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), + [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), + [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), + [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), + [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), + [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT), + [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT), +}; + static int arcturus_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -237,7 +257,7 @@ static int arcturus_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { kfree(smu_table->metrics_table); @@ -380,16 +400,31 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) return 0; } -static int arcturus_check_powerplay_table(struct smu_context *smu) +static void arcturus_check_bxco_support(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; struct smu_baco_context *smu_baco = &smu->smu_baco; + struct amdgpu_device *adev = smu->adev; + uint32_t val; if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || - powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) - smu_baco->platform_support = true; + powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { + val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); + smu_baco->platform_support = + (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : + false; + } +} + +static int arcturus_check_powerplay_table(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; + + arcturus_check_bxco_support(smu); table_context->thermal_controller_type = powerplay_table->thermal_controller_type; @@ -822,6 +857,52 @@ static int arcturus_print_clk_levels(struct smu_context *smu, now) ? "*" : "")); break; + case SMU_VCLK: + ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); + ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, single_dpm_table->dpm_levels[i].value, + (clocks.num_levels == 1) ? "*" : + (arcturus_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + + case SMU_DCLK: + ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); + ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, single_dpm_table->dpm_levels[i].value, + (clocks.num_levels == 1) ? "*" : + (arcturus_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + case SMU_PCIE: gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); @@ -1113,7 +1194,10 @@ static int arcturus_get_fan_parameters(struct smu_context *smu) return 0; } -static int arcturus_get_power_limit(struct smu_context *smu) +static int arcturus_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit) { struct smu_11_0_powerplay_table *powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; @@ -1129,17 +1213,24 @@ static int arcturus_get_power_limit(struct smu_context *smu) power_limit = pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = smu->default_power_limit = power_limit; - if (smu->od_enabled) { - od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); + if (current_power_limit) + *current_power_limit = power_limit; + if (default_power_limit) + *default_power_limit = power_limit; - dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + if (max_power_limit) { + if (smu->od_enabled) { + od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); - power_limit *= (100 + od_percent); - power_limit /= 100; + dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + + power_limit *= (100 + od_percent); + power_limit /= 100; + } + + *max_power_limit = power_limit; } - smu->max_power_limit = power_limit; return 0; } @@ -2101,18 +2192,6 @@ static void arcturus_get_unique_id(struct smu_context *smu) sprintf(adev->serial, "%llx", id); } -static bool arcturus_is_baco_supported(struct smu_context *smu) -{ - struct amdgpu_device *adev = smu->adev; - uint32_t val; - - if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev)) - return false; - - val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); - return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; -} - static int arcturus_set_df_cstate(struct smu_context *smu, enum pp_df_cstate state) { @@ -2229,8 +2308,8 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -2240,7 +2319,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2269,6 +2348,9 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + arcturus_throttler_map); gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; @@ -2281,7 +2363,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static const struct pptable_funcs arcturus_ppt_funcs = { @@ -2347,7 +2429,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { .register_irq_handler = smu_v11_0_register_irq_handler, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, - .baco_is_support= arcturus_is_baco_supported, + .baco_is_support = smu_v11_0_baco_is_support, .baco_get_state = smu_v11_0_baco_get_state, .baco_set_state = smu_v11_0_baco_set_state, .baco_enter = smu_v11_0_baco_enter, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 0eaf86b5e698..1ba42b69ce74 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -80,10 +80,10 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), - MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), - MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), - MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), - MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), + MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), + MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), + MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), + MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), @@ -238,6 +238,28 @@ static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; +static const uint8_t navi1x_throttler_map[] = { + [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), + [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), + [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), + [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), + [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), + [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), + [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), + [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), + [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), + [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), + [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), + [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), + [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), + [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), + [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), + [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), +}; + + static bool is_asic_secure(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -340,19 +362,34 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, return 0; } -static int navi10_check_powerplay_table(struct smu_context *smu) +static void navi10_check_bxco_support(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; struct smu_baco_context *smu_baco = &smu->smu_baco; + struct amdgpu_device *adev = smu->adev; + uint32_t val; + + if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || + powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { + val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); + smu_baco->platform_support = + (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : + false; + } +} + +static int navi10_check_powerplay_table(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) smu->dc_controlled_by_gpio = true; - if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || - powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) - smu_baco->platform_support = true; + navi10_check_bxco_support(smu); table_context->thermal_controller_type = powerplay_table->thermal_controller_type; @@ -431,30 +468,6 @@ static int navi10_store_powerplay_table(struct smu_context *smu) return 0; } -static int navi10_set_mp1_state(struct smu_context *smu, - enum pp_mp1_state mp1_state) -{ - struct amdgpu_device *adev = smu->adev; - uint32_t mp1_fw_flags; - int ret = 0; - - ret = smu_cmn_set_mp1_state(smu, mp1_state); - if (ret) - return ret; - - if (mp1_state == PP_MP1_STATE_UNLOAD) { - mp1_fw_flags = RREG32_PCIE(MP1_Public | - (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); - - mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK; - - WREG32_PCIE(MP1_Public | - (smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags); - } - - return 0; -} - static int navi10_setup_pptable(struct smu_context *smu) { int ret = 0; @@ -505,7 +518,7 @@ static int navi10_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -1273,6 +1286,8 @@ static int navi10_print_clk_levels(struct smu_context *smu, case SMU_MCLK: case SMU_UCLK: case SMU_FCLK: + case SMU_VCLK: + case SMU_DCLK: case SMU_DCEFCLK: ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); if (ret) @@ -2121,7 +2136,10 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, return ret; } -static int navi10_get_power_limit(struct smu_context *smu) +static int navi10_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit) { struct smu_11_0_powerplay_table *powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; @@ -2138,18 +2156,25 @@ static int navi10_get_power_limit(struct smu_context *smu) power_limit = pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = smu->default_power_limit = power_limit; - if (smu->od_enabled && - navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { - od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); + if (current_power_limit) + *current_power_limit = power_limit; + if (default_power_limit) + *default_power_limit = power_limit; - dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + if (max_power_limit) { + if (smu->od_enabled && + navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { + od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); - power_limit *= (100 + od_percent); - power_limit /= 100; + dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + + power_limit *= (100 + od_percent); + power_limit /= 100; + } + + *max_power_limit = power_limit; } - smu->max_power_limit = power_limit; return 0; } @@ -2240,16 +2265,27 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, return 0; } -static bool navi10_is_baco_supported(struct smu_context *smu) +static int navi10_baco_enter(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - uint32_t val; - if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) - return false; + if (adev->in_runpm) + return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); + else + return smu_v11_0_baco_enter(smu); +} - val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); - return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; +static int navi10_baco_exit(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + if (adev->in_runpm) { + /* Wait for PMFW handling for the Dstate change */ + msleep(10); + return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); + } else { + return smu_v11_0_baco_exit(smu); + } } static int navi10_set_default_od_settings(struct smu_context *smu) @@ -2627,8 +2663,8 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_legacy_t metrics; int ret = 0; @@ -2646,7 +2682,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2671,6 +2707,9 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + navi1x_throttler_map); gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; @@ -2681,17 +2720,27 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + if (metrics.CurrGfxVoltageOffset) + gpu_metrics->voltage_gfx = + (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; + if (metrics.CurrMemVidOffset) + gpu_metrics->voltage_mem = + (155000 - 625 * metrics.CurrMemVidOffset) / 100; + if (metrics.CurrSocVoltageOffset) + gpu_metrics->voltage_soc = + (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; + *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -2709,7 +2758,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2738,6 +2787,9 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + navi1x_throttler_map); gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; @@ -2746,17 +2798,27 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + if (metrics.CurrGfxVoltageOffset) + gpu_metrics->voltage_gfx = + (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; + if (metrics.CurrMemVidOffset) + gpu_metrics->voltage_mem = + (155000 - 625 * metrics.CurrMemVidOffset) / 100; + if (metrics.CurrSocVoltageOffset) + gpu_metrics->voltage_soc = + (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; + *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_NV12_legacy_t metrics; int ret = 0; @@ -2774,7 +2836,7 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2804,6 +2866,9 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + navi1x_throttler_map); gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; @@ -2814,17 +2879,27 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + if (metrics.CurrGfxVoltageOffset) + gpu_metrics->voltage_gfx = + (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; + if (metrics.CurrMemVidOffset) + gpu_metrics->voltage_mem = + (155000 - 625 * metrics.CurrMemVidOffset) / 100; + if (metrics.CurrSocVoltageOffset) + gpu_metrics->voltage_soc = + (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; + *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_NV12_t metrics; int ret = 0; @@ -2842,7 +2917,7 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2876,6 +2951,9 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + navi1x_throttler_map); gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; @@ -2884,9 +2962,19 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + if (metrics.CurrGfxVoltageOffset) + gpu_metrics->voltage_gfx = + (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; + if (metrics.CurrMemVidOffset) + gpu_metrics->voltage_mem = + (155000 - 625 * metrics.CurrMemVidOffset) / 100; + if (metrics.CurrSocVoltageOffset) + gpu_metrics->voltage_soc = + (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; + *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, @@ -3047,11 +3135,11 @@ static const struct pptable_funcs navi10_ppt_funcs = { .register_irq_handler = smu_v11_0_register_irq_handler, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, - .baco_is_support= navi10_is_baco_supported, + .baco_is_support = smu_v11_0_baco_is_support, .baco_get_state = smu_v11_0_baco_get_state, .baco_set_state = smu_v11_0_baco_set_state, - .baco_enter = smu_v11_0_baco_enter, - .baco_exit = smu_v11_0_baco_exit, + .baco_enter = navi10_baco_enter, + .baco_exit = navi10_baco_exit, .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, .set_default_od_settings = navi10_set_default_od_settings, @@ -3067,7 +3155,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { .get_fan_parameters = navi10_get_fan_parameters, .post_init = navi10_post_smu_init, .interrupt_work = smu_v11_0_interrupt_work, - .set_mp1_state = navi10_set_mp1_state, + .set_mp1_state = smu_cmn_set_mp1_state, }; void navi10_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b124a5e40dd6..c751f717a0da 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -73,6 +73,21 @@ #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 +#define GET_PPTABLE_MEMBER(field, member) do {\ + if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\ + (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ + else\ + (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ +} while(0) + +static int get_table_size(struct smu_context *smu) +{ + if (smu->adev->asic_type == CHIP_BEIGE_GOBY) + return sizeof(PPTable_beige_goby_t); + else + return sizeof(PPTable_t); +} + static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), @@ -224,6 +239,27 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; +static const uint8_t sienna_cichlid_throttler_map[] = { + [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), + [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), + [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), + [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), + [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), + [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), + [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), + [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), + [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), + [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), + [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), + [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), + [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), + [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), + [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), + [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), +}; + static int sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) @@ -302,25 +338,40 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, if (smu->dc_controlled_by_gpio) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); - if (amdgpu_aspm == 1) + if (amdgpu_aspm) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); return 0; } +static void sienna_cichlid_check_bxco_support(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_7_powerplay_table *powerplay_table = + table_context->power_play_table; + struct smu_baco_context *smu_baco = &smu->smu_baco; + struct amdgpu_device *adev = smu->adev; + uint32_t val; + + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || + powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) { + val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); + smu_baco->platform_support = + (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : + false; + } +} + static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; - struct smu_baco_context *smu_baco = &smu->smu_baco; if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) smu->dc_controlled_by_gpio = true; - if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || - powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) - smu_baco->platform_support = true; + sienna_cichlid_check_bxco_support(smu); table_context->thermal_controller_type = powerplay_table->thermal_controller_type; @@ -336,10 +387,9 @@ static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) { - struct smu_table_context *table_context = &smu->smu_table; - PPTable_t *smc_pptable = table_context->driver_pptable; struct atom_smc_dpm_info_v4_9 *smc_dpm_table; int index, ret; + I2cControllerConfig_t *table_member; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, smc_dpm_info); @@ -348,9 +398,9 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) (uint8_t **)&smc_dpm_table); if (ret) return ret; - - memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, - sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); + GET_PPTABLE_MEMBER(I2cControllers, &table_member); + memcpy(table_member, smc_dpm_table->I2cControllers, + sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); return 0; } @@ -360,9 +410,11 @@ static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) struct smu_table_context *table_context = &smu->smu_table; struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; + int table_size; + table_size = get_table_size(smu); memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, - sizeof(PPTable_t)); + table_size); return 0; } @@ -394,9 +446,11 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int table_size; - SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + table_size = get_table_size(smu); + SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), @@ -416,7 +470,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -572,13 +626,14 @@ static int sienna_cichlid_init_smc_tables(struct smu_context *smu) static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - PPTable_t *driver_ppt = smu->smu_table.driver_pptable; struct smu_11_0_dpm_table *dpm_table; struct amdgpu_device *adev = smu->adev; int ret = 0; + DpmDescriptor_t *table_member; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_SOCCLK, @@ -586,7 +641,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; + !table_member[PPCLK_SOCCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; @@ -604,7 +659,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; + !table_member[PPCLK_GFXCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; @@ -622,7 +677,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; + !table_member[PPCLK_UCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; @@ -640,7 +695,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; + !table_member[PPCLK_FCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; @@ -658,7 +713,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete; + !table_member[PPCLK_VCLK_0].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; @@ -677,7 +732,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete; + !table_member[PPCLK_VCLK_1].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = @@ -697,7 +752,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete; + !table_member[PPCLK_DCLK_0].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; @@ -716,7 +771,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete; + !table_member[PPCLK_DCLK_1].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = @@ -736,7 +791,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; + !table_member[PPCLK_DCEFCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; @@ -754,7 +809,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; + !table_member[PPCLK_PIXCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; @@ -772,7 +827,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; + !table_member[PPCLK_DISPCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; @@ -790,7 +845,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; + !table_member[PPCLK_PHYCLK].SnapToDiscrete; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; @@ -911,14 +966,15 @@ static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) { - PPTable_t *pptable = smu->smu_table.driver_pptable; DpmDescriptor_t *dpm_desc = NULL; + DpmDescriptor_t *table_member; uint32_t clk_index = 0; + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); clk_index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_CLK, clk_type); - dpm_desc = &pptable->DpmDescriptor[clk_index]; + dpm_desc = &table_member[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ return dpm_desc->SnapToDiscrete == 0; @@ -947,7 +1003,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, struct smu_table_context *table_context = &smu->smu_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; - PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; + uint16_t *table_member; + struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; @@ -966,6 +1023,10 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, case SMU_MCLK: case SMU_UCLK: case SMU_FCLK: + case SMU_VCLK: + case SMU_VCLK1: + case SMU_DCLK: + case SMU_DCLK1: case SMU_DCEFCLK: ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); if (ret) @@ -1016,6 +1077,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, case SMU_PCIE: gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); + GET_PPTABLE_MEMBER(LclkFreq, &table_member); for (i = 0; i < NUM_LINK_LEVELS; i++) size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : @@ -1028,7 +1090,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", - pptable->LclkFreq[i], + table_member[i], (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? "*" : ""); @@ -1275,9 +1337,10 @@ static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu, static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) { - PPTable_t *pptable = smu->smu_table.driver_pptable; + uint16_t *table_member; - smu->fan_max_rpm = pptable->FanMaximumRpm; + GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); + smu->fan_max_rpm = *table_member; return 0; } @@ -1568,8 +1631,7 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu, void *data, uint32_t *size) { int ret = 0; - struct smu_table_context *table_context = &smu->smu_table; - PPTable_t *pptable = table_context->driver_pptable; + uint16_t *temp; if(!data || !size) return -EINVAL; @@ -1577,7 +1639,8 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu, mutex_lock(&smu->sensor_lock); switch (sensor) { case AMDGPU_PP_SENSOR_MAX_FAN_RPM: - *(uint32_t *)data = pptable->FanMaximumRpm; + GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); + *(uint16_t *)data = *temp; *size = 4; break; case AMDGPU_PP_SENSOR_MEM_LOAD: @@ -1645,14 +1708,16 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t uint16_t *dpm_levels = NULL; uint16_t i = 0; struct smu_table_context *table_context = &smu->smu_table; - PPTable_t *driver_ppt = NULL; + DpmDescriptor_t *table_member1; + uint16_t *table_member2; if (!clocks_in_khz || !num_states || !table_context->driver_pptable) return -EINVAL; - driver_ppt = table_context->driver_pptable; - num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; - dpm_levels = driver_ppt->FreqTableUclk; + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); + num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; + GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); + dpm_levels = table_member2; if (num_discrete_levels == 0 || dpm_levels == NULL) return -EINVAL; @@ -1674,25 +1739,29 @@ static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, struct smu_table_context *table_context = &smu->smu_table; struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; - PPTable_t *pptable = smu->smu_table.driver_pptable; + uint16_t *table_member; + uint16_t temp_edge, temp_hotspot, temp_mem; if (!range) return -EINVAL; memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); - range->max = pptable->TemperatureLimit[TEMP_EDGE] * + GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); + temp_edge = table_member[TEMP_EDGE]; + temp_hotspot = table_member[TEMP_HOTSPOT]; + temp_mem = table_member[TEMP_MEM]; + + range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; - range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * + range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; - range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] * - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; - range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; - range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] * - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; - range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* + range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; return 0; @@ -1722,33 +1791,39 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context return ret; } -static int sienna_cichlid_get_power_limit(struct smu_context *smu) +static int sienna_cichlid_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit) { struct smu_11_0_7_powerplay_table *powerplay_table = (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; - PPTable_t *pptable = smu->smu_table.driver_pptable; uint32_t power_limit, od_percent; + uint16_t *table_member; + + GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { - /* the last hope to figure out the ppt limit */ - if (!pptable) { - dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); - return -EINVAL; - } power_limit = - pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; + table_member[PPT_THROTTLER_PPT0]; } - smu->current_power_limit = smu->default_power_limit = power_limit; - if (smu->od_enabled) { - od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); + if (current_power_limit) + *current_power_limit = power_limit; + if (default_power_limit) + *default_power_limit = power_limit; - dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + if (max_power_limit) { + if (smu->od_enabled) { + od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); - power_limit *= (100 + od_percent); - power_limit /= 100; + dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); + + power_limit *= (100 + od_percent); + power_limit /= 100; + } + *max_power_limit = power_limit; } - smu->max_power_limit = power_limit; return 0; } @@ -1758,36 +1833,39 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, uint32_t pcie_width_cap) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - PPTable_t *pptable = smu->smu_table.driver_pptable; + uint32_t smu_pcie_arg; + uint8_t *table_member1, *table_member2; int ret, i; + GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); + GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); + /* lclk dpm table setup */ for (i = 0; i < MAX_PCIE_CONF; i++) { - dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; - dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; + dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; + dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; } for (i = 0; i < NUM_LINK_LEVELS; i++) { smu_pcie_arg = (i << 16) | - ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? - (pptable->PcieGenSpeed[i] << 8) : - (pcie_gen_cap << 8)) | - ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? - pptable->PcieLaneCount[i] : - pcie_width_cap); + ((table_member1[i] <= pcie_gen_cap) ? + (table_member1[i] << 8) : + (pcie_gen_cap << 8)) | + ((table_member2[i] <= pcie_width_cap) ? + table_member2[i] : + pcie_width_cap); ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_OverridePcieParameters, - smu_pcie_arg, - NULL); - + SMU_MSG_OverridePcieParameters, + smu_pcie_arg, + NULL); if (ret) return ret; - if (pptable->PcieGenSpeed[i] > pcie_gen_cap) + if (table_member1[i] > pcie_gen_cap) dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; - if (pptable->PcieLaneCount[i] > pcie_width_cap) + if (table_member2[i] > pcie_width_cap) dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; } @@ -2052,16 +2130,27 @@ static int sienna_cichlid_run_btc(struct smu_context *smu) return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); } -static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) +static int sienna_cichlid_baco_enter(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - uint32_t val; - if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) - return false; + if (adev->in_runpm) + return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); + else + return smu_v11_0_baco_enter(smu); +} - val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); - return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; +static int sienna_cichlid_baco_exit(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + if (adev->in_runpm) { + /* Wait for PMFW handling for the Dstate change */ + msleep(10); + return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); + } else { + return smu_v11_0_baco_exit(smu); + } } static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) @@ -2086,12 +2175,646 @@ static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) return val != 0x0; } +static void beige_goby_dump_pptable(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + PPTable_beige_goby_t *pptable = table_context->driver_pptable; + int i; + + dev_info(smu->adev->dev, "Dumped PPTable:\n"); + + dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); + dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); + dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); + + for (i = 0; i < PPT_THROTTLER_COUNT; i++) { + dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); + dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); + dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); + dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); + } + + for (i = 0; i < TDC_THROTTLER_COUNT; i++) { + dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); + dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); + } + + for (i = 0; i < TEMP_COUNT; i++) { + dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); + } + + dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); + dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); + dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); + dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); + dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); + + dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); + for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { + dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); + dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); + } + dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); + + dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); + + dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); + dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); + dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); + dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); + + dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); + + dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); + + dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); + dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); + dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); + dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); + + dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); + dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); + + dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); + dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); + dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); + dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); + dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); + dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); + dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); + dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); + + dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, + pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, + pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, + pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, + pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, + pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, + pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, + pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, + pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, + pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_UCLK].Padding, + pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, + pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, + pptable->DpmDescriptor[PPCLK_UCLK].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, + pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_FCLK].Padding, + pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, + pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, + pptable->DpmDescriptor[PPCLK_FCLK].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, + pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, + pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, + pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, + pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, + pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, + pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, + pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, + pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, + pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, + pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, + pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, + pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); + + dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" + " .VoltageMode = 0x%02x\n" + " .SnapToDiscrete = 0x%02x\n" + " .NumDiscreteLevels = 0x%02x\n" + " .padding = 0x%02x\n" + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" + " .SsFmin = 0x%04x\n" + " .Padding_16 = 0x%04x\n", + pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, + pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, + pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, + pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, + pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, + pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, + pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, + pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); + + dev_info(smu->adev->dev, "FreqTableGfx\n"); + for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); + + dev_info(smu->adev->dev, "FreqTableVclk\n"); + for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); + + dev_info(smu->adev->dev, "FreqTableDclk\n"); + for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); + + dev_info(smu->adev->dev, "FreqTableSocclk\n"); + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); + + dev_info(smu->adev->dev, "FreqTableUclk\n"); + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); + + dev_info(smu->adev->dev, "FreqTableFclk\n"); + for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); + + dev_info(smu->adev->dev, "DcModeMaxFreq\n"); + dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); + dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); + dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); + dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); + dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); + dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); + dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); + dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); + + dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); + + dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); + dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); + + dev_info(smu->adev->dev, "Mp0clkFreq\n"); + for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); + + dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); + for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); + + dev_info(smu->adev->dev, "MemVddciVoltage\n"); + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); + + dev_info(smu->adev->dev, "MemMvddVoltage\n"); + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); + + dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); + dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); + dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); + dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); + dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); + + dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); + + dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); + dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); + dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); + dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); + dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); + dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); + dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); + dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); + dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); + dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); + dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); + + dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); + dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); + dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); + dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); + dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); + dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); + + dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); + dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); + dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); + dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); + dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); + + dev_info(smu->adev->dev, "FlopsPerByteTable\n"); + for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); + + dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); + dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); + dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); + dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); + + dev_info(smu->adev->dev, "UclkDpmPstates\n"); + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); + + dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); + dev_info(smu->adev->dev, " .Fmin = 0x%x\n", + pptable->UclkDpmSrcFreqRange.Fmin); + dev_info(smu->adev->dev, " .Fmax = 0x%x\n", + pptable->UclkDpmSrcFreqRange.Fmax); + dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); + dev_info(smu->adev->dev, " .Fmin = 0x%x\n", + pptable->UclkDpmTargFreqRange.Fmin); + dev_info(smu->adev->dev, " .Fmax = 0x%x\n", + pptable->UclkDpmTargFreqRange.Fmax); + dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); + dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); + + dev_info(smu->adev->dev, "PcieGenSpeed\n"); + for (i = 0; i < NUM_LINK_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); + + dev_info(smu->adev->dev, "PcieLaneCount\n"); + for (i = 0; i < NUM_LINK_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); + + dev_info(smu->adev->dev, "LclkFreq\n"); + for (i = 0; i < NUM_LINK_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); + + dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); + dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); + + dev_info(smu->adev->dev, "FanGain\n"); + for (i = 0; i < TEMP_COUNT; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); + + dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); + dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); + dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); + dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); + dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); + dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); + dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); + dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); + dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); + dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); + dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); + dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); + + dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); + dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); + dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); + dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); + + dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); + dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); + dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); + + dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); + dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); + dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->dBtcGbGfxPll.a, + pptable->dBtcGbGfxPll.b, + pptable->dBtcGbGfxPll.c); + dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->dBtcGbGfxDfll.a, + pptable->dBtcGbGfxDfll.b, + pptable->dBtcGbGfxDfll.c); + dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->dBtcGbSoc.a, + pptable->dBtcGbSoc.b, + pptable->dBtcGbSoc.c); + dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", + pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, + pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); + dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", + pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, + pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); + + dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); + for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { + dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", + i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); + dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", + i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); + } + + dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); + dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); + + dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); + + dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); + dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); + dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); + + dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); + dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); + + dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); + dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); + + dev_info(smu->adev->dev, "XgmiDpmPstates\n"); + for (i = 0; i < NUM_XGMI_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); + dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); + dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); + + dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); + dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->ReservedEquation0.a, + pptable->ReservedEquation0.b, + pptable->ReservedEquation0.c); + dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->ReservedEquation1.a, + pptable->ReservedEquation1.b, + pptable->ReservedEquation1.c); + dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->ReservedEquation2.a, + pptable->ReservedEquation2.b, + pptable->ReservedEquation2.c); + dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", + pptable->ReservedEquation3.a, + pptable->ReservedEquation3.b, + pptable->ReservedEquation3.c); + + dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); + dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); + dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); + dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); + dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); + dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); + dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); + dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); + + dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); + dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); + dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); + dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); + dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); + dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); + + for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { + dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); + dev_info(smu->adev->dev, " .Enabled = 0x%x\n", + pptable->I2cControllers[i].Enabled); + dev_info(smu->adev->dev, " .Speed = 0x%x\n", + pptable->I2cControllers[i].Speed); + dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", + pptable->I2cControllers[i].SlaveAddress); + dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", + pptable->I2cControllers[i].ControllerPort); + dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", + pptable->I2cControllers[i].ControllerName); + dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", + pptable->I2cControllers[i].ThermalThrotter); + dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", + pptable->I2cControllers[i].I2cProtocol); + dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", + pptable->I2cControllers[i].PaddingConfig); + } + + dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); + dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); + dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); + dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); + + dev_info(smu->adev->dev, "Board Parameters:\n"); + dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); + dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); + dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); + dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); + dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); + dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); + dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); + dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); + + dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); + dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); + dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); + + dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); + dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); + dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); + + dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); + dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); + dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); + + dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); + dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); + dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); + + dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); + + dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); + dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); + dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); + dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); + dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); + dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); + dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); + dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); + dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); + dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); + dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); + dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); + dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); + dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); + dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); + dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); + + dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); + dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); + dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); + + dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); + dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); + dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); + + dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); + dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); + + dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); + dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); + dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); + + dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); + dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); + dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); + dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); + dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); + + dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); + dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); + + dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); + dev_info(smu->adev->dev, "XgmiLinkWidth\n"); + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); + dev_info(smu->adev->dev, "XgmiFclkFreq\n"); + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); + dev_info(smu->adev->dev, "XgmiSocVoltage\n"); + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); + + dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); + dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); + dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); + dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); + + dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); + dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); + dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); + dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); + dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); + dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); + dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); + dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); + dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); + dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); + dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); + + dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); + dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); + dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); + dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); + dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); + dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); + dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); + dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); +} + static void sienna_cichlid_dump_pptable(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; PPTable_t *pptable = table_context->driver_pptable; int i; + if (smu->adev->asic_type == CHIP_BEIGE_GOBY) { + beige_goby_dump_pptable(smu); + return; + } + dev_info(smu->adev->dev, "Dumped PPTable:\n"); dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); @@ -2950,8 +3673,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetricsExternal_t metrics_external; SmuMetrics_t *metrics = &(metrics_external.SmuMetrics); @@ -2965,7 +3688,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics->TemperatureEdge; gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; @@ -3000,6 +3723,9 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; gpu_metrics->throttle_status = metrics->ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics->ThrottlerStatus, + sienna_cichlid_throttler_map); gpu_metrics->current_fan_speed = metrics->CurrFanSpeed; @@ -3022,7 +3748,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) @@ -3202,11 +3928,11 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .register_irq_handler = smu_v11_0_register_irq_handler, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, - .baco_is_support= sienna_cichlid_is_baco_supported, + .baco_is_support = smu_v11_0_baco_is_support, .baco_get_state = smu_v11_0_baco_get_state, .baco_set_state = smu_v11_0_baco_set_state, - .baco_enter = smu_v11_0_baco_enter, - .baco_exit = smu_v11_0_baco_exit, + .baco_enter = sienna_cichlid_baco_enter, + .baco_exit = sienna_cichlid_baco_exit, .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, .mode1_reset = smu_v11_0_mode1_reset, .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 6274cae4a065..388c5cb5c647 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -63,6 +63,7 @@ MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); #define SMU11_VOLTAGE_SCALE 4 @@ -115,6 +116,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu) case CHIP_DIMGREY_CAVEFISH: chip_name = "dimgrey_cavefish"; break; + case CHIP_BEIGE_GOBY: + chip_name = "beige_goby"; + break; default: dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type); return -EINVAL; @@ -259,6 +263,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) case CHIP_DIMGREY_CAVEFISH: smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; break; + case CHIP_BEIGE_GOBY: + smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; + break; default: dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; @@ -729,7 +736,7 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) * display num currently */ if (adev->asic_type >= CHIP_NAVY_FLOUNDER && - adev->asic_type <= CHIP_DIMGREY_CAVEFISH) + adev->asic_type <= CHIP_BEIGE_GOBY) return 0; return smu_cmn_send_smc_msg_with_param(smu, @@ -1121,6 +1128,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: + case CHIP_BEIGE_GOBY: case CHIP_VANGOGH: if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) return 0; @@ -1466,7 +1474,8 @@ int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); } -static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq) +int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, + enum smu_v11_0_baco_seq baco_seq) { return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); } @@ -1475,7 +1484,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu) { struct smu_baco_context *smu_baco = &smu->smu_baco; - if (!smu_baco->platform_support) + if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support) return false; /* Arcturus does not support this bit mask */ @@ -1531,7 +1540,8 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) NULL); break; default: - if (!ras || !ras->supported || adev->gmc.xgmi.pending_reset) { + if (!ras || !adev->ras_enabled || + adev->gmc.xgmi.pending_reset) { if (adev->asic_type == CHIP_ARCTURUS) { data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); data |= 0x80000000; @@ -1569,16 +1579,8 @@ out: int smu_v11_0_baco_enter(struct smu_context *smu) { - struct amdgpu_device *adev = smu->adev; int ret = 0; - /* Arcturus does not need this audio workaround */ - if (adev->asic_type != CHIP_ARCTURUS) { - ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); - if (ret) - return ret; - } - ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 77f532a49e37..18681dc458da 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -190,6 +190,20 @@ static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; +static const uint8_t vangogh_throttler_map[] = { + [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), + [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), + [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), + [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), + [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), + [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), + [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), + [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), + [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), + [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), +}; + static int vangogh_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -226,7 +240,7 @@ static int vangogh_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err1_out; @@ -1632,8 +1646,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v2_2 *gpu_metrics = + (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; SmuMetrics_legacy_t metrics; int ret = 0; @@ -1641,7 +1655,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1674,20 +1688,23 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + vangogh_throttler_map); gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v2_1); + return sizeof(struct gpu_metrics_v2_2); } static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v2_2 *gpu_metrics = + (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -1695,7 +1712,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; gpu_metrics->temperature_soc = metrics.Current.SocTemperature; @@ -1735,12 +1752,15 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, + vangogh_throttler_map); gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v2_1); + return sizeof(struct gpu_metrics_v2_2); } static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, @@ -2051,7 +2071,10 @@ static int vangogh_mode2_reset(struct smu_context *smu) return vangogh_mode_reset(smu, SMU_RESET_MODE_2); } -static int vangogh_get_power_limit(struct smu_context *smu) +static int vangogh_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit) { struct smu_11_5_power_context *power_context = smu->smu_power.power_context; @@ -2067,8 +2090,12 @@ static int vangogh_get_power_limit(struct smu_context *smu) return ret; } /* convert from milliwatt to watt */ - smu->current_power_limit = smu->default_power_limit = ppt_limit / 1000; - smu->max_power_limit = 29; + if (current_power_limit) + *current_power_limit = ppt_limit / 1000; + if (default_power_limit) + *default_power_limit = ppt_limit / 1000; + if (max_power_limit) + *max_power_limit = 29; ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); if (ret) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index f43b4c623685..9a9c24a6ec35 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -109,6 +109,8 @@ static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { CLK_MAP(SOCCLK, CLOCK_SOCCLK), CLK_MAP(UCLK, CLOCK_FCLK), CLK_MAP(MCLK, CLOCK_FCLK), + CLK_MAP(VCLK, CLOCK_VCLK), + CLK_MAP(DCLK, CLOCK_DCLK), }; static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { @@ -126,6 +128,22 @@ static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; +static const uint8_t renoir_throttler_map[] = { + [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), + [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), + [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), + [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), + [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), + [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), + [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), + [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), + [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT), + [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT), + [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT), + [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT), +}; + static int renoir_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -151,7 +169,7 @@ static int renoir_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) goto err3_out; @@ -202,6 +220,17 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type return -EINVAL; *freq = clk_table->FClocks[dpm_level].Freq; break; + case SMU_VCLK: + if (dpm_level >= NUM_VCN_DPM_LEVELS) + return -EINVAL; + *freq = clk_table->VClocks[dpm_level].Freq; + break; + case SMU_DCLK: + if (dpm_level >= NUM_VCN_DPM_LEVELS) + return -EINVAL; + *freq = clk_table->DClocks[dpm_level].Freq; + break; + default: return -EINVAL; } @@ -532,6 +561,14 @@ static int renoir_print_clk_levels(struct smu_context *smu, count = NUM_FCLK_DPM_LEVELS; cur_value = metrics.ClockFrequency[CLOCK_FCLK]; break; + case SMU_VCLK: + count = NUM_VCN_DPM_LEVELS; + cur_value = metrics.ClockFrequency[CLOCK_VCLK]; + break; + case SMU_DCLK: + count = NUM_VCN_DPM_LEVELS; + cur_value = metrics.ClockFrequency[CLOCK_DCLK]; + break; default: break; } @@ -543,6 +580,8 @@ static int renoir_print_clk_levels(struct smu_context *smu, case SMU_MCLK: case SMU_DCEFCLK: case SMU_FCLK: + case SMU_VCLK: + case SMU_DCLK: for (i = 0; i < count; i++) { ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); if (ret) @@ -730,6 +769,16 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; } + for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { + clock_table->VClocks[i].Freq = table->VClocks[i].Freq; + clock_table->VClocks[i].Vol = table->VClocks[i].Vol; + } + + for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { + clock_table->DClocks[i].Freq = table->DClocks[i].Freq; + clock_table->DClocks[i].Vol = table->DClocks[i].Vol; + } + return 0; } @@ -1131,6 +1180,28 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu, case METRICS_VOLTAGE_VDDSOC: *value = metrics->Voltage[1]; break; + case METRICS_SS_APU_SHARE: + /* return the percentage of APU power with respect to APU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if (metrics->StapmOriginalLimit > 0) + *value = (metrics->ApuPower * 100) / metrics->StapmOriginalLimit; + else + *value = 0; + break; + case METRICS_SS_DGPU_SHARE: + /* return the percentage of dGPU power with respect to dGPU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if ((metrics->dGpuPower > 0) && + (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)) + *value = (metrics->dGpuPower * 100) / + (metrics->StapmCurrentLimit - metrics->StapmOriginalLimit); + else + *value = 0; + break; default: *value = UINT_MAX; break; @@ -1202,6 +1273,18 @@ static int renoir_read_sensor(struct smu_context *smu, (uint32_t *)data); *size = 4; break; + case AMDGPU_PP_SENSOR_SS_APU_SHARE: + ret = renoir_get_smu_metrics_data(smu, + METRICS_SS_APU_SHARE, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: + ret = renoir_get_smu_metrics_data(smu, + METRICS_SS_DGPU_SHARE, + (uint32_t *)data); + *size = 4; + break; default: ret = -EOPNOTSUPP; break; @@ -1231,8 +1314,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v2_2 *gpu_metrics = + (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int ret = 0; @@ -1240,7 +1323,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1278,6 +1361,9 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + renoir_throttler_map); gpu_metrics->fan_pwm = metrics.FanPwm; @@ -1285,7 +1371,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v2_1); + return sizeof(struct gpu_metrics_v2_2); } static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile index 652b4e554378..9b3a8503f5cd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -SMU13_MGR = smu_v13_0.o aldebaran_ppt.o +SMU13_MGR = smu_v13_0.o aldebaran_ppt.o smu_v13_0_1.o yellow_carp_ppt.o AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR)) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index dcbe3a72da09..9316a726195c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -78,7 +78,11 @@ #define smnPCIE_ESM_CTRL 0x111003D0 -#define CLOCK_VALID (1 << 31) +static const struct smu_temperature_range smu13_thermal_policy[] = +{ + {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, + { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, +}; static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), @@ -187,6 +191,20 @@ static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { TAB_MAP(I2C_COMMANDS), }; +static const uint8_t aldebaran_throttler_map[] = { + [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), + [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), + [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), + [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), + [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), + [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), + [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), + [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), + [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), + [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), +}; + static int aldebaran_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -209,7 +227,7 @@ static int aldebaran_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { kfree(smu_table->metrics_table); @@ -351,13 +369,6 @@ static int aldebaran_check_powerplay_table(struct smu_context *smu) struct smu_table_context *table_context = &smu->smu_table; struct smu_13_0_powerplay_table *powerplay_table = table_context->power_play_table; - struct smu_baco_context *smu_baco = &smu->smu_baco; - - mutex_lock(&smu_baco->mutex); - if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO || - powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO) - smu_baco->platform_support = true; - mutex_unlock(&smu_baco->mutex); table_context->thermal_controller_type = powerplay_table->thermal_controller_type; @@ -455,12 +466,18 @@ static int aldebaran_populate_umd_state_clk(struct smu_context *smu) pstate_table->gfxclk_pstate.min = gfx_table->min; pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.curr.min = gfx_table->min; + pstate_table->gfxclk_pstate.curr.max = gfx_table->max; pstate_table->uclk_pstate.min = mem_table->min; pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.curr.min = mem_table->min; + pstate_table->uclk_pstate.curr.max = mem_table->max; pstate_table->socclk_pstate.min = soc_table->min; pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.curr.min = soc_table->min; + pstate_table->socclk_pstate.curr.max = soc_table->max; if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && @@ -507,6 +524,16 @@ static int aldebaran_freqs_in_same_level(int32_t frequency1, return (abs(frequency1 - frequency2) <= EPSILON); } +static bool aldebaran_is_primary(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) + return adev->smuio.funcs->get_die_id(adev) == 0; + + return true; +} + static int aldebaran_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) @@ -560,7 +587,10 @@ static int aldebaran_get_smu_metrics_data(struct smu_context *smu, *value = metrics->AverageUclkActivity; break; case METRICS_AVERAGE_SOCKETPOWER: - *value = metrics->AverageSocketPower << 8; + /* Valid power data is available only from primary die */ + *value = aldebaran_is_primary(smu) ? + metrics->AverageSocketPower << 8 : + 0; break; case METRICS_TEMPERATURE_EDGE: *value = metrics->TemperatureEdge * @@ -669,6 +699,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, { int i, now, size = 0; int ret = 0; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct pp_clock_levels_with_latency clocks; struct smu_13_0_dpm_table *single_dpm_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -703,12 +734,8 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, display_levels = clocks.num_levels; - min_clk = smu->gfx_actual_hard_min_freq & CLOCK_VALID ? - smu->gfx_actual_hard_min_freq & ~CLOCK_VALID : - single_dpm_table->dpm_levels[0].value; - max_clk = smu->gfx_actual_soft_max_freq & CLOCK_VALID ? - smu->gfx_actual_soft_max_freq & ~CLOCK_VALID : - single_dpm_table->dpm_levels[1].value; + min_clk = pstate_table->gfxclk_pstate.curr.min; + max_clk = pstate_table->gfxclk_pstate.curr.max; freq_values[0] = min_clk; freq_values[1] = max_clk; @@ -815,6 +842,52 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, now) ? "*" : "")); break; + case SMU_VCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, single_dpm_table->dpm_levels[i].value, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + + case SMU_DCLK: + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); + return ret; + } + + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); + if (ret) { + dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); + return ret; + } + + for (i = 0; i < single_dpm_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, single_dpm_table->dpm_levels[i].value, + (clocks.num_levels == 1) ? "*" : + (aldebaran_freqs_in_same_level( + clocks.data[i].clocks_in_khz / 1000, + now) ? "*" : "")); + break; + default: break; } @@ -1086,7 +1159,10 @@ static int aldebaran_read_sensor(struct smu_context *smu, return ret; } -static int aldebaran_get_power_limit(struct smu_context *smu) +static int aldebaran_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit) { PPTable_t *pptable = smu->smu_table.driver_pptable; uint32_t power_limit = 0; @@ -1095,24 +1171,46 @@ static int aldebaran_get_power_limit(struct smu_context *smu) if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) return -EINVAL; - ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); + /* Valid power data is available only from primary die. + * For secondary die show the value as 0. + */ + if (aldebaran_is_primary(smu)) { + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, + &power_limit); - if (ret) { - /* the last hope to figure out the ppt limit */ - if (!pptable) { - dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); - return -EINVAL; + if (ret) { + /* the last hope to figure out the ppt limit */ + if (!pptable) { + dev_err(smu->adev->dev, + "Cannot get PPT limit due to pptable missing!"); + return -EINVAL; + } + power_limit = pptable->PptLimit; } - power_limit = pptable->PptLimit; } - smu->current_power_limit = smu->default_power_limit = power_limit; - if (pptable) - smu->max_power_limit = pptable->PptLimit; + if (current_power_limit) + *current_power_limit = power_limit; + if (default_power_limit) + *default_power_limit = power_limit; + + if (max_power_limit) { + if (pptable) + *max_power_limit = pptable->PptLimit; + } return 0; } +static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n) +{ + /* Power limit can be set only through primary die */ + if (aldebaran_is_primary(smu)) + return smu_v13_0_set_power_limit(smu, n); + + return -EINVAL; +} + static int aldebaran_system_features_control(struct smu_context *smu, bool enable) { int ret; @@ -1128,15 +1226,17 @@ static int aldebaran_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_13_0_dpm_table *gfx_table = + &dpm_context->dpm_tables.gfx_table; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; /* Disable determinism if switching to another mode */ - if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) - && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) + if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && + (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); - - /* Reset user min/max gfx clock */ - smu->gfx_actual_hard_min_freq = 0; - smu->gfx_actual_soft_max_freq = 0; + pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + } switch (level) { @@ -1163,6 +1263,7 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; uint32_t min_clk; uint32_t max_clk; @@ -1176,15 +1277,23 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, return -EINVAL; if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { - min_clk = max(min, dpm_context->dpm_tables.gfx_table.min); - max_clk = min(max, dpm_context->dpm_tables.gfx_table.max); - ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, - min_clk, max_clk); - - if (!ret) { - smu->gfx_actual_hard_min_freq = min_clk | CLOCK_VALID; - smu->gfx_actual_soft_max_freq = max_clk | CLOCK_VALID; + if (min >= max) { + dev_err(smu->adev->dev, + "Minimum GFX clk should be less than the maximum allowed clock\n"); + return -EINVAL; } + + if ((min == pstate_table->gfxclk_pstate.curr.min) && + (max == pstate_table->gfxclk_pstate.curr.max)) + return 0; + + ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, + min, max); + if (!ret) { + pstate_table->gfxclk_pstate.curr.min = min; + pstate_table->gfxclk_pstate.curr.max = max; + } + return ret; } @@ -1209,10 +1318,8 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, dev_err(adev->dev, "Failed to enable determinism at GFX clock %d MHz\n", max); } else { - smu->gfx_actual_hard_min_freq = - min_clk | CLOCK_VALID; - smu->gfx_actual_soft_max_freq = - max | CLOCK_VALID; + pstate_table->gfxclk_pstate.curr.min = min_clk; + pstate_table->gfxclk_pstate.curr.max = max; } } } @@ -1225,6 +1332,7 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; uint32_t min_clk; uint32_t max_clk; int ret = 0; @@ -1245,16 +1353,22 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ if (input[1] < dpm_context->dpm_tables.gfx_table.min) { dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", input[1], dpm_context->dpm_tables.gfx_table.min); + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; return -EINVAL; } - smu->gfx_actual_hard_min_freq = input[1]; + + pstate_table->gfxclk_pstate.custom.min = input[1]; } else if (input[0] == 1) { if (input[1] > dpm_context->dpm_tables.gfx_table.max) { dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", input[1], dpm_context->dpm_tables.gfx_table.max); + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; return -EINVAL; } - smu->gfx_actual_soft_max_freq = input[1]; + + pstate_table->gfxclk_pstate.custom.max = input[1]; } else { return -EINVAL; } @@ -1276,8 +1390,17 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ dev_err(smu->adev->dev, "Input parameter number not correct\n"); return -EINVAL; } else { - min_clk = smu->gfx_actual_hard_min_freq; - max_clk = smu->gfx_actual_soft_max_freq; + if (!pstate_table->gfxclk_pstate.custom.min) + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; + + if (!pstate_table->gfxclk_pstate.custom.max) + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; + + min_clk = pstate_table->gfxclk_pstate.custom.min; + max_clk = pstate_table->gfxclk_pstate.custom.max; + return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); } break; @@ -1290,10 +1413,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ static bool aldebaran_is_dpm_running(struct smu_context *smu) { - int ret = 0; + int ret; uint32_t feature_mask[2]; unsigned long feature_enabled; + ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); + if (ret) + return false; feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | ((uint64_t)feature_mask[1] << 32)); return !!(feature_enabled & SMC_DPM_FEATURE); @@ -1632,8 +1758,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_1 *gpu_metrics = - (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_3 *gpu_metrics = + (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; SmuMetrics_t metrics; int i, ret = 0; @@ -1643,7 +1769,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -1656,8 +1782,16 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; gpu_metrics->average_mm_activity = 0; - gpu_metrics->average_socket_power = metrics.AverageSocketPower; - gpu_metrics->energy_accumulator = 0; + /* Valid power data is available only from primary die */ + if (aldebaran_is_primary(smu)) { + gpu_metrics->average_socket_power = metrics.AverageSocketPower; + gpu_metrics->energy_accumulator = + (uint64_t)metrics.EnergyAcc64bitHigh << 32 | + metrics.EnergyAcc64bitLow; + } else { + gpu_metrics->average_socket_power = 0; + gpu_metrics->energy_accumulator = 0; + } gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; @@ -1672,6 +1806,9 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->indep_throttle_status = + smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, + aldebaran_throttler_map); gpu_metrics->current_fan_speed = 0; @@ -1688,9 +1825,12 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, for (i = 0; i < NUM_HBM_INSTANCES; i++) gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; + gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | + metrics.TimeStampLow; + *table = (void *)gpu_metrics; - return sizeof(struct gpu_metrics_v1_1); + return sizeof(struct gpu_metrics_v1_3); } static int aldebaran_mode2_reset(struct smu_context *smu) @@ -1779,10 +1919,22 @@ static int aldebaran_set_mp1_state(struct smu_context *smu, case PP_MP1_STATE_UNLOAD: return smu_cmn_set_mp1_state(smu, mp1_state); default: - return -EINVAL; + return 0; } +} - return 0; +static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, + uint32_t size) +{ + int ret = 0; + + /* message SMU to update the bad page number on SMUBUS */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); + if (ret) + dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", + __func__); + + return ret; } static const struct pptable_funcs aldebaran_ppt_funcs = { @@ -1821,7 +1973,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { .get_enabled_mask = smu_cmn_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, - .set_power_limit = smu_v13_0_set_power_limit, + .set_power_limit = aldebaran_set_power_limit, .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, .enable_thermal_alert = smu_v13_0_enable_thermal_alert, .disable_thermal_alert = smu_v13_0_disable_thermal_alert, @@ -1847,6 +1999,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { .wait_for_event = smu_v13_0_wait_for_event, .i2c_init = aldebaran_i2c_control_init, .i2c_fini = aldebaran_i2c_control_fini, + .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, }; void aldebaran_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 0864083e7435..a3dc7194aaf8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1626,6 +1626,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, sclk_max); if (ret) return ret; + + pstate_table->gfxclk_pstate.curr.min = sclk_min; + pstate_table->gfxclk_pstate.curr.max = sclk_max; } if (mclk_min && mclk_max) { @@ -1635,6 +1638,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, mclk_max); if (ret) return ret; + + pstate_table->uclk_pstate.curr.min = mclk_min; + pstate_table->uclk_pstate.curr.max = mclk_max; } if (socclk_min && socclk_max) { @@ -1644,6 +1650,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, socclk_max); if (ret) return ret; + + pstate_table->socclk_pstate.curr.min = socclk_min; + pstate_table->socclk_pstate.curr.max = socclk_max; } return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c new file mode 100644 index 000000000000..61917b49f2bf --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c @@ -0,0 +1,311 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +//#include + +#define SWSMU_CODE_LAYER_L3 + +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "smu_v13_0_1.h" +#include "soc15_common.h" +#include "smu_cmn.h" +#include "atomfirmware.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_atombios.h" +#include "atom.h" + +#include "asic_reg/mp/mp_13_0_1_offset.h" +#include "asic_reg/mp/mp_13_0_1_sh_mask.h" + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +int smu_v13_0_1_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags; + + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + + if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + +int smu_v13_0_1_check_fw_version(struct smu_context *smu) +{ + uint32_t if_version = 0xff, smu_version = 0xff; + uint16_t smu_major; + uint8_t smu_minor, smu_debug; + int ret = 0; + + ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); + if (ret) + return ret; + + smu_major = (smu_version >> 16) & 0xffff; + smu_minor = (smu_version >> 8) & 0xff; + smu_debug = (smu_version >> 0) & 0xff; + + switch (smu->adev->asic_type) { + case CHIP_YELLOW_CARP: + smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP; + break; + + default: + dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); + smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV; + break; + } + + dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n", + smu_version, smu_major, smu_minor, smu_debug); + + /* + * 1. if_version mismatch is not critical as our fw is designed + * to be backward compatible. + * 2. New fw usually brings some optimizations. But that's visible + * only on the paired driver. + * Considering above, we just leave user a warning message instead + * of halt driver loading. + */ + if (if_version != smu->smc_driver_if_version) { + dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " + "smu fw version = 0x%08x (%d.%d.%d)\n", + smu->smc_driver_if_version, if_version, + smu_version, smu_major, smu_minor, smu_debug); + dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); + } + + return ret; +} + +int smu_v13_0_1_fini_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + kfree(smu_table->clocks_table); + smu_table->clocks_table = NULL; + + kfree(smu_table->metrics_table); + smu_table->metrics_table = NULL; + + kfree(smu_table->watermarks_table); + smu_table->watermarks_table = NULL; + + return 0; +} + +static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev, + uint8_t clk_id, + uint8_t syspll_id, + uint32_t *clk_freq) +{ + struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + int ret, index; + + input.clk_id = clk_id; + input.syspll_id = syspll_id; + input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, + getsmuclockinfo); + + ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, + (uint32_t *)&input); + if (ret) + return -EINVAL; + + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; + *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; + + return 0; +} + +int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu) +{ + int ret, index; + uint16_t size; + uint8_t frev, crev; + struct atom_common_table_header *header; + struct atom_firmware_info_v3_4 *v_3_4; + struct atom_firmware_info_v3_3 *v_3_3; + struct atom_firmware_info_v3_1 *v_3_1; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); + + ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, + (uint8_t **)&header); + if (ret) + return ret; + + if (header->format_revision != 3) { + dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); + return -EINVAL; + } + + switch (header->content_revision) { + case 0: + case 1: + case 2: + v_3_1 = (struct atom_firmware_info_v3_1 *)header; + smu->smu_table.boot_values.revision = v_3_1->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; + break; + case 3: + v_3_3 = (struct atom_firmware_info_v3_3 *)header; + smu->smu_table.boot_values.revision = v_3_3->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; + break; + case 4: + default: + v_3_4 = (struct atom_firmware_info_v3_4 *)header; + smu->smu_table.boot_values.revision = v_3_4->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; + break; + } + + smu->smu_table.boot_values.format_revision = header->format_revision; + smu->smu_table.boot_values.content_revision = header->content_revision; + + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.socclk); + + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.dcefclk); + + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_ECLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.eclk); + + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_VCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.vclk); + + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL0_DCLK_ID, + (uint8_t)0, + &smu->smu_table.boot_values.dclk); + + if ((smu->smu_table.boot_values.format_revision == 3) && + (smu->smu_table.boot_values.content_revision >= 2)) + smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, + (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, + (uint8_t)SMU11_SYSPLL1_2_ID, + &smu->smu_table.boot_values.fclk); + + return 0; +} + +int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); +} + +int smu_v13_0_1_set_driver_table_location(struct smu_context *smu) +{ + struct smu_table *driver_table = &smu->smu_table.driver_table; + int ret = 0; + + if (!driver_table->mc_address) + return 0; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetDriverDramAddrHigh, + upper_32_bits(driver_table->mc_address), + NULL); + + if (ret) + return ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetDriverDramAddrLow, + lower_32_bits(driver_table->mc_address), + NULL); + + return ret; +} + +int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable) +{ + int ret = 0; + struct amdgpu_device *adev = smu->adev; + + switch (adev->asic_type) { + case CHIP_YELLOW_CARP: + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + if (enable) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); + else + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); + break; + default: + break; + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c new file mode 100644 index 000000000000..7664334d8144 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -0,0 +1,1244 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#define SWSMU_CODE_LAYER_L2 + +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "smu_v13_0_1.h" +#include "smu13_driver_if_yellow_carp.h" +#include "yellow_carp_ppt.h" +#include "smu_v13_0_1_ppsmc.h" +#include "smu_v13_0_1_pmfw.h" +#include "smu_cmn.h" + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define FEATURE_MASK(feature) (1ULL << feature) +#define SMC_DPM_FEATURE ( \ + FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ + FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ + FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ + FEATURE_MASK(FEATURE_GFX_DPM_BIT)) + +static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), + MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), + MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1), + MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), + MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), + MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), + MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), + MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), + MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), + MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), + MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), + MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), + MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), + MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), + MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), + MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), + MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), + MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), + MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), + MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), + MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), + MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), + MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), + MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), + MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), + MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), + MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), + MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), +}; + +static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = { + FEA_MAP(CCLK_DPM), + FEA_MAP(FAN_CONTROLLER), + FEA_MAP(PPT), + FEA_MAP(TDC), + FEA_MAP(THERMAL), + FEA_MAP(ULV), + FEA_MAP(VCN_DPM), + FEA_MAP_REVERSE(FCLK), + FEA_MAP_REVERSE(SOCCLK), + FEA_MAP(LCLK_DPM), + FEA_MAP(SHUBCLK_DPM), + FEA_MAP(DCFCLK_DPM), + FEA_MAP_HALF_REVERSE(GFX), + FEA_MAP(DS_GFXCLK), + FEA_MAP(DS_SOCCLK), + FEA_MAP(DS_LCLK), + FEA_MAP(DS_DCFCLK), + FEA_MAP(DS_FCLK), + FEA_MAP(DS_MP1CLK), + FEA_MAP(DS_MP0CLK), + FEA_MAP(GFX_DEM), + FEA_MAP(PSI), + FEA_MAP(PROCHOT), + FEA_MAP(CPUOFF), + FEA_MAP(STAPM), + FEA_MAP(S0I3), + FEA_MAP(PERF_LIMIT), + FEA_MAP(CORE_DLDO), + FEA_MAP(RSMU_LOW_POWER), + FEA_MAP(SMN_LOW_POWER), + FEA_MAP(THM_LOW_POWER), + FEA_MAP(SMUIO_LOW_POWER), + FEA_MAP(MP1_LOW_POWER), + FEA_MAP(DS_VCN), + FEA_MAP(CPPC), + FEA_MAP(DF_CSTATES), + FEA_MAP(MSMU_LOW_POWER), + FEA_MAP(ATHUB_PG), +}; + +static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = { + TAB_MAP_VALID(WATERMARKS), + TAB_MAP_VALID(SMU_METRICS), + TAB_MAP_VALID(CUSTOM_DPM), + TAB_MAP_VALID(DPMCLOCKS), +}; + +static struct cmn2asic_mapping yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), +}; + +static int yellow_carp_init_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + + SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); + if (!smu_table->clocks_table) + goto err0_out; + + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); + if (!smu_table->metrics_table) + goto err1_out; + smu_table->metrics_time = 0; + + smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); + if (!smu_table->watermarks_table) + goto err2_out; + + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); + smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); + if (!smu_table->gpu_metrics_table) + goto err3_out; + + return 0; + +err3_out: + kfree(smu_table->watermarks_table); +err2_out: + kfree(smu_table->metrics_table); +err1_out: + kfree(smu_table->clocks_table); +err0_out: + return -ENOMEM; +} + +static int yellow_carp_system_features_control(struct smu_context *smu, bool en) +{ + struct smu_feature *feature = &smu->smu_feature; + uint32_t feature_mask[2]; + int ret = 0; + + if (!en) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); + + bitmap_zero(feature->enabled, feature->feature_num); + bitmap_zero(feature->supported, feature->feature_num); + + if (!en) + return ret; + + ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); + if (ret) + return ret; + + bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, + feature->feature_num); + bitmap_copy(feature->supported, (unsigned long *)&feature_mask, + feature->feature_num); + + return 0; +} + +static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable) +{ + int ret = 0; + + /* vcn dpm on is a prerequisite for vcn power gate messages */ + if (enable) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, + 0, NULL); + else + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, + 0, NULL); + + return ret; +} + +static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) +{ + int ret = 0; + + if (enable) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, + 0, NULL); + else + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_PowerDownJpeg, 0, + NULL); + + return ret; +} + + +static bool yellow_carp_is_dpm_running(struct smu_context *smu) +{ + int ret = 0; + uint32_t feature_mask[2]; + uint64_t feature_enabled; + + ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); + + if (ret) + return false; + + feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; + + return !!(feature_enabled & SMC_DPM_FEATURE); +} + +static int yellow_carp_post_smu_init(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + /* allow message will be sent after enable message on Yellow Carp*/ + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); + if (ret) + dev_err(adev->dev, "Failed to Enable GfxOff!\n"); + return ret; +} + +static int yellow_carp_mode_reset(struct smu_context *smu, int type) +{ + int ret = 0, index = 0; + + index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, + SMU_MSG_GfxDeviceDriverReset); + if (index < 0) + return index == -EACCES ? 0 : index; + + mutex_lock(&smu->message_lock); + + ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); + + mutex_unlock(&smu->message_lock); + + mdelay(10); + + return ret; +} + +static int yellow_carp_mode2_reset(struct smu_context *smu) +{ + return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2); +} + +static int yellow_carp_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; + int ret = 0; + + mutex_lock(&smu->metrics_lock); + + ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); + if (ret) { + mutex_unlock(&smu->metrics_lock); + return ret; + } + + switch (member) { + case METRICS_AVERAGE_GFXCLK: + *value = metrics->GfxclkFrequency; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->SocclkFrequency; + break; + case METRICS_AVERAGE_VCLK: + *value = metrics->VclkFrequency; + break; + case METRICS_AVERAGE_DCLK: + *value = metrics->DclkFrequency; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->MemclkFrequency; + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = metrics->GfxActivity / 100; + break; + case METRICS_AVERAGE_VCNACTIVITY: + *value = metrics->UvdActivity; + break; + case METRICS_AVERAGE_SOCKETPOWER: + *value = (metrics->CurrentSocketPower << 8) / 1000; + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->GfxTemperature / 100 * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->SocTemperature / 100 * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_STATUS: + *value = metrics->ThrottlerStatus; + break; + case METRICS_VOLTAGE_VDDGFX: + *value = metrics->Voltage[0]; + break; + case METRICS_VOLTAGE_VDDSOC: + *value = metrics->Voltage[1]; + break; + case METRICS_SS_APU_SHARE: + /* return the percentage of APU power with respect to APU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if (metrics->StapmOpnLimit > 0) + *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; + else + *value = 0; + break; + case METRICS_SS_DGPU_SHARE: + /* return the percentage of dGPU power with respect to dGPU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if ((metrics->dGpuPower > 0) && + (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) + *value = (metrics->dGpuPower * 100) / + (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); + else + *value = 0; + break; + default: + *value = UINT_MAX; + break; + } + + mutex_unlock(&smu->metrics_lock); + + return ret; +} + +static int yellow_carp_read_sensor(struct smu_context *smu, + enum amd_pp_sensors sensor, + void *data, uint32_t *size) +{ + int ret = 0; + + if (!data || !size) + return -EINVAL; + + mutex_lock(&smu->sensor_lock); + switch (sensor) { + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXACTIVITY, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_POWER: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_AVERAGE_SOCKETPOWER, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_EDGE_TEMP: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_EDGE, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_HOTSPOT, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_AVERAGE_UCLK, + (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXCLK, + (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDGFX: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_VOLTAGE_VDDGFX, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDNB: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_VOLTAGE_VDDSOC, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_SS_APU_SHARE: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_SS_APU_SHARE, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: + ret = yellow_carp_get_smu_metrics_data(smu, + METRICS_SS_DGPU_SHARE, + (uint32_t *)data); + *size = 4; + break; + default: + ret = -EOPNOTSUPP; + break; + } + mutex_unlock(&smu->sensor_lock); + + return ret; +} + +static int yellow_carp_set_watermarks_table(struct smu_context *smu, + struct pp_smu_wm_range_sets *clock_ranges) +{ + int i; + int ret = 0; + Watermarks_t *table = smu->smu_table.watermarks_table; + + if (!table || !clock_ranges) + return -EINVAL; + + if (clock_ranges) { + if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || + clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) + return -EINVAL; + + for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { + table->WatermarkRow[WM_DCFCLK][i].MinClock = + clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MaxClock = + clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MinMclk = + clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MaxMclk = + clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; + + table->WatermarkRow[WM_DCFCLK][i].WmSetting = + clock_ranges->reader_wm_sets[i].wm_inst; + } + + for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { + table->WatermarkRow[WM_SOCCLK][i].MinClock = + clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MaxClock = + clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MinMclk = + clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MaxMclk = + clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; + + table->WatermarkRow[WM_SOCCLK][i].WmSetting = + clock_ranges->writer_wm_sets[i].wm_inst; + } + + smu->watermarks_bitmap |= WATERMARKS_EXIST; + } + + /* pass data to smu controller */ + if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && + !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { + ret = smu_cmn_write_watermarks_table(smu); + if (ret) { + dev_err(smu->adev->dev, "Failed to update WMTABLE!"); + return ret; + } + smu->watermarks_bitmap |= WATERMARKS_LOADED; + } + + return 0; +} + +static int yellow_carp_get_power_profile_mode(struct smu_context *smu, + char *buf) +{ + static const char *profile_name[] = { + "BOOTUP_DEFAULT", + "3D_FULL_SCREEN", + "POWER_SAVING", + "VIDEO", + "VR", + "COMPUTE", + "CUSTOM"}; + uint32_t i, size = 0; + int16_t workload_type = 0; + + if (!buf) + return -EINVAL; + + for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { + /* + * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT. + * Not all profile modes are supported on yellow carp. + */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + i); + + if (workload_type < 0) + continue; + + size += sprintf(buf + size, "%2d %14s%s\n", + i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); + } + + return size; +} + +static int yellow_carp_set_power_profile_mode(struct smu_context *smu, + long *input, uint32_t size) +{ + int workload_type, ret; + uint32_t profile_mode = input[size]; + + if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { + dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); + return -EINVAL; + } + + if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || + profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) + return 0; + + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + profile_mode); + if (workload_type < 0) { + dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on YELLOWCARP\n", + profile_mode); + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, + 1 << workload_type, + NULL); + if (ret) { + dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", + workload_type); + return ret; + } + + smu->power_profile_mode = profile_mode; + + return 0; +} + +static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct gpu_metrics_v2_1 *gpu_metrics = + (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + SmuMetrics_t metrics; + int ret = 0; + + ret = smu_cmn_get_metrics_table(smu, &metrics, true); + if (ret) + return ret; + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); + + gpu_metrics->temperature_gfx = metrics.GfxTemperature; + gpu_metrics->temperature_soc = metrics.SocTemperature; + memcpy(&gpu_metrics->temperature_core[0], + &metrics.CoreTemperature[0], + sizeof(uint16_t) * 8); + gpu_metrics->temperature_l3[0] = metrics.L3Temperature; + + gpu_metrics->average_gfx_activity = metrics.GfxActivity; + gpu_metrics->average_mm_activity = metrics.UvdActivity; + + gpu_metrics->average_socket_power = metrics.CurrentSocketPower; + gpu_metrics->average_gfx_power = metrics.Power[0]; + gpu_metrics->average_soc_power = metrics.Power[1]; + memcpy(&gpu_metrics->average_core_power[0], + &metrics.CorePower[0], + sizeof(uint16_t) * 8); + + gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; + gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; + gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; + gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; + gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; + + memcpy(&gpu_metrics->current_coreclk[0], + &metrics.CoreFrequency[0], + sizeof(uint16_t) * 8); + gpu_metrics->current_l3clk[0] = metrics.L3Frequency; + + gpu_metrics->throttle_status = metrics.ThrottlerStatus; + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + *table = (void *)gpu_metrics; + + return sizeof(struct gpu_metrics_v2_1); +} + +static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, + long input[], uint32_t size) +{ + struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + int ret = 0; + + /* Only allowed in manual mode */ + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_OD_EDIT_SCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } + + if (input[0] == 0) { + if (input[1] < smu->gfx_default_hard_min_freq) { + dev_warn(smu->adev->dev, + "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", + input[1], smu->gfx_default_hard_min_freq); + return -EINVAL; + } + smu->gfx_actual_hard_min_freq = input[1]; + } else if (input[0] == 1) { + if (input[1] > smu->gfx_default_soft_max_freq) { + dev_warn(smu->adev->dev, + "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", + input[1], smu->gfx_default_soft_max_freq); + return -EINVAL; + } + smu->gfx_actual_soft_max_freq = input[1]; + } else { + return -EINVAL; + } + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } else { + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; + } + break; + case PP_OD_COMMIT_DPM_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } else { + if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { + dev_err(smu->adev->dev, + "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", + smu->gfx_actual_hard_min_freq, + smu->gfx_actual_soft_max_freq); + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, + smu->gfx_actual_hard_min_freq, NULL); + if (ret) { + dev_err(smu->adev->dev, "Set hard min sclk failed!"); + return ret; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, + smu->gfx_actual_soft_max_freq, NULL); + if (ret) { + dev_err(smu->adev->dev, "Set soft max sclk failed!"); + return ret; + } + } + break; + default: + return -ENOSYS; + } + + return ret; +} + +static int yellow_carp_get_current_clk_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + MetricsMember_t member_type; + + switch (clk_type) { + case SMU_SOCCLK: + member_type = METRICS_AVERAGE_SOCCLK; + break; + case SMU_VCLK: + member_type = METRICS_AVERAGE_VCLK; + break; + case SMU_DCLK: + member_type = METRICS_AVERAGE_DCLK; + break; + case SMU_MCLK: + member_type = METRICS_AVERAGE_UCLK; + break; + case SMU_FCLK: + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetFclkFrequency, 0, value); + default: + return -EINVAL; + } + + return yellow_carp_get_smu_metrics_data(smu, member_type, value); +} + +static int yellow_carp_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *count) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + switch (clk_type) { + case SMU_SOCCLK: + *count = clk_table->NumSocClkLevelsEnabled; + break; + case SMU_VCLK: + *count = clk_table->VcnClkLevelsEnabled; + break; + case SMU_DCLK: + *count = clk_table->VcnClkLevelsEnabled; + break; + case SMU_MCLK: + *count = clk_table->NumDfPstatesEnabled; + break; + case SMU_FCLK: + *count = clk_table->NumDfPstatesEnabled; + break; + default: + break; + } + + return 0; +} + +static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t dpm_level, + uint32_t *freq) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + if (!clk_table || clk_type >= SMU_CLK_COUNT) + return -EINVAL; + + switch (clk_type) { + case SMU_SOCCLK: + if (dpm_level >= clk_table->NumSocClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->SocClocks[dpm_level]; + break; + case SMU_VCLK: + if (dpm_level >= clk_table->VcnClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->VClocks[dpm_level]; + break; + case SMU_DCLK: + if (dpm_level >= clk_table->VcnClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->DClocks[dpm_level]; + break; + case SMU_UCLK: + case SMU_MCLK: + if (dpm_level >= clk_table->NumDfPstatesEnabled) + return -EINVAL; + *freq = clk_table->DfPstateTable[dpm_level].MemClk; + break; + case SMU_FCLK: + if (dpm_level >= clk_table->NumDfPstatesEnabled) + return -EINVAL; + *freq = clk_table->DfPstateTable[dpm_level].FClk; + break; + default: + return -EINVAL; + } + + return 0; +} + +static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu, + enum smu_clk_type clk_type) +{ + enum smu_feature_mask feature_id = 0; + + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + case SMU_FCLK: + feature_id = SMU_FEATURE_DPM_FCLK_BIT; + break; + case SMU_GFXCLK: + case SMU_SCLK: + feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; + break; + case SMU_SOCCLK: + feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; + break; + case SMU_VCLK: + case SMU_DCLK: + feature_id = SMU_FEATURE_VCN_DPM_BIT; + break; + default: + return true; + } + + return smu_cmn_feature_is_enabled(smu, feature_id); +} + +static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min, + uint32_t *max) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + uint32_t clock_limit; + uint32_t max_dpm_level, min_dpm_level; + int ret = 0; + + if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + clock_limit = smu->smu_table.boot_values.uclk; + break; + case SMU_FCLK: + clock_limit = smu->smu_table.boot_values.fclk; + break; + case SMU_GFXCLK: + case SMU_SCLK: + clock_limit = smu->smu_table.boot_values.gfxclk; + break; + case SMU_SOCCLK: + clock_limit = smu->smu_table.boot_values.socclk; + break; + case SMU_VCLK: + clock_limit = smu->smu_table.boot_values.vclk; + break; + case SMU_DCLK: + clock_limit = smu->smu_table.boot_values.dclk; + break; + default: + clock_limit = 0; + break; + } + + /* clock in Mhz unit */ + if (min) + *min = clock_limit / 100; + if (max) + *max = clock_limit / 100; + + return 0; + } + + if (max) { + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + *max = clk_table->MaxGfxClk; + break; + case SMU_MCLK: + case SMU_UCLK: + case SMU_FCLK: + max_dpm_level = 0; + break; + case SMU_SOCCLK: + max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; + break; + case SMU_VCLK: + case SMU_DCLK: + max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; + break; + default: + ret = -EINVAL; + goto failed; + } + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { + ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max); + if (ret) + goto failed; + } + } + + if (min) { + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + *min = clk_table->MinGfxClk; + break; + case SMU_MCLK: + case SMU_UCLK: + case SMU_FCLK: + min_dpm_level = clk_table->NumDfPstatesEnabled - 1; + break; + case SMU_SOCCLK: + min_dpm_level = 0; + break; + case SMU_VCLK: + case SMU_DCLK: + min_dpm_level = 0; + break; + default: + ret = -EINVAL; + goto failed; + } + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { + ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min); + if (ret) + goto failed; + } + } + +failed: + return ret; +} + +static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + enum smu_message_type msg_set_min, msg_set_max; + int ret = 0; + + if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) + return -EINVAL; + + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + msg_set_min = SMU_MSG_SetHardMinGfxClk; + msg_set_max = SMU_MSG_SetSoftMaxGfxClk; + break; + case SMU_FCLK: + msg_set_min = SMU_MSG_SetHardMinFclkByFreq; + msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; + break; + case SMU_SOCCLK: + msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; + msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; + break; + case SMU_VCLK: + case SMU_DCLK: + msg_set_min = SMU_MSG_SetHardMinVcn; + msg_set_max = SMU_MSG_SetSoftMaxVcn; + break; + default: + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL); + if (ret) + goto out; + + ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL); + if (ret) + goto out; + +out: + return ret; +} + +static int yellow_carp_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) +{ + int i, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + + switch (clk_type) { + case SMU_OD_SCLK: + size = sprintf(buf, "%s:\n", "OD_SCLK"); + size += sprintf(buf + size, "0: %10uMhz\n", + (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); + size += sprintf(buf + size, "1: %10uMhz\n", + (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); + break; + case SMU_OD_RANGE: + size = sprintf(buf, "%s:\n", "OD_RANGE"); + size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", + smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); + break; + case SMU_SOCCLK: + case SMU_VCLK: + case SMU_DCLK: + case SMU_MCLK: + case SMU_FCLK: + ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value); + if (ret) + goto print_clk_out; + + ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count); + if (ret) + goto print_clk_out; + + for (i = 0; i < count; i++) { + ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) + goto print_clk_out; + + size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, + cur_value == value ? "*" : ""); + } + break; + default: + break; + } + +print_clk_out: + return size; +} + +static int yellow_carp_force_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, uint32_t mask) +{ + uint32_t soft_min_level = 0, soft_max_level = 0; + uint32_t min_freq = 0, max_freq = 0; + int ret = 0; + + soft_min_level = mask ? (ffs(mask) - 1) : 0; + soft_max_level = mask ? (fls(mask) - 1) : 0; + + switch (clk_type) { + case SMU_SOCCLK: + case SMU_FCLK: + case SMU_VCLK: + case SMU_DCLK: + ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); + if (ret) + goto force_level_out; + + ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); + if (ret) + goto force_level_out; + + ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); + if (ret) + goto force_level_out; + break; + default: + ret = -EINVAL; + break; + } + +force_level_out: + return ret; +} + +static int yellow_carp_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t sclk_min = 0, sclk_max = 0; + uint32_t fclk_min = 0, fclk_max = 0; + uint32_t socclk_min = 0, socclk_max = 0; + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); + sclk_min = sclk_max; + fclk_min = fclk_max; + socclk_min = socclk_max; + break; + case AMD_DPM_FORCED_LEVEL_LOW: + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); + sclk_max = sclk_min; + fclk_max = fclk_min; + socclk_max = socclk_min; + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + /* Temporarily do nothing since the optimal clocks haven't been provided yet */ + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: + return 0; + default: + dev_err(adev->dev, "Invalid performance level %d\n", level); + return -EINVAL; + } + + if (sclk_min && sclk_max) { + ret = yellow_carp_set_soft_freq_limited_range(smu, + SMU_SCLK, + sclk_min, + sclk_max); + if (ret) + return ret; + + smu->gfx_actual_hard_min_freq = sclk_min; + smu->gfx_actual_soft_max_freq = sclk_max; + } + + if (fclk_min && fclk_max) { + ret = yellow_carp_set_soft_freq_limited_range(smu, + SMU_FCLK, + fclk_min, + fclk_max); + if (ret) + return ret; + } + + if (socclk_min && socclk_max) { + ret = yellow_carp_set_soft_freq_limited_range(smu, + SMU_SOCCLK, + socclk_min, + socclk_max); + if (ret) + return ret; + } + + return ret; +} + +static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; + smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; + smu->gfx_actual_hard_min_freq = 0; + smu->gfx_actual_soft_max_freq = 0; + + return 0; +} + +static const struct pptable_funcs yellow_carp_ppt_funcs = { + .check_fw_status = smu_v13_0_1_check_fw_status, + .check_fw_version = smu_v13_0_1_check_fw_version, + .init_smc_tables = yellow_carp_init_smc_tables, + .fini_smc_tables = smu_v13_0_1_fini_smc_tables, + .get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values, + .system_features_control = yellow_carp_system_features_control, + .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, + .send_smc_msg = smu_cmn_send_smc_msg, + .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable, + .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable, + .set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables, + .read_sensor = yellow_carp_read_sensor, + .is_dpm_running = yellow_carp_is_dpm_running, + .set_watermarks_table = yellow_carp_set_watermarks_table, + .get_power_profile_mode = yellow_carp_get_power_profile_mode, + .set_power_profile_mode = yellow_carp_set_power_profile_mode, + .get_gpu_metrics = yellow_carp_get_gpu_metrics, + .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .set_driver_table_location = smu_v13_0_1_set_driver_table_location, + .gfx_off_control = smu_v13_0_1_gfx_off_control, + .post_init = yellow_carp_post_smu_init, + .mode2_reset = yellow_carp_mode2_reset, + .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq, + .od_edit_dpm_table = yellow_carp_od_edit_dpm_table, + .print_clk_levels = yellow_carp_print_clk_levels, + .force_clk_levels = yellow_carp_force_clk_levels, + .set_performance_level = yellow_carp_set_performance_level, + .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters, +}; + +void yellow_carp_set_ppt_funcs(struct smu_context *smu) +{ + smu->ppt_funcs = &yellow_carp_ppt_funcs; + smu->message_map = yellow_carp_message_map; + smu->feature_map = yellow_carp_feature_mask_map; + smu->table_map = yellow_carp_table_map; + smu->workload_map = yellow_carp_workload_map; + smu->is_apu = true; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h new file mode 100644 index 000000000000..b3ad8352c68a --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __YELLOW_CARP_PPT_H__ +#define __YELLOW_CARP_PPT_H__ + +extern void yellow_carp_set_ppt_funcs(struct smu_context *smu); + +#endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index dc7d2e71aa6f..e802f9a95f08 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -104,8 +104,8 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu, ret = smu_cmn_wait_for_response(smu); if (ret != 0x1) { - dev_err(adev->dev, "Msg issuing pre-check failed and " - "SMU may be not in the right state!\n"); + dev_err(adev->dev, "Msg issuing pre-check failed(0x%x) and " + "SMU may be not in the right state!\n", ret); if (ret != -ETIME) ret = -EIO; return ret; @@ -126,7 +126,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, struct amdgpu_device *adev = smu->adev; int ret = 0, index = 0; - if (smu->adev->in_pci_err_recovery) + if (smu->adev->no_hw_access) return 0; index = smu_cmn_to_asic_specific_index(smu, @@ -398,6 +398,19 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu, } +uint64_t smu_cmn_get_indep_throttler_status( + const unsigned long dep_status, + const uint8_t *throttler_map) +{ + uint64_t indep_status = 0; + uint8_t dep_bit = 0; + + for_each_set_bit(dep_bit, &dep_status, 32) + indep_status |= 1ULL << throttler_map[dep_bit]; + + return indep_status; +} + int smu_cmn_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled) @@ -575,23 +588,52 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, return ret; } +/** + * smu_cmn_disable_all_features_with_exception - disable all dpm features + * except this specified by + * @mask + * + * @smu: smu_context pointer + * @no_hw_disablement: whether real dpm disablement should be performed + * true: update the cache(about dpm enablement state) only + * false: real dpm disablement plus cache update + * @mask: the dpm feature which should not be disabled + * SMU_FEATURE_COUNT: no exception, all dpm features + * to disable + * + * Returns: + * 0 on success or a negative error code on failure. + */ int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, + bool no_hw_disablement, enum smu_feature_mask mask) { + struct smu_feature *feature = &smu->smu_feature; uint64_t features_to_disable = U64_MAX; int skipped_feature_id; - skipped_feature_id = smu_cmn_to_asic_specific_index(smu, - CMN2ASIC_MAPPING_FEATURE, - mask); - if (skipped_feature_id < 0) - return -EINVAL; + if (mask != SMU_FEATURE_COUNT) { + skipped_feature_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_FEATURE, + mask); + if (skipped_feature_id < 0) + return -EINVAL; - features_to_disable &= ~(1ULL << skipped_feature_id); + features_to_disable &= ~(1ULL << skipped_feature_id); + } - return smu_cmn_feature_update_enable_state(smu, - features_to_disable, - 0); + if (no_hw_disablement) { + mutex_lock(&feature->mutex); + bitmap_andnot(feature->enabled, feature->enabled, + (unsigned long *)(&features_to_disable), SMU_FEATURE_MAX); + mutex_unlock(&feature->mutex); + + return 0; + } else { + return smu_cmn_feature_update_enable_state(smu, + features_to_disable, + 0); + } } int smu_cmn_get_smc_version(struct smu_context *smu, @@ -761,12 +803,21 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) case METRICS_VERSION(1, 1): structure_size = sizeof(struct gpu_metrics_v1_1); break; + case METRICS_VERSION(1, 2): + structure_size = sizeof(struct gpu_metrics_v1_2); + break; + case METRICS_VERSION(1, 3): + structure_size = sizeof(struct gpu_metrics_v1_3); + break; case METRICS_VERSION(2, 0): structure_size = sizeof(struct gpu_metrics_v2_0); break; case METRICS_VERSION(2, 1): structure_size = sizeof(struct gpu_metrics_v2_1); break; + case METRICS_VERSION(2, 2): + structure_size = sizeof(struct gpu_metrics_v2_2); + break; default: return; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index da6ff6f024f9..9add5f16ff56 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -60,6 +60,10 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); +uint64_t smu_cmn_get_indep_throttler_status( + const unsigned long dep_status, + const uint8_t *throttler_map); + int smu_cmn_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled); @@ -75,6 +79,7 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, + bool no_hw_disablement, enum smu_feature_mask mask); int smu_cmn_get_smc_version(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 68d9464ababc..59f9cfff3d61 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -57,7 +57,7 @@ #define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu) #define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num) #define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask) -#define smu_disable_all_features_with_exception(smu, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, mask) +#define smu_disable_all_features_with_exception(smu, no_hw_disablement, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, no_hw_disablement, mask) #define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu) #define smu_notify_display_change(smu) smu_ppt_funcs(notify_display_change, 0, smu) #define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu) @@ -82,7 +82,7 @@ #define smu_i2c_fini(smu, control) smu_ppt_funcs(i2c_fini, 0, smu, control) #define smu_get_unique_id(smu) smu_ppt_funcs(get_unique_id, 0, smu) #define smu_log_thermal_throttling(smu) smu_ppt_funcs(log_thermal_throttling_event, 0, smu) -#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu) +#define smu_get_asic_power_limits(smu, current, default, max) smu_ppt_funcs(get_power_limit, 0, smu, current, default, max) #define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf) #define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask) #define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c index aeda4e5ec4f4..ff45f23f3d56 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c @@ -247,7 +247,6 @@ static void komeda_kms_mode_config_init(struct komeda_kms_dev *kms, config->min_height = 0; config->max_width = 4096; config->max_height = 4096; - config->allow_fb_modifiers = true; config->funcs = &komeda_mode_config_funcs; config->helper_private = &komeda_mode_config_helpers; diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index d83c7366b348..de59f3302516 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -403,7 +403,6 @@ static int malidp_init(struct drm_device *drm) drm->mode_config.max_height = hwdev->max_line_size; drm->mode_config.funcs = &malidp_mode_config_funcs; drm->mode_config.helper_private = &malidp_mode_config_helpers; - drm->mode_config.allow_fb_modifiers = true; ret = malidp_crtc_init(drm); if (ret) diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index ddbba67f0283..8c2ab3d653b7 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -927,6 +927,11 @@ static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { .atomic_disable = malidp_de_plane_disable, }; +static const uint64_t linear_only_modifiers[] = { + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + int malidp_de_planes_init(struct drm_device *drm) { struct malidp_drm *malidp = drm->dev_private; @@ -990,8 +995,8 @@ int malidp_de_planes_init(struct drm_device *drm) */ ret = drm_universal_plane_init(drm, &plane->base, crtcs, &malidp_de_plane_funcs, formats, n, - (id == DE_SMART) ? NULL : modifiers, plane_type, - NULL); + (id == DE_SMART) ? linear_only_modifiers : modifiers, + plane_type, NULL); if (ret < 0) goto cleanup; diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 44fe9f994fc5..dab0a1f0983b 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -94,9 +95,7 @@ static int armada_drm_bind(struct device *dev) } /* Remove early framebuffers */ - ret = drm_fb_helper_remove_conflicting_framebuffers(NULL, - "armada-drm-fb", - false); + ret = drm_aperture_remove_framebuffers(false, "armada-drm-fb"); if (ret) { dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n", __func__, ret); diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c index 88121c0e0d05..cd93c44f2662 100644 --- a/drivers/gpu/drm/ast/ast_dp501.c +++ b/drivers/gpu/drm/ast/ast_dp501.c @@ -189,6 +189,9 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size) u32 i, data; u32 boot_address; + if (ast->config_mode != ast_use_p2a) + return false; + data = ast_mindwm(ast, 0x1e6e2100) & 0x01; if (data) { boot_address = get_fw_base(ast); @@ -207,6 +210,9 @@ static bool ast_launch_m68k(struct drm_device *dev) u8 *fw_addr = NULL; u8 jreg; + if (ast->config_mode != ast_use_p2a) + return false; + data = ast_mindwm(ast, 0x1e6e2100) & 0x01; if (!data) { @@ -271,25 +277,55 @@ u8 ast_get_dp501_max_clk(struct drm_device *dev) struct ast_private *ast = to_ast_private(dev); u32 boot_address, offset, data; u8 linkcap[4], linkrate, linklanes, maxclk = 0xff; + u32 *plinkcap; - boot_address = get_fw_base(ast); + if (ast->config_mode == ast_use_p2a) { + boot_address = get_fw_base(ast); - /* validate FW version */ - offset = 0xf000; - data = ast_mindwm(ast, boot_address + offset); - if ((data & 0xf0) != 0x10) /* version: 1x */ - return maxclk; + /* validate FW version */ + offset = AST_DP501_GBL_VERSION; + data = ast_mindwm(ast, boot_address + offset); + if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) /* version: 1x */ + return maxclk; - /* Read Link Capability */ - offset = 0xf014; - *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset); - if (linkcap[2] == 0) { - linkrate = linkcap[0]; - linklanes = linkcap[1]; - data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes); - if (data > 0xff) - data = 0xff; - maxclk = (u8)data; + /* Read Link Capability */ + offset = AST_DP501_LINKRATE; + plinkcap = (u32 *)linkcap; + *plinkcap = ast_mindwm(ast, boot_address + offset); + if (linkcap[2] == 0) { + linkrate = linkcap[0]; + linklanes = linkcap[1]; + data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes); + if (data > 0xff) + data = 0xff; + maxclk = (u8)data; + } + } else { + if (!ast->dp501_fw_buf) + return AST_DP501_DEFAULT_DCLK; /* 1024x768 as default */ + + /* dummy read */ + offset = 0x0000; + data = readl(ast->dp501_fw_buf + offset); + + /* validate FW version */ + offset = AST_DP501_GBL_VERSION; + data = readl(ast->dp501_fw_buf + offset); + if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) /* version: 1x */ + return maxclk; + + /* Read Link Capability */ + offset = AST_DP501_LINKRATE; + plinkcap = (u32 *)linkcap; + *plinkcap = readl(ast->dp501_fw_buf + offset); + if (linkcap[2] == 0) { + linkrate = linkcap[0]; + linklanes = linkcap[1]; + data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes); + if (data > 0xff) + data = 0xff; + maxclk = (u8)data; + } } return maxclk; } @@ -298,26 +334,57 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata) { struct ast_private *ast = to_ast_private(dev); u32 i, boot_address, offset, data; + u32 *pEDIDidx; - boot_address = get_fw_base(ast); + if (ast->config_mode == ast_use_p2a) { + boot_address = get_fw_base(ast); - /* validate FW version */ - offset = 0xf000; - data = ast_mindwm(ast, boot_address + offset); - if ((data & 0xf0) != 0x10) - return false; + /* validate FW version */ + offset = AST_DP501_GBL_VERSION; + data = ast_mindwm(ast, boot_address + offset); + if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) + return false; - /* validate PnP Monitor */ - offset = 0xf010; - data = ast_mindwm(ast, boot_address + offset); - if (!(data & 0x01)) - return false; + /* validate PnP Monitor */ + offset = AST_DP501_PNPMONITOR; + data = ast_mindwm(ast, boot_address + offset); + if (!(data & AST_DP501_PNP_CONNECTED)) + return false; - /* Read EDID */ - offset = 0xf020; - for (i = 0; i < 128; i += 4) { - data = ast_mindwm(ast, boot_address + offset + i); - *(u32 *)(ediddata + i) = data; + /* Read EDID */ + offset = AST_DP501_EDID_DATA; + for (i = 0; i < 128; i += 4) { + data = ast_mindwm(ast, boot_address + offset + i); + pEDIDidx = (u32 *)(ediddata + i); + *pEDIDidx = data; + } + } else { + if (!ast->dp501_fw_buf) + return false; + + /* dummy read */ + offset = 0x0000; + data = readl(ast->dp501_fw_buf + offset); + + /* validate FW version */ + offset = AST_DP501_GBL_VERSION; + data = readl(ast->dp501_fw_buf + offset); + if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) + return false; + + /* validate PnP Monitor */ + offset = AST_DP501_PNPMONITOR; + data = readl(ast->dp501_fw_buf + offset); + if (!(data & AST_DP501_PNP_CONNECTED)) + return false; + + /* Read EDID */ + offset = AST_DP501_EDID_DATA; + for (i = 0; i < 128; i += 4) { + data = readl(ast->dp501_fw_buf + offset + i); + pEDIDidx = (u32 *)(ediddata + i); + *pEDIDidx = data; + } } return true; diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index 01837bea18c2..5aa452b4efe6 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -30,10 +30,10 @@ #include #include +#include #include #include #include -#include #include #include @@ -89,23 +89,18 @@ static const struct pci_device_id ast_pciidlist[] = { MODULE_DEVICE_TABLE(pci, ast_pciidlist); -static void ast_kick_out_firmware_fb(struct pci_dev *pdev) +static int ast_remove_conflicting_framebuffers(struct pci_dev *pdev) { - struct apertures_struct *ap; bool primary = false; + resource_size_t base, size; - ap = alloc_apertures(1); - if (!ap) - return; - - ap->ranges[0].base = pci_resource_start(pdev, 0); - ap->ranges[0].size = pci_resource_len(pdev, 0); - + base = pci_resource_start(pdev, 0); + size = pci_resource_len(pdev, 0); #ifdef CONFIG_X86 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; #endif - drm_fb_helper_remove_conflicting_framebuffers(ap, "astdrmfb", primary); - kfree(ap); + + return drm_aperture_remove_conflicting_framebuffers(base, size, primary, "astdrmfb"); } static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -114,7 +109,9 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct drm_device *dev; int ret; - ast_kick_out_firmware_fb(pdev); + ret = ast_remove_conflicting_framebuffers(pdev); + if (ret) + return ret; ret = pcim_enable_device(pdev); if (ret) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index e82ab8628770..911f9f414774 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -150,6 +150,7 @@ struct ast_private { void __iomem *regs; void __iomem *ioregs; + void __iomem *dp501_fw_buf; enum ast_chip chip; bool vga2_clone; @@ -325,6 +326,17 @@ int ast_mode_config_init(struct ast_private *ast); #define AST_MM_ALIGN_SHIFT 4 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) +#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) +#define AST_DP501_FW_VERSION_1 BIT(4) +#define AST_DP501_PNP_CONNECTED BIT(1) + +#define AST_DP501_DEFAULT_DCLK 65 + +#define AST_DP501_GBL_VERSION 0xf000 +#define AST_DP501_PNPMONITOR 0xf010 +#define AST_DP501_LINKRATE 0xf014 +#define AST_DP501_EDID_DATA 0xf020 + int ast_mm_init(struct ast_private *ast); /* ast post */ diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 0ac3c2039c4b..2aff2e6cf450 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -99,7 +99,7 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { /* Double check it's actually working */ data = ast_read32(ast, 0xf004); - if (data != 0xFFFFFFFF) { + if ((data != 0xFFFFFFFF) && (data != 0x00)) { /* P2A works, grab silicon revision */ ast->config_mode = ast_use_p2a; @@ -413,7 +413,7 @@ struct ast_private *ast_device_create(const struct drm_driver *drv, pci_set_drvdata(pdev, dev); - ast->regs = pci_iomap(pdev, 1, 0); + ast->regs = pcim_iomap(pdev, 1, 0); if (!ast->regs) return ERR_PTR(-EIO); @@ -429,7 +429,7 @@ struct ast_private *ast_device_create(const struct drm_driver *drv, /* "map" IO regs if the above hasn't done so already */ if (!ast->ioregs) { - ast->ioregs = pci_iomap(pdev, 2, 0); + ast->ioregs = pcim_iomap(pdev, 2, 0); if (!ast->ioregs) return ERR_PTR(-EIO); } @@ -450,6 +450,14 @@ struct ast_private *ast_device_create(const struct drm_driver *drv, if (ret) return ERR_PTR(ret); + /* map reserved buffer */ + ast->dp501_fw_buf = NULL; + if (dev->vram_mm->vram_size < pci_resource_len(pdev, 0)) { + ast->dp501_fw_buf = pci_iomap_range(pdev, 0, dev->vram_mm->vram_size, 0); + if (!ast->dp501_fw_buf) + drm_info(dev, "failed to map reserved buffer!\n"); + } + ret = ast_mode_config_init(ast); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/bochs/bochs.h b/drivers/gpu/drm/bochs/bochs.h index e5bd1d517a18..e9645c612aff 100644 --- a/drivers/gpu/drm/bochs/bochs.h +++ b/drivers/gpu/drm/bochs/bochs.h @@ -78,6 +78,7 @@ struct bochs_device { int bochs_hw_init(struct drm_device *dev); void bochs_hw_fini(struct drm_device *dev); +void bochs_hw_blank(struct bochs_device *bochs, bool blank); void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode); void bochs_hw_setformat(struct bochs_device *bochs, diff --git a/drivers/gpu/drm/bochs/bochs_drv.c b/drivers/gpu/drm/bochs/bochs_drv.c index b469624fe40d..c828cadbabff 100644 --- a/drivers/gpu/drm/bochs/bochs_drv.c +++ b/drivers/gpu/drm/bochs/bochs_drv.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -109,7 +110,7 @@ static int bochs_pci_probe(struct pci_dev *pdev, return -ENOMEM; } - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "bochsdrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "bochsdrmfb"); if (ret) return ret; diff --git a/drivers/gpu/drm/bochs/bochs_hw.c b/drivers/gpu/drm/bochs/bochs_hw.c index 2d7380a9890e..7d3426d8cc69 100644 --- a/drivers/gpu/drm/bochs/bochs_hw.c +++ b/drivers/gpu/drm/bochs/bochs_hw.c @@ -7,6 +7,7 @@ #include #include +#include